[coreboot] Fwd: SimNOW VGA int 1a
mylesgw at gmail.com
Thu Oct 16 22:00:42 CEST 2008
On Thu, Oct 16, 2008 at 1:56 PM, ron minnich <rminnich at gmail.com> wrote:
> I did not realize we had gone private. see below.
> Basically, vga bios tries to size a 16 meg register and at an
> intermediate point the vga hardware ends up decoding the top 16 mb of
> I welcome a fix. It's just not obvious to me.
But we could just say that VGA ROM init is a black hole, only call functions
defined there and hope it works. :)
> ---------- Forwarded message ----------
> From: ron minnich <rminnich at gmail.com>
> Date: Thu, Oct 16, 2008 at 12:15 PM
> Subject: Re: [coreboot] SimNOW VGA int 1a
> To: Marc Jones <marc.jones at amd.com>
> Cc: Myles Watson <mylesgw at gmail.com>, Jordan Crouse <jordan.crouse at amd.com
> On Thu, Oct 16, 2008 at 12:08 PM, Marc Jones <marc.jones at amd.com> wrote:
> > ron minnich wrote:
> >> well, hang on.
> >> I write ffffffff to BAR 10.
> >> Then what is left in BAR 10 is ff000000. That decodes to the top 16 MB
> >> of address space. At that point, all the memory goes bye bye.
> >> So do we really want the device enabled?
> >> Is this maybe a bug in the vga bios? This won't be an issue for code
> >> not running in the top 16 MB
> > Yes it goes away but nothing should access it then. Put the BAR back and
> > should be fine.
> but the EIP is accessing it then. We're running code at ffffxxxx.
> Here is the sequence:
> we're running at ffffxxxx. We write ffffffff at request of vgabios to
> the BAR 10. At that point vga is decoding ffxxxxxx.
> We can no longer fetch code from ffffxxxx. We go bye bye.
> Fix is to NOT compile the pcibios into stage0, or to also decode it into
> coreboot mailing list: coreboot at coreboot.org
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