[coreboot] V3 ram assignment

[Corey Osgood]

On Sun, Oct 19, 2008 at 1:18 PM, Corey Osgood <corey.osgood at gmail.com>wrote:

> Just a quick question, I'm using the geode as an example:
>
> static void geodelx_pci_domain_set_resources(struct device *dev)
> {
>     int idx;
>     struct device *mc_dev;
>     struct northbridge_amd_geodelx_domain_config *nb_dm =
>      (struct northbridge_amd_geodelx_domain_config
> *)dev->device_configuration;
>
>     printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
>
>     mc_dev = dev->link[0].children;
>     if (mc_dev) {
>         /* Report the memory regions. */
>         idx = 10;
>         /* 0 .. 640 KB */
>         ram_resource(dev, idx++, 0, 640);
>         /* 1 MB .. (Systop - 1 MB) (in KB) */
>         ram_resource(dev, idx++, 1024,
>                  (get_systop(nb_dm) / 1024) - 1024);
>     }
>
>     phase4_assign_resources(&dev->link[0]);
> }
>
> Does ram_resource() have to be part of the pci domain setup? I know that it
> usually is, but the memory controller registers on the cn700 are part of
> d0f3, could I do ram_resource with the rest of that device's init?
>

Actually, I've got a couple more "little" questions, because cs5536 and
amd8111 differ greatly:

* Which is the proper naming convention for dts, ide or ide.dts?
* Should all stage2 code be in one file, or seperate files? ie on big
vt8237.c, or ide.c, lpc.c, etc?

Thanks,
Corey
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