[coreboot] patch: unshare pci operations
stepan at coresystems.de
Thu Oct 23 09:19:31 CEST 2008
Carl-Daniel Hailfinger wrote:
> On 21.10.2008 16:07, ron minnich wrote:
>> On Tue, Oct 21, 2008 at 7:04 AM, Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>>> Yes, that's why I hope the bootblock below 1M idea works out.
>> it will.
> Great. I totally trust you there.
Don't put your valuable live to such a risk.
I don't think it makes sense to take the efforts to even try keep the
It was a nice idea back when I came up with it, but since then things
1) If we want to share from below 1M we can't just put the code into the
bootblock and assume it pops up in the FSEG.
Because quite early we have to put some part of BIOS emulation (be it
seabios or the stuff we use for option roms right now) in the FSEG at
the critical addresses that our bootblock would use, too.
We can't get around using that part of the FSEG for something else.
We _could_ put the shared code at another fixed address in the image.
This would basically defeat LAR.
So, in order to share, we could only share between stage 2 and later
stages. That makes the whole idea quite useless.
Or we could drop either LAR or BIOS emulation. Both is not an option.
All the best,
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info at coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
More information about the coreboot