[coreboot] K8 HT architecture

[Carl-Daniel Hailfinger]

On 24.10.2008 20:14, Marc Jones wrote:
> Carl-Daniel Hailfinger wrote:
>> Hi,
>>
>> I'm trying to understand how HT is modeled into PCI space so that I can
>> propose the "right" way to handle it in the dts.
>> Depending on whether I run lspci -t under coreboot or factory BIOS,
>> different topologies will be displayed. That means looking at lspci is
>> not going to tell me how the hardware really works.
>>
>> Given a standard setup with three HT links from the CPU, where do I find
>> which device?
>> Is PCI device 18.0 sort of a PCI bridge which has multiple PCI buses (HT
>> links) behind itself?
>
>>
>> Or is the hardware organized in a completely different way? I'm
>> especially curious about the MP scenario as depicted above. Where do the
>> PCI functions of 18.[0123] reside?
>>
>
> This is why you don't want to mix the ht links and the pci bus. The
> physical layout and the logical layout on pci are different. the lspci
> -t view is the correct view.

Except that it sometimes differs (at least in numbering) between
coreboot and factory BIOS, so I'm not sure which aspects of lspci -t are
immutable and which are arbitrary.

> That is how the devices are addressed. Several different physical
> layouts will get you the same logical layout because of how pci buses
> are scanned.

Interesting.

> this
> cpu --- pci
>  |
> cpu --- pci
>
> would be equivalent to this (although unlikely topology)
> cpu --- pci
>  | \--- pci
> cpu
>
> I think it would be a mistake to over complicate the dts with the
> physical connections.

Is the "pci" in your graphics above a bus or a device?