[coreboot] v3 HT

Myles Watson mylesgw at gmail.com
Mon Oct 27 15:48:04 CET 2008

I've been looking at v2 and v3 HT code.  It seems like the biggest problem
is that we changed the representation of the device tree and didn't change
the code.

I think it would be best to have the dts match an lspci as closely as
possible.  That means the code has to be a little smarter so that it can
fill in the missing information.

If we start with a dts which describes the Serengeti machine, we have:

	mainboard_vendor = "AMD";
	mainboard_name = "Serengeti";
	cpus { };
	apic at 0 {
	domain at 0 {
		pci0 at 18,0 {
			pci at 0,0 {
				pci at 1,0{
			pci at 1,0 {
			pci at 1,1 {
			pci at 1,0{
/config/("southbridge/amd/amd8132/pcix.dts");				};

		pci1 at 18,0 {
		pci2 at 18,0 {
		pci at 18,1 {};
		pci at 18,2 {};
		pci at 18,3 {};
		ioport at 2e {
			com1enable = "1";

It doesn't exactly match an lspci, because lspci doesn't care what link the
devices are on.  I think we have to keep that difference.

Then when the hypertransport enumeration code runs, the bridges appear to be
siblings of their children.  With v2 there was another layer of hierarchy so
that the children of link 0 would just be the 8132 and the 8111.

So the new code should:
1. Scan the list of children for bridges
2. Assign the devices bus numbers and attach them correctly

Does that mean that we need to create dynamic bus devices or structures to
hold that information?  Probably not.  We can just change pointer

I don't think we need to expand the dts to fix this, we just need to make
the code match the structure.


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