[coreboot] r956 - in coreboot-v3: . device mainboard/amd mainboard/amd/serengeti southbridge/amd/amd8111 southbridge/amd/amd8132

svn at coreboot.org svn at coreboot.org
Tue Oct 28 03:06:16 CET 2008


Author: myles
Date: 2008-10-28 03:06:15 +0100 (Tue, 28 Oct 2008)
New Revision: 956

Modified:
   coreboot-v3/Kconfig
   coreboot-v3/device/Makefile
   coreboot-v3/device/pcix_device.c
   coreboot-v3/mainboard/amd/Kconfig
   coreboot-v3/mainboard/amd/serengeti/defconfig
   coreboot-v3/mainboard/amd/serengeti/dts
   coreboot-v3/southbridge/amd/amd8111/amd8111.c
   coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
Log:
This fixes the 8132 so that it can be included in the build for serengeti.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/Kconfig	2008-10-28 02:06:15 UTC (rev 956)
@@ -102,6 +102,8 @@
 	boolean
 config SOUTHBRIDGE_NVIDIA_MCP55
 	boolean
+config SOUTHBRIDGE_AMD_AMD8132
+	boolean
 config SOUTHBRIDGE_AMD_AMD8111
 	boolean
 config SOUTHBRIDGE_AMD_SB600

Modified: coreboot-v3/device/Makefile
===================================================================
--- coreboot-v3/device/Makefile	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/device/Makefile	2008-10-28 02:06:15 UTC (rev 956)
@@ -33,5 +33,9 @@
 STAGE2_DEVICE_SRC += hypertransport.c
 endif
 
+# this is only needed for pcix devices
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
+STAGE2_DEVICE_SRC += pcix_device.c
+endif
 
 $(obj)/device/pci_device.o: $(src)/device/pci_device.c $(obj)/statictree.h

Modified: coreboot-v3/device/pcix_device.c
===================================================================
--- coreboot-v3/device/pcix_device.c	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/device/pcix_device.c	2008-10-28 02:06:15 UTC (rev 956)
@@ -120,9 +120,9 @@
 
 	/* Find the PCI-X capability. */
 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
-	sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
+	status = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
 
-	if (PCI_X_SSTATUS_MFREQ(sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
+	if (PCI_X_SSTATUS_MFREQ(status) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
 		max = do_pci_scan_bridge(dev, max, pci_scan_bus);
 	} else {
 		max = do_pci_scan_bridge(dev, max, pcix_scan_bus);
@@ -130,23 +130,23 @@
 
 	/* Print the PCI-X bus speed. */
 	printk(BIOS_DEBUG, "PCI-X: %02x: %s\n", dev->link[0].secondary,
-		     pcix_speed(sstatus));
+		     pcix_speed(status));
 
 	return max;
 }
 
 /** Default device operations for PCI-X bridges. */
-static const struct pci_operations pcix_bus_ops_pci = {
+struct pci_operations pcix_bus_ops_pci = {
 	.set_subsystem = 0,
 };
 
-const struct device_operations default_pcix_ops_bus = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init             = 0,
-	.scan_bus         = pcix_scan_bridge,
-	.enable           = 0,
-	.reset_bus        = pci_bus_reset,
-	.ops_pci          = &pcix_bus_ops_pci,
+struct device_operations default_pcix_ops_bus = {
+	.phase4_read_resources   = pci_bus_read_resources,
+	.phase4_set_resources    = pci_dev_set_resources,
+	.phase5_enable_resources = pci_bus_enable_resources,
+	.phase6_init             = 0,
+	.phase3_scan             = pcix_scan_bridge,
+	.phase3_chip_setup_dev   = 0,
+	.reset_bus               = pci_bus_reset,
+	.ops_pci                 = &pcix_bus_ops_pci,
 };

Modified: coreboot-v3/mainboard/amd/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/Kconfig	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/mainboard/amd/Kconfig	2008-10-28 02:06:15 UTC (rev 956)
@@ -66,6 +66,7 @@
 	select CPU_AMD_K8
 	select NORTHBRIDGE_AMD_K8
 	select SOUTHBRIDGE_AMD_AMD8111
+	select SOUTHBRIDGE_AMD_AMD8132
 	select SUPERIO_WINBOND_W83627HF
 	select IOAPIC
 	help

Modified: coreboot-v3/mainboard/amd/serengeti/defconfig
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/defconfig	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/mainboard/amd/serengeti/defconfig	2008-10-28 02:06:15 UTC (rev 956)
@@ -24,6 +24,7 @@
 # CONFIG_VENDOR_PCENGINES is not set
 CONFIG_MAINBOARD_DIR="amd/serengeti"
 # CONFIG_BOARD_AMD_DB800 is not set
+# CONFIG_BOARD_AMD_DBM690T is not set
 # CONFIG_BOARD_AMD_NORWICH is not set
 CONFIG_BOARD_AMD_SERENGETI=y
 # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
@@ -71,6 +72,7 @@
 # Console
 #
 CONFIG_CONSOLE=y
+# CONFIG_CONSOLE_PREPEND_LOG_LEVEL is not set
 CONFIG_CONSOLE_LOGLEVEL_8=y
 # CONFIG_CONSOLE_LOGLEVEL_7 is not set
 # CONFIG_CONSOLE_LOGLEVEL_6 is not set
@@ -94,7 +96,7 @@
 # Cosmetic console options
 #
 # CONFIG_CONSOLE_PREFIX is not set
-CONFIG_CONSOLE_BUFFER=y
+# CONFIG_CONSOLE_BUFFER is not set
 
 #
 # Devices
@@ -110,6 +112,7 @@
 CONFIG_HW_MEM_HOLE_SIZEK=0x1000
 CONFIG_NORTHBRIDGE_AMD_K8=y
 CONFIG_SOUTHBRIDGE_AMD_AMD8111=y
+CONFIG_SOUTHBRIDGE_AMD_AMD8132=y
 CONFIG_SUPERIO_WINBOND_W83627HF=y
 
 #

Modified: coreboot-v3/mainboard/amd/serengeti/dts
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/dts	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/mainboard/amd/serengeti/dts	2008-10-28 02:06:15 UTC (rev 956)
@@ -27,15 +27,10 @@
 	};
 	domain at 0 {
 		/config/("northbridge/amd/k8/domain");
-		pci at 1,0{
-		};
 		pci0 at 18,0 {
 			/config/("northbridge/amd/k8/pci");
 			pci at 0,0 {
 				/config/("southbridge/amd/amd8111/pci.dts");
-				pci at 1,0{
-					/config/("southbridge/amd/amd8111/nic.dts");
-				};
 				pci at 0,0{
 					/config/("southbridge/amd/amd8111/usb.dts");
 				};
@@ -44,28 +39,34 @@
 				};
 				pci at 0,2{
 					/config/("southbridge/amd/amd8111/usb2.dts");
+					disable;
 				};
-				pci at 4,0{
+				pci at 1,0{
+					/config/("southbridge/amd/amd8111/nic.dts");
+					disable;
 				};
 			};
-			pci at 7,0 {
+			pci at 1,0 {
 				/config/("southbridge/amd/amd8111/lpc.dts");
 			};
-			pci at 7,1 {
+			pci at 1,1 {
 				/config/("southbridge/amd/amd8111/ide.dts");
 			};
-			pci at 7,2 {
+			pci at 1,2 {
 				/config/("southbridge/amd/amd8111/smbus.dts");
 			};
-			pci at 7,3 {
+			pci at 1,3 {
 				/config/("southbridge/amd/amd8111/acpi.dts");
 			};
-			pci at 7,5 {
+			pci at 1,5 {
 				/config/("southbridge/amd/amd8111/ac97audio.dts");
 			};
-			pci at 7,6 {
+			pci at 1,6 {
 				/config/("southbridge/amd/amd8111/ac97modem.dts");
 			};
+			pci at 2,0 {
+				/config/("southbridge/amd/amd8132/pcix.dts");
+			};
 		};
 		pci1 at 18,0 {
 			/config/("northbridge/amd/k8/pci");

Modified: coreboot-v3/southbridge/amd/amd8111/amd8111.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/amd8111.c	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/southbridge/amd/amd8111/amd8111.c	2008-10-28 02:06:15 UTC (rev 956)
@@ -34,19 +34,19 @@
 
 void amd8111_enable(struct device * dev)
 {
-	struct device * lpc_dev;
+	struct device * sub_dev;
 	struct device * bus_dev;
 	unsigned index;
 	unsigned reg_old, reg;
 
 	/* See if we are behind the amd8111 pci bridge */
 	bus_dev = dev->bus->dev;
-	if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) && 
-	    (bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI)) 
+	if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) &&
+	    (bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI))
 	{
 		unsigned devfn;
 		devfn = bus_dev->path.pci.devfn + (1 << 3);
-		lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
+		sub_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
 		index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
 		if (dev->path.pci.devfn == 2) { /* EHCI */
 			index = 16;
@@ -54,40 +54,40 @@
 	} else {
 		unsigned devfn;
 		devfn = (dev->path.pci.devfn) & ~7;
-		lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
+		sub_dev = dev_find_slot(dev->bus->secondary, devfn);
 		index = dev->path.pci.devfn & 7;
 	}
-	if ((!lpc_dev) || (index >= 17)) {
+	if ((!sub_dev) || (index >= 17)) {
 		return;
 	}
-	if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) ||
-	    (lpc_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA)) 
+	if ((sub_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) ||
+	    (sub_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA))
 	{
 		u32 id;
-		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
+		id = pci_read_config32(sub_dev, PCI_VENDOR_ID);
 		if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) {
 			return;
 		}
 	}
 
 	if (index < 16) {
-		reg = reg_old = pci_read_config16(lpc_dev, 0x48);
+		reg = reg_old = pci_read_config16(sub_dev, 0x48);
 		reg &= ~(1 << index);
 		if (dev->enabled) {
 			reg |= (1 << index);
 		}
 		if (reg != reg_old) {
-			pci_write_config16(lpc_dev, 0x48, reg);
+			pci_write_config16(sub_dev, 0x48, reg);
 		}
 	}
 	else if (index == 16) {
-		reg = reg_old = pci_read_config8(lpc_dev, 0x47);
+		reg = reg_old = pci_read_config8(sub_dev, 0x47);
 		reg &= ~(1 << 7);
 		if (!dev->enabled) {
 			reg |= (1 << 7);
 		}
 		if (reg != reg_old) {
-			pci_write_config8(lpc_dev, 0x47, reg);
+			pci_write_config8(sub_dev, 0x47, reg);
 		}
 	}
 }

Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c	2008-10-27 23:16:17 UTC (rev 955)
+++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c	2008-10-28 02:06:15 UTC (rev 956)
@@ -22,6 +22,7 @@
 #include <lib.h>
 #include <console.h>
 #include <device/pci.h>
+#include <device/pcix.h>
 #include <msr.h>
 #include <legacy.h>
 #include <device/pci_ids.h>
@@ -425,9 +426,9 @@
 			 .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable	 = ioapic_enable,
+	.phase3_chip_setup_dev	 = ioapic_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase6_init		 = amd8132_ioapic_init,
-	.ops_pci		 = &pci_dev_ops_pci,
+	.ops_pci		 = &pci_ops_pci_dev,
 };





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