[coreboot] K8 HT architecture

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Tue Oct 28 03:11:16 CET 2008

On 28.10.2008 00:49, Tom Sylla wrote:
> On Fri, Oct 24, 2008 at 8:24 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> Would you mind posting lspci -tvnn for that 5-processor board as well?
>> It would help me a lot to understand this issue better.
> Here they are, if you are still interested. There is a 5-node, and
> 8-node, and a 2-node with an nc device attached. This system is
> Barcelona, so you will see more devices for each Opteron.

Thanks a lot!
These dumps are extremely helpful in understanding the desired dts
structure better. My mail to Marc from a few minutes ago already
partially incorporates the new knowledge.



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