From svn at coreboot.org  Mon Sep  1 00:10:35 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Sep 2008 00:10:35 +0200
Subject: [coreboot] r3555 - in trunk/payloads/libpayload: i386 include libc
Message-ID: <mailman.2012.1355071372.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-09-01 00:10:35 +0200 (Mon, 01 Sep 2008)
New Revision: 3555

Modified:
   trunk/payloads/libpayload/i386/timer.c
   trunk/payloads/libpayload/include/libpayload.h
   trunk/payloads/libpayload/libc/readline.c
   trunk/payloads/libpayload/libc/time.c
Log:
Various Doxygen-related fixes in libpayload (trivial).
 
 - Drop all '@brief's, they're not needed as we use JAVADOC_AUTOBRIEF.
   The first sentence of every description will be treated as the '@brief'
   automatically.
 
 - Also, put all documentation/descriptions on top of the Doxygen-comments,
   and put the '@foo' keywords at the bottom of the comments for consistency.
 
 - Change comments for SEEK_SET/SEEK_CUR/SEEK_END from '/**@def' to '/**<'
   in order to make them appear in the output.
 
 - Drop all explicit '@struct' lines (which are optional; Doxygen will figure
   out that it's a struct if the comment is right before the struct).
 
 - Fix various typos, whitespace issues, etc.
 
 - Fix incorrect @param variable names, e.g. change '@param n foobar' to
   '@param s foobar' if the variable is named 's'.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/payloads/libpayload/i386/timer.c
===================================================================
--- trunk/payloads/libpayload/i386/timer.c	2008-08-29 09:06:16 UTC (rev 3554)
+++ trunk/payloads/libpayload/i386/timer.c	2008-08-31 22:10:35 UTC (rev 3555)
@@ -27,8 +27,9 @@
  * SUCH DAMAGE.
  */
 
-/** @file i386/timer.c
- * @brief i386 specific timer routines
+/**
+ * @file i386/timer.c
+ * i386 specific timer routines
  */
 
 #include <libpayload.h>
@@ -36,7 +37,7 @@
 
 /**
  * @ingroup arch
- * Global variable containing the speed of the processor in KHz
+ * Global variable containing the speed of the processor in KHz.
  */
 u32 cpu_khz;
 
@@ -81,8 +82,9 @@
 }
 
 /**
- * Delay for a specified number of nanoseconds
- * @param n Number of nanoseconds to delay for
+ * Delay for a specified number of nanoseconds.
+ *
+ * @param n Number of nanoseconds to delay for.
  */
 void ndelay(unsigned int n)
 {
@@ -90,8 +92,9 @@
 }
 
 /**
- * Delay for a specified number of microseconds
- * @param n Number of microseconds to delay for
+ * Delay for a specified number of microseconds.
+ *
+ * @param n Number of microseconds to delay for.
  */
 void udelay(unsigned int n)
 {
@@ -99,20 +102,20 @@
 }
 
 /**
- * Delay for a specified number of milliseconds
- * @param n Number of milliseconds to delay for
+ * Delay for a specified number of milliseconds.
+ *
+ * @param m Number of milliseconds to delay for.
  */
-
 void mdelay(unsigned int m)
 {
 	_delay(m * cpu_khz);
 }
 
 /**
- * Delay for a specified number of seconds
- * @param n Number of seconds to delay for
+ * Delay for a specified number of seconds.
+ *
+ * @param s Number of seconds to delay for.
  */
-
 void delay(unsigned int s)
 {
 	_delay(s * cpu_khz * 1000);

Modified: trunk/payloads/libpayload/include/libpayload.h
===================================================================
--- trunk/payloads/libpayload/include/libpayload.h	2008-08-29 09:06:16 UTC (rev 3554)
+++ trunk/payloads/libpayload/include/libpayload.h	2008-08-31 22:10:35 UTC (rev 3555)
@@ -27,7 +27,9 @@
  * SUCH DAMAGE.
  */
 
-/** @mainpage
+/**
+ * @mainpage
+ *
  * @section intro Introduction
  * libpayload is a small BSD-licensed static library (a lightweight
  * implementation of common and useful functions) intended to be used
@@ -36,10 +38,8 @@
  * @section example Example
  * Here is an example of a very simple payload:
  * @include sample/hello.c
- *
  */
 
-
 #ifndef _LIBPAYLOAD_H
 #define _LIBPAYLOAD_H
 
@@ -64,12 +64,12 @@
 
 #define RAND_MAX 0x7fffffff
 
-/* Payload information parameters - these are used to pass information
- * to the entity loading the payload
- * Usage:  PAYLOAD_INFO(key, value)
- * Example:  PAYLOAD_INFO(name, "CoreInfo!")
+/*
+ * Payload information parameters - these are used to pass information
+ * to the entity loading the payload.
+ * Usage:   PAYLOAD_INFO(key, value)
+ * Example: PAYLOAD_INFO(name, "CoreInfo!")
  */
-
 #define _pstruct(key) __pinfo_ ##key
 #define PAYLOAD_INFO(key, value)                                        \
 static const char _pstruct(key)[]                                        \
@@ -90,9 +90,7 @@
 #define NVRAM_RTC_FREQ_SELECT    10     /**< RTC Update Status Register */
 #define  NVRAM_RTC_UIP           0x80
 
-/** @struct tm
- *  \brief Broken down time structure
- */
+/** Broken down time structure */
 struct tm {
 	int tm_sec;   /**< Number of seconds after the minute */
 	int tm_min;   /**< Number of minutes after the hour */
@@ -136,7 +134,6 @@
 void serial_putchar(unsigned char c);
 int serial_havechar(void);
 int serial_getchar(void);
-
 void serial_clear(void);
 void serial_start_bold(void);
 void serial_end_bold(void);
@@ -189,7 +186,7 @@
 /** @} */
 
 /**
- * @defgroup ctype Character Type Functions
+ * @defgroup ctype Character type functions
  * @{
  */
 int isalnum(int c);
@@ -210,14 +207,14 @@
 /** @} */
 
 /**
- * @defgroup ipchecksum IP Checksum Functions
+ * @defgroup ipchecksum IP checksum functions
  * @{
  */
 unsigned short ipchksum(const void *ptr, unsigned long nbytes);
 /** @} */
 
 /**
- * @defgroup malloc Memory Allocation Functions
+ * @defgroup malloc Memory allocation functions
  * @{
  */
 void free(void *ptr);
@@ -227,14 +224,14 @@
 /** @} */
 
 /**
- * @defgroup exec Execution Functions
+ * @defgroup exec Execution functions
  * @{
  */
 int exec(long addr, int argc, char **argv);
 /** @} */
 
 /**
- * @defgroup misc Misc Functions
+ * @defgroup misc Misc functions
  * @{
  */
 int bcd2dec(int b);
@@ -244,11 +241,11 @@
 long long int llabs(long long int j);
 u8 bin2hex(u8 b);
 u8 hex2bin(u8 h);
-void fatal(const char* msg) __attribute__ ((noreturn));
+void fatal(const char *msg) __attribute__ ((noreturn));
 /** @} */
 
 /**
- * @defgroup memory Memory Manipulation Functions
+ * @defgroup memory Memory manipulation functions
  * @{
  */
 void *memset(void *s, int c, size_t n);
@@ -258,7 +255,7 @@
 /** @} */
 
 /**
- * @defgroup printf Print Functions
+ * @defgroup printf Print functions
  * @{
  */
 int snprintf(char *str, size_t size, const char *fmt, ...);
@@ -270,7 +267,7 @@
 /** @} */
 
 /**
- * @defgroup rand Random Number Generator Functions
+ * @defgroup rand Random number generator functions
  * @{
  */
 int rand_r(unsigned int *seed);
@@ -279,7 +276,7 @@
 /** @} */
 
 /**
- * @defgroup hash Hashing Functions
+ * @defgroup hash Hashing functions
  * @{
  */
 #define SHA1_BLOCK_LENGTH	64
@@ -297,7 +294,7 @@
 /** @} */
 
 /**
- * @defgroup string String Functions
+ * @defgroup string String functions
  * @{
  */
 size_t strnlen(const char *str, size_t maxlen);
@@ -313,14 +310,11 @@
 /** @} */
 
 /**
- * @defgroup time Time Functions
+ * @defgroup time Time functions
  * @{
  */
 
-/** @struct timeval
- * @brief System time structure
- */
-
+/** System time structure */
 struct timeval {
 	time_t tv_sec;       /**< Seconds */
 	suseconds_t tv_usec; /**< Microseconds */
@@ -330,15 +324,13 @@
 /** @} */
 
 /**
- * @defgroup lar LAR Functions
+ * @defgroup lar LAR functions
  * @{
  */
 
-/** @struct LAR
- * @brief LAR File Header
- */
+/** LAR file header */
 struct LAR {
-	void * start;   /**< Location of the LAR in memory */
+	void *start;    /**< Location of the LAR in memory */
 	int cindex;     /**< Next file to return in readlar() */
 	int count;      /**< Number of entries in the header cache */
 	int alloc;      /**< Number of slots in the header cache */
@@ -346,16 +338,12 @@
 	void **headers; /**< Pointer to the header cache */
 };
 
-/** @struct larent
- * @brief A structure representing the next LAR entry
- */
+/** A structure representing the next LAR entry */
 struct larent {
 	u8 name[LAR_MAX_PATHLEN]; /**< The name of the next LAR entry */
 };
 
-/** @struct larstat
- * @brief A structure containing information about a LAR file
- */
+/** A structure containing information about a LAR file */
 struct larstat {
 	u32 len;           /**< Length of the file in the LAR */
 	u32 reallen;       /**< Length of the uncompressed file */
@@ -367,10 +355,7 @@
 	u64 loadaddress;   /**< Address in memory to put the uncompressed file */
 };
 
-/** @struct LFILE
- * @brief A structure representing a LAR file
- */
-
+/** A structure representing a LAR file */
 struct LFILE {
 	struct LAR *lar;           /**< Pointer to the LAR struct */
 	struct lar_header *header; /**< Pointer to the header struct */
@@ -386,20 +371,20 @@
 int larstat(struct LAR *lar, const char *path, struct larstat *buf);
 void *larfptr(struct LAR *lar, const char *filename);
 int lfverify(struct LAR *lar, const char *filename);
-struct LFILE * lfopen(struct LAR *lar, const char *filename);
+struct LFILE *lfopen(struct LAR *lar, const char *filename);
 int lfread(void *ptr, size_t size, size_t nmemb, struct LFILE *stream);
 
-#define SEEK_SET 0 /**@def The seek offset is absolute  */
-#define SEEK_CUR 1 /**@def The seek offset is against the current position */
-#define SEEK_END 2 /**@def The see offset is against the end of the file */
+#define SEEK_SET 0 /**< The seek offset is absolute. */
+#define SEEK_CUR 1 /**< The seek offset is against the current position. */
+#define SEEK_END 2 /**< The seek offset is against the end of the file. */
 
 int lfseek(struct LFILE *stream, long offset, int whence);
 int lfclose(struct LFILE *file);
 /** @} */
 
 /**
- * @defgroup arch Architecture Specific Functions
- * This modules contains global architecture specific functions.
+ * @defgroup arch Architecture specific functions
+ * This module contains global architecture specific functions.
  * All architectures are expected to define these functions.
  * @{
  */
@@ -417,20 +402,18 @@
 #define abort() halt()    /**< Alias for the halt() function */
 
 /**
- * Stops executions and halts the processor.  This function does
- * not return.
+ * Stop execution and halt the processor (this function does not return).
  */
 void halt(void) __attribute__ ((noreturn));
 /** @} */
 
 /**
- * @defgroup readline Readline Functions
- * This interface provides a simple implementation of the standard
- * readline and getline functions.  They are suitable for reading a
- * line of input from the console.
+ * @defgroup readline Readline functions
+ * This interface provides a simple implementation of the standard readline()
+ * and getline() functions. They read a line of input from the console.
  * @{
  */
-char * readline(const char * prompt);
+char *readline(const char *prompt);
 int getline(char *buffer, int len);
 /** @} */
 

Modified: trunk/payloads/libpayload/libc/readline.c
===================================================================
--- trunk/payloads/libpayload/libc/readline.c	2008-08-29 09:06:16 UTC (rev 3554)
+++ trunk/payloads/libpayload/libc/readline.c	2008-08-31 22:10:35 UTC (rev 3555)
@@ -27,27 +27,27 @@
  * SUCH DAMAGE.
  */
 
-/** @file libc/readline.c
- * @brief Simple readline implementation
+/**
+ * @file libc/readline.c
+ * Simple readline implementation
  */
 
 #include <libpayload.h>
 
-static char * readline_buffer;
+static char *readline_buffer;
 static int readline_bufferlen;
 
 /**
- * @brief Read a line from the terminal and return it
- * @param prompt A prompt to display on the line
- * @return A pointer to the input string
+ * Read a line from the terminal and return it.
  *
- * Read a line from the terminal and return it.  This readline implementation
- * is rather simple, but it does more than the original readline() because
- * it allows us to have a pre-filled buffer. To pre-fill the buffer, use the
- * getline() function.
+ * This readline implementation is rather simple, but it does more than the
+ * original readline() because it allows us to have a pre-filled buffer.
+ * To pre-fill the buffer, use the getline() function.
+ *
+ * @param prompt A prompt to display on the line.
+ * @return A pointer to the input string.
  */
-
-char * readline(const char * prompt)
+char *readline(const char *prompt)
 {
 	char *buffer;
 	int current, ch, nonspace_seen;
@@ -141,7 +141,6 @@
 		}
 	}
 
-
 out:
 	if (current >= readline_bufferlen)
 		current = readline_bufferlen - 1;
@@ -151,22 +150,23 @@
 }
 
 /**
- * @brief Read a line from the input and store it in a buffer
- * @param prompt A buffer to store the line in
- * @param len Length of the buffer
- * @return The final length of the string
- * This function allows the user to pass a predefined buffer to
- * readline().  The buffer may be filled with a default value
- * which will be displayed by readline and can be edited as normal.
- * The final input string returned by readline will be returned in
+ * Read a line from the input and store it in a buffer.
+ *
+ * This function allows the user to pass a predefined buffer to readline().
+ * The buffer may be filled with a default value which will be displayed by
+ * readline() and can be edited as normal.
+ * The final input string returned by readline() will be returned in
  * the buffer and the function will return the length of the string.
+ *
+ * @param buffer Pointer to a buffer to store the line in.
+ * @param len Length of the buffer.
+ * @return The final length of the string.
  */
-
 int getline(char *buffer, int len)
 {
 	readline_buffer = buffer;
 	readline_bufferlen = len;
 	readline(NULL);
+
 	return strlen(buffer);
 }
-

Modified: trunk/payloads/libpayload/libc/time.c
===================================================================
--- trunk/payloads/libpayload/libc/time.c	2008-08-29 09:06:16 UTC (rev 3554)
+++ trunk/payloads/libpayload/libc/time.c	2008-08-31 22:10:35 UTC (rev 3555)
@@ -27,8 +27,9 @@
  * SUCH DAMAGE.
  */
 
-/** @file libc/time.c
- * @brief General Time Functions
+/**
+ * @file libc/time.c
+ * General time functions
  */
 
 #include <config.h>
@@ -115,18 +116,18 @@
 #endif
 
 /**
- * Return the current time broken into a timeval structure
- * @param tv A pointer to a timeval structure
- * @param tz Added for compatability - not used
- * @return 0 for success
+ * Return the current time broken into a timeval structure.
+ *
+ * @param tv A pointer to a timeval structure.
+ * @param tz Added for compatability - not used.
+ * @return 0 for success (this function cannot return non-zero currently).
  */
 int gettimeofday(struct timeval *tv, void *tz)
 {
-	/* Call the gtod init when we need it - this keeps
-	   the code from being included in the binary if we don't
-	   need it
-	*/
-
+	/*
+	 * Call the gtod init when we need it - this keeps the code from
+	 * being included in the binary if we don't need it.
+	 */
 	if (!clock.ticks)
 		gettimeofday_init();
 




From c-d.hailfinger.devel.2006 at gmx.net  Mon Sep  1 01:45:43 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 01 Sep 2008 01:45:43 +0200
Subject: [coreboot] k8 and memory training
In-Reply-To: <13426df10808302346j4290708fr95acfc1144f74a44@mail.gmail.com>
References: <13426df10808302346j4290708fr95acfc1144f74a44@mail.gmail.com>
Message-ID: <48BB2D27.2030405@gmx.net>

On 31.08.2008 08:46, ron minnich wrote:
> see http://coreboot.pastebin.com/m354e6401
>
> I can't really tell if it's working.
>   

I looked at the log and we're clearly doing something wrong odd. The
execution order simply does not make that much sense.

arch/x86/stage1.c:stage1_main()
{
  //stuff
  global_vars_init();
  hardware_stage1();
  uart_init();  // initialize serial port
  /* Exactly from now on we can use printk to the serial port.
   * Celebrate this by printing a LB banner.
   */
  console_init();
  //more stuff
}

mainboard/amd/serengeti/stage1.c:hardware_stage1()
{
  printk(BIOS_ERR, "Stage1: enable rom ...\n");
  max = ARRAY_SIZE(register_values);
  setup_resource_map(register_values, max);
  enumerate_ht_chain();
  amd8111_enable_rom();
  printk(BIOS_ERR, "Done.\n");
  w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
  post_code(POST_START_OF_MAIN);
}

Does it only look odd to me that we set up and initialize the serial
port only after we already have printed lots of stuff which may never
see the light of the day?
Three possible solutions:
1. Use the printk buffer to buffer messages until serial is fully set up.
2. Check a global variable which holds the status of serial and start
using serial only after it has been set up completely. (We may need that
anyway.)
3. Introduce hardware_early_stage1 which only sets up the console and
anything needed by the console.

My personal favourite is solution 3, with the additional option of
solution 2 in case some serial chips are sensitive to usage before
initialization.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From bari at onelabs.com  Mon Sep  1 01:59:07 2008
From: bari at onelabs.com (bari)
Date: Sun, 31 Aug 2008 18:59:07 -0500
Subject: [coreboot] Epia-CN Patch
Message-ID: <48BB304B.2020502@onelabs.com>

This patch gets the Epia-CN working without ACPI or APIC.

All devices work, no irq storms. Enjoy.

Signed-off-by: Bari Ari <bari at onelabs.com>

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From svn at coreboot.org  Mon Sep  1 03:48:08 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Sep 2008 03:48:08 +0200
Subject: [coreboot] r3556 - in trunk/coreboot-v2: src/mainboard/via/epia-cn
	src/northbridge/via/cn700 src/southbridge/via/vt8237r
	targets/via/epia-cn
Message-ID: <mailman.2013.1355071372.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-09-01 03:48:07 +0200 (Mon, 01 Sep 2008)
New Revision: 3556

Modified:
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c
   trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c
   trunk/coreboot-v2/src/northbridge/via/cn700/vga.c
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
   trunk/coreboot-v2/targets/via/epia-cn/Config.lb
Log:
This patch gets the Epia-CN working without ACPI or APIC.

All devices work, no irq storms. Enjoy.

Signed-off-by: Bari Ari <bari at onelabs.com>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb	2008-09-01 01:48:07 UTC (rev 3556)
@@ -98,12 +98,14 @@
       register "ide0_80pin_cable" = "0"
       register "ide1_80pin_cable" = "0"
       device pci f.0 on end			# IDE
-      register "fn_ctrl_lo" = "0x8a"
-      register "fn_ctrl_hi" = "0x9d"
-      device pci 10.0 on end			# USB 1.1
-      device pci 10.1 on end			# USB 1.1
-      device pci 10.2 on end			# USB 1.1
-      device pci 10.3 on end			# USB 1.1
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci 10.0 on end			# OHCI
+      device pci 10.1 on end			# OHCI
+      device pci 10.2 on end			# OHCI
+      device pci 10.3 on end			# OHCI
+      device pci 10.4 on end			# EHCI
+      device pci 10.5 on end			# UDCI
       device pci 11.0 on			# Southbridge LPC
         chip superio/via/vt1211			# Super I/O
           device pnp 2e.0 off			# Floppy

Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2008-09-01 01:48:07 UTC (rev 3556)
@@ -94,7 +94,7 @@
 default _RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
 default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
+default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
 default HOSTCC = "gcc"
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c	2008-09-01 01:48:07 UTC (rev 3556)
@@ -55,34 +55,27 @@
 {
 	device_t dev;
 	u8 reg;
+ 
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+	if (dev == PCI_DEV_INVALID)
+		die("Southbridge not found!!!\n");
 
-	/*
-	 * If I enable SATA, FILO will not find the IDE disk, so I'll disable
-	 * SATA here. To not conflict with PCI spec, I'll move IDE device
-	 * from 00:0f.1 to 00:0f.0.
+	/* bit=0 means enable function (per CX700 datasheet)
+	 *   5 16.1 USB 2
+	 *   4 16.0 USB 1
+	 *   3 15.0 SATA and PATA
+	 *   2 16.2 USB 3
+	 *   1 16.4 USB EHCI
 	 */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				PCI_DEVICE_ID_VIA_VT6420_SATA), 0);
-	if (dev != PCI_DEV_INVALID) {
-		/* Enable PATA. */
-		reg = pci_read_config8(dev, 0xd1);
-		reg |= 0x08;
-		pci_write_config8(dev, 0xd1, reg);
-		reg = pci_read_config8(dev, 0x49);
-		reg |= 0x80;
-		pci_write_config8(dev, 0x49, reg);
-	} else {
-		print_debug("No SATA device\r\n");
-	}
+	pci_write_config8(dev, 0x50, 0x80);
 
-	/* Disable SATA, and PATA device will be 00:0f.0. */
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
-	if (dev == PCI_DEV_INVALID)
-		die("Southbridge not found!!!\r\n");
-	reg = pci_read_config8(dev, 0x50);
-	reg |= 0x08;
-	pci_write_config8(dev, 0x50, reg);
+	/* bit=1 means enable internal function (per CX700 datasheet)
+	 *   3 Internal RTC
+	 *   2 Internal PS2 Mouse
+	 *   1 Internal KBC Configuration
+	 *   0 Internal Keyboard Controller
+	 */
+	pci_write_config8(dev, 0x51, 0x1d);
 }
 
 static const struct mem_controller ctrl = {

Modified: trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c	2008-09-01 01:48:07 UTC (rev 3556)
@@ -366,7 +366,7 @@
 	/* dram duty control */
 	pci_write_config8(ctrl->d0f3, 0xed, 0x10);
 
-	/* SMM and APIC deocoding, we donot use SMM */
+	/* SMM and APIC decoding, we do not use SMM */
 	reg = 0x29;
 	pci_write_config8(ctrl->d0f3, 0x86, reg);
 	/* SMM and APIC decoding mirror */

Modified: trunk/coreboot-v2/src/northbridge/via/cn700/vga.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/vga.c	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/vga.c	2008-09-01 01:48:07 UTC (rev 3556)
@@ -45,14 +45,12 @@
 	u8 reg8;
 
 	print_debug("Copying BOCHS Bios to 0xf000\n");
-/* Copy the BOCHs BIOS from 0xFFFFFFFF - ROM_SIZE - BOCHs size (64k) to 0xf0000
-   This is for compatibility with the VGA ROM's BIOS callbacks */
-	memcpy(0xf0000, (0xFFFFFFFF - ROM_SIZE - 0x10000), 0x10000);
+	/* Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
+	 * This is for compatibility with the VGA ROM's BIOS callbacks */
+	memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000);
 
 	printk_debug("Initializing VGA\n");
 	
-	pci_write_config8(dev, 0x3c, 0xb);
-
 	/* Set memory rate to 200MHz */
 	outb(0x3d, CRTM_INDEX);
 	reg8 = inb(CRTM_DATA);
@@ -71,8 +69,6 @@
 	pci_write_config8(dev, 0x0d, 0x20);
 	pci_write_config32(dev,0x10, 0xf4000008);
 	pci_write_config32(dev,0x14, 0xfb000000);
-	pci_write_config8(dev, 0x3e, 0x02);
-	pci_write_config8(dev, 0x3c, 0x0a);
 	
 	
 	printk_debug("INSTALL REAL-MODE IDT\n");

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c	2008-09-01 01:48:07 UTC (rev 3556)
@@ -79,8 +79,6 @@
 	pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
 
 	/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
-	/* Extend ROM decode to 1MB FFC00000 - FFFFFFFF */
-	pci_write_config8(dev, 0x41, 0x7f);
 }
 
 struct chip_operations southbridge_via_vt8237r_ops = {

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2008-09-01 01:48:07 UTC (rev 3556)
@@ -244,10 +244,20 @@
 	enables |= 0x80;
 	pci_write_config8(dev, 0x6C, enables);
 
-	/* FIXME: Map 4MB of flash into the address space,
-	 * this should be in CAR call.
+	/*
+	 * ROM decode
+	 * bit range
+	 *   7 000E0000h-000EFFFFh
+	 *   6 FFF00000h-FFF7FFFFh
+	 *   5 FFE80000h-FFEFFFFFh
+	 *   4 FFE00000h-FFE7FFFFh
+	 *   3 FFD80000h-FFDFFFFFh
+	 *   2 FFD00000h-FFD7FFFFh
+	 *   1 FFC80000h-FFCFFFFFh
+	 *   0 FFC00000h-FFC7FFFFh
+	 * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
 	 */
-	/* pci_write_config8(dev, 0x41, 0x7f); */
+	pci_write_config8(dev, 0x41, 0x7f);
 
 	/* Set bit 6 of 0x40 (I/O recovery time).
 	 * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
@@ -271,8 +281,14 @@
 	/* ROM memory cycles go to LPC. */
 	pci_write_config8(dev, 0x59, 0x80);
 
-	/* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */
-	pci_write_config8(dev, 0x5B, 0xb);
+	/*
+	 * bit meaning
+	 *   3 Bypass APIC De-Assert Message (1=Enable)
+	 *   1 possibly "INTE#, INTF#, INTG#, INTH# as PCI"
+	 *     bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
+	 *   0 Dynamic Clock Gating Main Switch (1=Enable)
+	 */
+	pci_write_config8(dev, 0x5b, 0x9);
 
 	/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */
 	pci_write_config8(dev, 0x48, 0x8c);

Modified: trunk/coreboot-v2/targets/via/epia-cn/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/via/epia-cn/Config.lb	2008-08-31 22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/targets/via/epia-cn/Config.lb	2008-09-01 01:48:07 UTC (rev 3556)
@@ -22,6 +22,13 @@
 target via_epia_cn
 mainboard via/epia-cn
 
+option MAXIMUM_CONSOLE_LOGLEVEL=8
+option DEFAULT_CONSOLE_LOGLEVEL=8
+option CONFIG_CONSOLE_SERIAL8250=1
+
+# coreboot C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
 #
 # Generate the final ROM like this:
 # cat vgabios bochsbios coreboot.rom > coreboot.rom.final




From peter at stuge.se  Mon Sep  1 03:48:45 2008
From: peter at stuge.se (Peter Stuge)
Date: Mon, 1 Sep 2008 03:48:45 +0200
Subject: [coreboot] Epia-CN Patch
In-Reply-To: <48BB304B.2020502@onelabs.com>
References: <48BB304B.2020502@onelabs.com>
Message-ID: <20080901014845.16879.qmail@stuge.se>

bari wrote:
> This patch gets the Epia-CN working without ACPI or APIC.
> 
> All devices work, no irq storms. Enjoy.
> 
> Signed-off-by: Bari Ari <bari at onelabs.com>

Awesome! Thank you very much.

I made some small changes regarding documentation and whitespace and
then committed this. It's in r3556.


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Mon Sep  1 04:13:21 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 01 Sep 2008 04:13:21 +0200
Subject: [coreboot]  K8 INIT detection
Message-ID: <48BB4FC1.4030309@gmx.net>

Hi Marc,

I'm working on v3 and K8 setup. Right now, we try to determine whether
we rebooted because of INIT by looking at bit 11 of MTRRdefType because
it survives INIT and doesn't survive a cold or warm reboot. Although
this is a nice generic way, we can only read it early in stage0 asm
because we clobber it late in stage0 asm.

HyperTransport Initialization Control Register Function 0 Offset 6Ch Bit
6: InitDet looks exactly like what we want for that, and it is not
clobbered. Quoting from a really old BKDG (26094 Rev. 3.30 February 2006):
"INIT Detect (InitDet)?Bit 6. This bit may be used to distinguish
between an INIT and a warm/cold reset by setting the bit to 1 before an
initialization event is generated. This bit is cleared by a warm or cold
reset but not by an INIT."
Newer BKDGs say the same, so my question is how far back into the past
(in terms of CPUs supported by coreboot v2) and how far into the future
we can rely on this. It would certainly allow our stage0/stage1 code to
enjoy a cleaner design, not to mention improved readability.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Mon Sep  1 04:44:09 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Sep 2008 04:44:09 +0200
Subject: [coreboot] r854 - in coreboot-v3: northbridge/amd/k8
	southbridge/amd/amd8111
Message-ID: <mailman.2014.1355071372.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-09-01 04:44:08 +0200 (Mon, 01 Sep 2008)
New Revision: 854

Modified:
   coreboot-v3/northbridge/amd/k8/coherent_ht.c
   coreboot-v3/northbridge/amd/k8/incoherent_ht.c
   coreboot-v3/northbridge/amd/k8/pci.c
   coreboot-v3/northbridge/amd/k8/raminit.c
   coreboot-v3/southbridge/amd/amd8111/acpi.c
Log:
This finishes the fix to log2. The computed dram size now matches the 
size indicated by byte 31 of SPD. 

Memory is still not working; hanging in dqs training. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/coherent_ht.c	2008-08-31 20:39:48 UTC (rev 853)
+++ coreboot-v3/northbridge/amd/k8/coherent_ht.c	2008-09-01 02:44:08 UTC (rev 854)
@@ -322,7 +322,7 @@
 	freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);
 
 	/* Calculate the highest possible frequency */
-	freq = log2(freq_cap1 & freq_cap2);
+	freq = log2c(freq_cap1 & freq_cap2);
 
 	/* See if I am changing the link freqency */
 	old_freq = pci_conf1_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);

Modified: coreboot-v3/northbridge/amd/k8/incoherent_ht.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/incoherent_ht.c	2008-08-31 20:39:48 UTC (rev 853)
+++ coreboot-v3/northbridge/amd/k8/incoherent_ht.c	2008-09-01 02:44:08 UTC (rev 854)
@@ -229,7 +229,7 @@
 	freq_cap2 = ht_read_freq_cap(bdf2, pos2 + LINK_FREQ_CAP(offs2));
 
 	/* Calculate the highest possible frequency */
-	freq = log2(freq_cap1 & freq_cap2);
+	freq = log2c(freq_cap1 & freq_cap2);
 
 	/* See if I am changing the link freqency */
 	old_freq = pci_conf1_read_config8(bdf1, pos1 + LINK_FREQ(offs1));

Modified: coreboot-v3/northbridge/amd/k8/pci.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/pci.c	2008-08-31 20:39:48 UTC (rev 853)
+++ coreboot-v3/northbridge/amd/k8/pci.c	2008-09-01 02:44:08 UTC (rev 854)
@@ -332,8 +332,8 @@
 	if (resource) {
 		resource->base  = 0;
 		resource->size  = 0;
-		resource->align = log2(HT_IO_HOST_ALIGN);
-		resource->gran  = log2(HT_IO_HOST_ALIGN);
+		resource->align = log2c(HT_IO_HOST_ALIGN);
+		resource->gran  = log2c(HT_IO_HOST_ALIGN);
 		resource->limit = 0xffffUL;
 		resource->flags = IORESOURCE_IO;
 		compute_allocate_resource(&dev->link[link], resource, 
@@ -345,8 +345,8 @@
 	if (resource) {
 		resource->base  = 0;
 		resource->size  = 0;
-		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran  = log2(HT_MEM_HOST_ALIGN);
+		resource->align = log2c(HT_MEM_HOST_ALIGN);
+		resource->gran  = log2c(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 		compute_allocate_resource(&dev->link[link], resource, 
@@ -359,8 +359,8 @@
 	if (resource) {
 		resource->base  = 0;
 		resource->size  = 0;
-		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran  = log2(HT_MEM_HOST_ALIGN);
+		resource->align = log2c(HT_MEM_HOST_ALIGN);
+		resource->gran  = log2c(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM;
 		compute_allocate_resource(&dev->link[link], resource, 

Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c	2008-08-31 20:39:48 UTC (rev 853)
+++ coreboot-v3/northbridge/amd/k8/raminit.c	2008-09-01 02:44:08 UTC (rev 854)
@@ -31,7 +31,7 @@
 #include <string.h>
 #include <mtrr.h>
 #include <macros.h>
-#include <spd.h>
+#include <spd_ddr2.h>
 #include <cpu.h>
 #include <msr.h>
 #include <amd/k8/k8.h>
@@ -765,7 +765,7 @@
 	value = spd_read_byte(device, SPD_BANK_NUM);	/* banks */
 	if (value < 0) goto hw_err;
 	if ((value & 0xff) == 0) goto val_err;
-	sz->bank = log2(value & 0xff);  // convert 4 to 2, and 8 to 3
+	sz->bank = log2c(value & 0xff);  // convert 4 to 2, and 8 to 3
 	printk(BIOS_SPEW, "%d SPD banks %d bank\n", value, sz->bank);
 	sz->per_rank += sz->bank;
 	printk(BIOS_SPEW, "sz->per_rank is now %d\n", sz->per_rank);
@@ -774,8 +774,9 @@
 	if (value < 0) goto hw_err;
 	value &= 0xff;
 	if ((value != 72) && (value != 64)) goto val_err;
-	sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
-	printk(BIOS_SPEW, "value %d log2(value) %d sz->per_rank now %d\n", value, log2(value), sz->per_rank);
+	/* why log2f (floor) here? because 72 bits is really 64 bits + parity */
+	sz->per_rank += log2f(value) - 3; //64 bit So another 3 lines
+	printk(BIOS_SPEW, "value %d log2f(value) %d sz->per_rank now %d\n", value, log2f(value), sz->per_rank);
 
 	/* How many ranks? */
 	value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);	/* number of physical banks */
@@ -783,7 +784,7 @@
 //	value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT;
 	value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
 	value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
-	printk(BIOS_SPEW, "# banks %d\n", value);
+	printk(BIOS_SPEW, "# ranks %d\n", value);
 	/*
 	  rank == 1 only one rank or say one side
 	  rank == 2 two side , and two ranks
@@ -802,13 +803,14 @@
         if (value < 0) goto hw_err;
         value &= 0xff;
 	printk(BIOS_SPEW, "spd rank size is %d\n", value);
-	value = log2(value);
+	value = log2f(value);
 	if(value <=4 ) value += 8; // add back to 1G to high
 	value += (27-5); // make 128MB to the real lines
 	printk(BIOS_SPEW, " computed value is %d\n", value);
 	if( value != (sz->per_rank)) { 
 		printk(BIOS_ERR, "Bad RANK Size -- value is 0x%x, and it should be 0x%x\n", value, sz->per_rank);
-		goto val_err;
+		printk(BIOS_ERR, "This error has been reduced to a warning for now\n");
+//		goto val_err;
 	}
 
 	goto out;
@@ -1112,7 +1114,7 @@
 	/* Chip selects can only be interleaved when there is
 	 * more than one and their is a power of two of them.
 	 */
-	bits = log2(chip_selects);
+	bits = log2c(chip_selects);
 	if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { //chip_selects max = 8
 		return 0;
 	}
@@ -1643,7 +1645,7 @@
 		printk(BIOS_DEBUG, "%s: 0x%x\n", "i:", i);
 		printk(BIOS_DEBUG, "%s: 0x%x\n", "\tlatencies:",  latencies);
 		/* Compute the lowest cas latency supported */
-		latency = log2(latencies) - 2;
+		latency = log2f(latencies) - 2;
 
 		/* Loop through and find a fast clock with a low latency */
 		for(index = 0; index < 3; index++, latency++) {
@@ -1716,7 +1718,7 @@
 		}
 
 		/* Compute the lowest cas latency supported */
-		latency = log2(latencies) -2;
+		latency = log2f(latencies) -2;
 
 		/* Walk through searching for the selected latency */
 		for(index = 0; index < 3; index++, latency++) {
@@ -1832,7 +1834,7 @@
                 return -1;
         }
 
-	value = 6 - log2(value); //4-->4, 8-->3, 16-->2
+	value = 6 - log2f(value); //4-->4, 8-->3, 16-->2
 
 	clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
 

Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/acpi.c	2008-08-31 20:39:48 UTC (rev 853)
+++ coreboot-v3/southbridge/amd/amd8111/acpi.c	2008-09-01 02:44:08 UTC (rev 854)
@@ -185,8 +185,8 @@
 	resource = new_resource(dev, 0x58);
 	resource->base  = 0;
 	resource->size  = 256;
-	resource->align = log2(256);
-	resource->gran  = log2(256);
+	resource->align = log2f(256);
+	resource->gran  = log2f(256);
 	resource->limit = 65536;
 	resource->flags = IORESOURCE_IO;
 	resource->index = 0x58;




From rminnich at gmail.com  Mon Sep  1 08:47:37 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 31 Aug 2008 23:47:37 -0700
Subject: [coreboot] k8 and memory training
Message-ID: <13426df10808312347v3cabaae3y78e0361491c29f2c@mail.gmail.com>

status:
train_DqsRcvrEn: end ctrl  0x0 0
 done
Ram4
stage1 returns
run_file returns with 0
Done RAM init code


Yep, we got through ram init code. Is it working? We'll see. It dies
in disable_car(), which I expected.

This is pretty neat .... I think disable_car() will be hard, but we'll
get it. I hope to have serengeti doing something interesting by the
end of the week. We'll see ... it's off vacation and back to work, so
it's back to nights and weekends, but we'll see.

thanks

ron



From rminnich at gmail.com  Mon Sep  1 08:51:01 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 31 Aug 2008 23:51:01 -0700
Subject: [coreboot] k8 and memory training
In-Reply-To: <48BB2D27.2030405@gmx.net>
References: <13426df10808302346j4290708fr95acfc1144f74a44@mail.gmail.com>
	<48BB2D27.2030405@gmx.net>
Message-ID: <13426df10808312351q5dbdba84p45d5ba12513e8884@mail.gmail.com>

On Sun, Aug 31, 2008 at 4:45 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 31.08.2008 08:46, ron minnich wrote:
>> see http://coreboot.pastebin.com/m354e6401
>>
>> I can't really tell if it's working.
>>
>
> I looked at the log and we're clearly doing something wrong odd. The
> execution order simply does not make that much sense.
>
> arch/x86/stage1.c:stage1_main()
> {
>  //stuff
>  global_vars_init();
>  hardware_stage1();

and here is where we would tie the actual uart hardware to port 3f8 such that:
>  uart_init();  // initialize serial port

works.

>  /* Exactly from now on we can use printk to the serial port.
>   * Celebrate this by printing a LB banner.
>   */
>  console_init();
>  //more stuff
> }
>
> mainboard/amd/serengeti/stage1.c:hardware_stage1()
> {
>  printk(BIOS_ERR, "Stage1: enable rom ...\n");
>  max = ARRAY_SIZE(register_values);
>  setup_resource_map(register_values, max);
>  enumerate_ht_chain();
>  amd8111_enable_rom();
>  printk(BIOS_ERR, "Done.\n");
>  w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
>  post_code(POST_START_OF_MAIN);
> }
>
> Does it only look odd to me that we set up and initialize the serial
> port only after we already have printed lots of stuff which may never
> see the light of the day?

we see the light of day because it is (a) simnow or (b) the legacy
chain is set up right. NOt sure which yet.

> Three possible solutions:
> 1. Use the printk buffer to buffer messages until serial is fully set up.
> 2. Check a global variable which holds the status of serial and start
> using serial only after it has been set up completely. (We may need that
> anyway.)
> 3. Introduce hardware_early_stage1 which only sets up the console and
> anything needed by the console.


It does not really matter actually. You can't really talk to uart
until the setup_resource_map and enumerate_ht_chain have run, and
those functions are solidly debugged. I don't think it's worth too
much concern. This same situation was found on v2. I'm much more
worried about disable_car(), which is the current drop dead point.

I would put this on the "let's look at it later" list. It's not going
to hurt us now if ever.

ron



From rminnich at gmail.com  Mon Sep  1 08:56:51 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 31 Aug 2008 23:56:51 -0700
Subject: [coreboot] /. effect:
Message-ID: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>

from just now:
billybob2 writes "VIA has released a 113,800 line open source graphics
driver with full mode-setting support for CRT, LCD, and DVI devices
along with 2D, X-Video, and cursor acceleration. Harald Welte, VIA's
open source representative, states that the next step is to add 3D
(see preview), TV-out, and hardware codec support while integrating
this work with existing open source projects. VIA has pre-installed
Linux on a significant portion of the company's latest products,
including the EVEREX gPC2, 15.4" gBook, and CloudBook. It has also
helped port the open source CoreBoot BIOS (previously LinuxBIOS) to
several of its motherboards." VIA seems to be making good on the
promise of its open source initiative announced last April.

Neat stuff.

ron



From paulepanter at users.sourceforge.net  Mon Sep  1 09:39:50 2008
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 01 Sep 2008 09:39:50 +0200
Subject: [coreboot] /. effect:
In-Reply-To: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>
References: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>
Message-ID: <1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>

Dear list,


Am Sonntag, den 31.08.2008, 23:56 -0700 schrieb ron minnich:
> from just now:
> billybob2 writes

[?]

> It has also
> helped port the open source CoreBoot BIOS (previously LinuxBIOS) to
> several of its motherboards."

Does anyone know about which boards they are talking? And have the
developers of coreboot experienced any improvement in cooperation?


Thanks,

Paul
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From patrick at georgi-clan.de  Mon Sep  1 15:28:17 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 01 Sep 2008 15:28:17 +0200
Subject: [coreboot] [PATCH]libpayload: memalign, take 2
Message-ID: <48BBEDF1.6030903@georgi-clan.de>

Hi there,

after the discussion on the list about memalign, I wrote version that's
better integrated with the other memory management stuff, and doesn't
come with its own pool allocator.


Regards,
Patrick Georgi
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From bari at onelabs.com  Mon Sep  1 16:09:09 2008
From: bari at onelabs.com (bari)
Date: Mon, 01 Sep 2008 09:09:09 -0500
Subject: [coreboot] /. effect:
In-Reply-To: <1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>
References: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>
	<1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>
Message-ID: <48BBF785.4070500@onelabs.com>

Paul Menzel wrote:
> Does anyone know about which boards they are talking? And have the
> developers of coreboot experienced any improvement in cooperation?
>   

VIA gave us V2 CAR for C7.

VIA fixed raminit for the CN700 so we can now support all the C7 + CN700 
+ vt8237 boards (about 30- 40 currently in production) in V2 and move 
them into V3.

VIA helped support the vt8237s and KT890 for the a8v-e_se and m2v-mx_se.

VIA posted programming guides for CX700M/VX700 and VX800 
http://linux.via.com.tw/support/downloadFiles.action

-Bari




From paulepanter at users.sourceforge.net  Mon Sep  1 16:18:21 2008
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 01 Sep 2008 16:18:21 +0200
Subject: [coreboot] /. effect:
In-Reply-To: <48BBF785.4070500@onelabs.com>
References: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>
	<1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>
	<48BBF785.4070500@onelabs.com>
Message-ID: <1220278701.3548.18.camel@mattotaupa.wohnung.familie-menzel.net>

Dear list,


Am Montag, den 01.09.2008, 09:09 -0500 schrieb bari:
> Paul Menzel wrote:
> > Does anyone know about which boards they are talking? And have the
> > developers of coreboot experienced any improvement in cooperation?
> >   
> 
> VIA gave us V2 CAR for C7.
> 
> VIA fixed raminit for the CN700 so we can now support all the C7 + CN700 
> + vt8237 boards (about 30- 40 currently in production) in V2 and move 
> them into V3.
> 
> VIA helped support the vt8237s and KT890 for the a8v-e_se and m2v-mx_se.
> 
> VIA posted programming guides for CX700M/VX700 and VX800 
> http://linux.via.com.tw/support/downloadFiles.action

Thanks Bari for this overview. I must have overlooked this on the
mailinglist, since when I subscribed around a year ago.


Thanks,

Paul
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From svn at coreboot.org  Mon Sep  1 16:49:07 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  1 Sep 2008 16:49:07 +0200
Subject: [coreboot] r57 - in trunk/filo: . drivers fs i386 include
	include/grub main main/grub
Message-ID: <mailman.2015.1355071372.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-09-01 16:49:06 +0200 (Mon, 01 Sep 2008)
New Revision: 57

Added:
   trunk/filo/include/drivers.h
Modified:
   trunk/filo/Makefile
   trunk/filo/build.sh
   trunk/filo/drivers/ide.c
   trunk/filo/drivers/via-sound.c
   trunk/filo/fs/blockdev.c
   trunk/filo/fs/eltorito.c
   trunk/filo/i386/ldscript
   trunk/filo/i386/timer.c
   trunk/filo/include/grub/shared.h
   trunk/filo/include/lib.h
   trunk/filo/include/sound.h
   trunk/filo/main/elfload.c
   trunk/filo/main/filo.c
   trunk/filo/main/grub.c
   trunk/filo/main/grub/builtins.c
   trunk/filo/main/grub/char_io.c
   trunk/filo/main/grub/cmdline.c
   trunk/filo/main/grub/stage2.c
   trunk/filo/main/sound.c
Log:
FILO fixes
* fix mixup issues between grub_printf and printf
* try to unify driver interface
* drop a couple of duplicate endianess functions
* fix serial port init failure
* fix creation of device names from grub interface device names (somewhat)
* fix timer calculation and overflow issues
* Clean up Makefile and build.sh script


Modified: trunk/filo/Makefile
===================================================================
--- trunk/filo/Makefile	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/Makefile	2008-09-01 14:49:06 UTC (rev 57)
@@ -117,11 +117,11 @@
 
 $(obj)/%.o: $(src)/%.c
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(CC) -m32 $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
+	$(Q)$(CC) $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
 
 $(obj)/%.S.o: $(src)/%.S
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(AS) --32 -o $@ $<
+	$(Q)$(AS) -o $@ $<
 
 endif
 

Modified: trunk/filo/build.sh
===================================================================
--- trunk/filo/build.sh	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/build.sh	2008-09-01 14:49:06 UTC (rev 57)
@@ -12,22 +12,22 @@
 	STRIP=i386-elf-strip	\
 	NM=i386-elf-nm		\
 	HOSTCC=gcc		\
-	-j
+	-j			\
 	"
 fi
 if [ "$OS" == "Linux" ]; then
-MAKEFLAGS='CC="gcc -m32" LD="ld -b elf32-i386" HOSTCC="gcc"'
+MAKEFLAGS='CC="gcc -m32" LD="ld -b elf32-i386" HOSTCC="gcc" AS="as --32"'
 fi
 
 if [ "$ALLCLEAN" != "" -o ! -r libpayload/build/lib/libpayload.a ]; then
   cd libpayload
   make clean
-  make defconfig
-  make $MAKEFLAGS
+  make oldconfig
+  eval make $MAKEFLAGS
   cd ..
 fi
 
 make distclean
 make defconfig
-make $MAKEFLAGS
+eval make $MAKEFLAGS
 

Modified: trunk/filo/drivers/ide.c
===================================================================
--- trunk/filo/drivers/ide.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/drivers/ide.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -246,7 +246,7 @@
 static unsigned char ide_buffer[IDE_SECTOR_SIZE];
 
 static int await_ide(int (*done)(struct controller *ctrl), 
-	struct controller *ctrl, unsigned long timeout)
+	struct controller *ctrl, u64 timeout)
 {
 	int result;
 	for(;;) {
@@ -839,7 +839,7 @@
  * This is based on a paper on Phoenix website. --ts1 */
 static int ide_bus_floating(struct controller *ctrl)
 {
-	unsigned long timeout;
+	u64 timeout;
 	unsigned char status;
 
 	/* Test 1: if status reads 0xff, probably no device is present
@@ -1007,7 +1007,7 @@
 	uint8_t packet[12];
 	uint8_t buf[8];
 	uint32_t block_len, sectors;
-	unsigned long timeout;
+	u64 timeout;
 	uint8_t asc, ascq;
 	int in_progress;
 
@@ -1308,4 +1308,30 @@
 	return 0;
 }
 
+#if 0
+
+static char my_name="hd";
+static char ide_name(void);
+{
+	return my_name;
+}
+
+static const struct storage_ops ide_ops = {
+	.init = NULL,
+	.open = ide_probe,
+	.close = NULL,
+	.read_sector = NULL // FIXME
+	// This should probably contain drive, too: Should it?
+	// void (*read_sector)(u64 sector, const void *buf, int size);
+	.name = ide_name,
+};
+
+static const struct driver ide_driver __driver = {
+	.type=DRIVER_STORAGE,
+	{
+		.storage_ops=&ide_ops
+	}
+};
+#endif
+
 /* vim:set sts=8 sw=8: */

Modified: trunk/filo/drivers/via-sound.c
===================================================================
--- trunk/filo/drivers/via-sound.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/drivers/via-sound.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -17,6 +17,7 @@
 
 #include <libpayload.h>
 #include <config.h>
+#include <drivers.h>
 #include <sound.h>
 #define DEBUG_THIS CONFIG_DEBUG_VIA_SOUND
 #include <debug.h>
@@ -91,11 +92,17 @@
 	return 0;
 }
 
-static struct sound_ops viasnd_ops = {
+static const struct sound_ops viasnd_ops = {
 	.init = viasnd_init,
 	.stop = viasnd_stop,
 };
 
-const struct sound_driver viasnd_driver[] __sound_driver = {
-	{0x1106, 0x3058, &viasnd_ops},	/* VT82C686 AC97 Audio Controller */
+/* VT82C686 AC97 Audio Controller */
+static const struct driver viasnd_driver __driver = {
+	.type=DRIVER_SOUND,
+	.vendor=0x1106,
+	.device=0x3058,
+	{
+		.sound_ops=&viasnd_ops
+	}
 };

Modified: trunk/filo/fs/blockdev.c
===================================================================
--- trunk/filo/fs/blockdev.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/fs/blockdev.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -82,8 +82,8 @@
 	    printf("Partition %d does not exist\n", part+1);
 	    return 0;
 	}
-	*start_p = get_le32(p->start_sect);
-	*length_p = get_le32(p->nr_sects);
+	*start_p = cpu_to_le32(*(u32 *)(p->start_sect));
+	*length_p = cpu_to_le32(*(u32 *)(p->nr_sects));
 	return 1;
     } else {
 	/* Extended partition */
@@ -102,7 +102,7 @@
 	}
 	debug("Extended partition at %d\n", i+1);
 	/* Visit each logical partition labels */
-	ext_start = get_le32(p[i].start_sect);
+	ext_start = cpu_to_le32(*(u32*)(p[i].start_sect));
 	cur_table = ext_start;
 	cur_part = 4;
 	for (;;) {
@@ -121,8 +121,8 @@
 		    printf("Partition %d is empty\n", part+1);
 		    return 0;
 		}
-		*start_p = cur_table + get_le32(p->start_sect);
-		*length_p = get_le32(p->nr_sects);
+		*start_p = cur_table + cpu_to_le32(*(u32*)(p->start_sect));
+		*length_p = cpu_to_le32(*(u32*)(p->nr_sects));
 		return 1;
 	    }
 	    /* Second entry is link to next partition */
@@ -130,7 +130,7 @@
 		debug("no link\n");
 		break;
 	    }
-	    cur_table = ext_start + get_le32(p[1].start_sect);
+	    cur_table = ext_start + cpu_to_le32(*(u32*)(p[1].start_sect));
 
 	    cur_part++;
 	}
@@ -451,17 +451,3 @@
     return 1;
 }
 
-uint32_t get_le32(const unsigned char *p)
-{
-	return ((unsigned int) p[0] << 0)
-		| ((unsigned int) p[1] << 8)
-		| ((unsigned int) p[2] << 16)
-		| ((unsigned int) p[3] << 24);
-}
-
-uint16_t get_le16(const unsigned char *p)
-{
-	return ((unsigned int) p[0] << 0) 
-		| ((unsigned int) p[1] << 8);
-}
-

Modified: trunk/filo/fs/eltorito.c
===================================================================
--- trunk/filo/fs/eltorito.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/fs/eltorito.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -100,7 +100,7 @@
 	return 0;
     }
 
-    cat_offset = get_le32(boot_record.catalog_offset);
+    cat_offset = le32_to_cpu(*(u32*)boot_record.catalog_offset);
     debug("El-Torito boot catalog at sector %u\n", cat_offset);
     if (!devread(cat_offset<<2, 0, 2048, catalog))
 	return 0;
@@ -115,7 +115,7 @@
     /* All words must sum up to zero */
     sum = 0;
     for (i = 0; i < sizeof(*ve); i += 2)
-	sum += get_le16(&catalog[i]);
+	sum += le16_to_cpu(catalog[i]);
     sum &= 0xffff;
     if (sum != 0) {
 	printf("El Torito boot catalog verify failed\n");
@@ -153,7 +153,7 @@
 	printf("Disc uses hard disk emulation - not supported\n");
 	return 0;
     }
-    *offset_p = get_le32(de->start_sector) << 2;
+    *offset_p = le32_to_cpu(*(u32*)(de->start_sector)) << 2;
     debug("offset=%#lx length=%#lx\n", *offset_p, *length_p);
 
     return 1;

Modified: trunk/filo/i386/ldscript
===================================================================
--- trunk/filo/i386/ldscript	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/i386/ldscript	2008-09-01 14:49:06 UTC (rev 57)
@@ -53,9 +53,9 @@
     .text : { *(.text) *(.text.*) }
     .rodata : {
 	. = ALIGN(4);
-	sound_drivers_start = .;
-	*(.rodata.sound_drivers)
-	sound_drivers_end = .;
+	drivers_start = .;
+	*(.rodata.drivers)
+	drivers_end = .;
 	*(.rodata)
 	*(.rodata.*)
     }

Modified: trunk/filo/i386/timer.c
===================================================================
--- trunk/filo/i386/timer.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/i386/timer.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -19,20 +19,19 @@
 
 #include <libpayload.h>
 #include <arch/rdtsc.h>
+#include <arch/timer.h>
 
-extern unsigned int cpu_khz;
-
 u64 currticks(void)
 {
 	/* Read the Time Stamp Counter */
-	return  rdtsc() / cpu_khz;
+	return  rdtsc();
 }
 
 int getrtsecs (void)
 {
 	u64 t;
 	t=currticks();
-	t=t/1000;
+	t=t/(TICKS_PER_SEC);
 	return (int)t;
 }
 

Added: trunk/filo/include/drivers.h
===================================================================
--- trunk/filo/include/drivers.h	                        (rev 0)
+++ trunk/filo/include/drivers.h	2008-09-01 14:49:06 UTC (rev 57)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of FILO.
+ *
+ * (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef DRIVERS_H
+#define DRIVERS_H
+
+#include <libpayload.h>
+
+/*
+ * Driver interface
+ */
+
+typedef enum {
+	DRIVER_SOUND = 1,
+	DRIVER_STORAGE = 2
+} drivertype_t;
+
+struct sound_ops {
+	int (*init)(pcidev_t dev);
+	void (*set_rate)(int rate);
+	void (*set_volume)(int volume);
+	int (*write)(const void *buf, int size);
+	int (*is_active)(void);
+	void (*stop)(void);
+};
+
+struct storage_ops {
+	int (*init)(pcidev_t dev);
+	int (*open)(int drive);
+	int (*close)(int drive);
+	void (*read_sector)(u64 sector, const void *buf, int size);
+	char *(*name)(void);
+};
+
+struct driver {
+	drivertype_t type;
+	u16 vendor;
+	u16 device;
+	union {
+		const struct storage_ops *storage_ops;
+		const struct sound_ops *sound_ops;
+	};
+};
+
+#define __driver __attribute__((unused, section(".rodata.drivers")))
+
+/* defined by the linker */
+extern struct driver drivers_start[];
+extern struct driver drivers_end[];
+
+#endif /* DRIVERS_H */

Modified: trunk/filo/include/grub/shared.h
===================================================================
--- trunk/filo/include/grub/shared.h	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/include/grub/shared.h	2008-09-01 14:49:06 UTC (rev 57)
@@ -362,7 +362,7 @@
 //#define memcpy grub_memmove	/* we don't need a separate memcpy */
 //#define memset grub_memset
 //#define isspace grub_isspace
-#define printf grub_printf
+// #define printf grub_printf
 //#define sprintf grub_sprintf
 #undef putchar
 #define putchar grub_putchar

Modified: trunk/filo/include/lib.h
===================================================================
--- trunk/filo/include/lib.h	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/include/lib.h	2008-09-01 14:49:06 UTC (rev 57)
@@ -28,9 +28,6 @@
 unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
 unsigned long long strtoull_with_suffix(const char *cp,char **endp,unsigned int base);
 
-u32 get_le32(const unsigned char *);
-u16 get_le16(const unsigned char *);
-
 void hexdump(const void *p, unsigned int len);
 
 long long simple_strtoll(const char *cp,char **endp,unsigned int base);

Modified: trunk/filo/include/sound.h
===================================================================
--- trunk/filo/include/sound.h	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/include/sound.h	2008-09-01 14:49:06 UTC (rev 57)
@@ -32,29 +32,4 @@
 void sound_stop(void);
 int sound_is_active(void);
 
-/*
- * Driver interface
- */
-
-struct sound_ops {
-    int (*init)(pcidev_t);
-    void (*set_rate)(int rate);
-    void (*set_volume)(int volume);
-    int (*write)(const void *buf, int size);
-    int (*is_active)(void);
-    void (*stop)(void);
-};
-
-struct sound_driver {
-    u16 vendor;
-    u16 device;
-    struct sound_ops *ops;
-};
-
-#define __sound_driver __attribute__((unused, section(".rodata.sound_drivers")))
-
-/* defined by the linker */
-extern struct sound_driver sound_drivers_start[];
-extern struct sound_driver sound_drivers_end[];
-
 #endif /* SOUND_H */

Modified: trunk/filo/main/elfload.c
===================================================================
--- trunk/filo/main/elfload.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/elfload.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -135,7 +135,7 @@
 	unsigned long checksum_offset)
 {
     unsigned long bytes;
-    unsigned int start_time, time;
+    u64 start_time, time;
     int i;
 
     bytes = 0;

Modified: trunk/filo/main/filo.c
===================================================================
--- trunk/filo/main/filo.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/filo.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -108,7 +108,7 @@
 #if CONFIG_AUTOBOOT_DELAY
 static inline int autoboot_delay(void)
 {
-    unsigned int timeout;
+    u64 timeout;
     int sec, tmp;
     char key;
     

Modified: trunk/filo/main/grub/builtins.c
===================================================================
--- trunk/filo/main/grub/builtins.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/grub/builtins.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -1,6 +1,9 @@
 /*
  * This file is part of FILO.
  *
+ *  Copyright (C) 1999,2000,2001,2002,2004  Free Software Foundation, Inc.
+ *  Copyright (C) 2005-2008 coresystems GmbH
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -18,7 +21,6 @@
 
 #include <libpayload.h>
 #include <config.h>
-#define printf grub_printf
 #include <grub/shared.h>
 #include <grub/term.h>
 #include <grub/terminfo.h>
@@ -58,7 +60,8 @@
 int auth = 0;
 
 /* -------- FILO logic -------- */
-char boot_line[1024]={0};
+#define BOOT_LINE_LENGTH 1024
+char boot_line[BOOT_LINE_LENGTH]={0};
 char root_device[16]={0};
 /* ---------------------------- */
 
@@ -494,23 +497,109 @@
 #endif
 };
 
+/**
+ * @param arg  source pointer with grub device names
+ * @param path destination pointer (will be filled with filo device names)
+ * @param use_rootdev values other than zero mean the root device set by the "root"
+ * command is taken into regard here. This has to be zero when calling from root_func.
+ */
 
+static void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev)
+{
+	char devicename[16];
+	char drivername[16];
+	int disk, part;
+	int i, len;
+
+
+	/* Clean up */
+	memset(devicename, 0, 16);
+	memset(drivername, 0, 16);
+
+	/* Copy over the driver name: "hd", "ud", "sd" ... */
+	if (arg[0] == '(') {
+		i = 1;
+		/* Read until we encounter a number, a comma or a closing
+		 * bracket
+		 */
+		while ((i <= 16) && (arg[i]) &&
+			(!isdigit(arg[i])) && (arg[i] != ',') && (arg[i] != ')')) {
+			drivername[i-1] = arg[i];
+			i++;
+		}
+	}
+
+	disk = -1;
+	part = -1;
+
+	len = strlen(drivername);
+	if (len) { /* We have a driver. No idea if it exists though */
+		// The driver should decide this:
+		len++; // skip driver name + opening bracket
+
+		// XXX put @ handling in here, too for flash at addr and mem at addr
+
+		if (isdigit(arg[len])) {
+			disk = arg[len] - '0';
+			len++;
+			if (isdigit(arg[len])) { /* More than 9 drives? */
+				/* ok, get one more number. No more than 99 drives */
+				disk *= 10;
+				disk += arg[len] - '0';
+				len++;
+			}
+		}
+		if (arg[len] == ',') {
+			len++;
+			part = arg[len] - '0';
+			len++;
+			if (isdigit(arg[len])) { /* More than 9 partitions? */
+				/* ok, get one more number. No more than 99
+				 * partitions */
+				part *= 10;
+				part += arg[len] - '0';
+				len++;
+			}
+		}
+		if (arg[len] != ')') {
+			grub_printf("Drive Error.\n");
+			// set len = 0 --> just copy the drive name 
+			len = 0;
+		} else {
+			len++; // skip closing bracket
+		}
+	}
+
+	if (disk == -1) {
+		grub_printf("No drive.\n");
+		len = 0; // just copy the drive name
+	} else {
+		if(part == -1) { // No partition
+			sprintf(devicename, "%s%c:", drivername, disk + 'a');
+		} else { // both disk and partition
+			sprintf(devicename, "%s%c%d:", drivername, disk + 'a', part + 1);
+		}
+		strncat(path, devicename, BOOT_LINE_LENGTH);
+		arg += len; // skip original drive name
+	}
+
+	if (use_rootdev && !len) { // No drive was explicitly specified
+		if (strlen(root_device)) { // But someone set a root device
+			strncat(path, root_device, BOOT_LINE_LENGTH);
+		}
+	}
+
+	/* Copy the rest over */
+	strncat(path, arg, BOOT_LINE_LENGTH);
+}
+
 /* initrd */
 static int
 initrd_func (char *arg, int flags)
 {
-	char dummy[16]={0};
-	int disk, part;
-	if(arg[0]=='(' && arg[1]=='h' && arg[2]=='d') {
-		disk=arg[3]-'0';
-		part=arg[5]-'0';
-		arg+=7; // FIXME only 9 disks with 9 partitions for booting
-		sprintf(dummy, "hd%c%c:", disk+'a', part+'1');
-	}
-	strncat(boot_line," initrd=", 1000);
-	if(dummy[0]) strncat(boot_line,dummy, 1000);
-	grub_strncat(boot_line,arg, 1000);
-	
+	strncat(boot_line, " initrd=", BOOT_LINE_LENGTH);
+	copy_path_to_filo_bootline(arg, boot_line, 1);
+
 	return 0;
 }
 
@@ -531,20 +620,14 @@
 static int
 kernel_func (char *arg, int flags)
 {
-	int disk,part;
 	/* Needed to pass grub checks */
 	kernel_type=KERNEL_TYPE_LINUX;
-	if(arg[0]=='(' && arg[1]=='h' && arg[2]=='d') {
-		disk=arg[3]-'0';
-		part=arg[5]-'0';
-		arg+=7; // FIXME only 9 disks with 9 partitions for booting
-		sprintf(boot_line, "hd%c%c:", disk+'a', part+'1');
-	} else if (root_device[0]=='h' && root_device[1]=='d') {
-		strcpy(boot_line, root_device);
-	}
-	
-	strncat(boot_line, arg, 1000);
-	
+
+	/* clear out boot_line. Kernel is the first thing */
+	memset(boot_line, 0, BOOT_LINE_LENGTH);
+
+	copy_path_to_filo_bootline(arg, boot_line, 1);
+
 	return 0;
 }
 
@@ -720,7 +803,7 @@
 static int
 pause_func (char *arg, int flags)
 {
-  printf("%s\n", arg);
+  grub_printf("%s\n", arg);
 
   /* If ESC is returned, then abort this entry.  */
   if (ASCII_CHAR (getkey ()) == 27)
@@ -742,15 +825,10 @@
 static int
 root_func (char *arg, int flags)
 {
-  int disk, part;
+	memset(root_device, 0, 16);
+	copy_path_to_filo_bootline(arg, root_device, 0);
 
-  if(arg[0]!='(') return 1;
-  if(arg[1]!='h') return 1;
-  if(arg[2]!='d') return 1;
-  disk=arg[3]-'0';
-  part=arg[5]-'0';
-  sprintf(root_device, "hd%c%c:", disk+'a', part+'1');
-  return 0;
+  	return 0;
 }
 
 static struct builtin builtin_root =

Modified: trunk/filo/main/grub/char_io.c
===================================================================
--- trunk/filo/main/grub/char_io.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/grub/char_io.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -85,10 +85,15 @@
       console_setcursor
     },
 #endif
+#ifdef CONFIG_SERIAL_CONSOLE
     {
       "serial",
       /* A serial device must be initialized.  */
+#if 0
       TERM_NEED_INIT,
+#else
+      0, // Not with FILO..
+#endif
       grub_serial_putchar,
       serial_checkkey,
       serial_getkey,
@@ -99,6 +104,7 @@
       0,
       0
     },
+#endif
     /* This must be the last entry.  */
     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
   };
@@ -116,10 +122,10 @@
 {
   if (errnum > ERR_NONE && errnum < MAX_ERR_NUM)
 #ifndef STAGE1_5
-    /* printf("\7\n %s\n", err_list[errnum]); */
-    printf ("\nError %u: %s\n", errnum, err_list[errnum]);
+    /* grub_printf("\7\n %s\n", err_list[errnum]); */
+    grub_printf ("\nError %u: %s\n", errnum, err_list[errnum]);
 #else /* STAGE1_5 */
-    printf ("Error %u\n", errnum);
+    grub_printf ("Error %u\n", errnum);
 #endif /* STAGE1_5 */
 }
 

Modified: trunk/filo/main/grub/cmdline.c
===================================================================
--- trunk/filo/main/grub/cmdline.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/grub/cmdline.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -42,20 +42,23 @@
 }
 
 /* Print a helpful message for the command-line interface.  */
-void
-print_cmdline_message (int type)
+void print_cmdline_message (int type)
 {
-  printf (" [ Minimal BASH-like line editing is supported.  For the first word, TAB\n"
-	  "   lists possible command completions.  Anywhere else TAB lists the possible\n"
-	  "   completions of a device/filename.");
-  if (type == CMDLINE_NORMAL_MODE)
-    printf("  ESC at any time exits.");
-  if (type == CMDLINE_EDIT_MODE)
-    printf("  ESC at any time cancels.  ENTER \n"
-           "   at any time accepts your changes.");
-  printf("]\n");
+	grub_printf(" [ Minimal BASH-like line editing is supported.  For the first word, TAB\n"
+		    "   lists possible command completions.  Anywhere else TAB lists the possible\n"
+		    "   completions of a device/filename.");
+
+	if (type == CMDLINE_NORMAL_MODE)
+		grub_printf("  ESC at any time exits.");
+
+	if (type == CMDLINE_EDIT_MODE)
+		grub_printf("  ESC at any time cancels.  ENTER \n"
+			    "   at any time accepts your changes.");
+
+	grub_printf("]\n");
+
 #ifndef CONFIG_NEWLINE_BEFORE_EACH_PROMPT
-  printf("\n");
+	grub_printf("\n");
 #endif
 }
 

Modified: trunk/filo/main/grub/stage2.c
===================================================================
--- trunk/filo/main/grub/stage2.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/grub/stage2.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -318,19 +318,19 @@
       
       if (! auth && password)
 	{
-	  printf ("\
+	  grub_printf ("\
       Press enter to boot the selected OS or \'p\' to enter a\n\
       password to unlock the next set of features.");
 	}
       else
 	{
 	  if (config_entries)
-	    printf ("\
+	    grub_printf ("\
       Press enter to boot the selected OS, \'e\' to edit the\n\
       commands before booting, \'a\' to modify the kernel arguments\n\
       before booting, or \'c\' for a command-line.");
 	  else
-	    printf ("\
+	    grub_printf ("\
       Press \'b\' to boot, \'e\' to edit the selected command in the\n\
       boot sequence, \'c\' for a command-line, \'o\' to open a new line\n\
       after (\'O\' for before) the selected line, \'d\' to remove the\n\
@@ -397,7 +397,7 @@
 		grub_putchar ('\r');
 	      else
 		gotoxy (3, 22);
-	      printf ("                                                                    ");
+	      grub_printf ("                                                                    ");
 	      grub_timeout = -1;
 	      fallback_entryno = -1;
 	      if (! (current_term->flags & TERM_DUMB))
@@ -819,10 +819,10 @@
   while (1)
     {
       if (config_entries)
-	printf ("  Booting \'%s\'\n\n",
+	grub_printf ("  Booting \'%s\'\n\n",
 		get_entry (menu_entries, first_entry + entryno, 0));
       else
-	printf ("  Booting command-list\n\n");
+	grub_printf ("  Booting command-list\n\n");
 
       if (! cur_entry)
 	cur_entry = get_entry (config_entries, first_entry + entryno, 1);

Modified: trunk/filo/main/grub.c
===================================================================
--- trunk/filo/main/grub.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/grub.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -38,7 +38,7 @@
 #if CONFIG_MENULST_TIMEOUT
 static inline int menulst_delay(void)
 {
-    unsigned int timeout;
+    u64 timeout;
     int sec, tmp;
     char key;
     

Modified: trunk/filo/main/sound.c
===================================================================
--- trunk/filo/main/sound.c	2008-08-29 13:43:47 UTC (rev 56)
+++ trunk/filo/main/sound.c	2008-09-01 14:49:06 UTC (rev 57)
@@ -15,21 +15,23 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
+#include <drivers.h>
 #include <sound.h>
 #include <pci.h>
 
-static struct sound_ops *ops;
+static const struct sound_ops *ops;
 
 int sound_init(void)
 {
-    struct sound_driver *drv;
+    struct driver *drv;
     pcidev_t dev = 0;
 
-    for (drv = sound_drivers_start; drv < sound_drivers_end; drv++) {
+    for (drv = drivers_start; drv < drivers_end; drv++) {
+	if (drv->type != DRIVER_SOUND)
+		continue;
 	if (pci_find_device(drv->vendor, drv->device, &dev)) {
-	    if (drv->ops->init(dev) == 0) {
-		ops = drv->ops;
+	    if (drv->sound_ops->init(dev) == 0) {
+		ops = drv->sound_ops;
 		return 0;
 	    }
 	}




From c-d.hailfinger.devel.2006 at gmx.net  Mon Sep  1 16:50:10 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 01 Sep 2008 16:50:10 +0200
Subject: [coreboot] k8 and memory training
In-Reply-To: <13426df10808312351q5dbdba84p45d5ba12513e8884@mail.gmail.com>
References: <13426df10808302346j4290708fr95acfc1144f74a44@mail.gmail.com>	
	<48BB2D27.2030405@gmx.net>
	<13426df10808312351q5dbdba84p45d5ba12513e8884@mail.gmail.com>
Message-ID: <48BC0122.7080102@gmx.net>

On 01.09.2008 08:51, ron minnich wrote:
> On Sun, Aug 31, 2008 at 4:45 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> On 31.08.2008 08:46, ron minnich wrote:
>>     
>>> see http://coreboot.pastebin.com/m354e6401
>>>
>>> I can't really tell if it's working.
>>>
>>>       
>> I looked at the log and we're clearly doing something wrong odd. The
>> execution order simply does not make that much sense.
>>
>> arch/x86/stage1.c:stage1_main()
>> {
>>  //stuff
>>  global_vars_init();
>>  hardware_stage1();
>>     
>
> and here is where we would tie the actual uart hardware to port 3f8 such that:
>   
>>  uart_init();  // initialize serial port
>>     
>
> works.
>
>   
>>  /* Exactly from now on we can use printk to the serial port.
>>   * Celebrate this by printing a LB banner.
>>   */
>>  console_init();
>>  //more stuff
>> }
>>
>> mainboard/amd/serengeti/stage1.c:hardware_stage1()
>> {
>>  printk(BIOS_ERR, "Stage1: enable rom ...\n");
>>  max = ARRAY_SIZE(register_values);
>>  setup_resource_map(register_values, max);
>>  enumerate_ht_chain();
>>  amd8111_enable_rom();
>>  printk(BIOS_ERR, "Done.\n");
>>  w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
>>  post_code(POST_START_OF_MAIN);
>> }
>>
>> Does it only look odd to me that we set up and initialize the serial
>> port only after we already have printed lots of stuff which may never
>> see the light of the day?
>>     
>
> we see the light of day because it is (a) simnow or (b) the legacy
> chain is set up right. NOt sure which yet.
>
>   
>> Three possible solutions:
>> 1. Use the printk buffer to buffer messages until serial is fully set up.
>> 2. Check a global variable which holds the status of serial and start
>> using serial only after it has been set up completely. (We may need that
>> anyway.)
>> 3. Introduce hardware_early_stage1 which only sets up the console and
>> anything needed by the console.
>>     
>
>
> It does not really matter actually. You can't really talk to uart
> until the setup_resource_map and enumerate_ht_chain have run, and
>   

Thanks for the explanation. I didn't know that.

> those functions are solidly debugged. I don't think it's worth too
> much concern. This same situation was found on v2. I'm much more
> worried about disable_car(), which is the current drop dead point.
>   

Sure, it is completely broken and trashes our stack. Yesterday I wanted
to post a patch/notice about this, but it seems the mail is still in my
draft folder. The global variable handling in the K8 code uses lots of
tricks which were appropriate in v3, but which completely kill v3.

> I would put this on the "let's look at it later" list. It's not going
> to hurt us now if ever.
>   

In theory, if the default serial port is used as GPIOs for something
vital, writing to it could be rather harmful. I'll try to cook up a patch.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Mon Sep  1 17:12:17 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 01 Sep 2008 17:12:17 +0200
Subject: [coreboot] K8 RAMinit problematic code
Message-ID: <48BC0651.6060800@gmx.net>

Hi,

this patch is not to be applied, but an annotation from my tree.

Index: northbridge/amd/k8/dqs.c
===================================================================
--- northbridge/amd/k8/dqs.c	(Revision 853)
+++ northbridge/amd/k8/dqs.c	(Arbeitskopie)
@@ -2001,6 +2001,7 @@
 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
 {
 	if(coreid) return; // only do it on core0
+#error This is broken beyond repair. We need to use the generic global variable infrastructure, especially if we relocate the global variables without telling anybody.
 	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
 	wait_till_sysinfo_in_ram(); // use pci to get it
 
@@ -2012,6 +2013,7 @@
 		sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
 		memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
 	#else
+#error Broken here as well.
 		memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE);
 	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's



Even if the stuff above is fixed, we absolutely have to finish the
concept of accessing global variables by adding locking and/or spelling
out the access rules, especially for the CAR stage.

Oh, and can we please mark struct sys_info as const where possible and
also not pass it around as parameter. Especially if we perform stack
relocation, this can lead to really nasty problems.
Thanks.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Mon Sep  1 17:38:10 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 1 Sep 2008 08:38:10 -0700
Subject: [coreboot] /. effect:
In-Reply-To: <48BBF785.4070500@onelabs.com>
References: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>
	<1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>
	<48BBF785.4070500@onelabs.com>
Message-ID: <13426df10809010838x3b2d8fe4h7ca0deac85bbfc4c@mail.gmail.com>

On Mon, Sep 1, 2008 at 7:09 AM, bari <bari at onelabs.com> wrote:
> Paul Menzel wrote:
>>
>> Does anyone know about which boards they are talking? And have the
>> developers of coreboot experienced any improvement in cooperation?
>>
>
> VIA gave us V2 CAR for C7.
>
> VIA fixed raminit for the CN700 so we can now support all the C7 + CN700 +
> vt8237 boards (about 30- 40 currently in production) in V2 and move them
> into V3.
>
> VIA helped support the vt8237s and KT890 for the a8v-e_se and m2v-mx_se.
>
> VIA posted programming guides for CX700M/VX700 and VX800
> http://linux.via.com.tw/support/downloadFiles.action
>

I think when vendors do this type of thing we should make a Big Deal about it.

This support is well known -- how about a "how vendors are helping"
page? We've got amd and via and silicon mechanics already!

thanks

ron



From rminnich at gmail.com  Mon Sep  1 17:39:25 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 1 Sep 2008 08:39:25 -0700
Subject: [coreboot] K8 RAMinit problematic code
In-Reply-To: <48BC0651.6060800@gmx.net>
References: <48BC0651.6060800@gmx.net>
Message-ID: <13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>

On Mon, Sep 1, 2008 at 8:12 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi,
>
> this patch is not to be applied, but an annotation from my tree.
>
> Index: northbridge/amd/k8/dqs.c
> ===================================================================
> --- northbridge/amd/k8/dqs.c    (Revision 853)
> +++ northbridge/amd/k8/dqs.c    (Arbeitskopie)
> @@ -2001,6 +2001,7 @@
>  static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
>  {
>        if(coreid) return; // only do it on core0
> +#error This is broken beyond repair. We need to use the generic global variable infrastructure, especially if we relocate the global variables without telling anybody.

These fixes come in to play once single core is done.

We're going to write this code as always SMP safe, and I want to
remove the CONFIG_*_SMP conditionals. They make no sense for a bios.

ron



From stepan at coresystems.de  Mon Sep  1 17:51:42 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 01 Sep 2008 17:51:42 +0200
Subject: [coreboot] /. effect:
In-Reply-To: <48BBF785.4070500@onelabs.com>
References: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>	<1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>
	<48BBF785.4070500@onelabs.com>
Message-ID: <48BC0F8E.20106@coresystems.de>

bari wrote:
> Paul Menzel wrote:
>> Does anyone know about which boards they are talking? And have the
>> developers of coreboot experienced any improvement in cooperation?
>>   
>
> VIA gave us V2 CAR for C7.
>
> VIA fixed raminit for the CN700 so we can now support all the C7 +
> CN700 + vt8237 boards (about 30- 40 currently in production) in V2 and
> move them into V3.
>
> VIA helped support the vt8237s and KT890 for the a8v-e_se and m2v-mx_se.
>
> VIA posted programming guides for CX700M/VX700 and VX800
> http://linux.via.com.tw/support/downloadFiles.action

We have been working with VIA to get a CX700 port done long before they
opened that documentation. At the moment the port is sleeping, but only
few things have to be fixed before it can be released. Stay tuned.

I want to take the opportunity to thank VIA for their great help. They
started thinking Open Source a long time before they actually hired
Harald Welte! Way to go!

As a comparison: The fact that Intel is hallowed so much for their Open
Source commitment is a joke, when it comes down to Firmware development.
It has been extremely hard to work with them so far. In fact at this
point I would say they do actively avoid working with us for the
funniest of all reasons. I found comments on Slashdot conspiring how the
great Open Source work on Intel forced VIA into action. If only Intel
would be a small tiny bit as cooperative as VIA was, we would see a vast
amount of Intel systems supported in coreboot today.

Public perception is not always the measure of all things.

Best regards,
Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From stepan at coresystems.de  Mon Sep  1 17:53:54 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 01 Sep 2008 17:53:54 +0200
Subject: [coreboot] [PATCH] libpayload keyboard driver fix.
Message-ID: <48BC1012.9000905@coresystems.de>

See Patch

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From c-d.hailfinger.devel.2006 at gmx.net  Mon Sep  1 19:10:05 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 01 Sep 2008 19:10:05 +0200
Subject: [coreboot] K8 RAMinit problematic code
In-Reply-To: <13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>
References: <48BC0651.6060800@gmx.net>
	<13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>
Message-ID: <48BC21ED.2000400@gmx.net>

On 01.09.2008 17:39, ron minnich wrote:
> On Mon, Sep 1, 2008 at 8:12 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> Hi,
>>
>> this patch is not to be applied, but an annotation from my tree.
>>
>> Index: northbridge/amd/k8/dqs.c
>> ===================================================================
>> --- northbridge/amd/k8/dqs.c    (Revision 853)
>> +++ northbridge/amd/k8/dqs.c    (Arbeitskopie)
>> @@ -2001,6 +2001,7 @@
>>  static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
>>  {
>>        if(coreid) return; // only do it on core0
>> +#error This is broken beyond repair. We need to use the generic global variable infrastructure, especially if we relocate the global variables without telling anybody.
>>     
>
> These fixes come in to play once single core is done.
>   

Sorry, I meant that

struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);

is broken beyond repair. Basically, that code tries to establish a new
location for global variables without telling anyone.

> We're going to write this code as always SMP safe, and I want to
> remove the CONFIG_*_SMP conditionals. They make no sense for a bios.
>   

Interesting point of view. As long as we're allowed to make locking on
pure uniprocessor architectures a no-op, I'm totally for it.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Mon Sep  1 19:28:40 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 01 Sep 2008 19:28:40 +0200
Subject: [coreboot] K8 RAMinit problematic code
In-Reply-To: <13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>
References: <48BC0651.6060800@gmx.net>
	<13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>
Message-ID: <48BC2648.9020406@coresystems.de>

ron minnich wrote:
> These fixes come in to play once single core is done.
>
> We're going to write this code as always SMP safe, and I want to
> remove the CONFIG_*_SMP conditionals. They make no sense for a bios.
>   
So you say a Geode LX bios should know how to do LAPIC, IOAPIC, INIT
IPI, SIPI, and all that stuff?

These conditionals _might_ make sense to save quite some space. Small
machines often have small flash.

Then there's this other thing... Intel Core (2) Duo/Solo/Quad CPUs
expect the BIOS to send the APs back to sleep. K8 does not do this.
Should we assume we (have to) do this anyways? Might make sense, power
consumption wise, if you're running a non-SMP OS on an SMP K8 system.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From stepan at coresystems.de  Mon Sep  1 19:29:51 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 01 Sep 2008 19:29:51 +0200
Subject: [coreboot] K8 RAMinit problematic code
In-Reply-To: <48BC21ED.2000400@gmx.net>
References: <48BC0651.6060800@gmx.net>	<13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>
	<48BC21ED.2000400@gmx.net>
Message-ID: <48BC268F.1050500@coresystems.de>

Carl-Daniel Hailfinger wrote:
> Interesting point of view. As long as we're allowed to make locking on
> pure uniprocessor architectures a no-op, I'm totally for it.
>
>   
The thing is, without those defines, figuring out whether we're SMP or
not is more complex than doing the actual locking.
So we might as well do the locking unconditionally, too.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From bari at onelabs.com  Mon Sep  1 19:33:29 2008
From: bari at onelabs.com (bari)
Date: Mon, 01 Sep 2008 12:33:29 -0500
Subject: [coreboot] /. effect:
In-Reply-To: <13426df10809010838x3b2d8fe4h7ca0deac85bbfc4c@mail.gmail.com>
References: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>	
	<1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>	
	<48BBF785.4070500@onelabs.com>
	<13426df10809010838x3b2d8fe4h7ca0deac85bbfc4c@mail.gmail.com>
Message-ID: <48BC2769.1020504@onelabs.com>

ron minnich wrote:
> I think when vendors do this type of thing we should make a Big Deal about it.
>
> This support is well known -- how about a "how vendors are helping"
> page? We've got amd and via and silicon mechanics already!
>
> thanks
>
> ron
>
>   
Added http://www.coreboot.org/Vendors  to the wiki.

Let the horn blowing begin!

-Bari



From stepan at coresystems.de  Mon Sep  1 19:35:41 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 01 Sep 2008 19:35:41 +0200
Subject: [coreboot] /. effect:
In-Reply-To: <48BC2769.1020504@onelabs.com>
References: <13426df10808312356s43d7b8bq221797cf820a2ac3@mail.gmail.com>		<1220254790.3548.4.camel@mattotaupa.wohnung.familie-menzel.net>		<48BBF785.4070500@onelabs.com>	<13426df10809010838x3b2d8fe4h7ca0deac85bbfc4c@mail.gmail.com>
	<48BC2769.1020504@onelabs.com>
Message-ID: <48BC27ED.9000805@coresystems.de>

bari wrote:
> ron minnich wrote:
>> I think when vendors do this type of thing we should make a Big Deal
>> about it.
>>
>> This support is well known -- how about a "how vendors are helping"
>> page? We've got amd and via and silicon mechanics already!
>>
>> thanks
>>
>> ron
>>
>>   
> Added http://www.coreboot.org/Vendors  to the wiki.
>
> Let the horn blowing begin!
good stuff. I wonder whether we should put Silicon Mechanics on there,
too. They're not a hardware vendor in our sense; so they might better
fit into the "Products" section.

Opinions?

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From rminnich at gmail.com  Mon Sep  1 20:19:15 2008
From: rminnich at gmail.com (ron minnich)
Date: Mon, 1 Sep 2008 11:19:15 -0700
Subject: [coreboot] K8 RAMinit problematic code
In-Reply-To: <48BC21ED.2000400@gmx.net>
References: <48BC0651.6060800@gmx.net>
	<13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>
	<48BC21ED.2000400@gmx.net>
Message-ID: <13426df10809011119x53441141m997007c3abe064fc@mail.gmail.com>

On Mon, Sep 1, 2008 at 10:10 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Sorry, I meant that
>
> struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
>
> is broken beyond repair. Basically, that code tries to establish a new
> location for global variables without telling anyone.

yow! that's supposed to have been gone already! I wonder if a patch got lost.


>
>> We're going to write this code as always SMP safe, and I want to
>> remove the CONFIG_*_SMP conditionals. They make no sense for a bios.
>>
>
> Interesting point of view. As long as we're allowed to make locking on
> pure uniprocessor architectures a no-op, I'm totally for it.
>

yeah, locks on up always succeed and there's no contention :-)

ron



From uwe at hermann-uwe.de  Mon Sep  1 21:22:55 2008
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 1 Sep 2008 21:22:55 +0200
Subject: [coreboot] [PATCH] libpayload keyboard driver fix.
In-Reply-To: <48BC1012.9000905@coresystems.de>
References: <48BC1012.9000905@coresystems.de>
Message-ID: <20080901192255.GA7388@greenwood>

On Mon, Sep 01, 2008 at 05:53:54PM +0200, Stefan Reinauer wrote:
> fix keyboard driver bugs.

Jordan is probably better-suited to review this, but can you elaborate
a bit more in the commit message? What bug, what's wrong, what effects does
the bug have, how is it fixed, etc?


> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> 
> Index: libpayload/drivers/keyboard.c
> ===================================================================
> --- libpayload/drivers/keyboard.c	(revision 3556)
> +++ libpayload/drivers/keyboard.c	(working copy)
> @@ -79,7 +79,7 @@
>  
>  int keyboard_getchar(void)
>  {
> -	static int modifier;
> +	static int modifier = 0;
>  	unsigned char ch;
>  	int shift;
>  	int ret = 0;
> @@ -91,17 +91,17 @@
>  	switch (ch) {
>  	case 0x36:
>  	case 0x2a:
> -		modifier &= ~MOD_SHIFT;
> +		modifier |= MOD_SHIFT;
>  		break;
>  	case 0x80 | 0x36:
>  	case 0x80 | 0x2a:
> -		modifier |= MOD_SHIFT;
> +		modifier &= ~MOD_SHIFT;
>  		break;
>  	case 0x1d:
> -		modifier &= ~MOD_CTRL;
> +		modifier |= MOD_CTRL;
>  		break;
>  	case 0x80 | 0x1d:
> -		modifier |= MOD_CTRL;
> +		modifier &= ~MOD_CTRL;
>  		break;
>  	case 0x3a:
>  		if (modifier & MOD_CAPSLOCK)


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From patrick at georgi-clan.de  Mon Sep  1 21:29:57 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 01 Sep 2008 21:29:57 +0200
Subject: [coreboot] [PATCH] libpayload keyboard driver fix.
In-Reply-To: <20080901192255.GA7388@greenwood>
References: <48BC1012.9000905@coresystems.de> <20080901192255.GA7388@greenwood>
Message-ID: <48BC42B5.2050908@georgi-clan.de>

Uwe Hermann schrieb:
> On Mon, Sep 01, 2008 at 05:53:54PM +0200, Stefan Reinauer wrote:
>   
>> fix keyboard driver bugs.
>>     
>
> Jordan is probably better-suited to review this, but can you elaborate
> a bit more in the commit message? What bug, what's wrong, what effects does
> the bug have, how is it fixed, etc?
>   

The |0x80 codes are "break codes", that means, codes that are emitted
when the key transitions from pressed to non-pressed, so the modifier
was always in the wrong state, as soon as you pressed shift for the
first time.

I have no idea why that didn't occur to me when I looked at it earlier
today :-/

Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>
>
>   
>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>
>> Index: libpayload/drivers/keyboard.c
>> ===================================================================
>> --- libpayload/drivers/keyboard.c	(revision 3556)
>> +++ libpayload/drivers/keyboard.c	(working copy)
>> @@ -79,7 +79,7 @@
>>  
>>  int keyboard_getchar(void)
>>  {
>> -	static int modifier;
>> +	static int modifier = 0;
>>  	unsigned char ch;
>>  	int shift;
>>  	int ret = 0;
>> @@ -91,17 +91,17 @@
>>  	switch (ch) {
>>  	case 0x36:
>>  	case 0x2a:
>> -		modifier &= ~MOD_SHIFT;
>> +		modifier |= MOD_SHIFT;
>>  		break;
>>  	case 0x80 | 0x36:
>>  	case 0x80 | 0x2a:
>> -		modifier |= MOD_SHIFT;
>> +		modifier &= ~MOD_SHIFT;
>>  		break;
>>  	case 0x1d:
>> -		modifier &= ~MOD_CTRL;
>> +		modifier |= MOD_CTRL;
>>  		break;
>>  	case 0x80 | 0x1d:
>> -		modifier |= MOD_CTRL;
>> +		modifier &= ~MOD_CTRL;
>>  		break;
>>  	case 0x3a:
>>  		if (modifier & MOD_CAPSLOCK)
>>     




From cristi.magherusan at net.utcluj.ro  Mon Sep  1 22:42:44 2008
From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Mon, 01 Sep 2008 23:42:44 +0300
Subject: [coreboot] AVATT Got signal !!!
In-Reply-To: <48BACCD1.5010405@sandia.gov>
References: <13426df10808250821l5a5e7a29v3e59177ff8175541@mail.gmail.com>
	<1219956750.6804.4.camel@localhost>
	<13426df10808281415t1bde6a69xc7049b9b6b629fe0@mail.gmail.com>
	<13426df10808281418y3b62d110l86261dbbf7cb499c@mail.gmail.com>
	<1219964286.22197.1.camel@kiwi> <48B78CF8.1080505@sandia.gov>
	<13426df10808291206h7e266b18v172c6d5a7640432a@mail.gmail.com>
	<48B887BD.9060508@sandia.gov>
	<13426df10808292023n1054f79t7a377f70f9c467c@mail.gmail.com>
	<1220070513.14143.9.camel@localhost>
	<13426df10808292133g74dfc708r874363b284ec4ddb@mail.gmail.com>
	<1220072069.14143.13.camel@localhost> <48BA1F37.9010905@sandia.gov>
	<1220171194.13260.10.camel@localhost>  <48BACCD1.5010405@sandia.gov>
Message-ID: <1220301765.24455.13.camel@localhost>

Hello,

I have great news! I just found out that AVATT is working!!!

The latest kvm version has a CFLAG --disable-nptl. I disabled it
yesterday in
http://repo.or.cz/w/kvm-coreboot.git?a=commitdiff;h=910b66268ed5a7a72a57a1b259f7b6982e440c41
and recompiled kvm, but I haven't tested it at that time to see whether
it works or not.

Today I did it, and it seems that OpenBSD's livecd is starting, but
unfortunatelly it crashes after a while. So does NetBSD's, but it's a
huge progress. See the images at
http://panzer.utcluj.ro/~alien/coreboot/AVATT/screenshots/running/

Best regards,
Cristi.

-- 
Ing. Cristi M?gheru?an,
Universitatea Tehnic? din Cluj-Napoca
Centrul de Comunica?ii "Pusztai Kalman"
Tel. 0264/401247  http://cc.utcluj.ro




From mats.andersson at gisladisker.se  Tue Sep  2 00:13:43 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Tue, 02 Sep 2008 00:13:43 +0200
Subject: [coreboot] Using only one romcc copy
Message-ID: <E1KaHeZ-0006E1-I7@aun.bellman.mea>

Hello all,

I submit here a little utility that slightly rebuilds the python
generated makefiles

	targets/*/*/Makefile
	targets/*/*/normal/Makefile
	targets/*/*/fallback/Makefile

in order to use a common copy of romcc, and to leave this compiler
until 'make build-clean' is issued. If the result is to peoples
liking, the corresponding changes should be implemented in the
master copies used by 'buildtargets'.

The rebuild is conducted any time after 'buildtargets' and
is as easy as

# reduce.sh targets/msi/ms6147/ms6147


Best regards

Mats Erik Andersson

---

#!/bin/sh
#
# A rebuild tool for three makefiles, that reduces some idiosyncracies of
# the build system regarding the romcc compiler.
#
if [ -z "$1" ];then
	echo "A target directory is mandatory. Aborting."
	exit 1
fi

if [ ! -s "$1/Makefile" ]; then
	echo "Wrong directory, or \"Makefile\" is missing."
	exit 1
fi

# Move the executable romcc copy to parent directory in all targets,
# dependencies, and build rules.
sed -i 's|\.\+/romcc|\.\./romcc|' $1/normal/Makefile
sed -i 's|\.\+/romcc|\.\./romcc|' $1/fallback/Makefile

# Introduce, if necessary, a new target that removes the common romcc.
if grep -q '^build-clean' $1/Makefile
then
	:
else
	sed -i '/^clean/ i\
build-clean:\tclean\
\t-rm romcc\

;' $1/Makefile

fi



From joe at settoplinux.org  Tue Sep  2 00:19:39 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Mon, 01 Sep 2008 18:19:39 -0400
Subject: [coreboot] AVATT Got signal !!!
In-Reply-To: <1220301765.24455.13.camel@localhost>
References: <13426df10808250821l5a5e7a29v3e59177ff8175541@mail.gmail.com>
	<1219956750.6804.4.camel@localhost>
	<13426df10808281415t1bde6a69xc7049b9b6b629fe0@mail.gmail.com>
	<13426df10808281418y3b62d110l86261dbbf7cb499c@mail.gmail.com>
	<1219964286.22197.1.camel@kiwi> <48B78CF8.1080505@sandia.gov>
	<13426df10808291206h7e266b18v172c6d5a7640432a@mail.gmail.com>
	<48B887BD.9060508@sandia.gov>
	<13426df10808292023n1054f79t7a377f70f9c467c@mail.gmail.com>
	<1220070513.14143.9.camel@localhost>
	<13426df10808292133g74dfc708r874363b284ec4ddb@mail.gmail.com>
	<1220072069.14143.13.camel@localhost> <48BA1F37.9010905@sandia.gov>
	<1220171194.13260.10.camel@localhost> <48BACCD1.5010405@sandia.gov>
	<1220301765.24455.13.camel@localhost>
Message-ID: <1f7eaa3cc6bda0f00181003a087ee06c@imap.1and1.com>




On Mon, 01 Sep 2008 23:42:44 +0300, Cristi Magherusan
<cristi.magherusan at net.utcluj.ro> wrote:
> Hello,
> 
> I have great news! I just found out that AVATT is working!!!
> 
> The latest kvm version has a CFLAG --disable-nptl. I disabled it
> yesterday in
>
http://repo.or.cz/w/kvm-coreboot.git?a=commitdiff;h=910b66268ed5a7a72a57a1b259f7b6982e440c41
> and recompiled kvm, but I haven't tested it at that time to see whether
> it works or not.
> 
> Today I did it, and it seems that OpenBSD's livecd is starting, but
> unfortunatelly it crashes after a while. So does NetBSD's, but it's a
> huge progress. See the images at
> http://panzer.utcluj.ro/~alien/coreboot/AVATT/screenshots/running/
> 

Exellent news Cristi:-)
Have you tried any Linux Distros yet?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Tue Sep  2 00:39:18 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Sep 2008 00:39:18 +0200
Subject: [coreboot] Using only one romcc copy
In-Reply-To: <E1KaHeZ-0006E1-I7@aun.bellman.mea>
References: <E1KaHeZ-0006E1-I7@aun.bellman.mea>
Message-ID: <48BC6F16.8000309@gmx.net>

Hi Mats,

nice work.

On 02.09.2008 00:13, Mats Erik Andersson wrote:
> I submit here a little utility that slightly rebuilds the python
> generated makefiles
>
> 	targets/*/*/Makefile
> 	targets/*/*/normal/Makefile
> 	targets/*/*/fallback/Makefile
>
> in order to use a common copy of romcc, and to leave this compiler
> until 'make build-clean' is issued. If the result is to peoples
> liking, the corresponding changes should be implemented in the
> master copies used by 'buildtargets'.
>   

Have you measured the speedup for this? Is it noticeable?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From cristi.magherusan at net.utcluj.ro  Tue Sep  2 00:56:08 2008
From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Tue, 02 Sep 2008 01:56:08 +0300
Subject: [coreboot] AVATT got false alarm
In-Reply-To: <1f7eaa3cc6bda0f00181003a087ee06c@imap.1and1.com>
References: <13426df10808250821l5a5e7a29v3e59177ff8175541@mail.gmail.com>
	<1219956750.6804.4.camel@localhost>
	<13426df10808281415t1bde6a69xc7049b9b6b629fe0@mail.gmail.com>
	<13426df10808281418y3b62d110l86261dbbf7cb499c@mail.gmail.com>
	<1219964286.22197.1.camel@kiwi> <48B78CF8.1080505@sandia.gov>
	<13426df10808291206h7e266b18v172c6d5a7640432a@mail.gmail.com>
	<48B887BD.9060508@sandia.gov>
	<13426df10808292023n1054f79t7a377f70f9c467c@mail.gmail.com>
	<1220070513.14143.9.camel@localhost>
	<13426df10808292133g74dfc708r874363b284ec4ddb@mail.gmail.com>
	<1220072069.14143.13.camel@localhost> <48BA1F37.9010905@sandia.gov>
	<1220171194.13260.10.camel@localhost> <48BACCD1.5010405@sandia.gov>
	<1220301765.24455.13.camel@localhost>
	<1f7eaa3cc6bda0f00181003a087ee06c@imap.1and1.com>
Message-ID: <1220309768.7332.13.camel@localhost>

Hello,

On Mon, 2008-09-01 at 18:19 -0400, Joseph Smith wrote:
> Exellent news Cristi:-)
> Have you tried any Linux Distros yet?

Sorry, but it turned out that it was a false alarm. 

I ran by mistake qemu in 32bit mode and this way kvm from inside it was
running as plain qemu, because it was missing the virtualization
instructions available only if the hosting qemu emulates 64bit CPUs.

Plain qemu should work, since the TLS stuff is used inside kvm only in
the libkvm code which is skipped if those instructions are missing. 

Anyway, the fact that kvm worked this way and didn't crash at startup
confirmed once again that TLS is the missing piece and makes me even
more motivated to get it done.

Best regards,
Cristi

-- 
Ing. Cristi M?gheru?an,
Universitatea Tehnic? din Cluj-Napoca
Centrul de Comunica?ii "Pusztai Kalman"
Tel. 0264/401247  http://cc.utcluj.ro
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From c-d.hailfinger.devel.2006 at gmx.net  Tue Sep  2 01:51:56 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 02 Sep 2008 01:51:56 +0200
Subject: [coreboot] K8 RAMinit problematic code
In-Reply-To: <13426df10809011119x53441141m997007c3abe064fc@mail.gmail.com>
References: <48BC0651.6060800@gmx.net>	<13426df10809010839x306abcd3i4774436b63d6e3a7@mail.gmail.com>	<48BC21ED.2000400@gmx.net>
	<13426df10809011119x53441141m997007c3abe064fc@mail.gmail.com>
Message-ID: <48BC801C.3040003@gmx.net>

On 01.09.2008 20:19, ron minnich wrote:
> On Mon, Sep 1, 2008 at 10:10 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>
>   
>> Sorry, I meant that
>>
>> struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
>>
>> is broken beyond repair. Basically, that code tries to establish a new
>> location for global variables without telling anyone.
>>     
>
> yow! that's supposed to have been gone already! I wonder if a patch got lost.
>   

Can you repost your remaining diff? I'll try to review ASAP.

>>> We're going to write this code as always SMP safe, and I want to
>>> remove the CONFIG_*_SMP conditionals. They make no sense for a bios.
>>>
>>>       
>> Interesting point of view. As long as we're allowed to make locking on
>> pure uniprocessor architectures a no-op, I'm totally for it.
>>     
>
> yeah, locks on up always succeed and there's no contention :-)
>   

I had a redefinition of the lock functions in mind because some
architectures may not have any fast/easy locking instructions.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Tue Sep  2 02:26:11 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  2 Sep 2008 02:26:11 +0200
Subject: [coreboot] r3557 - trunk/util/flashrom
Message-ID: <mailman.2016.1355071372.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-09-02 02:26:11 +0200 (Tue, 02 Sep 2008)
New Revision: 3557

Modified:
   trunk/util/flashrom/flashchips.c
Log:
flashrom: SST49LF016C TEST_OK_ PROBE READ ERASE WRITE

Per test report from Bari Ari. Thanks!

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/util/flashrom/flashchips.c
===================================================================
--- trunk/util/flashrom/flashchips.c	2008-09-01 01:48:07 UTC (rev 3556)
+++ trunk/util/flashrom/flashchips.c	2008-09-02 00:26:11 UTC (rev 3557)
@@ -88,7 +88,7 @@
 	{"SST",		"SST49LF004C",		SST_ID,		SST_49LF004C,		512,	4 * 1024,	TEST_UNTESTED,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
 	{"SST",		"SST49LF008A",		SST_ID,		SST_49LF008A,		1024,	64 * 1024,	TEST_OK_PREW,	probe_sst_fwhub,	erase_sst_fwhub,		write_sst_fwhub},
 	{"SST",		"SST49LF008C",		SST_ID,		SST_49LF008C,		1024,	4 * 1024,	TEST_UNTESTED,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
-	{"SST",		"SST49LF016C",		SST_ID,		SST_49LF016C,		2048,	4 * 1024,	TEST_UNTESTED,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
+	{"SST",		"SST49LF016C",		SST_ID,		SST_49LF016C,		2048,	4 * 1024,	TEST_OK_PREW,	probe_49lfxxxc,		erase_49lfxxxc,			write_49lfxxxc},
 	{"SST",		"SST49LF020A",		SST_ID,		SST_49LF020A,		256,	16 * 1024,	TEST_UNTESTED,	probe_jedec,		erase_49lf040,			write_49lf040},
 	{"SST",		"SST49LF040",		SST_ID,		SST_49LF040,		512,	4096,		TEST_OK_PREW,	probe_jedec,		erase_49lf040,			write_49lf040},
 	{"SST",		"SST49LF040B",		SST_ID,		SST_49LF040B,		512,	64 * 1024,	TEST_OK_PREW,	probe_sst_fwhub,	erase_sst_fwhub,		write_sst_fwhub},




From patrick at georgi-clan.de  Tue Sep  2 11:06:32 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 02 Sep 2008 11:06:32 +0200
Subject: [coreboot] [PATCH]libpayload: USB stack
Message-ID: <48BD0218.8000605@georgi-clan.de>

Hi there,

This patch adds USB capabilities to libpayload. It requires some
memalign implementation (eg. the one I sent yesterday).
Features:
 - UHCI controller driver
 - UHCI root hub driver
 - USB MSC (Mass Storage Class) driver
 - skeleton of a USB HID driver (requires better interrupt transfer
handling, which is TODO)
 - skeleton of a USB hub driver (needs several blank spots filled in,
eg. power management. Again: TODO)

OHCI and EHCI are not supported, though OHCI support should be rather
easy as the stack provides reasonable abstractions (or so I hope). EHCI
will probably be more complicated.
Isochronous transfers (eg. webcams, audio stuff, ...) are not supported
- they can be, but I doubt we'll have a reason for that in the boot
environment.

The MSC driver was tested against a couple of USB flash drives, and
should be reasonably tolerant by now. Though I probably underestimate
the amount of bugs present in USB flash drives, so feedback is welcome.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Regards,
Patrick Georgi
-------------- next part --------------
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From svn at coreboot.org  Tue Sep  2 11:35:44 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  2 Sep 2008 11:35:44 +0200
Subject: [coreboot] r3558 - trunk/payloads/libpayload/drivers
Message-ID: <mailman.2017.1355071373.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-09-02 11:35:43 +0200 (Tue, 02 Sep 2008)
New Revision: 3558

Modified:
   trunk/payloads/libpayload/drivers/keyboard.c
Log:
The keyboard driver mixed up the key press/release events for the
special keys.

Patrick Georgi explained:
The |0x80 codes are "break codes", that means, codes that are emitted
when the key transitions from pressed to non-pressed, so the modifier
was always in the wrong state, as soon as you pressed shift for the
first time.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/payloads/libpayload/drivers/keyboard.c
===================================================================
--- trunk/payloads/libpayload/drivers/keyboard.c	2008-09-02 00:26:11 UTC (rev 3557)
+++ trunk/payloads/libpayload/drivers/keyboard.c	2008-09-02 09:35:43 UTC (rev 3558)
@@ -79,7 +79,7 @@
 
 int keyboard_getchar(void)
 {
-	static int modifier;
+	static int modifier = 0;
 	unsigned char ch;
 	int shift;
 	int ret = 0;
@@ -91,17 +91,17 @@
 	switch (ch) {
 	case 0x36:
 	case 0x2a:
-		modifier &= ~MOD_SHIFT;
+		modifier |= MOD_SHIFT;
 		break;
 	case 0x80 | 0x36:
 	case 0x80 | 0x2a:
-		modifier |= MOD_SHIFT;
+		modifier &= ~MOD_SHIFT;
 		break;
 	case 0x1d:
-		modifier &= ~MOD_CTRL;
+		modifier |= MOD_CTRL;
 		break;
 	case 0x80 | 0x1d:
-		modifier |= MOD_CTRL;
+		modifier &= ~MOD_CTRL;
 		break;
 	case 0x3a:
 		if (modifier & MOD_CAPSLOCK)




From jordan.crouse at amd.com  Tue Sep  2 16:50:02 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 2 Sep 2008 08:50:02 -0600
Subject: [coreboot] libpayload: memalign, take 2
In-Reply-To: <48BBEDF1.6030903@georgi-clan.de>
References: <48BBEDF1.6030903@georgi-clan.de>
Message-ID: <20080902145002.GE15026@cosmic.amd.com>

On 01/09/08 15:28 +0200, Patrick Georgi wrote:
> Hi there,
> 
> after the discussion on the list about memalign, I wrote version that's
> better integrated with the other memory management stuff, and doesn't
> come with its own pool allocator.
> 
> 
> Regards,
> Patrick Georgi

> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Jordan Crouse <jordan.crouse at amd.com>

We need to get this in there. But I promise that that damn malloc()
engine is going to get gutted soon, because it constantly makes 
my eyes hurt when see it.

Patrick - if you get a chance, can you submit a short doxygen comment
for memalign?  I know the rest of the file isn't documented yet, but
we need to start getting into the habit of documenting external 
functions.

Jordan

> Index: include/libpayload.h
> ===================================================================
> --- include/libpayload.h	(revision 3536)
> +++ include/libpayload.h	(working copy)
> @@ -164,6 +164,7 @@
>  void *malloc(size_t size);
>  void *calloc(size_t nmemb, size_t size);
>  void *realloc(void *ptr, size_t size);
> +void *memalign(size_t align, size_t size);
>  
>  /* libc/exec.c */
>  int exec(long addr, int argc, char **argv);
> Index: libc/malloc.c
> ===================================================================
> --- libc/malloc.c	(revision 3536)
> +++ libc/malloc.c	(working copy)
> @@ -72,7 +72,7 @@
>  	*((hdrtype_t *) hstart) = FREE_BLOCK(size);
>  }
>  
> -static void *alloc(int len)
> +static void *alloc(int len, int align)
>  {
>  	hdrtype_t header;
>  	void *ptr = hstart;
> @@ -92,13 +92,20 @@
>  		header = *((hdrtype_t *) ptr);
>  		int size = SIZE(header);
>  
> -		if (!HAS_MAGIC(header) || size == 0) {
> +		if (!HAS_MAGIC(header)) {
>  			printf("memory allocator panic.\n");
>  			halt();
>  		}
>  
>  		if (header & FLAG_FREE) {
> -			if (len <= size) {
> +			int realaddr = (int)(ptr + HDRSIZE);
> +			int overhead = ((realaddr+align-1) & ~(align-1)) - realaddr;
> +			if (len + overhead <= size) {
> +				if (overhead != 0) {
> +					*((hdrtype_t *) ptr) = FREE_BLOCK(overhead - HDRSIZE);
> +					ptr += overhead;
> +					size -= overhead;
> +				}
>  				void *nptr = ptr + (HDRSIZE + len);
>  				int nsize = size - (HDRSIZE + len);
>  
> @@ -186,13 +193,13 @@
>  
>  void *malloc(size_t size)
>  {
> -	return alloc(size);
> +	return alloc(size, 1);
>  }
>  
>  void *calloc(size_t nmemb, size_t size)
>  {
>  	size_t total = nmemb * size;
> -	void *ptr = alloc(total);
> +	void *ptr = alloc(total, 1);
>  
>  	if (ptr)
>  		memset(ptr, 0, total);
> @@ -206,7 +213,7 @@
>  	unsigned int osize;
>  
>  	if (ptr == NULL)
> -		return alloc(size);
> +		return alloc(size, 1);
>  
>  	pptr = ptr - HDRSIZE;
>  
> @@ -222,7 +229,7 @@
>  	 * reallocated the new space.
>  	 */
>  	free(ptr);
> -	ret = alloc(size);
> +	ret = alloc(size, 1);
>  
>  	/*
>  	 * if ret == NULL, then doh - failure.
> @@ -237,6 +244,11 @@
>  	return ret;
>  }
>  
> +void *memalign(size_t align, size_t size)
> +{
> +	return alloc(size, align);
> +}
> +
>  /* This is for debugging purposes. */
>  #ifdef TEST
>  void print_malloc_map(void)

> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From jordan.crouse at amd.com  Tue Sep  2 16:58:58 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 2 Sep 2008 08:58:58 -0600
Subject: [coreboot] libpayload keyboard driver fix.
In-Reply-To: <48BC42B5.2050908@georgi-clan.de>
References: <48BC1012.9000905@coresystems.de> <20080901192255.GA7388@greenwood>
	<48BC42B5.2050908@georgi-clan.de>
Message-ID: <20080902145858.GF15026@cosmic.amd.com>

On 01/09/08 21:29 +0200, Patrick Georgi wrote:
> Uwe Hermann schrieb:
> > On Mon, Sep 01, 2008 at 05:53:54PM +0200, Stefan Reinauer wrote:
> >   
> >> fix keyboard driver bugs.
> >>     
> >
> > Jordan is probably better-suited to review this, but can you elaborate
> > a bit more in the commit message? What bug, what's wrong, what effects does
> > the bug have, how is it fixed, etc?
> >   
> 
> The |0x80 codes are "break codes", that means, codes that are emitted
> when the key transitions from pressed to non-pressed, so the modifier
> was always in the wrong state, as soon as you pressed shift for the
> first time.
> 
> I have no idea why that didn't occur to me when I looked at it earlier
> today :-/
> 
> Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Thats right - I hosed up that state machine and never noticed it because
we have never had any payloads that used special keys to any degree.

Also acked by me.

Jordan




From jordan.crouse at amd.com  Tue Sep  2 17:03:20 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Tue, 2 Sep 2008 09:03:20 -0600
Subject: [coreboot] libpayload: USB stack
In-Reply-To: <48BD0218.8000605@georgi-clan.de>
References: <48BD0218.8000605@georgi-clan.de>
Message-ID: <20080902150320.GG15026@cosmic.amd.com>

On 02/09/08 11:06 +0200, Patrick Georgi wrote:
> Hi there,
> 
> This patch adds USB capabilities to libpayload. It requires some
> memalign implementation (eg. the one I sent yesterday).
> Features:
>  - UHCI controller driver
>  - UHCI root hub driver
>  - USB MSC (Mass Storage Class) driver
>  - skeleton of a USB HID driver (requires better interrupt transfer
> handling, which is TODO)
>  - skeleton of a USB hub driver (needs several blank spots filled in,
> eg. power management. Again: TODO)
> 
> OHCI and EHCI are not supported, though OHCI support should be rather
> easy as the stack provides reasonable abstractions (or so I hope). EHCI
> will probably be more complicated.
> Isochronous transfers (eg. webcams, audio stuff, ...) are not supported
> - they can be, but I doubt we'll have a reason for that in the boot
> environment.
> 
> The MSC driver was tested against a couple of USB flash drives, and
> should be reasonably tolerant by now. Though I probably underestimate
> the amount of bugs present in USB flash drives, so feedback is welcome.

> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>

Lets get this in and then we can hack on it from there.
As with the previous patch, if you can document the external
(payload visible) functions, that would help a lot.

Now all we need is the one true USB 1.1 interface (OHCI, natch!). :)

> Index: Config.in
> ===================================================================
> --- Config.in	(revision 3557)
> +++ Config.in	(working copy)
> @@ -132,5 +132,46 @@
>  	bool "Support for PC speaker"
>  	default y
>  
> +config USB
> +	bool "USB Support"
> +	default n
> +
> +config USB_UHCI
> +	bool "Support for USB UHCI controllers"
> +	depends on USB
> +	help
> +	  Select this option if you are going to use USB 1.1 on an Intel based
> +	  system.
> +
> +config USB_OHCI
> +	bool "Support for USB OHCI controllers"
> +	depends on USB
> +	help
> +	  Select this option if you are going to use USB 1.1 on an AMD based
> +	  system.
> +	  NOTE: This option is not (fully) implemented yet
> +
> +config USB_EHCI
> +	bool "Support for USB EHCI controllers"
> +	depends on USB
> +	help
> +	  Select this option if you want to use USB 2.0
> +	  NOTE: This option is not (fully) implemented yet
> +
> +config USB_HID
> +	bool "Support for USB keyboards (broken)"
> +	depends on USB
> +	default n
> +
> +config USB_HUB
> +	bool "Support for USB hubs (broken)"
> +	depends on USB
> +	default n
> +
> +config USB_MSC
> +	bool "Support for USB storage"
> +	depends on USB
> +
> +
>  endmenu
>  
> Index: Makefile
> ===================================================================
> --- Makefile	(revision 3557)
> +++ Makefile	(working copy)
> @@ -137,6 +137,7 @@
>  prepare:
>  	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
>  	$(Q)mkdir -p $(obj)/crypto $(obj)/curses $(obj)/drivers/video
> +	$(Q)mkdir -p $(obj)/drivers/usb
>  	$(Q)mkdir -p $(obj)/i386 $(obj)/lib/$(ARCHDIR-y) $(obj)/libc 
>  	$(Q)mkdir -p $(src)/lib/$(ARCHDIR-y)
>  
> Index: drivers/Makefile.inc
> ===================================================================
> --- drivers/Makefile.inc	(revision 3557)
> +++ drivers/Makefile.inc	(working copy)
> @@ -47,3 +47,14 @@
>  # Geode console drivers
>  TARGETS-$(CONFIG_GEODE_VIDEO_CONSOLE) += drivers/video/geode.o
>  TARGETS-$(CONFIG_GEODE_VIDEO_CONSOLE) += drivers/video/font8x16.o
> +
> +# USB stack
> +TARGETS-$(CONFIG_USB) += drivers/usb/usbinit.o
> +TARGETS-$(CONFIG_USB) += drivers/usb/usb.o
> +TARGETS-$(CONFIG_USB) += drivers/usb/usb_dev.o
> +TARGETS-$(CONFIG_USB_HUB) += drivers/usb/usbhub.o
> +TARGETS-$(CONFIG_USB_UHCI) += drivers/usb/uhci.o
> +TARGETS-$(CONFIG_USB_UHCI) += drivers/usb/uhci_rh.o
> +TARGETS-$(CONFIG_USB_HID) += drivers/usb/usbhid.o
> +TARGETS-$(CONFIG_USB_MSC) += drivers/usb/usbmsc.o
> +
> Index: drivers/usb/usb.h
> ===================================================================
> --- drivers/usb/usb.h	(revision 0)
> +++ drivers/usb/usb.h	(revision 0)
> @@ -0,0 +1,224 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#ifndef __USB_H
> +#define __USB_H
> +#include <libpayload.h>
> +#include <pci.h>
> +
> +typedef enum { host_to_device = 0, device_to_host = 1 } dev_req_dir;
> +typedef enum { standard_type = 0, class_type = 1, vendor_type =
> +		2, reserved_type = 3
> +} dev_req_type;
> +typedef enum { dev_recp = 0, iface_recp = 1, endp_recp = 2, other_recp = 3
> +} dev_req_recp;
> +
> +typedef enum {
> +	GET_STATUS = 0,
> +	CLEAR_FEATURE = 1,
> +	SET_FEATURE = 3,
> +	SET_ADDRESS = 5,
> +	GET_DESCRIPTOR = 6,
> +	SET_DESCRIPTOR = 7,
> +	GET_CONFIGURATION = 8,
> +	SET_CONFIGURATION = 9,
> +	GET_INTERFACE = 10,
> +	SET_INTERFACE = 11,
> +	SYNCH_FRAME = 12
> +} bRequest_Codes;
> +
> +typedef enum {
> +	ENDPOINT_HALT = 0,
> +	DEVICE_REMOTE_WAKEUP = 1,
> +	TEST_MODE = 2
> +} feature_selectors;
> +
> +typedef struct {
> +	union {
> +		struct {
> +			dev_req_recp req_recp:5;
> +			dev_req_type req_type:2;
> +			dev_req_dir data_dir:1;
> +		} __attribute__ ((packed));
> +		unsigned char bmRequestType;
> +	} __attribute__ ((packed));
> +	unsigned char bRequest;
> +	unsigned short wValue;
> +	unsigned short wIndex;
> +	unsigned short wLength;
> +} __attribute__ ((packed)) dev_req_t;
> +
> +struct usbdev_hc;
> +typedef struct usbdev_hc hci_t;
> +
> +struct usbdev;
> +typedef struct usbdev usbdev_t;
> +
> +typedef enum { SETUP = 0x2d, IN = 0x69, OUT = 0xe1 } pid_t;
> +typedef enum { CONTROL = 0, ISOCHRONOUS = 1, BULK = 2, INTERRUPT = 3
> +} endpoint_type;
> +
> +typedef struct {
> +	usbdev_t *dev;
> +	int endpoint;
> +	pid_t direction;
> +	int toggle;
> +	int maxpacketsize;
> +	endpoint_type type;
> +} endpoint_t;
> +
> +
> +struct usbdev {
> +	hci_t *controller;
> +	endpoint_t endpoints[32];
> +	int num_endp;
> +	int address;		// usb address
> +	int hub;		// hub, device is attached to
> +	int port;		// port where device is attached
> +	int lowspeed;		// 1 if lowspeed device
> +	void *data;
> +	u8 *descriptor;
> +	u8 *configuration;
> +	void (*init) (usbdev_t *dev);
> +	void (*destroy) (usbdev_t *dev);
> +	void (*poll) (usbdev_t *dev);
> +};
> +
> +struct usbdev_hc {
> +	struct usbdev_hc *next;
> +	pcidev_t bus_address;
> +	u32 reg_base;
> +	usbdev_t devices[128];	// dev 0 is root hub, 127 is last addressable
> +	void (*start) (hci_t *controller);
> +	void (*stop) (hci_t *controller);
> +	void (*reset) (hci_t *controller);
> +	void (*shutdown) (hci_t *controller);
> +	int (*packet) (usbdev_t *dev, int endp, int pid, int toggle,
> +		       int length, u8 *data);
> +	int (*bulk) (endpoint_t *ep, int size, u8 *data, int finalize);
> +	int (*control) (usbdev_t *dev, pid_t pid, int dr_length,
> +			void *devreq, int data_length, u8 *data);
> +	void *instance;
> +};
> +
> +typedef struct {
> +	unsigned char bDescLength;
> +	unsigned char bDescriptorType;
> +	unsigned char bNbrPorts;
> +	union {
> +		struct {
> +			unsigned long logicalPowerSwitchingMode:2;
> +			unsigned long isCompoundDevice:1;
> +			unsigned long overcurrentProtectionMode:2;
> +			unsigned long ttThinkTime:2;
> +			unsigned long arePortIndicatorsSupported:1;
> +			unsigned long:8;
> +		} __attribute__ ((packed));
> +		unsigned short wHubCharacteristics;
> +	} __attribute__ ((packed));
> +	unsigned char bPowerOn2PwrGood;
> +	unsigned char bHubContrCurrent;
> +	char DeviceRemovable[];
> +} __attribute__ ((packed)) hub_descriptor_t;
> +
> +typedef struct {
> +	unsigned char bLength;
> +	unsigned char bDescriptorType;
> +	unsigned short bcdUSB;
> +	unsigned char bDeviceClass;
> +	unsigned char bDeviceSubClass;
> +	unsigned char bDeviceProtocol;
> +	unsigned char bMaxPacketSize0;
> +	unsigned short idVendor;
> +	unsigned short idProduct;
> +	unsigned short bcdDevice;
> +	unsigned char iManufacturer;
> +	unsigned char iProduct;
> +	unsigned char iSerialNumber;
> +	unsigned char bNumConfigurations;
> +} __attribute__ ((packed)) device_descriptor_t;
> +
> +typedef struct {
> +	unsigned char bLength;
> +	unsigned char bDescriptorType;
> +	unsigned short wTotalLength;
> +	unsigned char bNumInterfaces;
> +	unsigned char bConfigurationValue;
> +	unsigned char iConfiguration;
> +	unsigned char bmAttributes;
> +	unsigned char bMaxPower;
> +} __attribute__ ((packed)) configuration_descriptor_t;
> +
> +typedef struct {
> +	unsigned char bLength;
> +	unsigned char bDescriptorType;
> +	unsigned char bInterfaceNumber;
> +	unsigned char bAlternateSetting;
> +	unsigned char bNumEndpoints;
> +	unsigned char bInterfaceClass;
> +	unsigned char bInterfaceSubClass;
> +	unsigned char bInterfaceProtocol;
> +	unsigned char iInterface;
> +} __attribute__ ((packed)) interface_descriptor_t;
> +
> +typedef struct {
> +	unsigned char bLength;
> +	unsigned char bDescriptorType;
> +	unsigned char bEndpointAddress;
> +	unsigned char bmAttributes;
> +	unsigned short wMaxPacketSize;
> +	unsigned char bInterval;
> +} __attribute__ ((packed)) endpoint_descriptor_t;
> +
> +hci_t *new_controller (void);
> +void detach_controller (hci_t *controller);
> +void usb_poll (void);
> +void init_device_entry (hci_t *controller, int num);
> +
> +void set_feature (usbdev_t *dev, int endp, int feature, int rtype);
> +void get_status (usbdev_t *dev, int endp, int rtype, int len, void *data);
> +int clear_stall (endpoint_t *ep);
> +
> +void usb_nop_init (usbdev_t *dev);
> +void usb_hub_init (usbdev_t *dev);
> +void usb_hid_init (usbdev_t *dev);
> +void usb_msc_init (usbdev_t *dev);
> +
> +int set_address (hci_t *controller, int lowspeed);
> +
> +u8 *get_descriptor (usbdev_t *dev, unsigned char bmRequestType,
> +		    int descType, int descIdx, int langID);
> +
> +static inline unsigned char
> +gen_bmRequestType (dev_req_dir dir, dev_req_type type, dev_req_recp recp)
> +{
> +	return (dir << 7) | (type << 5) | recp;
> +}
> +
> +#endif
> Index: drivers/usb/usbhid.c
> ===================================================================
> --- drivers/usb/usbhid.c	(revision 0)
> +++ drivers/usb/usbhid.c	(revision 0)
> @@ -0,0 +1,137 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include "usb.h"
> +
> +enum { hid_subclass_none = 0, hid_subclass_boot = 1 };
> +enum { hid_proto_boot = 0, hid_proto_report = 1 };
> +enum { hid_boot_proto_none = 0, hid_boot_proto_keyboard =
> +		1, hid_boot_proto_mouse = 2
> +};
> +static const char *boot_protos[3] = { "(none)", "keyboard", "mouse" };
> +enum { GET_REPORT = 0x1, GET_IDLE = 0x2, GET_PROTOCOL = 0x3, SET_REPORT =
> +		0x9, SET_IDLE = 0xa, SET_PROTOCOL = 0xb
> +};
> +
> +static void
> +usb_hid_destroy (usbdev_t *dev)
> +{
> +}
> +
> +int keypress;
> +char keymap[256] = {
> +	-1, -1, -1, -1, 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k',
> +	'l',
> +	'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z',
> +	'1', '2',
> +	'3', '4', '5', '6', '7', '8', '9', '0', '\n', TERM_ESC,
> +	TERM_BACKSPACE, TERM_TAB, ' ', '-', '=', '[',
> +	']', '\\', -1, ';', '\'', '`', ',', '.', '/', -1, -1, -1, -1, -1, -1,
> +	-1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, TERM_HOME, TERM_PPAGE, -1,
> +	TERM_END, TERM_NPAGE, TERM_RIGHT,
> +	TERM_LEFT, TERM_DOWN, TERM_UP, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +};
> +
> +
> +static void
> +usb_hid_poll (usbdev_t *dev)
> +{
> +	char buf[8];
> +	static int toggle = 0;
> +	// hardcode to endpoint 1, 8 bytes
> +	dev->controller->packet (dev, 1, IN, toggle, 8, buf);
> +	toggle ^= 1;
> +	// FIXME: manage buf[0]=special keys, too
> +	keypress = keymap[buf[2]];
> +	if ((keypress == -1) && (buf[2] != 0)) {
> +		printf ("%x %x %x %x %x %x %x %x\n", buf[0], buf[1], buf[2],
> +			buf[3], buf[4], buf[5], buf[6], buf[7]);
> +	}
> +}
> +
> +int (*oldhook) (void);
> +
> +int
> +hookfunc (void)
> +{
> +	int key;
> +	if (oldhook != 0)
> +		key = oldhook ();
> +	if (key == -1)
> +		key = keypress;
> +	return key;
> +}
> +
> +void
> +usb_hid_init (usbdev_t *dev)
> +{
> +
> +	configuration_descriptor_t *cd = dev->configuration;
> +	interface_descriptor_t *interface = ((char *) cd) + cd->bLength;
> +
> +	if (interface->bInterfaceSubClass == hid_subclass_boot) {
> +		printf ("  supports boot interface..\n");
> +		printf ("  it's a %s\n",
> +			boot_protos[interface->bInterfaceProtocol]);
> +		if (interface->bInterfaceProtocol == hid_boot_proto_keyboard) {
> +			printf ("  activating...\n");
> +			dev_req_t dr;
> +			// set_protocol(hid_proto_boot)
> +			dr.data_dir = host_to_device;
> +			dr.req_type = class_type;
> +			dr.req_recp = iface_recp;
> +			dr.bRequest = SET_PROTOCOL;
> +			dr.wValue = hid_proto_boot;
> +			dr.wIndex = interface->bInterfaceNumber;
> +			dr.wLength = 0;
> +			dev->controller->control (dev, OUT,
> +						  sizeof (dev_req_t), &dr, 0,
> +						  0);
> +
> +			// only add here, because we only support boot-keyboard HID devices
> +			// FIXME: make this a real console input driver instead, once the API is there
> +			dev->destroy = usb_hid_destroy;
> +			dev->poll = usb_hid_poll;
> +			oldhook = getkey_hook;
> +			getkey_hook = hookfunc;
> +		}
> +	}
> +}
> Index: drivers/usb/uhci_rh.c
> ===================================================================
> --- drivers/usb/uhci_rh.c	(revision 0)
> +++ drivers/usb/uhci_rh.c	(revision 0)
> @@ -0,0 +1,182 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include <libpayload.h>
> +#include "uhci.h"
> +
> +typedef struct {
> +	int port[2];
> +} rh_inst_t;
> +
> +#define RH_INST(dev) ((rh_inst_t*)(dev)->data)
> +
> +static void
> +uhci_rh_enable_port (usbdev_t *dev, int port)
> +{
> +	u16 value;
> +	hci_t *controller = dev->controller;
> +	if (port == 1)
> +		port = PORTSC1;
> +	else
> +		port = PORTSC2;
> +	uhci_reg_mask16 (controller, port, ~(1 << 12), 0);	/* wakeup */
> +
> +	uhci_reg_mask16 (controller, port, ~0, 1 << 9);	/* reset */
> +	mdelay (30);		// >10ms
> +	uhci_reg_mask16 (controller, port, ~(1 << 9), 0);
> +	mdelay (1);		// >5.3us per spec, <3ms because some devices make trouble
> +
> +	uhci_reg_mask16 (controller, port, ~0, 1 << 2);	/* enable */
> +	do {
> +		value = uhci_reg_read16 (controller, port);
> +		mdelay (1);
> +	} while (((value & (1 << 2)) == 0) && (value & 0x01));
> +}
> +
> +/* disable root hub */
> +static void
> +uhci_rh_disable_port (usbdev_t *dev, int port)
> +{
> +	hci_t *controller = dev->controller;
> +	port = PORTSC2;
> +	if (port == 1)
> +		port = PORTSC1;
> +	uhci_reg_mask16 (controller, port, ~4, 0);
> +	int value;
> +	do {
> +		value = uhci_reg_read16 (controller, port);
> +		mdelay (1);
> +	} while ((value & (1 << 2)) != 0);
> +}
> +
> +static void
> +uhci_rh_scanport (usbdev_t *dev, int port)
> +{
> +	int portsc, offset;
> +	if (port == 1) {
> +		portsc = PORTSC1;
> +		offset = 0;
> +	} else if (port == 2) {
> +		portsc = PORTSC2;
> +		offset = 1;
> +	} else
> +		return;
> +	int devno = RH_INST (dev)->port[offset];
> +	if (devno != -1) {
> +		dev->controller->devices[devno].destroy (&dev->controller->
> +							 devices[devno]);
> +		init_device_entry (dev->controller, devno);
> +		RH_INST (dev)->port[offset] = -1;
> +	}
> +	uhci_reg_mask16 (dev->controller, portsc, ~0, (1 << 3) | (1 << 2));	// clear port state change, enable port
> +
> +	if ((uhci_reg_read16 (dev->controller, portsc) & 1) != 0) {
> +		int newdev;
> +		usbdev_t *newdev_t;
> +		// device attached
> +
> +		uhci_rh_disable_port (dev, port);
> +		uhci_rh_enable_port (dev, port);
> +
> +		int lowspeed =
> +			(uhci_reg_read16 (dev->controller, portsc) >> 8) & 1;
> +		printf ("%sspeed device\n", (lowspeed == 1) ? "low" : "full");
> +
> +		newdev = set_address (dev->controller, lowspeed);
> +		if (newdev == -1)
> +			return;
> +		newdev_t = &dev->controller->devices[newdev];
> +		RH_INST (dev)->port[offset] = newdev;
> +		newdev_t->address = newdev;
> +		newdev_t->hub = dev->address;
> +		newdev_t->port = portsc;
> +		// determine responsible driver
> +		newdev_t->init (newdev_t);
> +	}
> +}
> +
> +static int
> +uhci_rh_report_port_changes (usbdev_t *dev)
> +{
> +	int stored, real;
> +
> +	stored = (RH_INST (dev)->port[0] == -1);
> +	real = ((uhci_reg_read16 (dev->controller, PORTSC1) & 1) == 0);
> +	if (stored != real)
> +		return 1;
> +
> +	stored = (RH_INST (dev)->port[1] == -1);
> +	real = ((uhci_reg_read16 (dev->controller, PORTSC2) & 1) == 0);
> +	if (stored != real)
> +		return 2;
> +
> +// maybe detach+attach happened between two scans?
> +	if ((uhci_reg_read16 (dev->controller, PORTSC1) & 2) > 0)
> +		return 1;
> +	if ((uhci_reg_read16 (dev->controller, PORTSC2) & 2) > 0)
> +		return 2;
> +
> +// no change
> +	return -1;
> +}
> +
> +static void
> +uhci_rh_destroy (usbdev_t *dev)
> +{
> +	uhci_rh_disable_port (dev, 1);
> +	uhci_rh_disable_port (dev, 2);
> +	free (RH_INST (dev));
> +}
> +
> +static void
> +uhci_rh_poll (usbdev_t *dev)
> +{
> +	int port;
> +	while ((port = uhci_rh_report_port_changes (dev)) != -1)
> +		uhci_rh_scanport (dev, port);
> +}
> +
> +void
> +uhci_rh_init (usbdev_t *dev)
> +{
> +	dev->destroy = uhci_rh_destroy;
> +	dev->poll = uhci_rh_poll;
> +
> +	uhci_rh_enable_port (dev, 1);
> +	uhci_rh_enable_port (dev, 2);
> +	dev->data = malloc (sizeof (rh_inst_t));
> +	RH_INST (dev)->port[0] = -1;
> +	RH_INST (dev)->port[1] = -1;
> +
> +	/* we can set them here because a root hub _really_ shouldn't
> +	   appear elsewhere */
> +	dev->address = 0;
> +	dev->hub = -1;
> +	dev->port = -1;
> +}
> Index: drivers/usb/usbmsc.h
> ===================================================================
> --- drivers/usb/usbmsc.h	(revision 0)
> +++ drivers/usb/usbmsc.h	(revision 0)
> @@ -0,0 +1,47 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#ifndef __USBMSC_H
> +#define __USBMSC_H
> +typedef struct {
> +	unsigned int blocksize;
> +	unsigned int numblocks;
> +	endpoint_t *bulk_in;
> +	endpoint_t *bulk_out;
> +} usbmsc_inst_t;
> +
> +#define MSC_INST(dev) ((usbmsc_inst_t*)(dev)->data)
> +
> +typedef enum { cbw_direction_data_in = 0x80, cbw_direction_data_out = 0
> +} cbw_direction;
> +
> +int readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir,
> +		      u8 *buf);
> +
> +#endif
> Index: drivers/usb/TODO
> ===================================================================
> --- drivers/usb/TODO	(revision 0)
> +++ drivers/usb/TODO	(revision 0)
> @@ -0,0 +1,22 @@
> +- handle error conditions
> +- handle disconnect more gracefully (ie. make calling layer aware that the device doesn't exist somehow)
> +- usbhub:
> +  - proper client enumeration (esp. detach)
> +  - change detection
> +  - power management
> +- handle interrupts more cleverly:
> +  create a new queue for the interrupt with a couple of TD sequences,
> +    - each ending with "breadth first" flag
> +    - linked as a chain
> +  add that queue at the appropriate times in front of the default structure so the max latency is honored
> +    - only one intr chain per framelist item, so it must be arranged appropriately
> +  reads from usb device just look at "invalidated" tds and the results they got
> +  handled tds get reactivated as a ring structure
> +    - added as child of the oldest td
> +    - queue header already dropped the td, so no issue there
> +  
> +  this setup ensures that:
> +  - the max latency of the device is honored
> +  - the client knows the right order of the data
> +  - there is no need for an interrupt handler
> +    - but must be polled at least max latency * num tds times -> more tds = less time pressure
> Index: drivers/usb/usb_dev.c
> ===================================================================
> --- drivers/usb/usb_dev.c	(revision 0)
> +++ drivers/usb/usb_dev.c	(revision 0)
> @@ -0,0 +1,55 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include "usb.h"
> +
> +static void
> +usb_nop_destroy (usbdev_t *dev)
> +{
> +	if (dev->descriptor != 0)
> +		free (dev->descriptor);
> +	usb_nop_init (dev);
> +	dev->address = -1;
> +	dev->hub = -1;
> +	dev->port = -1;
> +}
> +
> +static void
> +usb_nop_poll (usbdev_t *dev)
> +{
> +	return;
> +}
> +
> +void
> +usb_nop_init (usbdev_t *dev)
> +{
> +	dev->descriptor = 0;
> +	dev->destroy = usb_nop_destroy;
> +	dev->poll = usb_nop_poll;
> +}
> Index: drivers/usb/uhci.c
> ===================================================================
> --- drivers/usb/uhci.c	(revision 0)
> +++ drivers/usb/uhci.c	(revision 0)
> @@ -0,0 +1,507 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include "usb.h"
> +#include "uhci.h"
> +#include <arch/virtual.h>
> +
> +static void uhci_start (hci_t *controller);
> +static void uhci_stop (hci_t *controller);
> +static void uhci_reset (hci_t *controller);
> +static void uhci_shutdown (hci_t *controller);
> +static int uhci_packet (usbdev_t *dev, int endp, int pid, int toggle,
> +			int length, u8 *data);
> +static int uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
> +static int uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq,
> +			 int dalen, u8 *data);
> +
> +#if 0
> +/* dump uhci */
> +static void
> +uhci_dump (hci_t *controller)
> +{
> +	printf ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD));
> +	printf ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS));
> +	printf ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR));
> +	printf ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM));
> +	printf ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD));
> +	printf ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD));
> +	printf ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1));
> +	printf ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2));
> +}
> +#endif
> +
> +static void
> +td_dump (td_t *td)
> +{
> +	printf ("%x packet (at %lx) to %x.%x failed\n", td->pid,
> +		virt_to_phys (td), td->dev_addr, td->endp);
> +	printf ("td (counter at %x) returns: ", td->counter);
> +	printf (" bitstuff err: %x, ", td->status_bitstuff_err);
> +	printf (" CRC err: %x, ", td->status_crc_err);
> +	printf (" NAK rcvd: %x, ", td->status_nakrcvd);
> +	printf (" Babble: %x, ", td->status_babble);
> +	printf (" Data Buffer err: %x, ", td->status_databuf_err);
> +	printf (" Stalled: %x, ", td->status_stalled);
> +	printf (" Active: %x\n", td->status_active);
> +	if (td->status_babble)
> +		printf (" Babble because of %s\n",
> +			td->status_bitstuff_err ? "host" : "device");
> +	if (td->status_active)
> +		printf (" still active - timeout?\n");
> +}
> +
> +static void
> +uhci_reset (hci_t *controller)
> +{
> +	/* reset */
> +	uhci_reg_write16 (controller, USBCMD, 4);
> +	mdelay (50);
> +	uhci_reg_write16 (controller, USBCMD, 0);
> +	mdelay (10);
> +	uhci_reg_write16 (controller, USBCMD, 2);
> +	while ((uhci_reg_read16 (controller, USBCMD) & 2) != 0)
> +		mdelay (1);
> +
> +	uhci_reg_write32 (controller, FLBASEADD,
> +			  (u32) virt_to_phys (UHCI_INST (controller)->
> +					      framelistptr));
> +	//printf ("framelist at %p\n",UHCI_INST(controller)->framelistptr);
> +
> +	/* disable irqs */
> +	uhci_reg_write16 (controller, USBINTR, 0);
> +
> +	/* reset framelist index */
> +	uhci_reg_write16 (controller, FRNUM, 0);
> +
> +	uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0);	// max packets, configure flag
> +
> +	uhci_start (controller);
> +}
> +
> +hci_t *
> +uhci_init (pcidev_t addr)
> +{
> +	int i;
> +	hci_t *controller = new_controller ();
> +
> +	controller->instance = malloc (sizeof (uhci_t));
> +	controller->start = uhci_start;
> +	controller->stop = uhci_stop;
> +	controller->reset = uhci_reset;
> +	controller->shutdown = uhci_shutdown;
> +	controller->packet = uhci_packet;
> +	controller->bulk = uhci_bulk;
> +	controller->control = uhci_control;
> +	UHCI_INST (controller)->roothub = &(controller->devices[0]);
> +
> +	controller->bus_address = addr;
> +	controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1;	/* ~1 clears the register type indicator that is set to 1 for IO space */
> +
> +	/* kill legacy support handler */
> +	uhci_stop (controller);
> +	mdelay (1);
> +	uhci_reg_write16 (controller, USBSTS, 0x3f);
> +	pci_write_config32 (controller->bus_address, 0xc0, 0x8f00);
> +
> +	UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t *));	/* 4kb aligned to 4kb */
> +	memset (UHCI_INST (controller)->framelistptr, 0,
> +		1024 * sizeof (flistp_t));
> +
> +	UHCI_INST (controller)->qh_intr = memalign (16, sizeof (qh_t));
> +	UHCI_INST (controller)->qh_data = memalign (16, sizeof (qh_t));
> +	UHCI_INST (controller)->qh_last = memalign (16, sizeof (qh_t));
> +
> +	UHCI_INST (controller)->qh_intr->headlinkptr.ptr =
> +		virt_to_phys (UHCI_INST (controller)->qh_data);
> +	UHCI_INST (controller)->qh_intr->headlinkptr.queue_head = 1;
> +	UHCI_INST (controller)->qh_intr->elementlinkptr.ptr = 0;
> +	UHCI_INST (controller)->qh_intr->elementlinkptr.terminate = 1;
> +
> +	UHCI_INST (controller)->qh_data->headlinkptr.ptr =
> +		virt_to_phys (UHCI_INST (controller)->qh_last);
> +	UHCI_INST (controller)->qh_data->headlinkptr.queue_head = 1;
> +	UHCI_INST (controller)->qh_data->elementlinkptr.ptr = 0;
> +	UHCI_INST (controller)->qh_data->elementlinkptr.terminate = 1;
> +
> +	UHCI_INST (controller)->qh_last->headlinkptr.ptr = 0;
> +	UHCI_INST (controller)->qh_last->headlinkptr.terminate = 1;
> +	UHCI_INST (controller)->qh_last->elementlinkptr.ptr = 0;
> +	UHCI_INST (controller)->qh_last->elementlinkptr.terminate = 1;
> +
> +	for (i = 0; i < 1024; i++) {
> +		UHCI_INST (controller)->framelistptr[i].ptr =
> +			virt_to_phys (UHCI_INST (controller)->qh_intr);
> +		UHCI_INST (controller)->framelistptr[i].terminate = 0;
> +		UHCI_INST (controller)->framelistptr[i].queue_head = 1;
> +	}
> +	for (i = 1; i < 128; i++) {
> +		init_device_entry (controller, i);
> +	}
> +	controller->devices[0].controller = controller;
> +	controller->devices[0].init = uhci_rh_init;
> +	controller->devices[0].init (&controller->devices[0]);
> +	uhci_reset (controller);
> +	return controller;
> +}
> +
> +static void
> +uhci_shutdown (hci_t *controller)
> +{
> +	if (controller == 0)
> +		return;
> +	detach_controller (controller);
> +	UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
> +						  roothub);
> +	uhci_reg_mask16 (controller, USBCMD, 0, 0);	// stop work
> +	free (UHCI_INST (controller)->framelistptr);
> +	free (UHCI_INST (controller)->qh_intr);
> +	free (UHCI_INST (controller)->qh_data);
> +	free (UHCI_INST (controller)->qh_last);
> +	free (UHCI_INST (controller));
> +	free (controller);
> +}
> +
> +static void
> +uhci_start (hci_t *controller)
> +{
> +	uhci_reg_mask16 (controller, USBCMD, ~0, 1);	// start work on schedule
> +}
> +
> +static void
> +uhci_stop (hci_t *controller)
> +{
> +	uhci_reg_mask16 (controller, USBCMD, ~1, 0);	// stop work on schedule
> +}
> +
> +#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
> +
> +static td_t *
> +wait_for_completed_qh (hci_t *controller, qh_t *qh)
> +{
> +	int timeout = 1000;	/* max 30 ms. */
> +	void *current = GET_TD (qh->elementlinkptr.ptr);
> +	while ((qh->elementlinkptr.terminate == 0) && (timeout-- > 0)) {
> +		if (current != GET_TD (qh->elementlinkptr.ptr)) {
> +			current = GET_TD (qh->elementlinkptr.ptr);
> +			timeout = 1000;
> +		}
> +		uhci_reg_mask16 (controller, USBSTS, ~0, 0);	// clear resettable registers
> +		udelay (30);
> +	}
> +	return (GET_TD (qh->elementlinkptr.ptr) ==
> +		0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr.ptr));
> +}
> +
> +static void
> +wait_for_completed_td (hci_t *controller, td_t *td)
> +{
> +	int timeout = 10000;
> +	while ((td->status_active == 1)
> +	       && ((uhci_reg_read16 (controller, USBSTS) & 2) == 0)
> +	       && (timeout-- > 0)) {
> +		uhci_reg_mask16 (controller, USBSTS, ~0, 0);	// clear resettable registers
> +		udelay (10);
> +	}
> +}
> +
> +static int
> +maxlen (int size)
> +{
> +	return (size - 1) & 0x7ff;
> +}
> +
> +static int
> +min (int a, int b)
> +{
> +	if (a < b)
> +		return a;
> +	else
> +		return b;
> +}
> +
> +static int
> +uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq, int dalen,
> +	      unsigned char *data)
> +{
> +	int endp = 0;		/* this is control: always 0 */
> +	int mlen = dev->endpoints[0].maxpacketsize;
> +	int count = (2 + (dalen + mlen - 1) / mlen);
> +	unsigned short req = ((unsigned short *) devreq)[0];
> +	int i;
> +	td_t *tds = memalign (16, sizeof (td_t) * count);
> +	memset (tds, 0, sizeof (td_t) * count);
> +	count--;		/* to compensate for 0-indexed array */
> +	for (i = 0; i < count; i++) {
> +		tds[i].ptr = virt_to_phys (&tds[i + 1]);
> +		tds[i].depth_first = 1;
> +		tds[i].terminate = 0;
> +	}
> +	tds[count].ptr = 0;
> +	tds[count].depth_first = 1;
> +	tds[count].terminate = 1;
> +
> +	tds[0].pid = SETUP;
> +	tds[0].dev_addr = dev->address;
> +	tds[0].endp = endp;
> +	tds[0].maxlen = maxlen (drlen);
> +	tds[0].counter = 3;
> +	tds[0].data_toggle = 0;
> +	tds[0].lowspeed = dev->lowspeed;
> +	tds[0].bufptr = virt_to_phys (devreq);
> +	tds[0].status_active = 1;
> +
> +	int toggle = 1;
> +	for (i = 1; i < count; i++) {
> +		tds[i].pid = dir;
> +		tds[i].dev_addr = dev->address;
> +		tds[i].endp = endp;
> +		tds[i].maxlen = maxlen (min (mlen, dalen));
> +		tds[i].counter = 3;
> +		tds[i].data_toggle = toggle;
> +		tds[i].lowspeed = dev->lowspeed;
> +		tds[i].bufptr = virt_to_phys (data);
> +		tds[i].status_active = 1;
> +		toggle ^= 1;
> +		dalen -= mlen;
> +		data += mlen;
> +	}
> +
> +	tds[count].pid = (dir == OUT) ? IN : OUT;
> +	tds[count].dev_addr = dev->address;
> +	tds[count].endp = endp;
> +	tds[count].maxlen = maxlen (0);
> +	tds[count].counter = 0;	/* as per linux 2.4.10 */
> +	tds[count].data_toggle = 1;
> +	tds[count].lowspeed = dev->lowspeed, tds[count].bufptr = 0;
> +	tds[count].status_active = 1;
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
> +		virt_to_phys (tds);
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
> +	td_t *td = wait_for_completed_qh (dev->controller,
> +					  UHCI_INST (dev->controller)->
> +					  qh_data);
> +	int result;
> +	if (td == 0) {
> +		result = 0;
> +	} else {
> +		printf ("control packet, req %x\n", req);
> +		td_dump (td);
> +		result = 1;
> +	}
> +	free (tds);
> +	return result;
> +}
> +
> +static int
> +uhci_packet (usbdev_t *dev, int endp, int pid, int toggle, int length,
> +	     unsigned char *data)
> +{
> +	static td_t *td = 0;
> +	if (td == 0)
> +		td = memalign (16, sizeof (td_t));
> +
> +	memset (td, 0, sizeof (td_t));
> +	td->ptr = 0;
> +	td->terminate = 1;
> +	td->queue_head = 0;
> +
> +	td->pid = pid;
> +	td->dev_addr = dev->address;
> +	td->endp = endp & 0xf;
> +	td->maxlen = maxlen (length);
> +	if (pid == SETUP)
> +		td->counter = 3;
> +	else
> +		td->counter = 0;
> +	td->data_toggle = toggle & 1;
> +	td->lowspeed = dev->lowspeed;
> +	td->bufptr = virt_to_phys (data);
> +
> +	td->status_active = 1;
> +
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
> +		virt_to_phys (td);
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
> +	wait_for_completed_td (dev->controller, td);
> +	if ((td->status & 0x7f) == 0) {
> +		//printf("successfully sent a %x packet to %x.%x\n",pid, dev->address,endp);
> +		// success
> +		return 0;
> +	} else {
> +		td_dump (td);
> +		return 1;
> +	}
> +}
> +
> +static td_t *
> +create_schedule (int numpackets)
> +{
> +	if (numpackets == 0)
> +		return 0;
> +	td_t *tds = memalign (16, sizeof (td_t) * numpackets);
> +	memset (tds, 0, sizeof (td_t) * numpackets);
> +	int i;
> +	for (i = 0; i < numpackets; i++) {
> +		tds[i].ptr = virt_to_phys (&tds[i + 1]);
> +		tds[i].terminate = 0;
> +		tds[i].queue_head = 0;
> +		tds[i].depth_first = 1;
> +	}
> +	tds[numpackets - 1].ptr = 0;
> +	tds[numpackets - 1].terminate = 1;
> +	tds[numpackets - 1].queue_head = 0;
> +	tds[numpackets - 1].depth_first = 0;
> +	return tds;
> +}
> +
> +static void
> +fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
> +	       int *toggle)
> +{
> +	td->pid = ep->direction;
> +	td->dev_addr = ep->dev->address;
> +	td->endp = ep->endpoint & 0xf;
> +	td->maxlen = maxlen (length);
> +	if (ep->direction == SETUP)
> +		td->counter = 3;
> +	else
> +		td->counter = 0;
> +	td->data_toggle = *toggle & 1;
> +	td->lowspeed = ep->dev->lowspeed;
> +	td->bufptr = virt_to_phys (data);
> +
> +	td->status_active = 1;
> +	*toggle ^= 1;
> +}
> +
> +static int
> +run_schedule (usbdev_t *dev, td_t *td)
> +{
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
> +		virt_to_phys (td);
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
> +	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
> +	td = wait_for_completed_qh (dev->controller,
> +				    UHCI_INST (dev->controller)->qh_data);
> +	if (td == 0) {
> +		return 0;
> +	} else {
> +		td_dump (td);
> +		return 1;
> +	}
> +}
> +
> +/* finalize == 1: if data is of packet aligned size, add a zero length packet */
> +static int
> +uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
> +{
> +	int maxpsize = ep->maxpacketsize;
> +	if (maxpsize == 0)
> +		fatal ("MaxPacketSize == 0!!!");
> +	int numpackets = (size + maxpsize - 1 + finalize) / maxpsize;
> +	if (numpackets == 0)
> +		return 0;
> +	td_t *tds = create_schedule (numpackets);
> +	int i = 0, toggle = ep->toggle;
> +	while ((size > 0) || ((size == 0) && (finalize != 0))) {
> +		fill_schedule (&tds[i], ep, min (size, maxpsize), data,
> +			       &toggle);
> +		i++;
> +		data += maxpsize;
> +		size -= maxpsize;
> +	}
> +	if (run_schedule (ep->dev, tds) == 1) {
> +		clear_stall (ep);
> +		free (tds);
> +		return 1;
> +	}
> +	ep->toggle = toggle;
> +	free (tds);
> +	return 0;
> +}
> +
> +void
> +uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value)
> +{
> +	outl (value, ctrl->reg_base + reg);
> +}
> +
> +u32
> +uhci_reg_read32 (hci_t *ctrl, usbreg reg)
> +{
> +	return inl (ctrl->reg_base + reg);
> +}
> +
> +void
> +uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value)
> +{
> +	outw (value, ctrl->reg_base + reg);
> +}
> +
> +u16
> +uhci_reg_read16 (hci_t *ctrl, usbreg reg)
> +{
> +	return inw (ctrl->reg_base + reg);
> +}
> +
> +void
> +uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value)
> +{
> +	outb (value, ctrl->reg_base + reg);
> +}
> +
> +u8
> +uhci_reg_read8 (hci_t *ctrl, usbreg reg)
> +{
> +	return inb (ctrl->reg_base + reg);
> +}
> +
> +void
> +uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask)
> +{
> +	uhci_reg_write32 (ctrl, reg,
> +			  (uhci_reg_read32 (ctrl, reg) & andmask) | ormask);
> +}
> +
> +void
> +uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask)
> +{
> +	uhci_reg_write16 (ctrl, reg,
> +			  (uhci_reg_read16 (ctrl, reg) & andmask) | ormask);
> +}
> +
> +void
> +uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask)
> +{
> +	uhci_reg_write8 (ctrl, reg,
> +			 (uhci_reg_read8 (ctrl, reg) & andmask) | ormask);
> +}
> Index: drivers/usb/usbhub.c
> ===================================================================
> --- drivers/usb/usbhub.c	(revision 0)
> +++ drivers/usb/usbhub.c	(revision 0)
> @@ -0,0 +1,158 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include "usb.h"
> +
> +// assume that host_to_device is overwritten if necessary
> +#define DR_PORT gen_bmRequestType(host_to_device, class_type, other_recp)
> +#define PORT_RESET 0x4
> +#define PORT_POWER 0x8
> +
> +typedef struct {
> +	int num_ports;
> +	int *ports;
> +	hub_descriptor_t *descriptor;
> +} usbhub_inst_t;
> +
> +#define HUB_INST(dev) ((usbhub_inst_t*)(dev)->data)
> +
> +static void
> +usb_hub_destroy (usbdev_t *dev)
> +{
> +	free (HUB_INST (dev)->ports);
> +	free (HUB_INST (dev)->descriptor);
> +	free (HUB_INST (dev));
> +}
> +
> +static void
> +usb_hub_scanport (usbdev_t *dev, int port)
> +{
> +	int newdev;
> +	unsigned short buf[2];
> +	usbdev_t *newdev_t;
> +
> +	get_status (dev, port, DR_PORT, 4, buf);
> +	int portstatus = ((buf[0] & 1) == 0);
> +	int datastatus = (HUB_INST (dev)->ports[port] == -1);
> +	if (portstatus == datastatus)
> +		return;		// no change - FIXME: read right fields for that test
> +
> +	if (!datastatus) {
> +		int devno = HUB_INST (dev)->ports[port];
> +		if (devno == -1)
> +			fatal ("FATAL: illegal devno!\n");
> +		dev->controller->devices[devno].destroy (&dev->controller->
> +							 devices[devno]);
> +		init_device_entry (dev->controller, devno);
> +		HUB_INST (dev)->ports[port] = -1;
> +		return;
> +	}
> +
> +	set_feature (dev, port, PORT_RESET, DR_PORT);
> +	mdelay (20);
> +
> +	get_status (dev, port, DR_PORT, 4, buf);
> +	int lowspeed = (buf[0] >> 9) & 1;
> +
> +	newdev = set_address (dev->controller, lowspeed);
> +	if (newdev == -1)
> +		return;
> +	newdev_t = &dev->controller->devices[newdev];
> +
> +	HUB_INST (dev)->ports[port] = newdev;
> +	newdev_t->address = newdev;
> +	newdev_t->hub = dev->address;
> +	newdev_t->port = port;
> +	// determine responsible driver
> +	newdev_t->init (newdev_t);
> +}
> +
> +static int
> +usb_hub_report_port_changes (usbdev_t *dev)
> +{
> +	int port;
> +	unsigned short buf[2];
> +	for (port = 1; port <= HUB_INST (dev)->num_ports; port++) {
> +		get_status (dev, port, DR_PORT, 4, buf);
> +		// FIXME: proper change detection
> +		int portstatus = ((buf[0] & 1) == 0);
> +		int datastatus = (HUB_INST (dev)->ports[port] == -1);
> +		if (portstatus != datastatus)
> +			return port;
> +	}
> +
> +// no change
> +	return -1;
> +}
> +
> +static void
> +usb_hub_enable_port (usbdev_t *dev, int port)
> +{
> +	set_feature (dev, port, PORT_POWER, DR_PORT);
> +	mdelay (20);
> +}
> +
> +#if 0
> +static void
> +usb_hub_disable_port (usbdev_t *dev, int port)
> +{
> +}
> +#endif
> +
> +static void
> +usb_hub_poll (usbdev_t *dev)
> +{
> +	int port;
> +	while ((port = usb_hub_report_port_changes (dev)) != -1)
> +		usb_hub_scanport (dev, port);
> +}
> +
> +void
> +usb_hub_init (usbdev_t *dev)
> +{
> +	int i;
> +	dev->destroy = usb_hub_destroy;
> +	dev->poll = usb_hub_poll;
> +
> +	dev->data = malloc (sizeof (usbhub_inst_t));
> +
> +	HUB_INST (dev)->descriptor =
> +		(hub_descriptor_t *) get_descriptor (dev,
> +						     gen_bmRequestType
> +						     (device_to_host,
> +						      class_type, dev_recp),
> +						     0x29, 0, 0);
> +	HUB_INST (dev)->num_ports = HUB_INST (dev)->descriptor->bNbrPorts;
> +	HUB_INST (dev)->ports =
> +		malloc (sizeof (int) * (HUB_INST (dev)->num_ports + 1));
> +	for (i = 1; i <= HUB_INST (dev)->num_ports; i++)
> +		HUB_INST (dev)->ports[i] = -1;
> +	for (i = 1; i <= HUB_INST (dev)->num_ports; i++)
> +		usb_hub_enable_port (dev, i);
> +}
> Index: drivers/usb/usb.c
> ===================================================================
> --- drivers/usb/usb.c	(revision 0)
> +++ drivers/usb/usb.c	(revision 0)
> @@ -0,0 +1,347 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include <config.h>
> +#include "usb.h"
> +
> +hci_t *usb_hcs = 0;
> +
> +hci_t *
> +new_controller ()
> +{
> +	hci_t *controller = malloc (sizeof (hci_t));
> +
> +	/* atomic */
> +	controller->next = usb_hcs;
> +	usb_hcs = controller;
> +	/* atomic end */
> +
> +	return controller;
> +}
> +
> +void
> +detach_controller (hci_t *controller)
> +{
> +	if (controller == 0)
> +		return;
> +	if (usb_hcs == controller) {
> +		usb_hcs = controller->next;
> +	} else {
> +		hci_t *it = usb_hcs;
> +		while (it != 0) {
> +			if (it->next == controller) {
> +				it->next = controller->next;
> +				return;
> +			}
> +		}
> +	}
> +}
> +
> +void
> +usb_poll ()
> +{
> +	if (usb_hcs == 0)
> +		return;
> +	hci_t *controller = usb_hcs;
> +	while (controller != 0) {
> +		int i;
> +		for (i = 0; i < 128; i++) {
> +			if (controller->devices[i].address != -1) {
> +				controller->devices[i].poll (&controller->
> +							     devices[i]);
> +			}
> +		}
> +		controller = controller->next;
> +	}
> +}
> +
> +void
> +init_device_entry (hci_t *controller, int i)
> +{
> +	controller->devices[i].controller = controller;
> +	controller->devices[i].address = -1;
> +	controller->devices[i].hub = -1;
> +	controller->devices[i].port = -1;
> +	controller->devices[i].init = usb_nop_init;
> +	controller->devices[i].init (&controller->devices[i]);
> +}
> +
> +void
> +set_feature (usbdev_t *dev, int endp, int feature, int rtype)
> +{
> +	dev_req_t dr;
> +
> +	dr.bmRequestType = rtype;
> +	dr.data_dir = host_to_device;
> +	dr.bRequest = SET_FEATURE;
> +	dr.wValue = feature;
> +	dr.wIndex = endp;
> +	dr.wLength = 0;
> +	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
> +}
> +
> +void
> +get_status (usbdev_t *dev, int intf, int rtype, int len, void *data)
> +{
> +	dev_req_t dr;
> +
> +	dr.bmRequestType = rtype;
> +	dr.data_dir = device_to_host;
> +	dr.bRequest = GET_STATUS;
> +	dr.wValue = 0;
> +	dr.wIndex = intf;
> +	dr.wLength = len;
> +	dev->controller->control (dev, IN, sizeof (dr), &dr, len, data);
> +}
> +
> +u8 *
> +get_descriptor (usbdev_t *dev, unsigned char bmRequestType, int descType,
> +		int descIdx, int langID)
> +{
> +	u8 buf[8];
> +	u8 *result;
> +	dev_req_t dr;
> +	int size;
> +
> +	dr.bmRequestType = bmRequestType;
> +	dr.data_dir = device_to_host;	// always like this for descriptors
> +	dr.bRequest = GET_DESCRIPTOR;
> +	dr.wValue = (descType << 8) | descIdx;
> +	dr.wIndex = langID;
> +	dr.wLength = 8;
> +	if (dev->controller->control (dev, IN, sizeof (dr), &dr, 8, buf)) {
> +		printf ("getting descriptor size (type %x) failed\n",
> +			descType);
> +	}
> +
> +	if (descType == 1) {
> +		device_descriptor_t *dd = (device_descriptor_t *) buf;
> +		printf ("maxPacketSize0: %x\n", dd->bMaxPacketSize0);
> +		if (dd->bMaxPacketSize0 != 0)
> +			dev->endpoints[0].maxpacketsize = dd->bMaxPacketSize0;
> +	}
> +
> +	/* special case for configuration descriptors: they carry all their
> +	   subsequent descriptors with them, and keep the entire size at a
> +	   different location */
> +	size = buf[0];
> +	if (buf[1] == 2) {
> +		int realsize = ((unsigned short *) (buf + 2))[0];
> +		size = realsize;
> +	}
> +	result = malloc (size);
> +	memset (result, 0, size);
> +	dr.wLength = size;
> +	if (dev->controller->
> +	    control (dev, IN, sizeof (dr), &dr, size, result)) {
> +		printf ("getting descriptor (type %x, size %x) failed\n",
> +			descType, size);
> +	}
> +
> +	return result;
> +}
> +
> +void
> +set_configuration (usbdev_t *dev)
> +{
> +	dev_req_t dr;
> +
> +	dr.bmRequestType = 0;
> +	dr.bRequest = SET_CONFIGURATION;
> +	dr.wValue = dev->configuration[5];
> +	dr.wIndex = 0;
> +	dr.wLength = 0;
> +	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
> +}
> +
> +int
> +clear_stall (endpoint_t *ep)
> +{
> +	usbdev_t *dev = ep->dev;
> +	int endp = ep->endpoint;
> +	dev_req_t dr;
> +
> +	dr.bmRequestType = 0;
> +	if (endp != 0) {
> +		dr.req_recp = endp_recp;
> +	}
> +	dr.bRequest = CLEAR_FEATURE;
> +	dr.wValue = ENDPOINT_HALT;
> +	dr.wIndex = endp;
> +	dr.wLength = 0;
> +	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
> +	return 0;
> +}
> +
> +/* returns free address or -1 */
> +static int
> +get_free_address (hci_t *controller)
> +{
> +	int i;
> +	for (i = 1; i < 128; i++) {
> +		if (controller->devices[i].address != i)
> +			return i;
> +	}
> +	printf ("no free address found\n");
> +	return -1;		// no free address
> +}
> +
> +int
> +set_address (hci_t *controller, int lowspeed)
> +{
> +	int adr = get_free_address (controller);	// address to set
> +	dev_req_t dr;
> +	configuration_descriptor_t *cd;
> +	device_descriptor_t *dd;
> +
> +	memset (&dr, 0, sizeof (dr));
> +	dr.data_dir = host_to_device;
> +	dr.req_type = standard_type;
> +	dr.req_recp = dev_recp;
> +	dr.bRequest = SET_ADDRESS;
> +	dr.wValue = adr;
> +	dr.wIndex = 0;
> +	dr.wLength = 0;
> +
> +	usbdev_t *dev = &controller->devices[adr];
> +	// dummy values for registering the address
> +	dev->address = 0;
> +	dev->lowspeed = lowspeed;
> +	dev->endpoints[0].dev = dev;
> +	dev->endpoints[0].endpoint = 0;
> +	dev->endpoints[0].maxpacketsize = 8;
> +	dev->endpoints[0].toggle = 0;
> +	dev->endpoints[0].direction = SETUP;
> +	mdelay (50);
> +	if (dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0)) {
> +		printf ("set_address failed\n");
> +		return -1;
> +	}
> +	mdelay (50);
> +	dev->address = adr;
> +	dev->descriptor =
> +		get_descriptor (dev,
> +				gen_bmRequestType (device_to_host,
> +						   standard_type, dev_recp),
> +				1, 0, 0);
> +	dd = (device_descriptor_t *) dev->descriptor;
> +	printf ("device version: %x.%x\n", dd->bcdUSB >> 8,
> +		dd->bcdUSB & 0xff);
> +	printf ("device has %x configurations\n", dd->bNumConfigurations);
> +	if (dd->bNumConfigurations == 0) {
> +		/* device isn't usable */
> +		printf ("no usable configuration!\n");
> +		dev->address = 0;
> +		return -1;
> +	}
> +	dev->configuration =
> +		get_descriptor (dev,
> +				gen_bmRequestType (device_to_host,
> +						   standard_type, dev_recp),
> +				2, 0, 0);
> +	cd = (configuration_descriptor_t *) dev->configuration;
> +	set_configuration (dev);
> +	interface_descriptor_t *interface =
> +		(interface_descriptor_t *) (((char *) cd) + cd->bLength);
> +	{
> +		int i;
> +		int num = cd->bNumInterfaces;
> +		interface_descriptor_t *current = interface;
> +		printf ("device has %x interfaces\n", num);
> +		num = (num > 5) ? 5 : num;
> +		for (i = 0; i < num; i++) {
> +			int j;
> +			printf (" #%x has %x endpoints, interface %x:%x, protocol %x\n", current->bInterfaceNumber, current->bNumEndpoints, current->bInterfaceClass, current->bInterfaceSubClass, current->bInterfaceProtocol);
> +			endpoint_descriptor_t *endp =
> +				(endpoint_descriptor_t *) (((char *) current)
> +							   +
> +							   current->bLength);
> +			if (interface->bInterfaceClass == 0x3)
> +				endp = (endpoint_descriptor_t *) (((char *) endp) + ((char *) endp)[0]);	// ignore HID descriptor
> +			memset (dev->endpoints, 0, sizeof (dev->endpoints));
> +			dev->num_endp = 1;	// 0 always exists
> +			dev->endpoints[0].dev = dev;
> +			dev->endpoints[0].maxpacketsize = dd->bMaxPacketSize0;
> +			dev->endpoints[0].direction = SETUP;
> +			dev->endpoints[0].type = CONTROL;
> +			for (j = 1; j <= current->bNumEndpoints; j++) {
> +				static const char *transfertypes[4] =
> +					{ "control", "isochronous", "bulk",
> +					"interrupt"
> +				};
> +				printf ("   #%x: Endpoint %x (%s), max packet size %x, type %s\n", j, endp->bEndpointAddress & 0x7f, ((endp->bEndpointAddress & 0x80) != 0) ? "in" : "out", endp->wMaxPacketSize, transfertypes[endp->bmAttributes]);
> +				endpoint_t *ep =
> +					&dev->endpoints[dev->num_endp++];
> +				ep->dev = dev;
> +				ep->endpoint = endp->bEndpointAddress;
> +				ep->toggle = 0;
> +				ep->maxpacketsize = endp->wMaxPacketSize;
> +				ep->direction =
> +					((endp->bEndpointAddress & 0x80) ==
> +					 0) ? OUT : IN;
> +				ep->type = endp->bmAttributes;
> +				endp = (endpoint_descriptor_t
> +					*) (((char *) endp) + endp->bLength);
> +			}
> +			current = (interface_descriptor_t *) endp;
> +		}
> +	}
> +	int class = dd->bDeviceClass;
> +	if (class == 0)
> +		class = interface->bInterfaceClass;
> +
> +	enum { hid_device = 0x3, msc_device = 0x8, hub_device = 0x9 };
> +
> +	printf ("device of class %x found\n", class);
> +	if (class == hub_device) {
> +		printf ("hub found\n");
> +#ifdef CONFIG_USB_HUB
> +		controller->devices[adr].init = usb_hub_init;
> +#else
> +		printf ("support not compiled in\n");
> +#endif
> +	}
> +	if (class == hid_device) {
> +		printf ("HID found\n");
> +#ifdef CONFIG_USB_HID
> +		controller->devices[adr].init = usb_hid_init;
> +#else
> +		printf ("support not compiled in\n");
> +#endif
> +	}
> +	if (class == msc_device) {
> +		printf ("MSC found\n");
> +#ifdef CONFIG_USB_MSC
> +		controller->devices[adr].init = usb_msc_init;
> +#else
> +		printf ("support not compiled in\n");
> +#endif
> +	}
> +	return adr;
> +}
> Index: drivers/usb/usbdisk.h
> ===================================================================
> --- drivers/usb/usbdisk.h	(revision 0)
> +++ drivers/usb/usbdisk.h	(revision 0)
> @@ -0,0 +1,37 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#ifndef __USBDISK_H
> +#define __USBDISK_H
> +#include "usb.h"
> +
> +void usbdisk_create (usbdev_t *dev);
> +void usbdisk_remove (usbdev_t *dev);
> +
> +#endif
> Index: drivers/usb/usbmsc.c
> ===================================================================
> --- drivers/usb/usbmsc.c	(revision 0)
> +++ drivers/usb/usbmsc.c	(revision 0)
> @@ -0,0 +1,389 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include <arch/endian.h>
> +#include "usb.h"
> +#include "usbmsc.h"
> +#include "usbdisk.h"
> +
> +enum {
> +	msc_subclass_rbc = 0x1,
> +	msc_subclass_mmc2 = 0x2,
> +	msc_subclass_qic157 = 0x3,
> +	msc_subclass_ufi = 0x4,
> +	msc_subclass_sff8070i = 0x5,
> +	msc_subclass_scsitrans = 0x6
> +};
> +static const char *msc_subclass_strings[7] = {
> +	"(none)",
> +	"RBC",
> +	"MMC-2",
> +	"QIC-157",
> +	"UFI",
> +	"SFF-8070i",
> +	"SCSI transparent"
> +};
> +enum {
> +	msc_proto_cbi_wcomp = 0x0,
> +	msc_proto_cbi_wocomp = 0x1,
> +	msc_proto_bulk_only = 0x50
> +};
> +static const char *msc_protocol_strings[0x51] = {
> +	"Control/Bulk/Interrupt protocol (with command completion interrupt)",
> +	"Control/Bulk/Interrupt protocol (with no command completion interrupt)",
> +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +	"Bulk-Only Transport"
> +};
> +
> +
> +static void
> +usb_msc_destroy (usbdev_t *dev)
> +{
> +	usbdisk_remove (dev);
> +	free (dev->data);
> +	dev->data = 0;
> +}
> +
> +static void
> +usb_msc_poll (usbdev_t *dev)
> +{
> +}
> +
> +const int DEV_RESET = 0xff;
> +const int GET_MAX_LUN = 0xfe;
> +
> +const unsigned int cbw_signature = 0x43425355;
> +const unsigned int csw_signature = 0x53425355;
> +
> +typedef struct {
> +	unsigned int dCBWSignature;
> +	unsigned int dCBWTag;
> +	unsigned int dCBWDataTransferLength;
> +	unsigned char bmCBWFlags;
> +	unsigned long bCBWLUN:4;
> +	unsigned long:4;
> +	unsigned long bCBWCBLength:5;
> +	unsigned long:3;
> +	unsigned char CBWCB[31 - 15];
> +} __attribute__ ((packed))
> +     cbw_t;
> +
> +     typedef struct {
> +	     unsigned int dCSWSignature;
> +	     unsigned int dCSWTag;
> +	     unsigned int dCSWDataResidue;
> +	     unsigned char bCSWStatus;
> +     } __attribute__ ((packed))
> +     csw_t;
> +
> +     static void
> +       reset_transport (usbdev_t *dev)
> +{
> +	dev_req_t dr;
> +	memset (&dr, 0, sizeof (dr));
> +	dr.bmRequestType = 0;
> +	dr.data_dir = host_to_device;
> +#ifndef QEMU
> +	dr.req_type = class_type;
> +	dr.req_recp = iface_recp;
> +#endif
> +	dr.bRequest = DEV_RESET;
> +	dr.wValue = 0;
> +	dr.wIndex = 0;
> +	dr.wLength = 0;
> +	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
> +	clear_stall (MSC_INST (dev)->bulk_in);
> +	clear_stall (MSC_INST (dev)->bulk_out);
> +}
> +
> +/* device may stall this command, so beware! */
> +static int
> +get_max_luns (usbdev_t *dev)
> +{
> +	unsigned char luns = 75;
> +	dev_req_t dr;
> +	dr.bmRequestType = 0;
> +	dr.data_dir = device_to_host;
> +#ifndef QEMU
> +	dr.req_type = class_type;
> +	dr.req_recp = iface_recp;
> +#endif
> +	dr.bRequest = GET_MAX_LUN;
> +	dr.wValue = 0;
> +	dr.wIndex = 0;
> +	dr.wLength = 1;
> +	if (dev->controller->control (dev, IN, sizeof (dr), &dr, 1, &luns)) {
> +		luns = 0;	// assume only 1 lun if req fails
> +	}
> +	return luns;
> +}
> +
> +int tag;
> +int lun = 0;
> +
> +static void
> +wrap_cbw (cbw_t *cbw, int datalen, cbw_direction dir, const u8 *cmd,
> +	  int cmdlen)
> +{
> +	memset (cbw, 0, sizeof (cbw_t));
> +
> +	cbw->dCBWSignature = cbw_signature;
> +	cbw->dCBWTag = tag++;
> +	cbw->bCBWLUN = lun;	// static value per device
> +
> +	cbw->dCBWDataTransferLength = datalen;
> +	cbw->bmCBWFlags = dir;
> +	memcpy (cbw->CBWCB, cmd, sizeof (cbw->CBWCB));
> +	cbw->bCBWCBLength = cmdlen;
> +}
> +
> +static void
> +get_csw (endpoint_t *ep, csw_t *csw)
> +{
> +	ep->dev->controller->bulk (ep, sizeof (csw_t), (u8 *) csw, 1);
> +}
> +
> +static int
> +execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen,
> +		 u8 *buf, int buflen)
> +{
> +	cbw_t cbw;
> +	csw_t csw;
> +
> +	int always_succeed = 0;
> +	if ((cb[0] == 0x1b) && (cb[4] == 1)) {	//start command, always succeed
> +		always_succeed = 1;
> +	}
> +	wrap_cbw (&cbw, buflen, dir, cb, cblen);
> +	if (dev->controller->
> +	    bulk (MSC_INST (dev)->bulk_out, sizeof (cbw), (u8 *) &cbw, 0)) {
> +		clear_stall (MSC_INST (dev)->bulk_out);
> +		return 1;
> +	}
> +	mdelay (10);
> +	if (dir == cbw_direction_data_in) {
> +		if (dev->controller->
> +		    bulk (MSC_INST (dev)->bulk_in, buflen, buf, 0)) {
> +			clear_stall (MSC_INST (dev)->bulk_in);
> +			return 1;
> +		}
> +	} else {
> +		if (dev->controller->
> +		    bulk (MSC_INST (dev)->bulk_out, buflen, buf, 0)) {
> +			clear_stall (MSC_INST (dev)->bulk_out);
> +			return 1;
> +		}
> +	}
> +	get_csw (MSC_INST (dev)->bulk_in, &csw);
> +	if (always_succeed == 1) {
> +		// return success, regardless of message
> +		return 0;
> +	}
> +	if (csw.bCSWStatus == 2) {
> +		// phase error, reset transport
> +		reset_transport (dev);
> +		return 1;
> +	}
> +	if (csw.bCSWStatus == 0) {
> +		// no error, exit
> +		return 0;
> +	}
> +	// error "check condition" or reserved error
> +	return 1;
> +}
> +
> +typedef struct {
> +	unsigned char command;	//0
> +	unsigned char res1;	//1
> +	unsigned int block;	//2-5
> +	unsigned char res2;	//6
> +	unsigned short numblocks;	//7-8
> +	unsigned char res3;	//9 - the block is 10 bytes long
> +} __attribute__ ((packed)) cmdblock_t;
> +
> +typedef struct {
> +	unsigned char command;	//0
> +	unsigned char res1;	//1
> +	unsigned char res2;	//2
> +	unsigned char res3;	//3
> +	unsigned char lun;	//4
> +	unsigned char res4;	//5
> +} __attribute__ ((packed)) cmdblock6_t;
> +
> +
> +/* returns success code (see execute_command)
> +   buf must be preallocated to at least n*512 bytes!
> +   limited to 2TB (READ(10) command)
> +*/
> +int
> +readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf)
> +{
> +	cmdblock_t cb;
> +	memset (&cb, 0, sizeof (cb));
> +	if (dir == cbw_direction_data_in) {
> +		// read
> +		cb.command = 0x28;
> +	} else {
> +		// write
> +		cb.command = 0x2a;
> +	}
> +	cb.block = ntohl (start);
> +	cb.numblocks = ntohw (n);
> +	return execute_command (dev, dir, (u8 *) &cb, sizeof (cb), buf,
> +				n * 512);
> +}
> +
> +static int
> +test_unit_ready (usbdev_t *dev)
> +{
> +	cmdblock6_t cb;
> +	memset (&cb, 0, sizeof (cb));	// full initialization for T-U-R
> +	return execute_command (dev, cbw_direction_data_out, (u8 *) &cb,
> +				sizeof (cb), 0, 0);
> +}
> +
> +static int
> +spin_up (usbdev_t *dev)
> +{
> +	cmdblock6_t cb;
> +	memset (&cb, 0, sizeof (cb));
> +	cb.command = 0x1b;
> +	cb.lun = 1;
> +	return execute_command (dev, cbw_direction_data_out, (u8 *) &cb,
> +				sizeof (cb), 0, 0);
> +}
> +
> +static void
> +read_capacity (usbdev_t *dev)
> +{
> +	cmdblock_t cb;
> +	memset (&cb, 0, sizeof (cb));
> +	cb.command = 0x25;	// read capacity
> +	u8 buf[8];
> +	int count = 0;
> +	while ((count++ < 20)
> +	       &&
> +	       (execute_command
> +		(dev, cbw_direction_data_in, (u8 *) &cb, sizeof (cb), buf,
> +		 8) == 1));
> +	if (count >= 20) {
> +		// still not successful, assume 2tb in 512byte sectors, which is just the same garbage as any other number, but probably reasonable.
> +		printf ("assuming 2TB in 512byte sectors as READ CAPACITY didn't answer.\n");
> +		MSC_INST (dev)->numblocks = 0xffffffff;
> +		MSC_INST (dev)->blocksize = 512;
> +	} else {
> +		MSC_INST (dev)->numblocks = ntohl (*(u32 *) buf) + 1;
> +		MSC_INST (dev)->blocksize = ntohl (*(u32 *) (buf + 4));
> +	}
> +	printf ("  has %d blocks sized %db\n", MSC_INST (dev)->numblocks,
> +		MSC_INST (dev)->blocksize);
> +}
> +
> +void
> +usb_msc_init (usbdev_t *dev)
> +{
> +	int i, timeout;
> +
> +	dev->destroy = usb_msc_destroy;
> +	dev->poll = usb_msc_poll;
> +
> +	configuration_descriptor_t *cd =
> +		(configuration_descriptor_t *) dev->configuration;
> +	interface_descriptor_t *interface =
> +		(interface_descriptor_t *) (((char *) cd) + cd->bLength);
> +
> +	printf ("  it uses %s command set\n",
> +		msc_subclass_strings[interface->bInterfaceSubClass]);
> +	printf ("  it uses %s protocol\n",
> +		msc_protocol_strings[interface->bInterfaceProtocol]);
> +
> +	if ((interface->bInterfaceProtocol != 0x50)
> +	    || (interface->bInterfaceSubClass != 6)) {
> +		/* Other protocols, such as ATAPI don't seem to be very popular. looks like ATAPI would be really easy to add, if necessary. */
> +		printf ("  Only SCSI over Bulk is supported.\n");
> +		return;
> +	}
> +
> +	dev->data = malloc (sizeof (usbmsc_inst_t));
> +	MSC_INST (dev)->bulk_in = 0;
> +	MSC_INST (dev)->bulk_out = 0;
> +
> +	for (i = 1; i <= dev->num_endp; i++) {
> +		if (dev->endpoints[i].endpoint == 0)
> +			continue;
> +		if (dev->endpoints[i].type != BULK)
> +			continue;
> +		if ((dev->endpoints[i].direction == IN)
> +		    && (MSC_INST (dev)->bulk_in == 0))
> +			MSC_INST (dev)->bulk_in = &dev->endpoints[i];
> +		if ((dev->endpoints[i].direction == OUT)
> +		    && (MSC_INST (dev)->bulk_out == 0))
> +			MSC_INST (dev)->bulk_out = &dev->endpoints[i];
> +	}
> +
> +	if (MSC_INST (dev)->bulk_in == 0)
> +		fatal ("couldn't find bulk-in endpoint");
> +	if (MSC_INST (dev)->bulk_out == 0)
> +		fatal ("couldn't find bulk-out endpoint");
> +	printf ("  using endpoint %x as in, %x as out\n",
> +		MSC_INST (dev)->bulk_in->endpoint,
> +		MSC_INST (dev)->bulk_out->endpoint);
> +
> +	printf ("  has %d luns\n", get_max_luns (dev) + 1);
> +
> +	printf ("  Waiting for device to become ready... ");
> +	timeout = 10;
> +	while (test_unit_ready (dev) && --timeout) {
> +		mdelay (100);
> +		printf (".");
> +	}
> +	if (test_unit_ready (dev)) {
> +		printf ("timeout. Device not ready. Still trying...\n");
> +	} else {
> +		printf ("ok.\n");
> +	}
> +
> +	printf ("  spin up");
> +	for (i = 0; i < 30; i++) {
> +		printf (".");
> +		if (!spin_up (dev)) {
> +			printf (" OK.");
> +			break;
> +		}
> +		mdelay (100);
> +	}
> +	printf ("\n");
> +
> +	read_capacity (dev);
> +	usbdisk_create (dev);
> +}
> Index: drivers/usb/uhci.h
> ===================================================================
> --- drivers/usb/uhci.h	(revision 0)
> +++ drivers/usb/uhci.h	(revision 0)
> @@ -0,0 +1,124 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#ifndef __UHCI_H
> +#define __UHCI_H
> +
> +#include <pci.h>
> +#include "usb.h"
> +
> +typedef union {
> +	struct {
> +		unsigned long terminate:1;
> +		unsigned long queue_head:1;
> +		unsigned long:2;
> +		unsigned long ptr_part:28;
> +	};
> +	u32 ptr;
> +} __attribute__ ((packed)) flistp_t;
> +
> +typedef struct {
> +	union {
> +		struct {
> +			unsigned long terminate:1;
> +			unsigned long queue_head:1;
> +			unsigned long depth_first:1;
> +			unsigned long:29;
> +		} __attribute__ ((packed));
> +		u32 ptr;
> +	} __attribute__ ((packed));
> +
> +	volatile unsigned long actlen:11;
> +	volatile unsigned long:5;
> +	union {
> +		struct {
> +			unsigned long:1;	// bit 0
> +			unsigned long status_bitstuff_err:1;
> +			unsigned long status_crc_err:1;
> +			unsigned long status_nakrcvd:1;
> +			unsigned long status_babble:1;
> +			unsigned long status_databuf_err:1;
> +			unsigned long status_stalled:1;
> +			unsigned long status_active:1;	// bit 7
> +		} __attribute__ ((packed));
> +		unsigned char status;
> +	} __attribute__ ((packed));
> +	volatile unsigned long ioc:1;	/* interrupt on complete */
> +	volatile unsigned long isochronous:1;
> +	volatile unsigned long lowspeed:1;
> +	volatile unsigned long counter:2;
> +	volatile unsigned long shortpck:1;
> +	volatile unsigned long:2;
> +
> +	unsigned long pid:8;
> +	unsigned long dev_addr:7;
> +	unsigned long endp:4;
> +	unsigned long data_toggle:1;
> +	unsigned long:1;
> +	unsigned long maxlen:11;
> +
> +	u32 bufptr;
> +
> +} __attribute__ ((packed))
> +     td_t;
> +
> +     typedef struct {
> +	     flistp_t headlinkptr;
> +	     volatile flistp_t elementlinkptr;
> +     } __attribute__ ((packed))
> +     qh_t;
> +
> +     typedef enum { USBCMD = 0, USBSTS = 2, USBINTR = 4, FRNUM =
> +		     6, FLBASEADD = 8, SOFMOD = 0xc, PORTSC1 = 0x10, PORTSC2 =
> +		     0x12
> +     } usbreg;
> +
> +     void uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value);
> +     u32 uhci_reg_read32 (hci_t *ctrl, usbreg reg);
> +     void uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value);
> +     u16 uhci_reg_read16 (hci_t *ctrl, usbreg reg);
> +     void uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value);
> +     u8 uhci_reg_read8 (hci_t *ctrl, usbreg reg);
> +     void uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask);
> +     void uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask);
> +     void uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask);
> +
> +     typedef struct uhci {
> +	     flistp_t *framelistptr;
> +	     qh_t *qh_intr, *qh_data, *qh_last;
> +	     usbdev_t *roothub;
> +     } uhci_t;
> +
> +#define UHCI_INST(controller) ((uhci_t*)((controller)->instance))
> +
> +     hci_t *uhci_init (pcidev_t addr);
> +
> +     void uhci_rh_init (usbdev_t *dev);
> +
> +#endif
> Index: drivers/usb/usbinit.c
> ===================================================================
> --- drivers/usb/usbinit.c	(revision 0)
> +++ drivers/usb/usbinit.c	(revision 0)
> @@ -0,0 +1,110 @@
> +/*
> + * This file is part of the libpayload project.
> + *
> + * Copyright (C) 2008 coresystems GmbH
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + * 3. The name of the author may not be used to endorse or promote products
> + *    derived from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#include <config.h>
> +#include "usb.h"
> +#include "uhci.h"
> +#include "usbdisk.h"
> +
> +int
> +usb_controller_initialize (int bus, int dev, int func)
> +{
> +	u32 class;
> +	u32 devclass;
> +	u32 prog_if;
> +	pcidev_t addr;
> +	u32 pciid;
> +
> +	addr = PCI_DEV (bus, dev, func);
> +	class = pci_read_config32 (addr, 8);
> +	pciid = pci_read_config32 (addr, 0);
> +
> +	devclass = class >> 16;
> +	prog_if = (class >> 8) & 0xff;
> +
> +	/* enable busmaster */
> +#define PCI_COMMAND 4
> +#define PCI_COMMAND_MASTER 4
> +	pci_write_config32 (addr, PCI_COMMAND,
> +			    pci_read_config32 (addr,
> +					       PCI_COMMAND) |
> +			    PCI_COMMAND_MASTER);
> +
> +	if (devclass == 0xc03) {
> +		printf ("%02x:%02x.%x %04x:%04x.%d ", 0, dev, func,
> +			pciid >> 16, pciid & 0xFFFF, func);
> +		if (prog_if == 0) {
> +			printf ("UHCI controller\n");
> +#ifdef CONFIG_USB_UHCI
> +			uhci_init (addr);
> +			usb_poll ();
> +			usb_poll ();
> +#else
> +			printf ("Not supported.\n");
> +#endif
> +		}
> +		if (prog_if == 0x10) {
> +			printf ("OHCI controller\n");
> +#ifdef CONFIG_USB_OHCI
> +			// ohci_init(addr);
> +#else
> +			printf ("Not supported.\n");
> +#endif
> +
> +		}
> +		if (prog_if == 0x20) {
> +			printf ("EHCI controller\n");
> +#ifdef CONFIG_USB_EHCI
> +			// ehci_init(addr);
> +#else
> +			printf ("Not supported.\n");
> +#endif
> +
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int
> +usb_initialize (void)
> +{
> +	int bus, dev, func;
> +	for (bus = 0; bus < 256; bus++)
> +		for (dev = 0; dev < 32; dev++)
> +			for (func = 0; func < 8; func++)
> +				usb_controller_initialize (bus, dev, func);
> +	return 0;
> +}
> +
> +int
> +usb_exit (void)
> +{
> +	return 0;
> +}




From svn at coreboot.org  Tue Sep  2 17:25:07 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  2 Sep 2008 17:25:07 +0200
Subject: [coreboot] r855 - coreboot-v3/arch/x86/amd/k8
Message-ID: <mailman.2018.1355071373.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2008-09-02 17:25:06 +0200 (Tue, 02 Sep 2008)
New Revision: 855

Modified:
   coreboot-v3/arch/x86/amd/k8/stage1.c
Log:
With this change, we get all the way to stage 2 and this output, at 
which point we hang:
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0
pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0
pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0
pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0
pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0
ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0
domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: PCI: 00:04.0 init.

The dts is quite incomplete and that is part of the problem. Doubtless 
there are other problems :-)

But training is indeed working in simnow, and memory is working, and we 
can return from disable_car as on the geode. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c	2008-09-01 02:44:08 UTC (rev 854)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-09-02 15:25:06 UTC (rev 855)
@@ -38,8 +38,16 @@
 	 * the data back over itself, and the wbinvd should then 
 	 * flush to memory. Let's see. 
 	 */
+	/* nope. 
 	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
+	 */
+	/* call the inlined function */
+	disable_cache_as_ram();
+
+	/* copy it down, wbinvd, copy it back? */
+	__asm__ __volatile__("cld; rep movsl" ::"D" (0x88000), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
 	__asm__ __volatile__ ("wbinvd\n");
+	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (0x88000), "c" (CONFIG_CARSIZE/4): "memory");
 	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
 	banner(BIOS_DEBUG, "disable_car: done");
 }




From rminnich at gmail.com  Tue Sep  2 17:29:08 2008
From: rminnich at gmail.com (ron minnich)
Date: Tue, 2 Sep 2008 08:29:08 -0700
Subject: [coreboot] k8 progress: now in stage2.
Message-ID: <13426df10809020829w7a46ef38te809253d480744d9@mail.gmail.com>

we're in to stage 2.

commit message:


With this change, we get all the way to stage 2 and this output, at
which point we hang:
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0
pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0
pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0
pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0
pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0
ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0
domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: PCI: 00:04.0 init.

The hang is in pci_domain_read_resources. pc is 5f92. That PC is not
compatible with the fact that we hit phase 6; something else is going
on.

The dts is quite incomplete and that is part of the problem. Doubtless
there are other problems :-)

But training is indeed working in simnow, and memory is working, and we
can return from disable_car as on the geode. For those of you who want
to help but were not sure what to do, well,
we've got LOTS of places that need help now :-)

ron



From svn at coreboot.org  Tue Sep  2 17:49:32 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  2 Sep 2008 17:49:32 +0200
Subject: [coreboot] r3559 - in trunk/payloads/libpayload: include libc
Message-ID: <mailman.2019.1355071373.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2008-09-02 17:49:32 +0200 (Tue, 02 Sep 2008)
New Revision: 3559

Modified:
   trunk/payloads/libpayload/include/libpayload.h
   trunk/payloads/libpayload/libc/malloc.c
Log:
Add memalign(align, size).

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>


Modified: trunk/payloads/libpayload/include/libpayload.h
===================================================================
--- trunk/payloads/libpayload/include/libpayload.h	2008-09-02 09:35:43 UTC (rev 3558)
+++ trunk/payloads/libpayload/include/libpayload.h	2008-09-02 15:49:32 UTC (rev 3559)
@@ -221,6 +221,7 @@
 void *malloc(size_t size);
 void *calloc(size_t nmemb, size_t size);
 void *realloc(void *ptr, size_t size);
+void *memalign(size_t align, size_t size);
 /** @} */
 
 /**

Modified: trunk/payloads/libpayload/libc/malloc.c
===================================================================
--- trunk/payloads/libpayload/libc/malloc.c	2008-09-02 09:35:43 UTC (rev 3558)
+++ trunk/payloads/libpayload/libc/malloc.c	2008-09-02 15:49:32 UTC (rev 3559)
@@ -72,7 +72,7 @@
 	*((hdrtype_t *) hstart) = FREE_BLOCK(size);
 }
 
-static void *alloc(int len)
+static void *alloc(int len, int align)
 {
 	hdrtype_t header;
 	void *ptr = hstart;
@@ -92,13 +92,20 @@
 		header = *((hdrtype_t *) ptr);
 		int size = SIZE(header);
 
-		if (!HAS_MAGIC(header) || size == 0) {
+		if (!HAS_MAGIC(header)) {
 			printf("memory allocator panic.\n");
 			halt();
 		}
 
 		if (header & FLAG_FREE) {
-			if (len <= size) {
+			int realaddr = (int)(ptr + HDRSIZE);
+			int overhead = ((realaddr+align-1) & ~(align-1)) - realaddr;
+			if (len + overhead <= size) {
+				if (overhead != 0) {
+					*((hdrtype_t *) ptr) = FREE_BLOCK(overhead - HDRSIZE);
+					ptr += overhead;
+					size -= overhead;
+				}
 				void *nptr = ptr + (HDRSIZE + len);
 				int nsize = size - (HDRSIZE + len);
 
@@ -186,13 +193,13 @@
 
 void *malloc(size_t size)
 {
-	return alloc(size);
+	return alloc(size, 1);
 }
 
 void *calloc(size_t nmemb, size_t size)
 {
 	size_t total = nmemb * size;
-	void *ptr = alloc(total);
+	void *ptr = alloc(total, 1);
 
 	if (ptr)
 		memset(ptr, 0, total);
@@ -206,7 +213,7 @@
 	unsigned int osize;
 
 	if (ptr == NULL)
-		return alloc(size);
+		return alloc(size, 1);
 
 	pptr = ptr - HDRSIZE;
 
@@ -222,7 +229,7 @@
 	 * reallocated the new space.
 	 */
 	free(ptr);
-	ret = alloc(size);
+	ret = alloc(size, 1);
 
 	/*
 	 * if ret == NULL, then doh - failure.
@@ -237,11 +244,23 @@
 	return ret;
 }
 
+/**
+ * Allocate an aligned chunk of memory
+ *
+ * @param align alignment, must be power of two
+ * @param size size of chunk in bytes
+ * @return Return the address of such a memory region or NULL
+ */
+void *memalign(size_t align, size_t size)
+{
+	return alloc(size, align);
+}
+
 /* This is for debugging purposes. */
 #ifdef TEST
 void print_malloc_map(void)
 {
-	void *ptr = hstart;
+void *ptr = hstart;
 
 	while (ptr < hend) {
 		hdrtype_t hdr = *((hdrtype_t *) ptr);




From svn at coreboot.org  Tue Sep  2 18:06:23 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  2 Sep 2008 18:06:23 +0200
Subject: [coreboot] r3560 - in trunk/payloads/libpayload: . drivers
	drivers/usb
Message-ID: <mailman.2020.1355071373.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2008-09-02 18:06:22 +0200 (Tue, 02 Sep 2008)
New Revision: 3560

Added:
   trunk/payloads/libpayload/drivers/usb/
   trunk/payloads/libpayload/drivers/usb/TODO
   trunk/payloads/libpayload/drivers/usb/uhci.c
   trunk/payloads/libpayload/drivers/usb/uhci.h
   trunk/payloads/libpayload/drivers/usb/uhci_rh.c
   trunk/payloads/libpayload/drivers/usb/usb.c
   trunk/payloads/libpayload/drivers/usb/usb.h
   trunk/payloads/libpayload/drivers/usb/usb_dev.c
   trunk/payloads/libpayload/drivers/usb/usbdisk.h
   trunk/payloads/libpayload/drivers/usb/usbhid.c
   trunk/payloads/libpayload/drivers/usb/usbhub.c
   trunk/payloads/libpayload/drivers/usb/usbinit.c
   trunk/payloads/libpayload/drivers/usb/usbmsc.c
   trunk/payloads/libpayload/drivers/usb/usbmsc.h
Modified:
   trunk/payloads/libpayload/Config.in
   trunk/payloads/libpayload/Makefile
   trunk/payloads/libpayload/drivers/Makefile.inc
Log:
This patch adds USB capabilities to libpayload. It requires some
memalign implementation (eg. the one I sent yesterday).
Features:
 - UHCI controller driver
 - UHCI root hub driver
 - USB MSC (Mass Storage Class) driver
 - skeleton of a USB HID driver
   (requires better interrupt transfer handling, which is TODO)
 - skeleton of a USB hub driver
   (needs several blank spots filled in, eg. power management.
    Again: TODO)

OHCI and EHCI are not supported, though OHCI support should be rather
easy as the stack provides reasonable abstractions (or so I hope). EHCI
will probably be more complicated.

Isochronous transfers (eg. webcams, audio stuff, ...) are not supported.
They can be, but I doubt we'll have a reason for that in the boot
environment.

The MSC driver was tested against a couple of USB flash drives, and
should be reasonably tolerant by now. But I probably underestimate
the amount of bugs present in USB flash drives, so feedback is welcome.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>


Modified: trunk/payloads/libpayload/Config.in
===================================================================
--- trunk/payloads/libpayload/Config.in	2008-09-02 15:49:32 UTC (rev 3559)
+++ trunk/payloads/libpayload/Config.in	2008-09-02 16:06:22 UTC (rev 3560)
@@ -132,5 +132,46 @@
 	bool "Support for PC speaker"
 	default y
 
+config USB
+	bool "USB Support"
+	default n
+
+config USB_UHCI
+	bool "Support for USB UHCI controllers"
+	depends on USB
+	help
+	  Select this option if you are going to use USB 1.1 on an Intel based
+	  system.
+
+config USB_OHCI
+	bool "Support for USB OHCI controllers"
+	depends on USB
+	help
+	  Select this option if you are going to use USB 1.1 on an AMD based
+	  system.
+	  NOTE: This option is not (fully) implemented yet
+
+config USB_EHCI
+	bool "Support for USB EHCI controllers"
+	depends on USB
+	help
+	  Select this option if you want to use USB 2.0
+	  NOTE: This option is not (fully) implemented yet
+
+config USB_HID
+	bool "Support for USB keyboards (broken)"
+	depends on USB
+	default n
+
+config USB_HUB
+	bool "Support for USB hubs (broken)"
+	depends on USB
+	default n
+
+config USB_MSC
+	bool "Support for USB storage"
+	depends on USB
+
+
 endmenu
 

Modified: trunk/payloads/libpayload/Makefile
===================================================================
--- trunk/payloads/libpayload/Makefile	2008-09-02 15:49:32 UTC (rev 3559)
+++ trunk/payloads/libpayload/Makefile	2008-09-02 16:06:22 UTC (rev 3560)
@@ -137,6 +137,7 @@
 prepare:
 	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
 	$(Q)mkdir -p $(obj)/crypto $(obj)/curses $(obj)/drivers/video
+	$(Q)mkdir -p $(obj)/drivers/usb
 	$(Q)mkdir -p $(obj)/i386 $(obj)/lib/$(ARCHDIR-y) $(obj)/libc 
 	$(Q)mkdir -p $(src)/lib/$(ARCHDIR-y)
 

Modified: trunk/payloads/libpayload/drivers/Makefile.inc
===================================================================
--- trunk/payloads/libpayload/drivers/Makefile.inc	2008-09-02 15:49:32 UTC (rev 3559)
+++ trunk/payloads/libpayload/drivers/Makefile.inc	2008-09-02 16:06:22 UTC (rev 3560)
@@ -47,3 +47,14 @@
 # Geode console drivers
 TARGETS-$(CONFIG_GEODE_VIDEO_CONSOLE) += drivers/video/geode.o
 TARGETS-$(CONFIG_GEODE_VIDEO_CONSOLE) += drivers/video/font8x16.o
+
+# USB stack
+TARGETS-$(CONFIG_USB) += drivers/usb/usbinit.o
+TARGETS-$(CONFIG_USB) += drivers/usb/usb.o
+TARGETS-$(CONFIG_USB) += drivers/usb/usb_dev.o
+TARGETS-$(CONFIG_USB_HUB) += drivers/usb/usbhub.o
+TARGETS-$(CONFIG_USB_UHCI) += drivers/usb/uhci.o
+TARGETS-$(CONFIG_USB_UHCI) += drivers/usb/uhci_rh.o
+TARGETS-$(CONFIG_USB_HID) += drivers/usb/usbhid.o
+TARGETS-$(CONFIG_USB_MSC) += drivers/usb/usbmsc.o
+

Added: trunk/payloads/libpayload/drivers/usb/TODO
===================================================================
--- trunk/payloads/libpayload/drivers/usb/TODO	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/TODO	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,22 @@
+- handle error conditions
+- handle disconnect more gracefully (ie. make calling layer aware that the device doesn't exist somehow)
+- usbhub:
+  - proper client enumeration (esp. detach)
+  - change detection
+  - power management
+- handle interrupts more cleverly:
+  create a new queue for the interrupt with a couple of TD sequences,
+    - each ending with "breadth first" flag
+    - linked as a chain
+  add that queue at the appropriate times in front of the default structure so the max latency is honored
+    - only one intr chain per framelist item, so it must be arranged appropriately
+  reads from usb device just look at "invalidated" tds and the results they got
+  handled tds get reactivated as a ring structure
+    - added as child of the oldest td
+    - queue header already dropped the td, so no issue there
+  
+  this setup ensures that:
+  - the max latency of the device is honored
+  - the client knows the right order of the data
+  - there is no need for an interrupt handler
+    - but must be polled at least max latency * num tds times -> more tds = less time pressure

Added: trunk/payloads/libpayload/drivers/usb/uhci.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/uhci.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/uhci.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,507 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "usb.h"
+#include "uhci.h"
+#include <arch/virtual.h>
+
+static void uhci_start (hci_t *controller);
+static void uhci_stop (hci_t *controller);
+static void uhci_reset (hci_t *controller);
+static void uhci_shutdown (hci_t *controller);
+static int uhci_packet (usbdev_t *dev, int endp, int pid, int toggle,
+			int length, u8 *data);
+static int uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
+static int uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq,
+			 int dalen, u8 *data);
+
+#if 0
+/* dump uhci */
+static void
+uhci_dump (hci_t *controller)
+{
+	printf ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD));
+	printf ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS));
+	printf ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR));
+	printf ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM));
+	printf ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD));
+	printf ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD));
+	printf ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1));
+	printf ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2));
+}
+#endif
+
+static void
+td_dump (td_t *td)
+{
+	printf ("%x packet (at %lx) to %x.%x failed\n", td->pid,
+		virt_to_phys (td), td->dev_addr, td->endp);
+	printf ("td (counter at %x) returns: ", td->counter);
+	printf (" bitstuff err: %x, ", td->status_bitstuff_err);
+	printf (" CRC err: %x, ", td->status_crc_err);
+	printf (" NAK rcvd: %x, ", td->status_nakrcvd);
+	printf (" Babble: %x, ", td->status_babble);
+	printf (" Data Buffer err: %x, ", td->status_databuf_err);
+	printf (" Stalled: %x, ", td->status_stalled);
+	printf (" Active: %x\n", td->status_active);
+	if (td->status_babble)
+		printf (" Babble because of %s\n",
+			td->status_bitstuff_err ? "host" : "device");
+	if (td->status_active)
+		printf (" still active - timeout?\n");
+}
+
+static void
+uhci_reset (hci_t *controller)
+{
+	/* reset */
+	uhci_reg_write16 (controller, USBCMD, 4);
+	mdelay (50);
+	uhci_reg_write16 (controller, USBCMD, 0);
+	mdelay (10);
+	uhci_reg_write16 (controller, USBCMD, 2);
+	while ((uhci_reg_read16 (controller, USBCMD) & 2) != 0)
+		mdelay (1);
+
+	uhci_reg_write32 (controller, FLBASEADD,
+			  (u32) virt_to_phys (UHCI_INST (controller)->
+					      framelistptr));
+	//printf ("framelist at %p\n",UHCI_INST(controller)->framelistptr);
+
+	/* disable irqs */
+	uhci_reg_write16 (controller, USBINTR, 0);
+
+	/* reset framelist index */
+	uhci_reg_write16 (controller, FRNUM, 0);
+
+	uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0);	// max packets, configure flag
+
+	uhci_start (controller);
+}
+
+hci_t *
+uhci_init (pcidev_t addr)
+{
+	int i;
+	hci_t *controller = new_controller ();
+
+	controller->instance = malloc (sizeof (uhci_t));
+	controller->start = uhci_start;
+	controller->stop = uhci_stop;
+	controller->reset = uhci_reset;
+	controller->shutdown = uhci_shutdown;
+	controller->packet = uhci_packet;
+	controller->bulk = uhci_bulk;
+	controller->control = uhci_control;
+	UHCI_INST (controller)->roothub = &(controller->devices[0]);
+
+	controller->bus_address = addr;
+	controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1;	/* ~1 clears the register type indicator that is set to 1 for IO space */
+
+	/* kill legacy support handler */
+	uhci_stop (controller);
+	mdelay (1);
+	uhci_reg_write16 (controller, USBSTS, 0x3f);
+	pci_write_config32 (controller->bus_address, 0xc0, 0x8f00);
+
+	UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t *));	/* 4kb aligned to 4kb */
+	memset (UHCI_INST (controller)->framelistptr, 0,
+		1024 * sizeof (flistp_t));
+
+	UHCI_INST (controller)->qh_intr = memalign (16, sizeof (qh_t));
+	UHCI_INST (controller)->qh_data = memalign (16, sizeof (qh_t));
+	UHCI_INST (controller)->qh_last = memalign (16, sizeof (qh_t));
+
+	UHCI_INST (controller)->qh_intr->headlinkptr.ptr =
+		virt_to_phys (UHCI_INST (controller)->qh_data);
+	UHCI_INST (controller)->qh_intr->headlinkptr.queue_head = 1;
+	UHCI_INST (controller)->qh_intr->elementlinkptr.ptr = 0;
+	UHCI_INST (controller)->qh_intr->elementlinkptr.terminate = 1;
+
+	UHCI_INST (controller)->qh_data->headlinkptr.ptr =
+		virt_to_phys (UHCI_INST (controller)->qh_last);
+	UHCI_INST (controller)->qh_data->headlinkptr.queue_head = 1;
+	UHCI_INST (controller)->qh_data->elementlinkptr.ptr = 0;
+	UHCI_INST (controller)->qh_data->elementlinkptr.terminate = 1;
+
+	UHCI_INST (controller)->qh_last->headlinkptr.ptr = 0;
+	UHCI_INST (controller)->qh_last->headlinkptr.terminate = 1;
+	UHCI_INST (controller)->qh_last->elementlinkptr.ptr = 0;
+	UHCI_INST (controller)->qh_last->elementlinkptr.terminate = 1;
+
+	for (i = 0; i < 1024; i++) {
+		UHCI_INST (controller)->framelistptr[i].ptr =
+			virt_to_phys (UHCI_INST (controller)->qh_intr);
+		UHCI_INST (controller)->framelistptr[i].terminate = 0;
+		UHCI_INST (controller)->framelistptr[i].queue_head = 1;
+	}
+	for (i = 1; i < 128; i++) {
+		init_device_entry (controller, i);
+	}
+	controller->devices[0].controller = controller;
+	controller->devices[0].init = uhci_rh_init;
+	controller->devices[0].init (&controller->devices[0]);
+	uhci_reset (controller);
+	return controller;
+}
+
+static void
+uhci_shutdown (hci_t *controller)
+{
+	if (controller == 0)
+		return;
+	detach_controller (controller);
+	UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
+						  roothub);
+	uhci_reg_mask16 (controller, USBCMD, 0, 0);	// stop work
+	free (UHCI_INST (controller)->framelistptr);
+	free (UHCI_INST (controller)->qh_intr);
+	free (UHCI_INST (controller)->qh_data);
+	free (UHCI_INST (controller)->qh_last);
+	free (UHCI_INST (controller));
+	free (controller);
+}
+
+static void
+uhci_start (hci_t *controller)
+{
+	uhci_reg_mask16 (controller, USBCMD, ~0, 1);	// start work on schedule
+}
+
+static void
+uhci_stop (hci_t *controller)
+{
+	uhci_reg_mask16 (controller, USBCMD, ~1, 0);	// stop work on schedule
+}
+
+#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
+
+static td_t *
+wait_for_completed_qh (hci_t *controller, qh_t *qh)
+{
+	int timeout = 1000;	/* max 30 ms. */
+	void *current = GET_TD (qh->elementlinkptr.ptr);
+	while ((qh->elementlinkptr.terminate == 0) && (timeout-- > 0)) {
+		if (current != GET_TD (qh->elementlinkptr.ptr)) {
+			current = GET_TD (qh->elementlinkptr.ptr);
+			timeout = 1000;
+		}
+		uhci_reg_mask16 (controller, USBSTS, ~0, 0);	// clear resettable registers
+		udelay (30);
+	}
+	return (GET_TD (qh->elementlinkptr.ptr) ==
+		0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr.ptr));
+}
+
+static void
+wait_for_completed_td (hci_t *controller, td_t *td)
+{
+	int timeout = 10000;
+	while ((td->status_active == 1)
+	       && ((uhci_reg_read16 (controller, USBSTS) & 2) == 0)
+	       && (timeout-- > 0)) {
+		uhci_reg_mask16 (controller, USBSTS, ~0, 0);	// clear resettable registers
+		udelay (10);
+	}
+}
+
+static int
+maxlen (int size)
+{
+	return (size - 1) & 0x7ff;
+}
+
+static int
+min (int a, int b)
+{
+	if (a < b)
+		return a;
+	else
+		return b;
+}
+
+static int
+uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq, int dalen,
+	      unsigned char *data)
+{
+	int endp = 0;		/* this is control: always 0 */
+	int mlen = dev->endpoints[0].maxpacketsize;
+	int count = (2 + (dalen + mlen - 1) / mlen);
+	unsigned short req = ((unsigned short *) devreq)[0];
+	int i;
+	td_t *tds = memalign (16, sizeof (td_t) * count);
+	memset (tds, 0, sizeof (td_t) * count);
+	count--;		/* to compensate for 0-indexed array */
+	for (i = 0; i < count; i++) {
+		tds[i].ptr = virt_to_phys (&tds[i + 1]);
+		tds[i].depth_first = 1;
+		tds[i].terminate = 0;
+	}
+	tds[count].ptr = 0;
+	tds[count].depth_first = 1;
+	tds[count].terminate = 1;
+
+	tds[0].pid = SETUP;
+	tds[0].dev_addr = dev->address;
+	tds[0].endp = endp;
+	tds[0].maxlen = maxlen (drlen);
+	tds[0].counter = 3;
+	tds[0].data_toggle = 0;
+	tds[0].lowspeed = dev->lowspeed;
+	tds[0].bufptr = virt_to_phys (devreq);
+	tds[0].status_active = 1;
+
+	int toggle = 1;
+	for (i = 1; i < count; i++) {
+		tds[i].pid = dir;
+		tds[i].dev_addr = dev->address;
+		tds[i].endp = endp;
+		tds[i].maxlen = maxlen (min (mlen, dalen));
+		tds[i].counter = 3;
+		tds[i].data_toggle = toggle;
+		tds[i].lowspeed = dev->lowspeed;
+		tds[i].bufptr = virt_to_phys (data);
+		tds[i].status_active = 1;
+		toggle ^= 1;
+		dalen -= mlen;
+		data += mlen;
+	}
+
+	tds[count].pid = (dir == OUT) ? IN : OUT;
+	tds[count].dev_addr = dev->address;
+	tds[count].endp = endp;
+	tds[count].maxlen = maxlen (0);
+	tds[count].counter = 0;	/* as per linux 2.4.10 */
+	tds[count].data_toggle = 1;
+	tds[count].lowspeed = dev->lowspeed, tds[count].bufptr = 0;
+	tds[count].status_active = 1;
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
+		virt_to_phys (tds);
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
+	td_t *td = wait_for_completed_qh (dev->controller,
+					  UHCI_INST (dev->controller)->
+					  qh_data);
+	int result;
+	if (td == 0) {
+		result = 0;
+	} else {
+		printf ("control packet, req %x\n", req);
+		td_dump (td);
+		result = 1;
+	}
+	free (tds);
+	return result;
+}
+
+static int
+uhci_packet (usbdev_t *dev, int endp, int pid, int toggle, int length,
+	     unsigned char *data)
+{
+	static td_t *td = 0;
+	if (td == 0)
+		td = memalign (16, sizeof (td_t));
+
+	memset (td, 0, sizeof (td_t));
+	td->ptr = 0;
+	td->terminate = 1;
+	td->queue_head = 0;
+
+	td->pid = pid;
+	td->dev_addr = dev->address;
+	td->endp = endp & 0xf;
+	td->maxlen = maxlen (length);
+	if (pid == SETUP)
+		td->counter = 3;
+	else
+		td->counter = 0;
+	td->data_toggle = toggle & 1;
+	td->lowspeed = dev->lowspeed;
+	td->bufptr = virt_to_phys (data);
+
+	td->status_active = 1;
+
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
+		virt_to_phys (td);
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
+	wait_for_completed_td (dev->controller, td);
+	if ((td->status & 0x7f) == 0) {
+		//printf("successfully sent a %x packet to %x.%x\n",pid, dev->address,endp);
+		// success
+		return 0;
+	} else {
+		td_dump (td);
+		return 1;
+	}
+}
+
+static td_t *
+create_schedule (int numpackets)
+{
+	if (numpackets == 0)
+		return 0;
+	td_t *tds = memalign (16, sizeof (td_t) * numpackets);
+	memset (tds, 0, sizeof (td_t) * numpackets);
+	int i;
+	for (i = 0; i < numpackets; i++) {
+		tds[i].ptr = virt_to_phys (&tds[i + 1]);
+		tds[i].terminate = 0;
+		tds[i].queue_head = 0;
+		tds[i].depth_first = 1;
+	}
+	tds[numpackets - 1].ptr = 0;
+	tds[numpackets - 1].terminate = 1;
+	tds[numpackets - 1].queue_head = 0;
+	tds[numpackets - 1].depth_first = 0;
+	return tds;
+}
+
+static void
+fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
+	       int *toggle)
+{
+	td->pid = ep->direction;
+	td->dev_addr = ep->dev->address;
+	td->endp = ep->endpoint & 0xf;
+	td->maxlen = maxlen (length);
+	if (ep->direction == SETUP)
+		td->counter = 3;
+	else
+		td->counter = 0;
+	td->data_toggle = *toggle & 1;
+	td->lowspeed = ep->dev->lowspeed;
+	td->bufptr = virt_to_phys (data);
+
+	td->status_active = 1;
+	*toggle ^= 1;
+}
+
+static int
+run_schedule (usbdev_t *dev, td_t *td)
+{
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
+		virt_to_phys (td);
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
+	UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
+	td = wait_for_completed_qh (dev->controller,
+				    UHCI_INST (dev->controller)->qh_data);
+	if (td == 0) {
+		return 0;
+	} else {
+		td_dump (td);
+		return 1;
+	}
+}
+
+/* finalize == 1: if data is of packet aligned size, add a zero length packet */
+static int
+uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
+{
+	int maxpsize = ep->maxpacketsize;
+	if (maxpsize == 0)
+		fatal ("MaxPacketSize == 0!!!");
+	int numpackets = (size + maxpsize - 1 + finalize) / maxpsize;
+	if (numpackets == 0)
+		return 0;
+	td_t *tds = create_schedule (numpackets);
+	int i = 0, toggle = ep->toggle;
+	while ((size > 0) || ((size == 0) && (finalize != 0))) {
+		fill_schedule (&tds[i], ep, min (size, maxpsize), data,
+			       &toggle);
+		i++;
+		data += maxpsize;
+		size -= maxpsize;
+	}
+	if (run_schedule (ep->dev, tds) == 1) {
+		clear_stall (ep);
+		free (tds);
+		return 1;
+	}
+	ep->toggle = toggle;
+	free (tds);
+	return 0;
+}
+
+void
+uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value)
+{
+	outl (value, ctrl->reg_base + reg);
+}
+
+u32
+uhci_reg_read32 (hci_t *ctrl, usbreg reg)
+{
+	return inl (ctrl->reg_base + reg);
+}
+
+void
+uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value)
+{
+	outw (value, ctrl->reg_base + reg);
+}
+
+u16
+uhci_reg_read16 (hci_t *ctrl, usbreg reg)
+{
+	return inw (ctrl->reg_base + reg);
+}
+
+void
+uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value)
+{
+	outb (value, ctrl->reg_base + reg);
+}
+
+u8
+uhci_reg_read8 (hci_t *ctrl, usbreg reg)
+{
+	return inb (ctrl->reg_base + reg);
+}
+
+void
+uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask)
+{
+	uhci_reg_write32 (ctrl, reg,
+			  (uhci_reg_read32 (ctrl, reg) & andmask) | ormask);
+}
+
+void
+uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask)
+{
+	uhci_reg_write16 (ctrl, reg,
+			  (uhci_reg_read16 (ctrl, reg) & andmask) | ormask);
+}
+
+void
+uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask)
+{
+	uhci_reg_write8 (ctrl, reg,
+			 (uhci_reg_read8 (ctrl, reg) & andmask) | ormask);
+}

Added: trunk/payloads/libpayload/drivers/usb/uhci.h
===================================================================
--- trunk/payloads/libpayload/drivers/usb/uhci.h	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/uhci.h	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __UHCI_H
+#define __UHCI_H
+
+#include <pci.h>
+#include "usb.h"
+
+typedef union {
+	struct {
+		unsigned long terminate:1;
+		unsigned long queue_head:1;
+		unsigned long:2;
+		unsigned long ptr_part:28;
+	};
+	u32 ptr;
+} __attribute__ ((packed)) flistp_t;
+
+typedef struct {
+	union {
+		struct {
+			unsigned long terminate:1;
+			unsigned long queue_head:1;
+			unsigned long depth_first:1;
+			unsigned long:29;
+		} __attribute__ ((packed));
+		u32 ptr;
+	} __attribute__ ((packed));
+
+	volatile unsigned long actlen:11;
+	volatile unsigned long:5;
+	union {
+		struct {
+			unsigned long:1;	// bit 0
+			unsigned long status_bitstuff_err:1;
+			unsigned long status_crc_err:1;
+			unsigned long status_nakrcvd:1;
+			unsigned long status_babble:1;
+			unsigned long status_databuf_err:1;
+			unsigned long status_stalled:1;
+			unsigned long status_active:1;	// bit 7
+		} __attribute__ ((packed));
+		unsigned char status;
+	} __attribute__ ((packed));
+	volatile unsigned long ioc:1;	/* interrupt on complete */
+	volatile unsigned long isochronous:1;
+	volatile unsigned long lowspeed:1;
+	volatile unsigned long counter:2;
+	volatile unsigned long shortpck:1;
+	volatile unsigned long:2;
+
+	unsigned long pid:8;
+	unsigned long dev_addr:7;
+	unsigned long endp:4;
+	unsigned long data_toggle:1;
+	unsigned long:1;
+	unsigned long maxlen:11;
+
+	u32 bufptr;
+
+} __attribute__ ((packed))
+     td_t;
+
+     typedef struct {
+	     flistp_t headlinkptr;
+	     volatile flistp_t elementlinkptr;
+     } __attribute__ ((packed))
+     qh_t;
+
+     typedef enum { USBCMD = 0, USBSTS = 2, USBINTR = 4, FRNUM =
+		     6, FLBASEADD = 8, SOFMOD = 0xc, PORTSC1 = 0x10, PORTSC2 =
+		     0x12
+     } usbreg;
+
+     void uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value);
+     u32 uhci_reg_read32 (hci_t *ctrl, usbreg reg);
+     void uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value);
+     u16 uhci_reg_read16 (hci_t *ctrl, usbreg reg);
+     void uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value);
+     u8 uhci_reg_read8 (hci_t *ctrl, usbreg reg);
+     void uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask);
+     void uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask);
+     void uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask);
+
+     typedef struct uhci {
+	     flistp_t *framelistptr;
+	     qh_t *qh_intr, *qh_data, *qh_last;
+	     usbdev_t *roothub;
+     } uhci_t;
+
+#define UHCI_INST(controller) ((uhci_t*)((controller)->instance))
+
+     hci_t *uhci_init (pcidev_t addr);
+
+     void uhci_rh_init (usbdev_t *dev);
+
+#endif

Added: trunk/payloads/libpayload/drivers/usb/uhci_rh.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/uhci_rh.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/uhci_rh.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload.h>
+#include "uhci.h"
+
+typedef struct {
+	int port[2];
+} rh_inst_t;
+
+#define RH_INST(dev) ((rh_inst_t*)(dev)->data)
+
+static void
+uhci_rh_enable_port (usbdev_t *dev, int port)
+{
+	u16 value;
+	hci_t *controller = dev->controller;
+	if (port == 1)
+		port = PORTSC1;
+	else
+		port = PORTSC2;
+	uhci_reg_mask16 (controller, port, ~(1 << 12), 0);	/* wakeup */
+
+	uhci_reg_mask16 (controller, port, ~0, 1 << 9);	/* reset */
+	mdelay (30);		// >10ms
+	uhci_reg_mask16 (controller, port, ~(1 << 9), 0);
+	mdelay (1);		// >5.3us per spec, <3ms because some devices make trouble
+
+	uhci_reg_mask16 (controller, port, ~0, 1 << 2);	/* enable */
+	do {
+		value = uhci_reg_read16 (controller, port);
+		mdelay (1);
+	} while (((value & (1 << 2)) == 0) && (value & 0x01));
+}
+
+/* disable root hub */
+static void
+uhci_rh_disable_port (usbdev_t *dev, int port)
+{
+	hci_t *controller = dev->controller;
+	port = PORTSC2;
+	if (port == 1)
+		port = PORTSC1;
+	uhci_reg_mask16 (controller, port, ~4, 0);
+	int value;
+	do {
+		value = uhci_reg_read16 (controller, port);
+		mdelay (1);
+	} while ((value & (1 << 2)) != 0);
+}
+
+static void
+uhci_rh_scanport (usbdev_t *dev, int port)
+{
+	int portsc, offset;
+	if (port == 1) {
+		portsc = PORTSC1;
+		offset = 0;
+	} else if (port == 2) {
+		portsc = PORTSC2;
+		offset = 1;
+	} else
+		return;
+	int devno = RH_INST (dev)->port[offset];
+	if (devno != -1) {
+		dev->controller->devices[devno].destroy (&dev->controller->
+							 devices[devno]);
+		init_device_entry (dev->controller, devno);
+		RH_INST (dev)->port[offset] = -1;
+	}
+	uhci_reg_mask16 (dev->controller, portsc, ~0, (1 << 3) | (1 << 2));	// clear port state change, enable port
+
+	if ((uhci_reg_read16 (dev->controller, portsc) & 1) != 0) {
+		int newdev;
+		usbdev_t *newdev_t;
+		// device attached
+
+		uhci_rh_disable_port (dev, port);
+		uhci_rh_enable_port (dev, port);
+
+		int lowspeed =
+			(uhci_reg_read16 (dev->controller, portsc) >> 8) & 1;
+		printf ("%sspeed device\n", (lowspeed == 1) ? "low" : "full");
+
+		newdev = set_address (dev->controller, lowspeed);
+		if (newdev == -1)
+			return;
+		newdev_t = &dev->controller->devices[newdev];
+		RH_INST (dev)->port[offset] = newdev;
+		newdev_t->address = newdev;
+		newdev_t->hub = dev->address;
+		newdev_t->port = portsc;
+		// determine responsible driver
+		newdev_t->init (newdev_t);
+	}
+}
+
+static int
+uhci_rh_report_port_changes (usbdev_t *dev)
+{
+	int stored, real;
+
+	stored = (RH_INST (dev)->port[0] == -1);
+	real = ((uhci_reg_read16 (dev->controller, PORTSC1) & 1) == 0);
+	if (stored != real)
+		return 1;
+
+	stored = (RH_INST (dev)->port[1] == -1);
+	real = ((uhci_reg_read16 (dev->controller, PORTSC2) & 1) == 0);
+	if (stored != real)
+		return 2;
+
+// maybe detach+attach happened between two scans?
+	if ((uhci_reg_read16 (dev->controller, PORTSC1) & 2) > 0)
+		return 1;
+	if ((uhci_reg_read16 (dev->controller, PORTSC2) & 2) > 0)
+		return 2;
+
+// no change
+	return -1;
+}
+
+static void
+uhci_rh_destroy (usbdev_t *dev)
+{
+	uhci_rh_disable_port (dev, 1);
+	uhci_rh_disable_port (dev, 2);
+	free (RH_INST (dev));
+}
+
+static void
+uhci_rh_poll (usbdev_t *dev)
+{
+	int port;
+	while ((port = uhci_rh_report_port_changes (dev)) != -1)
+		uhci_rh_scanport (dev, port);
+}
+
+void
+uhci_rh_init (usbdev_t *dev)
+{
+	dev->destroy = uhci_rh_destroy;
+	dev->poll = uhci_rh_poll;
+
+	uhci_rh_enable_port (dev, 1);
+	uhci_rh_enable_port (dev, 2);
+	dev->data = malloc (sizeof (rh_inst_t));
+	RH_INST (dev)->port[0] = -1;
+	RH_INST (dev)->port[1] = -1;
+
+	/* we can set them here because a root hub _really_ shouldn't
+	   appear elsewhere */
+	dev->address = 0;
+	dev->hub = -1;
+	dev->port = -1;
+}

Added: trunk/payloads/libpayload/drivers/usb/usb.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usb.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usb.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,350 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <config.h>
+#include "usb.h"
+
+hci_t *usb_hcs = 0;
+
+hci_t *
+new_controller ()
+{
+	hci_t *controller = malloc (sizeof (hci_t));
+
+	/* atomic */
+	controller->next = usb_hcs;
+	usb_hcs = controller;
+	/* atomic end */
+
+	return controller;
+}
+
+void
+detach_controller (hci_t *controller)
+{
+	if (controller == 0)
+		return;
+	if (usb_hcs == controller) {
+		usb_hcs = controller->next;
+	} else {
+		hci_t *it = usb_hcs;
+		while (it != 0) {
+			if (it->next == controller) {
+				it->next = controller->next;
+				return;
+			}
+		}
+	}
+}
+
+/**
+ * Polls all hubs on all USB controllers, to find out about device changes
+ */
+void
+usb_poll ()
+{
+	if (usb_hcs == 0)
+		return;
+	hci_t *controller = usb_hcs;
+	while (controller != 0) {
+		int i;
+		for (i = 0; i < 128; i++) {
+			if (controller->devices[i].address != -1) {
+				controller->devices[i].poll (&controller->
+							     devices[i]);
+			}
+		}
+		controller = controller->next;
+	}
+}
+
+void
+init_device_entry (hci_t *controller, int i)
+{
+	controller->devices[i].controller = controller;
+	controller->devices[i].address = -1;
+	controller->devices[i].hub = -1;
+	controller->devices[i].port = -1;
+	controller->devices[i].init = usb_nop_init;
+	controller->devices[i].init (&controller->devices[i]);
+}
+
+void
+set_feature (usbdev_t *dev, int endp, int feature, int rtype)
+{
+	dev_req_t dr;
+
+	dr.bmRequestType = rtype;
+	dr.data_dir = host_to_device;
+	dr.bRequest = SET_FEATURE;
+	dr.wValue = feature;
+	dr.wIndex = endp;
+	dr.wLength = 0;
+	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
+}
+
+void
+get_status (usbdev_t *dev, int intf, int rtype, int len, void *data)
+{
+	dev_req_t dr;
+
+	dr.bmRequestType = rtype;
+	dr.data_dir = device_to_host;
+	dr.bRequest = GET_STATUS;
+	dr.wValue = 0;
+	dr.wIndex = intf;
+	dr.wLength = len;
+	dev->controller->control (dev, IN, sizeof (dr), &dr, len, data);
+}
+
+u8 *
+get_descriptor (usbdev_t *dev, unsigned char bmRequestType, int descType,
+		int descIdx, int langID)
+{
+	u8 buf[8];
+	u8 *result;
+	dev_req_t dr;
+	int size;
+
+	dr.bmRequestType = bmRequestType;
+	dr.data_dir = device_to_host;	// always like this for descriptors
+	dr.bRequest = GET_DESCRIPTOR;
+	dr.wValue = (descType << 8) | descIdx;
+	dr.wIndex = langID;
+	dr.wLength = 8;
+	if (dev->controller->control (dev, IN, sizeof (dr), &dr, 8, buf)) {
+		printf ("getting descriptor size (type %x) failed\n",
+			descType);
+	}
+
+	if (descType == 1) {
+		device_descriptor_t *dd = (device_descriptor_t *) buf;
+		printf ("maxPacketSize0: %x\n", dd->bMaxPacketSize0);
+		if (dd->bMaxPacketSize0 != 0)
+			dev->endpoints[0].maxpacketsize = dd->bMaxPacketSize0;
+	}
+
+	/* special case for configuration descriptors: they carry all their
+	   subsequent descriptors with them, and keep the entire size at a
+	   different location */
+	size = buf[0];
+	if (buf[1] == 2) {
+		int realsize = ((unsigned short *) (buf + 2))[0];
+		size = realsize;
+	}
+	result = malloc (size);
+	memset (result, 0, size);
+	dr.wLength = size;
+	if (dev->controller->
+	    control (dev, IN, sizeof (dr), &dr, size, result)) {
+		printf ("getting descriptor (type %x, size %x) failed\n",
+			descType, size);
+	}
+
+	return result;
+}
+
+void
+set_configuration (usbdev_t *dev)
+{
+	dev_req_t dr;
+
+	dr.bmRequestType = 0;
+	dr.bRequest = SET_CONFIGURATION;
+	dr.wValue = dev->configuration[5];
+	dr.wIndex = 0;
+	dr.wLength = 0;
+	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
+}
+
+int
+clear_stall (endpoint_t *ep)
+{
+	usbdev_t *dev = ep->dev;
+	int endp = ep->endpoint;
+	dev_req_t dr;
+
+	dr.bmRequestType = 0;
+	if (endp != 0) {
+		dr.req_recp = endp_recp;
+	}
+	dr.bRequest = CLEAR_FEATURE;
+	dr.wValue = ENDPOINT_HALT;
+	dr.wIndex = endp;
+	dr.wLength = 0;
+	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
+	return 0;
+}
+
+/* returns free address or -1 */
+static int
+get_free_address (hci_t *controller)
+{
+	int i;
+	for (i = 1; i < 128; i++) {
+		if (controller->devices[i].address != i)
+			return i;
+	}
+	printf ("no free address found\n");
+	return -1;		// no free address
+}
+
+int
+set_address (hci_t *controller, int lowspeed)
+{
+	int adr = get_free_address (controller);	// address to set
+	dev_req_t dr;
+	configuration_descriptor_t *cd;
+	device_descriptor_t *dd;
+
+	memset (&dr, 0, sizeof (dr));
+	dr.data_dir = host_to_device;
+	dr.req_type = standard_type;
+	dr.req_recp = dev_recp;
+	dr.bRequest = SET_ADDRESS;
+	dr.wValue = adr;
+	dr.wIndex = 0;
+	dr.wLength = 0;
+
+	usbdev_t *dev = &controller->devices[adr];
+	// dummy values for registering the address
+	dev->address = 0;
+	dev->lowspeed = lowspeed;
+	dev->endpoints[0].dev = dev;
+	dev->endpoints[0].endpoint = 0;
+	dev->endpoints[0].maxpacketsize = 8;
+	dev->endpoints[0].toggle = 0;
+	dev->endpoints[0].direction = SETUP;
+	mdelay (50);
+	if (dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0)) {
+		printf ("set_address failed\n");
+		return -1;
+	}
+	mdelay (50);
+	dev->address = adr;
+	dev->descriptor =
+		get_descriptor (dev,
+				gen_bmRequestType (device_to_host,
+						   standard_type, dev_recp),
+				1, 0, 0);
+	dd = (device_descriptor_t *) dev->descriptor;
+	printf ("device version: %x.%x\n", dd->bcdUSB >> 8,
+		dd->bcdUSB & 0xff);
+	printf ("device has %x configurations\n", dd->bNumConfigurations);
+	if (dd->bNumConfigurations == 0) {
+		/* device isn't usable */
+		printf ("no usable configuration!\n");
+		dev->address = 0;
+		return -1;
+	}
+	dev->configuration =
+		get_descriptor (dev,
+				gen_bmRequestType (device_to_host,
+						   standard_type, dev_recp),
+				2, 0, 0);
+	cd = (configuration_descriptor_t *) dev->configuration;
+	set_configuration (dev);
+	interface_descriptor_t *interface =
+		(interface_descriptor_t *) (((char *) cd) + cd->bLength);
+	{
+		int i;
+		int num = cd->bNumInterfaces;
+		interface_descriptor_t *current = interface;
+		printf ("device has %x interfaces\n", num);
+		num = (num > 5) ? 5 : num;
+		for (i = 0; i < num; i++) {
+			int j;
+			printf (" #%x has %x endpoints, interface %x:%x, protocol %x\n", current->bInterfaceNumber, current->bNumEndpoints, current->bInterfaceClass, current->bInterfaceSubClass, current->bInterfaceProtocol);
+			endpoint_descriptor_t *endp =
+				(endpoint_descriptor_t *) (((char *) current)
+							   +
+							   current->bLength);
+			if (interface->bInterfaceClass == 0x3)
+				endp = (endpoint_descriptor_t *) (((char *) endp) + ((char *) endp)[0]);	// ignore HID descriptor
+			memset (dev->endpoints, 0, sizeof (dev->endpoints));
+			dev->num_endp = 1;	// 0 always exists
+			dev->endpoints[0].dev = dev;
+			dev->endpoints[0].maxpacketsize = dd->bMaxPacketSize0;
+			dev->endpoints[0].direction = SETUP;
+			dev->endpoints[0].type = CONTROL;
+			for (j = 1; j <= current->bNumEndpoints; j++) {
+				static const char *transfertypes[4] =
+					{ "control", "isochronous", "bulk",
+					"interrupt"
+				};
+				printf ("   #%x: Endpoint %x (%s), max packet size %x, type %s\n", j, endp->bEndpointAddress & 0x7f, ((endp->bEndpointAddress & 0x80) != 0) ? "in" : "out", endp->wMaxPacketSize, transfertypes[endp->bmAttributes]);
+				endpoint_t *ep =
+					&dev->endpoints[dev->num_endp++];
+				ep->dev = dev;
+				ep->endpoint = endp->bEndpointAddress;
+				ep->toggle = 0;
+				ep->maxpacketsize = endp->wMaxPacketSize;
+				ep->direction =
+					((endp->bEndpointAddress & 0x80) ==
+					 0) ? OUT : IN;
+				ep->type = endp->bmAttributes;
+				endp = (endpoint_descriptor_t
+					*) (((char *) endp) + endp->bLength);
+			}
+			current = (interface_descriptor_t *) endp;
+		}
+	}
+	int class = dd->bDeviceClass;
+	if (class == 0)
+		class = interface->bInterfaceClass;
+
+	enum { hid_device = 0x3, msc_device = 0x8, hub_device = 0x9 };
+
+	printf ("device of class %x found\n", class);
+	if (class == hub_device) {
+		printf ("hub found\n");
+#ifdef CONFIG_USB_HUB
+		controller->devices[adr].init = usb_hub_init;
+#else
+		printf ("support not compiled in\n");
+#endif
+	}
+	if (class == hid_device) {
+		printf ("HID found\n");
+#ifdef CONFIG_USB_HID
+		controller->devices[adr].init = usb_hid_init;
+#else
+		printf ("support not compiled in\n");
+#endif
+	}
+	if (class == msc_device) {
+		printf ("MSC found\n");
+#ifdef CONFIG_USB_MSC
+		controller->devices[adr].init = usb_msc_init;
+#else
+		printf ("support not compiled in\n");
+#endif
+	}
+	return adr;
+}

Added: trunk/payloads/libpayload/drivers/usb/usb.h
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usb.h	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usb.h	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,224 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __USB_H
+#define __USB_H
+#include <libpayload.h>
+#include <pci.h>
+
+typedef enum { host_to_device = 0, device_to_host = 1 } dev_req_dir;
+typedef enum { standard_type = 0, class_type = 1, vendor_type =
+		2, reserved_type = 3
+} dev_req_type;
+typedef enum { dev_recp = 0, iface_recp = 1, endp_recp = 2, other_recp = 3
+} dev_req_recp;
+
+typedef enum {
+	GET_STATUS = 0,
+	CLEAR_FEATURE = 1,
+	SET_FEATURE = 3,
+	SET_ADDRESS = 5,
+	GET_DESCRIPTOR = 6,
+	SET_DESCRIPTOR = 7,
+	GET_CONFIGURATION = 8,
+	SET_CONFIGURATION = 9,
+	GET_INTERFACE = 10,
+	SET_INTERFACE = 11,
+	SYNCH_FRAME = 12
+} bRequest_Codes;
+
+typedef enum {
+	ENDPOINT_HALT = 0,
+	DEVICE_REMOTE_WAKEUP = 1,
+	TEST_MODE = 2
+} feature_selectors;
+
+typedef struct {
+	union {
+		struct {
+			dev_req_recp req_recp:5;
+			dev_req_type req_type:2;
+			dev_req_dir data_dir:1;
+		} __attribute__ ((packed));
+		unsigned char bmRequestType;
+	} __attribute__ ((packed));
+	unsigned char bRequest;
+	unsigned short wValue;
+	unsigned short wIndex;
+	unsigned short wLength;
+} __attribute__ ((packed)) dev_req_t;
+
+struct usbdev_hc;
+typedef struct usbdev_hc hci_t;
+
+struct usbdev;
+typedef struct usbdev usbdev_t;
+
+typedef enum { SETUP = 0x2d, IN = 0x69, OUT = 0xe1 } pid_t;
+typedef enum { CONTROL = 0, ISOCHRONOUS = 1, BULK = 2, INTERRUPT = 3
+} endpoint_type;
+
+typedef struct {
+	usbdev_t *dev;
+	int endpoint;
+	pid_t direction;
+	int toggle;
+	int maxpacketsize;
+	endpoint_type type;
+} endpoint_t;
+
+
+struct usbdev {
+	hci_t *controller;
+	endpoint_t endpoints[32];
+	int num_endp;
+	int address;		// usb address
+	int hub;		// hub, device is attached to
+	int port;		// port where device is attached
+	int lowspeed;		// 1 if lowspeed device
+	void *data;
+	u8 *descriptor;
+	u8 *configuration;
+	void (*init) (usbdev_t *dev);
+	void (*destroy) (usbdev_t *dev);
+	void (*poll) (usbdev_t *dev);
+};
+
+struct usbdev_hc {
+	struct usbdev_hc *next;
+	pcidev_t bus_address;
+	u32 reg_base;
+	usbdev_t devices[128];	// dev 0 is root hub, 127 is last addressable
+	void (*start) (hci_t *controller);
+	void (*stop) (hci_t *controller);
+	void (*reset) (hci_t *controller);
+	void (*shutdown) (hci_t *controller);
+	int (*packet) (usbdev_t *dev, int endp, int pid, int toggle,
+		       int length, u8 *data);
+	int (*bulk) (endpoint_t *ep, int size, u8 *data, int finalize);
+	int (*control) (usbdev_t *dev, pid_t pid, int dr_length,
+			void *devreq, int data_length, u8 *data);
+	void *instance;
+};
+
+typedef struct {
+	unsigned char bDescLength;
+	unsigned char bDescriptorType;
+	unsigned char bNbrPorts;
+	union {
+		struct {
+			unsigned long logicalPowerSwitchingMode:2;
+			unsigned long isCompoundDevice:1;
+			unsigned long overcurrentProtectionMode:2;
+			unsigned long ttThinkTime:2;
+			unsigned long arePortIndicatorsSupported:1;
+			unsigned long:8;
+		} __attribute__ ((packed));
+		unsigned short wHubCharacteristics;
+	} __attribute__ ((packed));
+	unsigned char bPowerOn2PwrGood;
+	unsigned char bHubContrCurrent;
+	char DeviceRemovable[];
+} __attribute__ ((packed)) hub_descriptor_t;
+
+typedef struct {
+	unsigned char bLength;
+	unsigned char bDescriptorType;
+	unsigned short bcdUSB;
+	unsigned char bDeviceClass;
+	unsigned char bDeviceSubClass;
+	unsigned char bDeviceProtocol;
+	unsigned char bMaxPacketSize0;
+	unsigned short idVendor;
+	unsigned short idProduct;
+	unsigned short bcdDevice;
+	unsigned char iManufacturer;
+	unsigned char iProduct;
+	unsigned char iSerialNumber;
+	unsigned char bNumConfigurations;
+} __attribute__ ((packed)) device_descriptor_t;
+
+typedef struct {
+	unsigned char bLength;
+	unsigned char bDescriptorType;
+	unsigned short wTotalLength;
+	unsigned char bNumInterfaces;
+	unsigned char bConfigurationValue;
+	unsigned char iConfiguration;
+	unsigned char bmAttributes;
+	unsigned char bMaxPower;
+} __attribute__ ((packed)) configuration_descriptor_t;
+
+typedef struct {
+	unsigned char bLength;
+	unsigned char bDescriptorType;
+	unsigned char bInterfaceNumber;
+	unsigned char bAlternateSetting;
+	unsigned char bNumEndpoints;
+	unsigned char bInterfaceClass;
+	unsigned char bInterfaceSubClass;
+	unsigned char bInterfaceProtocol;
+	unsigned char iInterface;
+} __attribute__ ((packed)) interface_descriptor_t;
+
+typedef struct {
+	unsigned char bLength;
+	unsigned char bDescriptorType;
+	unsigned char bEndpointAddress;
+	unsigned char bmAttributes;
+	unsigned short wMaxPacketSize;
+	unsigned char bInterval;
+} __attribute__ ((packed)) endpoint_descriptor_t;
+
+hci_t *new_controller (void);
+void detach_controller (hci_t *controller);
+void usb_poll (void);
+void init_device_entry (hci_t *controller, int num);
+
+void set_feature (usbdev_t *dev, int endp, int feature, int rtype);
+void get_status (usbdev_t *dev, int endp, int rtype, int len, void *data);
+int clear_stall (endpoint_t *ep);
+
+void usb_nop_init (usbdev_t *dev);
+void usb_hub_init (usbdev_t *dev);
+void usb_hid_init (usbdev_t *dev);
+void usb_msc_init (usbdev_t *dev);
+
+int set_address (hci_t *controller, int lowspeed);
+
+u8 *get_descriptor (usbdev_t *dev, unsigned char bmRequestType,
+		    int descType, int descIdx, int langID);
+
+static inline unsigned char
+gen_bmRequestType (dev_req_dir dir, dev_req_type type, dev_req_recp recp)
+{
+	return (dir << 7) | (type << 5) | recp;
+}
+
+#endif

Added: trunk/payloads/libpayload/drivers/usb/usb_dev.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usb_dev.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usb_dev.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "usb.h"
+
+static void
+usb_nop_destroy (usbdev_t *dev)
+{
+	if (dev->descriptor != 0)
+		free (dev->descriptor);
+	usb_nop_init (dev);
+	dev->address = -1;
+	dev->hub = -1;
+	dev->port = -1;
+}
+
+static void
+usb_nop_poll (usbdev_t *dev)
+{
+	return;
+}
+
+void
+usb_nop_init (usbdev_t *dev)
+{
+	dev->descriptor = 0;
+	dev->destroy = usb_nop_destroy;
+	dev->poll = usb_nop_poll;
+}

Added: trunk/payloads/libpayload/drivers/usb/usbdisk.h
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usbdisk.h	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usbdisk.h	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __USBDISK_H
+#define __USBDISK_H
+#include "usb.h"
+
+/**
+ * To be implemented by libpayload-client. It's called by the USB stack
+ * when a new USB storage device is found, so the client has the chance
+ * to know about it.
+ *
+ * @param dev descriptor for the USB storage device
+ */
+void usbdisk_create (usbdev_t *dev);
+
+/**
+ * To be implemented by libpayload-client. It's called by the USB stack
+ * when it finds out that a USB storage device is removed.
+ *
+ * @param dev descriptor for the USB storage device
+ */
+void usbdisk_remove (usbdev_t *dev);
+
+#endif

Added: trunk/payloads/libpayload/drivers/usb/usbhid.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usbhid.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usbhid.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "usb.h"
+
+enum { hid_subclass_none = 0, hid_subclass_boot = 1 };
+enum { hid_proto_boot = 0, hid_proto_report = 1 };
+enum { hid_boot_proto_none = 0, hid_boot_proto_keyboard =
+		1, hid_boot_proto_mouse = 2
+};
+static const char *boot_protos[3] = { "(none)", "keyboard", "mouse" };
+enum { GET_REPORT = 0x1, GET_IDLE = 0x2, GET_PROTOCOL = 0x3, SET_REPORT =
+		0x9, SET_IDLE = 0xa, SET_PROTOCOL = 0xb
+};
+
+static void
+usb_hid_destroy (usbdev_t *dev)
+{
+}
+
+int keypress;
+char keymap[256] = {
+	-1, -1, -1, -1, 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k',
+	'l',
+	'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z',
+	'1', '2',
+	'3', '4', '5', '6', '7', '8', '9', '0', '\n', TERM_ESC,
+	TERM_BACKSPACE, TERM_TAB, ' ', '-', '=', '[',
+	']', '\\', -1, ';', '\'', '`', ',', '.', '/', -1, -1, -1, -1, -1, -1,
+	-1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, TERM_HOME, TERM_PPAGE, -1,
+	TERM_END, TERM_NPAGE, TERM_RIGHT,
+	TERM_LEFT, TERM_DOWN, TERM_UP, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+};
+
+
+static void
+usb_hid_poll (usbdev_t *dev)
+{
+	char buf[8];
+	static int toggle = 0;
+	// hardcode to endpoint 1, 8 bytes
+	dev->controller->packet (dev, 1, IN, toggle, 8, buf);
+	toggle ^= 1;
+	// FIXME: manage buf[0]=special keys, too
+	keypress = keymap[buf[2]];
+	if ((keypress == -1) && (buf[2] != 0)) {
+		printf ("%x %x %x %x %x %x %x %x\n", buf[0], buf[1], buf[2],
+			buf[3], buf[4], buf[5], buf[6], buf[7]);
+	}
+}
+
+int (*oldhook) (void);
+
+int
+hookfunc (void)
+{
+	int key;
+	if (oldhook != 0)
+		key = oldhook ();
+	if (key == -1)
+		key = keypress;
+	return key;
+}
+
+void
+usb_hid_init (usbdev_t *dev)
+{
+
+	configuration_descriptor_t *cd = dev->configuration;
+	interface_descriptor_t *interface = ((char *) cd) + cd->bLength;
+
+	if (interface->bInterfaceSubClass == hid_subclass_boot) {
+		printf ("  supports boot interface..\n");
+		printf ("  it's a %s\n",
+			boot_protos[interface->bInterfaceProtocol]);
+		if (interface->bInterfaceProtocol == hid_boot_proto_keyboard) {
+			printf ("  activating...\n");
+			dev_req_t dr;
+			// set_protocol(hid_proto_boot)
+			dr.data_dir = host_to_device;
+			dr.req_type = class_type;
+			dr.req_recp = iface_recp;
+			dr.bRequest = SET_PROTOCOL;
+			dr.wValue = hid_proto_boot;
+			dr.wIndex = interface->bInterfaceNumber;
+			dr.wLength = 0;
+			dev->controller->control (dev, OUT,
+						  sizeof (dev_req_t), &dr, 0,
+						  0);
+
+			// only add here, because we only support boot-keyboard HID devices
+			// FIXME: make this a real console input driver instead, once the API is there
+			dev->destroy = usb_hid_destroy;
+			dev->poll = usb_hid_poll;
+			oldhook = getkey_hook;
+			getkey_hook = hookfunc;
+		}
+	}
+}

Added: trunk/payloads/libpayload/drivers/usb/usbhub.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usbhub.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usbhub.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "usb.h"
+
+// assume that host_to_device is overwritten if necessary
+#define DR_PORT gen_bmRequestType(host_to_device, class_type, other_recp)
+#define PORT_RESET 0x4
+#define PORT_POWER 0x8
+
+typedef struct {
+	int num_ports;
+	int *ports;
+	hub_descriptor_t *descriptor;
+} usbhub_inst_t;
+
+#define HUB_INST(dev) ((usbhub_inst_t*)(dev)->data)
+
+static void
+usb_hub_destroy (usbdev_t *dev)
+{
+	free (HUB_INST (dev)->ports);
+	free (HUB_INST (dev)->descriptor);
+	free (HUB_INST (dev));
+}
+
+static void
+usb_hub_scanport (usbdev_t *dev, int port)
+{
+	int newdev;
+	unsigned short buf[2];
+	usbdev_t *newdev_t;
+
+	get_status (dev, port, DR_PORT, 4, buf);
+	int portstatus = ((buf[0] & 1) == 0);
+	int datastatus = (HUB_INST (dev)->ports[port] == -1);
+	if (portstatus == datastatus)
+		return;		// no change - FIXME: read right fields for that test
+
+	if (!datastatus) {
+		int devno = HUB_INST (dev)->ports[port];
+		if (devno == -1)
+			fatal ("FATAL: illegal devno!\n");
+		dev->controller->devices[devno].destroy (&dev->controller->
+							 devices[devno]);
+		init_device_entry (dev->controller, devno);
+		HUB_INST (dev)->ports[port] = -1;
+		return;
+	}
+
+	set_feature (dev, port, PORT_RESET, DR_PORT);
+	mdelay (20);
+
+	get_status (dev, port, DR_PORT, 4, buf);
+	int lowspeed = (buf[0] >> 9) & 1;
+
+	newdev = set_address (dev->controller, lowspeed);
+	if (newdev == -1)
+		return;
+	newdev_t = &dev->controller->devices[newdev];
+
+	HUB_INST (dev)->ports[port] = newdev;
+	newdev_t->address = newdev;
+	newdev_t->hub = dev->address;
+	newdev_t->port = port;
+	// determine responsible driver
+	newdev_t->init (newdev_t);
+}
+
+static int
+usb_hub_report_port_changes (usbdev_t *dev)
+{
+	int port;
+	unsigned short buf[2];
+	for (port = 1; port <= HUB_INST (dev)->num_ports; port++) {
+		get_status (dev, port, DR_PORT, 4, buf);
+		// FIXME: proper change detection
+		int portstatus = ((buf[0] & 1) == 0);
+		int datastatus = (HUB_INST (dev)->ports[port] == -1);
+		if (portstatus != datastatus)
+			return port;
+	}
+
+// no change
+	return -1;
+}
+
+static void
+usb_hub_enable_port (usbdev_t *dev, int port)
+{
+	set_feature (dev, port, PORT_POWER, DR_PORT);
+	mdelay (20);
+}
+
+#if 0
+static void
+usb_hub_disable_port (usbdev_t *dev, int port)
+{
+}
+#endif
+
+static void
+usb_hub_poll (usbdev_t *dev)
+{
+	int port;
+	while ((port = usb_hub_report_port_changes (dev)) != -1)
+		usb_hub_scanport (dev, port);
+}
+
+void
+usb_hub_init (usbdev_t *dev)
+{
+	int i;
+	dev->destroy = usb_hub_destroy;
+	dev->poll = usb_hub_poll;
+
+	dev->data = malloc (sizeof (usbhub_inst_t));
+
+	HUB_INST (dev)->descriptor =
+		(hub_descriptor_t *) get_descriptor (dev,
+						     gen_bmRequestType
+						     (device_to_host,
+						      class_type, dev_recp),
+						     0x29, 0, 0);
+	HUB_INST (dev)->num_ports = HUB_INST (dev)->descriptor->bNbrPorts;
+	HUB_INST (dev)->ports =
+		malloc (sizeof (int) * (HUB_INST (dev)->num_ports + 1));
+	for (i = 1; i <= HUB_INST (dev)->num_ports; i++)
+		HUB_INST (dev)->ports[i] = -1;
+	for (i = 1; i <= HUB_INST (dev)->num_ports; i++)
+		usb_hub_enable_port (dev, i);
+}

Added: trunk/payloads/libpayload/drivers/usb/usbinit.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usbinit.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usbinit.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <config.h>
+#include "usb.h"
+#include "uhci.h"
+#include "usbdisk.h"
+
+/**
+ * Initializes USB controller attached to PCI
+ *
+ * @param bus PCI bus number
+ * @param dev PCI device id at bus
+ * @param func function id of the controller
+ */
+int
+usb_controller_initialize (int bus, int dev, int func)
+{
+	u32 class;
+	u32 devclass;
+	u32 prog_if;
+	pcidev_t addr;
+	u32 pciid;
+
+	addr = PCI_DEV (bus, dev, func);
+	class = pci_read_config32 (addr, 8);
+	pciid = pci_read_config32 (addr, 0);
+
+	devclass = class >> 16;
+	prog_if = (class >> 8) & 0xff;
+
+	/* enable busmaster */
+#define PCI_COMMAND 4
+#define PCI_COMMAND_MASTER 4
+	pci_write_config32 (addr, PCI_COMMAND,
+			    pci_read_config32 (addr,
+					       PCI_COMMAND) |
+			    PCI_COMMAND_MASTER);
+
+	if (devclass == 0xc03) {
+		printf ("%02x:%02x.%x %04x:%04x.%d ", 0, dev, func,
+			pciid >> 16, pciid & 0xFFFF, func);
+		if (prog_if == 0) {
+			printf ("UHCI controller\n");
+#ifdef CONFIG_USB_UHCI
+			uhci_init (addr);
+			usb_poll ();
+			usb_poll ();
+#else
+			printf ("Not supported.\n");
+#endif
+		}
+		if (prog_if == 0x10) {
+			printf ("OHCI controller\n");
+#ifdef CONFIG_USB_OHCI
+			// ohci_init(addr);
+#else
+			printf ("Not supported.\n");
+#endif
+
+		}
+		if (prog_if == 0x20) {
+			printf ("EHCI controller\n");
+#ifdef CONFIG_USB_EHCI
+			// ehci_init(addr);
+#else
+			printf ("Not supported.\n");
+#endif
+
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * Initialize all USB controllers attached to PCI.
+ */
+int
+usb_initialize (void)
+{
+	int bus, dev, func;
+	for (bus = 0; bus < 256; bus++)
+		for (dev = 0; dev < 32; dev++)
+			for (func = 0; func < 8; func++)
+				usb_controller_initialize (bus, dev, func);
+	return 0;
+}
+
+int
+usb_exit (void)
+{
+	return 0;
+}

Added: trunk/payloads/libpayload/drivers/usb/usbmsc.c
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usbmsc.c	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usbmsc.c	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,397 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/endian.h>
+#include "usb.h"
+#include "usbmsc.h"
+#include "usbdisk.h"
+
+enum {
+	msc_subclass_rbc = 0x1,
+	msc_subclass_mmc2 = 0x2,
+	msc_subclass_qic157 = 0x3,
+	msc_subclass_ufi = 0x4,
+	msc_subclass_sff8070i = 0x5,
+	msc_subclass_scsitrans = 0x6
+};
+static const char *msc_subclass_strings[7] = {
+	"(none)",
+	"RBC",
+	"MMC-2",
+	"QIC-157",
+	"UFI",
+	"SFF-8070i",
+	"SCSI transparent"
+};
+enum {
+	msc_proto_cbi_wcomp = 0x0,
+	msc_proto_cbi_wocomp = 0x1,
+	msc_proto_bulk_only = 0x50
+};
+static const char *msc_protocol_strings[0x51] = {
+	"Control/Bulk/Interrupt protocol (with command completion interrupt)",
+	"Control/Bulk/Interrupt protocol (with no command completion interrupt)",
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	"Bulk-Only Transport"
+};
+
+
+static void
+usb_msc_destroy (usbdev_t *dev)
+{
+	usbdisk_remove (dev);
+	free (dev->data);
+	dev->data = 0;
+}
+
+static void
+usb_msc_poll (usbdev_t *dev)
+{
+}
+
+const int DEV_RESET = 0xff;
+const int GET_MAX_LUN = 0xfe;
+
+const unsigned int cbw_signature = 0x43425355;
+const unsigned int csw_signature = 0x53425355;
+
+typedef struct {
+	unsigned int dCBWSignature;
+	unsigned int dCBWTag;
+	unsigned int dCBWDataTransferLength;
+	unsigned char bmCBWFlags;
+	unsigned long bCBWLUN:4;
+	unsigned long:4;
+	unsigned long bCBWCBLength:5;
+	unsigned long:3;
+	unsigned char CBWCB[31 - 15];
+} __attribute__ ((packed))
+     cbw_t;
+
+     typedef struct {
+	     unsigned int dCSWSignature;
+	     unsigned int dCSWTag;
+	     unsigned int dCSWDataResidue;
+	     unsigned char bCSWStatus;
+     } __attribute__ ((packed))
+     csw_t;
+
+     static void
+       reset_transport (usbdev_t *dev)
+{
+	dev_req_t dr;
+	memset (&dr, 0, sizeof (dr));
+	dr.bmRequestType = 0;
+	dr.data_dir = host_to_device;
+#ifndef QEMU
+	dr.req_type = class_type;
+	dr.req_recp = iface_recp;
+#endif
+	dr.bRequest = DEV_RESET;
+	dr.wValue = 0;
+	dr.wIndex = 0;
+	dr.wLength = 0;
+	dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0);
+	clear_stall (MSC_INST (dev)->bulk_in);
+	clear_stall (MSC_INST (dev)->bulk_out);
+}
+
+/* device may stall this command, so beware! */
+static int
+get_max_luns (usbdev_t *dev)
+{
+	unsigned char luns = 75;
+	dev_req_t dr;
+	dr.bmRequestType = 0;
+	dr.data_dir = device_to_host;
+#ifndef QEMU
+	dr.req_type = class_type;
+	dr.req_recp = iface_recp;
+#endif
+	dr.bRequest = GET_MAX_LUN;
+	dr.wValue = 0;
+	dr.wIndex = 0;
+	dr.wLength = 1;
+	if (dev->controller->control (dev, IN, sizeof (dr), &dr, 1, &luns)) {
+		luns = 0;	// assume only 1 lun if req fails
+	}
+	return luns;
+}
+
+int tag;
+int lun = 0;
+
+static void
+wrap_cbw (cbw_t *cbw, int datalen, cbw_direction dir, const u8 *cmd,
+	  int cmdlen)
+{
+	memset (cbw, 0, sizeof (cbw_t));
+
+	cbw->dCBWSignature = cbw_signature;
+	cbw->dCBWTag = tag++;
+	cbw->bCBWLUN = lun;	// static value per device
+
+	cbw->dCBWDataTransferLength = datalen;
+	cbw->bmCBWFlags = dir;
+	memcpy (cbw->CBWCB, cmd, sizeof (cbw->CBWCB));
+	cbw->bCBWCBLength = cmdlen;
+}
+
+static void
+get_csw (endpoint_t *ep, csw_t *csw)
+{
+	ep->dev->controller->bulk (ep, sizeof (csw_t), (u8 *) csw, 1);
+}
+
+static int
+execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen,
+		 u8 *buf, int buflen)
+{
+	cbw_t cbw;
+	csw_t csw;
+
+	int always_succeed = 0;
+	if ((cb[0] == 0x1b) && (cb[4] == 1)) {	//start command, always succeed
+		always_succeed = 1;
+	}
+	wrap_cbw (&cbw, buflen, dir, cb, cblen);
+	if (dev->controller->
+	    bulk (MSC_INST (dev)->bulk_out, sizeof (cbw), (u8 *) &cbw, 0)) {
+		clear_stall (MSC_INST (dev)->bulk_out);
+		return 1;
+	}
+	mdelay (10);
+	if (dir == cbw_direction_data_in) {
+		if (dev->controller->
+		    bulk (MSC_INST (dev)->bulk_in, buflen, buf, 0)) {
+			clear_stall (MSC_INST (dev)->bulk_in);
+			return 1;
+		}
+	} else {
+		if (dev->controller->
+		    bulk (MSC_INST (dev)->bulk_out, buflen, buf, 0)) {
+			clear_stall (MSC_INST (dev)->bulk_out);
+			return 1;
+		}
+	}
+	get_csw (MSC_INST (dev)->bulk_in, &csw);
+	if (always_succeed == 1) {
+		// return success, regardless of message
+		return 0;
+	}
+	if (csw.bCSWStatus == 2) {
+		// phase error, reset transport
+		reset_transport (dev);
+		return 1;
+	}
+	if (csw.bCSWStatus == 0) {
+		// no error, exit
+		return 0;
+	}
+	// error "check condition" or reserved error
+	return 1;
+}
+
+typedef struct {
+	unsigned char command;	//0
+	unsigned char res1;	//1
+	unsigned int block;	//2-5
+	unsigned char res2;	//6
+	unsigned short numblocks;	//7-8
+	unsigned char res3;	//9 - the block is 10 bytes long
+} __attribute__ ((packed)) cmdblock_t;
+
+typedef struct {
+	unsigned char command;	//0
+	unsigned char res1;	//1
+	unsigned char res2;	//2
+	unsigned char res3;	//3
+	unsigned char lun;	//4
+	unsigned char res4;	//5
+} __attribute__ ((packed)) cmdblock6_t;
+
+
+/**
+ * Reads or writes a number of sequential blocks on a USB storage device.
+ * As it uses the READ(10) SCSI-2 command, it's limited to storage devices
+ * of at most 2TB. It assumes sectors of 512 bytes.
+ *
+ * @param dev device to access
+ * @param start first sector to access
+ * @param n number of sectors to access
+ * @param dir direction of access: cbw_direction_data_in == read, cbw_direction_data_out == write
+ * @param buf buffer to read into or write from. Must be at least n*512 bytes
+ * @return 0 on success, 1 on failure
+ */
+int
+readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf)
+{
+	cmdblock_t cb;
+	memset (&cb, 0, sizeof (cb));
+	if (dir == cbw_direction_data_in) {
+		// read
+		cb.command = 0x28;
+	} else {
+		// write
+		cb.command = 0x2a;
+	}
+	cb.block = ntohl (start);
+	cb.numblocks = ntohw (n);
+	return execute_command (dev, dir, (u8 *) &cb, sizeof (cb), buf,
+				n * 512);
+}
+
+static int
+test_unit_ready (usbdev_t *dev)
+{
+	cmdblock6_t cb;
+	memset (&cb, 0, sizeof (cb));	// full initialization for T-U-R
+	return execute_command (dev, cbw_direction_data_out, (u8 *) &cb,
+				sizeof (cb), 0, 0);
+}
+
+static int
+spin_up (usbdev_t *dev)
+{
+	cmdblock6_t cb;
+	memset (&cb, 0, sizeof (cb));
+	cb.command = 0x1b;
+	cb.lun = 1;
+	return execute_command (dev, cbw_direction_data_out, (u8 *) &cb,
+				sizeof (cb), 0, 0);
+}
+
+static void
+read_capacity (usbdev_t *dev)
+{
+	cmdblock_t cb;
+	memset (&cb, 0, sizeof (cb));
+	cb.command = 0x25;	// read capacity
+	u8 buf[8];
+	int count = 0;
+	while ((count++ < 20)
+	       &&
+	       (execute_command
+		(dev, cbw_direction_data_in, (u8 *) &cb, sizeof (cb), buf,
+		 8) == 1));
+	if (count >= 20) {
+		// still not successful, assume 2tb in 512byte sectors, which is just the same garbage as any other number, but probably reasonable.
+		printf ("assuming 2TB in 512byte sectors as READ CAPACITY didn't answer.\n");
+		MSC_INST (dev)->numblocks = 0xffffffff;
+		MSC_INST (dev)->blocksize = 512;
+	} else {
+		MSC_INST (dev)->numblocks = ntohl (*(u32 *) buf) + 1;
+		MSC_INST (dev)->blocksize = ntohl (*(u32 *) (buf + 4));
+	}
+	printf ("  has %d blocks sized %db\n", MSC_INST (dev)->numblocks,
+		MSC_INST (dev)->blocksize);
+}
+
+void
+usb_msc_init (usbdev_t *dev)
+{
+	int i, timeout;
+
+	dev->destroy = usb_msc_destroy;
+	dev->poll = usb_msc_poll;
+
+	configuration_descriptor_t *cd =
+		(configuration_descriptor_t *) dev->configuration;
+	interface_descriptor_t *interface =
+		(interface_descriptor_t *) (((char *) cd) + cd->bLength);
+
+	printf ("  it uses %s command set\n",
+		msc_subclass_strings[interface->bInterfaceSubClass]);
+	printf ("  it uses %s protocol\n",
+		msc_protocol_strings[interface->bInterfaceProtocol]);
+
+	if ((interface->bInterfaceProtocol != 0x50)
+	    || (interface->bInterfaceSubClass != 6)) {
+		/* Other protocols, such as ATAPI don't seem to be very popular. looks like ATAPI would be really easy to add, if necessary. */
+		printf ("  Only SCSI over Bulk is supported.\n");
+		return;
+	}
+
+	dev->data = malloc (sizeof (usbmsc_inst_t));
+	MSC_INST (dev)->bulk_in = 0;
+	MSC_INST (dev)->bulk_out = 0;
+
+	for (i = 1; i <= dev->num_endp; i++) {
+		if (dev->endpoints[i].endpoint == 0)
+			continue;
+		if (dev->endpoints[i].type != BULK)
+			continue;
+		if ((dev->endpoints[i].direction == IN)
+		    && (MSC_INST (dev)->bulk_in == 0))
+			MSC_INST (dev)->bulk_in = &dev->endpoints[i];
+		if ((dev->endpoints[i].direction == OUT)
+		    && (MSC_INST (dev)->bulk_out == 0))
+			MSC_INST (dev)->bulk_out = &dev->endpoints[i];
+	}
+
+	if (MSC_INST (dev)->bulk_in == 0)
+		fatal ("couldn't find bulk-in endpoint");
+	if (MSC_INST (dev)->bulk_out == 0)
+		fatal ("couldn't find bulk-out endpoint");
+	printf ("  using endpoint %x as in, %x as out\n",
+		MSC_INST (dev)->bulk_in->endpoint,
+		MSC_INST (dev)->bulk_out->endpoint);
+
+	printf ("  has %d luns\n", get_max_luns (dev) + 1);
+
+	printf ("  Waiting for device to become ready... ");
+	timeout = 10;
+	while (test_unit_ready (dev) && --timeout) {
+		mdelay (100);
+		printf (".");
+	}
+	if (test_unit_ready (dev)) {
+		printf ("timeout. Device not ready. Still trying...\n");
+	} else {
+		printf ("ok.\n");
+	}
+
+	printf ("  spin up");
+	for (i = 0; i < 30; i++) {
+		printf (".");
+		if (!spin_up (dev)) {
+			printf (" OK.");
+			break;
+		}
+		mdelay (100);
+	}
+	printf ("\n");
+
+	read_capacity (dev);
+	usbdisk_create (dev);
+}

Added: trunk/payloads/libpayload/drivers/usb/usbmsc.h
===================================================================
--- trunk/payloads/libpayload/drivers/usb/usbmsc.h	                        (rev 0)
+++ trunk/payloads/libpayload/drivers/usb/usbmsc.h	2008-09-02 16:06:22 UTC (rev 3560)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __USBMSC_H
+#define __USBMSC_H
+typedef struct {
+	unsigned int blocksize;
+	unsigned int numblocks;
+	endpoint_t *bulk_in;
+	endpoint_t *bulk_out;
+} usbmsc_inst_t;
+
+#define MSC_INST(dev) ((usbmsc_inst_t*)(dev)->data)
+
+typedef enum { cbw_direction_data_in = 0x80, cbw_direction_data_out = 0
+} cbw_direction;
+
+int readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir,
+		      u8 *buf);
+
+#endif




From patrick at georgi-clan.de  Tue Sep  2 18:07:31 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 02 Sep 2008 18:07:31 +0200
Subject: [coreboot] libpayload: memalign, take 2
In-Reply-To: <20080902145002.GE15026@cosmic.amd.com>
References: <48BBEDF1.6030903@georgi-clan.de>
	<20080902145002.GE15026@cosmic.amd.com>
Message-ID: <48BD64C2.4040202@georgi-clan.de>

Jordan Crouse schrieb:
>> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>>     
>
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>
>   
Thanks, r3559



From patrick at georgi-clan.de  Tue Sep  2 18:08:06 2008
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 02 Sep 2008 18:08:06 +0200
Subject: [coreboot] libpayload: USB stack
In-Reply-To: <20080902150320.GG15026@cosmic.amd.com>
References: <48BD0218.8000605@georgi-clan.de>
	<20080902150320.GG15026@cosmic.amd.com>
Message-ID: <48BD64E6.3060003@georgi-clan.de>

Jordan Crouse schrieb:
>> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>>     
> Acked-by: Jordan Crouse <jordan.crouse at amd.com>
>   
Thanks, r3560



From mats.andersson at gisladisker.se  Tue Sep  2 22:13:20 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Tue, 02 Sep 2008 22:13:20 +0200
Subject: [coreboot] Using only one romcc copy
In-Reply-To: <48BC6F16.8000309@gmx.net>
Message-ID: <E1KacFc-0006Z2-Sz@aun.bellman.mea>

Hello Carl-Daniel,

I did one round of timing the build processes:

Original make command:                      0m42.323s
My reduction and a clean start:             0m30.955s
After that a 'make clean' and renewed make: 0m23.081s

The timings might not be typical, but the time saving seems
to be substantial in the 'middle case' where only one romcc
needs to be built, as well as in the last case were romcc
is fully reused for both rom-images.

Since I only have used coreboot-v2, I have no knowledge
whether my utility could be applied also to coreboot-v3.

Best regards

Mats Erik Andersson


>Hi Mats,
>
>nice work.
>
>On 02.09.2008 00:13, Mats Erik Andersson wrote:
>> I submit here a little utility that slightly rebuilds the python
>> generated makefiles
>>
>> 	targets/*/*/Makefile
>> 	targets/*/*/normal/Makefile
>> 	targets/*/*/fallback/Makefile
>>
>> in order to use a common copy of romcc, and to leave this compiler
>> until 'make build-clean' is issued. If the result is to peoples
>> liking, the corresponding changes should be implemented in the
>> master copies used by 'buildtargets'.
>>   
>
>Have you measured the speedup for this? Is it noticeable?
>
>Regards,
>Carl-Daniel
>
>-- 
>http://www.hailfinger.org/




From joe at settoplinux.org  Wed Sep  3 02:53:46 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 02 Sep 2008 20:53:46 -0400
Subject: [coreboot] libpayload: USB stack
In-Reply-To: <48BD64E6.3060003@georgi-clan.de>
References: <48BD0218.8000605@georgi-clan.de>
	<20080902150320.GG15026@cosmic.amd.com>
	<48BD64E6.3060003@georgi-clan.de>
Message-ID: <d0eae812befe3ed1ee70ae5a61faad71@imap.1and1.com>




On Tue, 02 Sep 2008 18:08:06 +0200, Patrick Georgi <patrick at georgi-clan.de>
wrote:
> Jordan Crouse schrieb:
>>> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>>>
>> Acked-by: Jordan Crouse <jordan.crouse at amd.com>
>>
> Thanks, r3560
> 
YAHOO!!!
Sorry I wasn't much help Patrick, things have been crazy here, I haven't
had any time for extra ciricular activities...

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Wed Sep  3 02:57:54 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 02 Sep 2008 20:57:54 -0400
Subject: [coreboot] coreboot on AMD PIC
Message-ID: <3697d737c93ce56c8fe1f0fe2c1fc984@imap.1and1.com>


Hello everyone,
I just won an AMD PIC (Personal Internet Communicator) on eBay for 27 bucks
:-)
It has a Geode GX, what about coreboot on this baby? Has anyone tried?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Wed Sep  3 03:17:10 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Sep 2008 03:17:10 +0200
Subject: [coreboot] Using only one romcc copy
In-Reply-To: <E1KacFc-0006Z2-Sz@aun.bellman.mea>
References: <E1KacFc-0006Z2-Sz@aun.bellman.mea>
Message-ID: <48BDE596.8010703@gmx.net>

Hi Mats Erik,

I'm sorry that I don't know the exact convention for writing your first
name. Do you prefer to be called Mats Erik or just Mats?

On 02.09.2008 22:13, Mats Erik Andersson wrote:
> I did one round of timing the build processes:
>
> Original make command:                      0m42.323s
> My reduction and a clean start:             0m30.955s
> After that a 'make clean' and renewed make: 0m23.081s
>
> The timings might not be typical, but the time saving seems
> to be substantial in the 'middle case' where only one romcc
> needs to be built, as well as in the last case were romcc
> is fully reused for both rom-images.
>   

I measured an abuild run and the time savings on my machine are between
0% and 30% (average 12%), so there is no downside if you look at it from
a compile time standpoint.
Your work is really helpful for anybody working on v2 and I took your
suggestion to fix the make rules at the source.

> Since I only have used coreboot-v2, I have no knowledge
> whether my utility could be applied also to coreboot-v3.
>   

Fortunately v3 uses only the system gcc, so this doesn't apply.

This patch is the equivalent of running Mats' reduce.sh before every
compilation. Thanks to him for the initial idea and realization.

The only thing left out is the make rule for cleaning the romcc binary
shared between each fallback/normal image. That change should be
discussed separately.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Patch attached because it is >100k.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

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From c-d.hailfinger.devel.2006 at gmx.net  Wed Sep  3 03:28:11 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Sep 2008 03:28:11 +0200
Subject: [coreboot] coreboot on AMD PIC
In-Reply-To: <3697d737c93ce56c8fe1f0fe2c1fc984@imap.1and1.com>
References: <3697d737c93ce56c8fe1f0fe2c1fc984@imap.1and1.com>
Message-ID: <48BDE82B.9050007@gmx.net>

On 03.09.2008 02:57, Joseph Smith wrote:
> Hello everyone,
> I just won an AMD PIC (Personal Internet Communicator) on eBay for 27 bucks
> :-)
> It has a Geode GX, what about coreboot on this baby? Has anyone tried?
>   

The following link may be your best bet:
http://www.coreboot.org/pipermail/coreboot/2008-February/031521.html

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mats.andersson at gisladisker.se  Wed Sep  3 11:26:31 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Wed, 03 Sep 2008 11:26:31 +0200
Subject: [coreboot] v2: Watching dependencies for auto.c
Message-ID: <E1KaodD-0006nN-25@aun.bellman.mea>


Hello again,

the following tool calculates the dependencies in
$(MAINBOARD)/auto.c and inserts these into the
two makefiles for normal and fallback images.
It intentionally disregards the referenced
header files, but instead it helped me to find
an incorrect inclusion of bist.h in the basis
I presently use. Thus you might be forced to
inspect these by hand, after running the script.
Once again, the script only searches for lines
of the type

	#include "whatever/you/like"

The call is simple enough:

	watch_auto_c.sh targets/msi/ms6147/ms6147/

Please regard this snippet as taster of what could
be done, were the incorporated dependencies deeper
in the python tool itself. Already now the manipulated
makefiles catch very well the groundwork changes I
do to the subsystems for the boot images.

Best regards for now,

Mats E Andersson

---

#!/bin/sh
#
# A tool to include direct dependencies for auto.c.
# A constant is built containing these dependencies,
# and is then inserted into {normal,fallback}/Makefile.
#
if [ -z "$1" ];then
	echo "A target directory is mandatory. Aborting."
	exit 1
fi

if [ ! -s "$1/Makefile" ]; then
	echo "Wrong directory, or \"Makefile\" is missing."
	exit 1
fi

if grep -q AUTO_C_INCLUDES $1/fallback/Makefile; then
	echo "Already done."
	exit 0
fi

TOP=$(sed -n 's/TOP:=\(.*\)/\1/p' $1/Makefile.settings)
TARGET_DIR=$(sed -n 's/TARGET_DIR:=\(.*\)/\1/p' $1/Makefile.settings)
TARGET_DIR=$(dirname $TARGET_DIR)

AUTO_C_INCLUDES=$(perl -n -e 'if ( m/^\s*#\s*include\s*"/ ) { m/"(.*)"/; print "\$\(TOP\)/src/" . $1 . " ";};' $TOP/src/mainboard/$TARGET_DIR/auto.c)

for nn in $1/{normal,fallback}/Makefile; do
	sed -i "/^CRT0_INCLUDES/,/^$/ {/^$/a\
AUTO_C_INCLUDES:=$AUTO_C_INCLUDES\n
}; s/.*:.*\/auto\.c.*/& \$(AUTO_C_INCLUDES)/;" $nn
done




From stepan at coresystems.de  Wed Sep  3 11:39:15 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 03 Sep 2008 11:39:15 +0200
Subject: [coreboot] coreboot on AMD PIC
In-Reply-To: <3697d737c93ce56c8fe1f0fe2c1fc984@imap.1and1.com>
References: <3697d737c93ce56c8fe1f0fe2c1fc984@imap.1and1.com>
Message-ID: <48BE5B43.1020502@coresystems.de>

Joseph Smith wrote:
> Hello everyone,
> I just won an AMD PIC (Personal Internet Communicator) on eBay for 27 bucks
> :-)
> It has a Geode GX, what about coreboot on this baby? Has anyone tried?
>   

The Geode GX is supported nicely in coreboot v1 and v2.



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


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From timl at scintilla.utwente.nl  Wed Sep  3 11:42:50 2008
From: timl at scintilla.utwente.nl (Tim ter Laak)
Date: Wed, 3 Sep 2008 11:42:50 +0200 (CEST)
Subject: [coreboot] flashrom patch: add support for Abit AB-BM6 board
Message-ID: <Pine.LNX.4.64.0809031112270.11431@virtuscin>

Hello all,

This patch adds support for the Abit AB-BM6 mainboard to flashrom.

The biggest part is a generic function to lower a GPIO line on the PIIX4E 
southbridge, copied and adapted from its ich_gpio_raise() counterpart 
(mostly lower instead of raise, followed names from the PIIX4E datasheet). 
The board specific function then uses this to lower GPO 26.

Signed-off-by: Tim ter Laak <timl at scintilla.utwente.nl>
---

The patch was made from the flashrom subdir, because svn diff from the 
top-level coreboot dir (as per the directions in the Development 
Guidelines on the wiki) didn't seem to work for me. Probably because 
flashrom is fetched externally when checking out coreboot? Anyway, I hope 
this is okay. If you really prefer a diff from the top-level dir just let 
me know, and I'll regenerate it with gnu diff.

Kind regards,
 	Tim.


Index: board_enable.c
===================================================================
--- board_enable.c	(revision 3559)
+++ board_enable.c	(working copy)
@@ -349,6 +349,58 @@
  }

  /**
+ * Set the specified GPIO on the specified PIIX4 southbridge to low.
+ *
+ * @param name The name of this board.
+ * @param piix_vendor PCI vendor ID of the specified PIIX4 southbridge. (0x8086)
+ * @param piix_device PCI device ID of the specified PIIX4 southbridge, function Power Management (0x7113 for PIIX4E)
+ * @param pmbase_reg PMBASE register offset in the bridge. (0x40 for PIIX4E)
+ * @param pmbase_mask PMBASE bitmask (0xFFC0)
+ * @param gporeg Offset of GPOREG register in I/O space, relative to GPIOBASE. (0x34)
+ * @param gpio_bit The bit (GPIO) which shall be set to low.
+ * @return If the write-enable was successful return 0, otherwise return -1.
+ */
+static int piix4_gpio_lower(const char *name, uint16_t piix_vendor,
+			  uint16_t piix_device, uint8_t pmbase_reg,
+			  uint8_t gporeg, uint32_t pmbase_mask,
+			  unsigned int gpio_bit)
+{
+	struct pci_dev *dev;
+	uint16_t pmbar;
+	uint32_t reg32;
+
+	dev = pci_dev_find(piix_vendor, piix_device);     /* Intel PIIX4 ACPI function */
+	if (!dev) {
+		fprintf(stderr, "\nERROR: PIIX4 dev %4x:%4x not found.\n",
+			piix_vendor, piix_device);
+		return -1;
+	}
+
+	/* Use PMBASE register to find the I/O space for GPIO. */
+	pmbar = pci_read_word(dev, pmbase_reg) & pmbase_mask;
+
+	/* Set specified GPIO to high. */
+	reg32 = INL(pmbar + gporeg);
+	OUTB(0x00, 0xEB);	/* dummy write to unused port as delay */
+ 
+	reg32 &= ~(1 << gpio_bit);
+	OUTL(reg32, pmbar + gporeg);
+	OUTB(0x00, 0xEB);	/* another delay */
+
+	return 0;
+}
+
+/**
+ * Suited for Abit AB-BM6.
+ */
+static int piix4_gpio26_lower(const char *name)
+{
+	return piix4_gpio_lower(name, 0x8086, 0x7113, 0x40, 0x34, 0xffc0, 26);
+}
+
+
+
+/**
   * Suited for Acorp 6A815EPD.
   */
  static int board_acorp_6a815epd(const char *name)
@@ -672,6 +724,8 @@
   	 NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4},
  	{0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c,
  	 NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e},
+	{0x8086, 0x7190, 0x0000, 0x0000, 0x8086, 0x7110, 0x0000, 0x0000,
+	 "abit", "ab-bm6", "Abit AB-BM6", piix4_gpio26_lower},
  	{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL}	/* Keep this */
  };




From timl at scintilla.utwente.nl  Wed Sep  3 11:55:46 2008
From: timl at scintilla.utwente.nl (Tim ter Laak)
Date: Wed, 3 Sep 2008 11:55:46 +0200 (CEST)
Subject: [coreboot] flashrom patch: make AT49F002N(T) chip work
Message-ID: <Pine.LNX.4.64.0809031143000.11431@virtuscin>

Hello all,

This patch fixes support for the AT49F002N(T) chip in the flashrom tool.

It replaces the write function to one based on write_byte_program_jedec() 
instead of write_page_write_jedec(), as this part does not support page 
programming.
I have verified the NT variant to fully work now, and adjusted the test 
status accordingly. The N variant *should* also work with this patch, but 
remains untested.

Signed-off-by: Tim ter Laak <timl at scintilla.utwente.nl>
---

Like my previous patch, this one is also based inside the flashrom 
directory.

Kind regards,
 	Tim.


Index: flashchips.c
===================================================================
--- flashchips.c	(revision 3559)
+++ flashchips.c	(working copy)
@@ -38,8 +38,8 @@
  	{"ASD",		"AE49F2008",		ASD_ID,		ASD_AE49F2008,		256,	128,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
  	{"Atmel",	"AT29C020",		ATMEL_ID,	AT_29C020,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_jedec},
  	{"Atmel",	"AT29C040A",		ATMEL_ID,	AT_29C040A,		512,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Atmel",	"AT49F002(N)",		ATMEL_ID,	AT_49F002N,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
-	{"Atmel",	"AT49F002(N)T",		ATMEL_ID,	AT_49F002NT,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_jedec},
+	{"Atmel",	"AT49F002(N)",		ATMEL_ID,	AT_49F002N,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_49f002},
+	{"Atmel",	"AT49F002(N)T",		ATMEL_ID,	AT_49F002NT,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_49f002},
  	{"Atmel",       "AT25DF321",		ATMEL_ID,	AT_25DF321,		4096,	256,		TEST_OK_PREW,	probe_spi_rdid,		spi_chip_erase_c7,	spi_chip_write,	spi_chip_read},
  	{"AMIC",	"A25L40P",		AMIC_ID,	AMIC_A25L40P,		512,	256,		TEST_OK_PREW,	probe_spi_rdid4,	spi_chip_erase_c7,	spi_chip_write, spi_chip_read},
  	{"AMIC",	"A29002B",		AMIC_ID_NOPREFIX, AMIC_A29002B,		256,	64 * 1024,	TEST_UNTESTED,	probe_29f002,		erase_29f002,			write_29f002},



From svn at coreboot.org  Wed Sep  3 14:10:40 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 03 Sep 2008 12:10:40 -0000
Subject: [coreboot] #88: Add UHCI/OHCI/EHCI support to GRUB2
In-Reply-To: <039.a29419ae4cf2a53d96bab5721473bd40@coreboot.org>
References: <039.a29419ae4cf2a53d96bab5721473bd40@coreboot.org>
Message-ID: <048.39e680ec739132c67027b7f3c4f0ed0f@coreboot.org>

#88: Add UHCI/OHCI/EHCI support to GRUB2
----------------------------+-----------------------------------------------
    Reporter:  uwe          |         Owner:  oxygene          
        Type:  enhancement  |        Status:  closed           
    Priority:  minor        |     Milestone:                   
   Component:  libpayload   |       Version:                   
  Resolution:  wontfix      |      Keywords:                   
Dependencies:               |   Patchstatus:  there is no patch
----------------------------+-----------------------------------------------
Changes (by stepan):

  * priority:  critical => minor
  * resolution:  => wontfix
  * status:  new => closed
  * component:  grub2 => libpayload
  * milestone:  Port GRUB2 to coreboot =>


Comment:

 The usb stack was moved to libpayload, and we stopped developing for
 GRUB2. Thus closing this bug.

 OHCI and EHCI are still to be done. But that's a different story.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/88#comment:4>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Wed Sep  3 14:13:44 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 03 Sep 2008 12:13:44 -0000
Subject: [coreboot] #12: Make coreboot work on a laptop
In-Reply-To: <039.22f37b7604388563f8bf993f91062156@coreboot.org>
References: <039.22f37b7604388563f8bf993f91062156@coreboot.org>
Message-ID: <048.450eac771da7a66dc6f23541c481bae8@coreboot.org>

#12: Make coreboot work on a laptop
-------------------------+--------------------------------------------------
    Reporter:  uwe       |         Owner:  stepan           
        Type:  task      |        Status:  assigned         
    Priority:  major     |     Milestone:  Going mainstream 
   Component:  coreboot  |       Version:                   
  Resolution:            |      Keywords:                   
Dependencies:            |   Patchstatus:  there is no patch
-------------------------+--------------------------------------------------
Changes (by stepan):

  * status:  new => assigned


-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/12#comment:4>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Wed Sep  3 14:17:49 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 03 Sep 2008 12:17:49 -0000
Subject: [coreboot] #98: Eliminate false positive "unknown .. SPI chip"
 matches
In-Reply-To: <041.f5e0f851af475dd9ed354e9f68f1a10a@coreboot.org>
References: <041.f5e0f851af475dd9ed354e9f68f1a10a@coreboot.org>
Message-ID: <050.ceaf968a54f44323fe20e1d646ef9af1@coreboot.org>

#98: Eliminate false positive "unknown .. SPI chip" matches
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  somebody          
        Type:  defect    |        Status:  new               
    Priority:  major     |     Milestone:  flashrom v1.0     
   Component:  flashrom  |       Version:                    
  Resolution:            |      Keywords:  spi probe         
Dependencies:  #97       |   Patchstatus:  patch needs review
-------------------------+--------------------------------------------------

Comment(by stepan):

 Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/98#comment:2>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Wed Sep  3 14:18:26 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 03 Sep 2008 12:18:26 -0000
Subject: [coreboot] #98: Eliminate false positive "unknown .. SPI chip"
 matches
In-Reply-To: <041.f5e0f851af475dd9ed354e9f68f1a10a@coreboot.org>
References: <041.f5e0f851af475dd9ed354e9f68f1a10a@coreboot.org>
Message-ID: <050.dc25f89c56768eefb96e46dc7123bb34@coreboot.org>

#98: Eliminate false positive "unknown .. SPI chip" matches
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge                         
        Type:  defect    |        Status:  new                           
    Priority:  major     |     Milestone:  flashrom v1.0                 
   Component:  flashrom  |       Version:                                
  Resolution:            |      Keywords:  spi probe                     
Dependencies:  #97       |   Patchstatus:  patch is ready to be committed
-------------------------+--------------------------------------------------
Changes (by stepan):

  * owner:  somebody => stuge
  * patchstatus:  patch needs review => patch is ready to be committed


-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/98#comment:3>
coreboot <http://www.coreboot.org/>


From hansj.schmid at yahoo.com  Wed Sep  3 13:09:27 2008
From: hansj.schmid at yahoo.com (Hans Schmid)
Date: Wed, 3 Sep 2008 04:09:27 -0700 (PDT)
Subject: [coreboot] Bios Debugging
Message-ID: <840262.36470.qm@web46409.mail.sp1.yahoo.com>

General question:
Is there any reasonable way to debug BIOS code. I checked (almost) everything like
AMD's SimNow, Bochs, Qemu, hardware tools like interposers and so on but
they don't fit my expectations/requirements? What I would need were a hardware
based debugger for Intel multicore processors. Any idea?

Kind regards,
Hans :-)

________________________________


      
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From jordan.crouse at amd.com  Wed Sep  3 18:09:50 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 3 Sep 2008 10:09:50 -0600
Subject: [coreboot] Bios Debugging
In-Reply-To: <840262.36470.qm@web46409.mail.sp1.yahoo.com>
References: <840262.36470.qm@web46409.mail.sp1.yahoo.com>
Message-ID: <20080903160950.GF32202@cosmic.amd.com>

On 03/09/08 04:09 -0700, Hans Schmid wrote:
> General question:
> Is there any reasonable way to debug BIOS code. I checked (almost) everything like
> AMD's SimNow, Bochs, Qemu, hardware tools like interposers and so on but
> they don't fit my expectations/requirements? What I would need were a hardware
> based debugger for Intel multicore processors. Any idea?

What was missing from these emulators?  SimNow was designed specifically to
develop firmware images.  What did you find lacking?

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From c-d.hailfinger.devel.2006 at gmx.net  Wed Sep  3 18:24:10 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 03 Sep 2008 18:24:10 +0200
Subject: [coreboot] Using only one romcc copy
In-Reply-To: <48BDE596.8010703@gmx.net>
References: <E1KacFc-0006Z2-Sz@aun.bellman.mea> <48BDE596.8010703@gmx.net>
Message-ID: <48BEBA2A.6090409@gmx.net>

Hi Mats Erik,

if you want to sign off on my patch version of your utility, please do
so. Having an Ack from you would be cool as well.

On 03.09.2008 03:17, Carl-Daniel Hailfinger wrote:
> Hi Mats Erik,
>
> I'm sorry that I don't know the exact convention for writing your first
> name. Do you prefer to be called Mats Erik or just Mats?
>
> On 02.09.2008 22:13, Mats Erik Andersson wrote:
>   
>> I did one round of timing the build processes:
>>
>> Original make command:                      0m42.323s
>> My reduction and a clean start:             0m30.955s
>> After that a 'make clean' and renewed make: 0m23.081s
>>
>> The timings might not be typical, but the time saving seems
>> to be substantial in the 'middle case' where only one romcc
>> needs to be built, as well as in the last case were romcc
>> is fully reused for both rom-images.
>>     

I changed this a bit to trigger romcc rebuild on "make clean" in the
main target directory, but not on "make clean" in each normal/fallback
image.

> I measured an abuild run and the time savings on my machine are between
> 0% and 30% (average 12%), so there is no downside if you look at it from
> a compile time standpoint.
> Your work is really helpful for anybody working on v2 and I took your
> suggestion to fix the make rules at the source.
>
>   
>> Since I only have used coreboot-v2, I have no knowledge
>> whether my utility could be applied also to coreboot-v3.
>>   
>>     
>
> Fortunately v3 uses only the system gcc, so this doesn't apply.
>
> This patch is the equivalent of running Mats' reduce.sh before every
> compilation. Thanks to him for the initial idea and realization.
>
> The only thing left out is the make rule for cleaning the romcc binary
> shared between each fallback/normal image. That change should be
> discussed separately.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
> Patch attached because it is >100k.
>   

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From hansj.schmid at yahoo.com  Wed Sep  3 18:57:00 2008
From: hansj.schmid at yahoo.com (Hans Schmid)
Date: Wed, 3 Sep 2008 09:57:00 -0700 (PDT)
Subject: [coreboot] Bios Debugging
Message-ID: <933770.82392.qm@web46414.mail.sp1.yahoo.com>

Hi Jordan,

was just skimming over it today. I think I'll change my mind 
and claim the opposite: great product. I wasn't aware there is
also a full release. Tomorrow I will have a closer look at this
product but it looks really impressing so far. Thanks for 
insisting!!!

Hans :-)

________________________________




----- Original Message ----
From: Jordan Crouse <jordan.crouse at amd.com>
To: Hans Schmid <hansj.schmid at yahoo.com>
Cc: coreboot at coreboot.org
Sent: Wednesday, September 3, 2008 6:09:50 PM
Subject: Re: Bios Debugging

On 03/09/08 04:09 -0700, Hans Schmid wrote:
> General question:
> Is there any reasonable way to debug BIOS code. I checked (almost) everything like
> AMD's SimNow, Bochs, Qemu, hardware tools like interposers and so on but
> they don't fit my expectations/requirements? What I would need were a hardware
> based debugger for Intel multicore processors. Any idea?

What was missing from these emulators?  SimNow was designed specifically to
develop firmware images.  What did you find lacking?

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.


      
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From jordan.crouse at amd.com  Wed Sep  3 19:10:33 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 3 Sep 2008 11:10:33 -0600
Subject: [coreboot] Bios Debugging
In-Reply-To: <933770.82392.qm@web46414.mail.sp1.yahoo.com>
References: <933770.82392.qm@web46414.mail.sp1.yahoo.com>
Message-ID: <20080903171033.GA26472@cosmic.amd.com>

On 03/09/08 09:57 -0700, Hans Schmid wrote:
> Hi Jordan,
> 
> was just skimming over it today. I think I'll change my mind 
> and claim the opposite: great product. I wasn't aware there is
> also a full release. Tomorrow I will have a closer look at this
> product but it looks really impressing so far. Thanks for 
> insisting!!!

And please don't get me wrong - SimNow isn't perfect.  I was
asking to figure out what you thought could be better.
I am trying to encourage more SimNow users, and I will gladly
take anything I can send back to the developers.

Jordan

> ----- Original Message ----
> From: Jordan Crouse <jordan.crouse at amd.com>
> To: Hans Schmid <hansj.schmid at yahoo.com>
> Cc: coreboot at coreboot.org
> Sent: Wednesday, September 3, 2008 6:09:50 PM
> Subject: Re: Bios Debugging
> 
> On 03/09/08 04:09 -0700, Hans Schmid wrote:
> > General question:
> > Is there any reasonable way to debug BIOS code. I checked (almost) everything like
> > AMD's SimNow, Bochs, Qemu, hardware tools like interposers and so on but
> > they don't fit my expectations/requirements? What I would need were a hardware
> > based debugger for Intel multicore processors. Any idea?
> 
> What was missing from these emulators?  SimNow was designed specifically to
> develop firmware images.  What did you find lacking?
> 
> Jordan
> 
> -- 
> Jordan Crouse
> Systems Software Development Engineer 
> Advanced Micro Devices, Inc.
> 
> 
>       

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From mats.andersson at gisladisker.se  Wed Sep  3 19:26:20 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Wed, 03 Sep 2008 19:26:20 +0200
Subject: [coreboot] v2: Detection of sdram densities.
Message-ID: <E1Kaw7Y-0006ta-Br@aun.bellman.mea>


Hello again,

I have been experimenting with an algorithm to detect
and register with the northbridge i440bx the correct
amount of sdram present. A C-coded version is appended
to this message. Feel free to comment on the method.

In the actually working code, I had to split the
algorithm into a lower and an upper part, in order
not to run out of internal registers under romcc,
but the idea remains the same.

Since there are also some later stages where I have
not understood how the previous author hard coded
a single 64MB bank,  I presently achieve a running
system only when I dynamically detect a distribution
identical to what was earlier hard coded.

My detection works with any combination of 0MB and
64MB in two rows for DIMM0 and DIMM1.

Question: In case an sdram device has rows of mixed
sizes, can one depend on the larger density being
in row zero, and the smaller content in row one?

The input value to my function sdram_find_rowsize,
is typically the byte captured using

     spd_read_byte(ctrl->channel0[0],31)

and similar calls. The output has the largest density
in the least significant byte, and the smaller density
(or a copy for non-mixed devices) in the most significant
byte.

Best regards,

Mats E Andersson

---

static uint16_t sdram_find_rowsize(unsigned char d)
{
	char mask = 1;

	/* Bail out for empty socket and obviously invalid data. */
	if ( d == 0x00 || d == 0xff )
		return 0;

	while (1)
	{
		if ( d & mask )
		{
			if ( d & ~mask )
				/* Largest chunk in zero'th row, smallest chunk in first row. */
				return ((d & mask) << 8) | (d & ~mask);

			/* Make a duplicate copy in high and low part. */
			return (d << 8) | d;
		}
		mask <<= 1;
	}
}



From daniel-coreboot at lindenaar.eu  Wed Sep  3 21:02:39 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Wed, 03 Sep 2008 21:02:39 +0200
Subject: [coreboot] via vt82c686 southbridge
Message-ID: <48BEDF4F.1020405@lindenaar.eu>

Hi everybody,
I'm working on getting coreboot going on my 'thintune'. It's a thin 
client PC with a custom motherboard based on the via vt8601 North and 
vt82c686b south. I'm using coreboot v2 since v3 was stated to be 
unstable (Is this the best choice?).

I started out by porting some of the code for the 82c686 from the v1 
project and using the code for the vt8235 to structure it in the v2 way. 
I've no clue if I've done it right or not, but there doesn't seem to be 
very much documentation on that (feel free to point out if there is...).

I'm currently trying to get it built, but just found out that SMBus 
seems to be needed for the RAM stuff, so I'm porting it over from the 8235.

Any tips, tricks and remarks are welcome. I'll give word when it 
compiles and I've done a test boot.

regards,
Daniel Lindenaar



From jordan at chalmers.se  Wed Sep  3 21:24:29 2008
From: jordan at chalmers.se (Ulf Jordan)
Date: Wed, 3 Sep 2008 21:24:29 +0200 (CEST)
Subject: [coreboot] [PATCH 2/2] libpayload: support color over serial
In-Reply-To: <Pine.LNX.4.63.0808101643010.12042@elfpc10.elmagn.chalmers.se>
References: <Pine.LNX.4.63.0808101643010.12042@elfpc10.elmagn.chalmers.se>
Message-ID: <Pine.LNX.4.63.0809032101290.31192@elfpc10.elmagn.chalmers.se>

Here is an updated version of the serial color patch.

Compared to the previous patch:

* serial_set_color takes explicit foreground and background color numbers.

* The need to output color escape sequences is determined from the 
color pair number, not the color content of a given pair. This eliminates 
the possibbility of obtaining incorrect colors after \e[m (e.g. bold to 
non-bold transition) on terminals where the default color is not white on 
black.

* doxygen comment added to serial_set_color

* Foreground and background colors of a color pair are extracted with 
pair_content(), instead of relying on explicit bitmasking and shifting. 
Improves readability and removes some code duplication.

Build and runtime tested with coreinfo+libpayload+coreboot-v3 under QEMU.


/ulf
-------------- next part --------------
Add support for curses color output over serial.

Note that the sequence \e[m for turning off bold resets all attributes,
including color.

Signed-off-by: Ulf Jordan <jordan at chalmers.se>

Index: libpayload/curses/tinycurses.c
===================================================================
--- libpayload/curses/tinycurses.c.orig	2008-08-19 20:04:18.000000000 +0200
+++ libpayload/curses/tinycurses.c	2008-09-02 22:12:14.000000000 +0200
@@ -669,10 +669,12 @@
 	// FIXME.
 	int serial_is_bold = 0;
 	int serial_is_altcharset = 0;
+	int serial_cur_pair = 0;
 
 	int x, y;
 	chtype ch;
 	int need_altcharset;
+	short fg, bg;
 
 	serial_end_bold();
 	serial_end_altcharset();
@@ -703,6 +705,7 @@
 					if (serial_is_bold) {
 						serial_end_bold();
 						serial_is_bold = 0;
+						serial_cur_pair = 0;
 					}
 				}
 
@@ -723,6 +726,13 @@
 					serial_is_altcharset = 0;
 				}
 
+				if (serial_cur_pair != PAIR_NUMBER(attr)) {
+					pair_content(PAIR_NUMBER(attr),
+						     &fg, &bg);
+					serial_set_color(fg, bg);
+					serial_cur_pair = PAIR_NUMBER(attr);
+				}
+
 				serial_putchar(ch);
 			}
 
Index: libpayload/drivers/serial.c
===================================================================
--- libpayload/drivers/serial.c.orig	2008-08-19 20:04:18.000000000 +0200
+++ libpayload/drivers/serial.c	2008-09-02 22:38:19.000000000 +0200
@@ -110,6 +110,8 @@
    enacs=\E(B\E)0, smacs=^N, rmacs=^O.  */
 #define VT100_SMACS       "\e(0"
 #define VT100_RMACS       "\e(B"
+/* A vt100 doesn't do color, setaf/setab below are from xterm-color. */
+#define VT100_SET_COLOR   "\e[3%d;4%dm"
 
 static void serial_putcmd(char *str)
 {
@@ -142,6 +144,19 @@
 	serial_putcmd(VT100_RMACS);
 }
 
+/**
+ * Set the foreground and background colors on the serial console.
+ *
+ * @param fg Foreground color number.
+ * @param bg Background color number.
+ */
+void serial_set_color(short fg, short bg)
+{
+	char buffer[32];
+	snprintf(buffer, sizeof(buffer), VT100_SET_COLOR, fg, bg);
+	serial_putcmd(buffer);
+}
+
 void serial_set_cursor(int y, int x)
 {
 	char buffer[32];
Index: libpayload/include/libpayload.h
===================================================================
--- libpayload/include/libpayload.h.orig	2008-09-02 21:25:39.000000000 +0200
+++ libpayload/include/libpayload.h	2008-09-02 22:07:45.000000000 +0200
@@ -139,6 +139,7 @@
 void serial_end_bold(void);
 void serial_start_altcharset(void);
 void serial_end_altcharset(void);
+void serial_set_color(short fg, short bg);
 void serial_set_cursor(int y, int x);
 /** @} */
 

From svn at coreboot.org  Wed Sep  3 21:59:44 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  3 Sep 2008 21:59:44 +0200
Subject: [coreboot] r3561 - in trunk/payloads/libpayload: curses drivers
	include
Message-ID: <mailman.2021.1355071373.16123.coreboot@coreboot.org>

Author: jcrouse
Date: 2008-09-03 21:59:44 +0200 (Wed, 03 Sep 2008)
New Revision: 3561

Modified:
   trunk/payloads/libpayload/curses/tinycurses.c
   trunk/payloads/libpayload/drivers/serial.c
   trunk/payloads/libpayload/include/libpayload.h
Log:
Add support for curses color output over serial.

Note that the sequence \e[m for turning off bold resets all attributes,
including color.

Signed-off-by: Ulf Jordan <jordan at chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>


Modified: trunk/payloads/libpayload/curses/tinycurses.c
===================================================================
--- trunk/payloads/libpayload/curses/tinycurses.c	2008-09-02 16:06:22 UTC (rev 3560)
+++ trunk/payloads/libpayload/curses/tinycurses.c	2008-09-03 19:59:44 UTC (rev 3561)
@@ -669,10 +669,12 @@
 	// FIXME.
 	int serial_is_bold = 0;
 	int serial_is_altcharset = 0;
+	int serial_cur_pair = 0;
 
 	int x, y;
 	chtype ch;
 	int need_altcharset;
+	short fg, bg;
 
 	serial_end_bold();
 	serial_end_altcharset();
@@ -703,6 +705,7 @@
 					if (serial_is_bold) {
 						serial_end_bold();
 						serial_is_bold = 0;
+						serial_cur_pair = 0;
 					}
 				}
 
@@ -723,6 +726,13 @@
 					serial_is_altcharset = 0;
 				}
 
+				if (serial_cur_pair != PAIR_NUMBER(attr)) {
+					pair_content(PAIR_NUMBER(attr),
+						     &fg, &bg);
+					serial_set_color(fg, bg);
+					serial_cur_pair = PAIR_NUMBER(attr);
+				}
+
 				serial_putchar(ch);
 			}
 

Modified: trunk/payloads/libpayload/drivers/serial.c
===================================================================
--- trunk/payloads/libpayload/drivers/serial.c	2008-09-02 16:06:22 UTC (rev 3560)
+++ trunk/payloads/libpayload/drivers/serial.c	2008-09-03 19:59:44 UTC (rev 3561)
@@ -110,6 +110,8 @@
    enacs=\E(B\E)0, smacs=^N, rmacs=^O.  */
 #define VT100_SMACS       "\e(0"
 #define VT100_RMACS       "\e(B"
+/* A vt100 doesn't do color, setaf/setab below are from xterm-color. */
+#define VT100_SET_COLOR   "\e[3%d;4%dm"
 
 static void serial_putcmd(char *str)
 {
@@ -142,6 +144,19 @@
 	serial_putcmd(VT100_RMACS);
 }
 
+/**
+ * Set the foreground and background colors on the serial console.
+ *
+ * @param fg Foreground color number.
+ * @param bg Background color number.
+ */
+void serial_set_color(short fg, short bg)
+{
+	char buffer[32];
+	snprintf(buffer, sizeof(buffer), VT100_SET_COLOR, fg, bg);
+	serial_putcmd(buffer);
+}
+
 void serial_set_cursor(int y, int x)
 {
 	char buffer[32];

Modified: trunk/payloads/libpayload/include/libpayload.h
===================================================================
--- trunk/payloads/libpayload/include/libpayload.h	2008-09-02 16:06:22 UTC (rev 3560)
+++ trunk/payloads/libpayload/include/libpayload.h	2008-09-03 19:59:44 UTC (rev 3561)
@@ -139,6 +139,7 @@
 void serial_end_bold(void);
 void serial_start_altcharset(void);
 void serial_end_altcharset(void);
+void serial_set_color(short fg, short bg);
 void serial_set_cursor(int y, int x);
 /** @} */
 




From Marc.Jones at amd.com  Wed Sep  3 21:59:43 2008
From: Marc.Jones at amd.com (Marc Jones)
Date: Wed, 3 Sep 2008 13:59:43 -0600
Subject: [coreboot] K8 INIT detection
In-Reply-To: <48BB4FC1.4030309@gmx.net>
References: <48BB4FC1.4030309@gmx.net>
Message-ID: <48BEECAF.1020108@amd.com>

Carl-Daniel Hailfinger wrote:
> Hi Marc,
> 
> I'm working on v3 and K8 setup. Right now, we try to determine whether
> we rebooted because of INIT by looking at bit 11 of MTRRdefType because
> it survives INIT and doesn't survive a cold or warm reboot. Although
> this is a nice generic way, we can only read it early in stage0 asm
> because we clobber it late in stage0 asm.
> 
> HyperTransport Initialization Control Register Function 0 Offset 6Ch Bit
> 6: InitDet looks exactly like what we want for that, and it is not
> clobbered. Quoting from a really old BKDG (26094 Rev. 3.30 February 2006):
> "INIT Detect (InitDet)?Bit 6. This bit may be used to distinguish
> between an INIT and a warm/cold reset by setting the bit to 1 before an
> initialization event is generated. This bit is cleared by a warm or cold
> reset but not by an INIT."
> Newer BKDGs say the same, so my question is how far back into the past
> (in terms of CPUs supported by coreboot v2) and how far into the future
> we can rely on this. It would certainly allow our stage0/stage1 code to
> enjoy a cleaner design, not to mention improved readability.
> 
> Regards,
> Carl-Daniel
> 

Yes, 6Ch Bit 6: InitDet is a better way to do it. The 3.30 BKDG covers 
rev a-e so it should be in all revisions of k8. It is also in the 
Barcelona and I expect in all future versions. It looks like it is used 
in K8 and Fam10 code. Grep for HTIC_INIT_Detect

Marc




-- 
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors





From jordan.crouse at amd.com  Wed Sep  3 22:05:17 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Wed, 3 Sep 2008 14:05:17 -0600
Subject: [coreboot] libpayload: support color over serial
In-Reply-To: <Pine.LNX.4.63.0809032101290.31192@elfpc10.elmagn.chalmers.se>
References: <Pine.LNX.4.63.0808101643010.12042@elfpc10.elmagn.chalmers.se>
	<Pine.LNX.4.63.0809032101290.31192@elfpc10.elmagn.chalmers.se>
Message-ID: <20080903200517.GE26472@cosmic.amd.com>

On 03/09/08 21:24 +0200, Ulf Jordan wrote:
> Here is an updated version of the serial color patch.
> 
> Compared to the previous patch:
> 
> * serial_set_color takes explicit foreground and background color numbers.
> 
> * The need to output color escape sequences is determined from the 
> color pair number, not the color content of a given pair. This eliminates 
> the possibbility of obtaining incorrect colors after \e[m (e.g. bold to 
> non-bold transition) on terminals where the default color is not white on 
> black.
> 
> * doxygen comment added to serial_set_color
> 
> * Foreground and background colors of a color pair are extracted with 
> pair_content(), instead of relying on explicit bitmasking and shifting. 
> Improves readability and removes some code duplication.
> 
> Build and runtime tested with coreinfo+libpayload+coreboot-v3 under QEMU.
> 
> 
> /ulf

> Add support for curses color output over serial.
> 
> Note that the sequence \e[m for turning off bold resets all attributes,
> including color.
> 
> Signed-off-by: Ulf Jordan <jordan at chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>

r3561.    And thanks for documenting the function.

Jordan

> Index: libpayload/curses/tinycurses.c
> ===================================================================
> --- libpayload/curses/tinycurses.c.orig	2008-08-19 20:04:18.000000000 +0200
> +++ libpayload/curses/tinycurses.c	2008-09-02 22:12:14.000000000 +0200
> @@ -669,10 +669,12 @@
>  	// FIXME.
>  	int serial_is_bold = 0;
>  	int serial_is_altcharset = 0;
> +	int serial_cur_pair = 0;
>  
>  	int x, y;
>  	chtype ch;
>  	int need_altcharset;
> +	short fg, bg;
>  
>  	serial_end_bold();
>  	serial_end_altcharset();
> @@ -703,6 +705,7 @@
>  					if (serial_is_bold) {
>  						serial_end_bold();
>  						serial_is_bold = 0;
> +						serial_cur_pair = 0;
>  					}
>  				}
>  
> @@ -723,6 +726,13 @@
>  					serial_is_altcharset = 0;
>  				}
>  
> +				if (serial_cur_pair != PAIR_NUMBER(attr)) {
> +					pair_content(PAIR_NUMBER(attr),
> +						     &fg, &bg);
> +					serial_set_color(fg, bg);
> +					serial_cur_pair = PAIR_NUMBER(attr);
> +				}
> +
>  				serial_putchar(ch);
>  			}
>  
> Index: libpayload/drivers/serial.c
> ===================================================================
> --- libpayload/drivers/serial.c.orig	2008-08-19 20:04:18.000000000 +0200
> +++ libpayload/drivers/serial.c	2008-09-02 22:38:19.000000000 +0200
> @@ -110,6 +110,8 @@
>     enacs=\E(B\E)0, smacs=^N, rmacs=^O.  */
>  #define VT100_SMACS       "\e(0"
>  #define VT100_RMACS       "\e(B"
> +/* A vt100 doesn't do color, setaf/setab below are from xterm-color. */
> +#define VT100_SET_COLOR   "\e[3%d;4%dm"
>  
>  static void serial_putcmd(char *str)
>  {
> @@ -142,6 +144,19 @@
>  	serial_putcmd(VT100_RMACS);
>  }
>  
> +/**
> + * Set the foreground and background colors on the serial console.
> + *
> + * @param fg Foreground color number.
> + * @param bg Background color number.
> + */
> +void serial_set_color(short fg, short bg)
> +{
> +	char buffer[32];
> +	snprintf(buffer, sizeof(buffer), VT100_SET_COLOR, fg, bg);
> +	serial_putcmd(buffer);
> +}
> +
>  void serial_set_cursor(int y, int x)
>  {
>  	char buffer[32];
> Index: libpayload/include/libpayload.h
> ===================================================================
> --- libpayload/include/libpayload.h.orig	2008-09-02 21:25:39.000000000 +0200
> +++ libpayload/include/libpayload.h	2008-09-02 22:07:45.000000000 +0200
> @@ -139,6 +139,7 @@
>  void serial_end_bold(void);
>  void serial_start_altcharset(void);
>  void serial_end_altcharset(void);
> +void serial_set_color(short fg, short bg);
>  void serial_set_cursor(int y, int x);
>  /** @} */
>  

> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From rmh at aybabtu.com  Wed Sep  3 22:44:55 2008
From: rmh at aybabtu.com (Robert Millan)
Date: Wed, 3 Sep 2008 22:44:55 +0200
Subject: [coreboot] #88: Add UHCI/OHCI/EHCI support to GRUB2
In-Reply-To: <048.39e680ec739132c67027b7f3c4f0ed0f@coreboot.org>
References: <039.a29419ae4cf2a53d96bab5721473bd40@coreboot.org>
	<048.39e680ec739132c67027b7f3c4f0ed0f@coreboot.org>
Message-ID: <20080903204455.GA10530@thorin>

On Wed, Sep 03, 2008 at 12:10:40PM -0000, coreboot wrote:
> 
>  OHCI and EHCI are still to be done. But that's a different story.

Hi,

This year's GSoC Marco Gerards worked on USB for GRUB.  There's a preliminar
OHCI implementation that is currently in the process of being integrated, and
could use some testing.  See:

  http://grub.enbug.org/USBSupport

As for EHCI, Marco said he plans to do that next.

-- 
Robert Millan

  The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
  how) you may access your data; but nobody's threatening your freedom: we
  still allow you to remove your data and not access it at all."



From svn at coreboot.org  Thu Sep  4 01:10:06 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 01:10:06 +0200
Subject: [coreboot] r3562 - trunk/util/flashrom
Message-ID: <mailman.2022.1355071373.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-09-04 01:10:05 +0200 (Thu, 04 Sep 2008)
New Revision: 3562

Modified:
   trunk/util/flashrom/flashrom.c
Log:
flashrom: Only find "unknown .. SPI chip" if no other chip was found

This removes the false positive matches we've been seeing, and also removes
the true positive match in case there is more than one flash chip and the 2nd
or 3rd are unknown - but I think that case is uncommon enough to warrant the
improvement in the common case. Use flashrom -frc forced read if you have the
uncommon case, and/or please add the flash chip to the flashchips array.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c	2008-09-03 19:59:44 UTC (rev 3561)
+++ trunk/util/flashrom/flashrom.c	2008-09-03 23:10:05 UTC (rev 3562)
@@ -99,12 +99,13 @@
 	return 0;
 }
 
-struct flashchip *probe_flash(struct flashchip *flash, int force)
+struct flashchip *probe_flash(struct flashchip *first_flash, int force)
 {
 	volatile uint8_t *bios;
+	struct flashchip *flash;
 	unsigned long flash_baseaddr = 0, size;
 
-	for (; flash && flash->name; flash++) {
+	for (flash = first_flash; flash && flash->name; flash++) {
 		if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0)
 			continue;
 		printf_debug("Probing for %s %s, %d KB: ",
@@ -150,9 +151,13 @@
 		if (force)
 			break;
 
-		if (flash->probe(flash) == 1)
+		if (flash->probe(flash) != 1)
+			goto notfound;
+
+		if (first_flash == flashchips || flash->model_id != GENERIC_DEVICE_ID)
 			break;
 
+notfound:
 		munmap((void *)bios, size);
 	}
 




From svn at coreboot.org  Thu Sep  4 01:14:59 2008
From: svn at coreboot.org (coreboot)
Date: Wed, 03 Sep 2008 23:14:59 -0000
Subject: [coreboot] #98: Eliminate false positive "unknown .. SPI chip"
 matches
In-Reply-To: <041.f5e0f851af475dd9ed354e9f68f1a10a@coreboot.org>
References: <041.f5e0f851af475dd9ed354e9f68f1a10a@coreboot.org>
Message-ID: <050.4c783c2c2be80cb6f69bf2e013a2885b@coreboot.org>

#98: Eliminate false positive "unknown .. SPI chip" matches
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  stuge                   
        Type:  defect    |        Status:  closed                  
    Priority:  major     |     Milestone:  flashrom v1.0           
   Component:  flashrom  |       Version:                          
  Resolution:  fixed     |      Keywords:  spi probe               
Dependencies:  #97       |   Patchstatus:  patch has been committed
-------------------------+--------------------------------------------------
Changes (by stuge):

  * status:  new => closed
  * patchstatus:  patch is ready to be committed => patch has been
                  committed
  * resolution:  => fixed


Comment:

 Thanks! Committed in r3562.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/98#comment:4>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Thu Sep  4 01:32:31 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 01:32:31 +0200
Subject: [coreboot] r3563 - trunk/coreboot-v2/src/southbridge/intel/i3100
Message-ID: <mailman.2023.1355071373.16123.coreboot@coreboot.org>

Author: eswierk
Date: 2008-09-04 01:32:30 +0200 (Thu, 04 Sep 2008)
New Revision: 3563

Modified:
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c
Log:
Tidy up identifiers, per Uwe's suggestion.  Trivial.

Signed-off-by: Ed Swierk <eswierk at arastra.com>
Acked-by: Ed Swierk <eswierk at arastra.com>



Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c	2008-09-03 23:10:05 UTC (rev 3562)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c	2008-09-03 23:32:30 UTC (rev 3563)
@@ -76,25 +76,25 @@
 	.ops_pci          = &lops_pci,
 };
 
-static struct pci_driver sata_driver __pci_driver = {
+static struct pci_driver ide_driver __pci_driver = {
 	.ops    = &sata_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_3100_IDE,
 };
 
-static struct pci_driver sata_driver_nr __pci_driver = {
+static struct pci_driver sata_driver __pci_driver = {
 	.ops    = &sata_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_3100_AHCI,
 };
 
-static struct pci_driver sata_driver_ep80579 __pci_driver = {
+static struct pci_driver ide_driver_ep80579 __pci_driver = {
 	.ops    = &sata_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_EP80579_IDE,
 };
 
-static struct pci_driver sata_driver_nr_ep80579 __pci_driver = {
+static struct pci_driver sata_driver_ep80579 __pci_driver = {
 	.ops    = &sata_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_EP80579_AHCI,




From peter at stuge.se  Thu Sep  4 01:40:24 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Sep 2008 01:40:24 +0200
Subject: [coreboot] Bios Debugging
In-Reply-To: <840262.36470.qm@web46409.mail.sp1.yahoo.com>
References: <840262.36470.qm@web46409.mail.sp1.yahoo.com>
Message-ID: <20080903234024.16270.qmail@stuge.se>

Hans Schmid wrote:
> Is there any reasonable way to debug BIOS code.
> What I would need were a hardware based debugger for Intel
> multicore processors. Any idea?

ICE is unbeatable, but also very expensive.

http://www.lauterbach.com/


//Peter



From eswierk at arastra.com  Thu Sep  4 02:23:11 2008
From: eswierk at arastra.com (Ed Swierk)
Date: Wed, 3 Sep 2008 17:23:11 -0700
Subject: [coreboot] [PATCH 3/6] Intel EP80579 northbridge
In-Reply-To: <20080826180531.GA3805@greenwood>
References: <e6c711510808200919n7678754cq5f0abb3c9a55cb76@mail.gmail.com>
	<20080826180531.GA3805@greenwood>
Message-ID: <e6c711510809031723x7ff9a8a8mc8eb16ce688ef660@mail.gmail.com>

Thanks for the feedback. I have addressed most of your comments;
please see the attached patch.

I will address your comment about the duplicate struct dimm_size
declaration separately. Would it make sense to put it in a file common
to all Intel northbridges, say, src/northbridge/intel/mem.h, and then
remove it from the various raminit.c's?

Signed-off-by: Ed Swierk <eswierk at arastra.com>

--Ed

On Tue, Aug 26, 2008 at 11:05 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Wed, Aug 20, 2008 at 09:19:23AM -0700, Ed Swierk wrote:
>> This patch implements support for the memory controller and PCIe
>> interface of the Intel EP80579 Integrated Processor. The memory
>> controller code supports only 64-bit-wide DIMMs with x8 devices and
>> ECC. It has been tested on a development board using a single Micron
>> MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
>> DIMMs.
>>
>> Signed-off-by: Ed Swierk <eswierk at arastra.com>
>
>
>> Index: coreboot-v2-3363/src/northbridge/intel/i3100/raminit_ep80579.c
>> ===================================================================
>> --- /dev/null
>> +++ coreboot-v2-3363/src/northbridge/intel/i3100/raminit_ep80579.c
>> @@ -0,0 +1,862 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Arastra, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + *
>> + */
>> +
>> +/* This code is based on src/northbridge/intel/e7520/raminit.c */
>
> We should research svn history for who wrote the e7520/raminit.c
> initially (if your code retains substantial parts of the original code),
> so we can add the proper (C) line...
>
> Same for the stock i3100 raminit.c we have in svn now.
>
>
>> +static void sdram_set_registers(const struct mem_controller *ctrl)
>> +{
>> +     static const unsigned int register_values[] = {
>> +             PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
>> +             PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420801 | DEVPRES_CONFIG,
>> +             PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
>> +             PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
>> +             PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
>> +             PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0,
>> +     };
>> +     int i;
>> +     int max;
>> +
>> +     max = sizeof(register_values)/sizeof(register_values[0]);
>
> ARRAY_SIZE
>
>
>> +     for(i = 0; i < max; i += 3) {
>> +             device_t dev;
>> +             unsigned where;
>> +             unsigned long reg;
>> +             dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
>> +             where = register_values[i] & 0xff;
>> +             reg = pci_read_config32(dev, where);
>> +             reg &= register_values[i+1];
>> +             reg |= register_values[i+2];
>> +             pci_write_config32(dev, where, reg);
>> +     }
>> +}
>
>> +
>> +struct dimm_size {
>> +     unsigned long side1;
>> +     unsigned long side2;
>> +};
>
> This is pretty common, we have multiple copies of this struct definition
> in v2, can we move it somewhere globally?
>
>
>> +static struct dimm_size spd_get_dimm_size(unsigned device)
>> +{
>> +     /* Calculate the log base 2 size of a DIMM in bits */
>> +     struct dimm_size sz;
>> +     int value, low, ddr2;
>> +     sz.side1 = 0;
>> +     sz.side2 = 0;
>> +
>> +     /* Note it might be easier to use byte 31 here, it has the DIMM size as
>> +      * a multiple of 4MB.  The way we do it now we can size both
>> +      * sides of an assymetric dimm.
>> +      */
>> +     value = spd_read_byte(device, 3);       /* rows */
>
> Please use the #defines from spd.h (or similar) here, instead of
> magic values such as the "3" and others below...
>
>
>> +     if (value < 0) goto hw_err;
>> +     if ((value & 0xf) == 0) goto val_err;
>> +     sz.side1 += value & 0xf;
>> +
>> +     value = spd_read_byte(device, 4);       /* columns */
>> +     if (value < 0) goto hw_err;
>> +     if ((value & 0xf) == 0) goto val_err;
>> +     sz.side1 += value & 0xf;
>> +
>> +     value = spd_read_byte(device, 17);      /* banks */
>> +     if (value < 0) goto hw_err;
>> +     if ((value & 0xff) == 0) goto val_err;
>> +     sz.side1 += log2(value & 0xff);
>> +
>> +     /* Get the module data width and convert it to a power of two */
>> +     value = spd_read_byte(device, 7);       /* (high byte) */
>> +     if (value < 0) goto hw_err;
>> +     value &= 0xff;
>> +     value <<= 8;
>> +
>> +     low = spd_read_byte(device, 6); /* (low byte) */
>> +     if (low < 0) goto hw_err;
>> +     value = value | (low & 0xff);
>> +     if ((value != 72) && (value != 64)) goto val_err;
>> +     sz.side1 += log2(value);
>> +
>> +     /* side 2 */
>> +     value = spd_read_byte(device, 5);       /* number of ranks */
>> +
>> +     if (value < 0) goto hw_err;
>> +     value &= 7;
>> +     value++;
>> +     if (value == 1) goto out;
>> +     if (value != 2) goto val_err;
>> +
>> +     /* Start with the symmetrical case */
>> +     sz.side2 = sz.side1;
>> +
>> +     value = spd_read_byte(device, 3);       /* rows */
>> +     if (value < 0) goto hw_err;
>> +     if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
>> +     sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
>> +     sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
>> +
>> +     value = spd_read_byte(device, 4);       /* columns */
>> +     if (value < 0) goto hw_err;
>> +     if ((value & 0xff) == 0) goto val_err;
>> +     sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
>> +     sz.side2 += ((value >> 4) & 0x0f);      /* Add in columns on side 2 */
>> +     goto out;
>> +
>> + val_err:
>> +     die("Bad SPD value\r\n");
>> +     /* If an hw_error occurs report that I have no memory */
>> + hw_err:
>> +     sz.side1 = 0;
>> +     sz.side2 = 0;
>> + out:
>> +     print_debug("dimm ");
>> +     print_debug_hex8(device);
>> +     print_debug(" size = ");
>> +     print_debug_hex8(sz.side1);
>> +     print_debug(".");
>> +     print_debug_hex8(sz.side2);
>> +     print_debug("\r\n");
>> +     return sz;
>> +
>> +}
>> +
>> +static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
>> +{
>> +     int i;
>> +     int cum;
>> +
>> +     for(i = cum = 0; i < DIMM_SOCKETS; i++) {
>> +             struct dimm_size sz;
>> +             if (dimm_mask & (1 << i)) {
>> +                     sz = spd_get_dimm_size(ctrl->channel0[i]);
>> +                     if (sz.side1 < 29) {
>> +                             return -1; /* Report SPD error */
>> +                     }
>> +                     /* convert bits to multiples of 64MB */
>> +                     sz.side1 -= 29;
>> +                     cum += (1 << sz.side1);
>
>> +                     /* DRB = 0x60 */
>
> Comment not needed, the point of the DRB #define is that you don't have
> to know the value here ;-)
>
>
>> +                     pci_write_config8(ctrl->f0, DRB + (i*2), cum);
>> +                     pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
>> +                     if (spd_read_byte(ctrl->channel0[i], 5) & 0x1) {
>> +                             cum <<= 1;
>> +                     }
>> +             }
>> +             else {
>> +                     pci_write_config8(ctrl->f0, DRB + (i*2), cum);
>> +                     pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
>> +             }
>> +     }
>> +     print_debug("DRB = ");
>> +     print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
>> +     print_debug("\r\n");
>> +
>> +     cum >>= 1;
>> +     /* set TOM top of memory 0xcc */
>> +     pci_write_config16(ctrl->f0, TOM, cum);
>> +     print_debug("TOM = ");
>> +     print_debug_hex16(cum);
>> +     print_debug("\r\n");
>> +     /* set TOLM top of low memory */
>> +     if(cum > 0x18) {
>> +             cum = 0x18;
>> +     }
>> +     cum <<= 11;
>> +     /* 0xc4 TOLM */
>> +     pci_write_config16(ctrl->f0, TOLM, cum);
>> +     print_debug("TOLM = ");
>> +     print_debug_hex16(cum);
>> +     print_debug("\r\n");
>> +     return 0;
>> +}
>> +
>> +
>> +static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
>> +{
>> +     unsigned dimm_mask;
>> +     int i;
>> +     dimm_mask = 0;
>> +     for(i = 0; i < DIMM_SOCKETS; i++) {
>> +             int byte;
>> +             unsigned device;
>> +             device = ctrl->channel0[i];
>> +             if (device) {
>> +                     byte = spd_read_byte(device, 2);  /* Type */
>> +                     print_debug("spd ");
>> +                     print_debug_hex8(device);
>> +                     print_debug(" = ");
>> +                     print_debug_hex8(byte);
>> +                     print_debug("\r\n");
>> +                     if (byte == 8) {
>> +                             dimm_mask |= (1 << i);
>> +                     }
>> +             }
>> +     }
>> +     return dimm_mask;
>> +}
>> +
>> +
>> +static int spd_set_row_attributes(const struct mem_controller *ctrl,
>
>> +             long dimm_mask)
>
> How long must this mask be? Can we use u64 or maybe u32 here? I assume
> the length is a fixed, known value?
>
>
>> +{
>> +     int value;
>> +     int i;
>> +
>> +     for (i = 0; i < DIMM_SOCKETS; i++) {
>> +             uint32_t dra = 0;
>> +             int reg = 0;
>> +
>> +             if (!(dimm_mask & (1 << i))) {
>> +                     continue;
>> +             }
>> +
>> +             value = spd_read_byte(ctrl->channel0[i], 3);    /* rows */
>> +             if (value < 0) die("Bad SPD data\r\n");
>> +             if ((value & 0xf) == 0) die("Invalid # of rows\r\n");
>> +             dra |= (((value-13) & 0x7) << 23);
>> +             dra |= (((value-13) & 0x7) << 29);
>> +             reg += value & 0xf;
>> +
>> +             value = spd_read_byte(ctrl->channel0[i], 4);    /* columns */
>> +             if (value < 0) die("Bad SPD data\r\n");
>> +             if ((value & 0xf) == 0) die("Invalid # of columns\r\n");
>> +             dra |= (((value-10) & 0x7) << 20);
>> +             dra |= (((value-10) & 0x7) << 26);
>> +             reg += value & 0xf;
>> +
>> +             value = spd_read_byte(ctrl->channel0[i], 17);   /* banks */
>> +             if (value < 0) die("Bad SPD data\r\n");
>> +             if ((value & 0xff) == 0) die("Invalid # of banks\r\n");
>> +             reg += log2(value & 0xff);
>> +
>> +             print_debug("dimm ");
>> +             print_debug_hex8(i);
>> +             print_debug(" reg = ");
>> +             print_debug_hex8(reg);
>> +             print_debug("\r\n");
>> +
>> +             /* set device density */
>> +             dra |= ((31-reg));
>> +             dra |= ((31-reg) << 6);
>> +
>> +             /* set device width (x8) */
>> +             dra |= (1 << 4);
>> +             dra |= (1 << 10);
>> +
>> +             /* set device type (registered) */
>> +             dra |= (1 << 14);
>> +
>> +             /* set number of ranks (0=single, 1=dual) */
>> +             value = spd_read_byte(ctrl->channel0[i], 5);
>> +             dra |= ((value & 0x1) << 17);
>> +
>> +             print_debug("DRA");
>> +             print_debug_hex8(i);
>> +             print_debug(" = ");
>> +             print_debug_hex32(dra);
>> +             print_debug("\r\n");
>> +
>> +             /* 0x70 DRA */
>> +             pci_write_config32(ctrl->f0, DRA + (i*4), dra);
>> +     }
>> +     return 0;
>> +}
>> +
>> +
>> +static uint32_t spd_set_drt_attributes(const struct mem_controller *ctrl,
>> +             long dimm_mask, uint32_t drc)
>> +{
>> +     int i;
>> +     uint32_t val, val1;
>> +     uint32_t cl;
>> +     uint32_t trc = 0;
>> +     uint32_t trfc = 0;
>> +     uint32_t tras = 0;
>> +     uint32_t trtp = 0;
>> +     uint32_t twtr = 0;
>> +     int index = drc & 0x00000003;
>> +     int ci;
>> +     static const uint8_t latencies[] = { /* 533, 800, 400, 667 */
>> +             0x10, 0x60, 0x10, 0x20 };
>> +     static const uint32_t drt0[] = { /* 533, 800, 400, 667 */
>> +             0x24240002, 0x24360002, 0x24220002, 0x24360002 };
>> +     static const uint32_t drt1[] = { /* 533, 800, 400, 667 */
>> +             0x00400000, 0x00900000, 0x00200000, 0x00700000 };
>> +     static const uint32_t magic[] = { /* 533, 800, 400, 667 */
>> +             0x007b8221, 0x00b94331, 0x005ca1a1, 0x009a62b1 };
>> +     static const uint32_t mrs[] = { /* 533, 800, 400, 667 */
>> +             0x07020000, 0x0b020000, 0x05020000, 0x09020000 };
>> +     static const int cycle[] = { /* 533, 800, 400, 667 */
>> +             15, 10, 20, 12 }; /* cycle time in 1/4 ns units */
>> +     static const int byte40rem[] = {
>> +             0, 1, 2, 2, 3, 3, 0, 0 }; /* byte 40 remainder in 1/4 ns units */
>> +
>> +     /* CAS latency in cycles */
>> +     val = latencies[index];
>> +     for (i = 0; i < DIMM_SOCKETS; i++) {
>> +             if (!(dimm_mask & (1 << i)))
>> +                     continue;
>> +             val &= spd_read_byte(ctrl->channel0[i], 18);
>> +     }
>> +     if (val & 0x10)
>> +             cl = 4;
>> +     else if (val & 0x20)
>> +             cl = 5;
>> +     else if (val & 0x40)
>> +             cl = 6;
>> +     else
>> +             die("CAS latency mismatch\r\n");
>> +     print_debug("cl = ");
>> +     print_debug_hex8(cl);
>> +     print_debug("\r\n");
>> +
>> +     ci = cycle[index];
>> +
>> +     /* Trc, Trfc in cycles */
>> +     for (i = 0; i < DIMM_SOCKETS; i++) {
>> +             if (!(dimm_mask & (1 << i)))
>> +                     continue;
>> +             val1 = spd_read_byte(ctrl->channel0[i], 40);
>> +             val = spd_read_byte(ctrl->channel0[i], 41);
>> +             val <<= 2; /* convert to 1/4 ns */
>> +             val += byte40rem[(val1 >> 4) & 0x7];
>> +             val = (val + ci - 1) / ci + 1; /* convert to cycles */
>> +             if (trc < val)
>> +                     trc = val;
>> +             val = spd_read_byte(ctrl->channel0[i], 42);
>> +             val <<= 2; /* convert to 1/4 ns */
>> +             if (val1 & 0x01)
>> +                     val += 1024;
>> +             val += byte40rem[(val1 >> 1) & 0x7];
>> +             val = (val + ci - 1) / ci; /* convert to cycles */
>> +             if (trfc < val)
>> +                     trfc = val;
>> +     }
>> +     print_debug("trc = ");
>> +     print_debug_hex8(trc);
>> +     print_debug("\r\n");
>> +     print_debug("trfc = ");
>> +     print_debug_hex8(trfc);
>> +     print_debug("\r\n");
>> +
>> +     /* Tras, Trtp, Twtr in cycles */
>> +     for (i = 0; i < DIMM_SOCKETS; i++) {
>> +             if (!(dimm_mask & (1 << i)))
>> +                     continue;
>> +             val = spd_read_byte(ctrl->channel0[i], 30);
>> +             val <<= 2; /* convert to 1/4 ns */
>> +             val = (val + ci - 1) / ci; /* convert to cycles */
>> +             if (tras < val)
>> +                     tras = val;
>> +             val = spd_read_byte(ctrl->channel0[i], 38);
>> +             val = (val + ci - 1) / ci; /* convert to cycles */
>> +             if (trtp < val)
>> +                     trtp = val;
>> +             val = spd_read_byte(ctrl->channel0[i], 37);
>> +             val = (val + ci - 1) / ci; /* convert to cycles */
>> +             if (twtr < val)
>> +                     twtr = val;
>> +     }
>> +     print_debug("tras = ");
>> +     print_debug_hex8(tras);
>> +     print_debug("\r\n");
>> +     print_debug("trtp = ");
>> +     print_debug_hex8(trtp);
>> +     print_debug("\r\n");
>> +     print_debug("twtr = ");
>> +     print_debug_hex8(twtr);
>> +     print_debug("\r\n");
>> +
>> +     val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
>> +            | ((cl - 3) << 6) | ((cl - 3) << 3));
>> +     print_debug("drt0 = ");
>> +     print_debug_hex32(val);
>> +     print_debug("\r\n");
>> +     pci_write_config32(ctrl->f0, DRT0, val);
>> +
>> +     val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
>> +            | (twtr << 15));
>> +     print_debug("drt1 = ");
>> +     print_debug_hex32(val);
>> +     print_debug("\r\n");
>> +     pci_write_config32(ctrl->f0, DRT1, val);
>> +
>> +     val = (magic[index]);
>> +     print_debug("magic = ");
>> +     print_debug_hex32(val);
>> +     print_debug("\r\n");
>> +     pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
>> +
>> +     val = (mrs[index] | (cl << 20));
>> +     print_debug("mrs = ");
>> +     print_debug_hex32(val);
>> +     print_debug("\r\n");
>> +     return val;
>> +}
>> +
>> +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
>> +             long dimm_mask)
>> +{
>> +     int value;
>> +     int drc = 0;
>> +     int i;
>> +     msr_t msr;
>> +     uint8_t cycle = 0x25;
>> +
>> +     /* 0x7c DRC */
>> +     for (i = 0; i < DIMM_SOCKETS; i++) {
>> +             if (!(dimm_mask & (1 << i)))
>> +                     continue;
>> +             if ((spd_read_byte(ctrl->channel0[i], 6) & 0xf0) != 0x40)
>> +                     die("ERROR: Only 64-bit DIMMs supported\r\n");
>> +             if (!(spd_read_byte(ctrl->channel0[i], 11) & 0x02))
>> +                     die("ERROR: Only ECC DIMMs supported\r\n");
>> +             if (spd_read_byte(ctrl->channel0[i], 13) != 0x08)
>> +                     die("ERROR: Only x8 DIMMs supported\r\n");
>> +
>> +             value = spd_read_byte(ctrl->channel0[i], 9);    /* cycle time */
>> +             if (value > cycle)
>> +                     cycle = value;
>> +     }
>> +     print_debug("cycle = ");
>> +     print_debug_hex8(cycle);
>> +     print_debug("\r\n");
>> +
>> +     drc |= (1 << 20); /* enable ECC */
>> +     drc |= (3 << 30); /* enable CKE on each dimm */
>> +     drc |= (1 << 4); /* enable CKE globally */
>> +
>
>> +     /* eswierk check: */
>
> Done already? Remove? Turn into "TODO"?
>
>
>> +     /* set front side bus speed */
>> +     msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
>> +     print_debug("msr 0xcd = ");
>> +     print_debug_hex32(msr.hi);
>> +     print_debug_hex32(msr.lo);
>> +     print_debug("\r\n");
>> +
>
>> +     /* eswierk check that this msr really indicates fsb speed! */
>
> Ditto.
>
>
>> +     if (msr.lo & 0x07) {
>> +             print_info("533 MHz FSB\r\n");
>> +             if (cycle <= 0x25) {
>> +                     drc |= 0x5;
>> +                     print_info("400 MHz DDR\r\n");
>> +             } else if (cycle <= 0x30) {
>> +                     drc |= 0x7;
>> +                     print_info("333 MHz DDR\r\n");
>> +             } else if (cycle <= 0x3d) {
>> +                     drc |= 0x4;
>> +                     print_info("266 MHz DDR\r\n");
>> +             } else {
>> +                     drc |= 0x2;
>> +                     print_info("200 MHz DDR\r\n");
>> +             }
>> +     }
>> +     else {
>> +             print_info("400 MHz FSB\r\n");
>> +             if (cycle <= 0x30) {
>> +                     drc |= 0x7;
>> +                     print_info("333 MHz DDR\r\n");
>> +             } else if (cycle <= 0x3d) {
>> +                     drc |= 0x0;
>> +                     print_info("266 MHz DDR\r\n");
>> +             } else {
>> +                     drc |= 0x2;
>> +                     print_info("200 MHz DDR\r\n");
>> +             }
>> +     }
>> +
>> +     print_debug("DRC = ");
>> +     print_debug_hex32(drc);
>> +     print_debug("\r\n");
>> +
>> +     return drc;
>> +}
>> +
>> +static void sdram_set_spd_registers(const struct mem_controller *ctrl)
>> +{
>> +     long dimm_mask;
>> +     int i;
>> +
>> +     /* Test if we can read the spd */
>> +     dimm_mask = spd_detect_dimms(ctrl);
>> +     if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
>> +             print_err("No memory for this cpu\r\n");
>> +             return;
>> +     }
>> +     return;
>> +}
>> +
>> +static void do_delay(void)
>> +{
>> +     int i;
>> +     unsigned char b;
>> +     for(i=0;i<16;i++)
>> +             b=inb(0x80);
>> +}
>
> Please use the global delay function, no need for yet another one.
>
>
>> +
>> +#define TIMEOUT_LOOPS 300000
>> +
>> +#define DCALCSR  0x040
>> +#define DCALADDR 0x044
>> +#define DCALDATA 0x048
>> +#define MBCSR    0x140
>> +#define MBADDR   0x144
>> +#define MBDATA   0x148
>> +#define DDRIOMC2 0x268
>
> Move to some *.h file?
>
>> +
>> +static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
>> +{
>> +     unsigned char c1,c2;
>> +        unsigned int dimm,i;
>> +        unsigned int data32;
>> +     unsigned int t4;
>> +
>> +     /* Set up northbridge values */
>> +     /* ODT enable */
>> +     pci_write_config32(ctrl->f0, SDRC, 0xa0002c30);
>> +
>> +     c1 = pci_read_config8(ctrl->f0, DRB);
>> +     c2 = pci_read_config8(ctrl->f0, DRB+2);
>> +     if (c1 == c2) {
>> +             /* 1 single-rank DIMM */
>> +             data32 = 0x00000010;
>> +     }
>> +     else {
>> +             /* 2 single-rank DIMMs or 1 double-rank DIMM */
>> +             data32 = 0x00002010;
>> +     }
>> +
>> +     print_debug("ODT Value = ");
>> +     print_debug_hex32(data32);
>> +     print_debug("\r\n");
>> +
>> +     pci_write_config32(ctrl->f0, DDR2ODTC, data32);
>> +
>> +     for(i=0;i<2;i++) {
>> +             print_debug("ODT CS");
>> +             print_debug_hex8(i);
>> +             print_debug("\r\n");
>> +
>> +             write32(BAR+DCALADDR, 0x0b840001);
>> +             write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while (data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +}
>> +
>> +
>> +static void dump_dcal_regs(void)
>> +{
>> +     int i;
>> +     for (i = 0x0; i < 0x2a0; i += 4) {
>> +             if ((i % 16) == 0) {
>> +                     print_debug("\r\n");
>> +                     print_debug_hex16(i);
>> +                     print_debug(": ");
>> +             }
>> +             print_debug_hex32(read32(BAR+i));
>> +             print_debug(" ");
>> +     }
>> +     print_debug("\r\n");
>> +}
>> +
>> +
>> +static void sdram_enable(int controllers, const struct mem_controller *ctrl)
>> +{
>> +     int i;
>> +     int cs;
>> +     long mask;
>> +     uint32_t drc;
>> +     uint32_t data32;
>> +     uint32_t mode_reg;
>> +     msr_t msr;
>> +     uint16_t data16;
>> +
>> +     mask = spd_detect_dimms(ctrl);
>> +     print_debug("Starting SDRAM Enable\r\n");
>> +
>> +     /* set dram type and Front Side Bus freq. */
>> +     drc = spd_set_dram_controller_mode(ctrl, mask);
>> +     if (drc == 0) {
>> +             die("Error calculating DRC\r\n");
>> +     }
>> +     data32 = drc & ~(3 << 20);  /* clear ECC mode */
>> +     data32 = data32 | (3 << 5);  /* temp turn off ODT */
>> +     /* Set dram controller mode */
>> +     /* 0x7c DRC */
>> +     pci_write_config32(ctrl->f0, DRC, data32);
>> +
>> +             /* turn the clocks on */
>> +     /* 0x8c CKDIS */
>> +     pci_write_config16(ctrl->f0, CKDIS, 0x0000);
>> +
>> +             /* program row size DRB */
>> +     spd_set_ram_size(ctrl, mask);
>> +
>> +             /* program row attributes DRA */
>> +     spd_set_row_attributes(ctrl, mask);
>> +
>> +             /* program DRT timing values */
>> +     mode_reg = spd_set_drt_attributes(ctrl, mask, drc);
>
> The indentation of the comments here, and the coding style in general
> are not quite correct in various places. Let's commit this anyway for
> now, I'll do an 'indent'-run on the code later though, invoked as
> listed here: http://www.coreboot.org/Development_Guidelines#Coding_Style
>
>
>> +
>> +     dump_dcal_regs();
>> +
>> +     for(cs=0;cs<2;cs++) { /* loop through each dimm to test */
>> +             print_debug("NOP CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             /* Apply NOP */
>
> Wrong comment (or comment in the wrong place)? This only does a delay, no?
>
>
>> +             do_delay();
>> +
>> +             write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
>> +             write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
>> +
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +
>> +     /* Apply NOP */
>
> Ditto.
>
>
>> +     do_delay();
>> +
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("NOP CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +
>> +     /* Precharge all banks */
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("Precharge CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALADDR, 0x04000000);
>> +             write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +
>> +     /* EMRS: Enable DLLs, set OCD calibration mode to default */
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("EMRS CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALADDR, 0x0b840001);
>> +             write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +     /* MRS: Reset DLLs */
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("MRS CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALADDR, mode_reg);
>> +             write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +
>> +     /* Precharge all banks */
>> +     do_delay();
>> +     do_delay();
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("Precharge CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALADDR, 0x04000000);
>> +             write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>
>> +     /* Do 2 refreshes */
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("Refresh CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("Refresh CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>
> As far as I can see both blocks are identical? Why not a 'for' loop then?
> This would also make a smaller coreboot (binary) image (less
> code/printfs, less strings for the debug output, etc.).
>
> Are there code issues or romcc issues?
>
>
>> +     do_delay();
>> +     /* for good luck do 6 more */
>
> Better comment please, e.g. mention the reason why multiple runs are
> needed and why 6 and not some other number. I assume the SPD/RAM/NB
> datasheet says so?
>
>
>> +     for(cs=0;cs<2;cs++) {
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +     }
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +     }
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +     }
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +     }
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +     }
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
>> +     }
>> +     do_delay();
>
> Same as above, please pack this into a loop if possible.
>
>
>> +     /* MRS: Set DLLs to normal */
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("MRS CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
>> +             write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +
>> +     /* EMRS: Enable DLLs */
>> +     do_delay();
>> +     for(cs=0;cs<2;cs++) {
>> +             print_debug("EMRS CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALADDR, 0x0b840001);
>> +             write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +        }
>> +
>> +     do_delay();
>> +     /* No command */
>> +     write32(BAR+DCALCSR, 0x0000000f);
>> +
>> +     write32(BAR, 0x00100000);
>> +
>> +     /* enable on dimm termination */
>> +     set_on_dimm_termination_enable(ctrl);
>> +
>> +     dump_dcal_regs();
>> +
>> +     /* receive enable calibration */
>> +     do_delay();
>> +     for(cs=0;cs<1;cs++) {
>> +             print_debug("receive enable calibration CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
>> +             data32 = read32(BAR+DCALCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+DCALCSR);
>> +     }
>> +
>> +     dump_dcal_regs();
>> +
>> +     /* Adjust RCOMP */
>> +     data32 = read32(BAR+DDRIOMC2);
>> +     data32 &= ~(0xf << 16);
>> +     data32 |= (0xb << 16);
>> +     write32(BAR+DDRIOMC2, data32);
>> +
>> +     dump_dcal_regs();
>> +
>> +     /* 0x7c DRC */
>> +     data32 = drc & ~(3 << 20);  /* clear ECC mode */
>> +     pci_write_config32(ctrl->f0, DRC, data32);
>> +     write32(BAR+DCALCSR, 0x0008000f);
>> +
>> +     /* Clear memory and init ECC */
>> +     for(cs=0;cs<2;cs++) {
>> +             if (!(mask & (1<<cs)))
>> +                     continue;
>> +             print_debug("clear memory CS");
>> +             print_debug_hex8(cs);
>> +             print_debug("\r\n");
>> +             write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
>> +             data32 = read32(BAR+MBCSR);
>> +             while(data32 & 0x80000000)
>> +                     data32 = read32(BAR+MBCSR);
>> +             if(data32 & 0x40000000)
>> +                     print_debug("failed!\r\n");
>> +     }
>> +
>> +     /* Clear read/write FIFO pointers */
>> +     print_debug("clear read/write fifo pointers\r\n");
>> +     write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
>> +     do_delay();
>> +     write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
>> +     do_delay();
>> +
>> +     dump_dcal_regs();
>> +
>> +     print_debug("Done\r\n");
>> +
>> +     /* Set initialization complete */
>> +     /* 0x7c DRC */
>> +     drc |= (1 << 29);
>> +     drc |= (3 << 30);
>> +     data32 = drc & ~(3 << 20);  /* clear ECC mode */
>> +     pci_write_config32(ctrl->f0, DRC, data32);
>> +
>> +     /* Set the ECC mode */
>> +     pci_write_config32(ctrl->f0, DRC, drc);
>> +
>> +     /* The memory is now setup, use it */
>> +     cache_lbmem(MTRR_TYPE_WRBACK);
>> +}
>> +
>> +static inline int memory_initialized(void)
>> +{
>> +     return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29);
>> +}
>> Index: coreboot-v2-3363/src/northbridge/intel/i3100/raminit_ep80579.h
>> ===================================================================
>> --- /dev/null
>> +++ coreboot-v2-3363/src/northbridge/intel/i3100/raminit_ep80579.h
>> @@ -0,0 +1,33 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Arastra, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + *
>> + */
>> +
>
>> +/* This code is based on src/northbridge/intel/e7520/raminit.h */
>
> Nah, drop this, too trivial. This is soleley (C) Arastra, IMHO.
>
>
>> +
>> +#ifndef NORTHBRIDGE_INTEL_EP80579_RAMINIT_H
>> +#define NORTHBRIDGE_INTEL_EP80579_RAMINIT_H
>
> NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H for consistency.
>
>
>> +
>> +#define DIMM_SOCKETS 2
>> +struct mem_controller {
>> +     unsigned node_id;
>
> uint16_t or u16 here, as also done below?
>
>> +     device_t f0;
>> +     uint16_t channel0[DIMM_SOCKETS];
>> +};
>> +
>> +#endif
>> Index: coreboot-v2-3363/src/northbridge/intel/i3100/ep80579.h
>> ===================================================================
>> --- /dev/null
>> +++ coreboot-v2-3363/src/northbridge/intel/i3100/ep80579.h
>> @@ -0,0 +1,61 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2008 Arastra, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>> + *
>> + */
>> +
>> +#ifndef NORTHBRIDGE_INTEL_EP80579_H
>> +#define NORTHBRIDGE_INTEL_EP80579_H
>
> NORTHBRIDGE_INTEL_I3100_EP80579_H for consistency.
>
>
>> +#define VID       0x00
>> +#define DID       0x02
>> +#define PCICMD    0x04
>> +#define PCISTS    0x06
>> +#define RID       0x08
>
> These five are generic and already in pci.h I think (and not used in your
> code anyway), I'd drop them.
>
>
>> +#define SMRBASE   0x14
>> +#define MCHCFG0        0x50
>> +#define FDHC      0x58
>> +#define PAM       0x59
>> +#define DRB       0x60
>> +#define DRT1      0x64
>> +#define DRA       0x70
>> +#define DRT0      0x78
>> +#define DRC       0x7c
>> +#define ECCDIAG   0x84
>> +#define SDRC      0x88
>> +#define CKDIS     0x8c
>> +#define CKEDIS    0x8d
>> +#define DEVPRES   0x9c
>> +#define  DEVPRES_D0F0 (1 << 0)
>> +#define  DEVPRES_D1F0 (1 << 1)
>> +#define  DEVPRES_D2F0 (1 << 2)
>> +#define  DEVPRES_D3F0 (1 << 3)
>> +#define  DEVPRES_D4F0 (1 << 4)
>> +#define  DEVPRES_D10F0 (1 << 5)
>> +#define EXSMRC    0x9d
>> +#define SMRAM     0x9e
>> +#define EXSMRAMC  0x9f
>> +#define DDR2ODTC  0xb0
>> +#define TOLM      0xc4
>> +#define REMAPBASE 0xc6
>> +#define REMAPLIMIT 0xc8
>> +#define REMAPOFFSET 0xca
>> +#define TOM       0xcc
>> +#define HECBASE   0xce
>> +#define DEVPRES1  0xf4
>> +
>> +#endif
>
>
> Uwe.
> --
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
>
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From rminnich at gmail.com  Thu Sep  4 02:30:03 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 3 Sep 2008 17:30:03 -0700
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
	more to come
Message-ID: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>

This resolves the "unique name" problem. It sets up for k8 CPUs with
multiple busses per chip.

Comments welcome. I realize this code is not ideal :-)

ron
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From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 02:34:06 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 02:34:06 +0200
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
 more to come
In-Reply-To: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>
References: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>
Message-ID: <48BF2CFE.6000307@gmx.net>

On 04.09.2008 02:30, ron minnich wrote:
> This resolves the "unique name" problem. It sets up for k8 CPUs with
> multiple busses per chip.
>
> Comments welcome. I realize this code is not ideal :-)
>   

Forgive me, but I'd like to review this in depth and that might take
some time. I'm also doubting that the new scheme is really more readable
than my proposal from a few days ago.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Thu Sep  4 02:38:54 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 02:38:54 +0200
Subject: [coreboot] r856 - in coreboot-v3: arch/x86 lib
Message-ID: <mailman.2024.1355071373.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-09-04 02:38:54 +0200 (Thu, 04 Sep 2008)
New Revision: 856

Modified:
   coreboot-v3/arch/x86/pci_ops_conf1.c
   coreboot-v3/lib/lar.c
Log:
Improve debugging printks for LAR and PCI access.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/arch/x86/pci_ops_conf1.c
===================================================================
--- coreboot-v3/arch/x86/pci_ops_conf1.c	2008-09-02 15:25:06 UTC (rev 855)
+++ coreboot-v3/arch/x86/pci_ops_conf1.c	2008-09-04 00:38:54 UTC (rev 856)
@@ -144,8 +144,10 @@
 			 * things are set up (which we have to be able to do 
 			 * in stage 0 
 			 */
-			if (! busses)
+			if (!busses) {
+				printk(BIOS_WARNING, "pci_conf1_find_on_bus: busses is 0!\n");
 				continue;
+			}
 			if (pci_conf1_find_on_bus((busses >> 8) & 0xFF, vid, did, busdevfn))
 				return 1;
 		}

Modified: coreboot-v3/lib/lar.c
===================================================================
--- coreboot-v3/lib/lar.c	2008-09-02 15:25:06 UTC (rev 855)
+++ coreboot-v3/lib/lar.c	2008-09-04 00:38:54 UTC (rev 856)
@@ -120,8 +120,8 @@
 		header = (struct lar_header *)walk;
 		fullname = walk + sizeof(struct lar_header);
 
-		printk(BIOS_SPEW, "LAR: %s@%p, size %d\n", fullname, 
-				header, ntohl(header->len));
+		printk(BIOS_SPEW, "LAR: seen member %s@%p, size %d\n",
+		       fullname, header, ntohl(header->len));
 		// FIXME: check checksum
 
 		if (strcmp(fullname, filename) == 0) {




From rminnich at gmail.com  Thu Sep  4 02:45:55 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 3 Sep 2008 17:45:55 -0700
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
	more to come
In-Reply-To: <48BF2CFE.6000307@gmx.net>
References: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>
	<48BF2CFE.6000307@gmx.net>
Message-ID: <13426df10809031745l591c949dv8c9e1d8636b1668b@mail.gmail.com>

On Wed, Sep 3, 2008 at 5:34 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Forgive me, but I'd like to review this in depth and that might take
> some time. I'm also doubting that the new scheme is really more readable
> than my proposal from a few days ago.
>

ok, but I hope you'll see it is. The names of structs now have the
path in them. Create statictree.[ch] and you'll see what I mean.

But let me know.

Go ahead and resend your one from a few days ago and I'll look at it.
Keep in mind that this new stuff I'm doing is also there to support
multiple links per chip -- that's going in now. Currently we only
support one link per chip. We do need the inherited domain/bus/dev/fn
that I put in the dtc node struct (see dtc.h) to make this bus stuff
work.

ron



From rminnich at gmail.com  Thu Sep  4 02:59:09 2008
From: rminnich at gmail.com (ron minnich)
Date: Wed, 3 Sep 2008 17:59:09 -0700
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
	more to come
In-Reply-To: <13426df10809031745l591c949dv8c9e1d8636b1668b@mail.gmail.com>
References: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>
	<48BF2CFE.6000307@gmx.net>
	<13426df10809031745l591c949dv8c9e1d8636b1668b@mail.gmail.com>
Message-ID: <13426df10809031759q69fe8f03m1b62cf40a4a0e4fa@mail.gmail.com>

btw, I'm pretty happy with how this previous patch is working. It took
me about 5 mins to make the last mod and now I have this:

struct device dev_root = {
	.path = { .type = DEVICE_PATH_ROOT },
	.next = &dev_cpu_0,
	.link = {
		[0] = {
			.dev = &dev_root,
			.link = 0,
			.children = &dev_cpu_0
		},
		[1] = {
			.dev = &dev_root,
			.link = 0,
			.children = &dev_apic_0
		},
		[2] = {
			.dev = &dev_root,
			.link = 0,
			.children = &dev_domain_0
		},
	},
	.links = 3,
	.bus = &dev_root.link[0],
	.next = &dev_cpu_0,
	.ops = &default_dev_ops_root,
	.dtsname = "root",
	.enabled = 1
};

Multiple links that work. Does this work? I don't know.

I am not sure this it totally right yet, however:
struct device dev_domain_0 = {
	.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
	.device_configuration = &domain_0,
	.ops = &geodelx_north_domain,
	.link = {
		[0] = {
			.dev = &dev_domain_0,
			.link = 0,
			.children = &dev_pci_0_0_1_0
		},

		[1] = {
			.dev = &dev_domain_0,
			.link = 0,
			.children = &dev_pci_0_0_f_0
		},
		[2] = {
			.dev = &dev_domain_0,
			.link = 0,
			.children = &dev_pci_0_0_f_2
		},
	},
	.links = 3,
	.bus = &dev_root.link[2],
	.dtsname = "domain_0",
	.enabled = 1
};

Anyway, no further progess is possible on k8 until this is working as
the v2 config tool did for multiple links. It's the current
showstopper. So we need to solve it. I'm totally out of the loop
starting, well, very soon now and for next 10 days, so those with a
better idea are welcome to implement it :-)

ron



From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 04:35:50 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 04:35:50 +0200
Subject: [coreboot] [PATCH] v3: fix initial printk buffer address
	initialization
Message-ID: <48BF4986.6020009@gmx.net>

Fix initial printk buffer address initialization. This was broken in
r785 (move from explicit asm to implicit C) and unfortunately qemu never
triggered the bug, only real hardware did.

Thanks to Ron for bisecting this.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: corebootv3-printk_buffer_addr_init/lib/console.c
===================================================================
--- corebootv3-printk_buffer_addr_init/lib/console.c	(Revision 856)
+++ corebootv3-printk_buffer_addr_init/lib/console.c	(Arbeitskopie)
@@ -82,7 +82,9 @@
 
 void printk_buffer_init(void)
 {
-	struct printk_buffer *buf = printk_buffer_addr();
+	struct printk_buffer *buf = (struct printk_buffer *)PRINTK_BUF_ADDR_CAR;
+	global_vars()->printk_buffer = buf;
+	buf = printk_buffer_addr();
 	buf->len = PRINTK_BUF_SIZE_CAR - sizeof(struct printk_buffer);
 	buf->readoffset = 0;
 	buf->writeoffset = 0;


-- 
http://www.hailfinger.org/

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From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 05:05:34 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 05:05:34 +0200
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
 more to come
In-Reply-To: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>
References: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>
Message-ID: <48BF507E.8050305@gmx.net>

On 04.09.2008 02:30, ron minnich wrote:
> This resolves the "unique name" problem. It sets up for k8 CPUs with
> multiple busses per chip.
>
> Comments welcome. I realize this code is not ideal :-)
>
> Cleanup. Not totally yet. But it's better and it works with dbe62. 
>
> Basically, variables such as domain, bus, etc. are now inherited from the parent. 
>
> Label_tree has been fixed to do lots of tree annotation and cleanup. 
>
> One whole un-needed function is gone.
>   

But the patch added 90 lines of code in total. We may need to trim that
down.

> We're going to soon be able to do stuff like bus at 3{} bus at 2{} etc. which we 
> need to support k8. 
>
> This code "needs more love" as ward puts it but this is an improvement. 
>
> Also, names are now unique:
> struct device dev_pci_0_0_1_0
>
> which is domain 0, bus 0, dev 1, fn 0.
>   

My personal preferences for the name would be:
struct device dev_pci_domain_0_bus_0_dev_1_fn_0
or
struct device dev_pci_domain_0_bus_0_devfn_1_0
or
struct device dev_pci_domain0_bus0_dev1_fn0

Basically, pci_0_0_1_0 is not that intuitive.

> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   

I have not reviewed the code itself yet, but the output (except problems
with lots of additional linebreaks in inopportune places) is definitely
an improvement.
It would be cool if you could write in the changelog that your patch
initializes the dev.path for CPU devices (was zero before).

Once I fully understand your patch and its side effects, I'll probably ack.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 05:09:04 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 05:09:04 +0200
Subject: [coreboot] [PATCH] v3: more uniqueness in the dtc generated
 struct names
In-Reply-To: <48B87ED7.1030104@gmx.net>
References: <48B87ED7.1030104@gmx.net>
Message-ID: <48BF5150.9050804@gmx.net>

Hi Ron,

here's my patch proposal for struct device naming again. It has the
advantage of adding only 14 lines of code.

Regards,
Carl-Daniel

On 30.08.2008 00:57, Carl-Daniel Hailfinger wrote:
> I managed to break dtc while working on PCI bridges:
> dtc only uses dev_fn as identifier for a PCI device. That gets us a name
> collision if we have the same dev_fn combination on multiple buses.
> Either we add a random unique ID to the struct name or we integrate the
> number of the parent device as well.
> A third option would be to store the complete hierarchy in the name.
> I decided to go for integration of parent device name.
>
> With the following device tree
>
> /{
> 	cpus {};
> 	domain at 0 {
> 		bus at 0 {
> 			pci at 0,0 {
> 			};
> 			pci at 1,1 {
> 			};
> 			pci at f,0 {
> 				bus at 1 {
> 					pci at 0,0 {
> 					};
> 				};
> 			};
> 		};
> 	};
> };
>
>
> we get the old names:
> dev_root
> dev_cpus
> dev_domain_0
> dev_bus_0
> dev_pci_0_0
> dev_pci_1_1
> dev_pci_f_0
> dev_bus_1
> dev_pci_0_0 COLLISION!!!
>
>
> and the new names:
> dev_root
> dev_cpus
> dev_domain_0
> dev_domain_0_bus_0
> dev_bus_0_pci_0_0
> dev_bus_0_pci_1_1
> dev_bus_0_pci_f_0
> dev_pci_f_0_bus_1
> dev_bus_1_pci_0_0
>
> and the third option (not used) would have looked like this:
> dev_root
> dev_cpus
> dev_domain_0
> dev_domain_0_bus_0
> dev_domain_0_bus_0_pci_0_0
> dev_domain_0_bus_0_pci_1_1
> dev_domain_0_bus_0_pci_f_0
> dev_domain_0_bus_0_pci_f_0_bus_1
> dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0
>
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
>
> Index: corebootv3-pci_scan_bus/util/dtc/flattree.c
> ===================================================================
> --- corebootv3-pci_scan_bus/util/dtc/flattree.c	(Revision 846)
> +++ corebootv3-pci_scan_bus/util/dtc/flattree.c	(Arbeitskopie)
> @@ -931,6 +931,7 @@
>  		emit->endnode(etarget, treelabel);
>  	}
>  
> +	//fprintf(f, "//tree->label is %s, tree->parent->label is %s\n", tree->label, tree->parent ? tree->parent->label : NULL);
>  	/* now emit the device for this node, with sibling and child pointers etc. */
>  	emit->special(f, tree);
>  
> @@ -1313,8 +1314,23 @@
>  labeltree(struct node *tree)
>  {
>  	struct node *child;
> +	char *tmp1;
> +	char *tmp2;
>  
> +	//printf("//tree->label is %s, tree->parent->label is %s\n", tree->label, tree->parent ? tree->parent->label : NULL);
>  	tree->label = clean(tree->name, 1);
> +	if (tree->parent && tree->label) {
> +		tmp1 = clean(tree->parent->name, 1);
> +		if (strlen(tmp1)) {
> +			tmp2 = tree->label;
> +			tree->label = malloc(strlen(tmp1) + strlen(tmp2) + 2);
> +			strcpy(tree->label, tmp1);
> +			strcat(tree->label, "_");
> +			strcat(tree->label, tmp2);
> +			free(tmp2);
> +		}
> +		free(tmp1);
> +	}
>  	
>  	if (tree->next_sibling)
>  		labeltree(tree->next_sibling);
>
>
>   


-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 05:20:30 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 05:20:30 +0200
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
 more to come
In-Reply-To: <13426df10809031759q69fe8f03m1b62cf40a4a0e4fa@mail.gmail.com>
References: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>	
	<48BF2CFE.6000307@gmx.net>	
	<13426df10809031745l591c949dv8c9e1d8636b1668b@mail.gmail.com>
	<13426df10809031759q69fe8f03m1b62cf40a4a0e4fa@mail.gmail.com>
Message-ID: <48BF53FE.8000705@gmx.net>

On 04.09.2008 02:59, ron minnich wrote:
> btw, I'm pretty happy with how this previous patch is working. It took
> me about 5 mins to make the last mod and now I have this:
>   

Could you please resend your latest patch? Thanks.

> struct device dev_root = {
> 	.path = { .type = DEVICE_PATH_ROOT },
> 	.next = &dev_cpu_0,
> 	.link = {
> 		[0] = {
> 			.dev = &dev_root,
> 			.link = 0,
> 			.children = &dev_cpu_0
> 		},
> 		[1] = {
> 			.dev = &dev_root,
> 			.link = 0,
> 			.children = &dev_apic_0
> 		},
> 		[2] = {
> 			.dev = &dev_root,
> 			.link = 0,
> 			.children = &dev_domain_0
> 		},
> 	},
> 	.links = 3,
> 	.bus = &dev_root.link[0],
> 	.next = &dev_cpu_0,
> 	.ops = &default_dev_ops_root,
> 	.dtsname = "root",
> 	.enabled = 1
> };
>
> Multiple links that work. Does this work? I don't know.
>   

I'll try to modify a qemu target for testing and report back.

> I am not sure this it totally right yet, however:
> struct device dev_domain_0 = {
> 	.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
> 	.device_configuration = &domain_0,
> 	.ops = &geodelx_north_domain,
> 	.link = {
> 		[0] = {
> 			.dev = &dev_domain_0,
> 			.link = 0,
> 			.children = &dev_pci_0_0_1_0
> 		},
>
> 		[1] = {
> 			.dev = &dev_domain_0,
> 			.link = 0,
> 			.children = &dev_pci_0_0_f_0
> 		},
> 		[2] = {
> 			.dev = &dev_domain_0,
> 			.link = 0,
> 			.children = &dev_pci_0_0_f_2
> 		},
>   

The list of links "feels" wrong. I can't yet express that feeling in
technical terms, but I'll revisit this issue tomorrow.
One thing would be that PCI devices are now direct children of the
domain, not of the bus. That may cause problems.

> 	},
> 	.links = 3,
> 	.bus = &dev_root.link[2],
> 	.dtsname = "domain_0",
> 	.enabled = 1
> };
>
> Anyway, no further progess is possible on k8 until this is working as
> the v2 config tool did for multiple links. It's the current
> showstopper. So we need to solve it. I'm totally out of the loop
> starting, well, very soon now and for next 10 days, so those with a
> better idea are welcome to implement it :-)
>   

I'll look at v2 again and try to compare.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Thu Sep  4 08:21:52 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 08:21:52 +0200
Subject: [coreboot] r58 - /
Message-ID: <mailman.2025.1355071373.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-09-04 08:21:52 +0200 (Thu, 04 Sep 2008)
New Revision: 58

Added:
   branches/
Log:
create "branches"





From svn at coreboot.org  Thu Sep  4 08:22:40 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 08:22:40 +0200
Subject: [coreboot] r59 - branches trunk
Message-ID: <mailman.2026.1355071373.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-09-04 08:22:39 +0200 (Thu, 04 Sep 2008)
New Revision: 59

Added:
   branches/filo-0.5/
Removed:
   trunk/filo-0.5/
Log:
move the 0.5 branch to branches.





From mats.andersson at gisladisker.se  Thu Sep  4 12:38:04 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Thu, 04 Sep 2008 12:38:04 +0200
Subject: [coreboot] Using only one romcc copy
In-Reply-To: <48BDE596.8010703@gmx.net>
Message-ID: <E1KbCE0-0007EK-2b@aun.bellman.mea>

Action: patch evaluation


Ons den 3:e sep 03 03:17:34 2008 skrev Carl-Daniel Hailfinger:

>This patch is the equivalent of running Mats' reduce.sh before every
>compilation. Thanks to him for the initial idea and realization.
>
>The only thing left out is the make rule for cleaning the romcc binary
>shared between each fallback/normal image. That change should be
>discussed separately.
>
>Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
>Patch attached because it is >100k.

Acked-by: Mats Erik Andersson <mats.andersson at gisladisker.se>

---

There is one unresolved issue: romcc is built as it should
in a directory like "targets/msi/ms6119/ms6119/", but once
built, it remains in place forever, since there is no make-rule
to clean the executable romcc. The old clean-targets are
only looking inside target-machine/{normal,fallback}/ where
from now on there is no romcc. Thus the superordinate
Makefile "target-machine/Makefile" ought to have a target
"clean-romcc" that really removes romcc in cases where
the compiler undergoes changes.

Remark: A truly large patch to visually verify, but I did it
and I performed five different builds for an equal number of
targets.

Best regards,

Mats Andersson

P.S. Addressing me as "Mats" is the usual mode. The explicit
mention of a middle name is a remnant from my time as an 
active research mathematician!

P.P.S. I did not expect to become trustworthy to acknowledge
patches so soon, so I am improvising the formal protocol.
Hopefully it can be mended to pass as is intended.


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CiBlbmQK
--------------020901090104080503020506--




From peter at stuge.se  Thu Sep  4 13:52:51 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Sep 2008 13:52:51 +0200
Subject: [coreboot] Using only one romcc copy
In-Reply-To: <E1KbCE0-0007EK-2b@aun.bellman.mea>
References: <48BDE596.8010703@gmx.net> <E1KbCE0-0007EK-2b@aun.bellman.mea>
Message-ID: <20080904115251.7529.qmail@stuge.se>

Mats Erik Andersson wrote:
> P.P.S. I did not expect to become trustworthy to acknowledge
> patches so soon,

Anyone can send an acked-by.

I would like to remind everyone reading this to please not be afraid
of helping with development in any way shape or form, even if it is
only by reviewing simple patches and sending in acks.

In the end, committers make some kind of evaluation on the acks for
a certain patch. Sometimes more acks are required, sometimes one is
all that is needed.

The purpose of Acked-by is not to limit participation and openness
but to support the patch review workflow in all but trivial cases.


//Peter



From vincent.legoll at gmail.com  Thu Sep  4 15:31:13 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Thu, 4 Sep 2008 15:31:13 +0200
Subject: [coreboot] Added Shuttle SN25P wiki page & links
Message-ID: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>

Hello,

While I still have that info fresh in my head, I wrote what
I did for the Shuttle SN25P mainboard port.

main page:
http://www.coreboot.org/Shuttle_SN25P
linked from entry in supported mainboards

Thanks to all who helped me getting there, I hope
collaboration will continue.

-- 
Vincent Legoll



From svn at coreboot.org  Thu Sep  4 15:44:00 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 15:44:00 +0200
Subject: [coreboot] r3564 - in trunk/coreboot-v2: src/config
	src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240
	src/mainboard/abit/be6-ii_v2_0
	src/mainboard/advantech/pcm-5820 src/mainboard/agami/aruma
	src/mainboard/amd/rumba src/mainboard/arima/hdama
	src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp
	src/mainboard/asus/mew-am src/mainboard/asus/mew-vm
	src/mainboard/asus/p2b src/mainboard/asus/p2b-f
	src/mainboard/asus/p3b-f src/mainboard/axus/tc320
	src/mainboard/azza/pt-6ibd src/mainboard/bcom/winnet100
	src/mainboard/biostar/m6tba src/mainboard/compaq/deskpro_en_sff_p600
	src/mainboard/dell/s1850 src/mainboard/digitallogic/adl855pc
	src/mainboard/digitallogic/msm586seg
	src/mainboard/eaglelion/5bcm src/mainboard/emulation/qemu-x86
	src/mainboard/gigabyte/ga-6bxc src/mainboard/ibm/e325
	src/mainboard/ibm/e326 src/mainboard/iei/juki-511p
	src/mainboard/iei/nova4899r src/mainboard/intel/jarrell
	src/mainboard/intel/mtarvon src/mainboard/intel/xe7501devkit
	src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x
	src/mainboard/lippert/frontrunner src/mainboard/msi/ms6119
	src/mainboard/msi/ms6178 src/mainboard/msi/ms9282
	src/mainboard/newisys/khepri src/mainboard/olpc/btest
	src/mainboard/olpc/rev_a src/mainboard/rca/rm4100
	src/mainboard/sunw/ultra40 src/mainboard/supermicro/x6dai_g
	src/mainboard/supermicro/x6dhe_g src/mainboard/supermicro/x6dhe_g2
	src/mainboard/supermicro/x6dhr_ig src/mainboard/supermicro/x6dhr_ig2
	src/mainboard/technologic/ts5300
	src/mainboard/televideo/tc7020 src/mainboard/thomson/ip1000
	src/mainboard/tyan/s1846 src/mainboard/tyan/s2735
	src/mainboard/tyan/s2850 src/mainboard/tyan/s2875
	src/mainboard/tyan/s2880 src/mainboard/tyan/s2881
	src/mainboard/tyan/s2882 src/mainboard/tyan/s2885
	src/mainboard/tyan/s2891 src/mainboard/tyan/s2892
	src/mainboard/tyan/s2895 src/mainboard/tyan/s4880
	src/mainboard/tyan/s4882 src/mainboard/via/epia
	src/mainboard/via/epia-cn src/mainboard/via/epia-m util/newconfig
Message-ID: <mailman.2027.1355071374.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-09-04 15:44:00 +0200 (Thu, 04 Sep 2008)
New Revision: 3564

Modified:
   trunk/coreboot-v2/src/config/Config.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb
   trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb
   trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb
   trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb
   trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb
   trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb
   trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb
   trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
   trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb
   trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb
   trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb
   trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb
   trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
   trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb
   trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb
   trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb
   trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb
   trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia/Config.lb
   trunk/coreboot-v2/util/newconfig/config.g
Log:
This changes the python generated makefiles

        targets/*/*/Makefile
        targets/*/*/normal/Makefile
        targets/*/*/fallback/Makefile

to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.

Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.

The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson at gisladisker.se>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/config/Config.lb
===================================================================
--- trunk/coreboot-v2/src/config/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/config/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -162,7 +162,7 @@
 	action	"doxygen corebootDoc.config"
 end
 
-makerule ./romcc   
+makerule ../romcc   
 	depends	"$(TOP)/util/romcc/romcc.c" 
 	action	"$(HOSTCC) -g $(HOSTCFLAGS) $< -o $@"
 end

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -125,22 +125,22 @@
 	## Romcc output
 	##
 	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./failover.inc
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -51,22 +51,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -70,22 +70,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -52,22 +52,22 @@
 ## Romcc output
 ##
 # makerule ./failover.E
-# 	depends "$(MAINBOARD)/failover.c ./romcc" 
-# 	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+# 	depends "$(MAINBOARD)/failover.c ../romcc" 
+# 	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 # end
 # 
 # makerule ./failover.inc
-# 	depends "$(MAINBOARD)/failover.c ./romcc"
-# 	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+# 	depends "$(MAINBOARD)/failover.c ../romcc"
+# 	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 # end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,24 +37,24 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
 	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"./romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	action	"../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
 	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	action	"../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -51,22 +51,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -35,22 +35,22 @@
 driver mainboard.o
 if HAVE_PIRQ_TABLE object irq_tables.o end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -36,22 +36,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -56,22 +56,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -50,22 +50,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -52,22 +52,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -51,22 +51,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -47,22 +47,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -71,22 +71,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -71,22 +71,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -47,22 +47,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -51,22 +51,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -56,22 +56,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -68,22 +68,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c ./romcc"
-        action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c ../romcc"
+        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c ./romcc"
-        action "./romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c ../romcc"
+        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -62,22 +62,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -74,22 +74,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -71,22 +71,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -51,22 +51,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -35,22 +35,22 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 # object reset.o
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -100,22 +100,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -72,22 +72,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -51,22 +51,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -51,22 +51,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -40,22 +40,22 @@
 	object acpi_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -68,23 +68,23 @@
 	## Romcc output
 	##
 	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./failover.inc
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -56,22 +56,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -54,23 +54,23 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 makerule ./auto.inc 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -54,23 +54,23 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 makerule ./auto.inc 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -56,22 +56,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -56,22 +56,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -52,22 +52,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -36,22 +36,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -40,22 +40,22 @@
 	object acpi_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -37,22 +37,22 @@
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends	"$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	depends "$(MAINBOARD)/auto.c ./romcc"
-	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -69,22 +69,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -70,22 +70,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -70,22 +70,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -70,22 +70,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -70,22 +70,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -70,22 +70,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -70,22 +70,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -76,23 +76,23 @@
 	## Romcc output
 	##
 	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./failover.inc
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -76,22 +76,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -80,23 +80,23 @@
 	## Romcc output
 	##
 	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./failover.inc
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -67,23 +67,23 @@
 	## Romcc output
 	##
 	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./failover.inc
-	        depends "$(MAINBOARD)/failover.c ./romcc"
-        	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	        depends "$(MAINBOARD)/failover.c ../romcc"
+        	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 	##

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -67,23 +67,23 @@
 	## Romcc output
 	##
 	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ./romcc"
-	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        	depends "$(MAINBOARD)/failover.c ../romcc"
+	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./failover.inc
-	        depends "$(MAINBOARD)/failover.c ./romcc"
-        	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	        depends "$(MAINBOARD)/failover.c ../romcc"
+        	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 	end
 
 	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 	end
 
 	##

Modified: trunk/coreboot-v2/src/mainboard/via/epia/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/via/epia/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -50,22 +50,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -41,20 +41,20 @@
 	object acpi_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb	2008-09-04 13:44:00 UTC (rev 3564)
@@ -57,22 +57,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2008-09-03 23:32:30 UTC (rev 3563)
+++ trunk/coreboot-v2/util/newconfig/config.g	2008-09-04 13:44:00 UTC (rev 3564)
@@ -2159,10 +2159,13 @@
 	file.write("clean: ")
 	for i in romimages.keys():
 		file.write(" %s-clean" % i)
+	file.write(" base-clean")
 	file.write("\n\n")
 	for i, o in romimages.items():
 		file.write("%s-clean:\n" % o.getname())
 		file.write("\t(cd %s; $(MAKE) clean)\n\n" % o.getname())
+	file.write("base-clean:\n")
+	file.write("\trm -f romcc*\n\n")
 
 	for i in buildroms:
 		file.write("%s:" % i.name)




From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 15:59:21 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 15:59:21 +0200
Subject: [coreboot] Using only one romcc copy
In-Reply-To: <E1KbCE0-0007EK-2b@aun.bellman.mea>
References: <E1KbCE0-0007EK-2b@aun.bellman.mea>
Message-ID: <48BFE9B9.3010307@gmx.net>

Hi Mats,

On 04.09.2008 12:38, Mats Erik Andersson wrote:
> Action: patch evaluation
>
>
> Ons den 3:e sep 03 03:17:34 2008 skrev Carl-Daniel Hailfinger:
>   
>> This patch is the equivalent of running Mats' reduce.sh before every
>> compilation. Thanks to him for the initial idea and realization.
>>
>> The only thing left out is the make rule for cleaning the romcc binary
>> shared between each fallback/normal image. That change should be
>> discussed separately.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>
>> Patch attached because it is >100k.
>>     
>
> Acked-by: Mats Erik Andersson <mats.andersson at gisladisker.se>
>
> ---
>
> There is one unresolved issue: romcc is built as it should
> in a directory like "targets/msi/ms6119/ms6119/", but once
> built, it remains in place forever, since there is no make-rule
> to clean the executable romcc. The old clean-targets are
> only looking inside target-machine/{normal,fallback}/ where
> from now on there is no romcc. Thus the superordinate
> Makefile "target-machine/Makefile" ought to have a target
> "clean-romcc" that really removes romcc in cases where
> the compiler undergoes changes.
>   

Thanks, I forgot to resend my patch with that change. Fixed.

> Remark: A truly large patch to visually verify, but I did it
> and I performed five different builds for an equal number of
> targets.
>   

Thanks a lot!

Fixed version checked in as r3564.

> Best regards,
>
> Mats Andersson
>
> P.S. Addressing me as "Mats" is the usual mode. The explicit
> mention of a middle name is a remnant from my time as an 
> active research mathematician!
>   

Thanks for explaining. By the way, we have lots of code verification
tasks for you which should be suited perfectly for a mathematician. ;-)

> P.P.S. I did not expect to become trustworthy to acknowledge
> patches so soon, so I am improvising the formal protocol.
> Hopefully it can be mended to pass as is intended.
>   

Anyone who has read/tested/verified a patch is allowed and encouraged to
ack a patch. The final decision of checkin is in the hands of the committer.

By the way, you might want to look at coreboot v3. IMO it is a lot more
readable and has a cleaner codebase.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Thu Sep  4 16:11:41 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Sep 2008 16:11:41 +0200
Subject: [coreboot] Added Shuttle SN25P wiki page & links
In-Reply-To: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>
References: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>
Message-ID: <20080904141141.20995.qmail@stuge.se>

Vincent Legoll wrote:
> http://www.coreboot.org/Shuttle_SN25P

Great notes!

Only comment I can think of is to keep the tested kernel options
around even if they are discarded as not being useful, to keep record
of what has been tried.


//Peter



From vincent.legoll at gmail.com  Thu Sep  4 16:30:00 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Thu, 4 Sep 2008 16:30:00 +0200
Subject: [coreboot] Added Shuttle SN25P wiki page & links
In-Reply-To: <20080904141141.20995.qmail@stuge.se>
References: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>
	<20080904141141.20995.qmail@stuge.se>
Message-ID: <4727185d0809040730m43a9ae3ciee06b9d5edb616e3@mail.gmail.com>

On Thu, Sep 4, 2008 at 4:11 PM, Peter Stuge <peter at stuge.se> wrote:
> Vincent Legoll wrote:
>> http://www.coreboot.org/Shuttle_SN25P
>
> Great notes!
>
> Only comment I can think of is to keep the tested kernel options
> around even if they are discarded as not being useful, to keep record
> of what has been tried.

I'll try to keep a StepByStep section with all necessary infos.

But I intend to have a coreboot which is able to run the linux kernel
without special parameters, is that a realistic goal to aim for ?

Remember, I'm a newbie, I don't really understand (yet) what I'm
modifying in coreboot...

An area where I need something explained (that I didn't found in the
wiki) is: what would be required to have ACPI working ?

Couldn't we extract the tables from legacy BIOS and use them
within coreboot, if we don't stuff them in svn we should be fine.
At least as fine as people who extract them and load them with
the linux kernel... Or are there other things in ACPI that cannot
be extracted ?

-- 
Vincent Legoll



From rminnich at gmail.com  Thu Sep  4 16:42:11 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 07:42:11 -0700
Subject: [coreboot] [PATCH] v3: fix initial printk buffer address
	initialization
In-Reply-To: <48BF4986.6020009@gmx.net>
References: <48BF4986.6020009@gmx.net>
Message-ID: <13426df10809040742q2669015ay43535dcdddbd9e5f@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Not yet tested but it can't make it worse :-)

ron



From peter at stuge.se  Thu Sep  4 16:49:13 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Sep 2008 16:49:13 +0200
Subject: [coreboot] Added Shuttle SN25P wiki page & links
In-Reply-To: <4727185d0809040730m43a9ae3ciee06b9d5edb616e3@mail.gmail.com>
References: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>
	<20080904141141.20995.qmail@stuge.se>
	<4727185d0809040730m43a9ae3ciee06b9d5edb616e3@mail.gmail.com>
Message-ID: <20080904144913.1726.qmail@stuge.se>

Vincent Legoll wrote:
> But I intend to have a coreboot which is able to run the linux kernel
> without special parameters, is that a realistic goal to aim for ?

I think so.


> An area where I need something explained (that I didn't found in
> the wiki) is: what would be required to have ACPI working ?
> 
> Couldn't we extract the tables from legacy BIOS and use them
> within coreboot, if we don't stuff them in svn we should be fine.

No, you would be fine, noone else. We can't redistribute ACPI tables
from the factory BIOS. And a coreboot using them could probably be
argued to be a derivative work of the factory BIOS, and that is not
so good from a licensing perspective.


//Peter



From vincent.legoll at gmail.com  Thu Sep  4 17:05:18 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Thu, 4 Sep 2008 17:05:18 +0200
Subject: [coreboot] Added Shuttle SN25P wiki page & links
In-Reply-To: <20080904144913.1726.qmail@stuge.se>
References: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>
	<20080904141141.20995.qmail@stuge.se>
	<4727185d0809040730m43a9ae3ciee06b9d5edb616e3@mail.gmail.com>
	<20080904144913.1726.qmail@stuge.se>
Message-ID: <4727185d0809040805j59cb9b54g927ea6f85e90806c@mail.gmail.com>

On Thu, Sep 4, 2008 at 4:49 PM, Peter Stuge <peter at stuge.se> wrote:
>> An area where I need something explained (that I didn't found in
>> the wiki) is: what would be required to have ACPI working ?
>>
>> Couldn't we extract the tables from legacy BIOS and use them
>> within coreboot, if we don't stuff them in svn we should be fine.
>
> No, you would be fine, noone else. We can't redistribute ACPI tables
> from the factory BIOS.

I explicitely said they wouldn't be redistributed, just as the linux kernel
can have an updated DSDT to boot with, we could certainly allow the
load of external ACPI tables. But we wouldn't need to distribute them.

> And a coreboot using them could probably be
> argued to be a derivative work of the factory BIOS, and that is not
> so good from a licensing perspective.

That would be subject to local copyright laws, I think, and providing a
way to load external ACPI tables would not be a problem in itself.

What the final user does with his right or behind his closed doors
has no relationship with the fact that we allow to load external files.

Because we could certainly create the tables from scratch
ourselves if we would like...
(OK that would certainly be hard, but still...)

What would be cool, is an option in the coreboot build process to
use the ACPI tools to extract tables from the running legacy BIOS
and stuff them in the image being built. But would that be technically
possible ?

-- 
Vincent Legoll



From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 17:08:06 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 17:08:06 +0200
Subject: [coreboot] log2c, log2f and fms
Message-ID: <48BFF9D6.4090409@gmx.net>

Hi,

unless I'm mistaken, the fms() function is equivalent to log2f(), but
the former is in asm while the latter is in C.

Generally, I'd like to have a libmath.c with all these mathematical
functions. Having a file only for log2 variants is not exactly the most
optimal tree organization.

How do we treat functions which have an optimized asm version but also
exist as C code?
- Weak functions?
- Macro tricks like #ifdef _HAVE_ARCH_LOG2C ?
- Kill the optimized asm completely?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/



From r.marek at assembler.cz  Thu Sep  4 17:20:52 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 04 Sep 2008 17:20:52 +0200
Subject: [coreboot] Added Shuttle SN25P wiki page & links
In-Reply-To: <4727185d0809040805j59cb9b54g927ea6f85e90806c@mail.gmail.com>
References: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>	<20080904141141.20995.qmail@stuge.se>	<4727185d0809040730m43a9ae3ciee06b9d5edb616e3@mail.gmail.com>	<20080904144913.1726.qmail@stuge.se>
	<4727185d0809040805j59cb9b54g927ea6f85e90806c@mail.gmail.com>
Message-ID: <48BFFCD4.7070302@assembler.cz>

Hi,

The problem with use of original ACPI tables is different resources which might 
be static in the tables. Like I/O ports (legacy, smbus, pmio etc etc) Plus there 
might be some regions of memory reserved, which are not on Coreboot etc.

Basically it is not so difficult to create your own ACPI tables.

Check this http://www.coreboot.org/ACPI_in_coreboot

I'm using my own ACPI tables and it works very well.

Rudolf




From rminnich at gmail.com  Thu Sep  4 17:22:31 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 08:22:31 -0700
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
	more to come
In-Reply-To: <48BF53FE.8000705@gmx.net>
References: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>
	<48BF2CFE.6000307@gmx.net>
	<13426df10809031745l591c949dv8c9e1d8636b1668b@mail.gmail.com>
	<13426df10809031759q69fe8f03m1b62cf40a4a0e4fa@mail.gmail.com>
	<48BF53FE.8000705@gmx.net>
Message-ID: <13426df10809040822n5f10ca4cx8d40c4d6e6e6fa9@mail.gmail.com>

On Wed, Sep 3, 2008 at 8:20 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

>> struct device dev_root = {
>>       .path = { .type = DEVICE_PATH_ROOT },
>>       .next = &dev_cpu_0,
>>       .link = {
>>               [0] = {
>>                       .dev = &dev_root,
>>                       .link = 0,
>>                       .children = &dev_cpu_0
>>               },
>>               [1] = {
>>                       .dev = &dev_root,
>>                       .link = 0,
>>                       .children = &dev_apic_0
>>               },
>>               [2] = {
>>                       .dev = &dev_root,
>>                       .link = 0,
>>                       .children = &dev_domain_0
>>               },
>>       },
>>       .links = 3,
>>       .bus = &dev_root.link[0],
>>       .next = &dev_cpu_0,
>>       .ops = &default_dev_ops_root,
>>       .dtsname = "root",
>>       .enabled = 1
>> };
>>
>> Multiple links that work. Does this work? I don't know.
>>
>
> I'll try to modify a qemu target for testing and report back.

Thanks


>
>> I am not sure this it totally right yet, however:
>> struct device dev_domain_0 = {
>>       .path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
>>       .device_configuration = &domain_0,
>>       .ops = &geodelx_north_domain,
>>       .link = {
>>               [0] = {
>>                       .dev = &dev_domain_0,
>>                       .link = 0,
>>                       .children = &dev_pci_0_0_1_0
>>               },
>>
>>               [1] = {
>>                       .dev = &dev_domain_0,
>>                       .link = 0,
>>                       .children = &dev_pci_0_0_f_0
>>               },
>>               [2] = {
>>                       .dev = &dev_domain_0,
>>                       .link = 0,
>>                       .children = &dev_pci_0_0_f_2
>>               },
>>
>
> The list of links "feels" wrong. I can't yet express that feeling in
> technical terms, but I'll revisit this issue tomorrow.

it is wrong. :-)

Let's review links.

Links came in IIRC because of the k8. We needed a way to express the
HT links. It gets weird because on the k8, the HT address space is in
PCI space (this is actually a very nice thing AMD did). There are
three HT links, and they are all addressed as 0:18.0.

I never felt they way we expressed links in v2 was as clear as we
might have made them. How do you know a link is there?
It's not really explicitly named. You see this kind of comment in v2 Config.lb:

                        device pci 18.0 on #  northbridge
                                #  devices on link 0, link 0 == LDT 0

What would trigger that? How do we get to link 1? Turns out it happens
if we see this again:
                        device pci 18.0 on #  northbridge

config tool "knows" that it is now link 1. See tyan/s2892. It's not
just for HT either. And two children of a device in v2 having the same
path become links.

struct device _dev8 = {
        .ops = 0,
        .bus = &_dev6.link[0],
        .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x18,0)}}},
        .enabled = 1,
        .on_mainboard = 1,
        .link = {
                [0] = {
                        .link = 0,
                        .dev = &_dev8,
                        .children = &_dev10,
                },
                [1] = {
                        .link = 1,
                        .dev = &_dev8,
                },
                [2] = {
                        .link = 2,
                        .dev = &_dev8,
                        .children = &_dev72,
                },
        },
        .links = 3,
        .sibling = &_dev79,
        .next=&_dev10
};

dev10 is one pci bus, dev72 is the ck804.

Again, links come into play when multiple devices have the same path,
e.g. HT links on 18:0.0 (three of them) or I2C mux (2 of them). Again,
see tyan s2892.

So in the dts, what would this look like? Well, if we had:

pci at 18,0 {};
pci at 18,0 {};
pci at 18,0 {};

this might become three links. This is the v2 way of doing it. What I
wanted to do was something like this:
bus at 0 {pci at 18,0 {};};
bus at 1 {pci at 18,1 {};};

and so on. Really, if a bus is only ever going to be a link, maybe we
should rename "bus" to "link" and leave it at that.

So much for links.


Also, I see your point but:
struct device dev_pci_domain_0_bus_0_dev_1_fn_0

is just far more wordy than I like. Bear in mind that the primary goal
of this patch is to make the names unique.
Human readability is a secondary goal (no one ever looks at these
names anyway) and I think the long name you propose
is more than I would like to read all the time :-)


Thanks again

ron



From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 17:32:49 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 17:32:49 +0200
Subject: [coreboot] inline asm peculiarities in v3
Message-ID: <48BFFFA1.9040003@gmx.net>

Hi,

I decided to look at all cases of inline asm in our v3 code and I found
a few bits which either work by accident or need better documentation.

We use __asm__ and asm, __volatile__ and volatile. Can we please decide
which one we want, then I'll switch the tree over.

northbridge/amd/geodelx/vsmsetup.c:143
> __asm__(".text\n" "real_mode_switch_end:\n");
> extern char real_mode_switch_end[];
AFAICS the compiler and linker are free to place the resulting code
anywhere in the binary independent of each other.

include/arch/x86/amd/k8/k8.h:746
> static void disable_cache_as_ram_bsp(void)
> {
>         __asm__ volatile (
> //              "pushl %eax\n\t"
>                 "pushl %edx\n\t"
>                 "pushl %ecx\n\t"
>         );
>
>         disable_cache_as_ram();
>         __asm__ volatile (
>                 "popl %ecx\n\t"
>                 "popl %edx\n\t"
> //                "popl %eax\n\t"
>         );
> }
The pushl and popl instructions seem to serve no real purpose. Kill them?

The K8 CAR disabling has inline asm depending on good compiler behaviour
and luck. Patch will be sent separately.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Thu Sep  4 17:34:10 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 08:34:10 -0700
Subject: [coreboot] [PATCH] v3: more uniqueness in the dtc generated
	struct names
In-Reply-To: <48BF5150.9050804@gmx.net>
References: <48B87ED7.1030104@gmx.net> <48BF5150.9050804@gmx.net>
Message-ID: <13426df10809040834m1db2623fk4f5c316edfcc05b9@mail.gmail.com>

I like it. it's better than mine in the sense that  it is simple and
gets the job done.

But it does not add the new info to the nodes (the ints that contain
domain, bus, etc) in the tree that I think we ought to add. I also
prefer the consolidation of lots of work into labeltree() that my
patch does. Also, my patch does delete some code (although, sadly, I
grow the size overall). Finally, if we really want to use the links[]
support we can't do it with your patch.

So, your patch is better if we are trying to fix the uniquess problem
only; my patch is better if we want to ever use links[].

Now what :-)

ron



From svn at coreboot.org  Thu Sep  4 17:35:50 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 17:35:50 +0200
Subject: [coreboot] r857 - coreboot-v3/lib
Message-ID: <mailman.2028.1355071375.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-09-04 17:35:49 +0200 (Thu, 04 Sep 2008)
New Revision: 857

Modified:
   coreboot-v3/lib/console.c
Log:
Fix initial printk buffer address initialization. This was broken in
r785 (move from explicit asm to implicit C) and unfortunately qemu never
triggered the bug, only real hardware did. That's because qemu will not
spew an error on access to RAM before RAM is enabled.

Thanks to Ron for bisecting this.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/lib/console.c
===================================================================
--- coreboot-v3/lib/console.c	2008-09-04 00:38:54 UTC (rev 856)
+++ coreboot-v3/lib/console.c	2008-09-04 15:35:49 UTC (rev 857)
@@ -82,7 +82,9 @@
 
 void printk_buffer_init(void)
 {
-	struct printk_buffer *buf = printk_buffer_addr();
+	struct printk_buffer *buf = (struct printk_buffer *)PRINTK_BUF_ADDR_CAR;
+	global_vars()->printk_buffer = buf;
+	buf = printk_buffer_addr();
 	buf->len = PRINTK_BUF_SIZE_CAR - sizeof(struct printk_buffer);
 	buf->readoffset = 0;
 	buf->writeoffset = 0;




From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 17:36:21 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 17:36:21 +0200
Subject: [coreboot] [PATCH] v3: fix initial printk buffer
	address	initialization
In-Reply-To: <13426df10809040742q2669015ay43535dcdddbd9e5f@mail.gmail.com>
References: <48BF4986.6020009@gmx.net>
	<13426df10809040742q2669015ay43535dcdddbd9e5f@mail.gmail.com>
Message-ID: <48C00075.4030603@gmx.net>

On 04.09.2008 16:42, ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
> Not yet tested but it can't make it worse :-)
>   

Thanks, r857.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Thu Sep  4 17:42:40 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 08:42:40 -0700
Subject: [coreboot] log2c, log2f and fms
In-Reply-To: <48BFF9D6.4090409@gmx.net>
References: <48BFF9D6.4090409@gmx.net>
Message-ID: <13426df10809040842p411ec30o8266d71755933527@mail.gmail.com>

On Thu, Sep 4, 2008 at 8:08 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi,
>
> unless I'm mistaken, the fms() function is equivalent to log2f(), but
> the former is in asm while the latter is in C.

Let's get rid of fms then.

>
> Generally, I'd like to have a libmath.c with all these mathematical
> functions. Having a file only for log2 variants is not exactly the most
> optimal tree organization.
>
> How do we treat functions which have an optimized asm version but also
> exist as C code?
> - Weak functions?
> - Macro tricks like #ifdef _HAVE_ARCH_LOG2C ?
> - Kill the optimized asm completely?
>

(3). If you can do it in C, then asm goes away. I'd like to shoot all
asm in the head.

Also, please, let's minimize code in .h files. It just adds to (my)
the confusion :-)

The type of gratuitous use of assembly we sometimes see is Clever. This:
 http://research.swtch.com/2008/05/lessons-from-debianopenssl-fiasco.html
has an important point about Clever:

"# Try not to write clever code. Try to write well-organized code."

"# Inevitably, you will write clever, poorly-organized code. If
someone comes along asking questions about it, use that as a sign that
perhaps the code is probably too clever or not well enough organized.
Rewrite it to be simpler and easier to understand."

"# Avoid voodoo code. "

optimizing log2 in assembly when we call it almost never is, well,
Clever. Let's avoid it.

ron



From rminnich at gmail.com  Thu Sep  4 17:46:51 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 08:46:51 -0700
Subject: [coreboot] inline asm peculiarities in v3
In-Reply-To: <48BFFFA1.9040003@gmx.net>
References: <48BFFFA1.9040003@gmx.net>
Message-ID: <13426df10809040846g3435b158lf9aa4e48728bcd7d@mail.gmail.com>

On Thu, Sep 4, 2008 at 8:32 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi,
>
> I decided to look at all cases of inline asm in our v3 code and I found
> a few bits which either work by accident or need better documentation.
>
> We use __asm__ and asm, __volatile__ and volatile. Can we please decide
> which one we want, then I'll switch the tree over.

somebody who knows better than me the implications can comment.

>
> northbridge/amd/geodelx/vsmsetup.c:143
>> __asm__(".text\n" "real_mode_switch_end:\n");
>> extern char real_mode_switch_end[];
> AFAICS the compiler and linker are free to place the resulting code
> anywhere in the binary independent of each other.

Not a problem. The "extern" is simply making the label available to C.
They don't depend on any trickiness.

>
> include/arch/x86/amd/k8/k8.h:746
>> static void disable_cache_as_ram_bsp(void)
>> {
>>         __asm__ volatile (
>> //              "pushl %eax\n\t"
>>                 "pushl %edx\n\t"
>>                 "pushl %ecx\n\t"
>>         );
>>
>>         disable_cache_as_ram();
>>         __asm__ volatile (
>>                 "popl %ecx\n\t"
>>                 "popl %edx\n\t"
>> //                "popl %eax\n\t"
>>         );
>> }
> The pushl and popl instructions seem to serve no real purpose. Kill them?

My rule with the Clever v2 code is not to modify it until I understand
it. So I did not touch these because I don't know what function they
serve. That's one reason that I am bringing code over and leaving it
ugly to start. Let's leave this alone until K8 is working.

>
> The K8 CAR disabling has inline asm depending on good compiler behaviour
> and luck. Patch will be sent separately.
>

Thank you.

ron



From rminnich at gmail.com  Thu Sep  4 18:04:33 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 09:04:33 -0700
Subject: [coreboot] current dtc patch
Message-ID: <13426df10809040904x21350debo69777bd41cf567dc@mail.gmail.com>

no ack in it, for your viewing pleasure.

Tested on dbe62.

ron
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From daniel-coreboot at lindenaar.eu  Thu Sep  4 18:15:52 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar )
Date: Thu, 04 Sep 2008 18:15:52 +0200
Subject: [coreboot] via vt82c686 southbridge
Message-ID: <20080904181552.75624mmrfgeaxxfk@www.lindenaar.eu>

Hi everybody,
Too bad, first test boot didn't work... at all... I expected the early  
serial stuff to work at least (as this was already in svn, but...)

I'm using a very simple null-modem cable with only rx,tx and ground  
wired. Is this enough or does coreboot require a more complete cable?

Also, do I need some special settings to enable the debugging output?

I really feel like the newbie now, asking these basic questions :),  
but I also would really like to get this thing working on this  
motherboard...

regards Daniel


Quoting "Daniel Lindenaar" <daniel-coreboot at lindenaar.eu>:

> Hi everybody,
> I'm working on getting coreboot going on my 'thintune'. It's a thin  
> client PC with a custom motherboard based on the via vt8601 North  
> and vt82c686b south. I'm using coreboot v2 since v3 was stated to be  
> unstable (Is this the best choice?).
>
> I started out by porting some of the code for the 82c686 from the v1  
> project and using the code for the vt8235 to structure it in the v2  
> way. I've no clue if I've done it right or not, but there doesn't  
> seem to be very much documentation on that (feel free to point out  
> if there is...).
>
> I'm currently trying to get it built, but just found out that SMBus  
> seems to be needed for the RAM stuff, so I'm porting it over from  
> the 8235.
>
> Any tips, tricks and remarks are welcome. I'll give word when it  
> compiles and I've done a test boot.
>
> regards,
> Daniel Lindenaar
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>



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From rminnich at gmail.com  Thu Sep  4 18:16:58 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 09:16:58 -0700
Subject: [coreboot] [PATCH] v3: fix initial printk buffer address
	initialization
In-Reply-To: <48C00075.4030603@gmx.net>
References: <48BF4986.6020009@gmx.net>
	<13426df10809040742q2669015ay43535dcdddbd9e5f@mail.gmail.com>
	<48C00075.4030603@gmx.net>
Message-ID: <13426df10809040916k2ea9dcf3s25f1a94a1cc17762@mail.gmail.com>

On Thu, Sep 4, 2008 at 8:36 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 04.09.2008 16:42, ron minnich wrote:
>> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>>
>> Not yet tested but it can't make it worse :-)
>>
>
> Thanks, r857.
>

tested and working on dbe62!

ron



From daniel at lindenaar.eu  Thu Sep  4 17:55:24 2008
From: daniel at lindenaar.eu (Daniel Lindenaar)
Date: Thu, 04 Sep 2008 17:55:24 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48BEDF4F.1020405@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>
Message-ID: <20080904175524.854556r78he2jzls@www.lindenaar.eu>

Hi everybody,
Too bad, first test boot didn't work... at all... I expected the early  
serial stuff to work at least (as this was already in svn, but...)

I'm using a very simple null-modem cable with only rx,tx and ground  
wired. Is this enough or does coreboot require a more complete cable?

Also, do I need some special settings to enable the debugging output?

I really feel like the newbie now, asking these basic questions :),  
but I also would really like to get this thing working on this  
motherboard...

regards Daniel


Quoting "Daniel Lindenaar" <daniel-coreboot at lindenaar.eu>:

> Hi everybody,
> I'm working on getting coreboot going on my 'thintune'. It's a thin  
> client PC with a custom motherboard based on the via vt8601 North  
> and vt82c686b south. I'm using coreboot v2 since v3 was stated to be  
> unstable (Is this the best choice?).
>
> I started out by porting some of the code for the 82c686 from the v1  
> project and using the code for the vt8235 to structure it in the v2  
> way. I've no clue if I've done it right or not, but there doesn't  
> seem to be very much documentation on that (feel free to point out  
> if there is...).
>
> I'm currently trying to get it built, but just found out that SMBus  
> seems to be needed for the RAM stuff, so I'm porting it over from  
> the 8235.
>
> Any tips, tricks and remarks are welcome. I'll give word when it  
> compiles and I've done a test boot.
>
> regards,
> Daniel Lindenaar
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>



----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.



From c-d.hailfinger.devel.2006 at gmx.net  Thu Sep  4 19:21:36 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 04 Sep 2008 19:21:36 +0200
Subject: [coreboot] [PATCH] v3: fix initial printk buffer address
	initialization
In-Reply-To: <13426df10809040916k2ea9dcf3s25f1a94a1cc17762@mail.gmail.com>
References: <48BF4986.6020009@gmx.net>	
	<13426df10809040742q2669015ay43535dcdddbd9e5f@mail.gmail.com>	
	<48C00075.4030603@gmx.net>
	<13426df10809040916k2ea9dcf3s25f1a94a1cc17762@mail.gmail.com>
Message-ID: <48C01920.9050806@gmx.net>

On 04.09.2008 18:16, ron minnich wrote:
> On Thu, Sep 4, 2008 at 8:36 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> On 04.09.2008 16:42, ron minnich wrote:
>>     
>>> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>>>
>>> Not yet tested but it can't make it worse :-)
>>>
>>>       
>> Thanks, r857.
>>     
>
> tested and working on dbe62!
>   

Thanks for testing this!

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From corey.osgood at gmail.com  Thu Sep  4 19:26:06 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 4 Sep 2008 13:26:06 -0400
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <20080904175524.854556r78he2jzls@www.lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
Message-ID: <dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>

On Thu, Sep 4, 2008 at 11:55 AM, Daniel Lindenaar <daniel at lindenaar.eu> wrote:
> Hi everybody,
> Too bad, first test boot didn't work... at all... I expected the early
> serial stuff to work at least (as this was already in svn, but...)
>
> I'm using a very simple null-modem cable with only rx,tx and ground wired.
> Is this enough or does coreboot require a more complete cable?
>
> Also, do I need some special settings to enable the debugging output?
>
> I really feel like the newbie now, asking these basic questions :), but I
> also would really like to get this thing working on this motherboard...
>
> regards Daniel

Nope, that cable should be plenty, as long as it's good. A couple
things to check, when I wrote vt82c686's early serial stuff, I may
have configured it to use the second serial output, because I think
that's all my board had. I can't remember though, so check the
datasheet (I can't right now). Also, check that your debugging setup
actually works, boot linux with the stock bios and "console=tty0
console=ttyS0,115200" passed to linux. If you don't get a linux boot
log, something's wrong with your serial setup. If everything checks
out, send me a compressed copy of your tree, and I'll try to find the
problem.

-Corey



From stepan at coresystems.de  Thu Sep  4 19:26:31 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 04 Sep 2008 19:26:31 +0200
Subject: [coreboot] Added Shuttle SN25P wiki page & links
In-Reply-To: <4727185d0809040805j59cb9b54g927ea6f85e90806c@mail.gmail.com>
References: <4727185d0809040631j65bb2095p92f179e063578707@mail.gmail.com>	<20080904141141.20995.qmail@stuge.se>	<4727185d0809040730m43a9ae3ciee06b9d5edb616e3@mail.gmail.com>	<20080904144913.1726.qmail@stuge.se>
	<4727185d0809040805j59cb9b54g927ea6f85e90806c@mail.gmail.com>
Message-ID: <48C01A47.6020409@coresystems.de>

Vincent Legoll wrote:
>> And a coreboot using them could probably be
>> argued to be a derivative work of the factory BIOS, and that is not
>> so good from a licensing perspective.
>>     
>
> That would be subject to local copyright laws, I think, and providing a
> way to load external ACPI tables would not be a problem in itself.
>   

Remember though that just using "foreign" acpi tables will not work usually:

* Many DSDTs have pointers to other tables / data which need to be fixed
up during runtime or they will access memory in stupid locations
* Same applies for IO locations of certain hardware
* The ACPI code often communicates with an SMI handler in order to do
the deed. If there is no SMI handler there will not be a working ACPI
either.

Please look at the ACPI implementation in coreboot to get an idea what
is currently there. It will evolve over time. And if you have a system
that needs ACPI or benefits from it, the project would gain a lot more
if you developed ACPI support for that board instead of borrowing a
foreign implementation.
> What the final user does with his right or behind his closed doors
> has no relationship with the fact that we allow to load external files.
>   
What good is going through the effort of replacing your bios if you
replace it with a free-/non-free hybrid?

> Because we could certainly create the tables from scratch
> ourselves if we would like...
> (OK that would certainly be hard, but still...)
>   
We did that for a couple of boards already.

> What would be cool, is an option in the coreboot build process to
> use the ACPI tools to extract tables from the running legacy BIOS
> and stuff them in the image being built. But would that be technically
> possible ?
>   
Besides the fact that those tables wouldnt work with coreboot, I believe
technically it could be done, as long as you compile on the very system
you want to flash. (In which case you exactly have one try to get it
right ;)

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From todthgie at hotmail.com  Thu Sep  4 20:27:52 2008
From: todthgie at hotmail.com (a a)
Date: Thu, 4 Sep 2008 18:27:52 +0000
Subject: [coreboot] via vt82c686 southbridge
Message-ID: <BAY132-W246539FDD154D4AF831818C7590@phx.gbl>


Corey Osgood wrote:
> On Thu, Sep 4, 2008 at 11:55 AM, Daniel Lindenaar  wrote:
>> Hi everybody,
>> Too bad, first test boot didn't work... at all... I expected the early
>> serial stuff to work at least (as this was already in svn, but...)
>>
>> I'm using a very simple null-modem cable with only rx,tx and ground wired.
>> Is this enough or does coreboot require a more complete cable?
>>
>> Also, do I need some special settings to enable the debugging output?
>>
>> I really feel like the newbie now, asking these basic questions :), but I
>> also would really like to get this thing working on this motherboard...
>>
>> regards Daniel
> 
> Nope, that cable should be plenty, as long as it's good. A couple
> things to check, when I wrote vt82c686's early serial stuff, I may
> have configured it to use the second serial output, because I think
> that's all my board had. I can't remember though, so check the
> datasheet (I can't right now). Also, check that your debugging setup
> actually works, boot linux with the stock bios and "console=tty0
> console=ttyS0,115200" passed to linux. If you don't get a linux boot
> log, something's wrong with your serial setup. If everything checks
> out, send me a compressed copy of your tree, and I'll try to find the
> problem.
> 
> -Corey
> 
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 
> 

as far as i know the vt82c686 was already supported by coreboot v2..
i have it more or less working for my netier netexpress xl2000

first thing to check if no serial output is the io address op the 
superio eg 2E vs 4E ect

greetings,
todthgie


_________________________________________________________________
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From daniel-coreboot at lindenaar.eu  Thu Sep  4 20:30:24 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Thu, 04 Sep 2008 20:30:24 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
Message-ID: <48C02940.7040600@lindenaar.eu>

Corey Osgood wrote:
> On Thu, Sep 4, 2008 at 11:55 AM, Daniel Lindenaar <daniel at lindenaar.eu> wrote:
>   
>> Hi everybody,
>> Too bad, first test boot didn't work... at all... I expected the early
>> serial stuff to work at least (as this was already in svn, but...)
>>
>> I'm using a very simple null-modem cable with only rx,tx and ground wired.
>> Is this enough or does coreboot require a more complete cable?
>>
>> Also, do I need some special settings to enable the debugging output?
>>
>> I really feel like the newbie now, asking these basic questions :), but I
>> also would really like to get this thing working on this motherboard...
>>
>> regards Daniel
>>     
>
> Nope, that cable should be plenty, as long as it's good. A couple
> things to check, when I wrote vt82c686's early serial stuff, I may
> have configured it to use the second serial output, because I think
> that's all my board had. I can't remember though, so check the
> datasheet (I can't right now). Also, check that your debugging setup
> actually works, boot linux with the stock bios and "console=tty0
> console=ttyS0,115200" passed to linux. If you don't get a linux boot
> log, something's wrong with your serial setup. If everything checks
> out, send me a compressed copy of your tree, and I'll try to find the
> problem.
>
> -Corey
>   
Great! the com port was indeed nr2. That works better... well the
minimal version of better actually :/

coreboot-2.0.0.0Fallback Wed Sep  3 22:07:38 UTC 2008 starting...

This is all I'm seeing... I guess I should check loglevel and such.

Corey, If you're willing to help I'll be glad to send you my tree, but I
don't want to impose too much; but if you're willing ;)

regards,
Daniel


> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>   





From daniel-coreboot at lindenaar.eu  Thu Sep  4 20:42:34 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Thu, 04 Sep 2008 20:42:34 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <BAY132-W246539FDD154D4AF831818C7590@phx.gbl>
References: <BAY132-W246539FDD154D4AF831818C7590@phx.gbl>
Message-ID: <48C02C1A.8010206@lindenaar.eu>

a a wrote:
> Corey Osgood wrote:
> > On Thu, Sep 4, 2008 at 11:55 AM, Daniel Lindenaar wrote:
> >> Hi everybody,
> >> Too bad, first test boot didn't work... at all... I expected the early
> >> serial stuff to work at least (as this was already in svn, but...)
> >>
> >> I'm using a very simple null-modem cable with only rx,tx and ground 
> wired.
> >> Is this enough or does coreboot require a more complete cable?
> >>
> >> Also, do I need some special settings to enable the debugging output?
> >>
> >> I really feel like the newbie now, asking these basic questions :), 
> but I
> >> also would really like to get this thing working on this motherboard...
> >>
> >> regards Daniel
> >
> > Nope, that cable should be plenty, as long as it's good. A couple
> > things to check, when I wrote vt82c686's early serial stuff, I may
> > have configured it to use the second serial output, because I think
> > that's all my board had. I can't remember though, so check the
> > datasheet (I can't right now). Also, check that your debugging setup
> > actually works, boot linux with the stock bios and "console=tty0
> > console=ttyS0,115200" passed to linux. If you don't get a linux boot
> > log, something's wrong with your serial setup. If everything checks
> > out, send me a compressed copy of your tree, and I'll try to find the
> > problem.
> >
> > -Corey
> >
> > --
> > coreboot mailing list
> > coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> >
> >
>
> as far as i know the vt82c686 was already supported by coreboot v2..
> i have it more or less working for my netier netexpress xl2000
Do you have some details on that? I don't see that board in current svn 
and the only thing I saw on the 686 was the early serial... Maybe you 
could share your tree and/or adaptations?

thanks,
Daniel
>
> first thing to check if no serial output is the io address op the
> superio eg 2E vs 4E ect
>
> greetings,
> todthgie
>
>
> ------------------------------------------------------------------------
> Express yourself instantly with MSN Messenger! MSN Messenger 
> <http://clk.atdmt.com/AVE/go/onm00200471ave/direct/01/>
> ------------------------------------------------------------------------
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From daniel at lindenaar.eu  Thu Sep  4 20:27:38 2008
From: daniel at lindenaar.eu (Daniel Lindenaar)
Date: Thu, 04 Sep 2008 20:27:38 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
Message-ID: <48C0289A.1020203@lindenaar.eu>

Corey Osgood wrote:
> On Thu, Sep 4, 2008 at 11:55 AM, Daniel Lindenaar <daniel at lindenaar.eu> wrote:
>   
>> Hi everybody,
>> Too bad, first test boot didn't work... at all... I expected the early
>> serial stuff to work at least (as this was already in svn, but...)
>>
>> I'm using a very simple null-modem cable with only rx,tx and ground wired.
>> Is this enough or does coreboot require a more complete cable?
>>
>> Also, do I need some special settings to enable the debugging output?
>>
>> I really feel like the newbie now, asking these basic questions :), but I
>> also would really like to get this thing working on this motherboard...
>>
>> regards Daniel
>>     
>
> Nope, that cable should be plenty, as long as it's good. A couple
> things to check, when I wrote vt82c686's early serial stuff, I may
> have configured it to use the second serial output, because I think
> that's all my board had. I can't remember though, so check the
> datasheet (I can't right now). Also, check that your debugging setup
> actually works, boot linux with the stock bios and "console=tty0
> console=ttyS0,115200" passed to linux. If you don't get a linux boot
> log, something's wrong with your serial setup. If everything checks
> out, send me a compressed copy of your tree, and I'll try to find the
> problem.
>
> -Corey
>   
Great! the com port was indeed nr2. That works better... well the 
minimal version of better actually :/

coreboot-2.0.0.0Fallback Wed Sep  3 22:07:38 UTC 2008 starting...

This is all I'm seeing... I guess I should check loglevel and such.

Corey, If you're willing to help I'll be glad to send you my tree, but I 
don't want to impose too much; but if you're willing ;)

regards,
Daniel


> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>   




From jordan at chalmers.se  Thu Sep  4 22:08:32 2008
From: jordan at chalmers.se (Ulf Jordan)
Date: Thu, 4 Sep 2008 22:08:32 +0200 (CEST)
Subject: [coreboot] [PATCH] libpayload: serial output 8 bit clean
Message-ID: <Pine.LNX.4.63.0809042153580.10048@elfpc10.elmagn.chalmers.se>

The attached patch makes the serial output function serial_putchar() 8 bit 
clean. The motivation for this is that the low level driver should not 
modify the data in unexpected ways. Furthermore translate_special_chars() 
is removed, since that functionality is now provided by the ACS machinery 
in tinycurses.

Compile and runtime tested with coreinfo+libpayload+coreboot-v3 under 
QEMU.

/ulf
-------------- next part --------------
Make the serial output driver 8 bit clean. Remove translate_special_chars(),
since it has been superseeded by the ACS code in tinycurses.

Signed-off-by: Ulf Jordan <jordan at chalmers.se>

Index: libpayload/drivers/serial.c
===================================================================
--- libpayload/drivers/serial.c.orig	2008-09-03 22:38:45.000000000 +0200
+++ libpayload/drivers/serial.c	2008-09-03 22:39:02.000000000 +0200
@@ -37,25 +37,6 @@
 #define DIVISOR (115200 / CONFIG_SERIAL_BAUD_RATE)
 #endif
 
-/* This is a hack - we convert the drawing characters to ASCII */
-
-static unsigned char translate_special_chars(unsigned char c)
-{
-	switch(c) {
-	case 196:
-		return '-';
-	case 179:
-		return '|';
-	case 218:
-	case 191:
-	case 192:
-	case 217:
-		return '+';
-	default:
-		return ' ';
-	}
-}
-
 void serial_init(void)
 {
 #ifdef CONFIG_SERIAL_SET_SPEED
@@ -82,9 +63,6 @@
 
 void serial_putchar(unsigned char c)
 {
-	if (c > 127)
-		c = translate_special_chars(c);
-
 	while ((inb(IOBASE + 0x05) & 0x20) == 0) ;
 	outb(c, IOBASE);
 }

From peter at stuge.se  Thu Sep  4 22:17:56 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Sep 2008 22:17:56 +0200
Subject: [coreboot] [PATCH] libpayload: serial output 8 bit clean
In-Reply-To: <Pine.LNX.4.63.0809042153580.10048@elfpc10.elmagn.chalmers.se>
References: <Pine.LNX.4.63.0809042153580.10048@elfpc10.elmagn.chalmers.se>
Message-ID: <20080904201756.12577.qmail@stuge.se>

Ulf Jordan wrote:
> Make the serial output driver 8 bit clean. Remove translate_special_chars(),
> since it has been superseeded by the ACS code in tinycurses.
> 
> Signed-off-by: Ulf Jordan <jordan at chalmers.se>

Acked-by: Peter Stuge <peter at stuge.se>



From corey.osgood at gmail.com  Thu Sep  4 22:32:06 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 4 Sep 2008 16:32:06 -0400
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C02940.7040600@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
Message-ID: <dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>

On Thu, Sep 4, 2008 at 2:30 PM, Daniel Lindenaar
<daniel-coreboot at lindenaar.eu> wrote:
> Corey Osgood wrote:
>>
>> On Thu, Sep 4, 2008 at 11:55 AM, Daniel Lindenaar <daniel at lindenaar.eu>
>> wrote:
>>
>>>
>>> Hi everybody,
>>> Too bad, first test boot didn't work... at all... I expected the early
>>> serial stuff to work at least (as this was already in svn, but...)
>>>
>>> I'm using a very simple null-modem cable with only rx,tx and ground
>>> wired.
>>> Is this enough or does coreboot require a more complete cable?
>>>
>>> Also, do I need some special settings to enable the debugging output?
>>>
>>> I really feel like the newbie now, asking these basic questions :), but I
>>> also would really like to get this thing working on this motherboard...
>>>
>>> regards Daniel
>>>
>>
>> Nope, that cable should be plenty, as long as it's good. A couple
>> things to check, when I wrote vt82c686's early serial stuff, I may
>> have configured it to use the second serial output, because I think
>> that's all my board had. I can't remember though, so check the
>> datasheet (I can't right now). Also, check that your debugging setup
>> actually works, boot linux with the stock bios and "console=tty0
>> console=ttyS0,115200" passed to linux. If you don't get a linux boot
>> log, something's wrong with your serial setup. If everything checks
>> out, send me a compressed copy of your tree, and I'll try to find the
>> problem.
>>
>> -Corey
>>
>
> Great! the com port was indeed nr2. That works better... well the
> minimal version of better actually :/
>
> coreboot-2.0.0.0Fallback Wed Sep  3 22:07:38 UTC 2008 starting...
>
> This is all I'm seeing... I guess I should check loglevel and such.
>
> Corey, If you're willing to help I'll be glad to send you my tree, but I
> don't want to impose too much; but if you're willing ;)

Well, serial's working now ;) Looks like you're dying either somewhere
in SMBus or ram init. I'd start with inserting LOTS of debug messages,
and turning the log level up to 9. The more messages you have, the
easier it is to pinpoint where it dies. I can try to help, but I'm not
sure how much I can ;)

-Corey



From svn at coreboot.org  Thu Sep  4 23:05:59 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  4 Sep 2008 23:05:59 +0200
Subject: [coreboot] r3565 - trunk/payloads/libpayload/drivers
Message-ID: <mailman.2029.1355071375.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-09-04 23:05:59 +0200 (Thu, 04 Sep 2008)
New Revision: 3565

Modified:
   trunk/payloads/libpayload/drivers/serial.c
Log:
Make the serial output driver 8 bit clean. Remove translate_special_chars(),    
since it has been superseeded by the ACS code in tinycurses.
  
Signed-off-by: Ulf Jordan <jordan at chalmers.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/payloads/libpayload/drivers/serial.c
===================================================================
--- trunk/payloads/libpayload/drivers/serial.c	2008-09-04 13:44:00 UTC (rev 3564)
+++ trunk/payloads/libpayload/drivers/serial.c	2008-09-04 21:05:59 UTC (rev 3565)
@@ -37,25 +37,6 @@
 #define DIVISOR (115200 / CONFIG_SERIAL_BAUD_RATE)
 #endif
 
-/* This is a hack - we convert the drawing characters to ASCII */
-
-static unsigned char translate_special_chars(unsigned char c)
-{
-	switch(c) {
-	case 196:
-		return '-';
-	case 179:
-		return '|';
-	case 218:
-	case 191:
-	case 192:
-	case 217:
-		return '+';
-	default:
-		return ' ';
-	}
-}
-
 void serial_init(void)
 {
 #ifdef CONFIG_SERIAL_SET_SPEED
@@ -82,9 +63,6 @@
 
 void serial_putchar(unsigned char c)
 {
-	if (c > 127)
-		c = translate_special_chars(c);
-
 	while ((inb(IOBASE + 0x05) & 0x20) == 0) ;
 	outb(c, IOBASE);
 }




From peter at stuge.se  Thu Sep  4 23:06:15 2008
From: peter at stuge.se (Peter Stuge)
Date: Thu, 4 Sep 2008 23:06:15 +0200
Subject: [coreboot] [PATCH] libpayload: serial output 8 bit clean
In-Reply-To: <20080904201756.12577.qmail@stuge.se>
References: <Pine.LNX.4.63.0809042153580.10048@elfpc10.elmagn.chalmers.se>
	<20080904201756.12577.qmail@stuge.se>
Message-ID: <20080904210615.26064.qmail@stuge.se>

Peter Stuge wrote:
> Ulf Jordan wrote:
> > Make the serial output driver 8 bit clean. Remove translate_special_chars(),
> > since it has been superseeded by the ACS code in tinycurses.
> > 
> > Signed-off-by: Ulf Jordan <jordan at chalmers.se>
> 
> Acked-by: Peter Stuge <peter at stuge.se>

r3565



From daniel-coreboot at lindenaar.eu  Thu Sep  4 23:20:46 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Thu, 04 Sep 2008 23:20:46 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
Message-ID: <48C0512E.9050104@lindenaar.eu>

Corey Osgood wrote:
> On Thu, Sep 4, 2008 at 2:30 PM, Daniel Lindenaar
> <daniel-coreboot at lindenaar.eu> wrote:
>   
>> Corey Osgood wrote:
>>     
>>> On Thu, Sep 4, 2008 at 11:55 AM, Daniel Lindenaar <daniel at lindenaar.eu>
>>> wrote:
>>>
>>>       
>>>> Hi everybody,
>>>> Too bad, first test boot didn't work... at all... I expected the early
>>>> serial stuff to work at least (as this was already in svn, but...)
>>>>
>>>> I'm using a very simple null-modem cable with only rx,tx and ground
>>>> wired.
>>>> Is this enough or does coreboot require a more complete cable?
>>>>
>>>> Also, do I need some special settings to enable the debugging output?
>>>>
>>>> I really feel like the newbie now, asking these basic questions :), but I
>>>> also would really like to get this thing working on this motherboard...
>>>>
>>>> regards Daniel
>>>>
>>>>         
>>> Nope, that cable should be plenty, as long as it's good. A couple
>>> things to check, when I wrote vt82c686's early serial stuff, I may
>>> have configured it to use the second serial output, because I think
>>> that's all my board had. I can't remember though, so check the
>>> datasheet (I can't right now). Also, check that your debugging setup
>>> actually works, boot linux with the stock bios and "console=tty0
>>> console=ttyS0,115200" passed to linux. If you don't get a linux boot
>>> log, something's wrong with your serial setup. If everything checks
>>> out, send me a compressed copy of your tree, and I'll try to find the
>>> problem.
>>>
>>> -Corey
>>>
>>>       
>> Great! the com port was indeed nr2. That works better... well the
>> minimal version of better actually :/
>>
>> coreboot-2.0.0.0Fallback Wed Sep  3 22:07:38 UTC 2008 starting...
>>
>> This is all I'm seeing... I guess I should check loglevel and such.
>>
>> Corey, If you're willing to help I'll be glad to send you my tree, but I
>> don't want to impose too much; but if you're willing ;)
>>     
>
> Well, serial's working now ;) Looks like you're dying either somewhere
> in SMBus or ram init. I'd start with inserting LOTS of debug messages,
> and turning the log level up to 9. The more messages you have, the
> easier it is to pinpoint where it dies. I can try to help, but I'm not
> sure how much I can ;)
>
> -Corey
>
>   
hmmm it's working partly, it seems. First i did something wrong that 
skrewed up the com port setup, which I fixed. I now get the debug 
messages I added via the serial line, but, strangely, only when i do a 
(warm) reboot from a running linux, not with a cold boot... probably 
something needs to be set that doesn't get set by default on cold reboot.

Anyway, it's the SMBus controller where things go wrong; the log says:

SMBUS controller not found

as the last item. At least some progress is made. Besides the logging 
not working on cold boot, which it should at some point, I've now got 
something that works well enough to start proper debugging.

regards,
Daniel
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>   




From rminnich at gmail.com  Thu Sep  4 23:26:29 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 14:26:29 -0700
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C0512E.9050104@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu>
Message-ID: <13426df10809041426l1e91193cx38f56a9f7142c6a@mail.gmail.com>

in other words, you boot the factory bios, boot linux, swap flash
part, reboot, and there's no smbus controller? This is probably an I2C
mux then.

ron



From rminnich at gmail.com  Thu Sep  4 23:27:09 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 14:27:09 -0700
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <13426df10809041426l1e91193cx38f56a9f7142c6a@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu>
	<13426df10809041426l1e91193cx38f56a9f7142c6a@mail.gmail.com>
Message-ID: <13426df10809041427h296c0ba7x547721487081509c@mail.gmail.com>

On Thu, Sep 4, 2008 at 2:26 PM, ron minnich <rminnich at gmail.com> wrote:
> in other words, you boot the factory bios, boot linux, swap flash
> part, reboot, and there's no smbus controller? This is probably an I2C
> mux then.
>

now why'd I say that? This is *possibly* an i2c mux but more likely
the smbus device has some weird enable bit. What's the pci discovery
stuff in coreboot show?

ron



From stepan at coresystems.de  Thu Sep  4 23:41:32 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 04 Sep 2008 23:41:32 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C0512E.9050104@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu>
Message-ID: <48C0560C.9040500@coresystems.de>

Daniel Lindenaar wrote: 
> hmmm it's working partly, it seems. First i did something wrong that
> skrewed up the com port setup, which I fixed. I now get the debug
> messages I added via the serial line, but, strangely, only when i do a
> (warm) reboot from a running linux, not with a cold boot... 
This sounds an awful lot like superio init, or some GPIO issue.

Are you initializing your superio correctly? Does your board use the
82c686 superio? Or does it have an extra superio?
(Check with superiotool)

> probably something needs to be set that doesn't get set by default on
> cold reboot.
>
> Anyway, it's the SMBus controller where things go wrong; the log says:
>
> SMBUS controller not found 
What device are you looking for at that point?

On the vt82c686 the smbus device has vendor 0x1106 and device 0x3057




-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


-------------- next part --------------
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From stepan at coresystems.de  Thu Sep  4 23:50:36 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 04 Sep 2008 23:50:36 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48BEDF4F.1020405@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>
Message-ID: <48C0582C.2030100@coresystems.de>

Daniel Lindenaar wrote:
> I'm currently trying to get it built, but just found out that SMBus
> seems to be needed for the RAM stuff, so I'm porting it over from the
> 8235.

Be careful, the 686 has different PCI IDs and different offsets..

on the 8235 the smbus io base is at 0xd0, on the c686 it's at 0x90



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866


-------------- next part --------------
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From r.marek at assembler.cz  Fri Sep  5 00:24:09 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 05 Sep 2008 00:24:09 +0200
Subject: [coreboot] [PATCH] do not advertise HPET on A8V-E SE
Message-ID: <48C06009.6040505@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello,

Attached patch removes HPET info from ACPI tables. HPET does not work fine on
VT8237R (random keyboard/mouse lockups). In folowup patch I will remove HPET
from VT8237R setup code too.

Running system without HPET for half a year and its really because of it ;)

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf
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From mats.andersson at gisladisker.se  Fri Sep  5 00:24:41 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Fri, 05 Sep 2008 00:24:41 +0200
Subject: [coreboot] v2: The elfboot process with 128MB RAM
Message-ID: <E1KbNFp-0007Q1-Cx@aun.bellman.mea>

Hello all,

I could use some of your insight into the elfboot stage.
Appended to this message are two printouts of the elfboot
process for 128MB RAM (which comes to a halt), and for
64MB RAM (which succeeds). It is jmp_to_elf_entry() in

   src/arch/i386/boot/boot.c

that is unable to complete the set task for 128MB RAM.
I suspect that the problem lies in the value of
'bounce_buffer' that is determined in src/boot/elfboot.c,
but I fail to identify why a large value is causing
any problem at all. The informational "Candidate bounce_buffer"
is my addition at the loop end in get_bounce_buffer().

Since FILO never starts with 128MB, I cannot verify that the
linuxbios_table indeed gets the expected last entry

 "convert_memmap: 0x00000000100000 0x00000007f00000 1",

which the debugging output for FILO for 64MB would suggest.

A slightly provocative question:

Is the elfboot process implicitly hardcoded to depend on
no more than 64MB RAM? My setup makes sure that PAM#, RPS,
and PGPOL are correct (to my understanding) for distribution
of memory: 64MB, 64MB+64MB, 64MB+0MB+64MB, etc.

I will be much obliged for any pointers. They will all
help me to understand the code base better than presently.

Best regards,

Mats E Andersson


##
## 64MB + 64MB RAM
##

Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0400 to 0x00100000
Wrote coreboot table at: 00000530 - 00000734  checksum ed60

elfboot: Attempting to load payload.
rom_stream: 0xfffe0000 - 0xfffeffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
Candidate bounce_buffer: 0x0000054000.
Candidate bounce_buffer: 0x0007fb4000.
malloc Enter, size 32, free_mem_ptr 0002757c
malloc 0x0002757c
New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88
(cleaned up) New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88
lb: [0x0000000000004000, 0x000000000002a000)
malloc Enter, size 32, free_mem_ptr 0002759c
malloc 0x0002759c
New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48
(cleaned up) New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48
lb: [0x0000000000004000, 0x000000000002a000)
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036000 filesz: 0x000000000000cb88
[ 0x0000000000100000, 000000000010cb88, 0x0000000000136000) <- 00000000000000c0
Clearing Segment: addr: 0x000000000010cb88 memsz: 0x0000000000029478
Loading Segment: addr: 0x0000000000136000 memsz: 0x0000000000000048 filesz: 0x0000000000000048
[ 0x0000000000136000, 0000000000136048, 0x0000000000136048) <- 000000000000cc60
Loaded segments
verified segments
closed down stream
Jumping to boot code at 0x100078
entry    = 0x00100078
lb_start = 0x00004000
lb_size  = 0x00026000
buffer   = 0x07fb4000
adjust   = 0x07fd6000
     elf_boot_notes = 0x0001f640
adjusted_boot_notes = 0x07ff5640

## The system is stuck here!
##
## Next case:

##
## 64MB
##

Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0400 to 0x00100000
Wrote coreboot table at: 00000530 - 00000734  checksum ab60

elfboot: Attempting to load payload.
rom_stream: 0xfffe0000 - 0xfffeffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
Candidate bounce_buffer: 0x0000054000.
Candidate bounce_buffer: 0x0003fb4000.
malloc Enter, size 32, free_mem_ptr 0002757c
malloc 0x0002757c
New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88
(cleaned up) New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88
lb: [0x0000000000004000, 0x000000000002a000)
malloc Enter, size 32, free_mem_ptr 0002759c
malloc 0x0002759c
New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48
(cleaned up) New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48
lb: [0x0000000000004000, 0x000000000002a000)
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036000 filesz: 0x000000000000cb88
[ 0x0000000000100000, 000000000010cb88, 0x0000000000136000) <- 00000000000000c0
Clearing Segment: addr: 0x000000000010cb88 memsz: 0x0000000000029478
Loading Segment: addr: 0x0000000000136000 memsz: 0x0000000000000048 filesz: 0x0000000000000048
[ 0x0000000000136000, 0000000000136048, 0x0000000000136048) <- 000000000000cc60
Loaded segments
verified segments
closed down stream
Jumping to boot code at 0x100078
entry    = 0x00100078
lb_start = 0x00004000
lb_size  = 0x00026000
buffer   = 0x03fb4000
adjust   = 0x03fd6000
     elf_boot_notes = 0x0001f640
adjusted_boot_notes = 0x03ff5640
FILO version 0.5.6 (mats at asus) Thu Sep  4 22:51:36 CEST 2008
collect_linuxbios_info: Searching for LinuxBIOS tables...
find_lb_table: Found candidate at: 00000530
find_lb_table: header checksum o.k.
find_lb_table: table checksum o.k.
find_lb_table: record count o.k.
collect_linuxbios_info: Found LinuxBIOS table at: 00000530
convert_memmap: 0x00000000000000 0x00000000001000 16
convert_memmap: 0x00000000001000 0x0000000009f000 1
convert_memmap: 0x000000000c0000 0x00000000030000 1
convert_memmap: 0x000000000f0000 0x00000000010000 16
convert_memmap: 0x00000000100000 0x00000003f00000 1
Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 usr=flash
IDE time out
reset failed, but we may be on SATA
Drive 0 does not exist
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 usr=flash



From r.marek at assembler.cz  Fri Sep  5 00:33:37 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 05 Sep 2008 00:33:37 +0200
Subject: [coreboot] [PATCH] fix K8M890
Message-ID: <48C06241.6010307@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello

Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the
D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
whole PCI bus.

U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
does we not.

Second small change just changes a bit which controls the PSTATECTL logic.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf
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From stepan at coresystems.de  Fri Sep  5 00:42:37 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Sep 2008 00:42:37 +0200
Subject: [coreboot] v2: The elfboot process with 128MB RAM
In-Reply-To: <E1KbNFp-0007Q1-Cx@aun.bellman.mea>
References: <E1KbNFp-0007Q1-Cx@aun.bellman.mea>
Message-ID: <48C0645D.2070908@coresystems.de>

Mats Erik Andersson wrote:
> Hello all,
>
> I could use some of your insight into the elfboot stage.
> Appended to this message are two printouts of the elfboot
> process for 128MB RAM (which comes to a halt), and for
> 64MB RAM (which succeeds). It is jmp_to_elf_entry() in
>
>    src/arch/i386/boot/boot.c
>
> that is unable to complete the set task for 128MB RAM.
> I suspect that the problem lies in the value of
> 'bounce_buffer' that is determined in src/boot/elfboot.c,
> but I fail to identify why a large value is causing
> any problem at all. The informational "Candidate bounce_buffer"
> is my addition at the loop end in get_bounce_buffer().
>
> Since FILO never starts with 128MB, I cannot verify that the
> linuxbios_table indeed gets the expected last entry
Are you sure your second 64M are working correctly?

This could well be a ram init problem.

Which board?

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From r.marek at assembler.cz  Fri Sep  5 00:48:25 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 05 Sep 2008 00:48:25 +0200
Subject: [coreboot] [PATCH] Add VIA VT8237S support
Message-ID: <48C065B9.6020605@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello,

Its here! SATA issue solved (thanks for hint VIA!). This patch adds support for
the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested
on mine desktop) except of reverting the small change introduced by Bari
(gpio/inta setup reg 0x5b). This should go for some board specific file. The
change would broke at least mine board. But seems to be needed for jakllsch.

Please someone try to fix it.

Ok now back to patch.

VT8237S peripherals:

SPI flash - works, flashing fine
SATA - now works, maybe need adjustments for your PCB
USB - OK works
IDE - OK works
Network - OK works even if the board has no own flash - new code has to be
called, default MAC will be 00:00:DE:AD:BE:EF.
Sound - untested may work

ACPI - works
APIC - works

Please try to ack the patch quickly, because a lot of people needs to dig into
those files :)

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf

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From r.marek at assembler.cz  Fri Sep  5 00:57:47 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 05 Sep 2008 00:57:47 +0200
Subject: [coreboot] [PATCH] Add support for Asus M2V-MX SE
Message-ID: <48C067EB.6080506@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello,

Following patch adds support for Asus M2V-E SE. Works pretty well, the only
problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers
recently released, maybe with OpenChrome too.

It wont work with the little patch attached, somehow mine default value on
superIO is different. Any idea how to solve that?

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf
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From rminnich at gmail.com  Fri Sep  5 01:39:23 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 16:39:23 -0700
Subject: [coreboot] IASL has moved
Message-ID: <13426df10809041639x2efa997akeaa6a3c4c734c69c@mail.gmail.com>

This page: http://www.coreboot.org/FAQ

references this page: http://www.intel.com/technology/iapc/acpi/downloads.htm

which is gone :-(

search for iasl says:
Your search - iasl - did not match any documents.
No pages were found containing "iasl"

oh boy.

But there is a package from yum :-)

ron



From jordan.crouse at amd.com  Fri Sep  5 01:52:31 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 4 Sep 2008 17:52:31 -0600
Subject: [coreboot] IASL has moved
In-Reply-To: <13426df10809041639x2efa997akeaa6a3c4c734c69c@mail.gmail.com>
References: <13426df10809041639x2efa997akeaa6a3c4c734c69c@mail.gmail.com>
Message-ID: <20080904235231.GA31555@cosmic.amd.com>

On 04/09/08 16:39 -0700, ron minnich wrote:
> This page: http://www.coreboot.org/FAQ
> 
> references this page: http://www.intel.com/technology/iapc/acpi/downloads.htm
> 
> which is gone :-(

It is now:
http://acpica.org/downloads/unix_source_code_cont.php

Jordan




From rminnich at gmail.com  Fri Sep  5 01:55:50 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 16:55:50 -0700
Subject: [coreboot] IASL has moved
In-Reply-To: <20080904235231.GA31555@cosmic.amd.com>
References: <13426df10809041639x2efa997akeaa6a3c4c734c69c@mail.gmail.com>
	<20080904235231.GA31555@cosmic.amd.com>
Message-ID: <13426df10809041655j6c6fd079pab254e396de5fc3a@mail.gmail.com>

On Thu, Sep 4, 2008 at 4:52 PM, Jordan Crouse <jordan.crouse at amd.com> wrote:
> On 04/09/08 16:39 -0700, ron minnich wrote:
>> This page: http://www.coreboot.org/FAQ
>>
>> references this page: http://www.intel.com/technology/iapc/acpi/downloads.htm
>>
>> which is gone :-(
>
> It is now:
> http://acpica.org/downloads/unix_source_code_cont.php

Thanks I fixed the web page. Now we get to fix every single script
because the command names have changed :-)

ron



From jordan.crouse at amd.com  Fri Sep  5 02:00:03 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Thu, 4 Sep 2008 18:00:03 -0600
Subject: [coreboot] IASL has moved
In-Reply-To: <13426df10809041655j6c6fd079pab254e396de5fc3a@mail.gmail.com>
References: <13426df10809041639x2efa997akeaa6a3c4c734c69c@mail.gmail.com>
	<20080904235231.GA31555@cosmic.amd.com>
	<13426df10809041655j6c6fd079pab254e396de5fc3a@mail.gmail.com>
Message-ID: <20080905000003.GB31555@cosmic.amd.com>

On 04/09/08 16:55 -0700, ron minnich wrote:
> On Thu, Sep 4, 2008 at 4:52 PM, Jordan Crouse <jordan.crouse at amd.com> wrote:
> > On 04/09/08 16:39 -0700, ron minnich wrote:
> >> This page: http://www.coreboot.org/FAQ
> >>
> >> references this page: http://www.intel.com/technology/iapc/acpi/downloads.htm
> >>
> >> which is gone :-(
> >
> > It is now:
> > http://acpica.org/downloads/unix_source_code_cont.php
> 
> Thanks I fixed the web page. Now we get to fix every single script
> because the command names have changed :-)

Huh?  Not according to the aspcia.org git tree - its still iasl:

http://git.acpica.org/repos/?p=acpica.git;a=blob;f=generate/linux/Makefile.iasl;h=85b52a83b33407e646a1325f627b3007fdfd10eb;hb=HEAD

Jordan


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From vincent.legoll at gmail.com  Fri Sep  5 02:00:16 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Fri, 5 Sep 2008 02:00:16 +0200
Subject: [coreboot] Kernel hang solid
Message-ID: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>

Could someone explain the differences in linux kernel boot
logs for coreboot vs BIOS that are attached. The coreboot
log is here too, just in case.

The total absence of reserved memory ranges seems
unnatural. The DMA zone range starting at 0x00000001
looks fishy too.

I'm completely lost, the hang happen at init/main.c in
console_init()

-- 
Vincent Legoll
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From rminnich at gmail.com  Fri Sep  5 02:02:58 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 17:02:58 -0700
Subject: [coreboot] IASL has moved
In-Reply-To: <20080905000003.GB31555@cosmic.amd.com>
References: <13426df10809041639x2efa997akeaa6a3c4c734c69c@mail.gmail.com>
	<20080904235231.GA31555@cosmic.amd.com>
	<13426df10809041655j6c6fd079pab254e396de5fc3a@mail.gmail.com>
	<20080905000003.GB31555@cosmic.amd.com>
Message-ID: <13426df10809041702g4e06dc48tbccf25d2b500cb46@mail.gmail.com>

On Thu, Sep 4, 2008 at 5:00 PM, Jordan Crouse <jordan.crouse at amd.com> wrote:
> On 04/09/08 16:55 -0700, ron minnich wrote:
>> On Thu, Sep 4, 2008 at 4:52 PM, Jordan Crouse <jordan.crouse at amd.com> wrote:
>> > On 04/09/08 16:39 -0700, ron minnich wrote:
>> >> This page: http://www.coreboot.org/FAQ
>> >>
>> >> references this page: http://www.intel.com/technology/iapc/acpi/downloads.htm
>> >>
>> >> which is gone :-(
>> >
>> > It is now:
>> > http://acpica.org/downloads/unix_source_code_cont.php
>>
>> Thanks I fixed the web page. Now we get to fix every single script
>> because the command names have changed :-)
>
> Huh?  Not according to the aspcia.org git tree - its still iasl:
>
> http://git.acpica.org/repos/?p=acpica.git;a=blob;f=generate/linux/Makefile.iasl;h=85b52a83b33407e646a1325f627b3007fdfd10eb;hb=HEAD
>

yeah you're right. I looked at these other commands and ASSuMEd:
 AcpiExec simulator/user-space-interpreter:
$ cd acpica-unix-VERSION/tools/acpiexec
$ make

AcpiXtract table extraction utility:
$ cd acpica-unix-VERSION/tools/acpixtract
$ make

oops.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 03:49:03 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 03:49:03 +0200
Subject: [coreboot] [PATCH] v3: correct K8 stack preservation asm
Message-ID: <48C0900F.8050409@gmx.net>

The current K8 stack preservation code in disable_car() works by chance,
but that's not something we should rely on.

The new code is entirely rewritten, fixes a few missing constraints in
the asm and should be a lot more readable. However, the generated code
should be mostly identical.

Attached for Ron.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: corebootv3-k8_car_disable_inline_asm/arch/x86/amd/k8/stage1.c
===================================================================
--- corebootv3-k8_car_disable_inline_asm/arch/x86/amd/k8/stage1.c	(Revision 856)
+++ corebootv3-k8_car_disable_inline_asm/arch/x86/amd/k8/stage1.c	(Arbeitskopie)
@@ -34,20 +34,31 @@
  */
 void disable_car(void)
 {
-	/* OK, here is the theory: we should be able to copy 
-	 * the data back over itself, and the wbinvd should then 
-	 * flush to memory. Let's see. 
-	 */
-	/* nope. 
-	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
-	 */
 	/* call the inlined function */
 	disable_cache_as_ram();
 
-	/* copy it down, wbinvd, copy it back? */
-	__asm__ __volatile__("cld; rep movsl" ::"D" (0x88000), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
-	__asm__ __volatile__ ("wbinvd\n");
-	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (0x88000), "c" (CONFIG_CARSIZE/4): "memory");
+	/* The BKDG says that a WBINVD will not flush CAR to RAM (because the
+	 * cache tags are not dirty).
+	 * Solution:
+	 * - Two subsequent memcpy in the same inline asm block, one from stack
+	 *   to backup, one from backup to stack.
+	 * The solution for geode of using a inline asm memcpy of the stack
+	 * onto itself will not mark the cache tags as dirty on K8.
+	 */
+	__asm__ __volatile__(
+	"	movl %[carbase], %%esi		\n"
+	"	movl %[backuplocation], %%edi	\n"
+	"	movl %[carsizequads], %%ecx	\n"
+	"	cld				\n"
+	"	rep movsl			\n"
+	"	wbinvd				\n"
+	"	movl %[backuplocation], %%esi	\n"
+	"	movl %[carbase], %%edi		\n"
+	"	movl %[carsizequads], %%ecx	\n"
+	"	rep movsl			\n"
+	:: [carbase] "i" (CONFIG_CARBASE), [backuplocation] "i" (0x88000),
+	   [carsizequads] "i" (CONFIG_CARSIZE/4)
+	: "memory", "%edi", "%esi", "%ecx");
 	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
 	banner(BIOS_DEBUG, "disable_car: done");
 }


-- 
http://www.hailfinger.org/

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From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 03:50:12 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 03:50:12 +0200
Subject: [coreboot] inline asm peculiarities in v3
In-Reply-To: <13426df10809040846g3435b158lf9aa4e48728bcd7d@mail.gmail.com>
References: <48BFFFA1.9040003@gmx.net>
	<13426df10809040846g3435b158lf9aa4e48728bcd7d@mail.gmail.com>
Message-ID: <48C09054.4090109@gmx.net>

On 04.09.2008 17:46, ron minnich wrote:
> On Thu, Sep 4, 2008 at 8:32 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> Hi,
>>
>> I decided to look at all cases of inline asm in our v3 code and I found
>> a few bits which either work by accident or need better documentation.
>>
>> We use __asm__ and asm, __volatile__ and volatile. Can we please decide
>> which one we want, then I'll switch the tree over.
>>     
>
> somebody who knows better than me the implications can comment.
>   

The gcc info page states that __asm__ and asm are equivalent, but if you
use -ansi or -fno-asm or -fno-gnu-keywords in your CFLAGS only __asm__
will be recognized. asm is shorter, so I'd prefer asm.
__volatile__ vs. volatile is not explained in the gcc docs at all, but
various places on the net state that they're identical.

Segher confirmed these findings. I'll send a patch to move everything to
the short syntax.


>> northbridge/amd/geodelx/vsmsetup.c:143
>>     
>>> __asm__(".text\n" "real_mode_switch_end:\n");
>>> extern char real_mode_switch_end[];
>>>       
>> AFAICS the compiler and linker are free to place the resulting code
>> anywhere in the binary independent of each other.
>>     
>
> Not a problem. The "extern" is simply making the label available to C.
> They don't depend on any trickiness.
>   

My point was about the label. Sorry for being unclear. That label can be
placed anywhere, so I can't see it serving any purpose.


>> include/arch/x86/amd/k8/k8.h:746
>>     
>>> static void disable_cache_as_ram_bsp(void)
>>> {
>>>         __asm__ volatile (
>>> //              "pushl %eax\n\t"
>>>                 "pushl %edx\n\t"
>>>                 "pushl %ecx\n\t"
>>>         );
>>>
>>>         disable_cache_as_ram();
>>>         __asm__ volatile (
>>>                 "popl %ecx\n\t"
>>>                 "popl %edx\n\t"
>>> //                "popl %eax\n\t"
>>>         );
>>> }
>>>       
>> The pushl and popl instructions seem to serve no real purpose. Kill them?
>>     
>
> My rule with the Clever v2 code is not to modify it until I understand
> it. So I did not touch these because I don't know what function they
> serve. That's one reason that I am bringing code over and leaving it
> ugly to start. Let's leave this alone until K8 is working.
>   

But can I add a comment that the current code seems nonsensical?


>> The K8 CAR disabling has inline asm depending on good compiler behaviour
>> and luck. Patch will be sent separately.
>>     
>
> Thank you.
>   

You're welcome. See the mail with subject "[PATCH] v3: correct K8 stack
preservation asm".

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 03:57:33 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 03:57:33 +0200
Subject: [coreboot] inline asm peculiarities in v3
In-Reply-To: <48C09054.4090109@gmx.net>
References: <48BFFFA1.9040003@gmx.net>	<13426df10809040846g3435b158lf9aa4e48728bcd7d@mail.gmail.com>
	<48C09054.4090109@gmx.net>
Message-ID: <48C0920D.3010902@gmx.net>

By the way, we have quite a few asm statements which have incorrect
clobber constraints. That could lead to all sorts of mayhem if gcc
becomes more clever.

Oh, and at least for geodelx we break gcc ABI expectations by not
clearing the direction flag in stage0 asm.

I'll send patches in a few days unless someone else wants to tackle this.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 04:12:08 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 04:12:08 +0200
Subject: [coreboot] [PATCH] v3: correct K8 stack preservation asm
In-Reply-To: <48C0900F.8050409@gmx.net>
References: <48C0900F.8050409@gmx.net>
Message-ID: <48C09578.9090807@gmx.net>

On 05.09.2008 03:49, Carl-Daniel Hailfinger wrote:
> The current K8 stack preservation code in disable_car() works by chance,
> but that's not something we should rely on.
>
> The new code is entirely rewritten, fixes a few missing constraints in
> the asm and should be a lot more readable. However, the generated code
> should be mostly identical.
>   

I hate to say it, but the generated code is NOT identical. The old code
was broken because of the missing ecx clobber constraint and it did not
copy the stack back (ecx was zero at the beginning of the copy-back loop
and so the loop executed exactly zero times).
So this is a genuine bug fix. v2 may be affected as well.

> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From bari at onelabs.com  Fri Sep  5 04:20:33 2008
From: bari at onelabs.com (bari)
Date: Thu, 04 Sep 2008 21:20:33 -0500
Subject: [coreboot] [PATCH] Add VIA VT8237S support
In-Reply-To: <48C065B9.6020605@assembler.cz>
References: <48C065B9.6020605@assembler.cz>
Message-ID: <48C09771.9010000@onelabs.com>

Rudolf Marek wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Hello,
>
> Its here! SATA issue solved (thanks for hint VIA!). This patch adds support for
> the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested
> on mine desktop) except of reverting the small change introduced by Bari
> (gpio/inta setup reg 0x5b). This should go for some board specific file. The
> change would broke at least mine board. But seems to be needed for jakllsch.
>
> Please someone try to fix it.
>
> Ok now back to patch.
>
> VT8237S peripherals:
>
> SPI flash - works, flashing fine
> SATA - now works, maybe need adjustments for your PCB
> USB - OK works
> IDE - OK works
> Network - OK works even if the board has no own flash - new code has to be
> called, default MAC will be 00:00:DE:AD:BE:EF.
> Sound - untested may work
>
> ACPI - works
> APIC - works
>
> Please try to ack the patch quickly, because a lot of people needs to dig into
> those files :)
>
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
>
> Rudolf
>
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.6 (GNU/Linux)
> Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
>
> iD8DBQFIwGW53J9wPJqZRNURAoLyAJoCFu/QwvZhTjnINYl6QPe4oNcCngCgiej+
> PdLlpDgskjraKY/Y14LI1wU=
> =3s3C
> -----END PGP SIGNATURE-----
>   
> ------------------------------------------------------------------------
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
acked by: Bari Ari <bari at onelabs.com>



From corey.osgood at gmail.com  Fri Sep  5 04:23:04 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 4 Sep 2008 22:23:04 -0400
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C0512E.9050104@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu>
Message-ID: <dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>

On Thu, Sep 4, 2008 at 5:20 PM, Daniel Lindenaar
<daniel-coreboot at lindenaar.eu> wrote:
> hmmm it's working partly, it seems. First i did something wrong that skrewed
> up the com port setup, which I fixed. I now get the debug messages I added
> via the serial line, but, strangely, only when i do a (warm) reboot from a
> running linux, not with a cold boot... probably something needs to be set
> that doesn't get set by default on cold reboot.

Not good. Can you send me a copy of your tree or a patch, and a
complete boot log? I've seen the same issue, I just can't remember how
I fixed it at the moment. It's something to do with either the romcc
build parameters or failover code, I can't remember atm. Also, vt8601
is compatible with both c3 and p2/p3, right? Which are you using?

>
> Anyway, it's the SMBus controller where things go wrong; the log says:
>
> SMBUS controller not found

Check the datasheet, there's probably a bit somewhere in the LPC
controller that enables the smbus controller, you'll need to flip that
first, if you haven't already.

-Corey

>
> as the last item. At least some progress is made. Besides the logging not
> working on cold boot, which it should at some point, I've now got something
> that works well enough to start proper debugging.
>
> regards,
> Daniel
>>
>> --
>> coreboot mailing list
>> coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>>
>
>



From corey.osgood at gmail.com  Fri Sep  5 04:50:34 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 4 Sep 2008 22:50:34 -0400
Subject: [coreboot] Kernel hang solid
In-Reply-To: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
References: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
Message-ID: <dd3c80060809041950l60045aefs6528f43240563c65@mail.gmail.com>

On Thu, Sep 4, 2008 at 8:00 PM, Vincent Legoll <vincent.legoll at gmail.com> wrote:
> Could someone explain the differences in linux kernel boot
> logs for coreboot vs BIOS that are attached. The coreboot
> log is here too, just in case.
>
> The total absence of reserved memory ranges seems
> unnatural. The DMA zone range starting at 0x00000001
> looks fishy too.
>
> I'm completely lost, the hang happen at init/main.c in
> console_init()
>
> --
> Vincent Legoll

It looks like you're IRQ routing is broken, at least on the surface.
Is this a currently supported board, or a new port you're working on?

-Corey



From yinghailu at gmail.com  Fri Sep  5 05:03:51 2008
From: yinghailu at gmail.com (yhlu)
Date: Thu, 4 Sep 2008 20:03:51 -0700
Subject: [coreboot] Kernel hang solid
In-Reply-To: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
References: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
Message-ID: <2ea3fae10809042003i3c450fbewb70bca920f9711aa@mail.gmail.com>

On Thu, Sep 4, 2008 at 5:00 PM, Vincent Legoll <vincent.legoll at gmail.com>wrote:

> Could someone explain the differences in linux kernel boot
> logs for coreboot vs BIOS that are attached. The coreboot
> log is here too, just in case.
>
> The total absence of reserved memory ranges seems
> unnatural. The DMA zone range starting at 0x00000001
> looks fishy too.
>
> I'm completely lost, the hang happen at init/main.c in
> console_init()
>

does previous kernel work? like 2.6.24

YH
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From rminnich at gmail.com  Fri Sep  5 05:25:36 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 20:25:36 -0700
Subject: [coreboot] [PATCH] v3: correct K8 stack preservation asm
In-Reply-To: <48C09578.9090807@gmx.net>
References: <48C0900F.8050409@gmx.net> <48C09578.9090807@gmx.net>
Message-ID: <13426df10809042025v84060c5p3d250609c4d4b5ac@mail.gmail.com>

wow! nice catch!

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

We also need disable_car_and_halt, which only disables car and halts,
for the APs (i.e. no need to copy stack back)

hint, hint, hint :-)

ron



From corey.osgood at gmail.com  Fri Sep  5 05:27:50 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 4 Sep 2008 23:27:50 -0400
Subject: [coreboot] v2: Detection of sdram densities.
In-Reply-To: <E1Kaw7Y-0006ta-Br@aun.bellman.mea>
References: <E1Kaw7Y-0006ta-Br@aun.bellman.mea>
Message-ID: <dd3c80060809042027n78e01c12nc84dc0e644545991@mail.gmail.com>

On Wed, Sep 3, 2008 at 1:26 PM, Mats Erik Andersson
<mats.andersson at gisladisker.se> wrote:
>
> Hello again,
>
> I have been experimenting with an algorithm to detect
> and register with the northbridge i440bx the correct
> amount of sdram present. A C-coded version is appended
> to this message. Feel free to comment on the method.
>
> In the actually working code, I had to split the
> algorithm into a lower and an upper part, in order
> not to run out of internal registers under romcc,
> but the idea remains the same.
>
> Since there are also some later stages where I have
> not understood how the previous author hard coded
> a single 64MB bank,  I presently achieve a running
> system only when I dynamically detect a distribution
> identical to what was earlier hard coded.
>
> My detection works with any combination of 0MB and
> 64MB in two rows for DIMM0 and DIMM1.
>
> Question: In case an sdram device has rows of mixed
> sizes, can one depend on the larger density being
> in row zero, and the smaller content in row one?

Yes. The spd spec assumes the larger row will be row 0, any stick that
didn't wouldn't follow the standard. At least, that was my
understanding of it.

-Corey



From rminnich at gmail.com  Fri Sep  5 05:33:22 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 20:33:22 -0700
Subject: [coreboot] inline asm peculiarities in v3
In-Reply-To: <48C09054.4090109@gmx.net>
References: <48BFFFA1.9040003@gmx.net>
	<13426df10809040846g3435b158lf9aa4e48728bcd7d@mail.gmail.com>
	<48C09054.4090109@gmx.net>
Message-ID: <13426df10809042033r64616cd2x1b66ecd35c3143c4@mail.gmail.com>

On Thu, Sep 4, 2008 at 6:50 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 04.09.2008 17:46, ron minnich wrote:
>> On Thu, Sep 4, 2008 at 8:32 AM, Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>>
>>> Hi,
>>>
>>> I decided to look at all cases of inline asm in our v3 code and I found
>>> a few bits which either work by accident or need better documentation.
>>>
>>> We use __asm__ and asm, __volatile__ and volatile. Can we please decide
>>> which one we want, then I'll switch the tree over.
>>>
>>
>> somebody who knows better than me the implications can comment.
>>
>
> The gcc info page states that __asm__ and asm are equivalent, but if you
> use -ansi or -fno-asm or -fno-gnu-keywords in your CFLAGS only __asm__
> will be recognized. asm is shorter, so I'd prefer asm.
> __volatile__ vs. volatile is not explained in the gcc docs at all, but
> various places on the net state that they're identical.

you definitely want a volatile in there, else the various tools agree
to helpfully optimize the code. I've seen it completely eliminate
__asm__ that was not protect with a __volatile__. As to the use of __
vs no __, I'm not picky. We're probably locked into gcc so this
particular gcc-ism is not going to cause me to sleep badly :-)


>>> northbridge/amd/geodelx/vsmsetup.c:143
>>>
>>>> __asm__(".text\n" "real_mode_switch_end:\n");
>>>> extern char real_mode_switch_end[];
>>>>
>>> AFAICS the compiler and linker are free to place the resulting code
>>> anywhere in the binary independent of each other.
>>>
>>
>> Not a problem. The "extern" is simply making the label available to C.
>> They don't depend on any trickiness.
>>
>
> My point was about the label. Sorry for being unclear. That label can be
> placed anywhere, so I can't see it serving any purpose.

I don't remember why it is done the way it is. But we can test a
change easily, so no problem to try a change.

>
>
>>> include/arch/x86/amd/k8/k8.h:746
>>>
>>>> static void disable_cache_as_ram_bsp(void)
>>>> {
>>>>         __asm__ volatile (
>>>> //              "pushl %eax\n\t"
>>>>                 "pushl %edx\n\t"
>>>>                 "pushl %ecx\n\t"
>>>>         );
>>>>
>>>>         disable_cache_as_ram();
>>>>         __asm__ volatile (
>>>>                 "popl %ecx\n\t"
>>>>                 "popl %edx\n\t"
>>>> //                "popl %eax\n\t"
>>>>         );
>>>> }
>>>>
>>> The pushl and popl instructions seem to serve no real purpose. Kill them?
>>>
>>
>> My rule with the Clever v2 code is not to modify it until I understand
>> it. So I did not touch these because I don't know what function they
>> serve. That's one reason that I am bringing code over and leaving it
>> ugly to start. Let's leave this alone until K8 is working.
>>
>
> But can I add a comment that the current code seems nonsensical?

absolutely. See all the #warnings you get when you build k8 :-)

ron



From corey.osgood at gmail.com  Fri Sep  5 05:34:22 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 4 Sep 2008 23:34:22 -0400
Subject: [coreboot] CAR for C7
In-Reply-To: <48B60D2D.8080703@gmx.net>
References: <48B5D04C.8000608@onelabs.com> <48B5D230.9090702@gmx.net>
	<48B5D4E0.9000307@onelabs.com> <48B60D2D.8080703@gmx.net>
Message-ID: <dd3c80060809042034g5e1d24eetfbae3f04885d692c@mail.gmail.com>

On Wed, Aug 27, 2008 at 10:27 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 28.08.2008 00:27, bari wrote:
>> Carl-Daniel Hailfinger wrote:
>>> I can attack C7 CAR on v3 now. Will report on my status later tonight.
>> Great! Corey had a vt8237 patch for V3 that was untested. Now we just
>> need to move cn700 to V3. Any takers?
>>
>> There are about 40 different VIA Epia's, Jetways and MSI boards in
>> production that will be pretty easily ready to go with this soon.
>
> Sorry, I had to call this off to get the v3 tree in shape again. Will
> try tomorrow to post my WIP.
>
> Regards,
> Carl-Daniel

*bump* :p

Have you gotten to this? If not, I'll try and attack it this weekend,
I'd really rather post a working vt8237r patch along with a cn700 one.
And can anyone confirm that CAR on the C7 is actually working in v2?

Thanks,
Corey



From rminnich at gmail.com  Fri Sep  5 05:34:52 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 20:34:52 -0700
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu>
	<dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>
Message-ID: <13426df10809042034g3ba822a2hc8ec1dc4d671783f@mail.gmail.com>

On Thu, Sep 4, 2008 at 7:23 PM, Corey Osgood <corey.osgood at gmail.com> wrote:

> Check the datasheet, there's probably a bit somewhere in the LPC
> controller that enables the smbus controller, you'll need to flip that
> first, if you haven't already.

and in case you're wondering why this is done, it is common to have
duplicate functions on chipsets on the board, so some PCI functions
are disabled (not even visible in config space!) unless you enable
them.

ron



From bari at onelabs.com  Fri Sep  5 05:44:38 2008
From: bari at onelabs.com (bari)
Date: Thu, 04 Sep 2008 22:44:38 -0500
Subject: [coreboot] CAR for C7
In-Reply-To: <dd3c80060809042034g5e1d24eetfbae3f04885d692c@mail.gmail.com>
References: <48B5D04C.8000608@onelabs.com> <48B5D230.9090702@gmx.net>	
	<48B5D4E0.9000307@onelabs.com> <48B60D2D.8080703@gmx.net>
	<dd3c80060809042034g5e1d24eetfbae3f04885d692c@mail.gmail.com>
Message-ID: <48C0AB26.70003@onelabs.com>

Corey Osgood wrote:
> Have you gotten to this? If not, I'll try and attack it this weekend,
> I'd really rather post a working vt8237r patch along with a cn700 one.
>   
Are the latest cn700 and vt8237r patches not working for you? What's wrong?
> And can anyone confirm that CAR on the C7 is actually working in v2?
>   
Yes, it works.

-Bari



From rminnich at gmail.com  Fri Sep  5 05:49:31 2008
From: rminnich at gmail.com (ron minnich)
Date: Thu, 4 Sep 2008 20:49:31 -0700
Subject: [coreboot] CAR for C7
In-Reply-To: <48C0AB26.70003@onelabs.com>
References: <48B5D04C.8000608@onelabs.com> <48B5D230.9090702@gmx.net>
	<48B5D4E0.9000307@onelabs.com> <48B60D2D.8080703@gmx.net>
	<dd3c80060809042034g5e1d24eetfbae3f04885d692c@mail.gmail.com>
	<48C0AB26.70003@onelabs.com>
Message-ID: <13426df10809042049h97cc4b6n56866f47bbce89c4@mail.gmail.com>

On Thu, Sep 4, 2008 at 8:44 PM, bari <bari at onelabs.com> wrote:
> Corey Osgood wrote:
>>
>> Have you gotten to this? If not, I'll try and attack it this weekend,
>> I'd really rather post a working vt8237r patch along with a cn700 one.
>>
>
> Are the latest cn700 and vt8237r patches not working for you? What's wrong?
>>
>> And can anyone confirm that CAR on the C7 is actually working in v2?
>>
>
> Yes, it works.
>
> -Bari
>

Sorry to be so clueless, but can I buy a CN700 board TODAY that will
work with the v2 CAR code? I have some money to spend ...

Are there jtag debuggers I can use with CN700 and nano?

ron



From bari at onelabs.com  Fri Sep  5 06:44:58 2008
From: bari at onelabs.com (bari)
Date: Thu, 04 Sep 2008 23:44:58 -0500
Subject: [coreboot] CAR for C7
In-Reply-To: <13426df10809042049h97cc4b6n56866f47bbce89c4@mail.gmail.com>
References: <48B5D04C.8000608@onelabs.com> <48B5D230.9090702@gmx.net>	
	<48B5D4E0.9000307@onelabs.com> <48B60D2D.8080703@gmx.net>	
	<dd3c80060809042034g5e1d24eetfbae3f04885d692c@mail.gmail.com>	
	<48C0AB26.70003@onelabs.com>
	<13426df10809042049h97cc4b6n56866f47bbce89c4@mail.gmail.com>
Message-ID: <48C0B94A.6080002@onelabs.com>

ron minnich wrote:
> Sorry to be so clueless, but can I buy a CN700 board TODAY that will
> work with the v2 CAR code? I have some money to spend ...
>
>   
Sure!

Idotpc is just across the bay from you in Hayward, Ca. near the VIA office.

http://www.idotpc.com/thestore/pc/viewCategories.asp?idCategory=89
VIA VB7001G  is only $99 right now.

Epia-CN, LN, EN will all work.

Logic Supply is another:
http://www.logicsupply.com/categories/mainboards/via_c7

The pc2500 is also up and running:

http://store1.alrightdeals.com/CommonItem.htm?Product=S1_Motherboards_Socket.370___58913

http://www.imagine-digital.com/58913.html

Walmart has the whole case+ power supply and all for only  $130.00

http://www.walmart.com/catalog/product.do?product_id=7754614

> Are there jtag debuggers I can use with CN700 and nano?
>   
Not sure besides the VIA development boards if any others have the JTAG 
connectors.

-Bari



From bari at onelabs.com  Fri Sep  5 06:58:31 2008
From: bari at onelabs.com (bari)
Date: Thu, 04 Sep 2008 23:58:31 -0500
Subject: [coreboot] CAR for C7
In-Reply-To: <13426df10809042049h97cc4b6n56866f47bbce89c4@mail.gmail.com>
References: <48B5D04C.8000608@onelabs.com> <48B5D230.9090702@gmx.net>	
	<48B5D4E0.9000307@onelabs.com> <48B60D2D.8080703@gmx.net>	
	<dd3c80060809042034g5e1d24eetfbae3f04885d692c@mail.gmail.com>	
	<48C0AB26.70003@onelabs.com>
	<13426df10809042049h97cc4b6n56866f47bbce89c4@mail.gmail.com>
Message-ID: <48C0BC77.8090005@onelabs.com>

ron minnich wrote:
> Are there jtag debuggers I can use with CN700 and nano?
>   
The Nano isn't being paired with the cn700. Only VX800 and 896 from what 
I have seen so far.

VIA has vx800+c7 working with coreboot and acpi. It may be released to 
us soon.

Rudolf just got SATA-II working with the vt8237s so this also may fix 
the cx700 that Stefan has had the same issues with.

This gives us almost every chipset from VIA that supports C7 and Nano 
working with coreboot. Well over 50 mainboards that may easily work with 
coreboot. VIA is our most well supported x86 cpu and chipset vendor now.

-Bari



From stepan at coresystems.de  Fri Sep  5 08:30:35 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Sep 2008 08:30:35 +0200
Subject: [coreboot] inline asm peculiarities in v3
In-Reply-To: <48C09054.4090109@gmx.net>
References: <48BFFFA1.9040003@gmx.net>	<13426df10809040846g3435b158lf9aa4e48728bcd7d@mail.gmail.com>
	<48C09054.4090109@gmx.net>
Message-ID: <48C0D20B.2060407@coresystems.de>

Carl-Daniel Hailfinger wrote:
>> My rule with the Clever v2 code is not to modify it until I understand
>> it. So I did not touch these because I don't know what function they
>> serve. That's one reason that I am bringing code over and leaving it
>> ugly to start. Let's leave this alone until K8 is working.
>>   
>>     
>
> But can I add a comment that the current code seems nonsensical?
>
>
>   
But it seems not because we know what gcc is doing and its doing the
right thing.





-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From corey.osgood at gmail.com  Fri Sep  5 09:00:38 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 5 Sep 2008 03:00:38 -0400
Subject: [coreboot] CAR for C7
In-Reply-To: <48C0AB26.70003@onelabs.com>
References: <48B5D04C.8000608@onelabs.com> <48B5D230.9090702@gmx.net>
	<48B5D4E0.9000307@onelabs.com> <48B60D2D.8080703@gmx.net>
	<dd3c80060809042034g5e1d24eetfbae3f04885d692c@mail.gmail.com>
	<48C0AB26.70003@onelabs.com>
Message-ID: <dd3c80060809050000k602d4626x362b024768681785@mail.gmail.com>

On Thu, Sep 4, 2008 at 11:44 PM, bari <bari at onelabs.com> wrote:
> Corey Osgood wrote:
>>
>> Have you gotten to this? If not, I'll try and attack it this weekend,
>> I'd really rather post a working vt8237r patch along with a cn700 one.
>>
>

I meant for v3. I'm planning on integrating some of the vt8237s port
into a vt8237r for the v3 port (thanks Rudolf!), and would like to
know if it works before I go posting it ;) cn700 in v3 should be a
snap with CAR up and running.

Thanks,
Corey

> Are the latest cn700 and vt8237r patches not working for you? What's wrong?
>>
>> And can anyone confirm that CAR on the C7 is actually working in v2?
>>
>
> Yes, it works.
>
> -Bari
>



From corey.osgood at gmail.com  Fri Sep  5 09:02:44 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 5 Sep 2008 03:02:44 -0400
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <13426df10809042034g3ba822a2hc8ec1dc4d671783f@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu>
	<dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>
	<13426df10809042034g3ba822a2hc8ec1dc4d671783f@mail.gmail.com>
Message-ID: <dd3c80060809050002t13243507wa8353299faac1dc9@mail.gmail.com>

On Thu, Sep 4, 2008 at 11:34 PM, ron minnich <rminnich at gmail.com> wrote:
> On Thu, Sep 4, 2008 at 7:23 PM, Corey Osgood <corey.osgood at gmail.com> wrote:
>
>> Check the datasheet, there's probably a bit somewhere in the LPC
>> controller that enables the smbus controller, you'll need to flip that
>> first, if you haven't already.
>
> and in case you're wondering why this is done, it is common to have
> duplicate functions on chipsets on the board, so some PCI functions
> are disabled (not even visible in config space!) unless you enable
> them.
>
> ron
>

Or in case there are multiple southbridges/SMBus controllers, and only
one SMBus controller/USB controller/NIC is actually connected to
anything.

-Corey



From jackiepan93 at gmail.com  Fri Sep  5 09:45:17 2008
From: jackiepan93 at gmail.com (Jackie Pan)
Date: Fri, 5 Sep 2008 15:45:17 +0800
Subject: [coreboot] Cache as RAM - is it possible to execute code in cache?
Message-ID: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>

Hi all,
I'm wondering if it's possible to place code into cache-emulated RAM, I
tested on an intel T2300,
after CAR setup, I can read/write to the mapped region, however code
execution seems not working.
Postcode reveals that the CPU seems to be spinning on the very first
instruction in the 'RAM' region.

Anyone could give some hints? thanks.
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From rminnich at gmail.com  Fri Sep  5 09:46:49 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 00:46:49 -0700
Subject: [coreboot] Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
Message-ID: <13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>

On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan <jackiepan93 at gmail.com> wrote:
> Hi all,
> I'm wondering if it's possible to place code into cache-emulated RAM, I
> tested on an intel T2300,
> after CAR setup, I can read/write to the mapped region, however code
> execution seems not working.
> Postcode reveals that the CPU seems to be spinning on the very first
> instruction in the 'RAM' region.
> Anyone could give some hints? thanks.

It is possible and it works. What you might do is dump the contents of
the CAR once you have copied to it and see what is there.

ron



From rminnich at gmail.com  Fri Sep  5 10:17:35 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 01:17:35 -0700
Subject: [coreboot] [PATCH] v3: more uniqueness in the dtc generated
	struct names
In-Reply-To: <48BF5150.9050804@gmx.net>
References: <48B87ED7.1030104@gmx.net> <48BF5150.9050804@gmx.net>
Message-ID: <13426df10809050117u31cb592dhde546712f9d22926@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

not yet tested. But some test builds look good.

ron

On Wed, Sep 3, 2008 at 8:09 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi Ron,
>
> here's my patch proposal for struct device naming again. It has the
> advantage of adding only 14 lines of code.
>
> Regards,
> Carl-Daniel
>
> On 30.08.2008 00:57, Carl-Daniel Hailfinger wrote:
>> I managed to break dtc while working on PCI bridges:
>> dtc only uses dev_fn as identifier for a PCI device. That gets us a name
>> collision if we have the same dev_fn combination on multiple buses.
>> Either we add a random unique ID to the struct name or we integrate the
>> number of the parent device as well.
>> A third option would be to store the complete hierarchy in the name.
>> I decided to go for integration of parent device name.
>>
>> With the following device tree
>>
>> /{
>>       cpus {};
>>       domain at 0 {
>>               bus at 0 {
>>                       pci at 0,0 {
>>                       };
>>                       pci at 1,1 {
>>                       };
>>                       pci at f,0 {
>>                               bus at 1 {
>>                                       pci at 0,0 {
>>                                       };
>>                               };
>>                       };
>>               };
>>       };
>> };
>>
>>
>> we get the old names:
>> dev_root
>> dev_cpus
>> dev_domain_0
>> dev_bus_0
>> dev_pci_0_0
>> dev_pci_1_1
>> dev_pci_f_0
>> dev_bus_1
>> dev_pci_0_0 COLLISION!!!
>>
>>
>> and the new names:
>> dev_root
>> dev_cpus
>> dev_domain_0
>> dev_domain_0_bus_0
>> dev_bus_0_pci_0_0
>> dev_bus_0_pci_1_1
>> dev_bus_0_pci_f_0
>> dev_pci_f_0_bus_1
>> dev_bus_1_pci_0_0
>>
>> and the third option (not used) would have looked like this:
>> dev_root
>> dev_cpus
>> dev_domain_0
>> dev_domain_0_bus_0
>> dev_domain_0_bus_0_pci_0_0
>> dev_domain_0_bus_0_pci_1_1
>> dev_domain_0_bus_0_pci_f_0
>> dev_domain_0_bus_0_pci_f_0_bus_1
>> dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0
>>
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>
>>
>> Index: corebootv3-pci_scan_bus/util/dtc/flattree.c
>> ===================================================================
>> --- corebootv3-pci_scan_bus/util/dtc/flattree.c       (Revision 846)
>> +++ corebootv3-pci_scan_bus/util/dtc/flattree.c       (Arbeitskopie)
>> @@ -931,6 +931,7 @@
>>               emit->endnode(etarget, treelabel);
>>       }
>>
>> +     //fprintf(f, "//tree->label is %s, tree->parent->label is %s\n", tree->label, tree->parent ? tree->parent->label : NULL);
>>       /* now emit the device for this node, with sibling and child pointers etc. */
>>       emit->special(f, tree);
>>
>> @@ -1313,8 +1314,23 @@
>>  labeltree(struct node *tree)
>>  {
>>       struct node *child;
>> +     char *tmp1;
>> +     char *tmp2;
>>
>> +     //printf("//tree->label is %s, tree->parent->label is %s\n", tree->label, tree->parent ? tree->parent->label : NULL);
>>       tree->label = clean(tree->name, 1);
>> +     if (tree->parent && tree->label) {
>> +             tmp1 = clean(tree->parent->name, 1);
>> +             if (strlen(tmp1)) {
>> +                     tmp2 = tree->label;
>> +                     tree->label = malloc(strlen(tmp1) + strlen(tmp2) + 2);
>> +                     strcpy(tree->label, tmp1);
>> +                     strcat(tree->label, "_");
>> +                     strcat(tree->label, tmp2);
>> +                     free(tmp2);
>> +             }
>> +             free(tmp1);
>> +     }
>>
>>       if (tree->next_sibling)
>>               labeltree(tree->next_sibling);
>>
>>
>>
>
>
> --
> http://www.hailfinger.org/
>
>



From yinghailu at gmail.com  Fri Sep  5 10:30:32 2008
From: yinghailu at gmail.com (yhlu)
Date: Fri, 5 Sep 2008 01:30:32 -0700
Subject: [coreboot] Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
Message-ID: <2ea3fae10809050130j3a72252ocbc1e13497885161@mail.gmail.com>

On Fri, Sep 5, 2008 at 12:46 AM, ron minnich <rminnich at gmail.com> wrote:

> On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan <jackiepan93 at gmail.com> wrote:
> > Hi all,
> > I'm wondering if it's possible to place code into cache-emulated RAM, I
> > tested on an intel T2300,
> > after CAR setup, I can read/write to the mapped region, however code
> > execution seems not working.
> > Postcode reveals that the CPU seems to be spinning on the very first
> > instruction in the 'RAM' region.
> > Anyone could give some hints? thanks.
>
> It is possible and it works. What you might do is dump the contents of
> the CAR once you have copied to it and see what is there.
>
> in v2, there is one option for Opteron rev F, after enable it, DDR2 mem
training code is copied to core0  cache of other nodes,
it will train the mem when core0 of node0 is doing hardware_main(),,,,

YH
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From jackiepan93 at gmail.com  Fri Sep  5 11:24:21 2008
From: jackiepan93 at gmail.com (Jackie Pan)
Date: Fri, 5 Sep 2008 17:24:21 +0800
Subject: [coreboot] Fwd: Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <3c66930d0809050216pdbcc78cy701af3ae458242d0@mail.gmail.com>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
	<3c66930d0809050216pdbcc78cy701af3ae458242d0@mail.gmail.com>
Message-ID: <3c66930d0809050224x76aa39e4t496e881ee57159ba@mail.gmail.com>

2008/9/5 ron minnich <rminnich at gmail.com>

On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan <jackiepan93 at gmail.com> wrote:
> > Hi all,
> > I'm wondering if it's possible to place code into cache-emulated RAM, I
> > tested on an intel T2300,
> > after CAR setup, I can read/write to the mapped region, however code
> > execution seems not working.
> > Postcode reveals that the CPU seems to be spinning on the very first
> > instruction in the 'RAM' region.
> > Anyone could give some hints? thanks.
>
> It is possible and it works. What you might do is dump the contents of
> the CAR once you have copied to it and see what is there.
>
> ron

I just got an XDP emulator, now the emulator tells me that the code has been
correctlycopied to the CAR region, which is 0xc0000, I can see the code
through both disassembly
window and the data window, but when I try to step on the first
instruction, source-point
pops up a window saying 'memory access failed', then the emulator
connection is lost.

btw, the simulator is an ARIUM ECM-XDP3, I've followed the advice in its
manual to set
0xc0000 to be a SRAM region.

so, is the XDP lying to me? or I missed some points?

@Stefan: I'm trying to port v2 to several grantsdale/calistoga boards that
we manufactured.
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From vincent.legoll at gmail.com  Fri Sep  5 11:37:22 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Fri, 5 Sep 2008 11:37:22 +0200
Subject: [coreboot] Kernel hang solid
In-Reply-To: <dd3c80060809041950l60045aefs6528f43240563c65@mail.gmail.com>
References: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
	<dd3c80060809041950l60045aefs6528f43240563c65@mail.gmail.com>
Message-ID: <4727185d0809050237m645d40cak6b8516313c67ed04@mail.gmail.com>

On Fri, Sep 5, 2008 at 4:50 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
> It looks like you're IRQ routing is broken, at least on the surface.
> Is this a currently supported board, or a new port you're working on?

New port, IRQ routing just has landed. So it may still be broken.

But, kernel "apic=debug" output is now the same for coreboot-based
or BIOS-based boots.

Where could I have more infos on other IRQs not listed there (for
example the IRQs 3 & 4 that are being used for serial port when
booted with legacy bios). Kernel is silent about them at that stage
of the boot process.

-- 
Vincent Legoll



From vincent.legoll at gmail.com  Fri Sep  5 11:38:46 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Fri, 5 Sep 2008 11:38:46 +0200
Subject: [coreboot] Kernel hang solid
In-Reply-To: <2ea3fae10809042003i3c450fbewb70bca920f9711aa@mail.gmail.com>
References: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
	<2ea3fae10809042003i3c450fbewb70bca920f9711aa@mail.gmail.com>
Message-ID: <4727185d0809050238g8aa8694u1f88b86fffc27885@mail.gmail.com>

On Fri, Sep 5, 2008 at 5:03 AM, yhlu <yinghailu at gmail.com> wrote:
> does previous kernel work? like 2.6.24

I've not tried a kernel that old, but I will.

I've tried vanilla -git for last few days only.

-- 
Vincent Legoll



From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 11:44:20 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 11:44:20 +0200
Subject: [coreboot] Cache as RAM - is it possible to execute code
	in	cache?
In-Reply-To: <13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
Message-ID: <48C0FF74.6070608@gmx.net>

On 05.09.2008 09:46, ron minnich wrote:
> On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan <jackiepan93 at gmail.com> wrote:
>   
>> I'm wondering if it's possible to place code into cache-emulated RAM, I
>> tested on an intel T2300,
>> after CAR setup, I can read/write to the mapped region, however code
>> execution seems not working.
>> Postcode reveals that the CPU seems to be spinning on the very first
>> instruction in the 'RAM' region.
>> Anyone could give some hints? thanks.
>>     
>
> It is possible and it works. What you might do is dump the contents of
> the CAR once you have copied to it and see what is there.
>   

Yes and no. At least the new AMD Family 10h processors can't use CAR for
data storage and code storage at the same time. In theory, you could
fill the CAR area in data storage mode, then switch over to code
storage. Not tested, though, and NOT mentioned as viable in the BKDG
(BIOS and Kernel Developer's Guide).

Intel CPUs might have similar restrictions.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From daniel-coreboot at lindenaar.eu  Fri Sep  5 12:13:59 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar )
Date: Fri, 05 Sep 2008 12:13:59 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C0560C.9040500@coresystems.de>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu> <48C0560C.9040500@coresystems.de>
Message-ID: <20080905121359.154557oo2wfn0jnk@www.lindenaar.eu>

Quoting "Stefan Reinauer" <stepan at coresystems.de>:

> Daniel Lindenaar wrote:
>> hmmm it's working partly, it seems. First i did something wrong that
>> skrewed up the com port setup, which I fixed. I now get the debug
>> messages I added via the serial line, but, strangely, only when i do a
>> (warm) reboot from a running linux, not with a cold boot...
> This sounds an awful lot like superio init, or some GPIO issue.
>
> Are you initializing your superio correctly? Does your board use the
> 82c686 superio? Or does it have an extra superio?
> (Check with superiotool)
>
>> probably something needs to be set that doesn't get set by default on
>> cold reboot.
>>
>> Anyway, it's the SMBus controller where things go wrong; the log says:
>>
>> SMBUS controller not found
> What device are you looking for at that point?
>
> On the vt82c686 the smbus device has vendor 0x1106 and device 0x3057
>
hmm i'll have to look into the code (at work, now). In linux the  
device is shown as vt82xxx ACPI and power something.. and that device  
includes the SMBus controller at some IO offset. I'm pretty sure I'm  
using the right PCI device, bus maybe the IO offset is wrong.

It's using the 82c686 superio and superiotool doesn't find any other,  
so I'm pretty sure it's the integrated one. I'll need to check the  
SMBus code path's and/or initialisation code and see if there's  
something wrong.

regards,
Daniel
>
>
>
> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
>
>
>



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This message was sent using IMP, the Internet Messaging Program.



From daniel-coreboot at lindenaar.eu  Fri Sep  5 12:15:40 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar )
Date: Fri, 05 Sep 2008 12:15:40 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <13426df10809041427h296c0ba7x547721487081509c@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu>
	<13426df10809041426l1e91193cx38f56a9f7142c6a@mail.gmail.com>
	<13426df10809041427h296c0ba7x547721487081509c@mail.gmail.com>
Message-ID: <20080905121540.25943luo0q8kl9ds@www.lindenaar.eu>

Quoting "ron minnich" <rminnich at gmail.com>:

> On Thu, Sep 4, 2008 at 2:26 PM, ron minnich <rminnich at gmail.com> wrote:
>> in other words, you boot the factory bios, boot linux, swap flash
>> part, reboot, and there's no smbus controller? This is probably an I2C
>> mux then.
>>
>
> now why'd I say that? This is *possibly* an i2c mux but more likely
> the smbus device has some weird enable bit. What's the pci discovery
> stuff in coreboot show?

Hmm, I don't get any logging from pci discovery stuff; anything  
special needed for that?

regards Daniel
>
> ron
>
>



----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.




From svn at coreboot.org  Fri Sep  5 12:29:33 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Sep 2008 12:29:33 +0200
Subject: [coreboot] r858 - coreboot-v3/arch/x86/amd/k8
Message-ID: <mailman.2030.1355071375.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-09-05 12:29:33 +0200 (Fri, 05 Sep 2008)
New Revision: 858

Modified:
   coreboot-v3/arch/x86/amd/k8/stage1.c
Log:
The current K8 stack preservation code in disable_car() works by chance,
but that's not something we should rely on.

The new code is entirely rewritten, fixes a few missing constraints in
the asm and should be a lot more readable. However, the generated code
is NOT identical. The old code was broken because of the missing ecx
clobber constraint and it did not copy the stack back (ecx was zero at
the beginning of the copy-back loop and so the loop executed exactly
zero times).
So this is a genuine bug fix.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Ron writes:
wow! nice catch!

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

We also need disable_car_and_halt, which only disables car and halts,
for the APs (i.e. no need to copy stack back)


Modified: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c	2008-09-04 15:35:49 UTC (rev 857)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-09-05 10:29:33 UTC (rev 858)
@@ -34,20 +34,31 @@
  */
 void disable_car(void)
 {
-	/* OK, here is the theory: we should be able to copy 
-	 * the data back over itself, and the wbinvd should then 
-	 * flush to memory. Let's see. 
-	 */
-	/* nope. 
-	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
-	 */
 	/* call the inlined function */
 	disable_cache_as_ram();
 
-	/* copy it down, wbinvd, copy it back? */
-	__asm__ __volatile__("cld; rep movsl" ::"D" (0x88000), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory");
-	__asm__ __volatile__ ("wbinvd\n");
-	__asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (0x88000), "c" (CONFIG_CARSIZE/4): "memory");
+	/* The BKDG says that a WBINVD will not flush CAR to RAM (because the
+	 * cache tags are not dirty).
+	 * Solution:
+	 * - Two subsequent memcpy in the same inline asm block, one from stack
+	 *   to backup, one from backup to stack.
+	 * The solution for geode of using a inline asm memcpy of the stack
+	 * onto itself will not mark the cache tags as dirty on K8.
+	 */
+	__asm__ __volatile__(
+	"	movl %[carbase], %%esi		\n"
+	"	movl %[backuplocation], %%edi	\n"
+	"	movl %[carsizequads], %%ecx	\n"
+	"	cld				\n"
+	"	rep movsl			\n"
+	"	wbinvd				\n"
+	"	movl %[backuplocation], %%esi	\n"
+	"	movl %[carbase], %%edi		\n"
+	"	movl %[carsizequads], %%ecx	\n"
+	"	rep movsl			\n"
+	:: [carbase] "i" (CONFIG_CARBASE), [backuplocation] "i" (0x88000),
+	   [carsizequads] "i" (CONFIG_CARSIZE/4)
+	: "memory", "%edi", "%esi", "%ecx");
 	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
 	banner(BIOS_DEBUG, "disable_car: done");
 }




From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 12:30:13 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 12:30:13 +0200
Subject: [coreboot] [PATCH] v3: correct K8 stack preservation asm
In-Reply-To: <13426df10809042025v84060c5p3d250609c4d4b5ac@mail.gmail.com>
References: <48C0900F.8050409@gmx.net> <48C09578.9090807@gmx.net>
	<13426df10809042025v84060c5p3d250609c4d4b5ac@mail.gmail.com>
Message-ID: <48C10A35.5090303@gmx.net>

On 05.09.2008 05:25, ron minnich wrote:
> wow! nice catch!
>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>   

Thanks, r858.

> We also need disable_car_and_halt, which only disables car and halts,
> for the APs (i.e. no need to copy stack back)
>
> hint, hint, hint :-)
>   

Yes, I'll look into that.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Fri Sep  5 12:54:17 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 5 Sep 2008 12:54:17 +0200
Subject: [coreboot] Cache as RAM - is it possible to execute code
	in	cache?
In-Reply-To: <48C0FF74.6070608@gmx.net>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
	<48C0FF74.6070608@gmx.net>
Message-ID: <8012472D-CBBA-451C-A009-D7931A33D458@coresystems.de>



Core 2 Duo can do cache for ram and code... But it works well enough  
to just set an mtrr to make rom cacheable during car and that also  
works for older intel CPUs

On 05.09.2008, at 11:44, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net 
 > wrote:

> On 05.09.2008 09:46, ron minnich wrote:
>> On Fri, Sep 5, 2008 at 12:45 AM, Jackie Pan <jackiepan93 at gmail.com>  
>> wrote:
>>
>>> I'm wondering if it's possible to place code into cache-emulated  
>>> RAM, I
>>> tested on an intel T2300,
>>> after CAR setup, I can read/write to the mapped region, however code
>>> execution seems not working.
>>> Postcode reveals that the CPU seems to be spinning on the very first
>>> instruction in the 'RAM' region.
>>> Anyone could give some hints? thanks.
>>>
>>
>> It is possible and it works. What you might do is dump the contents  
>> of
>> the CAR once you have copied to it and see what is there.
>>
>
> Yes and no. At least the new AMD Family 10h processors can't use CAR  
> for
> data storage and code storage at the same time. In theory, you could
> fill the CAR area in data storage mode, then switch over to code
> storage. Not tested, though, and NOT mentioned as viable in the BKDG
> (BIOS and Kernel Developer's Guide).
>
> Intel CPUs might have similar restrictions.
>
> Regards,
> Carl-Daniel
>
> -- 
> http://www.hailfinger.org/
>
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From stepan at coresystems.de  Fri Sep  5 13:11:37 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Sep 2008 13:11:37 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <20080905121359.154557oo2wfn0jnk@www.lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>	<48C0512E.9050104@lindenaar.eu>
	<48C0560C.9040500@coresystems.de>
	<20080905121359.154557oo2wfn0jnk@www.lindenaar.eu>
Message-ID: <48C113E9.8060302@coresystems.de>

Daniel Lindenaar wrote:
> Quoting "Stefan Reinauer" <stepan at coresystems.de>:
>
>> Daniel Lindenaar wrote:
>>> hmmm it's working partly, it seems. First i did something wrong that
>>> skrewed up the com port setup, which I fixed. I now get the debug
>>> messages I added via the serial line, but, strangely, only when i do a
>>> (warm) reboot from a running linux, not with a cold boot...
>> This sounds an awful lot like superio init, or some GPIO issue.
>>
>> Are you initializing your superio correctly? Does your board use the
>> 82c686 superio? Or does it have an extra superio?
>> (Check with superiotool)
>>
>>> probably something needs to be set that doesn't get set by default on
>>> cold reboot.
>>>
>>> Anyway, it's the SMBus controller where things go wrong; the log says:
>>>
>>> SMBUS controller not found
>> What device are you looking for at that point?
>>
>> On the vt82c686 the smbus device has vendor 0x1106 and device 0x3057
>>
> hmm i'll have to look into the code (at work, now). In linux the
> device is shown as vt82xxx ACPI and power something.. and that device
> includes the SMBus controller at some IO offset. I'm pretty sure I'm
> using the right PCI device, bus maybe the IO offset is wrong.
The message "SMBUS controller not found" implies that the PCI device is
not there. It doesn't even start looking for the offset at that point.




-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From joe at settoplinux.org  Fri Sep  5 14:09:03 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 05 Sep 2008 08:09:03 -0400
Subject: [coreboot] v2: Detection of sdram densities.
In-Reply-To: <dd3c80060809042027n78e01c12nc84dc0e644545991@mail.gmail.com>
References: <E1Kaw7Y-0006ta-Br@aun.bellman.mea>
	<dd3c80060809042027n78e01c12nc84dc0e644545991@mail.gmail.com>
Message-ID: <5b6d38ae9075ca1f76f7cc9266e44e14@imap.1and1.com>




On Thu, 4 Sep 2008 23:27:50 -0400, "Corey Osgood" <corey.osgood at gmail.com>
wrote:
> On Wed, Sep 3, 2008 at 1:26 PM, Mats Erik Andersson
> <mats.andersson at gisladisker.se> wrote:
>>
>> Hello again,
>>
>> I have been experimenting with an algorithm to detect
>> and register with the northbridge i440bx the correct
>> amount of sdram present. A C-coded version is appended
>> to this message. Feel free to comment on the method.
>>
>> In the actually working code, I had to split the
>> algorithm into a lower and an upper part, in order
>> not to run out of internal registers under romcc,
>> but the idea remains the same.
>>
>> Since there are also some later stages where I have
>> not understood how the previous author hard coded
>> a single 64MB bank,  I presently achieve a running
>> system only when I dynamically detect a distribution
>> identical to what was earlier hard coded.
>>
>> My detection works with any combination of 0MB and
>> 64MB in two rows for DIMM0 and DIMM1.
>>
>> Question: In case an sdram device has rows of mixed
>> sizes, can one depend on the larger density being
>> in row zero, and the smaller content in row one?
> 
> Yes. The spd spec assumes the larger row will be row 0, any stick that
> didn't wouldn't follow the standard. At least, that was my
> understanding of it.
> 
This can get a little confusing, when you are talking about rows, do you
mean banks? Or actuall sdram slots?
As far as it goes with rows/banks, most intel boards only support
asymmetrical sdrams so if the dimm has two sides the second side has to
equal the first side. As far as sdram slots any combination should work as
long as it follows the the northbridge criteria. You can look at the i830
raminit.c, it has a pretty clever way to detect dimms, and it works every
time no matter what the combination. By the way Uwe was the original author
of the i440bx code. Hope that helps.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From corey.osgood at gmail.com  Fri Sep  5 16:39:02 2008
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 5 Sep 2008 10:39:02 -0400
Subject: [coreboot] v2: Detection of sdram densities.
In-Reply-To: <5b6d38ae9075ca1f76f7cc9266e44e14@imap.1and1.com>
References: <E1Kaw7Y-0006ta-Br@aun.bellman.mea>
	<dd3c80060809042027n78e01c12nc84dc0e644545991@mail.gmail.com>
	<5b6d38ae9075ca1f76f7cc9266e44e14@imap.1and1.com>
Message-ID: <dd3c80060809050739w40abc184v2824817b8372b12a@mail.gmail.com>

On Fri, Sep 5, 2008 at 8:09 AM, Joseph Smith <joe at settoplinux.org> wrote:
>
>
>
> On Thu, 4 Sep 2008 23:27:50 -0400, "Corey Osgood" <corey.osgood at gmail.com>
> wrote:
>> On Wed, Sep 3, 2008 at 1:26 PM, Mats Erik Andersson
>> <mats.andersson at gisladisker.se> wrote:
>>>
>>> Hello again,
>>>
>>> I have been experimenting with an algorithm to detect
>>> and register with the northbridge i440bx the correct
>>> amount of sdram present. A C-coded version is appended
>>> to this message. Feel free to comment on the method.
>>>
>>> In the actually working code, I had to split the
>>> algorithm into a lower and an upper part, in order
>>> not to run out of internal registers under romcc,
>>> but the idea remains the same.
>>>
>>> Since there are also some later stages where I have
>>> not understood how the previous author hard coded
>>> a single 64MB bank,  I presently achieve a running
>>> system only when I dynamically detect a distribution
>>> identical to what was earlier hard coded.
>>>
>>> My detection works with any combination of 0MB and
>>> 64MB in two rows for DIMM0 and DIMM1.
>>>
>>> Question: In case an sdram device has rows of mixed
>>> sizes, can one depend on the larger density being
>>> in row zero, and the smaller content in row one?
>>
>> Yes. The spd spec assumes the larger row will be row 0, any stick that
>> didn't wouldn't follow the standard. At least, that was my
>> understanding of it.
>>
> This can get a little confusing, when you are talking about rows, do you
> mean banks? Or actuall sdram slots?

Banks, I assume, all this terminology gets me confuseded. I'm pretty
sure Mats was talking about each side of the slot/ram pcb.

> As far as it goes with rows/banks, most intel boards only support
> asymmetrical sdrams so if the dimm has two sides the second side has to
> equal the first side.

You mean "only support symmetrical sdrams". IIRC, i810 supports
asymmetrical dimms, but I can't remember...

-Corey

> As far as sdram slots any combination should work as
> long as it follows the the northbridge criteria. You can look at the i830
> raminit.c, it has a pretty clever way to detect dimms, and it works every
> time no matter what the combination. By the way Uwe was the original author
> of the i440bx code. Hope that helps.
>
> --
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
>
>



From rminnich at gmail.com  Fri Sep  5 16:50:02 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 07:50:02 -0700
Subject: [coreboot] Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <48C0FF74.6070608@gmx.net>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
	<48C0FF74.6070608@gmx.net>
Message-ID: <13426df10809050750r48b7a80cjc465b6ad83c691c@mail.gmail.com>

On Fri, Sep 5, 2008 at 2:44 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Yes and no. At least the new AMD Family 10h processors can't use CAR for
> data storage and code storage at the same time. In theory, you could
> fill the CAR area in data storage mode, then switch over to code
> storage. Not tested, though, and NOT mentioned as viable in the BKDG
> (BIOS and Kernel Developer's Guide).
>


hmm, this will mean a redesign in v3 if true.

We count on using CAR for code (initram)

ron



From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 17:01:02 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 17:01:02 +0200
Subject: [coreboot] Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <13426df10809050750r48b7a80cjc465b6ad83c691c@mail.gmail.com>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>	
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>	
	<48C0FF74.6070608@gmx.net>
	<13426df10809050750r48b7a80cjc465b6ad83c691c@mail.gmail.com>
Message-ID: <48C149AE.5090104@gmx.net>

On 05.09.2008 16:50, ron minnich wrote:
> On Fri, Sep 5, 2008 at 2:44 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>
>   
>> Yes and no. At least the new AMD Family 10h processors can't use CAR for
>> data storage and code storage at the same time. In theory, you could
>> fill the CAR area in data storage mode, then switch over to code
>> storage. Not tested, though, and NOT mentioned as viable in the BKDG
>> (BIOS and Kernel Developer's Guide).
>>     
>
> hmm, this will mean a redesign in v3 if true.
>   

Not really. v3 does not try to load any code into the CAR area.

> We count on using CAR for code (initram)
>   

initram is not loaded into the CAR area, it is XIP in the ROM.

Let me rephrase: On Fam10h, it is not possible to _store_ code and
read/write data in a given CAR area. Depending on CAR granularity, you
can designate each part of the CAR area for a different purpose. Example:
CAR as code storage (readonly) from 0xc8000-0xc8fff, CAR as data storage
(read/write) from 0xc9000-0xcffff.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Fri Sep  5 17:06:11 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 08:06:11 -0700
Subject: [coreboot] Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <48C149AE.5090104@gmx.net>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
	<48C0FF74.6070608@gmx.net>
	<13426df10809050750r48b7a80cjc465b6ad83c691c@mail.gmail.com>
	<48C149AE.5090104@gmx.net>
Message-ID: <13426df10809050806r22471d99oe66fb31cc2058b50@mail.gmail.com>

On Fri, Sep 5, 2008 at 8:01 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 05.09.2008 16:50, ron minnich wrote:


>> hmm, this will mean a redesign in v3 if true.
>>
>
> Not really. v3 does not try to load any code into the CAR area.
>

you're right. Ron, drink more coffee. Sorry, was up very late.

ron



From rmh at aybabtu.com  Fri Sep  5 17:08:17 2008
From: rmh at aybabtu.com (Robert Millan)
Date: Fri, 5 Sep 2008 17:08:17 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
Message-ID: <20080905150817.GA11396@thorin>


Hi,

I notice in http://tracker.coreboot.org/trac/coreboot/ticket/88 that
Coresystems is no longer working on GRUB 2 (that's too bad, sorry that
it didn't work out, etc...).

I have nothing to say about what you will be recommending as default bootloader
in the future.  Right now your wiki still recommends GRUB 2, and I suppose
Coresystems folks will want to push for FILO.  But this is not a discussion
I want to be involved in (just wanted to clarify ;-)).

What I'm concerned about is that http://www.coreboot.org/GRUB2 in the wiki
currently points to a branch of GRUB that is (unless I missed something)
no longer being maintained.  And it provides information that will, over time,
become more and more obsolete.  I'm worried that this can reflect bad on the
image of GRUB.

So what I'd like is permission to keep it up to date, and reflect the current
state of GRUB mainline.  If you would give me a wiki account to do that, it'd
be much appreciated.

Thanks

-- 
Robert Millan

  The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
  how) you may access your data; but nobody's threatening your freedom: we
  still allow you to remove your data and not access it at all."



From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 17:16:00 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 17:16:00 +0200
Subject: [coreboot] Cache as RAM - is it possible to execute
	code	in	cache?
In-Reply-To: <8012472D-CBBA-451C-A009-D7931A33D458@coresystems.de>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>	<48C0FF74.6070608@gmx.net>
	<8012472D-CBBA-451C-A009-D7931A33D458@coresystems.de>
Message-ID: <48C14D30.5090700@gmx.net>

On 05.09.2008 12:54, Stefan Reinauer wrote:

> On 05.09.2008 09:45, Jackie Pan wrote:
>> if it's possible to place code into cache-emulated RAM
>
> Core 2 Duo can do cache for ram and code... But it works well enough
> to just set an mtrr to make rom cacheable during car and that also
> works for older intel CPUs

We're talking about different things.
Jackie was talking about executing code stored inside the pseudo-RAM CAR
area. I was talking about that as well.
Stefan wrote about using cache for code outside the CAR area.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Fri Sep  5 17:18:15 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Sep 2008 17:18:15 +0200
Subject: [coreboot] r3566 - trunk/payloads/coreinfo
Message-ID: <mailman.2031.1355071375.16123.coreboot@coreboot.org>

Author: stepan
Date: 2008-09-05 17:18:15 +0200 (Fri, 05 Sep 2008)
New Revision: 3566

Modified:
   trunk/payloads/coreinfo/pci_module.c
Log:
define array size in a single place (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/payloads/coreinfo/pci_module.c
===================================================================
--- trunk/payloads/coreinfo/pci_module.c	2008-09-04 21:05:59 UTC (rev 3565)
+++ trunk/payloads/coreinfo/pci_module.c	2008-09-05 15:18:15 UTC (rev 3566)
@@ -29,7 +29,8 @@
 	unsigned int id;
 };
 
-static struct pci_devices devices[64];
+#define MAX_PCI_DEVICES 64
+static struct pci_devices devices[MAX_PCI_DEVICES];
 static int devices_index;
 
 /* Number of entries to show in the list */
@@ -190,7 +191,7 @@
 				continue;
 
 			/* FIXME: Remove this arbitrary limitation. */
-			if (devices_index >= 64)
+			if (devices_index >= MAX_PCI_DEVICES)
 				return;
 
 			devices[devices_index].device = 




From stepan at coresystems.de  Fri Sep  5 17:19:38 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Sep 2008 17:19:38 +0200
Subject: [coreboot] Cache as RAM - is it possible to execute
	code	in	cache?
In-Reply-To: <48C14D30.5090700@gmx.net>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>	<48C0FF74.6070608@gmx.net>
	<8012472D-CBBA-451C-A009-D7931A33D458@coresystems.de>
	<48C14D30.5090700@gmx.net>
Message-ID: <48C14E0A.2070304@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 05.09.2008 12:54, Stefan Reinauer wrote:
>
>   
>> On 05.09.2008 09:45, Jackie Pan wrote:
>>     
>>> if it's possible to place code into cache-emulated RAM
>>>       
>> Core 2 Duo can do cache for ram and code... But it works well enough
>> to just set an mtrr to make rom cacheable during car and that also
>> works for older intel CPUs
>>     
>
> We're talking about different things.
> Jackie was talking about executing code stored inside the pseudo-RAM CAR
> area. I was talking about that as well.
> Stefan wrote about using cache for code outside the CAR area.
>   
No, not at all different things. As I said, the Core 2 Duo can execute
code stored in CAR.



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From vincent.legoll at gmail.com  Fri Sep  5 17:24:10 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Fri, 5 Sep 2008 17:24:10 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905150817.GA11396@thorin>
References: <20080905150817.GA11396@thorin>
Message-ID: <4727185d0809050824i7c33559co2ae73bbbba32dbe0@mail.gmail.com>

On Fri, Sep 5, 2008 at 5:08 PM, Robert Millan <rmh at aybabtu.com> wrote:
> So what I'd like is permission to keep it up to date, and reflect the current
> state of GRUB mainline.  If you would give me a wiki account to do that, it'd
> be much appreciated.

The payloads page would need to be updated too, then.

-- 
Vincent Legoll



From jordan.crouse at amd.com  Fri Sep  5 17:42:29 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 5 Sep 2008 09:42:29 -0600
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905150817.GA11396@thorin>
References: <20080905150817.GA11396@thorin>
Message-ID: <20080905154229.GD31555@cosmic.amd.com>

On 05/09/08 17:08 +0200, Robert Millan wrote:
> 
> Hi,
> 
> I notice in http://tracker.coreboot.org/trac/coreboot/ticket/88 that
> Coresystems is no longer working on GRUB 2 (that's too bad, sorry that
> it didn't work out, etc...).
> 
> I have nothing to say about what you will be recommending as default bootloader
> in the future.  Right now your wiki still recommends GRUB 2, and I suppose
> Coresystems folks will want to push for FILO.  But this is not a discussion
> I want to be involved in (just wanted to clarify ;-)).

Coresystems has people that depend on them for a livelyhood - they have to
do what is best for their customers, and we are very lucky that their goals
often align with those of the community.   I do wish things had ended up
differently, but I welcome the FILO work because it make both FILO and
libpayload that much better, and thats not a bad thing.

But I don't think we as a community are ready to abandon GRUB2 quite yet.
We need a working bootloader for Linux, that is true, but I believe in 
providing options to our customers. If there are people willing to do the
work for GRUB2, then we'll be glad to keep tracking it in the wiki and
in buildrom.

When you anoint a single program as the "chosen one" then you lock yourself
for trouble down the road.  I would much prefer to chose between 3 great
programs then one mediocre one.

> What I'm concerned about is that http://www.coreboot.org/GRUB2 in the wiki
> currently points to a branch of GRUB that is (unless I missed something)
> no longer being maintained.  And it provides information that will, over time,
> become more and more obsolete.  I'm worried that this can reflect bad on the
> image of GRUB.
> 
> So what I'd like is permission to keep it up to date, and reflect the current
> state of GRUB mainline.  If you would give me a wiki account to do that, it'd
> be much appreciated.

I second the request.

Jordan

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From stepan at coresystems.de  Fri Sep  5 17:52:51 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Sep 2008 17:52:51 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905150817.GA11396@thorin>
References: <20080905150817.GA11396@thorin>
Message-ID: <48C155D3.7010900@coresystems.de>

Robert Millan wrote:
> I have nothing to say about what you will be recommending as default bootloader
> in the future.  Right now your wiki still recommends GRUB 2, and I suppose
> Coresystems folks will want to push for FILO.  But this is not a discussion
> I want to be involved in (just wanted to clarify ;-)).
>   
We've not been pushing any "default bootloader" in the past, nor will we
do so in the future.
I believe coreboot is about freedom and choice. And about making stuff
that people can actually use.
Now, this last criteria is different for a multitude of use cases.
> What I'm concerned about is that http://www.coreboot.org/GRUB2 in the wiki
> currently points to a branch of GRUB that is (unless I missed something)
> no longer being maintained.  And it provides information that will, over time,
> become more and more obsolete.  I'm worried that this can reflect bad on the
> image of GRUB.
>   
I wonder whether we need to keep our own GRUB2 page at all, since
there's a coreboot page in the GRUB2 wiki already and if things go as
you suggest, one of them will eventually be a copy of the other one.

> So what I'd like is permission to keep it up to date, and reflect the current
> state of GRUB mainline.  If you would give me a wiki account to do that, it'd
> be much appreciated.
>   

Use ist wisely. And please create User:RobertMillan so people know who
you are.

All the best,

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From joe at settoplinux.org  Fri Sep  5 17:54:49 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 05 Sep 2008 11:54:49 -0400
Subject: [coreboot] v2: Detection of sdram densities.
In-Reply-To: <dd3c80060809050739w40abc184v2824817b8372b12a@mail.gmail.com>
References: <E1Kaw7Y-0006ta-Br@aun.bellman.mea>
	<dd3c80060809042027n78e01c12nc84dc0e644545991@mail.gmail.com>
	<5b6d38ae9075ca1f76f7cc9266e44e14@imap.1and1.com>
	<dd3c80060809050739w40abc184v2824817b8372b12a@mail.gmail.com>
Message-ID: <4e1cf4153f7e400c12d91ffdf64bd5e5@imap.1and1.com>




On Fri, 5 Sep 2008 10:39:02 -0400, "Corey Osgood" <corey.osgood at gmail.com>
wrote:
> On Fri, Sep 5, 2008 at 8:09 AM, Joseph Smith <joe at settoplinux.org> wrote:
>>
>>
>>
>> On Thu, 4 Sep 2008 23:27:50 -0400, "Corey Osgood"
> <corey.osgood at gmail.com>
>> wrote:
>>> On Wed, Sep 3, 2008 at 1:26 PM, Mats Erik Andersson
>>> <mats.andersson at gisladisker.se> wrote:
>>>>
>>>> Hello again,
>>>>
>>>> I have been experimenting with an algorithm to detect
>>>> and register with the northbridge i440bx the correct
>>>> amount of sdram present. A C-coded version is appended
>>>> to this message. Feel free to comment on the method.
>>>>
>>>> In the actually working code, I had to split the
>>>> algorithm into a lower and an upper part, in order
>>>> not to run out of internal registers under romcc,
>>>> but the idea remains the same.
>>>>
>>>> Since there are also some later stages where I have
>>>> not understood how the previous author hard coded
>>>> a single 64MB bank,  I presently achieve a running
>>>> system only when I dynamically detect a distribution
>>>> identical to what was earlier hard coded.
>>>>
>>>> My detection works with any combination of 0MB and
>>>> 64MB in two rows for DIMM0 and DIMM1.
>>>>
>>>> Question: In case an sdram device has rows of mixed
>>>> sizes, can one depend on the larger density being
>>>> in row zero, and the smaller content in row one?
>>>
>>> Yes. The spd spec assumes the larger row will be row 0, any stick that
>>> didn't wouldn't follow the standard. At least, that was my
>>> understanding of it.
>>>
>> This can get a little confusing, when you are talking about rows, do you
>> mean banks? Or actuall sdram slots?
> 
> Banks, I assume, all this terminology gets me confuseded. I'm pretty
> sure Mats was talking about each side of the slot/ram pcb.
> 
>> As far as it goes with rows/banks, most intel boards only support
>> asymmetrical sdrams so if the dimm has two sides the second side has to
>> equal the first side.
> 
> You mean "only support symmetrical sdrams". IIRC, i810 supports
> asymmetrical dimms, but I can't remember...
> 
> -Corey
> 
>> As far as sdram slots any combination should work as
>> long as it follows the the northbridge criteria. You can look at the
> i830
>> raminit.c, it has a pretty clever way to detect dimms, and it works
> every
>> time no matter what the combination. By the way Uwe was the original
> author
>> of the i440bx code. Hope that helps.
>>
Right, symmetrical sdrams, sorry for the slip of toung. And yes to Mat's
question, in the case of a asymmetrical dual-sided DIMM the first side will
always be larger. But that should not matter, if your code is calculating
on a per side/bank basis, I mean it should be able to detect the size of
each side/bank, and if it is dual-sided, and add the two sides/banks
togethor to give you the total size. As far as initailization goes, each
side/bank needs to initalized seperatly... that's where it can get a little
tricky. That's also why it is important to calculate memory on a per
side/bank basis....
Hope that helps.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri Sep  5 18:04:27 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 05 Sep 2008 12:04:27 -0400
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905154229.GD31555@cosmic.amd.com>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
Message-ID: <102a5694a717575e13c04245c84a818f@imap.1and1.com>


>> Coresystems folks will want to push for FILO.

I've actually been think about FILO alot lately. The code is still solid.
With libpayload progressing, it would be really cool to see a "FILO 2.0"
that is totally revamped with all dependencies on libpayload and all the
great things libpayload has to offer. Just something I have been pondering
lately....

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 18:10:44 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 18:10:44 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905150817.GA11396@thorin>
References: <20080905150817.GA11396@thorin>
Message-ID: <48C15A04.60005@gmx.net>

On 05.09.2008 17:08, Robert Millan wrote:
> I notice in http://tracker.coreboot.org/trac/coreboot/ticket/88 that
> Coresystems is no longer working on GRUB 2 (that's too bad, sorry that
> it didn't work out, etc...).
>
> [...]
> What I'm concerned about is that http://www.coreboot.org/GRUB2 in the wiki
> currently points to a branch of GRUB that is (unless I missed something)
> no longer being maintained.  And it provides information that will, over time,
> become more and more obsolete.  I'm worried that this can reflect bad on the
> image of GRUB.
>   

The most interesting question is why these GRUB patches were not merged
upstream. If any, that may reflect badly on the image of GRUB.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Fri Sep  5 18:45:41 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Sep 2008 18:45:41 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <102a5694a717575e13c04245c84a818f@imap.1and1.com>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
	<102a5694a717575e13c04245c84a818f@imap.1and1.com>
Message-ID: <48C16235.7020707@coresystems.de>

Joseph Smith wrote:
>>> Coresystems folks will want to push for FILO.
>>>       
>
> I've actually been think about FILO alot lately. The code is still solid.
> With libpayload progressing, it would be really cool to see a "FILO 2.0"
> that is totally revamped with all dependencies on libpayload and all the
> great things libpayload has to offer. Just something I have been pondering
> lately....
>   

Yep, that's pretty much where it's going...

FILO might become just the main loop calling libpayload functions and
painting a nice menu.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From joe at settoplinux.org  Fri Sep  5 19:02:45 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 05 Sep 2008 13:02:45 -0400
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <48C16235.7020707@coresystems.de>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
	<102a5694a717575e13c04245c84a818f@imap.1and1.com>
	<48C16235.7020707@coresystems.de>
Message-ID: <522432352237bd8ca4d0a0fa9d2b22f4@imap.1and1.com>




On Fri, 05 Sep 2008 18:45:41 +0200, Stefan Reinauer <stepan at coresystems.de>
wrote:
> Joseph Smith wrote:
>>>> Coresystems folks will want to push for FILO.
>>>>       
>>
>> I've actually been think about FILO alot lately. The code is still
> solid.
>> With libpayload progressing, it would be really cool to see a "FILO 2.0"
>> that is totally revamped with all dependencies on libpayload and all the
>> great things libpayload has to offer. Just something I have been
> pondering
>> lately....
>>   
> 
> Yep, that's pretty much where it's going...
> 
> FILO might become just the main loop calling libpayload functions and
> painting a nice menu.
> 
Do you mean integrating FILO into libpayload or will the FILO main() still
be seperate code?
I like the "painting a nice menu" part. Maybe with a pretty coreboot logo
too...
While we are on the subject, I was also thinking about how hard would it be
to allocate a small part of flash as a read/write user area for saving boot
options?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From stepan at coresystems.de  Fri Sep  5 19:17:13 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 05 Sep 2008 19:17:13 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <522432352237bd8ca4d0a0fa9d2b22f4@imap.1and1.com>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
	<102a5694a717575e13c04245c84a818f@imap.1and1.com>
	<48C16235.7020707@coresystems.de>
	<522432352237bd8ca4d0a0fa9d2b22f4@imap.1and1.com>
Message-ID: <48C16999.6040109@coresystems.de>

Joseph Smith wrote:
>> FILO might become just the main loop calling libpayload functions and
>> painting a nice menu
> Do you mean integrating FILO into libpayload or will the FILO main() still
> be seperate code?
>   
No, it will always stay seperate code.

> I like the "painting a nice menu" part. Maybe with a pretty coreboot logo
> too...
>   

> While we are on the subject, I was also thinking about how hard would it be
> to allocate a small part of flash as a read/write user area for saving boot
> options?
>   
With flashrom ported to libpayload it should be quite reasonable.

If nvram (256 bytes of cmos) are enough, you can have that right away..
FILO 0.6 has an option to read the default menu entry from cmos, and it
can be set/changed with nvramtool.



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From joe at settoplinux.org  Fri Sep  5 19:39:18 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 05 Sep 2008 13:39:18 -0400
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <48C16999.6040109@coresystems.de>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
	<102a5694a717575e13c04245c84a818f@imap.1and1.com>
	<48C16235.7020707@coresystems.de>
	<522432352237bd8ca4d0a0fa9d2b22f4@imap.1and1.com>
	<48C16999.6040109@coresystems.de>
Message-ID: <5f0fccd1f2db3f42764fe11de1ed1939@imap.1and1.com>




On Fri, 05 Sep 2008 19:17:13 +0200, Stefan Reinauer <stepan at coresystems.de>
wrote:
> Joseph Smith wrote:
>>> FILO might become just the main loop calling libpayload functions and
>>> painting a nice menu
>> Do you mean integrating FILO into libpayload or will the FILO main()
> still
>> be seperate code?
>>   
> No, it will always stay seperate code.
> 
>> I like the "painting a nice menu" part. Maybe with a pretty coreboot
> logo
>> too...
>>   
> 
>> While we are on the subject, I was also thinking about how hard would it
> be
>> to allocate a small part of flash as a read/write user area for saving
> boot
>> options?
>>   
> With flashrom ported to libpayload it should be quite reasonable.
> 
> If nvram (256 bytes of cmos) are enough, you can have that right away..
> FILO 0.6 has an option to read the default menu entry from cmos, and it
> can be set/changed with nvramtool.
> 
Cool I did not know that, is it documented on the wiki somewhere?
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Fri Sep  5 20:20:57 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Sep 2008 20:20:57 +0200
Subject: [coreboot] r3567 - in trunk/coreboot-v2/src: include/device
	southbridge/via/vt8237r
Message-ID: <mailman.2032.1355071375.16123.coreboot@coreboot.org>

Author: ruik
Date: 2008-09-05 20:20:57 +0200 (Fri, 05 Sep 2008)
New Revision: 3567

Added:
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c
Modified:
   trunk/coreboot-v2/src/include/device/pci_ids.h
   trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_sata.c
Log:
This patch adds support for the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested
on mine desktop) except of reverting the small change introduced by Bari
(gpio/inta setup reg 0x5b). This should go for some board specific file. The
change would broke at least mine board. But seems to be needed for jakllsch.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Bari Ari <bari at onelabs.com> 



Modified: trunk/coreboot-v2/src/include/device/pci_ids.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ids.h	2008-09-05 15:18:15 UTC (rev 3566)
+++ trunk/coreboot-v2/src/include/device/pci_ids.h	2008-09-05 18:20:57 UTC (rev 3567)
@@ -1160,6 +1160,9 @@
 #define PCI_DEVICE_ID_VIA_K8T890CE_BR	0xb188
 #define PCI_DEVICE_ID_VIA_VT6420_SATA	0x3149
 #define PCI_DEVICE_ID_VIA_VT8237R_LPC	0x3227
+#define PCI_DEVICE_ID_VIA_VT8237S_LPC	0x3372
+#define PCI_DEVICE_ID_VIA_VT8237_SATA	0x5372
+#define PCI_DEVICE_ID_VIA_VT8237_VLINK	0x287e
 #define PCI_DEVICE_ID_VIA_CN700_AGP	0x0314
 #define PCI_DEVICE_ID_VIA_CN700_ERR	0x1314
 #define PCI_DEVICE_ID_VIA_CN700_HOST	0x2314

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb	2008-09-05 15:18:15 UTC (rev 3566)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/Config.lb	2008-09-05 18:20:57 UTC (rev 3567)
@@ -20,6 +20,7 @@
 config chip.h
 
 driver vt8237r.o
+driver vt8237_ctrl.o
 driver vt8237r_ide.o
 driver vt8237r_lpc.o
 driver vt8237r_sata.o

Added: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c	2008-09-05 18:20:57 UTC (rev 3567)
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+/* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */
+
+static void vt8237_cfg(struct device *dev)
+{
+	u8 regm, regm2, regm3;
+
+	device_t devfun3;
+
+	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+
+		if (!devfun3)
+			devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
+
+		if (!devfun3)
+			die("Unknown NB");
+
+	/* CPU to PCI Flow Control 1 & 2, just fill in recommended */
+	pci_write_config8(dev, 0x70, 0xc2);
+	pci_write_config8(dev, 0x71, 0xc8);
+
+	/* PCI Control */
+	pci_write_config8(dev, 0x72, 0xee);
+	pci_write_config8(dev, 0x73, 0x01);
+	pci_write_config8(dev, 0x74, 0x3c);
+	pci_write_config8(dev, 0x75, 0x0f);
+	pci_write_config8(dev, 0x76, 0x50);
+	pci_write_config8(dev, 0x77, 0x48);
+	pci_write_config8(dev, 0x78, 0x01);
+	/* APIC on HT */
+	pci_write_config8(dev, 0x7c, 0x77); //maybe Enable LDT APIC Mode bit3 set to 1
+
+	/* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */
+
+	regm = pci_read_config8(devfun3, 0x88);	/* Shadow mem CTRL */
+	pci_write_config8(dev, 0x57, regm);
+
+	regm = pci_read_config8(devfun3, 0x80);	/* Shadow page C */
+	pci_write_config8(dev, 0x61, regm);
+
+	regm = pci_read_config8(devfun3, 0x81);	/* Shadow page D */
+	pci_write_config8(dev, 0x62, regm);
+
+	/* Shadow page F + memhole copy */
+	regm = pci_read_config8(devfun3, 0x83);
+	pci_write_config8(dev, 0x63, regm);
+
+	regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
+	pci_write_config8(dev, 0x64, regm);
+
+	regm = pci_read_config8(devfun3, 0x86);	/* SMM and APIC decoding */
+	pci_write_config8(dev, 0xe6, regm);
+}
+
+/**
+ * Example of setup: Setup the V-Link for VT8237R, 8X mode.
+ *
+ * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
+ *
+ *						 REG   DEF   AW  VIA-8X VIA-4X
+ *						 -----------------------------
+ * NB V-Link Manual Driving Control strobe	 0xb5  0x46  0x46  0x88  0x88
+ * NB V-Link Manual Driving Control - Data	 0xb6  0x46  0x46  0x88  0x88
+ * NB V-Link Receiving Strobe Delay		 0xb7  0x02  0x02  0x61  0x01
+ * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4  0x10  0x10  0x11  0x11
+ * SB V-Link Strobe Drive Control 		 0xb9  0x00  0xa5  0x98  0x98
+ * SB V-Link Data drive Control????		 0xba  0x00  0xbb  0x77  0x77
+ * SB V-Link Receive Strobe Delay????		 0xbb  0x04  0x11  0x11  0x11
+ * SB V-Link Compensation Control bit0 (use b9)	 0xb8  0x00  0x01  0x01  0x01
+ * V-Link CKG Control				 0xb0  0x05  0x05  0x06  0x03
+ * V-Link CKG Control				 0xb1  0x05  0x05  0x01  0x03
+ */
+
+static void vt8237s_vlink_init(struct device *dev)
+{
+	u8 reg;
+
+	device_t devfun7;
+
+	devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					   PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+
+	/* no pairing NB found */
+	if (!devfun7)
+		return;
+
+	/*
+	 * This init code is valid only for the VT8237S! For different
+	 * sounthbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R)
+	 * and VT8251) a different init code is required.
+	 */
+
+	pci_write_config8(devfun7, 0xb5, 0x66);
+	pci_write_config8(devfun7, 0xb6, 0x66);
+	pci_write_config8(devfun7, 0xb7, 0x65);
+
+	reg = pci_read_config8(devfun7, 0xb4);
+	reg |= 0x1;
+	pci_write_config8(devfun7, 0xb4, reg);
+
+	pci_write_config8(dev, 0xb9, 0x68);
+	pci_write_config8(dev, 0xba, 0x88);
+	pci_write_config8(dev, 0xbb, 0x89);
+
+
+	reg = pci_read_config8(dev, 0xbd);
+	reg |= 0x3;
+	pci_write_config8(dev, 0xbd, reg);
+
+	/* Program V-link 8X 8bit full duplex, parity disabled FIXME */
+	pci_write_config8(dev, 0x48, 0x13);
+}
+
+static void ctrl_enable(struct device *dev) {
+	
+	/* enable the 0:13 and 0:13.1 */
+	/* FIXME */
+	pci_write_config8(dev, 0x4f, 0x43);
+}
+
+
+extern void dump_south(device_t dev);
+
+static void ctrl_init(struct device *dev) {
+
+	/* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
+	   should to 1 FIXME DO you need?*/
+
+	/* VT8237R specific configuration  other SB are done in their own directories */
+	/*  add A version */
+	device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
+					PCI_DEVICE_ID_VIA_VT8237S_LPC, 0);
+	if (devsb) {
+		/* FIXME: Skip v-link setup for now */
+//		vt8237s_vlink_init(dev);
+	}
+
+	/* configure PCI1 and copy mirror registers from D0F3 */
+	vt8237_cfg(dev);
+	dump_south(dev);
+}
+
+static const struct device_operations ctrl_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ctrl_init,
+	.enable			= ctrl_enable,
+	.ops_pci		= 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+	.ops	= &ctrl_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT8237_VLINK,
+};

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h	2008-09-05 15:18:15 UTC (rev 3566)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h	2008-09-05 18:20:57 UTC (rev 3567)
@@ -20,6 +20,8 @@
 #ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
 #define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
 
+#include <stdint.h>
+
 /* Static resources for the VT8237R southbridge */
 
 #define VT8237R_APIC_ID			0x2
@@ -27,6 +29,7 @@
 #define VT8237R_SMBUS_IO_BASE		0x400
 /* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */
 #define VT8237R_ACPI_IRQ		0x9
+#define VT8237S_SPI_MEM_BASE		0xfed02000ULL
 #define VT8237R_HPET_ADDR		0xfed00000ULL
 #define VT8237R_APIC_BASE		0xfec00000ULL
 
@@ -68,4 +71,28 @@
 
 #define SMBUS_DELAY() inb(0x80)
 
+struct vt8237_network_rom {
+	u8 mac_address[6];
+	u8 phy_addr;
+	u8 res1;
+	u16 sub_sid;
+	u16 sub_vid;
+	u16 pid;
+	u16 vid;
+	u8 pmcc;
+	u8 data_sel;
+	u8 pmu_data_reg;
+	u8 aux_curr;
+	u16 reserved;
+	u8 min_gnt;
+	u8 max_lat;
+	u8 bcr0;
+	u8 bcr1;
+	u8 cfg_a;
+	u8 cfg_b;
+	u8 cfg_c;
+	u8 cfg_d;
+	u8 checksum;
+} __attribute__ ((packed));
+
 #endif

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-09-05 15:18:15 UTC (rev 3566)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	2008-09-05 18:20:57 UTC (rev 3567)
@@ -128,7 +128,6 @@
 
 	return val;
 }
-
 /**
  * Enable the smbus on vt8237r-based systems
  */
@@ -137,11 +136,17 @@
 	device_t dev;
 
 	/* Power management controller */
+
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
 
-	if (dev == PCI_DEV_INVALID)
-		die("Power management controller not found\r\n");
+	if (dev == PCI_DEV_INVALID) {
+		/* Power management controller */
+		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					       PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+		if (dev == PCI_DEV_INVALID)
+			die("Power management controller not found\r\n");
+	}
 
 	/* 7 = SMBus Clock from RTC 32.768KHz
 	 * 5 = Internal PLL reset from susp
@@ -213,17 +218,253 @@
 		PRINT_DEBUG("Done\r\n");
 }
 
+/* fixme better separate the NB and SB, will done once it works */
+
+void vt8237_sb_enable_fid_vid(void) {
+	device_t dev;
+	device_t devctl;
+
+	/* Power management controller */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+
+	if (dev == PCI_DEV_INVALID) {
+    		/* Power management controller */
+		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					       PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+		if (dev == PCI_DEV_INVALID)
+			return;
+
+		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					       PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
+		if (devctl == PCI_DEV_INVALID)
+			return;
+		
+		{
+		u8 tmp;
+		tmp = pci_read_config8(devctl, 0xec);
+		print_debug("EC is ");
+		print_debug_hex8(tmp);
+		print_debug(" E5 is ");
+		tmp = pci_read_config8(dev, 0xe5);
+		print_debug_hex8(tmp);
+		
+		}
+		/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
+		pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+		/* Enable ACPI accessm RTC signal gated with PSON. */
+		pci_write_config8(dev, 0x81, 0x84);
+		/* Allow SLP# signal to assert LDTSTOP_L.
+		 * Will work for C3 and for FID/VID change.
+		 */
+
+		/* fixme */
+		outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);  //fixme maybe not needed
+
+//		outb(0x4, VT8237R_ACPI_IO_BASE + 0x50);  //fixme maybe not needed
+
+		/* it seems for AMD LDTSTP is connected not to SLP anymore */
+		/* enable 0: DPSLP# / DPRSTP# / VRDSLP */
+
+		/* Enable SATA LED, VR timer = 100us
+		 * Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs to some of those pins! (and not to SLP as on R ver)
+		 */
+		 //fixme
+		pci_write_config8(dev, 0xe5, 0x69);
+	
+		/* REQ5 as PCI request input - should be together with INTE-INTH. 
+		 * Fast VR timer disable - need for LDTSTP signal
+		*/
+		pci_write_config8(dev, 0xe4, 0xa5);
+	
+		/* reduce further the STPCLK/LDTSTP signal to 5us */
+
+		pci_write_config8(dev, 0xec, 0x4);
+		/* Host Bus Power Management Control, maybe not needed */
+		pci_write_config8(dev, 0x8c, 0x5);
+
+		/* so the chip knows we are on AMD */
+		pci_write_config8(devctl, 0x7c, 0x77);
+
+		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					       0x2336), 0);
+		if (devctl == PCI_DEV_INVALID)
+			return;
+		/* Enable C2NOW delay to PSTATECTL VID / FID Change Delay to P-State Control */
+		pci_write_config8(devctl, 0xa6, 0x83);
+
+		//return; //FIXME fall through some revs have it old way
+	}
+	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
+	pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+	/* Enable ACPI accessm RTC signal gated with PSON. */
+	pci_write_config8(dev, 0x81, 0x84);
+	/* Allow SLP# signal to assert LDTSTOP_L.
+	 * Will work for C3 and for FID/VID change.
+	 */
+	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+}
+
 void enable_rom_decode(void)
 {
 	device_t dev;
 
-	/* Bus Control and Power Management  */
+	/* Power management controller */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 				       PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
 
-	if (dev == PCI_DEV_INVALID)
-		die("SB not found\r\n");
+	if (dev == PCI_DEV_INVALID) {
+    		/* Power management controller */
+		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+					       PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+		if (dev == PCI_DEV_INVALID)
+			return;
+	}
 
 	/* ROM decode last 1MB FFC00000 - FFFFFFFF */
 	pci_write_config8(dev, 0x41, 0x7f);
 }
+
+void vt8237_early_spi_init(void) {
+	device_t dev;
+	volatile u16 *spireg;
+	u32 tmp;
+
+	/* Bus Control and Power Management  */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				       PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+
+	if (dev == PCI_DEV_INVALID)
+		die("SB not found\r\n");
+
+	/* put SPI base 20 d0 fe */
+	tmp = pci_read_config32(dev, 0xbc);
+	pci_write_config32(dev, 0xbc, (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
+
+	/* set SPI clock to 33MHz */
+	spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
+	(*spireg) &=  0xff00;
+}
+
+/* offset 0x58
+ * 31:20 	reserved
+ * 19:16	4 bit position in shadow EEPROM
+ * 15:0		data to write
+ *
+ * offset 0x5c
+ * 31:28	reserved
+ * 27 		ERDBG - enable read from 0x5c
+ * 26		reserved
+ * 25		SEELD
+ * 24		SEEPR - write 1 when done updating, wait until SEELD is set to 1, sticky
+ *		cleared by reset, if it is 1 writing is disabled
+ * 19:16	4 bit position in shadow EEPROM
+ * 15:0		data from shadow EEPROM
+ *
+ * after PCIRESET SEELD and SEEPR must be 1 and 1
+*/
+
+/* 1 = needs PCI reset, 0 don't reset, network initialized */
+
+/* fixme maybe close the debug register after use? */
+
+#define LAN_TIMEOUT 0x7FFFFFFF
+
+int vt8237_early_network_init(struct vt8237_network_rom *rom) {
+	struct vt8237_network_rom n;
+	int loops;
+	device_t dev;
+	u32 tmp;
+	u8 status;
+	u16 *rom_write;
+	unsigned int checksum;
+	int i;
+
+	/* Network adapter */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				       PCI_DEVICE_ID_VIA_8233_7), 0);
+
+	if (dev == PCI_DEV_INVALID) {
+	    print_err("Network is disabled, please enable\n");
+	    return 0;
+	}
+
+	tmp = pci_read_config32(dev, 0x5c);
+	/* enable ERDBG */
+	tmp |= 0x08000000;
+	pci_write_config32(dev, 0x5c, tmp);
+	
+	status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3);
+	
+	if (status == 3) {
+	    /* network controller OK, EEPROM loaded */
+	    return 0;
+	}
+	
+	if (rom == NULL) {
+	    print_err("No configuration data specified, using default MAC!\n");
+		n.mac_address[0] = 0x0;
+		n.mac_address[1] = 0x0;
+		n.mac_address[2] = 0xde;
+		n.mac_address[3] = 0xad;
+		n.mac_address[4] = 0xbe;
+		n.mac_address[5] = 0xef;
+		n.phy_addr = 0x1;
+		n.res1 = 0x0;
+		n.sub_sid = 0x102;
+		n.sub_vid = 0x1106;
+		n.pid = 0x3065;
+		n.vid = 0x1106;
+		n.pmcc = 0x1f;
+		n.data_sel = 0x10;
+		n.pmu_data_reg = 0x0;
+		n.aux_curr = 0x0;
+		n.reserved = 0x0;
+		n.min_gnt = 0x3;
+		n.max_lat = 0x8;
+		n.bcr0 = 0x9;
+		n.bcr1 = 0xe;
+		n.cfg_a = 0x3;
+		n.cfg_b = 0x0;
+		n.cfg_c = 0x40;
+		n.cfg_d = 0x82;
+		n.checksum = 0x0;
+		rom = &n;
+	}
+	
+	rom_write = (u16 *) rom;
+	checksum = 0;
+	/* write all data except checksum and second to last byte */
+	tmp &= 0xff000000; /* leave reserved bits in */
+	for (i = 0; i < 15; i++) {
+		pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]);
+		/* lame code fixme */
+		checksum += rom_write[i] & 0xff;
+		//checksum %= 256;
+		checksum += (rom_write[i] >> 8) & 0xff;
+		//checksum %= 256;
+	}
+	
+	checksum += (rom_write[15] & 0xff);
+	checksum = ~(checksum & 0xff);
+	tmp |= (((checksum & 0xff) << 8) | rom_write[15]);
+
+	/* write last byte and checksum */
+	pci_write_config32(dev, 0x58, (15 << 16) |  tmp);
+	
+	tmp = pci_read_config32(dev, 0x5c);
+	pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* toggle SEEPR */
+	
+	/* Yes, this is a mess, but it's the easiest way to do it. */
+	while ( (((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0)
+ 			&& (loops < LAN_TIMEOUT))
+		++loops;
+
+	if (loops >= LAN_TIMEOUT) {
+	    print_err("Timout - LAN controller did not accept configuration\n");
+	    return 0;
+	}
+	
+	/* we are done, config will be used after PCIRST# */
+	return 1;
+}

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2008-09-05 15:18:15 UTC (rev 3566)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2008-09-05 18:20:57 UTC (rev 3567)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek at assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License v2 as published by
@@ -116,6 +116,8 @@
 	}
 }
 
+static void southbridge_init_common(struct device *dev);
+
 /** Set up PCI IRQ routing, route everything through APIC. */
 static void pci_routing_fixup(struct device *dev)
 {
@@ -173,6 +175,7 @@
 
 	/* 7 = stp to sust delay 1msec
 	 * 6 = SUSST# Deasserted Before PWRGD for STD
+	 * 4 = PWRGOOD reset on VT8237A/S
 	 * 3 = GPO26/GPO27 is GPO 
 	 * 2 = Disable Alert on Lan
 	 */
@@ -181,14 +184,6 @@
 	/* Disable GP3 timer. */
 	pci_write_config8(dev, 0x98, 0);
 
-	/* Enable SATA LED, disable special CPU Frequency Change -
-	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
-	 */
-	pci_write_config8(dev, 0xe5, 0x9);
-
-	/* REQ5 as PCI request input - should be together with INTE-INTH. */
-	pci_write_config8(dev, 0xe4, 0x4);
-
 	/* Enable ACPI accessm RTC signal gated with PSON. */
 	pci_write_config8(dev, 0x81, 0x84);
 
@@ -222,6 +217,30 @@
 	/* SCI is generated for RTC/pwrBtn/slpBtn. */
 	outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
 
+}
+
+
+static void vt8237r_init(struct device *dev) {
+	u8 enables;
+
+	/* Enable SATA LED, disable special CPU Frequency Change -
+	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 */
+	pci_write_config8(dev, 0xe5, 0x9);
+
+	/* REQ5 as PCI request input - should be together with INTE-INTH. */
+	pci_write_config8(dev, 0xe4, 0x4);
+
+	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
+	enables = pci_read_config8(dev, 0x4f);
+	enables |= 0x08;
+	pci_write_config8(dev, 0x4f, enables);
+
+	/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */
+	pci_write_config8(dev, 0x48, 0x8c);
+
+	southbridge_init_common(dev);
+
 	/* FIXME: Intel needs more bit set for C2/C3. */
 
 	/* Allow SLP# signal to assert LDTSTOP_L.
@@ -230,8 +249,45 @@
 	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
 }
 
-static void vt8237r_init(struct device *dev)
+static void vt8237s_init(struct device *dev)
 {
+	u32 tmp;
+	
+	/* put SPI base VT8237S_SPI_MEM_BASE */
+	tmp = pci_read_config32(dev, 0xbc);
+	pci_write_config32(dev, 0xbc, (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
+
+	/* Enable SATA LED, VR timer = 100us, VR timer should be fixed */
+	
+	pci_write_config8(dev, 0xe5, 0x69);
+
+	/* REQ5 as PCI request input - should be together with INTE-INTH. 
+	 * Fast VR timer disable - need for LDTSTOP_L signal
+	*/
+	pci_write_config8(dev, 0xe4, 0xa5);
+
+	/* reduce further the STPCLK/LDTSTP signal to 5us */
+
+	pci_write_config8(dev, 0xec, 0x4);
+
+	/* Host Bus Power Management Control, maybe not needed */
+	pci_write_config8(dev, 0x8c, 0x5);
+
+	/* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R */
+	pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+
+	southbridge_init_common(dev);
+	
+	/* FIXME: Intel needs more bit set for C2/C3. */
+
+	/* Allow SLP# signal to assert LDTSTOP_L.
+	 * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2
+	 */
+	outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
+	dump_south(dev);
+}
+static void vt8237_common_init(struct device *dev)
+{
 	u8 enables, byte;
 
 	/* Enable addr/data stepping. */
@@ -275,7 +331,7 @@
 	/* Delay transaction control */
 	pci_write_config8(dev, 0x43, 0xb);
 
-	/* I/O recovery time */
+	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x44);
 
 	/* ROM memory cycles go to LPC. */
@@ -288,25 +344,14 @@
 	 *     bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
 	 *   0 Dynamic Clock Gating Main Switch (1=Enable)
 	 */
-	pci_write_config8(dev, 0x5b, 0x9);
+	pci_write_config8(dev, 0x5b, 0xb);
 
-	/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */
-	pci_write_config8(dev, 0x48, 0x8c);
-
 	/* Set 0x58 to 0x43 APIC and RTC. */
 	pci_write_config8(dev, 0x58, 0x43);
 
-	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
-
 	/* Enable serial IRQ, 6PCI clocks. */
 	pci_write_config8(dev, 0x52, 0x9);
 
-	/* Enable HPET at VT8237R_HPET_ADDR. */
-	pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
-
 	/* Power management setup */
 	setup_pm(dev);
 
@@ -348,25 +393,40 @@
 		init_pc_keyboard(0x60, 0x64, 0);
 }
 
-static void southbridge_init(struct device *dev)
+static void southbridge_init_common(struct device *dev)
 {
-	vt8237r_init(dev);
+	vt8237_common_init(dev);
 	pci_routing_fixup(dev);
 	setup_ioapic(VT8237R_APIC_BASE);
 	setup_i8259();
 	init_keyboard(dev);
 }
 
-static const struct device_operations vt8237r_lpc_ops = {
+static const struct device_operations vt8237r_lpc_ops_s = {
 	.read_resources		= vt8237r_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= vt8237r_enable_resources,
-	.init			= &southbridge_init,
+	.init			= &vt8237s_init,
 	.scan_bus		= scan_static_bus,
 };
 
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops	= &vt8237r_lpc_ops,
+
+static const struct device_operations vt8237r_lpc_ops_r = {
+	.read_resources		= vt8237r_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= vt8237r_enable_resources,
+	.init			= &vt8237r_init,
+	.scan_bus		= scan_static_bus,
+};
+
+static const struct pci_driver lpc_driver_r __pci_driver = {
+	.ops	= &vt8237r_lpc_ops_r,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_VT8237R_LPC,
 };
+
+static const struct pci_driver lpc_driver_s __pci_driver = {
+	.ops	= &vt8237r_lpc_ops_s,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT8237S_LPC,
+};

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_sata.c	2008-09-05 15:18:15 UTC (rev 3566)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_sata.c	2008-09-05 18:20:57 UTC (rev 3567)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek at assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License v2 as published by
@@ -24,7 +24,7 @@
 
 #define SATA_MISC_CTRL 0x45
 
-static void sata_init(struct device *dev)
+static void sata_i_init(struct device *dev)
 {
 	u8 reg;
 
@@ -39,19 +39,82 @@
 	pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1);
 	reg |= 0x80;		/* Sub Class Write Protect on */
 	pci_write_config8(dev, SATA_MISC_CTRL, reg);
+	
+	return;
 }
 
-static const struct device_operations sata_ops = {
+static void sata_ii_init(struct device *dev) {
+	u8 reg;
+
+	sata_i_init(dev);
+	
+	/* analog black magic, you may or may not need to adjust 0x60-0x6f, depends on PCB */
+	
+	/* Analog PHY - gen1
+	 * CDR bandwidth [6:5] = 3
+	 * Squelch Window Select [4:3] = 1
+	 * CDR Charge Pump [2:0] = 1
+	 */
+	 
+	pci_write_config8(dev, 0x64, 0x49);
+	
+	/* adjust driver current source value to 9 */
+	reg = pci_read_config8(dev, 0x65);
+	reg &= 0xf0;
+	reg |= 0x9;
+	pci_write_config8(dev, 0x65, reg);
+	
+	/* set all manual termination 50ohm bits [2:0] and enable [4] */
+	reg = pci_read_config8(dev, 0x6a);
+	reg |= 0xf;
+	pci_write_config8(dev, 0x6a, reg);
+
+	/* Analog PHY - gen2
+	 * CDR bandwidth [5:4] = 2
+	 * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e
+	 * CDR Charge Pump [2:0] = 1
+	 */
+
+	reg = pci_read_config8(dev, 0x6f);
+	reg &= 0x08;
+	reg |= 0x61;
+	pci_write_config8(dev, 0x6f, reg);
+
+	/* check if staggered spinup is supported */
+	reg = pci_read_config8(dev, 0x83);
+	if ((reg & 0x8) == 0) {
+		/* start OOB sequence on both drives */
+		reg |= 0x30;
+		pci_write_config8(dev, 0x83, reg);
+	}
+}
+
+static const struct device_operations sata_i_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= sata_init,
+	.init			= sata_i_init,
 	.enable			= 0,
 	.ops_pci		= 0,
 };
 
-static const struct pci_driver northbridge_driver __pci_driver = {
-	.ops	= &sata_ops,
+static const struct device_operations sata_ii_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= sata_ii_init,
+	.enable			= 0,
+	.ops_pci		= 0,
+};
+
+static const struct pci_driver northbridge_driver_ii __pci_driver = {
+	.ops	= &sata_ii_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_VT8237_SATA,
+};
+
+static const struct pci_driver northbridge_driver_i __pci_driver = {
+	.ops	= &sata_i_ops,
+	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_VT6420_SATA,
 };




From r.marek at assembler.cz  Fri Sep  5 20:21:42 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 05 Sep 2008 20:21:42 +0200
Subject: [coreboot] [PATCH] Add VIA VT8237S support
In-Reply-To: <48C09771.9010000@onelabs.com>
References: <48C065B9.6020605@assembler.cz> <48C09771.9010000@onelabs.com>
Message-ID: <48C178B6.6060006@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

As Committed revision 3567.

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iD8DBQFIwXi23J9wPJqZRNURApD2AJwN9JUtVqqf//pJPEYsLINkKyL1OwCg2ugQ
4eEH8zNcUDw4WfF6slP/x7Q=
=q0ER
-----END PGP SIGNATURE-----



From info at coresystems.de  Fri Sep  5 21:13:22 2008
From: info at coresystems.de (coreboot information)
Date: Fri, 05 Sep 2008 21:13:22 +0200
Subject: [coreboot] r3567 build service
Message-ID: <E1KbgkE-00055y-DH@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "ruik" checked in revision 3567 to
the coreboot source repository and caused the following 
changes:

Change Log:
This patch adds support for the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested
on mine desktop) except of reverting the small change introduced by Bari
(gpio/inta setup reg 0x5b). This should go for some board specific file. The
change would broke at least mine board. But seems to be needed for jakllsch.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Bari Ari <bari at onelabs.com>



Build Log:
Compilation of via:epia-cn has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3567&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in ruik's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From joe at settoplinux.org  Fri Sep  5 21:17:55 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 05 Sep 2008 15:17:55 -0400
Subject: [coreboot] was: wiki account request (for GRUB 2) - now: FILO
 integration into libpayload
In-Reply-To: <5f0fccd1f2db3f42764fe11de1ed1939@imap.1and1.com>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
	<102a5694a717575e13c04245c84a818f@imap.1and1.com>
	<48C16235.7020707@coresystems.de>
	<522432352237bd8ca4d0a0fa9d2b22f4@imap.1and1.com>
	<48C16999.6040109@coresystems.de>
	<5f0fccd1f2db3f42764fe11de1ed1939@imap.1and1.com>
Message-ID: <32d0a575f02cdbf46ac582bb5a3e988c@imap.1and1.com>




On Fri, 05 Sep 2008 13:39:18 -0400, Joseph Smith <joe at settoplinux.org>
wrote:
> 
> 
> 
> On Fri, 05 Sep 2008 19:17:13 +0200, Stefan Reinauer
> <stepan at coresystems.de>
> wrote:
>> Joseph Smith wrote:
>>>> FILO might become just the main loop calling libpayload functions and
>>>> painting a nice menu
>>> Do you mean integrating FILO into libpayload or will the FILO main()
>> still
>>> be seperate code?
>>>
>> No, it will always stay seperate code.
>>
>>> I like the "painting a nice menu" part. Maybe with a pretty coreboot
>> logo
>>> too...
>>>
>>
>>> While we are on the subject, I was also thinking about how hard would
> it
>> be
>>> to allocate a small part of flash as a read/write user area for saving
>> boot
>>> options?
>>>
>> With flashrom ported to libpayload it should be quite reasonable.
>>
>> If nvram (256 bytes of cmos) are enough, you can have that right away..
>> FILO 0.6 has an option to read the default menu entry from cmos, and it
>> can be set/changed with nvramtool.
>>
> Cool I did not know that, is it documented on the wiki somewhere?
>
Looks like the nvram page on the wiki says:

Some of the fields are used by payloads - for instance all the fields that
start with 'boot_' in the list above. FILO does not use those fields
currently, but Etherboot does (someone confirm this please!). 


Does this need to be updated?? Has it been confirmed??

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From vincent.legoll at gmail.com  Fri Sep  5 22:21:02 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Fri, 5 Sep 2008 22:21:02 +0200
Subject: [coreboot] Kernel hang solid
In-Reply-To: <4727185d0809050238g8aa8694u1f88b86fffc27885@mail.gmail.com>
References: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
	<2ea3fae10809042003i3c450fbewb70bca920f9711aa@mail.gmail.com>
	<4727185d0809050238g8aa8694u1f88b86fffc27885@mail.gmail.com>
Message-ID: <4727185d0809051321l5f2d1566q84b3ab96ce293d00@mail.gmail.com>

On Fri, Sep 5, 2008 at 11:38 AM, Vincent Legoll
<vincent.legoll at gmail.com> wrote:
> On Fri, Sep 5, 2008 at 5:03 AM, yhlu <yinghailu at gmail.com> wrote:
>> does previous kernel work? like 2.6.24
>
> I've not tried a kernel that old, but I will.
>
> I've tried vanilla -git for last few days only.

Tested 2.6.{23,24,25} they all hang the same way at the same place:
the first console_initcall() (which I don't know if it is the serial one or
the vga one)

Anyone can explain the strange things (at least strange to me) in
linux_coreboot.txt ? (attached to 1st post in thread)

-- 
Vincent Legoll



From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 22:22:33 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 22:22:33 +0200
Subject: [coreboot] current dtc patch
In-Reply-To: <13426df10809040904x21350debo69777bd41cf567dc@mail.gmail.com>
References: <13426df10809040904x21350debo69777bd41cf567dc@mail.gmail.com>
Message-ID: <48C19509.9040908@gmx.net>

On 04.09.2008 18:04, ron minnich wrote:
> no ack in it, for your viewing pleasure.
>
> Tested on dbe62.
>   

Looks nice.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Ron, I trust you to make the right choice. You select the patch (yours
or mine) and commit it. I have almost no experience with dtc and
although I think I understand the simple parts of the device model, your
experience trumps mine in any case. (I don't have any emotional
attachment to my patch, it was born out of need.)

Oh, and any of your current and future dtc/dts changes for uniqueness,
collision avoidance and multiple links have my carte blanche. Feel free
to apply it anywhere if compile tested on qemu, geodelx and k8.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Fri Sep  5 22:39:47 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 05 Sep 2008 22:39:47 +0200
Subject: [coreboot] current dtc patch
In-Reply-To: <48C19509.9040908@gmx.net>
References: <13426df10809040904x21350debo69777bd41cf567dc@mail.gmail.com>
	<48C19509.9040908@gmx.net>
Message-ID: <48C19913.907@gmx.net>

On 05.09.2008 22:22, Carl-Daniel Hailfinger wrote:
> On 04.09.2008 18:04, ron minnich wrote:
>   
>> no ack in it, for your viewing pleasure.
>>
>> Tested on dbe62.
>>   
>>     
>
> Looks nice.
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

It exploded with the current dts of the AMD Serengeti, though, and
produced this statictree.c excerpt:
> struct device dev_ioport_2e = {
>         .path = {{.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x2e}}},
One opening bracket too many.

>         .device_configuration = &ioport_2e,
>         .next = &dev_domain_0,
>         .links = 0,
>         .bus = &dev_domain_0.link[0],
>         .next = &dev_domain_0,
>         .dtsname = "ioport_2e",
>         .enabled = 1
> };

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Fri Sep  5 22:45:46 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 13:45:46 -0700
Subject: [coreboot] current dtc patch
In-Reply-To: <48C19913.907@gmx.net>
References: <13426df10809040904x21350debo69777bd41cf567dc@mail.gmail.com>
	<48C19509.9040908@gmx.net> <48C19913.907@gmx.net>
Message-ID: <13426df10809051345w182235c8g8ad3a165d2f3d654@mail.gmail.com>

On Fri, Sep 5, 2008 at 1:39 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 05.09.2008 22:22, Carl-Daniel Hailfinger wrote:
>> On 04.09.2008 18:04, ron minnich wrote:
>>
>>> no ack in it, for your viewing pleasure.
>>>
>>> Tested on dbe62.
>>>
>>>
>>
>> Looks nice.
>> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>
>
> It exploded with the current dts of the AMD Serengeti, though, and
> produced this statictree.c excerpt:
>> struct device dev_ioport_2e = {
>>         .path = {{.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x2e}}},
> One opening bracket too many.
>
>>         .device_configuration = &ioport_2e,
>>         .next = &dev_domain_0,
>>         .links = 0,
>>         .bus = &dev_domain_0.link[0],
>>         .next = &dev_domain_0,
>>         .dtsname = "ioport_2e",
>>         .enabled = 1
>> };
>
> Regards,
> Carl-Daniel
>
> --
> http://www.hailfinger.org/
>
>

yeah my bad I fixed that.

ron



From jordan at chalmers.se  Fri Sep  5 23:01:17 2008
From: jordan at chalmers.se (Ulf Jordan)
Date: Fri, 5 Sep 2008 23:01:17 +0200 (CEST)
Subject: [coreboot] [PATCH] libpayload: editing keys for serial curses
Message-ID: <Pine.LNX.4.63.0809052249460.30936@elfpc10.elmagn.chalmers.se>

The attached patch adds editing keys and the missing F11 key to 
curses serial input cooking. This brings serial and local keyboard better 
in line with each other.

Compile and runtime tested with coreinfo+libpayload+coreboot-v3 under 
QEMU.

/ulf
-------------- next part --------------
Add editing keypad keys and the missing F11 key to the curses serial
input cooking table.

Signed-off-by: Ulf Jordan <jordan at chalmers.se>

Index: libpayload/curses/keyboard.c
===================================================================
--- libpayload/curses/keyboard.c	(revision 3567)
+++ libpayload/curses/keyboard.c	(arbetskopia)
@@ -73,6 +73,12 @@
 	{ "[B", KEY_DOWN },
 	{ "[C", KEY_RIGHT },
 	{ "[D", KEY_LEFT },
+	{ "[F", KEY_END },
+	{ "[H", KEY_HOME },
+	{ "[2~", KEY_IC },
+	{ "[3~", KEY_DC },
+	{ "[5~", KEY_PPAGE },
+	{ "[6~", KEY_NPAGE },
 	{ "OP", KEY_F(1) },
 	{ "OQ", KEY_F(2) },
 	{ "OR", KEY_F(3) },
@@ -83,6 +89,7 @@
 	{ "[19~", KEY_F(8) },
 	{ "[20~", KEY_F(9) },
 	{ "[21~", KEY_F(10) },
+	{ "[23~", KEY_F(11) },
 	{ "[24~", KEY_F(12) },
 	{ NULL },
 };

From daniel-coreboot at lindenaar.eu  Fri Sep  5 23:03:30 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Fri, 05 Sep 2008 23:03:30 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <20080905121359.154557oo2wfn0jnk@www.lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>	<48C0512E.9050104@lindenaar.eu>
	<48C0560C.9040500@coresystems.de>
	<20080905121359.154557oo2wfn0jnk@www.lindenaar.eu>
Message-ID: <48C19EA2.9060300@lindenaar.eu>

Hi Guys,
Some progress... I now get the following log:

coreboot-2.0.0.0Fallback Fri Sep  5 22:02:42 UTC 2008 starting...
test spew
test err
passed bist failure
entering enable_mainboard_devices
pci_loc_dev 1106:0686
....
exiting enable_motherboard_devsvt8601 init starting
00000000 is the north1106 0601
0120smbus_error: 04
Device Error
smbus_error: 04
Device Error
smbus_error: 04
Device Error
84 is the computed timingNOP
PRECHARGE
DUMMY READS
CBR
MRS
NORMAL
set ref. rate
enable multi-page open
Slot 00smbus_error: 04
Device Error
 is empty
Slot 01smbus_error: 04
Device Error
 is empty
Slot 02smbus_error: 04
Device Error
 is empty
Slot 03smbus_error: 04
Device Error
 is empty
vt8601 done
Copying coreboot to RAM.
Jumping to coreboot.


Seems the SMBus is not yet working fully. Any suggestions?

btw. there was the wrong PCI device set up for SMBus functionality :/ 
sloppy...

Another question: Is it normal that the booted coreboot is the 
.0Fallback one?

regards,
Daniel



From rminnich at gmail.com  Fri Sep  5 23:05:29 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 14:05:29 -0700
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C19EA2.9060300@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>
	<20080904175524.854556r78he2jzls@www.lindenaar.eu>
	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>
	<48C02940.7040600@lindenaar.eu>
	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>
	<48C0512E.9050104@lindenaar.eu> <48C0560C.9040500@coresystems.de>
	<20080905121359.154557oo2wfn0jnk@www.lindenaar.eu>
	<48C19EA2.9060300@lindenaar.eu>
Message-ID: <13426df10809051405scf5c49dh735f50bc5ccb3b01@mail.gmail.com>

Now it's time to look for an smbus mux ...

ron



From svn at coreboot.org  Fri Sep  5 23:23:02 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  5 Sep 2008 23:23:02 +0200
Subject: [coreboot] r3568 - trunk/payloads/libpayload/curses
Message-ID: <mailman.2033.1355071375.16123.coreboot@coreboot.org>

Author: jcrouse
Date: 2008-09-05 23:23:02 +0200 (Fri, 05 Sep 2008)
New Revision: 3568

Modified:
   trunk/payloads/libpayload/curses/keyboard.c
Log:
Add editing keypad keys and the missing F11 key to the curses serial
input cooking table.

Signed-off-by: Ulf Jordan <jordan at chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>


Modified: trunk/payloads/libpayload/curses/keyboard.c
===================================================================
--- trunk/payloads/libpayload/curses/keyboard.c	2008-09-05 18:20:57 UTC (rev 3567)
+++ trunk/payloads/libpayload/curses/keyboard.c	2008-09-05 21:23:02 UTC (rev 3568)
@@ -73,6 +73,12 @@
 	{ "[B", KEY_DOWN },
 	{ "[C", KEY_RIGHT },
 	{ "[D", KEY_LEFT },
+	{ "[F", KEY_END },
+	{ "[H", KEY_HOME },
+	{ "[2~", KEY_IC },
+	{ "[3~", KEY_DC },
+	{ "[5~", KEY_PPAGE },
+	{ "[6~", KEY_NPAGE },
 	{ "OP", KEY_F(1) },
 	{ "OQ", KEY_F(2) },
 	{ "OR", KEY_F(3) },
@@ -83,6 +89,7 @@
 	{ "[19~", KEY_F(8) },
 	{ "[20~", KEY_F(9) },
 	{ "[21~", KEY_F(10) },
+	{ "[23~", KEY_F(11) },
 	{ "[24~", KEY_F(12) },
 	{ NULL },
 };




From jordan.crouse at amd.com  Fri Sep  5 23:23:51 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 5 Sep 2008 15:23:51 -0600
Subject: [coreboot] libpayload: editing keys for serial curses
In-Reply-To: <Pine.LNX.4.63.0809052249460.30936@elfpc10.elmagn.chalmers.se>
References: <Pine.LNX.4.63.0809052249460.30936@elfpc10.elmagn.chalmers.se>
Message-ID: <20080905212351.GC18550@cosmic.amd.com>

On 05/09/08 23:01 +0200, Ulf Jordan wrote:
> The attached patch adds editing keys and the missing F11 key to 
> curses serial input cooking. This brings serial and local keyboard better 
> in line with each other.
> 
> Compile and runtime tested with coreinfo+libpayload+coreboot-v3 under 
> QEMU.
> 
> /ulf

> Add editing keypad keys and the missing F11 key to the curses serial
> input cooking table.
> 
> Signed-off-by: Ulf Jordan <jordan at chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>

3568.  Thanks

> Index: libpayload/curses/keyboard.c
> ===================================================================
> --- libpayload/curses/keyboard.c	(revision 3567)
> +++ libpayload/curses/keyboard.c	(arbetskopia)
> @@ -73,6 +73,12 @@
>  	{ "[B", KEY_DOWN },
>  	{ "[C", KEY_RIGHT },
>  	{ "[D", KEY_LEFT },
> +	{ "[F", KEY_END },
> +	{ "[H", KEY_HOME },
> +	{ "[2~", KEY_IC },
> +	{ "[3~", KEY_DC },
> +	{ "[5~", KEY_PPAGE },
> +	{ "[6~", KEY_NPAGE },
>  	{ "OP", KEY_F(1) },
>  	{ "OQ", KEY_F(2) },
>  	{ "OR", KEY_F(3) },
> @@ -83,6 +89,7 @@
>  	{ "[19~", KEY_F(8) },
>  	{ "[20~", KEY_F(9) },
>  	{ "[21~", KEY_F(10) },
> +	{ "[23~", KEY_F(11) },
>  	{ "[24~", KEY_F(12) },
>  	{ NULL },
>  };

> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From daniel-coreboot at lindenaar.eu  Fri Sep  5 23:29:06 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Fri, 05 Sep 2008 23:29:06 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <13426df10809051405scf5c49dh735f50bc5ccb3b01@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>	<48C0512E.9050104@lindenaar.eu>
	<48C0560C.9040500@coresystems.de>	<20080905121359.154557oo2wfn0jnk@www.lindenaar.eu>	<48C19EA2.9060300@lindenaar.eu>
	<13426df10809051405scf5c49dh735f50bc5ccb3b01@mail.gmail.com>
Message-ID: <48C1A4A2.6010404@lindenaar.eu>

Sounds great...but... how do I go about this???

regards,
 Daniel

ron minnich wrote:
> Now it's time to look for an smbus mux ...
>
> ron
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>   




From rmh at aybabtu.com  Fri Sep  5 23:35:02 2008
From: rmh at aybabtu.com (Robert Millan)
Date: Fri, 5 Sep 2008 23:35:02 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905154229.GD31555@cosmic.amd.com>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
Message-ID: <20080905213502.GA31582@thorin>

On Fri, Sep 05, 2008 at 09:42:29AM -0600, Jordan Crouse wrote:
> On 05/09/08 17:08 +0200, Robert Millan wrote:
> > 
> > Hi,
> > 
> > I notice in http://tracker.coreboot.org/trac/coreboot/ticket/88 that
> > Coresystems is no longer working on GRUB 2 (that's too bad, sorry that
> > it didn't work out, etc...).
> > 
> > I have nothing to say about what you will be recommending as default bootloader
> > in the future.  Right now your wiki still recommends GRUB 2, and I suppose
> > Coresystems folks will want to push for FILO.  But this is not a discussion
> > I want to be involved in (just wanted to clarify ;-)).
> 
> Coresystems has people that depend on them for a livelyhood - they have to
> do what is best for their customers, and we are very lucky that their goals
> often align with those of the community.   I do wish things had ended up
> differently, but I welcome the FILO work because it make both FILO and
> libpayload that much better, and thats not a bad thing.

I understand.  I didn't mean to say it is!

> When you anoint a single program as the "chosen one" then you lock yourself
> for trouble down the road.  I would much prefer to chose between 3 great
> programs then one mediocre one.

It seems I made too many assumptions; sorry about that.  Let me put it as:
whatever you choose to endorse or recommend is not my problem.  I just want
to make GRUB provide good support for coreboot, and (to the extent that this
is reasonable) that users can find readily available information about it when
browsing your list of supported payloads.

-- 
Robert Millan

  The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
  how) you may access your data; but nobody's threatening your freedom: we
  still allow you to remove your data and not access it at all."



From rmh at aybabtu.com  Sat Sep  6 00:02:09 2008
From: rmh at aybabtu.com (Robert Millan)
Date: Sat, 6 Sep 2008 00:02:09 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <48C155D3.7010900@coresystems.de>
References: <20080905150817.GA11396@thorin> <48C155D3.7010900@coresystems.de>
Message-ID: <20080905220209.GB31582@thorin>

On Fri, Sep 05, 2008 at 05:52:51PM +0200, Stefan Reinauer wrote:
> Robert Millan wrote:
> > I have nothing to say about what you will be recommending as default bootloader
> > in the future.  Right now your wiki still recommends GRUB 2, and I suppose
> > Coresystems folks will want to push for FILO.  But this is not a discussion
> > I want to be involved in (just wanted to clarify ;-)).
> >   
> We've not been pushing any "default bootloader" in the past, nor will we
> do so in the future.
> I believe coreboot is about freedom and choice. And about making stuff
> that people can actually use.
> Now, this last criteria is different for a multitude of use cases.

Ok, understood.  Thanks for the clarification.  Anyway, I just wanted to make
it clear that it's not my bussiness if you decide to endorse or recommend
something else.  My goal is to improve GRUB and its associated documentation
& support, and that's it.

> > What I'm concerned about is that http://www.coreboot.org/GRUB2 in the wiki
> > currently points to a branch of GRUB that is (unless I missed something)
> > no longer being maintained.  And it provides information that will, over time,
> > become more and more obsolete.  I'm worried that this can reflect bad on the
> > image of GRUB.
> >   
> I wonder whether we need to keep our own GRUB2 page at all, since
> there's a coreboot page in the GRUB2 wiki already and if things go as
> you suggest, one of them will eventually be a copy of the other one.

Or perhaps in long-term one of them could become a stub for the other?  I'll
talk about this with Marco and the other GRUB developers too.  Anyway, in short
term I'd like to put there a summary of GRUB status from coreboot perspective,
including:

  - The info which is currently in http://grub.enbug.org/CoreBoot

  - References to information about other areas indirectly related to coreboot
    (such as USB support).

  - A reference to the Coresystems branch, highlighting the extra features,
    in case someone is interested.

Seeing that you approved my account request, if there are no objections I'll
proceed to prepare an edit for that page.

> > So what I'd like is permission to keep it up to date, and reflect the current
> > state of GRUB mainline.  If you would give me a wiki account to do that, it'd
> > be much appreciated.
> >   
> 
> Use ist wisely. And please create User:RobertMillan so people know who
> you are.

Thank you.  I will.

-- 
Robert Millan

  The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
  how) you may access your data; but nobody's threatening your freedom: we
  still allow you to remove your data and not access it at all."



From info at coresystems.de  Sat Sep  6 00:14:37 2008
From: info at coresystems.de (coreboot information)
Date: Sat, 06 Sep 2008 00:14:37 +0200
Subject: [coreboot] r3568 build service
Message-ID: <E1KbjZd-0007G4-Vd@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "jcrouse" checked in revision 3568 to
the coreboot source repository and caused the following 
changes:

Change Log:
Add editing keypad keys and the missing F11 key to the curses serial
input cooking table.

Signed-off-by: Ulf Jordan <jordan at chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse at amd.com>


Build Log:
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3568&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in jcrouse's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rmh at aybabtu.com  Sat Sep  6 00:18:35 2008
From: rmh at aybabtu.com (Robert Millan)
Date: Sat, 6 Sep 2008 00:18:35 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <48C15A04.60005@gmx.net>
References: <20080905150817.GA11396@thorin> <48C15A04.60005@gmx.net>
Message-ID: <20080905221835.GC31582@thorin>

On Fri, Sep 05, 2008 at 06:10:44PM +0200, Carl-Daniel Hailfinger wrote:
> 
> The most interesting question is why these GRUB patches were not merged
> upstream. If any, that may reflect badly on the image of GRUB.

I won't argue against your preconception that this is GRUB's fault, mainly
because this is a thing of the past, and I believe both sides have agreed
to move on, but also because my perspective is probably biased.

To answer your question, suffice to say that the FSF and Coresystems didn't
agree on the legal framework to be used for the contributions, because of
a variety of reasons which I don't even know in detail.  Therefore both sides
exercised their legitimate right not to engage in collaboration under terms
that weren't suitable for them.

If I expressed any opinion about this before, it is a mistake, and I now
reserve my opinion for myself.  I don't represent the FSF, and the only thing
I care right now is to make GRUB as good as possible so that coreboot users
may find coreboot/GRUB a suitable combination.

-- 
Robert Millan

  The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
  how) you may access your data; but nobody's threatening your freedom: we
  still allow you to remove your data and not access it at all."



From jackiepan93 at gmail.com  Sat Sep  6 01:08:35 2008
From: jackiepan93 at gmail.com (Jackie Pan)
Date: Sat, 6 Sep 2008 07:08:35 +0800
Subject: [coreboot] Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <48C14E0A.2070304@coresystems.de>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>
	<48C0FF74.6070608@gmx.net>
	<8012472D-CBBA-451C-A009-D7931A33D458@coresystems.de>
	<48C14D30.5090700@gmx.net> <48C14E0A.2070304@coresystems.de>
Message-ID: <3c66930d0809051608y557b2e68j8f9e56336d463516@mail.gmail.com>

2008/9/5 Stefan Reinauer <stepan at coresystems.de>

> Carl-Daniel Hailfinger wrote:
> > On 05.09.2008 12:54, Stefan Reinauer wrote:
> >
> >
> >> On 05.09.2008 09:45, Jackie Pan wrote:
> >>
> >>> if it's possible to place code into cache-emulated RAM
> >>>
> >> Core 2 Duo can do cache for ram and code... But it works well enough
> >> to just set an mtrr to make rom cacheable during car and that also
> >> works for older intel CPUs
> >>
> >
> > We're talking about different things.
> > Jackie was talking about executing code stored inside the pseudo-RAM CAR
> > area. I was talking about that as well.
> > Stefan wrote about using cache for code outside the CAR area.
> >
> No, not at all different things. As I said, the Core 2 Duo can execute
> code stored in CAR.
>
>
>
> --
> coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
>      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
> Email: info at coresystems.de  ? http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg ? HRB 7656
> Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866
>
> Hi Stefan,
I'm very curious about how you achieve this. As Intel's separate L1 data
cache and instruction cache,after checking the prog. manual I come to the
conclusion that the i-cache can only be filled by instruction fetching
process(or am i wrong?), when I copy code into the CAR region(i.e., not by
caching of the XIP region using MTRR),
the data I supplied goes directly into the d-cache, at the same time the
corresponding line in the i-cache(if any) gets
invalidated immediately, or more exactly for the CAR case, there's no such
line in the i-cache at all because there's
not been any instruction fetching targeting at the CAR region before. Thus
it seems impossible to synchronize the
i-cache and d-cache without a RAM as backup.

let me guess, are you implying storing  to another core's cache while using
MESI for the purpose of synchronizing?
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From mats.andersson at gisladisker.se  Sat Sep  6 01:31:01 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Sat, 06 Sep 2008 01:31:01 +0200
Subject: [coreboot] v2: Detection of sdram densities.
In-Reply-To: <4e1cf4153f7e400c12d91ffdf64bd5e5@imap.1and1.com>
Message-ID: <E1KbklZ-0007r9-Qt@aun.bellman.mea>

Hello all,

to round off this thread, I must agree with you on the confusing
terminology for SDRAM modules/devices/cards. Until Monday
this week I thought that an SDRAM-card consisted of one or
two memory banks, depending on the number of physically
populated sides of the memory carrier. Then I began
studying Intel's publication

    PC SDRAM Serial Presence Detect (SPD) Specification

and all the expected terms were turned around, and it was
with that phrasing my original question was posed. Both of
you, Joseph and Corey, quickly caught this, and thus resolved
my dilemma. 

I am porting Uwe Hammer's code for msi/ms6119 to the similar
setting msi/6147, and at the moment it is an accurate SDRAM
detection that keeps me occupied. Uwe Hammer's code is  tied
down by a handful presumptions on the amount of present SDRAM.
My detection works, but elfboot dislikes the result so far!

Best regards for now,

Mats E Andersson


On Fri, 05 Sep 2008 17:54:59 +0200, Joseph Smith <joe at settoplinux.org> wrote
>On Fri, 5 Sep 2008 10:39:02 -0400, "Corey Osgood" <corey.osgood at gmail.com>
>wrote:
>> On Fri, Sep 5, 2008 at 8:09 AM, Joseph Smith <joe at settoplinux.org> wrote:
>>>
>>>
>>>
>>> On Thu, 4 Sep 2008 23:27:50 -0400, "Corey Osgood"
>> <corey.osgood at gmail.com>
>>> wrote:
>>>> On Wed, Sep 3, 2008 at 1:26 PM, Mats Erik Andersson
>>>> <mats.andersson at gisladisker.se> wrote:
>>>>>
>>>>> Hello again,
>>>>>
>>>>> I have been experimenting with an algorithm to detect
>>>>> and register with the northbridge i440bx the correct
>>>>> amount of sdram present. A C-coded version is appended
>>>>> to this message. Feel free to comment on the method.
>>>>>
>>>>> In the actually working code, I had to split the
>>>>> algorithm into a lower and an upper part, in order
>>>>> not to run out of internal registers under romcc,
>>>>> but the idea remains the same.
>>>>>
>>>>> Since there are also some later stages where I have
>>>>> not understood how the previous author hard coded
>>>>> a single 64MB bank,  I presently achieve a running
>>>>> system only when I dynamically detect a distribution
>>>>> identical to what was earlier hard coded.
>>>>>
>>>>> My detection works with any combination of 0MB and
>>>>> 64MB in two rows for DIMM0 and DIMM1.
>>>>>
>>>>> Question: In case an sdram device has rows of mixed
>>>>> sizes, can one depend on the larger density being
>>>>> in row zero, and the smaller content in row one?
>>>>
>>>> Yes. The spd spec assumes the larger row will be row 0, any stick that
>>>> didn't wouldn't follow the standard. At least, that was my
>>>> understanding of it.
>>>>
>>> This can get a little confusing, when you are talking about rows, do you
>>> mean banks? Or actuall sdram slots?
>> 
>> Banks, I assume, all this terminology gets me confuseded. I'm pretty
>> sure Mats was talking about each side of the slot/ram pcb.
>> 
>>> As far as it goes with rows/banks, most intel boards only support
>>> asymmetrical sdrams so if the dimm has two sides the second side has to
>>> equal the first side.
>> 
>> You mean "only support symmetrical sdrams". IIRC, i810 supports
>> asymmetrical dimms, but I can't remember...
>> 
>> -Corey
>> 
>>> As far as sdram slots any combination should work as
>>> long as it follows the the northbridge criteria. You can look at the
>> i830
>>> raminit.c, it has a pretty clever way to detect dimms, and it works
>> every
>>> time no matter what the combination. By the way Uwe was the original
>> author
>>> of the i440bx code. Hope that helps.
>>>
>Right, symmetrical sdrams, sorry for the slip of toung. And yes to Mat's
>question, in the case of a asymmetrical dual-sided DIMM the first side will
>always be larger. But that should not matter, if your code is calculating
>on a per side/bank basis, I mean it should be able to detect the size of
>each side/bank, and if it is dual-sided, and add the two sides/banks
>togethor to give you the total size. As far as initailization goes, each
>side/bank needs to initalized seperatly... that's where it can get a little
>tricky. That's also why it is important to calculate memory on a per
>side/bank basis....
>Hope that helps.
>



From c-d.hailfinger.devel.2006 at gmx.net  Sat Sep  6 01:35:22 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Sep 2008 01:35:22 +0200
Subject: [coreboot] [flashrom] RE:  Tyan Product Listings
In-Reply-To: <62331AE06C95A144869EEB7EB2F8BE675CC4A5@MUSAEXVS01.mitacad.com>
References: <62331AE06C95A144869EEB7EB2F8BE675CC3BA@MUSAEXVS01.mitacad.com>
	<200808271415.m7REFAf0015817@hyspamsql01.mic.com.tw>
	<62331AE06C95A144869EEB7EB2F8BE675CC4A5@MUSAEXVS01.mitacad.com>
Message-ID: <48C1C23A.9010709@gmx.net>

Hi Joel,

I added your listings to
http://www.coreboot.org/Flashrom#Supported_mainboards and linked the
board names to the matching product pages on your website. If you see
any mistakes, please tell us.

By the way, if flashrom works for a particular board on 32bit Linux, it
should work on 64bit as well and vice versa.

However, I believe the flash chip you mentioned for a few boards (PMC
49LF004T) does not exist according to PMC. Did you mean the PMC Pm49FL004T?
I know what the official Tyan website says (PMC 49LF004T), but I believe
that to be an error.
It would be great if you could look up the actual engraved model number
(below the colorful sticker) on such a flash chip.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rmh at aybabtu.com  Sat Sep  6 01:39:50 2008
From: rmh at aybabtu.com (Robert Millan)
Date: Sat, 6 Sep 2008 01:39:50 +0200
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905220209.GB31582@thorin>
References: <20080905150817.GA11396@thorin> <48C155D3.7010900@coresystems.de>
	<20080905220209.GB31582@thorin>
Message-ID: <20080905233950.GA3546@thorin>

On Sat, Sep 06, 2008 at 12:02:09AM +0200, Robert Millan wrote:
> > Use ist wisely. And please create User:RobertMillan so people know who
> > you are.
> 
> Thank you.  I will.

I hope it's not too informal (but if it is, let me know and I'll find another
picture):

  http://www.coreboot.org/User:RobertMillan

-- 
Robert Millan

  The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
  how) you may access your data; but nobody's threatening your freedom: we
  still allow you to remove your data and not access it at all."



From vincent.legoll at gmail.com  Sat Sep  6 01:54:28 2008
From: vincent.legoll at gmail.com (Vincent Legoll)
Date: Sat, 6 Sep 2008 01:54:28 +0200
Subject: [coreboot] Kernel hang solid
In-Reply-To: <4727185d0809051321l5f2d1566q84b3ab96ce293d00@mail.gmail.com>
References: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
	<2ea3fae10809042003i3c450fbewb70bca920f9711aa@mail.gmail.com>
	<4727185d0809050238g8aa8694u1f88b86fffc27885@mail.gmail.com>
	<4727185d0809051321l5f2d1566q84b3ab96ce293d00@mail.gmail.com>
Message-ID: <4727185d0809051654k750a5ddcg208299a9196123ea@mail.gmail.com>

On Fri, Sep 5, 2008 at 10:21 PM, Vincent Legoll
<vincent.legoll at gmail.com> wrote:
> Tested 2.6.{23,24,25} they all hang the same way at the same place:
> the first console_initcall() (which I don't know if it is the serial one or
> the vga one)

I've narrowed it to the
down(&console_sem) in acquire_console_sem() in kernel/printk.c
called from con_init() in drivers/char/vt.c

I suspect the spin_lock_irqsave() in there hanging...

I have a lot of CONNFIG_DEBUG_ options activated, especially
CONFIG_DEBUG_SPINLOCK, but in vain...

So is there something I can do to narrow the problem.
How can I validate my irq setup ?

-- 
Vincent Legoll



From jordan.crouse at amd.com  Sat Sep  6 01:59:09 2008
From: jordan.crouse at amd.com (Jordan Crouse)
Date: Fri, 5 Sep 2008 17:59:09 -0600
Subject: [coreboot] wiki account request (for GRUB 2)
In-Reply-To: <20080905233950.GA3546@thorin>
References: <20080905150817.GA11396@thorin> <48C155D3.7010900@coresystems.de>
	<20080905220209.GB31582@thorin> <20080905233950.GA3546@thorin>
Message-ID: <20080905235909.GA24308@cosmic.amd.com>

On 06/09/08 01:39 +0200, Robert Millan wrote:
> On Sat, Sep 06, 2008 at 12:02:09AM +0200, Robert Millan wrote:
> > > Use ist wisely. And please create User:RobertMillan so people know who
> > > you are.
> > 
> > Thank you.  I will.
> 
> I hope it's not too informal (but if it is, let me know and I'll find another
> picture):
> 
>   http://www.coreboot.org/User:RobertMillan

Seesh, a picture?  YOu are making the rest of us look bad over here :)

Jordan

> -- 
> Robert Millan
> 
>   The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
>   how) you may access your data; but nobody's threatening your freedom: we
>   still allow you to remove your data and not access it at all."
> 
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 

-- 
Jordan Crouse
Systems Software Development Engineer 
Advanced Micro Devices, Inc.




From mats.andersson at gisladisker.se  Sat Sep  6 02:03:47 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Sat, 06 Sep 2008 02:03:47 +0200
Subject: [coreboot] v2: The elfboot process with 128MB RAM
In-Reply-To: <48C0645D.2070908@coresystems.de>
Message-ID: <E1KblHH-0007rZ-VG@aun.bellman.mea>

Hello Stefan, and all interested people,

Stefan Reinauer <stepan at coresystems.de> skrev
>Mats Erik Andersson wrote:
>> Hello all,
>>
>> I could use some of your insight into the elfboot stage.
>> Appended to this message are two printouts of the elfboot
>> process for 128MB RAM (which comes to a halt), and for
>> 64MB RAM (which succeeds). It is jmp_to_elf_entry() in
>>
>>    src/arch/i386/boot/boot.c
>>
>> that is unable to complete the set task for 128MB RAM.
>> I suspect that the problem lies in the value of
>> 'bounce_buffer' that is determined in src/boot/elfboot.c,
>> but I fail to identify why a large value is causing
>> any problem at all. The informational "Candidate bounce_buffer"
>> is my addition at the loop end in get_bounce_buffer().
>>
>> Since FILO never starts with 128MB, I cannot verify that the
>> linuxbios_table indeed gets the expected last entry
>Are you sure your second 64M are working correctly?
>
>This could well be a ram init problem.
>
>Which board?

It is a port to msi/ms6147 of the code Uwe Hammer developed
for msi/ms6119. Essentially, I have so far made two contributions:

1) the generic /src/sdram/generic_dump_spd.c, has been tailored
   and moved to the mainboard source directory,

2) an almost complete spd-detection mechanism for sdram has been
   incorporated into raminit.c.

Presently, I 

a) boot successfully with a single sided 64MB card in either DIMM-slot.
   "Success" meaning that I can get a Debian Sarge router to run with
   /usr on an IDE-CF disk, and the rest loaded into a ramdisk.

b) The tree cases of double sided 128MB card in either slot, or two
   single sided 64MB cards in both slots, are correctly detected and
   the RAM memory is verified in 0x07ffff00 to 0x07fffff0 in all these
   cases. However, the execution halts after the jump into filo.elf.
   I was got an error message from malloc() inside Filo!

c) When populating with two double sided 32MB cards, already the jump
   into Coreboot is unsuccessful after attempted RAM initialisation.
   This probably depends on the timing parameters, that I have not
   dynamically implemented as of yet.

Thus, I am now trying to understand why a large amount of memory,
i.e., 128MB instead of a mere 64MB, can prevent elfboot to succeed,
even though the memory is undisputably well initialised.

I will report in due time. Best regards,

Mats E Andersson



From rminnich at gmail.com  Sat Sep  6 02:48:06 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 17:48:06 -0700
Subject: [coreboot] Kernel hang solid
In-Reply-To: <4727185d0809051654k750a5ddcg208299a9196123ea@mail.gmail.com>
References: <4727185d0809041700y6af9b5a9l8df77c932222df69@mail.gmail.com>
	<2ea3fae10809042003i3c450fbewb70bca920f9711aa@mail.gmail.com>
	<4727185d0809050238g8aa8694u1f88b86fffc27885@mail.gmail.com>
	<4727185d0809051321l5f2d1566q84b3ab96ce293d00@mail.gmail.com>
	<4727185d0809051654k750a5ddcg208299a9196123ea@mail.gmail.com>
Message-ID: <13426df10809051748n1b6fefb2h236c09925be24351@mail.gmail.com>

On Fri, Sep 5, 2008 at 4:54 PM, Vincent Legoll <vincent.legoll at gmail.com> wrote:
> On Fri, Sep 5, 2008 at 10:21 PM, Vincent Legoll
> <vincent.legoll at gmail.com> wrote:
>> Tested 2.6.{23,24,25} they all hang the same way at the same place:
>> the first console_initcall() (which I don't know if it is the serial one or
>> the vga one)
>
> I've narrowed it to the
> down(&console_sem) in acquire_console_sem() in kernel/printk.c
> called from con_init() in drivers/char/vt.c
>
> I suspect the spin_lock_irqsave() in there hanging...
>
> I have a lot of CONNFIG_DEBUG_ options activated, especially
> CONFIG_DEBUG_SPINLOCK, but in vain...
>
> So is there something I can do to narrow the problem.
> How can I validate my irq setup ?
>

I don't know but when it gets this weird it can actually be memory ...

ron



From joe at settoplinux.org  Sat Sep  6 04:47:43 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 05 Sep 2008 22:47:43 -0400
Subject: [coreboot] v2: The elfboot process with 128MB RAM
In-Reply-To: <E1KblHH-0007rZ-VG@aun.bellman.mea>
References: <E1KblHH-0007rZ-VG@aun.bellman.mea>
Message-ID: <0eaa68082f887113d32d9f4767cace89@imap.1and1.com>


> Thus, I am now trying to understand why a large amount of memory,
> i.e., 128MB instead of a mere 64MB, can prevent elfboot to succeed,
> even though the memory is undisputably well initialised.
> 
Hmm, I still have a feeling your memory is not initializing correctly. Have
you tried ram_check() (from auto.c) on various chucks of memory? I would
try..

ram_check(0, 640 * 1024);  //first 64k (begining of first side)
ram_check(64512 * 1024, 65536 * 1024);  //63 - 64MB (end of first side)
ram_check(65536 * 1024, 66560 * 1024);  //64 - 65MB (begining of second
side)
ram_check(130048 * 1024, 131072 * 1024); //127 - 128MB (end of second side)

You may have to do these seperatly, with each build. Post back the results.
Hope that helps.
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Sat Sep  6 04:57:57 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Sep 2008 04:57:57 +0200
Subject: [coreboot] current dtc patch
In-Reply-To: <13426df10809051345w182235c8g8ad3a165d2f3d654@mail.gmail.com>
References: <13426df10809040904x21350debo69777bd41cf567dc@mail.gmail.com>	<48C19509.9040908@gmx.net>
	<48C19913.907@gmx.net>
	<13426df10809051345w182235c8g8ad3a165d2f3d654@mail.gmail.com>
Message-ID: <48C1F1B5.7070707@gmx.net>

On 05.09.2008 22:45, ron minnich wrote:
> On Fri, Sep 5, 2008 at 1:39 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> On 05.09.2008 22:22, Carl-Daniel Hailfinger wrote:
>>     
>>> On 04.09.2008 18:04, ron minnich wrote:
>>>
>>>       
>>>> no ack in it, for your viewing pleasure.
>>>>
>>>> Tested on dbe62.
>>>>
>>>>
>>>>         
>>> Looks nice.
>>> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>
>>>       
>> It exploded with the current dts of the AMD Serengeti, though, and
>> produced this statictree.c excerpt:
>>     
>>> struct device dev_ioport_2e = {
>>>         .path = {{.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x2e}}},
>>>       
>> One opening bracket too many.
>>
>>     
>>>         .device_configuration = &ioport_2e,
>>>         .next = &dev_domain_0,
>>>         .links = 0,
>>>         .bus = &dev_domain_0.link[0],
>>>         .next = &dev_domain_0,
>>>         .dtsname = "ioport_2e",
>>>         .enabled = 1
>>> };
>>>       
>> Regards,
>> Carl-Daniel
>>
>> --
>> http://www.hailfinger.org/
>>
>>
>>     
>
> yeah my bad I fixed that.
>   

Oh, and another bug: The statictree.c code now refers to nonexisting
links. Look at this snippet:
struct device dev_root = {
        .path = { .type = DEVICE_PATH_ROOT },
        .next = &dev_cpu_0,
        .links = 0,
        .bus = &dev_root.link[0],
        .next = &dev_cpu_0,
        .ops = &default_dev_ops_root,
        .dtsname = "root",
        .enabled = 1
};
struct device dev_cpu_0 = {
        .path = {.type=DEVICE_PATH_CPU,{.cpu={ .id = 0x0 }}},
        .sibling = &dev_apic_0,
        .next = &dev_apic_0,
        .links = 0,
        .bus = &dev_root.link[0],   //DOES NOT EXIST
        .next = &dev_apic_0,
        .dtsname = "cpus",
        .enabled = 1
};


Maybe using my patch is really the better choice. I'll admit anytime
that my naming scheme is overly verbose and you're free to change it.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sat Sep  6 05:22:30 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Sep 2008 05:22:30 +0200
Subject: [coreboot] dtc patch: make all names unique, misc. cleanup,
 more to come
In-Reply-To: <13426df10809040822n5f10ca4cx8d40c4d6e6e6fa9@mail.gmail.com>
References: <13426df10809031730g54873576i935b62714bb970c6@mail.gmail.com>	
	<48BF2CFE.6000307@gmx.net>	
	<13426df10809031745l591c949dv8c9e1d8636b1668b@mail.gmail.com>	
	<13426df10809031759q69fe8f03m1b62cf40a4a0e4fa@mail.gmail.com>	
	<48BF53FE.8000705@gmx.net>
	<13426df10809040822n5f10ca4cx8d40c4d6e6e6fa9@mail.gmail.com>
Message-ID: <48C1F776.5020202@gmx.net>

On 04.09.2008 17:22, ron minnich wrote:
> On Wed, Sep 3, 2008 at 8:20 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>>> I am not sure this it totally right yet, however:
>>> struct device dev_domain_0 = {
>>>       .path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
>>>       .device_configuration = &domain_0,
>>>       .ops = &geodelx_north_domain,
>>>       .link = {
>>>               [0] = {
>>>                       .dev = &dev_domain_0,
>>>                       .link = 0,
>>>                       .children = &dev_pci_0_0_1_0
>>>               },
>>>
>>>               [1] = {
>>>                       .dev = &dev_domain_0,
>>>                       .link = 0,
>>>                       .children = &dev_pci_0_0_f_0
>>>               },
>>>               [2] = {
>>>                       .dev = &dev_domain_0,
>>>                       .link = 0,
>>>                       .children = &dev_pci_0_0_f_2
>>>               },
>>>
>>>       
>> The list of links "feels" wrong. I can't yet express that feeling in
>> technical terms, but I'll revisit this issue tomorrow.
>>     
>
> it is wrong. :-)
>
> Let's review links.
>
> Links came in IIRC because of the k8. We needed a way to express the
> HT links. It gets weird because on the k8, the HT address space is in
> PCI space (this is actually a very nice thing AMD did). There are
> three HT links, and they are all addressed as 0:18.0.
>
> I never felt they way we expressed links in v2 was as clear as we
> might have made them. How do you know a link is there?
> It's not really explicitly named. You see this kind of comment in v2 Config.lb:
>
>                         device pci 18.0 on #  northbridge
>                                 #  devices on link 0, link 0 == LDT 0
>
> What would trigger that? How do we get to link 1? Turns out it happens
> if we see this again:
>                         device pci 18.0 on #  northbridge
>
> config tool "knows" that it is now link 1. See tyan/s2892. It's not
> just for HT either. And two children of a device in v2 having the same
> path become links.
>   

Yes, and that implicit magic is something I want to avoid in v3. Sure,
it's clever, but how many people will ever understand it?

> struct device _dev8 = {
>         .ops = 0,
>         .bus = &_dev6.link[0],
>         .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x18,0)}}},
>         .enabled = 1,
>         .on_mainboard = 1,
>         .link = {
>                 [0] = {
>                         .link = 0,
>                         .dev = &_dev8,
>                         .children = &_dev10,
>                 },
>                 [1] = {
>                         .link = 1,
>                         .dev = &_dev8,
>                 },
>                 [2] = {
>                         .link = 2,
>                         .dev = &_dev8,
>                         .children = &_dev72,
>                 },
>         },
>         .links = 3,
>         .sibling = &_dev79,
>         .next=&_dev10
> };
>
> dev10 is one pci bus, dev72 is the ck804.
>
> Again, links come into play when multiple devices have the same path,
> e.g. HT links on 18:0.0 (three of them) or I2C mux (2 of them). Again,
> see tyan s2892.
>
> So in the dts, what would this look like? Well, if we had:
>
> pci at 18,0 {};
> pci at 18,0 {};
> pci at 18,0 {};
>
> this might become three links. This is the v2 way of doing it. What I
> wanted to do was something like this:
> bus at 0 {pci at 18,0 {};};
> bus at 1 {pci at 18,1 {};};
>
> and so on. Really, if a bus is only ever going to be a link, maybe we
> should rename "bus" to "link" and leave it at that.
>   

You correctly identified the biggest question from a conceptual POV. Is
a bus only a link? Or is a bus a device that hangs off its parent and
has its own children?

My current idea is:
Treat every dts node except "ht" normally. Nodes below a "ht" node don't
get added as multiple siblings below a single link/bus, but they each
end up as single sibling, each on its own link. The dts bus number is
treated as link number in generated code
I'll have to revisit that idea, though. It feels not quite right.

> So much for links.
>
>
> Also, I see your point but:
> struct device dev_pci_domain_0_bus_0_dev_1_fn_0
>
> is just far more wordy than I like. Bear in mind that the primary goal
> of this patch is to make the names unique.
>   

Yes.

> Human readability is a secondary goal (no one ever looks at these
> names anyway) and I think the long name you propose
> is more than I would like to read all the time :-)
>   

True. If we don't have a solution by Tuesday, I'll change my patch to
fit your naming taste.
The dtsname printed during coreboot bootup needs vast improvements,
though. It is barely readable both for current svn and any of our
proposals. I propose to offer specifying it in the dts. Having print
coreboot "First RTL8139 Network Card on bottom of board (PCI: 00:01.1)"
instead of "pci_0_0_1_1(PCI: 00:01.1)" is the difference between easy
and cryptic.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Sat Sep  6 06:36:45 2008
From: rminnich at gmail.com (ron minnich)
Date: Fri, 5 Sep 2008 21:36:45 -0700
Subject: [coreboot] current dtc patch
In-Reply-To: <48C1F1B5.7070707@gmx.net>
References: <13426df10809040904x21350debo69777bd41cf567dc@mail.gmail.com>
	<48C19509.9040908@gmx.net> <48C19913.907@gmx.net>
	<13426df10809051345w182235c8g8ad3a165d2f3d654@mail.gmail.com>
	<48C1F1B5.7070707@gmx.net>
Message-ID: <13426df10809052136k68bad92fw3da2bb6a0dd95fc2@mail.gmail.com>

On Fri, Sep 5, 2008 at 7:57 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Maybe using my patch is really the better choice. I'll admit anytime
> that my naming scheme is overly verbose and you're free to change it.
>

go ahead and commit your patch and I'll work with it as is

ron



From daniel-coreboot at lindenaar.eu  Sat Sep  6 11:01:43 2008
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Sat, 06 Sep 2008 11:01:43 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>	<48C0512E.9050104@lindenaar.eu>
	<dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>
Message-ID: <48C246F7.8060102@lindenaar.eu>

Corey Osgood wrote:
> On Thu, Sep 4, 2008 at 5:20 PM, Daniel Lindenaar
> <daniel-coreboot at lindenaar.eu> wrote:
>   
>> hmmm it's working partly, it seems. First i did something wrong that skrewed
>> up the com port setup, which I fixed. I now get the debug messages I added
>> via the serial line, but, strangely, only when i do a (warm) reboot from a
>> running linux, not with a cold boot... probably something needs to be set
>> that doesn't get set by default on cold reboot.
>>     
>
> Not good. Can you send me a copy of your tree or a patch, and a
> complete boot log? I've seen the same issue, I just can't remember how
> I fixed it at the moment. It's something to do with either the romcc
> build parameters or failover code, I can't remember atm. Also, vt8601
> is compatible with both c3 and p2/p3, right? Which are you using?
>
>   
OK, there some small progress made. I'll send you a patch later. Here's 
a complete bootlog. first after a warm reboot, then after a power cycle 
and then after a reset.

It's a pretty long log, because I'm dumping the pci config space, 
however, the PCI bus/device numbers don't seem right. Notice that even 
though SMBus still doesn't work, coreboot actually starts on warm 
reboot, but it finishes with a crash.

coreboot-2.0.0.0Fallback Sat Sep  6 11:31:58 UTC 2008 starting...
PCI: 00:00.00
PCI: 00:10.00
PCI: 03:10.00
PCI: 03:12.00
PCI: 03:14.00
PCI: 03:16.00
PCI: 03:18.00
PCI: 03:1a.00
PCI: 06:10.00
PCI: 06:12.00
PCI: 06:14.00
PCI: 06:16.00
PCI: 06:18.00
PCI: 06:1a.00
PCI: 06:1c.00
PCI: 06:1e.00
PCI: 00:00.00
00: 06 11 01 06 06 00 90 a2 05 00 00 06 00 08 00 00
10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 01 06
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: fe df c8 b8 00 00 08 08 80 00 08 08 08 08 08 08
60: 3f ea 00 20 e6 94 94 00 52 3c 86 2d 68 21 00 00
70: c0 88 ec 0c 0e 81 52 00 01 f4 09 00 00 00 00 00
80: 0f 41 00 00 c0 00 00 00 02 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 07 02 00 07 00 00 00 00 6e 02 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 01 01 22 42 00 b0 00 80 00 00
PCI: 00:10.00
00: 06 11 01 86 07 00 30 a2 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00
20: 00 e4 70 e5 00 10 00 10 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00
40: 48 4d 00 44 04 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:10.00
00: 06 11 86 06 87 00 10 02 40 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00
40: 09 01 00 c0 00 80 60 e6 01 01 c4 00 00 00 00 f3
50: 0c 70 34 00 00 00 5f b0 00 06 ff 08 d0 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 01 00 00 02 00 00 f0 40 00 00 00 00
80: 00 00 00 00 00 09 00 00 00 60 00 02 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 42 00 00 00 00 00 00 00 00 00
PCI: 03:12.00
00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 d0 00 00 00 00 00 00 00 00 00 00 06 11 71 05
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 00 00
40: 0a e2 09 35 1c 1f c0 00 a8 a8 a8 33 3f 00 ff 91
50: 03 03 03 07 34 00 00 00 a8 a8 a8 a8 00 00 00 00
60: 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00
70: 42 01 00 00 00 00 00 00 83 01 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 06 00 71 05 06 11 71 05 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:14.00
00: 06 11 38 30 07 00 10 02 1a 00 03 0c 08 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 d4 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 04 00 00
40: 00 12 03 00 c2 00 33 30 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:16.00
00: 06 11 38 30 07 00 10 02 1a 00 03 0c 08 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 d8 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 04 00 00
40: 00 12 03 00 c2 00 10 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:18.00
00: 06 11 57 30 00 00 90 02 40 00 80 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 57 30
30: 00 00 00 00 68 00 00 00 00 00 00 00 00 00 00 00
40: 20 84 59 00 ba 30 00 00 01 40 00 00 00 10 00 00
50: 00 6c 5f 88 00 04 00 00 00 27 db 00 06 11 57 30
60: 00 00 00 00 00 00 00 00 01 00 02 00 00 00 00 00
70: 01 60 00 00 01 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 01 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 01 00 00 00 40 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:1a.00
00: 06 11 58 30 01 00 10 02 50 00 01 04 00 00 00 00
10: 01 dc 00 00 01 e0 00 00 01 e4 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 58 30
30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 03 00 00
40: 01 cc 40 1c 00 00 00 00 00 00 00 02 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:10.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:12.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:14.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:16.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:18.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1a.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1c.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1e.00
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 e8 00 00 00 00 81 e5 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
passed bist failure
entering enable_mainboard_devices
pci_loc_dev 1106:0686
....
exiting enable_motherboard_devsvt8601 init starting
00000000 is the north1106 0601
0120smbus_error: 04
Device Error
smbus_error: 04
Device Error
smbus_error: 04
Device Error
84 is the computed timingNOP
PRECHARGE
DUMMY READS
CBR
MRS
NORMAL
set ref. rate
enable multi-page open
Slot 00smbus_error: 04
Device Error
 is empty
Slot 01smbus_error: 04
Device Error
 is empty
Slot 02smbus_error: 04
Device Error
 is empty
Slot 03smbus_error: 04
Device Error
 is empty
vt8601 done
Copying coreboot to RAM.
Jumping to coreboot.
coreboot-2.0.0.0Fallback Sat Sep  6 11:31:58 UTC 2008 booting...
Enumerating buses...
scan_static_bus for Root Device
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1106/0601] ops
PCI: 00:00.0 [1106/0601] enabled
malloc Enter, size 1100, free_mem_ptr 00016000
malloc 0x00016000
Capability: 0x07 @ 0x80
Capability: 0x08 @ 0x80
Capability: 0x10 @ 0x80
PCI: 00:01.0 [1106/8601] enabled
PCI: devfn 0x10, bad id 0xffffffff
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
In vt82c686_enable 1106 0686.
Initialising Devices
Keyboard init...
PCI: 00:07.0 [1106/0686] enabled
In vt82c686_enable 1106 0571.
south enable on non-south chip???PCI: 00:07.1 [1106/0571] ops
PCI: 00:07.1 [1106/0571] enabled
In vt82c686_enable 1106 3038.
south enable on non-south chip???PCI: 00:07.2 [1106/3038] disabled
In vt82c686_enable ffff ffff.
south enable on non-south chip???In vt82c686_enable 1106 3057.
south enable on non-south chip???PCI: 00:07.4 [1106/3057] disabled
In vt82c686_enable 1106 3058.
south enable on non-south chip???PCI: 00:07.5 [1106/3058] enabled
In vt82c686_enable ffff ffff.
south enable on non-south chip???Disabling static device: PCI: 00:07.6
PCI: devfn 0x3f, bad id 0xffffffff
PCI: devfn 0x40, bad id 0xffffffff
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
malloc Enter, size 1100, free_mem_ptr 0001644c
malloc 0x0001644c
PCI: 00:0d.0 [10ec/8139] enabled
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
In vt82c686_enable ffff ffff.
south enable on non-south chip???Disabling static device: PCI: 00:13.0
PCI: devfn 0x99, bad id 0xffffffff
PCI: devfn 0x9a, bad id 0xffffffff
PCI: devfn 0x9b, bad id 0xffffffff
PCI: devfn 0x9c, bad id 0xffffffff
PCI: devfn 0x9d, bad id 0xffffffff
PCI: devfn 0x9e, bad id 0xffffffff
PCI: devfn 0x9f, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: devfn 0xe8, bad id 0xffffffff
PCI: devfn 0xf0, bad id 0xffffffff
PCI: devfn 0xf8, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
malloc Enter, size 1100, free_mem_ptr 00016898
malloc 0x00016898
PCI: 01:00.0 [1023/8500] enabled
PCI: devfn 0x8, bad id 0xffffffff
PCI: devfn 0x10, bad id 0xffffffff
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
PCI: devfn 0x38, bad id 0xffffffff
PCI: devfn 0x40, bad id 0xffffffff
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
PCI: devfn 0x68, bad id 0xffffffff
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
PCI: devfn 0x98, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: devfn 0xe8, bad id 0xffffffff
PCI: devfn 0xf0, bad id 0xffffffff
PCI: devfn 0xf8, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device compute_allocate_resource io: base: 00000400 size: 00000000 
align: 0 gran: 0
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0


coreboot-2.0.0.0Fallback Sat Sep  6 11:31:58 UTC 2008 starting...


coreboot-2.0.0.0Fallback Sat Sep  6 11:31:58 UTC 2008 starting...
PCI: 00:00.00
PCI: 00:10.00
PCI: 03:10.00
PCI: 03:14.00
PCI: 03:16.00
PCI: 03:18.00
PCI: 03:1a.00
PCI: 03:1c.00
PCI: 06:10.00
PCI: 06:12.00
PCI: 06:14.00
PCI: 06:16.00
PCI: 06:18.00
PCI: 06:1a.00
PCI: 06:1c.00
PCI: 06:1e.00
PCI: 00:00.00
00: 06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: ac 08 80 00 00 00 01 01 40 00 13 f6 91 30 91 ca
60: 00 00 00 00 ec ec ec 00 02 00 00 01 00 09 00 00
70: 00 00 00 00 00 00 00 00 00 f0 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00
PCI: 00:10.00
00: 06 11 01 86 07 00 30 02 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 22 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:10.00
00: 06 11 86 06 87 00 10 02 40 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 03 00 04 00 00 00 00 03
50: 0e 00 00 00 00 00 00 00 00 04 ff 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 01 00 00 00 60 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 42 00 00 00 00 00 00 00 00 00
PCI: 03:14.00
00: 06 11 38 30 00 00 10 02 1a 00 03 0c 00 16 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: e1 fc 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00
40: 00 00 01 00 06 00 11 10 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:16.00
00: 06 11 38 30 00 00 10 02 1a 00 03 0c 00 16 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: e1 fc 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00
40: 00 00 01 00 06 00 10 40 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:18.00
00: 06 11 57 30 00 00 90 02 40 00 00 00 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 68 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 50 00 00 00 00 00 01 00 00 00 00 00 00 00
50: 00 6d 3f 00 00 00 00 00 00 a1 8b 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 00 02 00 00 00 00 00
70: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:1a.00
00: 06 11 58 30 00 00 10 02 50 00 01 04 00 00 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 03 00 00
40: 00 00 00 1c 00 00 00 00 00 00 00 02 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:1c.00
00: 06 11 68 30 00 00 10 02 30 00 80 07 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 03 00 00
40: 00 00 00 1c 00 00 00 00 00 00 00 02 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:10.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:12.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:14.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:16.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:18.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1a.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1c.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1e.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
passed bist failure
entering enable_mainboard_devices
pci_loc_dev 1106:0686
....
exiting enable_motherboard_devsvt8601 init starting
00000000 is the north1106 0601
0120smbus_error: 04
Device Error
smbus_error: 04
Device Error
smbus_error: 04
Device Error
84 is the computed timingNOP
PRECHARGE
DUMMY READS
CBR
MRS
NORMAL
set ref. rate
enable multi-page open
Slot 00smbus_error: 04
Device Error
 is empty
Slot 01smbus_error: 04
Device Error
 is empty
Slot 02smbus_error: 04
Device Error
 is empty
Slot 03smbus_error: 04
Device Error
 is empty
vt8601 done
Copying coreboot to RAM.
Jumping to coreboot.


coreboot-2.0.0.0Fallback Sat Sep  6 11:31:58 UTC 2008 starting...
PCI: 00:00.00
PCI: 00:10.00
PCI: 03:10.00
PCI: 03:14.00
PCI: 03:16.00
PCI: 03:18.00
PCI: 03:1a.00
PCI: 03:1c.00
PCI: 06:10.00
PCI: 06:12.00
PCI: 06:14.00
PCI: 06:16.00
PCI: 06:18.00
PCI: 06:1a.00
PCI: 06:1c.00
PCI: 06:1e.00
PCI: 00:00.00
00: 06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: ac 08 80 00 00 00 01 01 40 00 00 00 00 00 00 00
60: 3f 00 00 00 ec ec ec 00 02 00 00 01 00 0f 00 00
70: 00 00 00 00 00 00 00 00 00 f0 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00
PCI: 00:10.00
00: 06 11 01 86 07 00 30 02 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 22 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:10.00
00: 06 11 86 06 87 00 10 02 40 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 03 01 04 00 00 00 00 03
50: 0e 00 00 00 00 00 00 00 00 04 ff 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 01 00 00 00 60 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 42 00 00 00 00 00 00 00 00 00
PCI: 03:14.00
00: 06 11 38 30 00 00 10 02 1a 00 03 0c 00 16 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: e1 fc 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00
40: 00 00 01 00 c6 00 33 30 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:16.00
00: 06 11 38 30 00 00 10 02 1a 00 03 0c 00 16 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: e1 fc 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00
40: 00 00 01 00 c2 00 10 c0 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:18.00
00: 06 11 57 30 00 00 90 02 40 00 00 00 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 68 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 50 00 00 00 00 00 01 00 00 00 00 00 00 00
50: 00 6d 3f 00 00 00 00 00 00 a1 8b 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 01 00 02 00 00 00 00 00
70: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:1a.00
00: 06 11 58 30 00 00 10 02 50 00 01 04 00 00 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 03 00 00
40: 00 00 00 1c 00 00 00 00 00 00 00 02 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 03:1c.00
00: 06 11 68 30 00 00 10 02 30 00 80 07 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 03 00 00
40: 00 00 00 1c 00 00 00 00 00 00 00 02 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:10.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:12.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:14.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:16.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:18.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1a.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1c.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:1e.00
00: ec 10 39 81 00 00 90 02 10 00 00 02 00 00 00 00
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
passed bist failure
entering enable_mainboard_devices
pci_loc_dev 1106:0686
....
exiting enable_motherboard_devsvt8601 init starting
00000000 is the north1106 0601
0120smbus_error: 04
Device Error
smbus_error: 04
Device Error
smbus_error: 04
Device Error
84 is the computed timingNOP
PRECHARGE
DUMMY READS
CBR
MRS
NORMAL
set ref. rate
enable multi-page open
Slot 00smbus_error: 04
Device Error
 is empty
Slot 01smbus_error: 04
Device Error
 is empty
Slot 02smbus_error: 04
Device Error
 is empty
Slot 03smbus_error: 04
Device Error
 is empty
vt8601 done
Copying coreboot to RAM.
Jumping to coreboot.

Appreciate your help

regards,
Daniel
>> Anyway, it's the SMBus controller where things go wrong; the log says:
>>
>> SMBUS controller not found
>>     
>
> Check the datasheet, there's probably a bit somewhere in the LPC
> controller that enables the smbus controller, you'll need to flip that
> first, if you haven't already.
>
> -Corey
>
>   
>> as the last item. At least some progress is made. Besides the logging not
>> working on cold boot, which it should at some point, I've now got something
>> that works well enough to start proper debugging.
>>
>> regards,
>> Daniel
>>     
>>> --
>>> coreboot mailing list
>>> coreboot at coreboot.org
>>> http://www.coreboot.org/mailman/listinfo/coreboot
>>>
>>>
>>>       
>>     
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
>   




From daniel at lindenaar.eu  Sat Sep  6 11:56:45 2008
From: daniel at lindenaar.eu (Daniel Lindenaar)
Date: Sat, 06 Sep 2008 11:56:45 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C246F7.8060102@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>	<48C0512E.9050104@lindenaar.eu>	<dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>
	<48C246F7.8060102@lindenaar.eu>
Message-ID: <48C253DD.8080704@lindenaar.eu>

Daniel Lindenaar wrote:
> Corey Osgood wrote:
>> On Thu, Sep 4, 2008 at 5:20 PM, Daniel Lindenaar
>> <daniel-coreboot at lindenaar.eu> wrote:
>>  
>>> hmmm it's working partly, it seems. First i did something wrong that 
>>> skrewed
>>> up the com port setup, which I fixed. I now get the debug messages I 
>>> added
>>> via the serial line, but, strangely, only when i do a (warm) reboot 
>>> from a
>>> running linux, not with a cold boot... probably something needs to 
>>> be set
>>> that doesn't get set by default on cold reboot.
>>>     
>>
>> Not good. Can you send me a copy of your tree or a patch, and a
>> complete boot log? I've seen the same issue, I just can't remember how
>> I fixed it at the moment. It's something to do with either the romcc
>> build parameters or failover code, I can't remember atm. Also, vt8601
>> is compatible with both c3 and p2/p3, right? Which are you using?
>>
>>   
> OK, there some small progress made. I'll send you a patch later. 
> Here's a complete bootlog. first after a warm reboot, then after a 
> power cycle and then after a reset.
Here's the patch... Hope you can help <:)


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From daniel at lindenaar.eu  Sat Sep  6 12:01:06 2008
From: daniel at lindenaar.eu (Daniel Lindenaar)
Date: Sat, 06 Sep 2008 12:01:06 +0200
Subject: [coreboot] via vt82c686 southbridge
In-Reply-To: <48C253DD.8080704@lindenaar.eu>
References: <48BEDF4F.1020405@lindenaar.eu>	<20080904175524.854556r78he2jzls@www.lindenaar.eu>	<dd3c80060809041026h72b0afyd107cc1e916e8516@mail.gmail.com>	<48C02940.7040600@lindenaar.eu>	<dd3c80060809041332g51cef9b9g5f8d89c8d0d2c3b4@mail.gmail.com>	<48C0512E.9050104@lindenaar.eu>	<dd3c80060809041923t41f3932ft8867394714e46c3f@mail.gmail.com>	<48C246F7.8060102@lindenaar.eu>
	<48C253DD.8080704@lindenaar.eu>
Message-ID: <48C254E2.2000803@lindenaar.eu>

Daniel Lindenaar wrote:
> Daniel Lindenaar wrote:
>> Corey Osgood wrote:
>>> On Thu, Sep 4, 2008 at 5:20 PM, Daniel Lindenaar
>>> <daniel-coreboot at lindenaar.eu> wrote:
>>>  
>>>> hmmm it's working partly, it seems. First i did something wrong 
>>>> that skrewed
>>>> up the com port setup, which I fixed. I now get the debug messages 
>>>> I added
>>>> via the serial line, but, strangely, only when i do a (warm) reboot 
>>>> from a
>>>> running linux, not with a cold boot... probably something needs to 
>>>> be set
>>>> that doesn't get set by default on cold reboot.
>>>>     
>>>
>>> Not good. Can you send me a copy of your tree or a patch, and a
>>> complete boot log? I've seen the same issue, I just can't remember how
>>> I fixed it at the moment. It's something to do with either the romcc
>>> build parameters or failover code, I can't remember atm. Also, vt8601
>>> is compatible with both c3 and p2/p3, right? Which are you using?
>>>
>>>   
>> OK, there some small progress made. I'll send you a patch later. 
>> Here's a complete bootlog. first after a warm reboot, then after a 
>> power cycle and then after a reset.
> Here's the patch... Hope you can help <:)
>
ow I forgot the target dir... here's the new one

sorry
Daniel

>
> ------------------------------------------------------------------------
>
> --
> coreboot mailing list
> coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

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From mats.andersson at gisladisker.se  Sat Sep  6 14:19:37 2008
From: mats.andersson at gisladisker.se (Mats Erik Andersson)
Date: Sat, 06 Sep 2008 14:19:37 +0200
Subject: [coreboot] v2: The elfboot process with 128MB RAM
In-Reply-To: <0eaa68082f887113d32d9f4767cace89@imap.1and1.com>
Message-ID: <E1KbwlN-0000ut-Ls@aun.bellman.mea>


Joseph Smith <joe at settoplinux.org> skrev s? v?nligt:

>> Thus, I am now trying to understand why a large amount of memory,
>> i.e., 128MB instead of a mere 64MB, can prevent elfboot to succeed,
>> even though the memory is undisputably well initialised.
>> 
>Hmm, I still have a feeling your memory is not initializing correctly. Have
>you tried ram_check() (from auto.c) on various chucks of memory? I would
>try..
>

I did use these ram checks (last line was active for my last message):

	/* DOS-area */
	//ram_check(0, 640 * 1024);
	/* 1MB to 4MB */
	//ram_check(0x00100000, 0x00400000);
	/* Across 64MB boundary */
	//ram_check(0x03fff000, 0x04000010);
	/* Just below 128MB */
	ram_check(0x07ffff00, 0x07fffff0);

Now that I have prepared accurate SPD-dumps for seven SDRAM cards,
I will return on Monday to perform more extended verifications.
Possibly large memory chunks could tell me more than strategic
sampling does. The bad thing is that the code space prevents more
than one verification range in each build, so the pace is indeed slow.

Best regards

Mats E Andersson



From joe at settoplinux.org  Sat Sep  6 15:15:12 2008
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 06 Sep 2008 09:15:12 -0400
Subject: [coreboot] v2: The elfboot process with 128MB RAM
In-Reply-To: <E1KbwlN-0000ut-Ls@aun.bellman.mea>
References: <E1KbwlN-0000ut-Ls@aun.bellman.mea>
Message-ID: <6db3797b25d6b5da0a9b31cbb28514af@imap.1and1.com>




On Sat, 06 Sep 2008 14:19:37 +0200, Mats Erik Andersson
<mats.andersson at gisladisker.se> wrote:
> 
> Joseph Smith <joe at settoplinux.org> skrev s vnligt:
> 
>>> Thus, I am now trying to understand why a large amount of memory,
>>> i.e., 128MB instead of a mere 64MB, can prevent elfboot to succeed,
>>> even though the memory is undisputably well initialised.
>>>
>>Hmm, I still have a feeling your memory is not initializing correctly.
> Have
>>you tried ram_check() (from auto.c) on various chucks of memory? I would
>>try..
>>
> 
> I did use these ram checks (last line was active for my last message):
> 
> 	/* DOS-area */
> 	//ram_check(0, 640 * 1024);
> 	/* 1MB to 4MB */
> 	//ram_check(0x00100000, 0x00400000);
> 	/* Across 64MB boundary */
> 	//ram_check(0x03fff000, 0x04000010);
> 	/* Just below 128MB */
> 	ram_check(0x07ffff00, 0x07fffff0);
> 
> Now that I have prepared accurate SPD-dumps for seven SDRAM cards,
> I will return on Monday to perform more extended verifications.
> Possibly large memory chunks could tell me more than strategic
> sampling does. The bad thing is that the code space prevents more
> than one verification range in each build, so the pace is indeed slow.
> 
Another thought...have you tried booting to memtest? If you can, memtest
will absolutly be able to tell you what is going on here.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Sat Sep  6 20:48:07 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Sep 2008 20:48:07 +0200
Subject: [coreboot] [PATCH] v3: make inline asm declarations consistent
Message-ID: <48C2D067.4010309@gmx.net>

v3 uses all combinations of __asm__, asm, __volatile__, volatile and
single variations to declare inline asm statements. "asm" is a GNU C
extension, while volatile is ANSI C. That means:
- __volatile__ can be replaced by volatile unless you use a pure K&R
compiler.
- asm is not a reserved keyword and should be replaced by __asm__.
As a bonus, grepping for __asm__ returns less hits than asm because asm
is also used as a normal word in comments.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/msr.h
===================================================================
--- corebootv3-inline_asm_consistent_underscores/include/arch/x86/msr.h	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/msr.h	(Arbeitskopie)
@@ -36,7 +36,7 @@
 static inline struct msr rdmsr(u32 index)
 {
 	struct msr  result;
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"rdmsr"
 		: "=a" (result.lo), "=d" (result.hi)
 		: "c" (index)
@@ -46,7 +46,7 @@
 
 static inline void wrmsr(u32 index, struct msr msr)
 {
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"wrmsr"
 		: /* No outputs */
 		: "c" (index), "a" (msr.lo), "d" (msr.hi)
Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/io.h
===================================================================
--- corebootv3-inline_asm_consistent_underscores/include/arch/x86/io.h	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/io.h	(Arbeitskopie)
@@ -28,43 +28,43 @@
 
 static inline void outb(u8 value, u16 port)
 {
-	__asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
+	__asm__ volatile ("outb %b0, %w1" : : "a" (value), "Nd" (port));
 }
 
 static inline void outw(u16 value, u16 port)
 {
-	__asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port));
+	__asm__ volatile ("outw %w0, %w1" : : "a" (value), "Nd" (port));
 }
 
 static inline void outl(u32 value, u16 port)
 {
-	__asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port));
+	__asm__ volatile ("outl %0, %w1" : : "a" (value), "Nd" (port));
 }
 
 static inline u8 inb(u16 port)
 {
 	u8 value;
-	__asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port));
+	__asm__ volatile ("inb %w1, %b0" : "=a"(value) : "Nd" (port));
 	return value;
 }
 
 static inline u16 inw(u16 port)
 {
 	u16 value;
-	__asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port));
+	__asm__ volatile ("inw %w1, %w0" : "=a"(value) : "Nd" (port));
 	return value;
 }
 
 static inline u32 inl(u16 port)
 {
 	u32 value;
-	__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
+	__asm__ volatile ("inl %w1, %0" : "=a"(value) : "Nd" (port));
 	return value;
 }
 
 static inline void outsb(u16 port, const void *addr, unsigned long count)
 {
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"cld ; rep ; outsb " 
 		: "=S" (addr), "=c" (count)
 		: "d"(port), "0"(addr), "1" (count)
@@ -73,7 +73,7 @@
 
 static inline void outsw(u16 port, const void *addr, unsigned long count)
 {
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"cld ; rep ; outsw " 
 		: "=S" (addr), "=c" (count)
 		: "d"(port), "0"(addr), "1" (count)
@@ -82,7 +82,7 @@
 
 static inline void outsl(u16 port, const void *addr, unsigned long count)
 {
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"cld ; rep ; outsl " 
 		: "=S" (addr), "=c" (count)
 		: "d"(port), "0"(addr), "1" (count)
@@ -92,7 +92,7 @@
 
 static inline void insb(u16 port, void *addr, unsigned long count)
 {
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"cld ; rep ; insb " 
 		: "=D" (addr), "=c" (count)
 		: "d"(port), "0"(addr), "1" (count)
@@ -101,7 +101,7 @@
 
 static inline void insw(u16 port, void *addr, unsigned long count)
 {
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"cld ; rep ; insw " 
 		: "=D" (addr), "=c" (count)
 		: "d"(port), "0"(addr), "1" (count)
@@ -110,7 +110,7 @@
 
 static inline void insl(u16 port, void *addr, unsigned long count)
 {
-	__asm__ __volatile__ (
+	__asm__ volatile (
 		"cld ; rep ; insl " 
 		: "=D" (addr), "=c" (count)
 		: "d"(port), "0"(addr), "1" (count)
Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/arch/spinlock.h
===================================================================
--- corebootv3-inline_asm_consistent_underscores/include/arch/x86/arch/spinlock.h	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/arch/spinlock.h	(Arbeitskopie)
@@ -29,7 +29,7 @@
  *
  * We make no fairness assumptions. They have a cost.
  */
-#define barrier()		__asm__ __volatile__("": : :"memory")
+#define barrier()		__asm__ volatile("": : :"memory")
 #define spin_is_locked(x)	(*(volatile char *)(&(x)->lock) <= 0)
 #define spin_unlock_wait(x)	do { barrier(); } while(spin_is_locked(x))
 
@@ -53,14 +53,14 @@
 
 static inline __attribute__((always_inline)) void spin_lock(struct spinlock *lock)
 {
-	__asm__ __volatile__(
+	__asm__ volatile(
 		spin_lock_string
 		:"=m" (lock->lock) : : "memory");
 }
 
 static inline __attribute__((always_inline)) void spin_unlock(struct spinlock *lock)
 {
-	__asm__ __volatile__(
+	__asm__ volatile(
 		spin_unlock_string
 		:"=m" (lock->lock) : : "memory");
 }
Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/cpu.h
===================================================================
--- corebootv3-inline_asm_consistent_underscores/include/arch/x86/cpu.h	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/cpu.h	(Arbeitskopie)
@@ -149,23 +149,23 @@
 static inline unsigned long read_cr0(void)
 {
 	unsigned long cr0;
-	asm volatile("movl %%cr0, %0" : "=r" (cr0));
+	__asm__ volatile("movl %%cr0, %0" : "=r" (cr0));
 	return cr0;
 }
 
 static inline void write_cr0(unsigned long cr0)
 {
-	asm volatile("movl %0, %%cr0" : : "r" (cr0));
+	__asm__ volatile("movl %0, %%cr0" : : "r" (cr0));
 }
 
 static inline void invd(void)
 {
-	asm volatile("invd" : : : "memory");
+	__asm__ volatile("invd" : : : "memory");
 }
 
 static inline void wbinvd(void)
 {
-	asm volatile("wbinvd");
+	__asm__ volatile("wbinvd");
 }
 
 static inline void enable_cache(void)
@@ -194,7 +194,7 @@
  */
 static inline void cpu_relax(void)
 {
-	__asm__ __volatile__("rep; nop" : : : "memory");
+	__asm__ volatile("rep; nop" : : : "memory");
 }
 
 /**
@@ -206,7 +206,7 @@
  */
 static inline __attribute__((always_inline)) void hlt(void)
 {
-	__asm__ __volatile__("hlt" : : : "memory");
+	__asm__ volatile("hlt" : : : "memory");
 }
 
 /** 
@@ -216,7 +216,7 @@
  */
 static inline void clear_memory(void *addr, unsigned long size)
 {
-        asm volatile(
+	__asm__ volatile(
                 "cld \n\t"
                 "rep; stosl\n\t"
                 : /* No outputs */
Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/lapic.h
===================================================================
--- corebootv3-inline_asm_consistent_underscores/include/arch/x86/lapic.h	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/lapic.h	(Arbeitskopie)
@@ -93,19 +93,19 @@
 {
 	switch (size) {
 		case 1:
-			__asm__ __volatile__("xchgb %b0,%1"
+			__asm__ volatile("xchgb %b0,%1"
 				:"=q" (x)
 				:"m" (*__xg(ptr)), "0" (x)
 				:"memory");
 			break;
 		case 2:
-			__asm__ __volatile__("xchgw %w0,%1"
+			__asm__ volatile("xchgw %w0,%1"
 				:"=r" (x)
 				:"m" (*__xg(ptr)), "0" (x)
 				:"memory");
 			break;
 		case 4:
-			__asm__ __volatile__("xchgl %0,%1"
+			__asm__ volatile("xchgl %0,%1"
 				:"=r" (x)
 				:"m" (*__xg(ptr)), "0" (x)
 				:"memory");
Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/k8/dqs.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/northbridge/amd/k8/dqs.c	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/k8/dqs.c	(Arbeitskopie)
@@ -139,13 +139,13 @@
 static inline unsigned long read_cr4(void)
 {
         unsigned long cr4;
-        asm volatile ("movl %%cr4, %0" : "=r" (cr4));
+	__asm__ volatile ("movl %%cr4, %0" : "=r" (cr4));
         return cr4;
 }
 
 static inline void write_cr4(unsigned long cr4)
 {
-        asm volatile ("movl %0, %%cr4" : : "r" (cr4));
+	__asm__ volatile ("movl %0, %%cr4" : : "r" (cr4));
 }
 
 
Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/raminit.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/raminit.c	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/raminit.c	(Arbeitskopie)
@@ -815,7 +815,7 @@
 	post_code(POST_MEM_SETUP_GOOD);
 
 	/* Make sure there is nothing stale in the cache. */
-	/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
+	/* CAR stack is in the cache __asm__ volatile("wbinvd\n"); */
 
 	/* The RAM dll needs a write to lock on so generate a few dummy
 	 * writes. Note: The descriptor needs to be enabled to point at memory.
Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/vsmsetup.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/vsmsetup.c	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/vsmsetup.c	(Arbeitskopie)
@@ -50,7 +50,7 @@
 	u16 entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4;
 	u16 entryLo = (VSA2_ENTRY_POINT & 0xffff);
 
-	__asm__ __volatile__(
+	__asm__ volatile(
 		/* Paranoia -- does ecx get saved? not sure. This is
 		 * the easiest safe thing to do.
 		 */
@@ -148,7 +148,7 @@
 u32 VSA_vrRead(u16 classIndex)
 {
 	unsigned eax, ebx, ecx, edx;
-	asm volatile (
+	__asm__ volatile (
 		"movw	$0x0AC1C, %%dx		\n"
 		"orl	$0x0FC530000, %%eax	\n"
 		"outl	%%eax, %%dx		\n"
@@ -164,7 +164,7 @@
 u32 VSA_msrRead(u32 msrAddr)
 {
 	unsigned eax, ebx, ecx, edx;
-	asm volatile (
+	__asm__ volatile (
 		"movw	$0x0AC1C, %%dx			\n"
 		"movl	$0x0FC530007, %%eax		\n"
 		"outl	%%eax, %%dx				\n"
Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/geodelxinit.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/geodelxinit.c	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/geodelxinit.c	(Arbeitskopie)
@@ -758,7 +758,7 @@
 	GLPCI_init();
 	clock_gating_init();
 
-	__asm__ __volatile__("FINIT\n"); /* TODO: Create finit() function? */
+	__asm__ volatile("FINIT\n"); /* TODO: Create finit() function? */
 
 	printk(BIOS_DEBUG, "Exit %s\n", __FUNCTION__);
 }
Index: corebootv3-inline_asm_consistent_underscores/arch/x86/geodelx/stage1.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/arch/x86/geodelx/stage1.c	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/arch/x86/geodelx/stage1.c	(Arbeitskopie)
@@ -65,8 +65,8 @@
 	 * the data back over itself, and the wbinvd should then 
 	 * flush to memory. Let's see. 
 	 */
-	__asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
-	__asm__ __volatile__ ("wbinvd\n");
+	__asm__ volatile("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
+	__asm__ volatile ("wbinvd\n");
 	banner(BIOS_DEBUG, "Disable_car: done wbinvd");
 	northbridge_init_early();
 	banner(BIOS_DEBUG, "disable_car: done");
Index: corebootv3-inline_asm_consistent_underscores/arch/x86/archtables.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/arch/x86/archtables.c	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/arch/x86/archtables.c	(Arbeitskopie)
@@ -54,7 +54,7 @@
 	memcpy((void*)newgdt, &gdt, num_gdt_bytes);
 	gdtarg.base = newgdt;
 	gdtarg.limit = num_gdt_bytes - 1;
-	__asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg));
+	__asm__ volatile ("lgdt %0\n\t" : : "m" (gdtarg));
 	printk(BIOS_DEBUG,"OK\n");
 }
 #endif
Index: corebootv3-inline_asm_consistent_underscores/arch/x86/amd/k8/stage1.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/arch/x86/amd/k8/stage1.c	(Revision 858)
+++ corebootv3-inline_asm_consistent_underscores/arch/x86/amd/k8/stage1.c	(Arbeitskopie)
@@ -45,7 +45,7 @@
 	 * The solution for geode of using a inline asm memcpy of the stack
 	 * onto itself will not mark the cache tags as dirty on K8.
 	 */
-	__asm__ __volatile__(
+	__asm__ volatile(
 	"	movl %[carbase], %%esi		\n"
 	"	movl %[backuplocation], %%edi	\n"
 	"	movl %[carsizequads], %%ecx	\n"
Index: corebootv3-inline_asm_consistent_underscores/arch/x86/stage1.c
===================================================================
--- corebootv3-inline_asm_consistent_underscores/arch/x86/stage1.c	(Revision 856)
+++ corebootv3-inline_asm_consistent_underscores/arch/x86/stage1.c	(Arbeitskopie)
@@ -117,7 +117,7 @@
 u64 cycles(void)
 {
 	u64 ret;
-	asm volatile ("rdtsc" : "=A" (ret));
+	__asm__ volatile ("rdtsc" : "=A" (ret));
 	return ret;
 }
 


-- 
http://www.hailfinger.org/




From svn at coreboot.org  Sat Sep  6 22:30:26 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  6 Sep 2008 22:30:26 +0200
Subject: [coreboot] r859 - coreboot-v3/util/dtc
Message-ID: <mailman.2034.1355071376.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-09-06 22:30:26 +0200 (Sat, 06 Sep 2008)
New Revision: 859

Modified:
   coreboot-v3/util/dtc/flattree.c
Log:
The .next pointer was written twice for every struct device in
statictree.c. This bug was introduced in r175.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/util/dtc/flattree.c
===================================================================
--- coreboot-v3/util/dtc/flattree.c	2008-09-05 10:29:33 UTC (rev 858)
+++ coreboot-v3/util/dtc/flattree.c	2008-09-06 20:30:26 UTC (rev 859)
@@ -661,8 +661,6 @@
 	}
 	if (tree->next_sibling) 
 		fprintf(f, "\t.sibling = &dev_%s,\n", tree->next_sibling->label);
-	if (tree->next) 
-		fprintf(f, "\t.next = &dev_%s,\n", tree->next->label);
 	/* now do we do next? */
 	/* this will need to do a bus for every child. And, below, we're going to need to find which bus we're on*/
 	/* for now, let's keep it to the minimum that will work, while we see if we like this. */




From stepan at coresystems.de  Sat Sep  6 22:34:09 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 06 Sep 2008 22:34:09 +0200
Subject: [coreboot] [PATCH] v3: make inline asm declarations consistent
In-Reply-To: <48C2D067.4010309@gmx.net>
References: <48C2D067.4010309@gmx.net>
Message-ID: <48C2E941.1020506@coresystems.de>

Carl-Daniel Hailfinger wrote:
> v3 uses all combinations of __asm__, asm, __volatile__, volatile and
> single variations to declare inline asm statements. "asm" is a GNU C
> extension, while volatile is ANSI C. That means:
> - __volatile__ can be replaced by volatile unless you use a pure K&R
> compiler.
> - asm is not a reserved keyword and should be replaced by __asm__.
> As a bonus, grepping for __asm__ returns less hits than asm because asm
> is also used as a normal word in comments.
>
>   
What are the implications of this? I think we should either go __asm__
__volatile__ or asm volatile for the sake of looking at the code without
eye cancer, but not mix it.

We're absolutely gcc specific, so discussing about asm not being
reserved sounds a bit vain. Also, is __asm__ reserved? Reserved by whom?
I know more compilers that know about asm than __asm__ if we're really
trying to become non-GNU-centric.

What's the goal of your patch?

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Sat Sep  6 22:39:25 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  6 Sep 2008 22:39:25 +0200
Subject: [coreboot] r860 - coreboot-v3/util/dtc
Message-ID: <mailman.2035.1355071376.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2008-09-06 22:39:25 +0200 (Sat, 06 Sep 2008)
New Revision: 860

Modified:
   coreboot-v3/util/dtc/flattree.c
Log:
I managed to break dtc while working on PCI bridges:
dtc only uses dev_fn as identifier for a PCI device. That gets us a name
collision if we have the same dev_fn combination on multiple buses.
Either we add a random unique ID to the struct name or we integrate the
path to the parent device as well.
I decided to go for integration of parent device path.

With the following device tree

/{
        cpus {};
        domain at 0 {
                bus at 0 {
                        pci at 0,0 {
                        };
                        pci at 1,1 {
                        };
                        pci at f,0 {
                                bus at 1 {
                                        pci at 0,0 {
                                        };
                                };
                        };
                };
        };
};


we get the old names:
dev_root
dev_cpus
dev_domain_0
dev_bus_0
dev_pci_0_0
dev_pci_1_1
dev_pci_f_0
dev_bus_1
dev_pci_0_0 COLLISION!!!

and the new names:
dev_root
dev_cpus
dev_domain_0
dev_domain_0_bus_0
dev_domain_0_bus_0_pci_0_0
dev_domain_0_bus_0_pci_1_1
dev_domain_0_bus_0_pci_f_0
dev_domain_0_bus_0_pci_f_0_bus_1
dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0

Ron would like shorter names because they only have to be
machine-readable. That's left for another patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/util/dtc/flattree.c
===================================================================
--- coreboot-v3/util/dtc/flattree.c	2008-09-06 20:30:26 UTC (rev 859)
+++ coreboot-v3/util/dtc/flattree.c	2008-09-06 20:39:25 UTC (rev 860)
@@ -1311,8 +1311,22 @@
 labeltree(struct node *tree)
 {
 	struct node *child;
+	char *tmp1;
+	char *tmp2;
 
 	tree->label = clean(tree->name, 1);
+	if (tree->parent && tree->label) {
+		tmp1 = strdup(tree->parent->label);
+		if (strlen(tmp1)) {
+			tmp2 = tree->label;
+			tree->label = malloc(strlen(tmp1) + strlen(tmp2) + 2);
+			strcpy(tree->label, tmp1);
+			strcat(tree->label, "_");
+			strcat(tree->label, tmp2);
+			free(tmp2);
+		}
+		free(tmp1);
+	}
 	
 	if (tree->next_sibling)
 		labeltree(tree->next_sibling);




From c-d.hailfinger.devel.2006 at gmx.net  Sat Sep  6 22:42:38 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Sep 2008 22:42:38 +0200
Subject: [coreboot] [PATCH] v3: more uniqueness in the dtc generated
 struct names
In-Reply-To: <13426df10809050117u31cb592dhde546712f9d22926@mail.gmail.com>
References: <48B87ED7.1030104@gmx.net> <48BF5150.9050804@gmx.net>
	<13426df10809050117u31cb592dhde546712f9d22926@mail.gmail.com>
Message-ID: <48C2EB3E.40904@gmx.net>

On 05.09.2008 10:17, ron minnich wrote:
> On Wed, Sep 3, 2008 at 8:09 PM, Carl-Daniel Hailfinger wrote:
>   
>> Hi Ron,
>>
>> here's my patch proposal for struct device naming again. It has the
>> advantage of adding only 14 lines of code.
>>
>> Regards,
>> Carl-Daniel
>>
>> On 30.08.2008 00:57, Carl-Daniel Hailfinger wrote:
>>     
>>> I managed to break dtc while working on PCI bridges:
>>> dtc only uses dev_fn as identifier for a PCI device. That gets us a name
>>> collision if we have the same dev_fn combination on multiple buses.
>>> [...]
>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>       
>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
> not yet tested. But some test builds look good.
>   

Thanks. Per the discussion in other threads, I committed this as r860.
Feel free to change the naming scheme anytime.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Sat Sep  6 23:02:40 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 06 Sep 2008 23:02:40 +0200
Subject: [coreboot] Cache as RAM - is it possible to execute code in
	cache?
In-Reply-To: <3c66930d0809051608y557b2e68j8f9e56336d463516@mail.gmail.com>
References: <3c66930d0809050045q35b9a373hcf2a6d00da2c2acf@mail.gmail.com>	
	<13426df10809050046h4839f420me48e94f595e1cdd6@mail.gmail.com>	
	<48C0FF74.6070608@gmx.net>	
	<8012472D-CBBA-451C-A009-D7931A33D458@coresystems.de>	
	<48C14D30.5090700@gmx.net> <48C14E0A.2070304@coresystems.de>
	<3c66930d0809051608y557b2e68j8f9e56336d463516@mail.gmail.com>
Message-ID: <48C2EFF0.9000100@coresystems.de>

Jackie Pan wrote:
> I'm very curious about how you achieve this. As Intel's separate L1
> data cache and instruction cache,
> after checking the prog. manual I come to the conclusion that the
> i-cache can only be filled by instruction fetching 
> process(or am i wrong?), when I copy code into the CAR region(i.e.,
> not by caching of the XIP region using MTRR), 
> the data I supplied goes directly into the d-cache, at the same time
> the corresponding line in the i-cache(if any) gets
> invalidated immediately, or more exactly for the CAR case, there's no
> such line in the i-cache at all because there's
> not been any instruction fetching targeting at the CAR region before.
> Thus it seems impossible to synchronize the
> i-cache and d-cache without a RAM as backup.
>
> let me guess, are you implying storing  to another core's cache while
> using MESI for the purpose of synchronizing? 
I don't know much about MESI except it exists. But for CAR as we do it
on Intel CPUs it is essential that we keep all AP cores in Wait for SIPI
state to get them out of the way. They're only re-activated when RAM is
working, at which point we're using ram based semaphores.

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Sat Sep  6 23:22:40 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 06 Sep 2008 23:22:40 +0200
Subject: [coreboot] [PATCH] v3: make inline asm declarations consistent
In-Reply-To: <48C2E941.1020506@coresystems.de>
References: <48C2D067.4010309@gmx.net> <48C2E941.1020506@coresystems.de>
Message-ID: <48C2F4A0.5060109@gmx.net>

On 06.09.2008 22:34, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> v3 uses all combinations of __asm__, asm, __volatile__, volatile and
>> single variations to declare inline asm statements. "asm" is a GNU C
>> extension, while volatile is ANSI C. That means:
>> - __volatile__ can be replaced by volatile unless you use a pure K&R
>> compiler.
>> - asm is not a reserved keyword and should be replaced by __asm__.
>> As a bonus, grepping for __asm__ returns less hits than asm because asm
>> is also used as a normal word in comments.
>>
>>     
> What are the implications of this? I think we should either go __asm__
> __volatile__ or asm volatile for the sake of looking at the code without
> eye cancer, but not mix it.
>
> We're absolutely gcc specific, so discussing about asm not being
> reserved sounds a bit vain. Also, is __asm__ reserved? Reserved by whom?
> I know more compilers that know about asm than __asm__ if we're really
> trying to become non-GNU-centric.
>
> What's the goal of your patch?
>   

Two goals:
1. __volatile__ is pointless since 1983 (ANSI-C). No idea why anyone
uses it.
2. Neither __asm__ nor asm are reserved. Grepping for asm turns up lots
of stuff that is not inline asm, so using __asm__ eases grepping.

If you prefer asm volatile, tell me. I'll prepare an updated patch.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sun Sep  7 00:04:25 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Sep 2008 00:04:25 +0200
Subject: [coreboot] [PATCH] Add VIA VT8237S support
In-Reply-To: <48C178B6.6060006@assembler.cz>
References: <48C065B9.6020605@assembler.cz> <48C09771.9010000@onelabs.com>
	<48C178B6.6060006@assembler.cz>
Message-ID: <48C2FE69.5030505@gmx.net>

On 05.09.2008 20:21, Rudolf Marek wrote:
> As Committed revision 3567.

That checkin broke EPIA-CN compilation. See
http://qa.coreboot.org/log_buildbrd.php?revision=3567&device=epia-cn&vendor=via
for details.

Any idea how to fix it up?

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Sun Sep  7 00:25:53 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Sep 2008 15:25:53 -0700
Subject: [coreboot] [PATCH] Add VIA VT8237S support
In-Reply-To: <48C2FE69.5030505@gmx.net>
References: <48C065B9.6020605@assembler.cz> <48C09771.9010000@onelabs.com>
	<48C178B6.6060006@assembler.cz> <48C2FE69.5030505@gmx.net>
Message-ID: <13426df10809061525p22b0d73fj1f3f6616c2546e61@mail.gmail.com>

On Sat, Sep 6, 2008 at 3:04 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 05.09.2008 20:21, Rudolf Marek wrote:
>> As Committed revision 3567.
>
> That checkin broke EPIA-CN compilation. See
> http://qa.coreboot.org/log_buildbrd.php?revision=3567&device=epia-cn&vendor=via
> for details.
>
> Any idea how to fix it up?


Unknown attribute:packed

not sure where this is, but why are we using packed anyway? it's just
asking for trouble.

ron



From stepan at coresystems.de  Sun Sep  7 00:48:56 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 07 Sep 2008 00:48:56 +0200
Subject: [coreboot] was: wiki account request (for GRUB 2) - now: FILO
 integration into libpayload
In-Reply-To: <32d0a575f02cdbf46ac582bb5a3e988c@imap.1and1.com>
References: <20080905150817.GA11396@thorin>
	<20080905154229.GD31555@cosmic.amd.com>
	<102a5694a717575e13c04245c84a818f@imap.1and1.com>
	<48C16235.7020707@coresystems.de>
	<522432352237bd8ca4d0a0fa9d2b22f4@imap.1and1.com>
	<48C16999.6040109@coresystems.de>
	<5f0fccd1f2db3f42764fe11de1ed1939@imap.1and1.com>
	<32d0a575f02cdbf46ac582bb5a3e988c@imap.1and1.com>
Message-ID: <48C308D8.4060600@coresystems.de>

Joseph Smith wrote:
> Looks like the nvram page on the wiki says:
>
> Some of the fields are used by payloads - for instance all the fields that
> start with 'boot_' in the list above. FILO does not use those fields
> currently, but Etherboot does (someone confirm this please!). 
>   
Any payload using libpayload can read arbitrary variables listed in
cmos.layout with the functions libpayload provides.

The documentation there is quite outdated.

See
http://tracker.coreboot.org/trac/filo/browser/trunk/filo/main/grub/builtins.c#L282
for an example.

> Does this need to be updated?? Has it been confirmed?
Yes, I think this should be updated.



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Sun Sep  7 01:25:17 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Sep 2008 01:25:17 +0200
Subject: [coreboot]  Tyan S2892 lspci
Message-ID: <48C3115D.1070709@gmx.net>

Hi Myles,

could you please run
lspci -tvn
lspci -nnvvx
both under coreboot and proprietary BIOS on your S2892? We're trying to
figure out how to best represent the multiple link structure of that
board in our v3 dts.

Thanks!
Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sun Sep  7 01:54:36 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Sep 2008 01:54:36 +0200
Subject: [coreboot]  link representation in v3 dts
Message-ID: <48C3183C.6050306@gmx.net>

Since link representation is a difficult topic to understand and present
cleanly, I tried to use the v2 S2892 Config.lb into a v3 dts. Attached
are a shortened version of the v2 Config.lb and the mostly matching v3 dts.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

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From bari at onelabs.com  Sun Sep  7 03:31:10 2008
From: bari at onelabs.com (bari)
Date: Sat, 06 Sep 2008 20:31:10 -0500
Subject: [coreboot] [PATCH] Add VIA VT8237S support
In-Reply-To: <48C2FE69.5030505@gmx.net>
References: <48C065B9.6020605@assembler.cz> <48C09771.9010000@onelabs.com>
	<48C178B6.6060006@assembler.cz> <48C2FE69.5030505@gmx.net>
Message-ID: <48C32EDE.9080306@onelabs.com>

Carl-Daniel Hailfinger wrote:
> On 05.09.2008 20:21, Rudolf Marek wrote:
>   
>> As Committed revision 3567.
>>     
>
> That checkin broke EPIA-CN compilation. See
> http://qa.coreboot.org/log_buildbrd.php?revision=3567&device=epia-cn&vendor=via
> for details.
>
> Any idea how to fix it up?
>
> Regards,
> Carl-Daniel
>   
Lets fix this and get the CAR patch for C7 in for V2 so we can all use GCC.

-Bari



From bari at onelabs.com  Sun Sep  7 03:57:11 2008
From: bari at onelabs.com (bari)
Date: Sat, 06 Sep 2008 20:57:11 -0500
Subject: [coreboot] VIA C7 + CN700 + VT8237r boards are back in stock $59.99
Message-ID: <48C334F7.3050306@onelabs.com>


For anyone looking to develop with the VIA C7 + CN700 + VT8237r

The pc2500e boards are back in stock:
http://www.clubit.com/product_detail.cfm?itemno=A4842001

-Bari



From r.marek at assembler.cz  Sun Sep  7 00:49:58 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Sep 2008 00:49:58 +0200
Subject: [coreboot] [PATCH] Add VIA VT8237S support
In-Reply-To: <13426df10809061525p22b0d73fj1f3f6616c2546e61@mail.gmail.com>
References: <48C065B9.6020605@assembler.cz>
	<48C09771.9010000@onelabs.com>	<48C178B6.6060006@assembler.cz>
	<48C2FE69.5030505@gmx.net>
	<13426df10809061525p22b0d73fj1f3f6616c2546e61@mail.gmail.com>
Message-ID: <48C30916.40409@assembler.cz>

> not sure where this is, but why are we using packed anyway? it's just
> asking for trouble.


Because that structure maps directly to ROM layout. Maybe it will work fine 
without it - dont know.

Rudolf



From rminnich at gmail.com  Sun Sep  7 04:29:43 2008
From: rminnich at gmail.com (ron minnich)
Date: Sat, 6 Sep 2008 19:29:43 -0700
Subject: [coreboot] link representation in v3 dts
In-Reply-To: <48C3183C.6050306@gmx.net>
References: <48C3183C.6050306@gmx.net>
Message-ID: <13426df10809061929s656f895ey14477d5e63bf2362@mail.gmail.com>

don't worry about that children_as_links thing, I have a much simpler
fix now that your naming fix is in. I hope to get it out next week.
It's actually somewhat tested ;-)

Other than that you're very, very close.

ron



From svn at coreboot.org  Sun Sep  7 05:14:27 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  7 Sep 2008 05:14:27 +0200
Subject: [coreboot] r3569 - trunk/util/flashrom
Message-ID: <mailman.2036.1355071376.16123.coreboot@coreboot.org>

Author: stuge
Date: 2008-09-07 05:14:27 +0200 (Sun, 07 Sep 2008)
New Revision: 3569

Modified:
   trunk/util/flashrom/udelay.c
Log:
flashrom: Debug print actual time base calculated by myusec_calibrate_delay()

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/util/flashrom/udelay.c
===================================================================
--- trunk/util/flashrom/udelay.c	2008-09-05 21:23:02 UTC (rev 3568)
+++ trunk/util/flashrom/udelay.c	2008-09-07 03:14:27 UTC (rev 3569)
@@ -55,6 +55,12 @@
 	// compute one microsecond. That will be count / time
 	micro = count / timeusec;
 
-	printf_debug("%ldM loops per second. ", (unsigned long)micro);
+	gettimeofday(&start, 0);
+	myusec_delay(100);
+	gettimeofday(&end, 0);
+	timeusec = 1000000 * (end.tv_sec - start.tv_sec) +
+	    (end.tv_usec - start.tv_usec);
+	printf_debug("%ldM loops per second, 100 myus = %ld us. ",
+	    (unsigned long)micro, timeusec);
 	printf("OK.\n");
 }




From info at coresystems.de  Sun Sep  7 05:59:34 2008
From: info at coresystems.de (coreboot information)
Date: Sun, 07 Sep 2008 05:59:34 +0200
Subject: [coreboot] r3569 build service
Message-ID: <E1KcBR0-0002TK-78@khepri.openbios.org>

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "stuge" checked in revision 3569 to
the coreboot source repository and caused the following 
changes:

Change Log:
flashrom: Debug print actual time base calculated by myusec_calibrate_delay()

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3569&device=epia-cn&vendor=via


If something broke during this checkin please be a pain 
in stuge's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From stepan at coresystems.de  Sun Sep  7 09:49:00 2008
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 07 Sep 2008 09:49:00 +0200
Subject: [coreboot] r3569 - trunk/util/flashrom
Message-ID: <48C3876C.8000708@coresystems.de>

svn at coreboot.org wrote:
> Author: stuge
> Date: 2008-09-07 05:14:27 +0200 (Sun, 07 Sep 2008)
> New Revision: 3569
>
> Modified:
>    trunk/util/flashrom/udelay.c
> Log:
> flashrom: Debug print actual time base calculated by myusec_calibrate_delay()
>
> Signed-off-by: Peter Stuge <peter at stuge.se>
> Acked-by: Peter Stuge <peter at stuge.se>
>
>
> Modified: trunk/util/flashrom/udelay.c
> ===================================================================
> --- trunk/util/flashrom/udelay.c	2008-09-05 21:23:02 UTC (rev 3568)
> +++ trunk/util/flashrom/udelay.c	2008-09-07 03:14:27 UTC (rev 3569)
> @@ -55,6 +55,12 @@
>  	// compute one microsecond. That will be count / time
>  	micro = count / timeusec;
>  
> -	printf_debug("%ldM loops per second. ", (unsigned long)micro);
> +	gettimeofday(&start, 0);
> +	myusec_delay(100);
> +	gettimeofday(&end, 0);
> +	timeusec = 1000000 * (end.tv_sec - start.tv_sec) +
> +	    (end.tv_usec - start.tv_usec);
> +	printf_debug("%ldM loops per second, 100 myus = %ld us. ",
> +	    (unsigned long)micro, timeusec);
>  	printf("OK.\n");
>  }
>   

I think that reads really weird. What's myus supposed to be, except an
ancient greek city?

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Sun Sep  7 19:18:10 2008
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  7 Sep 2008 19:18:10 +0200
Subject: [coreboot] r861 - coreboot-v3/include
Message-ID: <mailman.2037.1355071376.16123.coreboot@coreboot.org>

Author: uwe
Date: 2008-09-07 19:18:10 +0200 (Sun, 07 Sep 2008)
New Revision: 861

Modified:
   coreboot-v3/include/spd.h
Log:
Port some of the recent SPD DDR2 #defines from v2 to v3 (trivial).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: coreboot-v3/include/spd.h
===================================================================
--- coreboot-v3/include/spd.h	2008-09-06 20:39:25 UTC (rev 860)
+++ coreboot-v3/include/spd.h	2008-09-07 17:18:10 UTC (rev 861)
@@ -75,6 +75,17 @@
 #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME      33 /* Command and address signal input hold time */
 #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME    34 /* Data signal input setup time */
 #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME     35 /* Data signal input hold time */
+#define SPD_WRITE_RECOVERY_TIME             36 /* Write recovery time (tWR) */
+#define SPD_INT_WRITE_TO_READ_DELAY         37 /* Internal write to read command delay (tWTR) */
+#define SPD_INT_READ_TO_PRECHARGE_DELAY     38 /* Internal read to precharge command delay (tRTP) */
+#define SPD_MEM_ANALYSIS_PROBE_PARAMS       39 /* Memory analysis probe characteristics */
+#define SPD_BYTE_41_42_EXTENSION            40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
+#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH     41 /* Minimum active to active auto refresh (tRCmin) */
+#define SPD_MIN_AUTO_REFRESH_TO_ACT         42 /* Minimum auto refresh to active/auto refresh (tRFC) */
+#define SPD_MAX_DEVICE_CYCLE_TIME           43 /* Maximum device cycle time (tCKmax) */
+#define SPD_MAX_DQS_DQ_SKEW                 44 /* Maximum skew between DQS and DQ (tDQSQ) */
+#define SPD_MAX_READ_DATAHOLD_SKEW          45 /* Maximum read data-hold skew factor (tQHS) */
+#define SPD_PLL_RELOCK_TIME                 46 /* PLL relock time */
 #define SPD_SPD_DATA_REVISION_CODE          62 /* SPD data revision code */
 #define SPD_CHECKSUM_FOR_BYTES_0_TO_62      63 /* Checksum for bytes 0-62 */
 #define SPD_MANUFACTURER_JEDEC_ID_CODE      64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
@@ -107,6 +118,7 @@
 #define SPD_MEMORY_TYPE_SGRAM_DDR        6
 #define SPD_MEMORY_TYPE_SDRAM_DDR        7
 #define SPD_MEMORY_TYPE_SDRAM_DDR2       8
+#define SPD_MEMORY_TYPE_SDRAM_DDR3       0xb
 
 /* SPD_MODULE_VOLTAGE values. */
 #define SPD_VOLTAGE_TTL                  0 /* 5.0 Volt/TTL */
@@ -130,6 +142,11 @@
 #define SPD_CAS_LATENCY_3_5              0x20
 #define SPD_CAS_LATENCY_4_0              0x40
 
+#define SPD_CAS_LATENCY_DDR2_3		(1 << 3)
+#define SPD_CAS_LATENCY_DDR2_4		(1 << 4)
+#define SPD_CAS_LATENCY_DDR2_5		(1 << 5)
+#define SPD_CAS_LATENCY_DDR2_6		(1 << 6)
+
 /* SPD_SUPPORTED_BURST_LENGTHS values. */
 #define SPD_BURST_LENGTH_1               1
 #define SPD_BURST_LENGTH_2               2
@@ -145,4 +162,3 @@
 u8 spd_read_byte(u16 device, u8 address);
 
 #endif /* _SPD_H_ */
-




From peter at stuge.se  Sun Sep  7 19:50:29 2008
From: peter at stuge.se (Peter Stuge)
Date: Sun, 7 Sep 2008 19:50:29 +0200
Subject: [coreboot] suspend/resume in v3
Message-ID: <20080907175029.25122.qmail@stuge.se>

Discussing on IRC, ruik pointed out that we of course have to
consider suspend and resume in v3.

He wrote some great pointers on the topic today and I'm pasting here
for archival and as food for thought.

<ruik> CareBear\: the S3 works this way:
<ruik> 1) get the wakeup info from chipset
<ruik> 2) in intraphase ask the memory to go out of self refresh (skip train)
<ruik> 3) do coreboot chipset init as usual
<ruik> 4) when creating ACPI tables look to that place, in one table there will be OS waking vector
<ruik> 5) after all done, jump to OS instead of payload, switch A20 on go to real mode and jump
<ruik> 6) do this all steps in reserved memory, do not corrupt system memory used by OS
<ruik> 7) minor fix for ACPI dsdt is needed, just one line ;)
<ruik> CareBear\: just add one line to SLP
<ruik> similar to bit for S5 and S0
<ruik> one more caveat
<ruik> make sure that suspend signal clock from SB is understood by superIO
<ruik> so superIO wont cut RAM power

I think 6) in particular deserves some consideration.


//Peter



From peter at stuge.se  Sun Sep  7 20:17:43 2008
From: peter at stuge.se (Peter Stuge)
Date: Sun, 7 Sep 2008 20:17:43 +0200
Subject: [coreboot] r3569 - trunk/util/flashrom
In-Reply-To: <48C3876C.8000708@coresystems.de>
References: <48C3876C.8000708@coresystems.de>
Message-ID: <20080907181743.8838.qmail@stuge.se>

Stefan Reinauer wrote:
> > +	printf_debug("%ldM loops per second, 100 myus = %ld us. ",
> > +	    (unsigned long)micro, timeusec);
> 
> I think that reads really weird. What's myus supposed to be, except
> an ancient greek city?

"my useconds" derived from myusec_delay()


//Peter



From rminnich at gmail.com  Sun Sep  7 20:40:31 2008
From: rminnich at gmail.com (ron minnich)
Date: Sun, 7 Sep 2008 11:40:31 -0700
Subject: [coreboot] suspend/resume in v3
In-Reply-To: <20080907175029.25122.qmail@stuge.se>
References: <20080907175029.25122.qmail@stuge.se>
Message-ID: <13426df10809071140t79811963i40706d158995ad85@mail.gmail.com>

great info.

I'd never considered any of this, which shows my cluster bias :-)

OK where do we want v3 reserved memory?


ron



From c-d.hailfinger.devel.2006 at gmx.net  Sun Sep  7 21:18:34 2008
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 07 Sep 2008 21:18:34 +0200
Subject: [coreboot] suspend/resume in v3
In-Reply-To: <20080907175029.25122.qmail@stuge.se>
References: <20080907175029.25122.qmail@stuge.se>
Message-ID: <48C4290A.50506@gmx.net>

Rudolf, thanks for giving us that overview. I see that it is a
description of S3 wakeup. Could you perhaps supplement that with a
description of S3 suspend?

Peter, thanks for preserving that info.

On 07.09.2008 19:50, Peter Stuge wrote:
> Discussing on IRC, ruik pointed out that we of course have to
> consider suspend and resume in v3.
>
> He wrote some great pointers on the topic today and I'm pasting here
> for archival and as food for thought.
>
> <ruik> CareBear\: the S3 works this way:
> <ruik> 1) get the wakeup info from chipset
> <ruik> 2) in intraphase ask the memory to go out of self refresh (skip train)
>   

intraphase is initram? Would it make sense to have a fast path in
initram for this?

> <ruik> 3) do coreboot chipset init as usual
>   

What about BARs which have been moved by the OS? Should we initialize
them to the values last used by the OS or should we use the values
calculated automatically at startup?

> <ruik> 4) when creating ACPI tables look to that place, in one table there will be OS waking vector
> <ruik> 5) after all done, jump to OS instead of payload, switch A20 on go to real mode and jump
> <ruik> 6) do this all steps in reserved memory, do not corrupt system memory used by OS
> <ruik> 7) minor fix for ACPI dsdt is needed, just one line ;)
> <ruik> CareBear\: just add one line to SLP
> <ruik> similar to bit for S5 and S0
> <ruik> one more caveat
> <ruik> make sure that suspend signal clock from SB is understood by superIO
> <ruik> so superIO wont cut RAM power
>
> I think 6) in particular deserves some consideration.
>   

6) is really easy with v3. A lot easier than with v2. I think I wrote a
design doc about that one year ago.

However, I am surprised that the SuperI/O acts as a power supply for RAM.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From r.marek at assembler.cz  Sun Sep  7 21:22:06 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Sep 2008 21:22:06 +0200
Subject: [coreboot] suspend/resume in v3
In-Reply-To: <13426df10809071140t79811963i40706d158995ad85@mail.gmail.com>
References: <20080907175029.25122.qmail@stuge.se>
	<13426df10809071140t79811963i40706d158995ad85@mail.gmail.com>
Message-ID: <48C429DE.8050103@assembler.cz>

> I'd never considered any of this, which shows my cluster bias :-)
> 
> OK where do we want v3 reserved memory?

I think we can reserve last MB of RAM, where we will copy coreboot and 
stacks/heaps. If anyone is worried about the "waste" of last MB. I think we can 
hotplug the memory back to OS through ACPI, got some experimental ASL code, but 
kernel panicked. Maybe it is there some glitch.

The tables might not be written for second time, when resuming because they are 
there already ;)

The code absolutely _must_ _not_ write to any other memory. No strange AP stacks 
in random 0 - 640kb ;)

There is no need for SMM code.

Here is mine v2 suspend/resume 
http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html


Rudolf







From r.marek at assembler.cz  Sun Sep  7 21:28:54 2008
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 07 Sep 2008 21:28:54 +0200
Subject: [coreboot] suspend/resume in v3
In-Reply-To: <48C4290A.50506@gmx.net>
References: <20080907175029.25122.qmail@stuge.se> <48C4290A.50506@gmx.net>
Message-ID: <48C42B76.4080707@assembler.cz>

Carl-Daniel Hailfinger napsal(a):
> Rudolf, thanks for giving us that overview. I see that it is a
> description of S3 wakeup. Could you perhaps supplement that with a
> description of S3 suspend?

S3 suspend is just this line in ACPI ASL:

+Name (\_S3, Package () {0x01, 0x01, 0x00, 0x00 })

OS will write the 0x1 to SLP register in ACPI PMIO. OS will take care of cache 
flushes etc. The write to this register will cause the SMAF Stop grant message 
to be send to CPU, CPU will disconnect the bus, and SB will sequence all signals 
  similar to power off. The only problem is suspend signal which goes to 
superIO, which is needed not to cut power to RAM.

In other words, you dont need to preserve anything/no need for SMM. ACPI allows 
that the hardware is in same state as it was during normal power on (for HW 
managed by BIOS).

If needed, writing to SLP register might be traped by SMM, and BIOS can save 
some values to NVRAM regs, sometimes found in chipsets (memory timing etc) to 
ease the startup. But we dont need that we are fast anyway.

Some extra hw clobber might be done in ACPI ASL code, there are methods which 
will be called during wakeup or during resume.

http://acpi.info/spec30a.htm

Rudolf




From svn at coreboot.org  Sun Sep  7 21:54:36 2008
From: svn at coreboot.org (coreboot)
Date: Sun, 07 Sep 2008 19:54:36 -0000
Subje