[coreboot] v2: [RFC] Dynamic RAM detection for intel/i440bx

Mats Erik Andersson mats.andersson at gisladisker.se
Sun Sep 14 15:19:12 CEST 2008

Hello all,

I send a patch which is not intended for insertion as is,
but I have to draw the line somewhere in order to get your

The patch alters


and it implements dynamic calculation of the registers
DRB#, RPS and PGPOL. It does this using alternate methods,
chosen by macro switches in the beginning of the file.

In order to successfully compile the new source, it is
unfortunately necessary to use Romcc with optimisation
"-mcpu=p2" to provide scratch registers for normal/fallback,
and also "-O2" to shrink the fallback image. A script "optim.sh",
that mends the makefiles, is appended to this message.

I have successfully (in the sense of complete image build) 
done this alteration for all relevant mainboards in the
source tree:

a-trend/atc-6240         (needs one PRINT_DEBUG less!)

and for my own mainboard msi/ms6147 I can actually boot into
Filo with many different combinations and positions of SDRAM
devices. However, there are still some issues with timings,
which lead to the strange phenomenon that one particular
double sided 128 MB card in my possession, boots well enough
into Filo when positioned in DIMM1, but cannot enter the second
phase of Coreboot when used in DIMM0. Other 128 MB cards work
in both positions. These differences are probably due to my
incomplete understanding of the northbridge register MBSC, as
well as the buffer strength bits in NBXCFG.

Since ms6147 only has two DIMM-slots, I have not been able to
test the patch for use with USE_DIMM2 or USE_DIMM3 activated.
The function do_ram_command() has two outcommented work arounds
in order to activate the different RAM position, but a true dynamic
code has not yet been taken into consideration. 

I now desire other people to test this code against their
mainboards, in order that we (or mainly I) could get indications
as to push forward to choose one of the methods the code
offers for its SPD-detection, and to provide me with more
information on SDRAM timings that do not work with the present
values in MBSC and NBXCFG. The values present now are _not_
the only values I have _inconclusively_ tried!

I welcome all feedback. The 48 first SPD-bytes of malfunctioning
SDRAM cards would be most valuable. Testers should take care
to add one or more read32() inside do_ram_command() in order
to perform a read in any additional memory bank. That read32()
bears the sole responsibility of awakening the SDRAM chips,
as this mechanism is independent of any configuration the
northbridge i440bx gets from any code for dynamic detection.

Best regards and with the best intents,

Mats Erik Andersson

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