[coreboot] flashrom: [PATCH] Fully working EON EN29F002NT

Tim ter Laak timl at scintilla.utwente.nl
Mon Sep 29 21:39:37 CEST 2008

On Mon, 29 Sep 2008, ron minnich wrote:

> note to all: we did find, long ago, on  one mainboard with one
> particular chip, that a POST cycle at the wrong time would hang
> flashrom. The issue is that every POST cycle is a failed cycle, in the
> sense that no device ever responds. The chipset timeout cycle was long
> enough to glitch the timing.
> Linux does indeed have some POST cycles in the kernel. So, it is
> possible that on some chipsets, now and in the future, this could be
> an issue. The best part is that the actual problem can appear or not
> appear depending on chipset, revision, and bios revision. Isn't that
> fun?

Since kernel version 2.6.25 (I believe) it is possible switch off (most 
of?) the POST cycles in the kernel. In the menuconfig, the option can be 
found under Kernel Hacking -> IO delay type. Available options are to use 
port 0x80 (POST), port 0xed, use the kernel's internal udelay function, or 
to make the delays a NOP since they are generally not necessary anymore on 
current hardware.

The default for i386 is still to use port 0x80, but that may improve over 
time (after it has received more testing). And we have a way to try 
to solve the problem if you suspect being bitten by it now.

Kind regards,

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