From uwe at hermann-uwe.de  Wed Apr  1 03:45:21 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Wed, 1 Apr 2009 03:45:21 +0200
Subject: [coreboot] [PATCH] flashrom: README / manpage fixes
Message-ID: <20090401014520.GC22189@greenwood>

See patch.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From joe at settoplinux.org  Wed Apr  1 04:22:16 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 31 Mar 2009 22:22:16 -0400
Subject: [coreboot] Dell latitude c610
In-Reply-To: <195019370903311629p60853b3bgdfb19b742736f5b9@mail.gmail.com>
References: <195019370903300926u64e8cdabr7085fe145f8b174d@mail.gmail.com>
	<8ee436c75286503af69607d4841c6692@imap.1and1.com>
	<195019370903311629p60853b3bgdfb19b742736f5b9@mail.gmail.com>
Message-ID: <d07723387fb75a3bda915b236ef98cb0@imap.1and1.com>




On Wed, 1 Apr 2009 01:29:30 +0200, Michal Janke <m.yankee at gmail.com> wrote:
> 2009/3/31 Joseph Smith <joe at settoplinux.org>:
>>
>> Hello, Looks like an i830 chipset laptop. I would love to see coreboot
>> running on an i830 chipset laptop. I wrote the i830 code (with lots of
> help
>> from everyone here:-) ) and would be glad to help in any way that I can.
>> Looks like the first thing is to get your SMSC LPC47N252 SuperIO
> working.
>> Most of the SMSC LPC47* are closely related from a programming stand
> point.
>> I think everything else is supported by coreboot. The only concerns I
> have
>> is with the graphics (LCD) and battery charging. See:
>> http://www.coreboot.org/Laptop
>> If your willing to give it a go, I woud be glad to support you any way I
>> can. If you want some base code to start with you can use the RCA RM4100
>> (i830 based set-top-box). Hope that helps.
>>
> 
> Thanks for your reply, Joseph. Sounds quite encouraging. Could you
> suggest, what I can start with? Qemu maybe? 
> 
If you want to start with Qemu, to get familiar with coreboot, that would
be good.
But if your really serious about this and want to dive right into real
hardware the first thing you need to do is get your SMSC LPC47N252 running,
I suggest downloading the datasheet and a few other LPC47* datasheets that
are supported to find the closest matching one. If your serious about this
get ready to send some time reading datasheets. Even though sometimes they
can be dry reading they are a wealth of information. Once you get your
SuperIO running you will be able to get serial console output, So you can
see what is happening.

You are going to want to socket your FWH chip and even order a few extras
from your favorite electronics supplier (ex: www.mouser.com or
www.newark.com).

> Do you think there would
> be a need for a lot of programming?
>
Well there is always room for improvement, but most of the coded needed has
already been laid down for you.

> I hope I would be able to handle this. Any I will surely need quite
> some help... It's been quite a while since I last wrote any
> significant portion of code.
>
No problem I am a novice programmer, I think I just have a good
understanding of how things work. And, with a little help from my Peers, I
am able to translate that understanding into code.

> 
> What did you mean I should look for at http://www.coreboot.org/Laptop?
>
Ah, I guess the page has change a little since the last time I looked at
it. As I remember from our discussions about laptops there are a few
mysteries yet to be discovered:

1. What controls battery charging
2. Blacklight control
3. Open / close lid sleep functions
4. Graphics / LVDS (LCD chip) control

I believe the first three can be and already may be a part of ACPI. The
fourth depends on how your VGA is setup. It appears you have this:

01:00.0 VGA compatible controller: ATI Technologies Inc Radeon Mobility M6
LY

It is an AGP card from the device number. You may have a seperate VGA ROM
for the ATI card, so the fourth may not even be an issue?

Anyone else want to touch on the mysteries of laptops?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From Zheng.Bao at amd.com  Wed Apr  1 04:50:09 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Wed, 1 Apr 2009 10:50:09 +0800
Subject: [coreboot] Micro code for 1022h 01000095h
Message-ID: <DD1CC71B621B004FA76856E5129D6B1702871384@sbjgexmb1.amd.com>

This patch applies for DR-B2 and B3.


The patch file is for RFC requirement. Just copy the header file to
src/cpu/amd/model_10xxx/


Signed-off-by: Zheng Bao <zheng.bao at amd.com>


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From m.yankee at gmail.com  Wed Apr  1 01:29:30 2009
From: m.yankee at gmail.com (Michal Janke)
Date: Wed, 1 Apr 2009 01:29:30 +0200
Subject: [coreboot] Dell latitude c610
In-Reply-To: <8ee436c75286503af69607d4841c6692@imap.1and1.com>
References: <195019370903300926u64e8cdabr7085fe145f8b174d@mail.gmail.com>
	<8ee436c75286503af69607d4841c6692@imap.1and1.com>
Message-ID: <195019370903311629p60853b3bgdfb19b742736f5b9@mail.gmail.com>

2009/3/31 Joseph Smith <joe at settoplinux.org>:
>
> Hello, Looks like an i830 chipset laptop. I would love to see coreboot
> running on an i830 chipset laptop. I wrote the i830 code (with lots of help
> from everyone here:-) ) and would be glad to help in any way that I can.
> Looks like the first thing is to get your SMSC LPC47N252 SuperIO working.
> Most of the SMSC LPC47* are closely related from a programming stand point.
> I think everything else is supported by coreboot. The only concerns I have
> is with the graphics (LCD) and battery charging. See:
> http://www.coreboot.org/Laptop
> If your willing to give it a go, I woud be glad to support you any way I
> can. If you want some base code to start with you can use the RCA RM4100
> (i830 based set-top-box). Hope that helps.
>

Thanks for your reply, Joseph. Sounds quite encouraging. Could you
suggest, what I can start with? Qemu maybe? Do you think there would
be a need for a lot of programming?
I hope I would be able to handle this. Any I will surely need quite
some help... It's been quite a while since I last wrote any
significant portion of code.

What did you mean I should look for at http://www.coreboot.org/Laptop?
I didn't notice anything much related to my hardware there. Probably I
do not yet associate the therms with each other too well.



From nuessle at uni-hd.de  Wed Apr  1 09:13:08 2009
From: nuessle at uni-hd.de (Mondrian Nuessle)
Date: Wed, 01 Apr 2009 09:13:08 +0200
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
Message-ID: <49D31404.1070603@uni-hd.de>

>> thank you very much for your patch. Do you happen to know if the component's name is HT2100 or HT21000? Just to make sure we have it in the repository correctly.
> The naming in the patch looks right. Broadcom refers to it as HT-2100
> and as both HT-2100 and BCM21000 in the datasheet (often as "BCM21000
> (HT-2100)" ).
that's my understanding, too.
-- 
 Dr. Mondrian Nuessle
 Phone: +49 621 181 2717          University of Heidelberg
 Fax:   +49 621 181 2713          Computer Architecture Group
 mailto:nuessle at uni-hd.de         http://ra.ziti.uni-heidelberg.de



From vinuxes at gmail.com  Wed Apr  1 12:27:47 2009
From: vinuxes at gmail.com (vinuxes gmail)
Date: Wed, 1 Apr 2009 15:57:47 +0530
Subject: [coreboot] flashrom fails to write/erase on VIA VT8237
In-Reply-To: <49D1A3A7.7050703@gmail.com>
References: <49D05438.4040102@gmail.com> <49D09607.6010808@gmail.com>
	<20090330115759.6344.qmail@stuge.se> <49D19BAE.3060009@gmail.com>
	<20090331043750.4384.qmail@stuge.se> <49D1A3A7.7050703@gmail.com>
Message-ID: <fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>

Hello Peter,
Is there something that i can look into? or any pointers?
Please help!

Rgds,
Vinod

On Tue, Mar 31, 2009 at 10:31 AM, vinuxesgmail <vinuxes at gmail.com> wrote:

> Peter,
>   I am stuck with the same error even after applying the new patch. Here's
> the command output:
> {-------------------
> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E          Calibrating
> delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> Found board "Portwell PPAP-2020VL", enabling flash write... OK.
> Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
> Erasing flash chip... ERASE FAILED!
> FAILED!
> ERROR at 0x00000000: Expected=0xff, Read=0x49
> -------------------
> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "VIA VT8237", enabling flash write... OK.
> Found board "Portwell PPAP-2020VL", enabling flash write... OK.
> Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
> Flash image seems to be a legacy BIOS. Disabling checks.
> ERASE FAILED!
> -------------------}
>
> Please guide me further.
>
> Regards,
> Vinod
>
> Peter Stuge wrote:
>
>> Gah! Sorry. Here it is.
>>
>>
>> //Peter
>>
>>
>
>
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From c-d.hailfinger.devel.2006 at gmx.net  Wed Apr  1 12:44:59 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 01 Apr 2009 12:44:59 +0200
Subject: [coreboot] coreboot v4.1
Message-ID: <49D345AB.6030808@gmx.net>

[Distribution to news outlets is encouraged.]

I'm happy to announce that today coreboot v4.1 has been released.

Besides being totally redesigned, it is super-fast, handles almost every
existing chipset, opens our codebase to contributors without lowlevel C
skills and is generally something to be celebrated. Not to mention the
environmental friendliness and promotion of world peace.

Features include, but are not limited to:

- LARROMFS-NG, allowing code and configuration storage in the ROM
without risking accidental reflashes. With its clean and simple design,
you can store hundreds of different file types easily in the ROM, each
of them being handled by a different plugin.

- SQL-based chipset programming. Gone are the days where you had to
differentiate between accessing PCI regs via struct device, u32 or
device_t variants. Now you can use statements like:
SELECT val_32bit FROM pci WHERE buslocation="badc:0f:fe.e" AND
configbytenumber=00;
or the even simpler
SELECT val_32bit FROM pci NATURAL JOIN configbytes WHERE
buslocation="badc:0f:fe.e" AND configbytename="Vendor ID";
Changing PCI config space follows similar rules.

- A SQL interpreter in coreboot which handles all chipset code. This SQL
interpreter combines the clarity of obfuscated FORTH with the speed of
unoptimized SQL.

- Self-modifying code! As we all know, self-modifying code has less bugs
because any given bug disappears after the code has been modified often
enough. Plus, this is a good way to exercise CPUs to detect hardware
problems more easily.

- Fancy linker scripts. LARROMFS-NG is the next generation archiving
solution for all our needs because it does not rely on inherently
bug-prone C code. LARROMFS-NG is implemented as a really big and
all-encompassing set of linker scripts which can even link new linkers
together which reinterpret these linker scripts.

- New plugin architecture. Coreboot v4.1 will faithfully execute any and
all code presented on any device attached to the board. Due to that,
trojanizing computers becomes a piece of cake, freeing up the precious
time of the intelligence community for more pressing problems like world
peace.

- Multi-language error messages. Although chinese error messages were a
bit difficult to store in 7-bit ASCII, we created a lossy compression
scheme which will hardly ever insult users by accident.

- An animated splash screen with sound. This was one of the most wanted
features in the past, but coreboot was too fast for anyone to notice the
splash screen. Now we have a mandatory delay of 20 seconds, enough for
short movies and even some tacked on ads.

- Ultra-secure Suspend-to-RAM (S3) for people worried of RAM readout
(the "cold boot attacks" with frozen RAM). During every suspend cycle,
coreboot completely wipes the RAM and will resume to a data-free system.

- WORN technology. This is shorthand for Write Once, Read Never. Others
practice that coding tradition by accident, but we have perfected it as
an art.

- Double use technology. Most people think of weapons when they hear
this, but it's more simple and a lot more environmentally friendly. Your
CPU will not only calculate stuff, coreboot can also switch off the fans
on demand to make sure the CPU will fry your omelette exactly right.

- Less-than-zero boot times. Ever had the problem that your boot took
too long? We have the simple solution: Once coreboot is finished with
initializing the hardware, it will set back your clock by 30 seconds.
Even with the mandatory 20 second delay for splash movies, you can
finish booting 9-10 seconds before you switched the machine on.

- Real life impact. With a less-than-zero boot time, time goes
effectively backward. If you assemble a big enough cluster of coreboot
machines, you can undo the worst decisions of your life.

As you can see, coreboot v4.1 is the best thing since the invention of
sliced bread. It even makes firmware veterans spin in their graves to
act as human-powered electricity generators (a nice environmental plus).


To limit the impact on the real world (especially due to the time
machine properties), this coreboot version will only be available for
download this April 1st.


Sincerely,
the coreboot team

-- 
http://www.hailfinger.org/




From patrick at georgi-clan.de  Wed Apr  1 12:47:02 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 01 Apr 2009 12:47:02 +0200
Subject: [coreboot] patch: add code for romfs booting to v2
In-Reply-To: <20090331190924.GB22189@greenwood>
References: <13426df10903311152i5a3cd9a5k3aeb6b458c64d1b3@mail.gmail.com>
	<20090331190924.GB22189@greenwood>
Message-ID: <49D34626.7040903@georgi-clan.de>

Am 31.03.2009 21:09, schrieb Uwe Hermann:
>> Index: src/boot/selfboot.c
>> ===================================================================
>> --- src/boot/selfboot.c	(revision 0)
>> +++ src/boot/selfboot.c	(revision 0)
>> @@ -0,0 +1,497 @@
>> +#include<console/console.h>
>>      
>
> Missing copyright owner, year, and license.
>    
I asked Eric, and he states that elfboot is his. I'll prepare a patch 
for both files, but will commit this patch as-is.
Thanks Uwe for spotting this!

For the patch
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Patrick
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From svn at coreboot.org  Wed Apr  1 12:48:39 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Apr 2009 12:48:39 +0200
Subject: [coreboot] [v2] r4039 - in trunk/coreboot-v2/src: boot lib
Message-ID: <mailman.2916.1355071508.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-01 12:48:39 +0200 (Wed, 01 Apr 2009)
New Revision: 4039

Added:
   trunk/coreboot-v2/src/boot/selfboot.c
   trunk/coreboot-v2/src/lib/romfs.c
Modified:
   trunk/coreboot-v2/src/boot/Config.lb
   trunk/coreboot-v2/src/boot/hardwaremain.c
   trunk/coreboot-v2/src/lib/Config.lb
Log:
This code adds support for coreboot images that use ROMFS. 

It also removes the call to FILO from hardwaremain -- that 
has needed removal for a long time. 

abuild tested.
Note that this code has been tested and works on 
both qemu and kontron. The changes to use it are coming 
next.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



Modified: trunk/coreboot-v2/src/boot/Config.lb
===================================================================
--- trunk/coreboot-v2/src/boot/Config.lb	2009-03-31 17:17:30 UTC (rev 4038)
+++ trunk/coreboot-v2/src/boot/Config.lb	2009-04-01 10:48:39 UTC (rev 4039)
@@ -1,5 +1,8 @@
 object elfboot.o
 object hardwaremain.o
+if CONFIG_ROMFS
+	object selfboot.o
+end
 if CONFIG_FS_PAYLOAD
 	object filo.o
 end

Modified: trunk/coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- trunk/coreboot-v2/src/boot/hardwaremain.c	2009-03-31 17:17:30 UTC (rev 4038)
+++ trunk/coreboot-v2/src/boot/hardwaremain.c	2009-04-01 10:48:39 UTC (rev 4039)
@@ -88,10 +88,21 @@
 	 */
 	lb_mem = write_tables();
 
-#if CONFIG_FS_PAYLOAD == 1
-	filo(lb_mem);
+#if CONFIG_ROMFS == 1
+	printk_err("=================================================\n");
+#if USE_FALLBACK_IMAGE == 1
+	void (*pl)(void) = romfs_load_payload(lb_mem, "fallback/payload");
 #else
+	void (*pl)(void) = romfs_load_payload(lb_mem, "normal/payload");
+#endif
+#endif
+
+#warning elfboot will soon be deprecated
+
+	printk_err("Trying elfboot, but that will be gone soon!\n");
 	elfboot(lb_mem);
-#endif
+
+	printk_err("NO BOOT METHOD succeeded\n");
+
 }
 

Added: trunk/coreboot-v2/src/boot/selfboot.c
===================================================================
--- trunk/coreboot-v2/src/boot/selfboot.c	                        (rev 0)
+++ trunk/coreboot-v2/src/boot/selfboot.c	2009-04-01 10:48:39 UTC (rev 4039)
@@ -0,0 +1,497 @@
+#include <console/console.h>
+#include <part/fallback_boot.h>
+#include <boot/elf.h>
+#include <boot/elf_boot.h>
+#include <boot/coreboot_tables.h>
+#include <ip_checksum.h>
+#include <stream/read_bytes.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <romfs.h>
+
+#ifndef CONFIG_BIG_ENDIAN
+#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \
+		((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) )
+#else
+#define ntohl(x) (x)
+#endif
+
+/* Maximum physical address we can use for the coreboot bounce buffer.
+ */
+#ifndef MAX_ADDR
+#define MAX_ADDR -1UL
+#endif
+
+extern unsigned char _ram_seg;
+extern unsigned char _eram_seg;
+
+struct segment {
+	struct segment *next;
+	struct segment *prev;
+	struct segment *phdr_next;
+	struct segment *phdr_prev;
+	unsigned long s_dstaddr;
+	unsigned long s_srcaddr;
+	unsigned long s_memsz;
+	unsigned long s_filesz;
+};
+
+struct verify_callback {
+	struct verify_callback *next;
+	int (*callback)(struct verify_callback *vcb, 
+		Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head);
+	unsigned long desc_offset;
+	unsigned long desc_addr;
+};
+
+struct ip_checksum_vcb {
+	struct verify_callback data;
+	unsigned short ip_checksum;
+};
+
+int romfs_self_decompress(int algo, void *src,struct segment *new)
+{
+	u8 *dst;
+
+	/* for uncompressed, it's easy: just point at the area in ROM */
+	if (algo ==  ROMFS_COMPRESS_NONE) {
+		new->s_srcaddr = (u32) src;
+		new->s_filesz =  new->s_memsz;
+		return 0;
+	}
+
+	/* for compression, let's keep it simple. We'll malloc the destination 
+	 * area and decompress to there. The compression overhead far outweighs
+	 * any overhead for an extra copy. 
+	 */
+	dst = malloc(new->s_memsz);
+	if (! dst)
+		return -1;
+
+	switch(algo) {
+#ifdef CONFIG_COMPRESSION_LZMA
+	case ROMFS_COMPRESS_LZMA: {
+		unsigned long ulzma(unsigned char *src, unsigned char *dst);		
+		ulzma(src, dst);
+	}
+#endif
+
+#ifdef CONFIG_COMPRESSION_NRV2B
+	case ROMFS_COMPRESS_NRV2B: {
+		unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p);
+		unsigned long tmp;
+		unrv2b(src, dst, &tmp);
+	}
+#endif
+	default:
+		printk_info( "ROMFS:  Unknown compression type %d\n",
+		       algo);
+		return -1;
+	}
+
+	new->s_srcaddr = (u32) dst;
+	new->s_filesz =  new->s_memsz;
+	return 0;
+	
+}
+
+/* The problem:  
+ * Static executables all want to share the same addresses
+ * in memory because only a few addresses are reliably present on
+ * a machine, and implementing general relocation is hard.
+ *
+ * The solution:
+ * - Allocate a buffer twice the size of the coreboot image.
+ * - Anything that would overwrite coreboot copy into the lower half of
+ *   the buffer. 
+ * - After loading an ELF image copy coreboot to the upper half of the
+ *   buffer.
+ * - Then jump to the loaded image.
+ * 
+ * Benefits:
+ * - Nearly arbitrary standalone executables can be loaded.
+ * - Coreboot is preserved, so it can be returned to.
+ * - The implementation is still relatively simple,
+ *   and much simpler then the general case implemented in kexec.
+ * 
+ */
+
+static unsigned long get_bounce_buffer(struct lb_memory *mem)
+{
+	unsigned long lb_size;
+	unsigned long mem_entries;
+	unsigned long buffer;
+	int i;
+	lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
+	/* Double coreboot size so I have somewhere to place a copy to return to */
+	lb_size = lb_size + lb_size;
+	mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
+	buffer = 0;
+	for(i = 0; i < mem_entries; i++) {
+		unsigned long mstart, mend;
+		unsigned long msize;
+		unsigned long tbuffer;
+		if (mem->map[i].type != LB_MEM_RAM)
+			continue;
+		if (unpack_lb64(mem->map[i].start) > MAX_ADDR)
+			continue;
+		if (unpack_lb64(mem->map[i].size) < lb_size)
+			continue;
+		mstart = unpack_lb64(mem->map[i].start);
+		msize = MAX_ADDR - mstart +1;
+		if (msize > unpack_lb64(mem->map[i].size))
+			msize = unpack_lb64(mem->map[i].size);
+		mend = mstart + msize;
+		tbuffer = mend - lb_size;
+		if (tbuffer < buffer) 
+			continue;
+		buffer = tbuffer;
+	}
+	return buffer;
+}
+
+static int valid_area(struct lb_memory *mem, unsigned long buffer,
+	unsigned long start, unsigned long len)
+{
+	/* Check through all of the memory segments and ensure
+	 * the segment that was passed in is completely contained
+	 * in RAM.
+	 */
+	int i;
+	unsigned long end = start + len;
+	unsigned long mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
+
+	/* See if I conflict with the bounce buffer */
+	if (end >= buffer) {
+		return 0;
+	}
+
+	/* Walk through the table of valid memory ranges and see if I
+	 * have a match.
+	 */
+	for(i = 0; i < mem_entries; i++) {
+		uint64_t mstart, mend;
+		uint32_t mtype;
+		mtype = mem->map[i].type;
+		mstart = unpack_lb64(mem->map[i].start);
+		mend = mstart + unpack_lb64(mem->map[i].size);
+		if ((mtype == LB_MEM_RAM) && (start < mend) && (end > mstart)) {
+			break;
+		}
+		if ((mtype == LB_MEM_TABLE) && (start < mend) && (end > mstart)) {
+			printk_err("Payload is overwriting Coreboot tables.\n");
+			break;
+		}
+	}
+	if (i == mem_entries) {
+		printk_err("No matching ram area found for range:\n");
+		printk_err("  [0x%016lx, 0x%016lx)\n", start, end);
+		printk_err("Ram areas\n");
+		for(i = 0; i < mem_entries; i++) {
+			uint64_t mstart, mend;
+			uint32_t mtype;
+			mtype = mem->map[i].type;
+			mstart = unpack_lb64(mem->map[i].start);
+			mend = mstart + unpack_lb64(mem->map[i].size);
+			printk_err("  [0x%016lx, 0x%016lx) %s\n",
+				(unsigned long)mstart, 
+				(unsigned long)mend, 
+				(mtype == LB_MEM_RAM)?"RAM":"Reserved");
+			
+		}
+		return 0;
+	}
+	return 1;
+}
+
+static void relocate_segment(unsigned long buffer, struct segment *seg)
+{
+	/* Modify all segments that want to load onto coreboot
+	 * to load onto the bounce buffer instead.
+	 */
+	unsigned long lb_start = (unsigned long)&_ram_seg;
+	unsigned long lb_end = (unsigned long)&_eram_seg;
+	unsigned long start, middle, end;
+
+	printk_spew("lb: [0x%016lx, 0x%016lx)\n", 
+		lb_start, lb_end);
+
+	start = seg->s_dstaddr;
+	middle = start + seg->s_filesz;
+	end = start + seg->s_memsz;
+	/* I don't conflict with coreboot so get out of here */
+	if ((end <= lb_start) || (start >= lb_end))
+		return;
+
+	printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
+		start, middle, end);
+
+	/* Slice off a piece at the beginning
+	 * that doesn't conflict with coreboot.
+	 */
+	if (start < lb_start) {
+		struct segment *new;
+		unsigned long len = lb_start - start;
+		new = malloc(sizeof(*new));
+		*new = *seg;
+		new->s_memsz = len;
+		seg->s_memsz -= len;
+		seg->s_dstaddr += len;
+		seg->s_srcaddr += len;
+		if (seg->s_filesz > len) {
+			new->s_filesz = len;
+			seg->s_filesz -= len;
+		} else {
+			seg->s_filesz = 0;
+		}
+
+		/* Order by stream offset */
+		new->next = seg;
+		new->prev = seg->prev;
+		seg->prev->next = new;
+		seg->prev = new;
+		/* Order by original program header order */
+		new->phdr_next = seg;
+		new->phdr_prev = seg->phdr_prev;
+		seg->phdr_prev->phdr_next = new;
+		seg->phdr_prev = new;
+
+		/* compute the new value of start */
+		start = seg->s_dstaddr;
+		
+		printk_spew("   early: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
+			new->s_dstaddr, 
+			new->s_dstaddr + new->s_filesz,
+			new->s_dstaddr + new->s_memsz);
+	}
+	
+	/* Slice off a piece at the end 
+	 * that doesn't conflict with coreboot 
+	 */
+	if (end > lb_end) {
+		unsigned long len = lb_end - start;
+		struct segment *new;
+		new = malloc(sizeof(*new));
+		*new = *seg;
+		seg->s_memsz = len;
+		new->s_memsz -= len;
+		new->s_dstaddr += len;
+		new->s_srcaddr += len;
+		if (seg->s_filesz > len) {
+			seg->s_filesz = len;
+			new->s_filesz -= len;
+		} else {
+			new->s_filesz = 0;
+		}
+		/* Order by stream offset */
+		new->next = seg->next;
+		new->prev = seg;
+		seg->next->prev = new;
+		seg->next = new;
+		/* Order by original program header order */
+		new->phdr_next = seg->phdr_next;
+		new->phdr_prev = seg;
+		seg->phdr_next->phdr_prev = new;
+		seg->phdr_next = new;
+
+		/* compute the new value of end */
+		end = start + len;
+		
+		printk_spew("   late: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
+			new->s_dstaddr, 
+			new->s_dstaddr + new->s_filesz,
+			new->s_dstaddr + new->s_memsz);
+		
+	}
+	/* Now retarget this segment onto the bounce buffer */
+	/* sort of explanation: the buffer is a 1:1 mapping to coreboot. 
+	 * so you will make the dstaddr be this buffer, and it will get copied
+	 * later to where coreboot lives.
+	 */
+	seg->s_dstaddr = buffer + (seg->s_dstaddr - lb_start);
+
+	printk_spew(" bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
+		seg->s_dstaddr, 
+		seg->s_dstaddr + seg->s_filesz, 
+		seg->s_dstaddr + seg->s_memsz);
+}
+
+
+static int build_self_segment_list(
+	struct segment *head, 
+	unsigned long bounce_buffer, struct lb_memory *mem,
+	struct romfs_payload *payload, u32 *entry)
+{
+	struct segment *new;
+	struct segment *ptr;
+	u8 *data;
+	int datasize;
+	struct romfs_payload_segment *segment, *first_segment;
+	memset(head, 0, sizeof(*head));
+	head->phdr_next = head->phdr_prev = head;
+	head->next = head->prev = head;
+	first_segment = segment = &payload->segments;
+
+	while(1) {
+		printk_debug("Segment %p\n", segment);
+		switch(segment->type) {
+		default: printk_emerg("Bad segment type %x\n", segment->type);
+			return -1;
+		case PAYLOAD_SEGMENT_PARAMS:
+			printk_info("found param section\n");
+			segment++;
+			continue;
+		case PAYLOAD_SEGMENT_CODE:
+		case PAYLOAD_SEGMENT_DATA:
+			printk_info( "%s: ", segment->type == PAYLOAD_SEGMENT_CODE ? 
+				"code" : "data");
+		new = malloc(sizeof(*new));
+		new->s_dstaddr = ntohl((u32) segment->load_addr);
+		new->s_memsz = ntohl(segment->mem_len);
+
+		datasize = ntohl(segment->len);
+		/* figure out decompression, do it, get pointer to the area */
+		if (romfs_self_decompress(ntohl(segment->compression),
+					     ((unsigned char *) first_segment) +
+					     ntohl(segment->offset), new)) {
+			printk_emerg("romfs_self_decompress failed\n");
+			return;
+		}
+		printk_debug("New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n",
+			new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz);
+		/* Clean up the values */
+		if (new->s_filesz > new->s_memsz)  {
+			new->s_filesz = new->s_memsz;
+		}
+		printk_debug("(cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n",
+			new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz);
+		break;
+		case PAYLOAD_SEGMENT_BSS:
+			printk_info("BSS %p/%d\n", (void *) ntohl((u32) segment->load_addr),
+				 ntohl(segment->mem_len));
+			new = malloc(sizeof(*new));
+			new->s_filesz = 0;
+			new->s_dstaddr = ntohl((u32) segment->load_addr);
+			new->s_memsz = ntohl(segment->mem_len);
+
+			break;
+
+		case PAYLOAD_SEGMENT_ENTRY:
+			printk_info("Entry %p\n", (void *) ntohl((u32) segment->load_addr));
+			*entry =  (void *) ntohl((u32) segment->load_addr);
+			return 1;
+		}
+		segment++;
+		for(ptr = head->next; ptr != head; ptr = ptr->next) {
+			if (new->s_srcaddr < ntohl((u32) segment->load_addr))
+				break;
+		}
+		/* Order by stream offset */
+		new->next = ptr;
+		new->prev = ptr->prev;
+		ptr->prev->next = new;
+		ptr->prev = new;
+		/* Order by original program header order */
+		new->phdr_next = head;
+		new->phdr_prev = head->phdr_prev;
+		head->phdr_prev->phdr_next  = new;
+		head->phdr_prev = new;
+
+		/* Verify the memory addresses in the segment are valid */
+		if (!valid_area(mem, bounce_buffer, new->s_dstaddr, new->s_memsz)) 
+			goto out;
+
+		/* Modify the segment to load onto the bounce_buffer if necessary.
+		 */
+		relocate_segment(bounce_buffer, new);
+	}
+	return 1;
+ out:
+	return 0;
+}
+
+static int load_self_segments(
+	struct segment *head, struct romfs_payload *payload)
+{
+	unsigned long offset;
+	struct segment *ptr;
+	
+	offset = 0;
+	for(ptr = head->next; ptr != head; ptr = ptr->next) {
+		unsigned long skip_bytes, read_bytes;
+		unsigned char *dest, *middle, *end, *src;
+		byte_offset_t result;
+		printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
+			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
+		
+		/* Compute the boundaries of the segment */
+		dest = (unsigned char *)(ptr->s_dstaddr);
+		end = dest + ptr->s_memsz;
+		middle = dest + ptr->s_filesz;
+		src = ptr->s_srcaddr;
+		printk_spew("[ 0x%016lx, %016lx, 0x%016lx) <- %016lx\n",
+			(unsigned long)dest,
+			(unsigned long)middle,
+			(unsigned long)end,
+			(unsigned long)src);
+		
+		/* Copy data from the initial buffer */
+		if (ptr->s_filesz) {
+			size_t len;
+			len = ptr->s_filesz;
+			memcpy(dest, src, len);
+			dest += len;
+		}
+		
+		/* Zero the extra bytes between middle & end */
+		if (middle < end) {
+			printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n",
+				(unsigned long)middle, (unsigned long)(end - middle));
+			
+			/* Zero the extra bytes */
+			memset(middle, 0, end - middle);
+		}
+	}
+	return 1;
+ out:
+	return 0;
+}
+
+int selfboot(struct lb_memory *mem, struct romfs_payload *payload)
+{
+	void *entry;
+	struct segment head;
+	unsigned long bounce_buffer;
+
+	/* Find a bounce buffer so I can load to coreboot's current location */
+	bounce_buffer = get_bounce_buffer(mem);
+	if (!bounce_buffer) {
+		printk_err("Could not find a bounce buffer...\n");
+		goto out;
+	}
+
+	/* Preprocess the self segments */
+	if (!build_self_segment_list(&head, bounce_buffer, mem, payload, &entry))
+		goto out;
+
+	/* Load the segments */
+	if (!load_self_segments(&head, payload))
+		goto out;
+
+	printk_spew("Loaded segments\n");
+
+	/* Reset to booting from this image as late as possible */
+	boot_successful();
+
+	printk_debug("Jumping to boot code at %p\n", entry);
+	post_code(0xfe);
+
+	/* Jump to kernel */
+	jmp_to_elf_entry(entry, bounce_buffer);
+	return 1;
+
+ out:
+	return 0;
+}
+

Modified: trunk/coreboot-v2/src/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/lib/Config.lb	2009-03-31 17:17:30 UTC (rev 4038)
+++ trunk/coreboot-v2/src/lib/Config.lb	2009-04-01 10:48:39 UTC (rev 4039)
@@ -27,3 +27,7 @@
 	initobject memcpy.o
 	initobject memcmp.o
 end
+
+if CONFIG_ROMFS
+	object romfs.o
+end

Added: trunk/coreboot-v2/src/lib/romfs.c
===================================================================
--- trunk/coreboot-v2/src/lib/romfs.c	                        (rev 0)
+++ trunk/coreboot-v2/src/lib/romfs.c	2009-04-01 10:48:39 UTC (rev 4039)
@@ -0,0 +1,234 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008, Jordan Crouse <jordan at cosmicpenguin.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <boot/coreboot_tables.h>
+#include <romfs.h>
+
+#ifndef CONFIG_BIG_ENDIAN
+#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \
+		((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) )
+#else
+#define ntohl(x) (x)
+#endif
+
+int run_address(void *f);
+
+int romfs_decompress(int algo, void *src, void *dst, int len)
+{
+	switch(algo) {
+	case ROMFS_COMPRESS_NONE:
+		memcpy(dst, src, len);
+		return 0;
+
+#ifdef CONFIG_COMPRESSION_LZMA
+
+	case ROMFS_COMPRESS_LZMA: {
+		unsigned long ulzma(unsigned char *src, unsigned char *dst);
+		ulzma(src, dst);
+	}
+		return 0;
+#endif
+
+#ifdef CONFIG_COMPRESSION_NRV2B
+	case ROMFS_COMPRESS_NRV2B: {
+		unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p);
+		unsigned long tmp;
+
+		unrv2b(src, dst, &tmp);
+	}
+		return 0;
+#endif
+	default:
+		printk_info( "ROMFS:  Unknown compression type %d\n",
+		       algo);
+		return -1;
+	}
+}
+
+int romfs_check_magic(struct romfs_file *file)
+{
+	return !strcmp(file->magic, ROMFS_FILE_MAGIC) ? 1 : 0;
+}
+
+struct romfs_header *romfs_master_header(void)
+{
+	struct romfs_header *header;
+
+	unsigned long ptr = *((unsigned long *) ROMFS_HEADPTR_ADDR);
+	printk_debug("Check ROMFS header at %p\n", ptr);
+	header = (struct romfs_header *) ptr;
+
+	printk_debug("magic is %08x\n", ntohl(header->magic));
+	if (ntohl(header->magic) != ROMFS_HEADER_MAGIC) {
+		printk_err("NO ROMFS HEADER\n");
+		return NULL;
+	}
+
+	printk_debug("Found ROMFS header at %p\n", ptr);
+	return header;
+}
+
+struct romfs_file *romfs_find(const char *name)
+{
+	struct romfs_header *header = romfs_master_header();
+	unsigned long offset;
+
+	if (header == NULL)
+		return NULL;
+	offset = 0 - ntohl(header->romsize) + ntohl(header->offset);
+
+	while(1) {
+		struct romfs_file *file = (struct romfs_file *) offset;
+		if (romfs_check_magic(file)) printk_info("Check %s\n", ROMFS_NAME(file));
+		if (romfs_check_magic(file) &&
+		    !strcmp(ROMFS_NAME(file), name))
+			return file;
+
+		offset += ntohl(header->align);
+
+		if (offset < 0xFFFFFFFF - ntohl(header->romsize))
+			return NULL;
+	}
+}
+
+struct romfs_stage *romfs_find_file(const char *name, int type)
+{
+	struct romfs_file *file = romfs_find(name);
+
+	if (file == NULL) {
+		printk_info( "ROMFS:  Could not find file %s\n",
+		       name);
+		return NULL;
+	}
+
+	if (ntohl(file->type) != type) {
+		printk_info( "ROMFS:  File %s is of type %x instead of"
+		       "type %x\n", name, file->type, type);
+
+		return NULL;
+	}
+
+	return (void *) ROMFS_SUBHEADER(file);
+}
+
+int romfs_load_optionrom(const char *name, u32 dest)
+{
+	struct romfs_optionrom *orom = (struct romfs_optionrom *)
+		romfs_find_file(name, ROMFS_TYPE_OPTIONROM);
+
+	if (orom == NULL)
+		return -1;
+
+	if (romfs_decompress(ntohl(orom->compression),
+			     ((unsigned char *) orom) +
+			     sizeof(struct romfs_optionrom),
+			     (void *) dest,
+			     ntohl(orom->len)))
+		return -1;
+
+	return 0;
+}
+
+void * romfs_load_payload(struct lb_memory *lb_mem, const char *name)
+{
+	int selfboot(struct lb_memory *mem, struct romfs_payload *payload);
+	struct romfs_payload *payload = (struct romfs_payload *)
+		romfs_find_file(name, ROMFS_TYPE_PAYLOAD);
+
+	struct romfs_payload_segment *segment, *first_segment;
+
+	if (payload == NULL)
+		return (void *) -1;
+	printk_debug("Got a payload\n");
+	first_segment = segment = &payload->segments;
+	selfboot(lb_mem, payload);
+	printk_emerg("SELFBOOT RETURNED!\n");
+
+	return (void *) -1;
+}
+
+void * romfs_load_stage(const char *name)
+{
+	struct romfs_stage *stage = (struct romfs_stage *)
+		romfs_find_file(name, ROMFS_TYPE_STAGE);
+	/* this is a mess. There is no ntohll. */
+	/* for now, assume compatible byte order until we solve this. */
+	u32 entry;
+
+	if (stage == NULL)
+		return (void *) -1;
+
+	printk_info("Stage: load @ %d/%d bytes, enter @ %llx\n", 
+			ntohl((u32) stage->load), ntohl(stage->memlen), 
+			stage->entry);
+	memset((void *) ntohl((u32) stage->load), 0, ntohl(stage->memlen));
+
+	if (romfs_decompress(ntohl(stage->compression),
+			     ((unsigned char *) stage) +
+			     sizeof(struct romfs_stage),
+			     (void *) ntohl((u32) stage->load),
+			     ntohl(stage->len)))
+		return (void *) -1;
+
+	entry = stage->entry;
+//	return (void *) ntohl((u32) stage->entry);
+	return (void *) entry;
+}
+
+void * romfs_get_file(const char *name)
+{
+	return romfs_find(name);
+}
+
+int romfs_execute_stage(const char *name)
+{
+	struct romfs_stage *stage = (struct romfs_stage *)
+		romfs_find_file(name, ROMFS_TYPE_STAGE);
+
+	if (stage == NULL)
+		return 1;
+
+	if (ntohl(stage->compression) != ROMFS_COMPRESS_NONE) {
+		printk_info( "ROMFS:  Unable to run %s:  Compressed file"
+		       "Not supported for in-place execution\n", name);
+		return 1;
+	}
+
+	/* FIXME: This isn't right */
+	printk_info( "ROMFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
+	return run_address((void *) ntohl((u32) stage->entry));
+}
+
+/**
+ *  * run_address is passed the address of a function taking no parameters and
+ *   * jumps to it, returning the result. 
+ *    * @param f the address to call as a function. 
+ *     * returns value returned by the function. 
+ *      */
+
+int run_address(void *f)
+{
+        int (*v) (void);
+        v = f;
+        return v();
+}
+




From svn at coreboot.org  Wed Apr  1 13:03:32 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Apr 2009 13:03:32 +0200
Subject: [coreboot] [v2] r4040 - trunk/coreboot-v2/src/boot
Message-ID: <mailman.2917.1355071508.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-01 13:03:32 +0200 (Wed, 01 Apr 2009)
New Revision: 4040

Modified:
   trunk/coreboot-v2/src/boot/elfboot.c
   trunk/coreboot-v2/src/boot/selfboot.c
Log:
Add copyright notices to two files, src/boot/elfboot.c
and its derivative src/boot/selfboot.c.

The mail in which Eric asserts authorship on elfboot.c is
quoted below, selfboot.c was substantially edited by Ron.
With that information in mind the change is trivial.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



From: ebiederm at xmission.com (Eric W. Biederman)
Date: Wed, 01 Apr 2009 03:31:15 -0700
To: Patrick Georgi <patrick at georgi-clan.de>

Patrick Georgi <patrick at georgi-clan.de> writes:

> Hi,
>
> We found some file in the coreboot tree that we suspect is yours.
> Unfortunately,
> both copyright notice and license are missing.
> Could you please take a look at it, and state whether it's yours,
> and if so,
> what license is to be attached?

Yes. GPLv2

> The file in question is
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/boot/elfboot.c
> and its history goes back to
> http://tracker.coreboot.org/trac/coreboot/log/trunk/LinuxBIOSv2/src/boot/elfboot.c?rev=2890


Eric


Modified: trunk/coreboot-v2/src/boot/elfboot.c
===================================================================
--- trunk/coreboot-v2/src/boot/elfboot.c	2009-04-01 10:48:39 UTC (rev 4039)
+++ trunk/coreboot-v2/src/boot/elfboot.c	2009-04-01 11:03:32 UTC (rev 4040)
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric W. Biederman <ebiederm at xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <part/fallback_boot.h>
 #include <boot/elf.h>

Modified: trunk/coreboot-v2/src/boot/selfboot.c
===================================================================
--- trunk/coreboot-v2/src/boot/selfboot.c	2009-04-01 10:48:39 UTC (rev 4039)
+++ trunk/coreboot-v2/src/boot/selfboot.c	2009-04-01 11:03:32 UTC (rev 4040)
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric W. Biederman <ebiederm at xmission.com>
+ * Copyright (C) 2009 Ron Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <part/fallback_boot.h>
 #include <boot/elf.h>




From info at coresystems.de  Wed Apr  1 13:09:01 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Apr 2009 13:09:01 +0200
Subject: [coreboot] build service results for r4039
Message-ID: <E1LoyJZ-0005Xo-L4@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4039 to
the coreboot repository. This caused the following 
changes:

Change Log:
This code adds support for coreboot images that use ROMFS.

It also removes the call to FILO from hardwaremain -- that
has needed removal for a long time.

abuild tested.
Note that this code has been tested and works on
both qemu and kontron. The changes to use it are coming
next.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



Build Log:
Configuration of supermicro:h8dme has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4039&device=h8dme&vendor=supermicro&num=1


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Wed Apr  1 13:33:33 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Apr 2009 13:33:33 +0200
Subject: [coreboot] build service results for r4040
Message-ID: <E1LoyhJ-0001Oi-Kj@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4040 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add copyright notices to two files, src/boot/elfboot.c
and its derivative src/boot/selfboot.c.

The mail in which Eric asserts authorship on elfboot.c is
quoted below, selfboot.c was substantially edited by Ron.
With that information in mind the change is trivial.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



From: ebiederm at xmission.com (Eric W. Biederman)
Date: Wed, 01 Apr 2009 03:31:15 -0700
To: Patrick Georgi <patrick at georgi-clan.de>

Patrick Georgi <patrick at georgi-clan.de> writes:

> Hi,
>
> We found some file in the coreboot tree that we suspect is yours.
> Unfortunately,
> both copyright notice and license are missing.
> Could you please take a look at it, and state whether it's yours,
> and if so,
> what license is to be attached?

Yes. GPLv2

> The file in question is
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/boot/elfboot.c
> and its history goes back to
> http://tracker.coreboot.org/trac/coreboot/log/trunk/LinuxBIOSv2/src/boot/elfboot.c?rev=2890


Eric


Build Log:
Configuration of supermicro:h8dme is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4040&device=h8dme&vendor=supermicro&num=1


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Apr  1 13:37:40 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Apr 2009 13:37:40 +0200
Subject: [coreboot] [v2] r4041 -
	trunk/coreboot-v2/src/mainboard/supermicro/h8dme
Message-ID: <mailman.2918.1355071508.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-01 13:37:39 +0200 (Wed, 01 Apr 2009)
New Revision: 4041

Modified:
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
Log:
Forgot CONFIG_ROMFS for supermicro/h8dme.
Trivial fix, just add the defaults as with all other boards.


Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb	2009-04-01 11:03:32 UTC (rev 4040)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
@@ -20,6 +20,7 @@
 ## 
 
 uses HAVE_MP_TABLE
+uses CONFIG_ROMFS
 uses HAVE_PIRQ_TABLE
 uses HAVE_ACPI_TABLES
 uses ACPI_SSDTX_NUM
@@ -350,4 +351,9 @@
 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
+#
+# ROMFS
+#
+#
+default CONFIG_ROMFS=0
 end




From joe at settoplinux.org  Wed Apr  1 14:24:41 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 01 Apr 2009 08:24:41 -0400
Subject: [coreboot] coreboot v4.1
In-Reply-To: <49D345AB.6030808@gmx.net>
References: <49D345AB.6030808@gmx.net>
Message-ID: <582bc2be3be4837394409c66e4cb73b8@imap.1and1.com>




On Wed, 01 Apr 2009 12:44:59 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> [Distribution to news outlets is encouraged.]
> 
> I'm happy to announce that today coreboot v4.1 has been released.
> 
> Besides being totally redesigned, it is super-fast, handles almost every
> existing chipset, opens our codebase to contributors without lowlevel C
> skills and is generally something to be celebrated. Not to mention the
> environmental friendliness and promotion of world peace.
> 
> Features include, but are not limited to:
> 
> - LARROMFS-NG, allowing code and configuration storage in the ROM
> without risking accidental reflashes. With its clean and simple design,
> you can store hundreds of different file types easily in the ROM, each
> of them being handled by a different plugin.
> 
> - SQL-based chipset programming. Gone are the days where you had to
> differentiate between accessing PCI regs via struct device, u32 or
> device_t variants. Now you can use statements like:
> SELECT val_32bit FROM pci WHERE buslocation="badc:0f:fe.e" AND
> configbytenumber=00;
> or the even simpler
> SELECT val_32bit FROM pci NATURAL JOIN configbytes WHERE
> buslocation="badc:0f:fe.e" AND configbytename="Vendor ID";
> Changing PCI config space follows similar rules.
> 
> - A SQL interpreter in coreboot which handles all chipset code. This SQL
> interpreter combines the clarity of obfuscated FORTH with the speed of
> unoptimized SQL.
> 
> - Self-modifying code! As we all know, self-modifying code has less bugs
> because any given bug disappears after the code has been modified often
> enough. Plus, this is a good way to exercise CPUs to detect hardware
> problems more easily.
> 
> - Fancy linker scripts. LARROMFS-NG is the next generation archiving
> solution for all our needs because it does not rely on inherently
> bug-prone C code. LARROMFS-NG is implemented as a really big and
> all-encompassing set of linker scripts which can even link new linkers
> together which reinterpret these linker scripts.
> 
> - New plugin architecture. Coreboot v4.1 will faithfully execute any and
> all code presented on any device attached to the board. Due to that,
> trojanizing computers becomes a piece of cake, freeing up the precious
> time of the intelligence community for more pressing problems like world
> peace.
> 
> - Multi-language error messages. Although chinese error messages were a
> bit difficult to store in 7-bit ASCII, we created a lossy compression
> scheme which will hardly ever insult users by accident.
> 
> - An animated splash screen with sound. This was one of the most wanted
> features in the past, but coreboot was too fast for anyone to notice the
> splash screen. Now we have a mandatory delay of 20 seconds, enough for
> short movies and even some tacked on ads.
> 
> - Ultra-secure Suspend-to-RAM (S3) for people worried of RAM readout
> (the "cold boot attacks" with frozen RAM). During every suspend cycle,
> coreboot completely wipes the RAM and will resume to a data-free system.
> 
> - WORN technology. This is shorthand for Write Once, Read Never. Others
> practice that coding tradition by accident, but we have perfected it as
> an art.
> 
> - Double use technology. Most people think of weapons when they hear
> this, but it's more simple and a lot more environmentally friendly. Your
> CPU will not only calculate stuff, coreboot can also switch off the fans
> on demand to make sure the CPU will fry your omelette exactly right.
> 
> - Less-than-zero boot times. Ever had the problem that your boot took
> too long? We have the simple solution: Once coreboot is finished with
> initializing the hardware, it will set back your clock by 30 seconds.
> Even with the mandatory 20 second delay for splash movies, you can
> finish booting 9-10 seconds before you switched the machine on.
> 
> - Real life impact. With a less-than-zero boot time, time goes
> effectively backward. If you assemble a big enough cluster of coreboot
> machines, you can undo the worst decisions of your life.
> 
> As you can see, coreboot v4.1 is the best thing since the invention of
> sliced bread. It even makes firmware veterans spin in their graves to
> act as human-powered electricity generators (a nice environmental plus).
> 
> 
> To limit the impact on the real world (especially due to the time
> machine properties), this coreboot version will only be available for
> download this April 1st.
> 
> 
> Sincerely,
> the coreboot team
> 
Is this your April fools joke Carl-Daniel :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From stepan at coresystems.de  Wed Apr  1 15:13:50 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 01 Apr 2009 15:13:50 +0200
Subject: [coreboot] [PATCH] drop CONFIG_CHIP_NAME
Message-ID: <49D3688E.3020306@coresystems.de>

See patch

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

-------------- next part --------------
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From info at coresystems.de  Wed Apr  1 15:37:29 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Apr 2009 15:37:29 +0200
Subject: [coreboot] build service results for r4041
Message-ID: <E1Lp0dF-0004LX-7k@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4041 to
the coreboot repository. This caused the following 
changes:

Change Log:
Forgot CONFIG_ROMFS for supermicro/h8dme.
Trivial fix, just add the defaults as with all other boards.


Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Configuration of supermicro:h8dme has been fixed


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Wed Apr  1 15:37:33 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 01 Apr 2009 15:37:33 +0200
Subject: [coreboot] [PATCH] drop CONFIG_CHIP_NAME
In-Reply-To: <49D3688E.3020306@coresystems.de>
References: <49D3688E.3020306@coresystems.de>
Message-ID: <49D36E1D.5020308@gmx.net>

On 01.04.2009 15:13, Stefan Reinauer wrote:
> Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should
> be used unconditionally, and the names don't hurt.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>   

If it survives abuild, it is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Wed Apr  1 15:43:21 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Apr 2009 15:43:21 +0200
Subject: [coreboot] [v2] r4042 - in trunk/coreboot-v2/src: config
	cpu/amd/socket_754 cpu/amd/socket_939 cpu/amd/socket_940
	cpu/amd/socket_AM2 cpu/amd/socket_F cpu/amd/socket_F_1207
	cpu/amd/socket_S1G1 cpu/intel/socket_mPGA604_533Mhz
	drivers/generic/debug drivers/pci/onboard include/device
	mainboard/amd/dbm690t mainboard/amd/pistachio
	mainboard/amd/serengeti_cheetah
	mainboard/amd/serengeti_cheetah_fam10 mainboard/asus/a8n_e
	mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se
	mainboard/bcom/winnetp680 mainboard/broadcom/blast
	mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli
	mainboard/intel/xe7501devkit mainboard/iwill/dk8_htx
	mainboard/jetway/j7f24 mainboard/kontron/986lcd-m
	mainboard/msi/ms7135 mainboard/msi/ms7260
	mainboard/msi/ms9185 mainboard/msi/ms9282
	mainboard/newisys/khepri mainboard/nvidia/l1_2pvv
	mainboard/sunw/ultra40 mainboard/supermicro/h8dme
	mainboard/supermicro/h8dmr mainboard/technologic/ts5300
	mainboard/tyan/s2735 mainboard/tyan/s2850
	mainboard/tyan/s2875 mainboard/tyan/s2880
	mainboard/tyan/s2881 mainboard/tyan/s2882
	mainboard/tyan/s2885 mainboard/tyan/s2891
	mainboard/tyan/s2892 mainboard/tyan/s2895
	mainboard/tyan/s2912 mainboard/tyan/s2912_fam10
	mainboard/tyan/s4880 mainboard/tyan/s4882 mainboard/via/epia
	mainboard/via/epia-cn mainboard/via/pc2500e
	northbridge/amd/amdfam10 northbridge/amd/amdk8
Message-ID: <mailman.2919.1355071508.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-01 15:43:21 +0200 (Wed, 01 Apr 2009)
New Revision: 4042

Modified:
   trunk/coreboot-v2/src/config/Options.lb
   trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb
   trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb
   trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c
   trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c
   trunk/coreboot-v2/src/include/device/device.h
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
   trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
   trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb
   trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb
   trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c
   trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
   trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c
   trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c
   trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c
   trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c
   trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia/Options.lb
   trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb
   trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb
   trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
Log:
Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should
be used unconditionally, and the names don't hurt.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>




Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/config/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -854,12 +854,6 @@
 # Misc options
 ###############################################
 
-define CONFIG_CHIP_NAME
-	default 0
-	export always
-	comment "Compile in the chip name"
-end
-
 define CONFIG_GDB_STUB
 	default 0
 	export used

Modified: trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,7 +1,4 @@
-uses CONFIG_CHIP_NAME
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 object socket_754.o
 dir /cpu/amd/model_fxx

Modified: trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,5 @@
-uses CONFIG_CHIP_NAME
+config chip.h
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
-
 object socket_939.o
 
 dir /cpu/amd/model_fxx

Modified: trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,5 @@
-uses CONFIG_CHIP_NAME
+config chip.h
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
-
 object socket_940.o
 
 dir /cpu/amd/model_fxx

Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,12 +1,9 @@
-uses CONFIG_CHIP_NAME
 uses K8_REV_F_SUPPORT
 uses K8_HT_FREQ_1G_SUPPORT
 uses DIMM_SUPPORT
 uses CPU_SOCKET_TYPE
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 default K8_REV_F_SUPPORT=1
 #Opteron K8 1G HT Support

Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,12 +1,9 @@
-uses CONFIG_CHIP_NAME
 uses K8_REV_F_SUPPORT
 uses K8_HT_FREQ_1G_SUPPORT
 uses DIMM_SUPPORT
 uses CPU_SOCKET_TYPE
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 default K8_REV_F_SUPPORT=1
 #Opteron K8 1G HT Support

Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -17,7 +17,6 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-uses CONFIG_CHIP_NAME
 uses PCI_IO_CFG_EXT
 uses MMCONF_SUPPORT
 uses HT3_SUPPORT
@@ -30,9 +29,7 @@
 uses PCI_BUS_SEGN_BITS
 uses CAR_FAM10
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 default PCI_IO_CFG_EXT=1
 

Modified: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,12 +1,9 @@
-uses CONFIG_CHIP_NAME
 uses K8_REV_F_SUPPORT
 uses K8_HT_FREQ_1G_SUPPORT
 uses DIMM_SUPPORT
 uses CPU_SOCKET_TYPE
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 default K8_REV_F_SUPPORT=1
 #Opteron K8 1G HT Support

Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,6 +1,3 @@
-uses CONFIG_CHIP_NAME
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 object socket_mPGA604_533Mhz.o
 dir /cpu/intel/model_f2x

Modified: trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c
===================================================================
--- trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -231,13 +231,11 @@
 
 static void debug_init(device_t dev)
 {
-#if CONFIG_CHIP_NAME
 	device_t parent;
-#endif
+
 	if (!dev->enabled)
 		return;
 	switch(dev->path.pnp.device) {
-#if CONFIG_CHIP_NAME
 	case 0:
 		parent = dev->bus->dev;
 		printk_debug("DEBUG: %s", dev_path(parent));
@@ -247,7 +245,6 @@
 			printk_debug("\n");
 		}
 		break;
-#endif
 		
 	case 1:
 		print_pci_regs_all();

Modified: trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c
===================================================================
--- trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -73,8 +73,6 @@
 }
 
 struct chip_operations drivers_pci_onboard_ops = {
-#if CONFIG_CHIP_NAME == 1
 	CHIP_NAME("Onboard PCI")
-#endif
 	.enable_dev = onboard_enable,
 };

Modified: trunk/coreboot-v2/src/include/device/device.h
===================================================================
--- trunk/coreboot-v2/src/include/device/device.h	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/include/device/device.h	2009-04-01 13:43:21 UTC (rev 4042)
@@ -15,16 +15,10 @@
 /* Chip operations */
 struct chip_operations {
 	void (*enable_dev)(struct device *dev);
-#if CONFIG_CHIP_NAME == 1
 	char *name;
-#endif
 };
 
-#if CONFIG_CHIP_NAME == 1
 #define CHIP_NAME(X) .name = X,
-#else
-#define CHIP_NAME(X)
-#endif
 
 struct bus;
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -178,9 +178,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 #The variables belong to mainboard are defined here.
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -73,7 +73,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -157,9 +156,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=1
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -263,9 +263,6 @@
 #endif
 }
 
-/*
-* CONFIG_CHIP_NAME defined in Option.lb.
-*/
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("AMD DBM690T   Mainboard")
 	.enable_dev = dbm690t_enable,

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -178,9 +178,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 #The variables belong to mainboard are defined here.
 

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -73,7 +73,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -157,9 +156,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=1
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -335,9 +335,6 @@
 #endif
 }
 
-/*
-* CONFIG_CHIP_NAME defined in Option.lb.
-*/
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("AMD Pistachio Mainboard")
 	.enable_dev = pistachio_enable,

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -253,9 +253,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for amd/serengeti_cheetah 
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -57,7 +57,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -171,9 +170,6 @@
 default APIC_ID_OFFSET=0x8
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("AMD Serengeti Cheetah Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -263,9 +263,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 dir /southbridge/amd/amd8151
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -76,7 +76,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -197,9 +196,6 @@
 default APIC_ID_OFFSET=0x00
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -25,8 +25,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("AMD family 10 Cheetah mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -146,9 +146,7 @@
 		mainboardinit ./auto.inc
 	end
 end
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device apic_cluster 0 on			# APIC cluster

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -77,7 +77,6 @@
 uses CONFIG_CONSOLE_BTEXT
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -22,8 +22,6 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("ASUS A8N-E Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -112,9 +112,7 @@
   end
 end
 
-if CONFIG_CHIP_NAME
-  config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device apic_cluster 0 on			# APIC cluster

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -71,7 +71,6 @@
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 # bx_b001- uses K8_HW_MEM_HOLE_SIZEK
@@ -111,7 +110,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS = 1
 default CONFIG_LOGICAL_CPUS = 1
 default HAVE_ACPI_TABLES = 1
-# default CONFIG_CHIP_NAME = 1
 
 # 1G memory hole
 # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -23,8 +23,6 @@
 #include <device/pci_ids.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("ASUS A8V-E SE Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -115,9 +115,7 @@
   end
 end
 
-if CONFIG_CHIP_NAME
-  config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device apic_cluster 0 on			# APIC cluster

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -74,7 +74,6 @@
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 # bx_b001- uses K8_HW_MEM_HOLE_SIZEK
@@ -118,8 +117,6 @@
 default HAVE_HIGH_TABLES = 1
 default HAVE_LOW_TABLES = 0
 
-# default CONFIG_CHIP_NAME = 1
-
 # 1G memory hole
 # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -37,8 +37,6 @@
 	return 0;
 }
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("ASUS M2V-MX SE Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -64,7 +64,6 @@
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_MAX_PCI_BUSES
-uses CONFIG_CHIP_NAME
 uses CONFIG_VIDEO_MB
 uses CONFIG_IOAPIC
 
@@ -74,7 +73,6 @@
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default CONFIG_PCI_ROM_RUN = 0
 default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
 default HAVE_FALLBACK_BOOT = 1
 default HAVE_MP_TABLE = 0
 default CONFIG_UDELAY_TSC = 1

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -145,9 +145,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for broadcom/blast 
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -53,7 +53,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -128,9 +127,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Broadcom Blast Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -223,9 +223,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -81,7 +81,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
@@ -195,9 +194,6 @@
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -225,9 +225,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -79,7 +79,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
@@ -199,9 +198,6 @@
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("GIGABYTE GA-M57SLI Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -142,9 +142,7 @@
 ##
 dir /pc80
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # based on sample config for tyan/s2735
 chip northbridge/intel/e7501

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -40,7 +40,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses DEBUG
@@ -238,7 +237,6 @@
 
 default DEBUG=1
 # default CPU_OPT="-g"
-default CONFIG_CHIP_NAME=1
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Intel Xeon E7501 DevKit Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -261,9 +261,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 dir /southbridge/amd/amd8132
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -57,7 +57,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -171,9 +170,6 @@
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,6 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("IWILL DK8-HTX Mainboard")
 };
-#endif
-

Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -65,7 +65,6 @@
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_MAX_PCI_BUSES
 uses TTYS0_BAUD
-uses CONFIG_CHIP_NAME
 uses CONFIG_VIDEO_MB
 uses CONFIG_IOAPIC
 
@@ -75,7 +74,6 @@
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default CONFIG_PCI_ROM_RUN = 0
 default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
 default HAVE_FALLBACK_BOOT = 1
 default HAVE_MP_TABLE = 0
 default CONFIG_UDELAY_TSC = 1

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -58,7 +58,6 @@
 uses _ROMBASE
 uses STACK_SIZE
 uses HEAP_SIZE
-uses CONFIG_CHIP_NAME
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
@@ -324,11 +323,6 @@
 ## Select power on after power fail setting
 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-##
-## chip name
-##
-default  CONFIG_CHIP_NAME=1
-
 #
 # ROMFS
 # 

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -223,9 +223,7 @@
 ##
 ## Include the secondary configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device apic_cluster 0 on			# APIC cluster

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -77,7 +77,6 @@
 uses CONFIG_CONSOLE_BTEXT
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -21,8 +21,6 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("MSI MS7135 Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -164,9 +164,7 @@
   end
 end
 
-if CONFIG_CHIP_NAME
-  config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device apic_cluster 0 on			# APIC cluster

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -74,7 +74,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_USBDEBUG_DIRECT
@@ -120,7 +119,6 @@
 default ENABLE_APIC_EXT_ID = 0
 default APIC_ID_OFFSET = 0x10
 default LIFT_BSP_APIC_ID = 1
-default CONFIG_CHIP_NAME = 1
 
 # Move the default coreboot CMOS range off of AMD RTC registers.
 default LB_CKS_RANGE_START = 49

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -21,8 +21,6 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -172,9 +172,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-       config chip.h
-end
+config chip.h
 
 # sample config for amd/serengeti_cheetah
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -78,7 +78,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -180,9 +179,6 @@
 default APIC_ID_OFFSET=0x8
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
        CHIP_NAME("MSI MS-9185 Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -222,9 +222,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-        config chip.h
-end
+config chip.h
 
 
 # sample config for msi/ms9282

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -74,7 +74,6 @@
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 #bx_b001- uses K8_HW_MEM_HOLE_SIZEK
@@ -164,9 +163,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-#default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 #bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
        CHIP_NAME("MSI MS-9282 Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -51,7 +51,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -121,9 +120,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -252,9 +252,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on

Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -79,7 +79,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
@@ -193,9 +192,6 @@
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("NVIDIA l1_2pvv Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -188,9 +188,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2895
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -134,9 +133,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-#default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Sun Ultra 40 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -218,9 +218,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -79,7 +79,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -192,9 +191,6 @@
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -23,8 +23,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Supermicro H8DME Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -221,9 +221,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -79,7 +79,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -192,9 +191,6 @@
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Supermicro H8DMR Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -39,7 +39,6 @@
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
-uses CONFIG_CHIP_NAME
 
 
 uses CONFIG_CONSOLE_SERIAL8250
@@ -137,10 +136,6 @@
 default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
-default CONFIG_CHIP_NAME = 1
-
-
-
 #
 # ROMFS
 #

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -175,11 +175,8 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
-
 # sample config for tyan/s2735
 chip northbridge/intel/e7501
         device pci_domain 0 on

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -56,7 +56,6 @@
 uses CONFIG_CONSOLE_BTEXT
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2735 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -185,9 +185,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2850
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -122,9 +121,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=1
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2850 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -185,9 +185,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2875
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -123,9 +122,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2875 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -185,9 +185,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2880
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -122,9 +121,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=0
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2880 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -185,9 +185,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2881
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -127,9 +126,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 ##HT Unit ID offset, default is 1, the typical one
 default HT_CHAIN_UNITID_BASE=0x0a
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -158,9 +158,7 @@
 	dev->ops = &mainboard_operations;
 }
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2881 Mainboard")
 	.enable_dev = enable_dev,
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -185,9 +185,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2882
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -122,9 +121,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2882 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -185,9 +185,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2885
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -133,9 +132,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 ##HT Unit ID offset, default is 1, the typical one
 default HT_CHAIN_UNITID_BASE=0x0a
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2885 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -205,9 +205,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2891
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -59,7 +59,6 @@
 uses CONFIG_CONSOLE_BTEXT
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_VGA_ROM_RUN
 uses CONFIG_PCI_ROM_RUN

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -17,9 +17,7 @@
 }
 
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2891 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -206,9 +206,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2892
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -59,7 +59,6 @@
 uses CONFIG_CONSOLE_BTEXT
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_VGA_ROM_RUN
 uses CONFIG_PCI_ROM_RUN

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -17,9 +17,7 @@
 }
 
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2892 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -242,9 +242,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s2895
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -61,7 +61,6 @@
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_VGA_ROM_RUN
 uses CONFIG_PCI_ROM_RUN
@@ -169,9 +168,6 @@
 
 default SERIAL_CPU_INIT=0
 
-#CHIP_NAME ?
-#default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -17,9 +17,7 @@
 }
 
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2895 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -222,9 +222,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -79,7 +79,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
@@ -195,9 +194,6 @@
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2912 Mainboard")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -223,9 +223,7 @@
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 dir /southbridge/nvidia/mcp55
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -78,7 +78,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
@@ -197,9 +196,6 @@
 default APIC_ID_OFFSET=0x00
 default LIFT_BSP_APIC_ID=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -26,8 +26,6 @@
 #include <device/pci_ops.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2912 Mainboard (Family 10)")
 };
-#endif

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -186,9 +186,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s4880
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -126,9 +125,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=4
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S4880 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -186,9 +186,7 @@
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 # sample config for tyan/s4882
 chip northbridge/amd/amdk8/root_complex

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -52,7 +52,6 @@
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
@@ -126,9 +125,6 @@
 default CONFIG_MAX_PHYSICAL_CPUS=4
 default CONFIG_LOGICAL_CPUS=1
 
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
 #1G memory hole
 default HW_MEM_HOLE_SIZEK=0x100000
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,9 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-#if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S4882 Mainboard")
 };
-#endif
 

Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -5,7 +5,6 @@
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
-uses CONFIG_CHIP_NAME
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
@@ -64,7 +63,6 @@
 # This defaults to 8 data bits, 1 stop bit, and no parity
 default TTYS0_LCS=0x3
 
-default CONFIG_CHIP_NAME=1
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
 

Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -65,7 +65,6 @@
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_MAX_PCI_BUSES
 uses TTYS0_BAUD
-uses CONFIG_CHIP_NAME
 uses CONFIG_VIDEO_MB
 uses CONFIG_IOAPIC
 
@@ -75,7 +74,6 @@
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default CONFIG_PCI_ROM_RUN = 0
 default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
 default HAVE_FALLBACK_BOOT = 1
 default HAVE_MP_TABLE = 0
 default CONFIG_UDELAY_TSC = 1

Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -68,7 +68,6 @@
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
-uses CONFIG_CHIP_NAME
 uses CONFIG_VIDEO_MB
 uses CONFIG_IOAPIC
 
@@ -80,7 +79,6 @@
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default CONFIG_PCI_ROM_RUN = 0
 default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
 default HAVE_FALLBACK_BOOT = 1
 default CONFIG_SMP = 1
 default HAVE_MP_TABLE = 1

Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -17,15 +17,12 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-uses CONFIG_CHIP_NAME
 uses AGP_APERTURE_SIZE
 uses HAVE_ACPI_TABLES
 
 default AGP_APERTURE_SIZE=0x4000000
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 driver northbridge.o
 driver misc_control.o

Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -652,15 +652,11 @@
 	.device = 0x1200,
 };
 
-#if CONFIG_CHIP_NAME == 1
-
 struct chip_operations northbridge_amd_amdfam10_ops = {
 	CHIP_NAME("AMD FAM10 Northbridge")
 	.enable_dev = 0,
 };
 
-#endif
-
 static void pci_domain_read_resources(device_t dev)
 {
 	struct resource *resource;

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb	2009-04-01 13:43:21 UTC (rev 4042)
@@ -1,12 +1,9 @@
-uses CONFIG_CHIP_NAME
 uses AGP_APERTURE_SIZE
 uses HAVE_ACPI_TABLES
 
 default AGP_APERTURE_SIZE=0x4000000
 
-if CONFIG_CHIP_NAME
-	config chip.h
-end
+config chip.h
 
 driver northbridge.o
 driver misc_control.o

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-04-01 11:37:39 UTC (rev 4041)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-04-01 13:43:21 UTC (rev 4042)
@@ -629,15 +629,11 @@
 	.device = 0x1100,
 };
 
-#if CONFIG_CHIP_NAME == 1
-
 struct chip_operations northbridge_amd_amdk8_ops = {
 	CHIP_NAME("AMD K8 Northbridge")
 	.enable_dev = 0,
 };
 
-#endif
-
 static void pci_domain_read_resources(device_t dev)
 {
 	struct resource *resource;




From svn at coreboot.org  Wed Apr  1 15:54:16 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Apr 2009 15:54:16 +0200
Subject: [coreboot] [v2] r4043 - trunk/coreboot-v2/src/boot
Message-ID: <mailman.2920.1355071508.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-01 15:54:16 +0200 (Wed, 01 Apr 2009)
New Revision: 4043

Modified:
   trunk/coreboot-v2/src/boot/hardwaremain.c
Log:
(trivial) add filo call back for those few mainboards that still (need to) 
use the built-in filo.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- trunk/coreboot-v2/src/boot/hardwaremain.c	2009-04-01 13:43:21 UTC (rev 4042)
+++ trunk/coreboot-v2/src/boot/hardwaremain.c	2009-04-01 13:54:16 UTC (rev 4043)
@@ -89,20 +89,20 @@
 	lb_mem = write_tables();
 
 #if CONFIG_ROMFS == 1
-	printk_err("=================================================\n");
-#if USE_FALLBACK_IMAGE == 1
+# if USE_FALLBACK_IMAGE == 1
 	void (*pl)(void) = romfs_load_payload(lb_mem, "fallback/payload");
-#else
+# else
 	void (*pl)(void) = romfs_load_payload(lb_mem, "normal/payload");
+# endif
 #endif
-#endif
 
-#warning elfboot will soon be deprecated
-
-	printk_err("Trying elfboot, but that will be gone soon!\n");
+#if CONFIG_FS_PAYLOAD == 1
+#warning "CONFIG_FS_PAYLOAD is deprecated."
+	filo(lb_mem);
+#else
+#warning "elfboot will soon be deprecated."
 	elfboot(lb_mem);
-
-	printk_err("NO BOOT METHOD succeeded\n");
-
+#endif
+	printk_err("Boot failed.\n");
 }
 




From corey.osgood at gmail.com  Wed Apr  1 16:46:59 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 1 Apr 2009 10:46:59 -0400
Subject: [coreboot] flashrom fails to write/erase on VIA VT8237
In-Reply-To: <fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>
References: <49D05438.4040102@gmail.com> <49D09607.6010808@gmail.com>
	<20090330115759.6344.qmail@stuge.se> <49D19BAE.3060009@gmail.com>
	<20090331043750.4384.qmail@stuge.se> <49D1A3A7.7050703@gmail.com>
	<fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>
Message-ID: <dd3c80060904010746q2aa5fcc8s7d789c75aef1434a@mail.gmail.com>

Look through the vt823x code in chipset_enable.c and also the epia-cn code
in board_enable.c. Check the values of the registers modified by those
functions, and if your board's registers don't match those values, call the
appropriate function at the end of the board_enable for your board. Sorry I
can't be more specific, I only have a few minutes to check email.

-Corey

2009/4/1 vinuxes gmail <vinuxes at gmail.com>

> Hello Peter,
> Is there something that i can look into? or any pointers?
> Please help!
>
> Rgds,
> Vinod
>
>
> On Tue, Mar 31, 2009 at 10:31 AM, vinuxesgmail <vinuxes at gmail.com> wrote:
>
>> Peter,
>>   I am stuck with the same error even after applying the new patch. Here's
>> the command output:
>> {-------------------
>> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E          Calibrating
>> delay loop... OK.
>> No coreboot table found.
>> Found chipset "VIA VT8237", enabling flash write... OK.
>> Found board "Portwell PPAP-2020VL", enabling flash write... OK.
>> Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
>> Erasing flash chip... ERASE FAILED!
>> FAILED!
>> ERROR at 0x00000000: Expected=0xff, Read=0x49
>> -------------------
>> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin
>> Calibrating delay loop... OK.
>> No coreboot table found.
>> Found chipset "VIA VT8237", enabling flash write... OK.
>> Found board "Portwell PPAP-2020VL", enabling flash write... OK.
>> Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
>> Flash image seems to be a legacy BIOS. Disabling checks.
>> ERASE FAILED!
>> -------------------}
>>
>> Please guide me further.
>>
>> Regards,
>> Vinod
>>
>> Peter Stuge wrote:
>>
>>> Gah! Sorry. Here it is.
>>>
>>>
>>> //Peter
>>>
>>>
>>
>>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From corey.osgood at gmail.com  Wed Apr  1 16:49:17 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 1 Apr 2009 10:49:17 -0400
Subject: [coreboot] question about irc
In-Reply-To: <2831fecf0903310806x5a3a2b82m8b9b5b891d293eb6@mail.gmail.com>
References: <df1430310903310725x5cd03f44t5b415483b56284b4@mail.gmail.com>
	<2831fecf0903310806x5a3a2b82m8b9b5b891d293eb6@mail.gmail.com>
Message-ID: <dd3c80060904010749k21c68069lc1dc251ccddc83fd@mail.gmail.com>

On Tue, Mar 31, 2009 at 11:06 AM, Myles Watson <mylesgw at gmail.com> wrote:

> 2009/3/31 Jason Wang <wangqingpei at gmail.com>:
> > Hi all,
> >     Is there anyone who know how to use IRC to join in coreboot chat? I
> > really do not know how to apply an account for it.
>
> No account necessary.  Find an IRC client and connect.  For example,
> with chatzilla:
> /attach irc.freenode.net/coreboot
>
>
Once you are connected, you'll probably want to register your nick:
http://freenode.net/faq.shtml#nicksetup

-Corey
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From svn at coreboot.org  Wed Apr  1 18:06:34 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Apr 2009 18:06:34 +0200
Subject: [coreboot] [v2] r4044 - trunk/coreboot-v2/src/include
Message-ID: <mailman.2921.1355071508.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-04-01 18:06:33 +0200 (Wed, 01 Apr 2009)
New Revision: 4044

Added:
   trunk/coreboot-v2/src/include/romfs.h
Log:
forgot this. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Added: trunk/coreboot-v2/src/include/romfs.h
===================================================================
--- trunk/coreboot-v2/src/include/romfs.h	                        (rev 0)
+++ trunk/coreboot-v2/src/include/romfs.h	2009-04-01 16:06:33 UTC (rev 4044)
@@ -0,0 +1,170 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan at cosmicpenguin.net>
+ *
+ * This file is dual-licensed. You can choose between:
+ *   - The GNU GPL, version 2, as published by the Free Software Foundation
+ *   - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _ROMFS_H_
+#define _ROMFS_H_
+
+/** These are standard values for the known compression
+    alogrithms that coreboot knows about for stages and
+    payloads.  Of course, other LAR users can use whatever
+    values they want, as long as they understand them. */
+
+#define ROMFS_COMPRESS_NONE  0
+#define ROMFS_COMPRESS_LZMA  1
+#define ROMFS_COMPRESS_NRV2B 2
+
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define ROMFS_TYPE_STAGE     0x10
+#define ROMFS_TYPE_PAYLOAD   0x20
+#define ROMFS_TYPE_OPTIONROM 0x30
+
+/** this is the master romfs header - it need to be
+    located somewhere in the bootblock.  Where it
+    actually lives is up to coreboot. A pointer to
+    this header will live at 0xFFFFFFFc, so we can
+    easily find it. */
+
+#define ROMFS_HEADER_MAGIC  0x4F524243
+#define ROMFS_HEADPTR_ADDR 0xFFFFFFFc
+#define VERSION1 0x31313131
+
+struct romfs_header {
+	u32 magic;
+        u32 version; 
+        u32 romsize;
+        u32 bootblocksize;
+	u32 align;
+	u32 offset;
+	u32 pad[2];
+} __attribute__((packed));
+
+/** This is a component header - every entry in the ROMFS
+    will have this header.
+
+    This is how the component is arranged in the ROM:
+
+    --------------   <- 0
+    component header
+    --------------   <- sizeof(struct component)
+    component name
+    --------------   <- offset
+    data
+    ...
+    --------------   <- offset + len
+*/
+
+#define ROMFS_FILE_MAGIC "LARCHIVE"
+
+struct romfs_file {
+	char magic[8];
+	u32 len;
+	u32 type;
+	u32 checksum;
+	u32 offset;
+} __attribute__((packed));
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+   component types */
+
+/** This is the sub-header for stage components.  Stages are
+    loaded by coreboot during the normal boot process */
+
+struct romfs_stage {
+	u32 compression;  /** Compression type */
+	u64 entry;  /** entry point */
+	u64 load;   /** Where to load in memory */
+	u32 len;          /** length of data to load */
+	u32 memlen;	   /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components.  Payloads
+    are loaded by coreboot at the end of the boot process */
+
+struct romfs_payload_segment {
+	u32 type;
+	u32 compression;
+	u32 offset;
+	u64 load_addr;
+	u32 len;
+	u32 mem_len;
+} __attribute__((packed));
+
+struct romfs_payload {
+	struct romfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_DATA   0x41544144
+#define PAYLOAD_SEGMENT_BSS    0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+
+struct romfs_optionrom {
+	u32 compression;
+	u32 len;
+} __attribute__((packed));
+
+#define ROMFS_NAME(_c) (((char *) (_c)) + sizeof(struct romfs_file))
+#define ROMFS_SUBHEADER(_p) ( (void *) ((((u8 *) (_p)) + ntohl((_p)->offset))) )
+
+void * romfs_load_payload(struct lb_memory *lb_mem, const char *name);
+void * romfs_load_stage(const char *name);
+int romfs_execute_stage(const char *name);
+void * romfs_get_file(const char *name);
+int romfs_load_optionrom(const char *name, u32 dest);
+
+int run_address(void *f);
+
+#endif
+




From rminnich at gmail.com  Wed Apr  1 18:09:13 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Apr 2009 09:09:13 -0700
Subject: [coreboot] coreboot v4.1
In-Reply-To: <49D345AB.6030808@gmx.net>
References: <49D345AB.6030808@gmx.net>
Message-ID: <13426df10904010909i100773a9wcab31765b3132246@mail.gmail.com>

I hate this! You didn't include a browser?

ron



From svn at coreboot.org  Wed Apr  1 18:22:38 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Apr 2009 18:22:38 +0200
Subject: [coreboot] [v2] r4045 - trunk/coreboot-v2/src/cpu/amd/model_10xxx
Message-ID: <mailman.2922.1355071508.16123.coreboot@coreboot.org>

Author: mjones
Date: 2009-04-01 18:22:38 +0200 (Wed, 01 Apr 2009)
New Revision: 4045

Added:
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000095.h
Log:
Updated microcode for for AMD Fam10 DR-B2 and B3.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000095.h
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000095.h	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000095.h	2009-04-01 16:22:38 UTC (rev 4045)
@@ -0,0 +1,163 @@
+/*
+ ============================================================
+ (c) Advanced Micro Devices, Inc., 2004-2009
+
+ The  enclosed microcode  is intended  to be  used  with AMD
+ Microprocessors.  You  may   copy,  view  and  install  the
+ enclosed microcode  only for development  and deployment of
+ firmware,  BIOS,  or  operating  system code  for  computer
+ systems   that  contain  AMD   processors.   You   are  not
+ authorized  to use  the  enclosed microcode  for any  other
+ purpose.
+
+ THE  MICROCODE IS PROVIDED  "AS IS"  WITHOUT ANY  EXPRESS OR
+ IMPLIED WARRANTY  OF ANY KIND, INCLUDING BUT  NOT LIMITED TO
+ WARRANTIES    OF    MERCHANTABILITY,   NON-    INFRINGEMENT,
+ TITLE,FITNESS  FOR  ANY  PARTICULAR PURPOSE,  OR  WARRANTIES
+ ARISING FROM CONDUCT, COURSE  OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume  any responsibility for any errors which
+ may  appear   in  this   microcode  or  any   other  related
+ information provided  to you by  AMD, or result from  use of
+ this microcode.   AMD is not obligated  to furnish, support,
+ or  make   any  further  information,   software,  technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The  microcode is provided  with "RESTRICTED  RIGHTS."  Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to  the  restrictions as  set  forth  in  FAR 52.227-14  and
+ DFAR252.227-7013,  et seq.,  or its  successor.  Use  of the
+ microcode    by    the    U.S.     Government    constitutes
+ acknowledgement  of   AMD's  proprietary  rights   in  them.
+ ============================================================
+*/
+
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+    
+
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From marcj303 at gmail.com  Wed Apr  1 18:24:14 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 1 Apr 2009 10:24:14 -0600
Subject: [coreboot] Micro code for 1022h 01000095h
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1702871384@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1702871384@sbjgexmb1.amd.com>
Message-ID: <534e5dc20904010924k1ca90cd0m5fa50927e9204b26@mail.gmail.com>

2009/3/31 Bao, Zheng <Zheng.Bao at amd.com>:
> This patch applies for DR-B2 and B3.
>
>
> The patch file is for RFC requirement. Just copy the header file to
> src/cpu/amd/model_10xxx/
>
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>

Acked-by: Marc Jones <marcj303 at gmail.com>

r4045

-- 
http://marcjonesconsulting.com



From peter at stuge.se  Wed Apr  1 19:06:17 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Apr 2009 19:06:17 +0200
Subject: [coreboot] flashrom fails to write/erase on VIA VT8237
In-Reply-To: <fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>
References: <49D05438.4040102@gmail.com> <49D09607.6010808@gmail.com>
	<20090330115759.6344.qmail@stuge.se> <49D19BAE.3060009@gmail.com>
	<20090331043750.4384.qmail@stuge.se> <49D1A3A7.7050703@gmail.com>
	<fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>
Message-ID: <20090401170617.5933.qmail@stuge.se>

Hi Vinod,

vinuxes gmail wrote:
> Is there something that i can look into? or any pointers?

> > Found chipset "VIA VT8237", enabling flash write... OK.
> > Found board "Portwell PPAP-2020VL", enabling flash write... OK.
> > Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
> > Erasing flash chip... ERASE FAILED!

Ok. I guess my board enable code doesn't work properly. Maybe you can
help me look into the relevant registers manually?

Please download http://stuge.se/io.c and compile it using:
gcc -O2 -o io io.c

Please run:
setpci -d 1106:3227 e6.b 88.l

The command should print one hexadecimal byte and one hex long.
Please save these values.

Use bits 8-15 as port bits 8-15 and use 4f as bits 0-7, then please
run io:
./io r__4f

(Replace __ here with bits 8-15 from the hex long value from setpci.)

After this, please run flashrom with the patch. (It will still fail.)

Then please run the setpci and io command again, and finally send an
email with the output from all commands.


Thanks for your help!

//Peter



From peter at stuge.se  Wed Apr  1 19:12:47 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Apr 2009 19:12:47 +0200
Subject: [coreboot] question about irc
In-Reply-To: <df1430310903310725x5cd03f44t5b415483b56284b4@mail.gmail.com>
References: <df1430310903310725x5cd03f44t5b415483b56284b4@mail.gmail.com>
Message-ID: <20090401171247.7921.qmail@stuge.se>

Hi Jason,

Jason Wang wrote:
> Is there anyone who know how to use IRC to join in coreboot chat?

Sure thing! IRC is a chat network with special chat servers that
everyone can connect to. You can run an IRC client program on your
own computer (many exist for different operating systems) or you can
use one of several web based IRC clients:

http://www.mibbit.com/chat/
(Select IRC: Freenode, choose your own Nick and Channel is #coreboot)

http://www.web-irc.org/
Nickname (choose your own)
Server irc.freenode.net
Port 6667
Channel #coreboot
No password is needed.


> I really do not know how to apply an account for it.

You do not need an account to connect to IRC, but different IRC
networks have different policies when it comes to nicknames. For
Freenode it is recommended that you pick a unique nickname that noone
else on Freenode is using, and that you register the nickname with
the Freenode services. You do this after you have connected with your
nickname. There is more information at
http://freenode.net/faq.shtml#userregistration

Please ask again if you run into any trouble! I look forward to
talking to you in the channel. :)


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Wed Apr  1 19:43:10 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 01 Apr 2009 19:43:10 +0200
Subject: [coreboot] coreboot v4.1
In-Reply-To: <49D345AB.6030808@gmx.net>
References: <49D345AB.6030808@gmx.net>
Message-ID: <49D3A7AE.6010106@gmx.net>

I forgot the source tarball.

By the way, this is mentioned in the wiki as well to make sure even the
casual visitor sees it.

Can someone please submit to slashdot, lwn and phoronix? Thanks.

Regards,
Carl-Daniel

On 01.04.2009 12:44, Carl-Daniel Hailfinger wrote:
> [Distribution to news outlets is encouraged.]
>
> I'm happy to announce that today coreboot v4.1 has been released.
>
> Besides being totally redesigned, it is super-fast, handles almost every
> existing chipset, opens our codebase to contributors without lowlevel C
> skills and is generally something to be celebrated. Not to mention the
> environmental friendliness and promotion of world peace.
>
> Features include, but are not limited to:
>
> - LARROMFS-NG, allowing code and configuration storage in the ROM
> without risking accidental reflashes. With its clean and simple design,
> you can store hundreds of different file types easily in the ROM, each
> of them being handled by a different plugin.
>
> - SQL-based chipset programming. Gone are the days where you had to
> differentiate between accessing PCI regs via struct device, u32 or
> device_t variants. Now you can use statements like:
> SELECT val_32bit FROM pci WHERE buslocation="badc:0f:fe.e" AND
> configbytenumber=00;
> or the even simpler
> SELECT val_32bit FROM pci NATURAL JOIN configbytes WHERE
> buslocation="badc:0f:fe.e" AND configbytename="Vendor ID";
> Changing PCI config space follows similar rules.
>
> - A SQL interpreter in coreboot which handles all chipset code. This SQL
> interpreter combines the clarity of obfuscated FORTH with the speed of
> unoptimized SQL.
>
> - Self-modifying code! As we all know, self-modifying code has less bugs
> because any given bug disappears after the code has been modified often
> enough. Plus, this is a good way to exercise CPUs to detect hardware
> problems more easily.
>
> - Fancy linker scripts. LARROMFS-NG is the next generation archiving
> solution for all our needs because it does not rely on inherently
> bug-prone C code. LARROMFS-NG is implemented as a really big and
> all-encompassing set of linker scripts which can even link new linkers
> together which reinterpret these linker scripts.
>
> - New plugin architecture. Coreboot v4.1 will faithfully execute any and
> all code presented on any device attached to the board. Due to that,
> trojanizing computers becomes a piece of cake, freeing up the precious
> time of the intelligence community for more pressing problems like world
> peace.
>
> - Multi-language error messages. Although chinese error messages were a
> bit difficult to store in 7-bit ASCII, we created a lossy compression
> scheme which will hardly ever insult users by accident.
>
> - An animated splash screen with sound. This was one of the most wanted
> features in the past, but coreboot was too fast for anyone to notice the
> splash screen. Now we have a mandatory delay of 20 seconds, enough for
> short movies and even some tacked on ads.
>
> - Ultra-secure Suspend-to-RAM (S3) for people worried of RAM readout
> (the "cold boot attacks" with frozen RAM). During every suspend cycle,
> coreboot completely wipes the RAM and will resume to a data-free system.
>
> - WORN technology. This is shorthand for Write Once, Read Never. Others
> practice that coding tradition by accident, but we have perfected it as
> an art.
>
> - Double use technology. Most people think of weapons when they hear
> this, but it's more simple and a lot more environmentally friendly. Your
> CPU will not only calculate stuff, coreboot can also switch off the fans
> on demand to make sure the CPU will fry your omelette exactly right.
>
> - Less-than-zero boot times. Ever had the problem that your boot took
> too long? We have the simple solution: Once coreboot is finished with
> initializing the hardware, it will set back your clock by 30 seconds.
> Even with the mandatory 20 second delay for splash movies, you can
> finish booting 9-10 seconds before you switched the machine on.
>
> - Real life impact. With a less-than-zero boot time, time goes
> effectively backward. If you assemble a big enough cluster of coreboot
> machines, you can undo the worst decisions of your life.
>
> As you can see, coreboot v4.1 is the best thing since the invention of
> sliced bread. It even makes firmware veterans spin in their graves to
> act as human-powered electricity generators (a nice environmental plus).
>
>
> To limit the impact on the real world (especially due to the time
> machine properties), this coreboot version will only be available for
> download this April 1st.
>
>
> Sincerely,
> the coreboot team
>
>   


-- 
http://www.hailfinger.org/

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From joe at settoplinux.org  Wed Apr  1 21:45:39 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 01 Apr 2009 15:45:39 -0400
Subject: [coreboot] coreboot v4.1
In-Reply-To: <49D3A7AE.6010106@gmx.net>
References: <49D345AB.6030808@gmx.net> <49D3A7AE.6010106@gmx.net>
Message-ID: <0e2686929cfccf36d7ddfc5e03782e73@imap.1and1.com>




On Wed, 01 Apr 2009 19:43:10 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> I forgot the source tarball.
> 
Wow, the source dircetory is only 4.62k. With source that small we could
definitely fit a browser!!!

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Thu Apr  2 00:07:54 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Apr 2009 00:07:54 +0200
Subject: [coreboot] [v2] r4046 - trunk/coreboot-v2/src/cpu/x86/mtrr
Message-ID: <mailman.2923.1355071508.16123.coreboot@coreboot.org>

Author: mjones
Date: 2009-04-02 00:07:53 +0200 (Thu, 02 Apr 2009)
New Revision: 4046

Modified:
   trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c
Log:
Fix typo.
trivial.

Signed-off-by: Marc Jones <marcj303 at gmail.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c	2009-04-01 16:22:38 UTC (rev 4045)
+++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c	2009-04-01 22:07:53 UTC (rev 4046)
@@ -134,7 +134,7 @@
 	return r;
 }
 
-/* fms: find least sigificant bit set */
+/* fls: find least sigificant bit set */
 static inline unsigned int fls(unsigned int x)
 {
 	int r;




From marcj303 at gmail.com  Thu Apr  2 00:20:03 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 1 Apr 2009 16:20:03 -0600
Subject: [coreboot] [v2][patch] use updated microcode patches from AMD
Message-ID: <534e5dc20904011520g278c104cld8e55a57d7cd873b@mail.gmail.com>

I no longer have a Fam10 test setup but it should just work. If
someone can test it I would appreciate it.

Update equivalent processor revision ID to load latest microcode patches.
Signed-off-by: Marc Jones <marcj303 at gmail.com>

Thanks,
Marc

-- 
http://marcjonesconsulting.com
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From harald.gutmann at gmx.net  Thu Apr  2 00:22:32 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Apr 2009 00:22:32 +0200
Subject: [coreboot] Fix some PCI issues on M57SLI v2
In-Reply-To: <20090331155740.GA29619@localdomain>
References: <200903241854.53171.harald.gutmann@gmx.net>
	<200903311744.56445.harald.gutmann@gmx.net>
	<20090331155740.GA29619@localdomain>
Message-ID: <200904020022.36806.harald.gutmann@gmx.net>

Hello once again,
today Ward was able to test this patch on his mainboard, and it seems that 
nearly everything worked like supposed.

I missed, that this mainboard has a second PCI-E 16x port which wasn't 
initialized correctly in my previous patch.

This patch appended should clean up initialization of the second PCI-E 16x 
port too. I also just forgot in the last patch to do a correct init of the IDE 
controller.

What has not been verified until now are the PCI-1x ports, but neither Ward nor 
i own PCI-1x hardware. So it would be good if someone else, which has this 
mainboard and a PCI-1x card could help us to get the last PCI-(E) things 
working.

It would be grate if someone could verify my changes.

Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>

Kind regards,
Harald



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From ronald at zonnet.nl  Thu Apr  2 01:16:00 2009
From: ronald at zonnet.nl (Ronald Hoogenboom)
Date: Thu, 02 Apr 2009 01:16:00 +0200
Subject: [coreboot] build optimization
In-Reply-To: <mailman.481.1238624568.24014.coreboot@coreboot.org>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
Message-ID: <1238627760.2840.11.camel@amd-x2.grundel>

Hi,

I've attached a patch that removes the 3-mile-long compiler
commandlines, which vim's quickfix doesn't like so much. Instead of
putting all those -DXYZ='bla' on the compiler commandline, they are put
in a file called settings.h (as #define XYZ bla) and only a
--include=settings.h is put on the commandline.
This file is created unconditionally at the same time as when the
CPUFLAGS simply expanded make variable used to be created (not via a
target rule and dependency), so it shouldn't change anything.

Signed-off-by: Ronald Hoogenboom<hoogenboom30 at zonnet.nl>


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From corey.osgood at gmail.com  Thu Apr  2 01:42:26 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Wed, 1 Apr 2009 19:42:26 -0400
Subject: [coreboot] build optimization
In-Reply-To: <1238627760.2840.11.camel@amd-x2.grundel>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
Message-ID: <dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>

I think you're missing part of the patch, there should be a settings.h
included, right?

-Corey

2009/4/1 Ronald Hoogenboom <ronald at zonnet.nl>

> Hi,
>
> I've attached a patch that removes the 3-mile-long compiler
> commandlines, which vim's quickfix doesn't like so much. Instead of
> putting all those -DXYZ='bla' on the compiler commandline, they are put
> in a file called settings.h (as #define XYZ bla) and only a
> --include=settings.h is put on the commandline.
> This file is created unconditionally at the same time as when the
> CPUFLAGS simply expanded make variable used to be created (not via a
> target rule and dependency), so it shouldn't change anything.
>
> Signed-off-by: Ronald Hoogenboom<hoogenboom30 at zonnet.nl>
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From rminnich at gmail.com  Thu Apr  2 01:45:44 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Apr 2009 16:45:44 -0700
Subject: [coreboot] build optimization
In-Reply-To: <dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
	<dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
Message-ID: <13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>

On Wed, Apr 1, 2009 at 4:42 PM, Corey Osgood <corey.osgood at gmail.com> wrote:
> I think you're missing part of the patch, there should be a settings.h
> included, right?

no,that is generated by the >> in the patch.

I kind of like this. But, if the python is run twice, do you get the
file twice as large? There's no "zero out the file" step from what i
can see.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Thu Apr  2 02:05:24 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Apr 2009 02:05:24 +0200
Subject: [coreboot] build optimization
In-Reply-To: <1238627760.2840.11.camel@amd-x2.grundel>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
Message-ID: <49D40144.8060200@gmx.net>

Hi Ronald,

On 02.04.2009 01:16, Ronald Hoogenboom wrote:
> I've attached a patch that removes the 3-mile-long compiler
> commandlines, which vim's quickfix doesn't like so much. Instead of
> putting all those -DXYZ='bla' on the compiler commandline, they are put
> in a file called settings.h (as #define XYZ bla) and only a
> --include=settings.h is put on the commandline.
> This file is created unconditionally at the same time as when the
> CPUFLAGS simply expanded make variable used to be created (not via a
> target rule and dependency), so it shouldn't change anything.
>
> Signed-off-by: Ronald Hoogenboom<hoogenboom30 at zonnet.nl>
>   

This is definitely a great idea! Unfortunately, I don't understand the
v2 build system well enough to ack this patch.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From ward at gnu.org  Thu Apr  2 02:07:06 2009
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 1 Apr 2009 20:07:06 -0400
Subject: [coreboot] build optimization
In-Reply-To: <13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
	<dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
	<13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>
Message-ID: <20090402000706.GA16223@localdomain>

On Wed, Apr 01, 2009 at 04:45:44PM -0700, ron minnich wrote:
> On Wed, Apr 1, 2009 at 4:42 PM, Corey Osgood <corey.osgood at gmail.com> wrote:
> > I think you're missing part of the patch, there should be a settings.h
> > included, right?
> 
> no,that is generated by the >> in the patch.
> 
> I kind of like this. But, if the python is run twice, do you get the
> file twice as large? There's no "zero out the file" step from what i
> can see.

Hmm. Seems like replacing the >> by > should fix that.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From rminnich at gmail.com  Thu Apr  2 02:32:59 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Apr 2009 17:32:59 -0700
Subject: [coreboot] build optimization
In-Reply-To: <20090402000706.GA16223@localdomain>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
	<dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
	<13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>
	<20090402000706.GA16223@localdomain>
Message-ID: <13426df10904011732j67d94108l33517c2432a8b3d7@mail.gmail.com>

On Wed, Apr 1, 2009 at 5:07 PM, Ward Vandewege <ward at gnu.org> wrote:
> On Wed, Apr 01, 2009 at 04:45:44PM -0700, ron minnich wrote:
>> On Wed, Apr 1, 2009 at 4:42 PM, Corey Osgood <corey.osgood at gmail.com> wrote:
>> > I think you're missing part of the patch, there should be a settings.h
>> > included, right?
>>
>> no,that is generated by the >> in the patch.
>>
>> I kind of like this. But, if the python is run twice, do you get the
>> file twice as large? There's no "zero out the file" step from what i
>> can see.
>
> Hmm. Seems like replacing the >> by > should fix that.

Seems that way to me, but it's worth testing :-)

ron



From vogel at ct.metrocast.net  Thu Apr  2 03:47:41 2009
From: vogel at ct.metrocast.net (vogel at ct.metrocast.net)
Date: Wed, 1 Apr 2009 21:47:41 -0400
Subject: [coreboot] Soldering a socket on your board
References: <6f98bfb9dd28a51f61e9ab52b50d82cf@imap.1and1.com><20090327220759.27975.qmail@stuge.se><afed2e026b2e710a2237d61dcd7416d4@imap.1and1.com>
	<961e01bd9249d25e1d7071970e3e7cba@imap.1and1.com>
Message-ID: <5CF085516E104D29B565E7589A1E3190@JUNKNAME>

Does anyone know if the Gigabyte MA790GP-UD4H would be ok for a coreboot 
install ? It has Dual BIOS that allows a backup copy to take over in case 
there is any problem flashing a revised version.

Would this avoid the need for soldering a socket onto the board ?

Bob



----- Original Message ----- 
From: "Joseph Smith" <joe at settoplinux.org>
To: "Peter Stuge" <peter at stuge.se>; "Uwe" <uwe at hermann-uwe.de>; 
<coreboot at coreboot.org>
Sent: Monday, March 30, 2009 10:41 PM
Subject: Re: [coreboot] Soldering a socket on your board


>
>
>
> On Sun, 29 Mar 2009 23:40:13 -0400, Joseph Smith <joe at settoplinux.org>
> wrote:
>>
>>>> If I get time this weekend I will do it and take some picks if you
>>>> want.
>>>
>>> In any case I think that would be great!
>>>
>>>
>> Ok all done. http://www.coreboot.org/Soldering_a_socket_on_your_board
>>
>
> I added a quick "Tips" section with a few things I have learned over the
> hardware hacking years, check it out :-)
>
> -- 
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
>
>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot 




From c-d.hailfinger.devel.2006 at gmx.net  Thu Apr  2 04:04:16 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Apr 2009 04:04:16 +0200
Subject: [coreboot] Soldering a socket on your board
In-Reply-To: <5CF085516E104D29B565E7589A1E3190@JUNKNAME>
References: <6f98bfb9dd28a51f61e9ab52b50d82cf@imap.1and1.com><20090327220759.27975.qmail@stuge.se><afed2e026b2e710a2237d61dcd7416d4@imap.1and1.com>	<961e01bd9249d25e1d7071970e3e7cba@imap.1and1.com>
	<5CF085516E104D29B565E7589A1E3190@JUNKNAME>
Message-ID: <49D41D20.5050904@gmx.net>

On 02.04.2009 03:47, vogel at ct.metrocast.net wrote:
> Does anyone know if the Gigabyte MA790GP-UD4H would be ok for a
> coreboot install ? It has Dual BIOS that allows a backup copy to take
> over in case there is any problem flashing a revised version.

Sorry, that chipset is unsupported.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From russ at ashlandhome.net  Thu Apr  2 03:56:52 2009
From: russ at ashlandhome.net (Russell Whitaker)
Date: Wed, 1 Apr 2009 18:56:52 -0700 (PDT)
Subject: [coreboot] build optimization
In-Reply-To: <20090402000706.GA16223@localdomain>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
	<dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
	<13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>
	<20090402000706.GA16223@localdomain>
Message-ID: <alpine.LNX.2.00.0904011842150.1903@bigred.russwhit.org>



On Wed, 1 Apr 2009, Ward Vandewege wrote:

> On Wed, Apr 01, 2009 at 04:45:44PM -0700, ron minnich wrote:
>> On Wed, Apr 1, 2009 at 4:42 PM, Corey Osgood <corey.osgood at gmail.com> wrote:
>>> I think you're missing part of the patch, there should be a settings.h
>>> included, right?
>>
>> no,that is generated by the >> in the patch.
>>
>> I kind of like this. But, if the python is run twice, do you get the
>> file twice as large? There's no "zero out the file" step from what i
>> can see.
>
> Hmm. Seems like replacing the >> by > should fix that.
>
I suspect the patch should look something like:

+	file.write('/* autogenerated */' > settings.h)\n")
+	file.write("D_item = $(shell echo '$(if $(subst undefined,,$(origin $1)),\\#define $1$(if $($1), $($1),),\\#undef $1)' >> settings.h)\n\n")
+	file.write("CPUFLAGS := $(strip $(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))--include=settings.h)\n\n")

Now the first line forces a new copy and (if I didn't goof it up) the 2nd
and 3rd lines can add multiple lines to settings.h

Perhaps the nest step would be to combine the 2nd & 3rd lines.

    Russ



From vinuxes at gmail.com  Thu Apr  2 07:55:22 2009
From: vinuxes at gmail.com (vinuxesgmail)
Date: Thu, 02 Apr 2009 11:25:22 +0530
Subject: [coreboot] flashrom fails to write/erase on VIA VT8237
In-Reply-To: <20090401170617.5933.qmail@stuge.se>
References: <49D05438.4040102@gmail.com>
	<49D09607.6010808@gmail.com>	<20090330115759.6344.qmail@stuge.se>
	<49D19BAE.3060009@gmail.com>	<20090331043750.4384.qmail@stuge.se>
	<49D1A3A7.7050703@gmail.com>	<fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>
	<20090401170617.5933.qmail@stuge.se>
Message-ID: <49D4534A.2080506@gmail.com>

Hi Peter,
    Here's the output of all the commands:

stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l
    00
    00000401

 >> Extract 8-15 bits from long value: 04

stress:/tmp # ./io r044f
    r0x044f=ff

stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -r backup.bin
    Calibrating delay loop... OK.
    No coreboot table found.
    Found chipset "VIA VT8237", enabling flash write... OK.
    Found board "Portwell PPAP-2020VL", enabling flash write... OK.
    Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
    Reading flash... done.

stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E          
    Calibrating delay loop... OK.
    No coreboot table found.
    Found chipset "VIA VT8237", enabling flash write... OK.
    Found board "Portwell PPAP-2020VL", enabling flash write... OK.
    Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
    Erasing flash chip... ERASE FAILED!
    FAILED!
    ERROR at 0x00000000: Expected=0xff, Read=0x49

stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin
    Calibrating delay loop... OK.
    No coreboot table found.
    Found chipset "VIA VT8237", enabling flash write... OK.
    Found board "Portwell PPAP-2020VL", enabling flash write... OK.
    Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
    Flash image seems to be a legacy BIOS. Disabling checks.
    ERASE FAILED!

stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l
    00
    00000401

stress:/tmp # ./io r044f
    r0x044f=ff

Rgds,
Vinod

Peter Stuge wrote:
> Ok. I guess my board enable code doesn't work properly. Maybe you can
> help me look into the relevant registers manually?
>
> Please download http://stuge.se/io.c and compile it using:
> gcc -O2 -o io io.c
>
> Please run:
> setpci -d 1106:3227 e6.b 88.l
>
> The command should print one hexadecimal byte and one hex long.
> Please save these values.
>
> Use bits 8-15 as port bits 8-15 and use 4f as bits 0-7, then please
> run io:
> ./io r__4f
>
> (Replace __ here with bits 8-15 from the hex long value from setpci.)
>
> After this, please run flashrom with the patch. (It will still fail.)
>
> Then please run the setpci and io command again, and finally send an
> email with the output from all commands.
>
>
> Thanks for your help!
>
> //Peter



From paulepanter at users.sourceforge.net  Thu Apr  2 08:46:05 2009
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 02 Apr 2009 08:46:05 +0200
Subject: [coreboot] [PATCH] flashrom: README / manpage fixes
In-Reply-To: <20090401014520.GC22189@greenwood>
References: <20090401014520.GC22189@greenwood>
Message-ID: <1238654765.19966.4.camel@mattotaupa.wohnung.familie-menzel.net>

Dear Uwe,


I found one typo.


Am Mittwoch, den 01.04.2009, 03:45 +0200 schrieb Uwe Hermann:
> Index: flashrom.8
> ===================================================================
> --- flashrom.8  (Revision 4038)
> +++ flashrom.8  (Arbeitskopie)
> @@ -1,14 +1,17 @@
>  .TH FLASHROM 8 "January 5, 2009"
>  .SH NAME
> -flashrom \- a universal BIOS/ROM/flash programming utility
> +flashrom \- utility for reading, writing, and erasong BIOS/ROM/flash chips

s/erasong/erasing/

>  .SH SYNOPSIS
>  .B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
>           [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
>  .SH DESCRIPTION
>  .B flashrom
> -is a universal flash programming utility for DIP, PLCC, or SPI flash ROM
> -chips. It can be used to flash BIOS/coreboot/firmware images, for example.
> -.sp
> +is a utility for reading, writing, and erasing flash ROM chips.
> +It's often used to flash BIOS/coreboot/firmware images.
> +.PP
> +It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
> +various protocols such as LPC, FWH, parallel flash, or SPI.
> +.PP
>  (see
>  .B http://coreboot.org
>  for details on coreboot)
> @@ -16,17 +19,21 @@
>  If no file is specified, then all that happens
>  is that flash info is dumped and the flash chip is set to writable.
>  .TP
> -.B "\-r, \-\-read"
> -Read flash ROM contents and save them into the given file.
> +.B "\-r, \-\-read <file>"
> +Read flash ROM contents and save them into the given
> +.BR <file> .
>  .TP
> -.B "\-w, \-\-write"
> -Write file into flash ROM (default when file is specified).
> +.B "\-w, \-\-write <file>"
> +Write file into flash ROM (default when
> +.B <file>
> +is specified).
>  .TP
> -.B "\-v, \-\-verify"
> -Verify the flash ROM contents against the given file.
> +.B "\-v, \-\-verify <file>"
> +Verify the flash ROM contents against the given
> +.BR <file> .
>  .TP
>  .B "\-E, \-\-erase"
> -Erase the flash ROM device.
> +Erase the flash ROM chip.
>  .TP
>  .B "\-V, \-\-verbose"
>  More verbose output.
> @@ -53,10 +60,11 @@
>  Note: This check only works while coreboot is running, and only for those
>  boards where the coreboot code supports it.
>  .TP
> -.B "\-l, \-\-layout" <layout.file>
> -Read ROM layout from file.
> +.B "\-l, \-\-layout <file>"
> +Read ROM layout from
> +.BR <file> .
>  .TP
> -.B "\-i, \-\-image" <name>
> +.B "\-i, \-\-image <name>"
>  Only flash image
>  .B <name>
>  from flash layout.
> @@ -71,6 +79,9 @@
>  are listed at
>  .BR http://coreboot.org/Flashrom#Supported_mainboards ,
>  but the list is not exhaustive, of course.
> +.sp
> +Please let us know if you can verify other boards to work or not work out
> +of the box.
>  .TP
>  .B "\-h, \-\-help"
>  Show a help text and exit.
> Index: README
> ===================================================================
> --- README      (Revision 4038)
> +++ README      (Arbeitskopie)
> @@ -2,9 +2,12 @@
>  Flashrom README
>  -------------------------------------------------------------------------------
>  
> -Flashrom is a universal flash programming utility for DIP, PLCC, or SPI
> -flash ROM chips. It can be used to flash BIOS/coreboot/firmware images.
> +Flashrom is a utility for reading, writing, and erasing flash ROM chips.
> +It's often used to flash BIOS/coreboot/firmware images.
>  
> +It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
> +various protocols such as LPC, FWH, parallel flash, or SPI.
> +
>  (see http://coreboot.org for details on coreboot)
>  
>  
> @@ -46,16 +49,17 @@
>  
>  Exit status
>  -----------
> -flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem
> +
> +Flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem
>  (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails.
>  
>  
>  coreboot Table and Mainboard Identification
>  --------------------------------------------
>  
> -Flashrom reads the coreboot table to determine the current mainboard
> -(parse DMI as well in future?). If no coreboot table could be read
> -or if you want to override these values, you can specify -m, e.g.:
> +Flashrom reads the coreboot table to determine the current mainboard. If no
> +coreboot table could be read or if you want to override these values, you can
> +specify -m, e.g.:
>  
>   $ flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom
>  
> @@ -94,15 +98,6 @@
>  ROM layout and the ROM image in one file (cpio, zip or something?).
>  
>  
> -Disk on Chip support
> ---------------------
> -
> -Disk on Chip support was removed from flashrom in r3382. It had already
> -been disabled by default in flashrom for several years because the code
> -was considered unstable and incomplete. The products intended to work
> -have been End-Of-Lifed by the manufacturer for a long time.
> -
> -
>  Supported Flash Chips / Chipsets / Mainboards
>  ---------------------------------------------


Thanks,

Paul
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From Zheng.Bao at amd.com  Thu Apr  2 10:24:47 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Thu, 2 Apr 2009 16:24:47 +0800
Subject: [coreboot] command uuid in grub.conf
Message-ID: <DD1CC71B621B004FA76856E5129D6B17028CF088@sbjgexmb1.amd.com>

Hi, All,
The ubuntu now uses the commline:
uuid 2a628170-1f5a-11de-8c30-0800200c9a66
instead of:
root (hd0,0)

Either current stable version of grub2 or filo doesn't support command
UUID. I am wondering if it is an issue that you guys have already known.
Any plan I don't know?

The ubuntu community uses a patched legacy grub 0.97 to support uuid
command.
http://packages.ubuntu.com/source/intrepid/grub/

Joe




From mart.raudsepp at artecdesign.ee  Thu Apr  2 11:42:04 2009
From: mart.raudsepp at artecdesign.ee (Mart Raudsepp)
Date: Thu, 02 Apr 2009 12:42:04 +0300
Subject: [coreboot] [v3] r1162 -
 coreboot-v3/northbridge/intel/i440bxemulation
In-Reply-To: <13426df10903240722x5557e4ccmd703930ce8251253@mail.gmail.com>
References: <20090323235617.4303gmx1@mx047.gmx.net> <49C8DAD0.4030509@gmx.net>
	<13426df10903240722x5557e4ccmd703930ce8251253@mail.gmail.com>
Message-ID: <1238665324.5560.3.camel@martr-gentoo.artec>

?hel kenal p?eval, T, 2009-03-24 kell 07:22, kirjutas ron minnich:
> On Tue, Mar 24, 2009 at 6:06 AM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> 
> > Emergency fixup for the missing is_coldboot().
> 
> overusing weak functions is a danger, I think. Every chipset or cpu
> should have a way to tell if the CPU is doing a coldboot. It is a bit
> dangerous for us to become too reliant on weak symbols.

Many CPU's don't need to do anything different on a coldboot vs hotboot
it seems like. Requiring all CPU's to start adding is_coldboot functions
that return a completely fake return value (as if it would always
coldboot, which surely isn't the case in reality) is not so good of an
idea either.

What's sure is that qemu is not special here to get an is_coldboot()
function while other boards don't and therefore rely on the weak symbol.

So r1162 should be reverted or r1161 reverted after addition of
is_coldboot() to all of the many necessary places.
I definitely prefer the former.

> >
> > Note that the weak is_coldboot() returns always 1.
> > The i945 is_coldboot() returns 1 for a warm boot?
> 
> 
> well, that's a mistake if so.

Lets fix it then? :)



Regards,
Mart Raudsepp




From uwe at hermann-uwe.de  Thu Apr  2 16:40:49 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 2 Apr 2009 16:40:49 +0200
Subject: [coreboot] [v2] r4040 - trunk/coreboot-v2/src/boot
In-Reply-To: <E1LoyEp-0003Wq-Q7@mi019.mc1.hosteurope.de>
References: <E1LoyEp-0003Wq-Q7@mi019.mc1.hosteurope.de>
Message-ID: <20090402144049.GA25703@greenwood>

On Wed, Apr 01, 2009 at 01:03:32PM +0200, svn at coreboot.org wrote:
> Add copyright notices to two files, src/boot/elfboot.c
> and its derivative src/boot/selfboot.c.

Nice, thanks for fixing that!


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Thu Apr  2 17:49:04 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Apr 2009 08:49:04 -0700
Subject: [coreboot] [v3] r1162 -
	coreboot-v3/northbridge/intel/i440bxemulation
In-Reply-To: <1238665324.5560.3.camel@martr-gentoo.artec>
References: <20090323235617.4303gmx1@mx047.gmx.net> <49C8DAD0.4030509@gmx.net>
	<13426df10903240722x5557e4ccmd703930ce8251253@mail.gmail.com>
	<1238665324.5560.3.camel@martr-gentoo.artec>
Message-ID: <13426df10904020849n6ab0ecfcq4464f98af927cc5c@mail.gmail.com>

On Thu, Apr 2, 2009 at 2:42 AM, Mart Raudsepp
<mart.raudsepp at artecdesign.ee> wrote:

> So r1162 should be reverted or r1161 reverted after addition of
> is_coldboot() to all of the many necessary places.
> I definitely prefer the former.

Go ahead and do that in a way that works for you, I'll ack it.

thanks

ron



From samuel.verstraete at gmail.com  Thu Apr  2 19:12:46 2009
From: samuel.verstraete at gmail.com (samuel)
Date: Thu, 2 Apr 2009 19:12:46 +0200
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <49D31404.1070603@uni-hd.de>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
Message-ID: <bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>

OK,

I managed booting the firmware... I never worked with serial ports and
stuff so this took me a while to grab the idea...

Anyway,
you can find the boot.log on http://merlin.ugent.be/~samuel/dl145g3/boot.log

Obviously that boot line is wrong.
http://merlin.ugent.be/~samuel/dl145g3/filo_config
obviously CONFIG_MENULST_FILE="hda3:/boot/filo/menu.lst" is wrong. My
kernel I'd like to boot is hda1:/2.6.28.8_x86-64

Trying to boot this as follows:

kernel hda1:/2.6.28.8_x86_64

results in:

Drive 0 does not exist
Error 15: File not found.

I'm a bit stuck I'm afraid, afaik i did patch filo with the patch from
mondrian so prolly me config of filo is wrong?

Kind regards,

Samuel



From samuel.verstraete at gmail.com  Thu Apr  2 20:38:41 2009
From: samuel.verstraete at gmail.com (samuel)
Date: Thu, 2 Apr 2009 20:38:41 +0200
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
	<bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
Message-ID: <bc122a250904021138w551598ceq2192e2e97cb756bf@mail.gmail.com>

ok... Fixed that too :)

used the following bootline: kernel hda1:/2.6.28.8-x86_64
root=/dev/md1 console=tty0 console=ttyS0,115200

and that worked like a charm...
Logged in with ssh and it works :D
Even kvm was just working:
from dmesg: loaded kvm module (kvm-84)

just wonderfull



So now on to the "issue list"
1. Cpu's are indeed running at 1Ghz. Running cpufreq-info says: no or
unknown cpufreq driver is active on this CPU

2. not all that important but some vga output would be convenient..
.right now it's doing nothing...


Anyway i need to thank everyone already for helping me gettng this far
:) I hope to get the procs running at full speed and then we can start
virtualzing machine :D

Kind regards,

Samuel



From paulepanter at users.sourceforge.net  Thu Apr  2 20:45:41 2009
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 02 Apr 2009 20:45:41 +0200
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
	<bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
Message-ID: <1238697941.6036.3.camel@mattotaupa.wohnung.familie-menzel.net>

Am Donnerstag, den 02.04.2009, 19:12 +0200 schrieb samuel:
> OK,
> 
> I managed booting the firmware... I never worked with serial ports and
> stuff so this took me a while to grab the idea...
> 
> Anyway,
> you can find the boot.log on http://merlin.ugent.be/~samuel/dl145g3/boot.log
> 
> Obviously that boot line is wrong.
> http://merlin.ugent.be/~samuel/dl145g3/filo_config
> obviously CONFIG_MENULST_FILE="hda3:/boot/filo/menu.lst" is wrong. My
> kernel I'd like to boot is hda1:/2.6.28.8_x86-64
> 
> Trying to boot this as follows:
> 
> kernel hda1:/2.6.28.8_x86_64
> 
> results in:
> 
> Drive 0 does not exist
> Error 15: File not found.
> 
> I'm a bit stuck I'm afraid, afaik i did patch filo with the patch from
> mondrian so prolly me config of filo is wrong?

I have never tried it myself. But as far as I know FILO handles config
files from GRUB, where is written what options are available for boot.
So if you have used GRUB before, you have to point the config to this
file.


Thanks,

Paul
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From marcj303 at gmail.com  Thu Apr  2 20:54:57 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 2 Apr 2009 12:54:57 -0600
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <bc122a250904021138w551598ceq2192e2e97cb756bf@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
	<bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
	<bc122a250904021138w551598ceq2192e2e97cb756bf@mail.gmail.com>
Message-ID: <534e5dc20904021154x3a28d59ayb11d72262dff3e76@mail.gmail.com>

> So now on to the "issue list"
> 1. Cpu's are indeed running at 1Ghz. Running cpufreq-info says: no or
> unknown cpufreq driver is active on this CPU
>

#define K8_SET_FIDVID 0 needs to be a 1 for full speed but there might
need to be some tweaking in cache_as_ram.c where it is used. Compare
it with a known working mainboard.

Marc

-- 
http://marcjonesconsulting.com



From samuel.verstraete at gmail.com  Thu Apr  2 21:43:00 2009
From: samuel.verstraete at gmail.com (samuel)
Date: Thu, 2 Apr 2009 21:43:00 +0200
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <534e5dc20904021154x3a28d59ayb11d72262dff3e76@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
	<bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
	<bc122a250904021138w551598ceq2192e2e97cb756bf@mail.gmail.com>
	<534e5dc20904021154x3a28d59ayb11d72262dff3e76@mail.gmail.com>
Message-ID: <bc122a250904021243j56b3c91at68137b88d79b745c@mail.gmail.com>

On Thu, Apr 2, 2009 at 8:54 PM, Marc Jones <marcj303 at gmail.com> wrote:
>> So now on to the "issue list"
>> 1. Cpu's are indeed running at 1Ghz. Running cpufreq-info says: no or
>> unknown cpufreq driver is active on this CPU
>>
>
> #define K8_SET_FIDVID 0 needs to be a 1 for full speed but there might
> need to be some tweaking in cache_as_ram.c where it is used. Compare
> it with a known working mainboard.


That indeed did the trick. It's running at 2.6Ghz now :)

>
> Marc
>
> --
> http://marcjonesconsulting.com
>



From harald.gutmann at gmx.net  Thu Apr  2 22:01:36 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Apr 2009 22:01:36 +0200
Subject: [coreboot] Fix some PCI issues on M57SLI v2
In-Reply-To: <200904020022.36806.harald.gutmann@gmx.net>
References: <200903241854.53171.harald.gutmann@gmx.net>
	<20090331155740.GA29619@localdomain>
	<200904020022.36806.harald.gutmann@gmx.net>
Message-ID: <200904022201.41702.harald.gutmann@gmx.net>

The last patch had a mistake somewhere because patch complains about a malform 
patch format.

This one is the same, and just comments have been modified slightly.

Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>


Kind Regards,
Harald
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From corey.osgood at gmail.com  Thu Apr  2 22:14:07 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 2 Apr 2009 16:14:07 -0400
Subject: [coreboot] coreboot v4.1
In-Reply-To: <0e2686929cfccf36d7ddfc5e03782e73@imap.1and1.com>
References: <49D345AB.6030808@gmx.net> <49D3A7AE.6010106@gmx.net>
	<0e2686929cfccf36d7ddfc5e03782e73@imap.1and1.com>
Message-ID: <dd3c80060904021314y63ccc354h10d45e3607c485d7@mail.gmail.com>

Now that April fool's day is over, should we take this off the front page
and put a disclaimer on the coreboot-v4.1 page?

-Corey

On Wed, Apr 1, 2009 at 3:45 PM, Joseph Smith <joe at settoplinux.org> wrote:

>
>
>
> On Wed, 01 Apr 2009 19:43:10 +0200, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> > I forgot the source tarball.
> >
> Wow, the source dircetory is only 4.62k. With source that small we could
> definitely fit a browser!!!
>
> --
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From peter at stuge.se  Thu Apr  2 22:14:35 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Apr 2009 22:14:35 +0200
Subject: [coreboot] command uuid in grub.conf
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17028CF088@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17028CF088@sbjgexmb1.amd.com>
Message-ID: <20090402201435.9403.qmail@stuge.se>

Bao, Zheng wrote:
> Either current stable version of grub2 or filo doesn't support
> command UUID.
> I am wondering if it is an issue that you guys have already known.

I can confirm that FILO does not support UUID.


> Any plan I don't know?

The issue of UUIDs has not come up before. There's no plan. I think
it would be a useful improvement.


//Peter



From vikhegde at gmail.com  Thu Apr  2 22:29:59 2009
From: vikhegde at gmail.com (Vikram Hegde)
Date: Thu, 2 Apr 2009 13:29:59 -0700
Subject: [coreboot] command uuid in grub.conf
In-Reply-To: <20090402201435.9403.qmail@stuge.se>
References: <DD1CC71B621B004FA76856E5129D6B17028CF088@sbjgexmb1.amd.com> 
	<20090402201435.9403.qmail@stuge.se>
Message-ID: <61326240904021329u1e7727f6ud518d9d3a56538c7@mail.gmail.com>

Hi,

Solaris now uses findroot command (also available only in patched GRUB).
Both findroot and uuid commands were created because the root command
(specifically "hd") is fiendishly difficult to determine from an OS. The
"hd" is the BIOS disk ID which the BIOS can assign as it pleases and very
difficult for the OS to determine what the mapping from BIOS ID to disk is
particularly when you change boot disks.

Vikram

On Thu, Apr 2, 2009 at 1:14 PM, Peter Stuge <peter at stuge.se> wrote:

> Bao, Zheng wrote:
> > Either current stable version of grub2 or filo doesn't support
> > command UUID.
> > I am wondering if it is an issue that you guys have already known.
>
> I can confirm that FILO does not support UUID.
>
>
> > Any plan I don't know?
>
> The issue of UUIDs has not come up before. There's no plan. I think
> it would be a useful improvement.
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From samuel.verstraete at gmail.com  Thu Apr  2 22:45:16 2009
From: samuel.verstraete at gmail.com (samuel)
Date: Thu, 2 Apr 2009 22:45:16 +0200
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <bc122a250904021243j56b3c91at68137b88d79b745c@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
	<bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
	<bc122a250904021138w551598ceq2192e2e97cb756bf@mail.gmail.com>
	<534e5dc20904021154x3a28d59ayb11d72262dff3e76@mail.gmail.com>
	<bc122a250904021243j56b3c91at68137b88d79b745c@mail.gmail.com>
Message-ID: <bc122a250904021345nfe918efu636855959ae507aa@mail.gmail.com>

Anyone has any hints on how to get the vga port going?

and another thing...
I'm trying to get filo/grub to autoload my config file i made... i
stored it on /dev/sda1 (together with the kernel) but it is not
loading that file... it simply goes straight to the prompt. No error
nothing...

the config i made looks like this:
#
timeout 10
default 0
fallback 1

title 2.6.28.8-x86_64
kernel /dev/sda1/2.6.28.8-x86_64 root=/dev/md1 console=tty0 console=ttyS0,115200
#



any ideas?



From ronald at zonnet.nl  Thu Apr  2 22:48:52 2009
From: ronald at zonnet.nl (Ronald Hoogenboom)
Date: Thu, 02 Apr 2009 22:48:52 +0200
Subject: [coreboot] build optimization
In-Reply-To: <alpine.LNX.2.00.0904011842150.1903@bigred.russwhit.org>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
	<dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
	<13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>
	<20090402000706.GA16223@localdomain>
	<alpine.LNX.2.00.0904011842150.1903@bigred.russwhit.org>
Message-ID: <1238705332.2791.9.camel@amd-x2.grundel>

On Wed, 2009-04-01 at 18:56 -0700, Russell Whitaker wrote:
> 
> On Wed, 1 Apr 2009, Ward Vandewege wrote:
> 
> > On Wed, Apr 01, 2009 at 04:45:44PM -0700, ron minnich wrote:
> >> On Wed, Apr 1, 2009 at 4:42 PM, Corey Osgood <corey.osgood at gmail.com> wrote:
> >>> I think you're missing part of the patch, there should be a settings.h
> >>> included, right?
> >>
> >> no,that is generated by the >> in the patch.
> >>
> >> I kind of like this. But, if the python is run twice, do you get the
> >> file twice as large? There's no "zero out the file" step from what i
> >> can see.
> >
> > Hmm. Seems like replacing the >> by > should fix that.
> >
> I suspect the patch should look something like:
> 
> +	file.write('/* autogenerated */' > settings.h)\n")
> +	file.write("D_item = $(shell echo '$(if $(subst undefined,,$(origin $1)),\\#define $1$(if $($1), $($1),),\\#undef $1)' >> settings.h)\n\n")
> +	file.write("CPUFLAGS := $(strip $(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))--include=settings.h)\n\n")
> 
> Now the first line forces a new copy and (if I didn't goof it up) the 2nd
> and 3rd lines can add multiple lines to settings.h
> 
> Perhaps the nest step would be to combine the 2nd & 3rd lines.
> 
>     Russ
Hi guys,

The original patch has all of that already. Please test it before
complaining....

The settings.h is generated from scratch each time the Makefile is read,
because each time the CPUFLAGS will be set to its value (it's a simply
expanded variable!, see 'info make'). The first $(shell echo...) will
truncate the file (or create an new one) and put the 'autogenerated'
line in. The subsequent echo's in the D_item macro will append #define
lines to that file. These $(shell ) functions will only contribute
whitespace to the CPUFLAGS variable, because of the redirection. The
whitespace is later stripped off by the strip function.

Ronald.




From c-d.hailfinger.devel.2006 at gmx.net  Thu Apr  2 22:49:43 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Apr 2009 22:49:43 +0200
Subject: [coreboot] coreboot v4.1
In-Reply-To: <dd3c80060904021314y63ccc354h10d45e3607c485d7@mail.gmail.com>
References: <49D345AB.6030808@gmx.net> <49D3A7AE.6010106@gmx.net>	
	<0e2686929cfccf36d7ddfc5e03782e73@imap.1and1.com>
	<dd3c80060904021314y63ccc354h10d45e3607c485d7@mail.gmail.com>
Message-ID: <49D524E7.7050807@gmx.net>

On 02.04.2009 22:14, Corey Osgood wrote:
> Now that April fool's day is over, should we take this off the front page
> and put a disclaimer on the coreboot-v4.1 page?
>   

Done.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mylesgw at gmail.com  Thu Apr  2 23:00:18 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Apr 2009 15:00:18 -0600
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <bc122a250904021345nfe918efu636855959ae507aa@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
	<bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
	<bc122a250904021138w551598ceq2192e2e97cb756bf@mail.gmail.com>
	<534e5dc20904021154x3a28d59ayb11d72262dff3e76@mail.gmail.com>
	<bc122a250904021243j56b3c91at68137b88d79b745c@mail.gmail.com>
	<bc122a250904021345nfe918efu636855959ae507aa@mail.gmail.com>
Message-ID: <2831fecf0904021400g3bbacf43q2242c410370bd4c0@mail.gmail.com>

On Thu, Apr 2, 2009 at 2:45 PM, samuel <samuel.verstraete at gmail.com> wrote:
> Anyone has any hints on how to get the vga port going?

I don't see it getting initialized.  I don't see a line where the ROM
is being run in your log.

Have you tried extracting the VGA BIOS?

Do you have a vga card to try?

> and another thing...
> I'm trying to get filo/grub to autoload my config file i made... i
> stored it on /dev/sda1 (together with the kernel) but it is not
> loading that file... it simply goes straight to the prompt. No error
> nothing...
>
> the config i made looks like this:
> #
> timeout 10
> default 0
> fallback 1
>
> title 2.6.28.8-x86_64
> kernel /dev/sda1/2.6.28.8-x86_64 root=/dev/md1 console=tty0 console=ttyS0,115200
/dev/sda1 looks wrong here.  Have you tried hda1 (like your working boot line)?

Myles



From rminnich at gmail.com  Thu Apr  2 23:24:10 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Apr 2009 14:24:10 -0700
Subject: [coreboot] build optimization
In-Reply-To: <1238705332.2791.9.camel@amd-x2.grundel>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
	<dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
	<13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>
	<20090402000706.GA16223@localdomain>
	<alpine.LNX.2.00.0904011842150.1903@bigred.russwhit.org>
	<1238705332.2791.9.camel@amd-x2.grundel>
Message-ID: <13426df10904021424r42fc716am58bbb1e36f2842dc@mail.gmail.com>

On Thu, Apr 2, 2009 at 1:48 PM, Ronald Hoogenboom <ronald at zonnet.nl> wrote:

> The original patch has all of that already. Please test it before
> complaining....

yeah, I missed that, was not complaining, was asking.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From ronald at zonnet.nl  Thu Apr  2 23:50:46 2009
From: ronald at zonnet.nl (Ronald Hoogenboom)
Date: Thu, 02 Apr 2009 23:50:46 +0200
Subject: [coreboot] build optimization
In-Reply-To: <13426df10904021424r42fc716am58bbb1e36f2842dc@mail.gmail.com>
References: <mailman.481.1238624568.24014.coreboot@coreboot.org>
	<1238627760.2840.11.camel@amd-x2.grundel>
	<dd3c80060904011642m4c485ea1s914038cea07135ec@mail.gmail.com>
	<13426df10904011645g1946f14ax5ff0cd6018690bbc@mail.gmail.com>
	<20090402000706.GA16223@localdomain>
	<alpine.LNX.2.00.0904011842150.1903@bigred.russwhit.org>
	<1238705332.2791.9.camel@amd-x2.grundel>
	<13426df10904021424r42fc716am58bbb1e36f2842dc@mail.gmail.com>
Message-ID: <1238709046.2791.17.camel@amd-x2.grundel>

On Thu, 2009-04-02 at 14:24 -0700, ron minnich wrote:

> yeah, I missed that, was not complaining, was asking.
> 
Ok, sorry for responding so slow. And I didn't expect so many responses
for such a small change...

> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Thanks.
Ronald.




From mjt at nysv.org  Fri Apr  3 00:11:57 2009
From: mjt at nysv.org (Markus Törnqvist)
Date: Fri, 3 Apr 2009 01:11:57 +0300
Subject: [coreboot] VIA Epia-MII stuff
Message-ID: <20090402221156.GN638@nysv.org>

Hi

I dug out my abandoned Epia to see if I could do something with it,
and based the stuff on

http://www.coreboot.org/VIA_EPIA-MII

There were some things I found weird and I'm hoping someone could
shed light on them..

The web says:
"The configuration as set up by the buildtarget process will create a coreboot
file which is exactly 196608 bytes long, which is exactly 64K bytes short of
what needs to go into the 256K flash rom."

For me, that's not true.
root at coraline:/usr/src/coreboot-v2-4046/targets/via/epia-m/epia-m# ls -l
normal/coreboot.rom fallback/coreboot.rom 
-rw-r--r-- 1 root src 131072 Apr  2 20:46 fallback/coreboot.rom
-rw-r--r-- 1 root src 131072 Apr  2 20:46 normal/coreboot.rom

Q1: Why is there a mismatch here?

Also, when encouraged to change the cat like
    cat fallback/coreboot.rom > coreboot.rom
to
    cat /video.bios.bin fallback/coreboot.rom >coreboot.rom

it wasn't accurate; the line is
    cat  normal/coreboot.rom  fallback/coreboot.rom > ./coreboot.rom

Let's remember those two are 262144 bytes, because now the wiki
tells us to add the 64k video.

It obviously doesn't fit in 256k, if we're there already, so what I
actually did was cat the video bios TWICE(!!) and then the normal
bios to make it 256k.

That seems kludgy but I got a FILO prompt :)

Q2: Ideas on why I had to do that?

Here's the Config.lb, where I just changed the FILO payload
to /filo.nohting.elf (to reflect the fact nothing seems to fit
in a rom this small ;)

Thanks!

# Sample config file for EPIA-M
# This will make a target directory of ./epia-m

target epia-m

mainboard via/epia-m

option  MAXIMUM_CONSOLE_LOGLEVEL=8
option  DEFAULT_CONSOLE_LOGLEVEL=8
option  CONFIG_CONSOLE_SERIAL8250=1

option ROM_SIZE=256*1024

option HAVE_OPTION_TABLE=1
option CONFIG_ROM_PAYLOAD=1
option HAVE_FALLBACK_BOOT=1

###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072

## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000

#
###
### Compute the start location and size size of
### The coreboot bootloader.
###

#
# EPIA-M
#

romimage "fallback" 
  option USE_FALLBACK_IMAGE=1
  option ROM_IMAGE_SIZE=0x10000
  option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf  
# payload ../../../../../lnxieepro100.ebi
  payload /filo.nothing.elf
end

romimage "normal" 
  option USE_FALLBACK_IMAGE=1
  option ROM_IMAGE_SIZE=0x10000
  option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf  
# payload ../../../../../lnxieepro100.ebi
  payload /filo.nothing.elf
end

buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

-- 
mjt




From corey.osgood at gmail.com  Fri Apr  3 00:46:47 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 2 Apr 2009 18:46:47 -0400
Subject: [coreboot] VIA Epia-MII stuff
In-Reply-To: <20090402221156.GN638@nysv.org>
References: <20090402221156.GN638@nysv.org>
Message-ID: <dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>

2009/4/2 Markus T?rnqvist <mjt at nysv.org>

> Hi
>
> I dug out my abandoned Epia to see if I could do something with it,
> and based the stuff on
>
> http://www.coreboot.org/VIA_EPIA-MII
>
> There were some things I found weird and I'm hoping someone could
> shed light on them..
>
> The web says:
> "The configuration as set up by the buildtarget process will create a
> coreboot
> file which is exactly 196608 bytes long, which is exactly 64K bytes short
> of
> what needs to go into the 256K flash rom."
>
> For me, that's not true.
> root at coraline:/usr/src/coreboot-v2-4046/targets/via/epia-m/epia-m# ls -l
> normal/coreboot.rom fallback/coreboot.rom
> -rw-r--r-- 1 root src 131072 Apr  2 20:46 fallback/coreboot.rom
> -rw-r--r-- 1 root src 131072 Apr  2 20:46 normal/coreboot.rom
>
> Q1: Why is there a mismatch here?


Because with the open source xf86-unichrome and Luc Verhaegan's kernel
driver, it's now possible for the kernel to initialize a framebuffer console
and X video without the need for the VGA BIOS, so someone decided to change
the default to build a 256k image and remove the commented out line with the
192k size. I believe the console driver is included with recent kernels, but
I couldn't tell you the exact version. If you want to use a different
driver, modify this line:

option ROM_SIZE=256*1024

to be

option ROM_SIZE=192*1024

Then, re-run buildtarget, make clean, and make. You should end up with a
128k fallback image and 64k normal image (yes, it's a nasty solution, part
of the reason for v3), and a 192k image in build directory (the one you ran
make from), that's the image you should probably use. If you want to
continue using your current solution, you should probably use the fallback
coreboot.rom, as there is code that will attempt to boot from the fallback
image in the event of an error, and if there is no fallback image to boot
from, nasty things could happen. If anything's not clear, let me know, I'm
terrible at explaining things.

-Corey


>
>
> Also, when encouraged to change the cat like
>    cat fallback/coreboot.rom > coreboot.rom
> to
>    cat /video.bios.bin fallback/coreboot.rom >coreboot.rom
>
> it wasn't accurate; the line is
>    cat  normal/coreboot.rom  fallback/coreboot.rom > ./coreboot.rom
>
> Let's remember those two are 262144 bytes, because now the wiki
> tells us to add the 64k video.
>
> It obviously doesn't fit in 256k, if we're there already, so what I
> actually did was cat the video bios TWICE(!!) and then the normal
> bios to make it 256k.
>
> That seems kludgy but I got a FILO prompt :)
>
> Q2: Ideas on why I had to do that?
>
> Here's the Config.lb, where I just changed the FILO payload
> to /filo.nohting.elf (to reflect the fact nothing seems to fit
> in a rom this small ;)
>
> Thanks!
>
> # Sample config file for EPIA-M
> # This will make a target directory of ./epia-m
>
> target epia-m
>
> mainboard via/epia-m
>
> option  MAXIMUM_CONSOLE_LOGLEVEL=8
> option  DEFAULT_CONSOLE_LOGLEVEL=8
> option  CONFIG_CONSOLE_SERIAL8250=1
>
>
> option HAVE_OPTION_TABLE=1
> option CONFIG_ROM_PAYLOAD=1
> option HAVE_FALLBACK_BOOT=1
>
> ###
> ### Compute the location and size of where this firmware image
> ### (coreboot plus bootloader) will live in the boot rom chip.
> ###
> option FALLBACK_SIZE=131072
>
> ## Coreboot C code runs at this location in RAM
> option _RAMBASE=0x00004000
>
> #
> ###
> ### Compute the start location and size size of
> ### The coreboot bootloader.
> ###
>
> #
> # EPIA-M
> #
>
> romimage "fallback"
>  option USE_FALLBACK_IMAGE=1
>  option ROM_IMAGE_SIZE=0x10000
>  option COREBOOT_EXTRA_VERSION=".0Fallback"
> # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
> # payload ../../../../tg3--ide_disk.zelf
> # payload ../../../../../lnxieepro100.ebi
>  payload /filo.nothing.elf
> end
>
> romimage "normal"
>  option USE_FALLBACK_IMAGE=1
>  option ROM_IMAGE_SIZE=0x10000
>  option COREBOOT_EXTRA_VERSION=".0Fallback"
> # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
> # payload ../../../../tg3--ide_disk.zelf
> # payload ../../../../../lnxieepro100.ebi
>  payload /filo.nothing.elf
> end
>
> buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
>
> --
> mjt
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From svn at coreboot.org  Fri Apr  3 01:08:17 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 01:08:17 +0200
Subject: [coreboot] [v2] r4047 - trunk/coreboot-v2/util/newconfig
Message-ID: <mailman.2924.1355071508.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-03 01:08:16 +0200 (Fri, 03 Apr 2009)
New Revision: 4047

Modified:
   trunk/coreboot-v2/util/newconfig/config.g
Log:
Ronald Hoogenboom writes:
I've attached a patch that removes the 3-mile-long compiler
commandlines, which vim's quickfix doesn't like so much. Instead of
putting all those -DXYZ='bla' on the compiler commandline, they are put
in a file called settings.h (as #define XYZ bla) and only a
--include=settings.h is put on the commandline.
This file is created unconditionally at the same time as when the
CPUFLAGS simply expanded make variable used to be created (not via a
target rule and dependency), so it shouldn't change anything.

Signed-off-by: Ronald Hoogenboom <hoogenboom30 at zonnet.nl>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>




Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2009-04-01 22:07:53 UTC (rev 4046)
+++ trunk/coreboot-v2/util/newconfig/config.g	2009-04-02 23:08:16 UTC (rev 4047)
@@ -2049,9 +2049,9 @@
 	file.write("# Get the value of TOP, VARIABLES, and several other variables.\n")
 	file.write("include Makefile.settings\n\n")
 	file.write("# Function to create an item like -Di586 or -DCONFIG_MAX_CPUS='1' or -Ui686\n")
-	file.write("D_item = $(if $(subst undefined,,$(origin $1)),-D$1$(if $($1),='$($1)',),-U$1)\n\n")
+	file.write("D_item = $(shell echo '$(if $(subst undefined,,$(origin $1)),\\#define $1$(if $($1), $($1),),\\#undef $1)' >> settings.h)\n\n")
 	file.write("# Compute the value of CPUFLAGS here during make's first pass.\n")
-	file.write("CPUFLAGS := $(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))\n\n")
+	file.write("CPUFLAGS := $(strip $(shell echo '/* autogenerated */' > settings.h)$(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))--include=settings.h)\n\n")
 
 	for i in image.getuserdefines():
 		file.write("%s\n" %i)




From info at coresystems.de  Fri Apr  3 01:28:17 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 01:28:17 +0200
Subject: [coreboot] build service results for r4047
Message-ID: <E1LpWKX-0000zs-CV@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4047 to
the coreboot repository. This caused the following 
changes:

Change Log:
Ronald Hoogenboom writes:
I've attached a patch that removes the 3-mile-long compiler
commandlines, which vim's quickfix doesn't like so much. Instead of
putting all those -DXYZ='bla' on the compiler commandline, they are put
in a file called settings.h (as #define XYZ bla) and only a
--include=settings.h is put on the commandline.
This file is created unconditionally at the same time as when the
CPUFLAGS simply expanded make variable used to be created (not via a
target rule and dependency), so it shouldn't change anything.

Signed-off-by: Ronald Hoogenboom <hoogenboom30 at zonnet.nl>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>




Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:rumba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=rumba&vendor=amd&num=2
Compilation of asi:mb_5blgp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:mew-am has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=winnetp680&vendor=bcom&num=2
Compilation of biostar:m6tba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=s1850&vendor=dell&num=2
Compilation of digitallogic:adl855pc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm586seg has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=msm586seg&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=5bcm&vendor=eaglelion&num=2
Compilation of emulation:qemu-x86 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga-6bxc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of iei:juki-511p has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=juki-511p&vendor=iei&num=2
Compilation of iei:nova4899r has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=nova4899r&vendor=iei&num=2
Compilation of intel:jarrell has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=xe7501devkit&vendor=intel&num=2
Compilation of jetway:j7f24 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=j7f24&vendor=jetway&num=2
Compilation of lippert:frontrunner has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=frontrunner&vendor=lippert&num=2
Compilation of msi:ms6119 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=ms6178&vendor=msi&num=2
Compilation of nec:powermate2000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=powermate2000&vendor=nec&num=2
Compilation of olpc:btest has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=rev_a&vendor=olpc&num=2
Compilation of rca:rm4100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=rm4100&vendor=rca&num=2
Compilation of supermicro:x6dai_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technologic:ts5300 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=ip1000&vendor=thomson&num=2
Compilation of tyan:s1846 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=s1846&vendor=tyan&num=2
Compilation of via:epia has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=epia&vendor=via&num=2
Compilation of via:epia-cn has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=epia-m&vendor=via&num=2
Compilation of via:pc2500e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=pc2500e&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Fri Apr  3 01:43:26 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 01:43:26 +0200
Subject: [coreboot] build service results for r4047
In-Reply-To: <E1LpWKX-0000zs-CV@ra.coresystems.de>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de>
Message-ID: <20090402234326.2802.qmail@stuge.se>

coreboot information wrote:
> See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4047&device=atc-6220&vendor=a-trend&num=2

../romcc -O2 -mcpu=p2 --label-prefix=failover -Icoreboot-v2-4047/src
-I. -Icoreboot-v2-4047/src/include
-Icoreboot-v2-4047/src/arch/i386/include
-I/usr/lib64/gcc/x86_64-suse-linux/4.3/include --include=settings.h
coreboot-v2-4047/src/mainboard/a-trend/atc-6220/../../../arch/i386/lib/failover.c
-o failover.inc
Invalid option specified: --include=settings.h


Oops.

//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 02:33:53 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 02:33:53 +0200
Subject: [coreboot] build service results for r4047
In-Reply-To: <E1LpWKX-0000zs-CV@ra.coresystems.de>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de>
Message-ID: <49D55971.1090801@gmx.net>

On 03.04.2009 01:28, coreboot information wrote:
> Build Log:
> Compilation of a-trend:atc-6220 has been broken 
> Compilation of a-trend:atc-6240 has been broken 
> Compilation of abit:be6-ii_v2_0 has been broken 
> Compilation of advantech:pcm-5820 has been broken 
> Compilation of amd:rumba has been broken 
> Compilation of asi:mb_5blgp has been broken 
> Compilation of asi:mb_5blmp has been broken 
> Compilation of asus:mew-am has been broken 
> Compilation of asus:mew-vm has been broken 
> Compilation of asus:p2b has been broken 
> Compilation of asus:p2b-ds has been broken 
> Compilation of asus:p2b-f has been broken 
> Compilation of asus:p3b-f has been broken 
> Compilation of axus:tc320 has been broken 
> Compilation of azza:pt-6ibd has been broken 
> Compilation of bcom:winnet100 has been broken 
> Compilation of bcom:winnetp680 has been broken 
> Compilation of biostar:m6tba has been broken 
> Compilation of compaq:deskpro_en_sff_p600 has been broken 
> Compilation of dell:s1850 has been broken 
> Compilation of digitallogic:adl855pc has been broken 
> Compilation of digitallogic:msm586seg has been broken 
> Compilation of eaglelion:5bcm has been broken 
> Compilation of emulation:qemu-x86 has been broken 
> Compilation of gigabyte:ga-6bxc has been broken 
> Compilation of iei:juki-511p has been broken 
> Compilation of iei:nova4899r has been broken 
> Compilation of intel:jarrell has been broken 
> Compilation of intel:mtarvon has been broken 
> Compilation of intel:truxton has been broken 
> Compilation of intel:xe7501devkit has been broken 
> Compilation of jetway:j7f24 has been broken 
> Compilation of lippert:frontrunner has been broken 
> Compilation of msi:ms6119 has been broken 
> Compilation of msi:ms6147 has been broken 
> Compilation of msi:ms6178 has been broken 
> Compilation of nec:powermate2000 has been broken 
> Compilation of olpc:btest has been broken 
> Compilation of olpc:rev_a has been broken 
> Compilation of rca:rm4100 has been broken 
> Compilation of supermicro:x6dai_g has been broken 
> Compilation of supermicro:x6dhe_g has been broken 
> Compilation of supermicro:x6dhe_g2 has been broken 
> Compilation of supermicro:x6dhr_ig has been broken 
> Compilation of supermicro:x6dhr_ig2 has been broken 
> Compilation of technologic:ts5300 has been broken 
> Compilation of televideo:tc7020 has been broken 
> Compilation of thomson:ip1000 has been broken 
> Compilation of tyan:s1846 has been broken 
> Compilation of via:epia has been broken 
> Compilation of via:epia-cn has been broken 
> Compilation of via:epia-m has been broken 
> Compilation of via:pc2500e has been broken
>   

Although the breakage itself is not something to be celebrated, we now
have a list of boards using ROMCC by default. Now if we could convert
them to CAR, we'd win big time.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From corey.osgood at gmail.com  Fri Apr  3 03:41:54 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Thu, 2 Apr 2009 21:41:54 -0400
Subject: [coreboot] build service results for r4047
In-Reply-To: <49D55971.1090801@gmx.net>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de> <49D55971.1090801@gmx.net>
Message-ID: <dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>

On Thu, Apr 2, 2009 at 8:33 PM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> On 03.04.2009 01:28, coreboot information wrote:
> > Build Log:
> > Compilation of a-trend:atc-6220 has been broken
> > Compilation of a-trend:atc-6240 has been broken
> > Compilation of abit:be6-ii_v2_0 has been broken
> > Compilation of advantech:pcm-5820 has been broken
> > Compilation of amd:rumba has been broken
> > Compilation of asi:mb_5blgp has been broken
> > Compilation of asi:mb_5blmp has been broken
> > Compilation of asus:mew-am has been broken
> > Compilation of asus:mew-vm has been broken
> > Compilation of asus:p2b has been broken
> > Compilation of asus:p2b-ds has been broken
> > Compilation of asus:p2b-f has been broken
> > Compilation of asus:p3b-f has been broken
> > Compilation of axus:tc320 has been broken
> > Compilation of azza:pt-6ibd has been broken
> > Compilation of bcom:winnet100 has been broken
> > Compilation of bcom:winnetp680 has been broken
> > Compilation of biostar:m6tba has been broken
> > Compilation of compaq:deskpro_en_sff_p600 has been broken
> > Compilation of dell:s1850 has been broken
> > Compilation of digitallogic:adl855pc has been broken
> > Compilation of digitallogic:msm586seg has been broken
> > Compilation of eaglelion:5bcm has been broken
> > Compilation of emulation:qemu-x86 has been broken
> > Compilation of gigabyte:ga-6bxc has been broken
> > Compilation of iei:juki-511p has been broken
> > Compilation of iei:nova4899r has been broken
> > Compilation of intel:jarrell has been broken
> > Compilation of intel:mtarvon has been broken
> > Compilation of intel:truxton has been broken
> > Compilation of intel:xe7501devkit has been broken
> > Compilation of jetway:j7f24 has been broken
> > Compilation of lippert:frontrunner has been broken
> > Compilation of msi:ms6119 has been broken
> > Compilation of msi:ms6147 has been broken
> > Compilation of msi:ms6178 has been broken
> > Compilation of nec:powermate2000 has been broken
> > Compilation of olpc:btest has been broken
> > Compilation of olpc:rev_a has been broken
> > Compilation of rca:rm4100 has been broken
> > Compilation of supermicro:x6dai_g has been broken
> > Compilation of supermicro:x6dhe_g has been broken
> > Compilation of supermicro:x6dhe_g2 has been broken
> > Compilation of supermicro:x6dhr_ig has been broken
> > Compilation of supermicro:x6dhr_ig2 has been broken
> > Compilation of technologic:ts5300 has been broken
> > Compilation of televideo:tc7020 has been broken
> > Compilation of thomson:ip1000 has been broken
> > Compilation of tyan:s1846 has been broken
> > Compilation of via:epia has been broken
> > Compilation of via:epia-cn has been broken
> > Compilation of via:epia-m has been broken
> > Compilation of via:pc2500e has been broken
> >
>
> Although the breakage itself is not something to be celebrated, we now
> have a list of boards using ROMCC by default. Now if we could convert
> them to CAR, we'd win big time.


As good as that would be, we know the ROMCC code works, and we don't know if
we can find people with boards to test new ports for all of them. That, and
CAR is so much easier to work with in v3, so let's concentrate our efforts
there. My 2 cents, at least.

-Corey
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 03:59:00 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 03:59:00 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
Message-ID: <49D56D64.3000303@gmx.net>

There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping dead
code around. Kill it.

This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
tyan/s2850.

Abuild build log with and without the patch is completely identical.

If this patch is OK, I'll create more of the same type, hopefully making
ROMCC dependencies a bit more clear for v2.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/Config.lb	(revision 4047)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/Config.lb	(working copy)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/Config.lb	(revision 4047)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/Config.lb	(working copy)
@@ -35,7 +35,6 @@
 
 arch i386 end 
 
-
 ##
 ## Build the objects we have code for in this directory.
 ##
@@ -44,8 +43,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 object reset.o
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -63,39 +60,13 @@
 end
 
 end
-else
 
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -103,7 +74,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/x86/car/cache_as_ram.lds
         end
-end
 
 
 ##
@@ -117,24 +87,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/x86/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -142,36 +104,18 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-# ROMCC
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##


-- 
http://www.hailfinger.org/

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From rminnich at gmail.com  Fri Apr  3 04:02:29 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 2 Apr 2009 19:02:29 -0700
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D56D64.3000303@gmx.net>
References: <49D56D64.3000303@gmx.net>
Message-ID: <13426df10904021902g7db0c5d7jfa843a35f69fe33a@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 04:16:50 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 04:16:50 +0200
Subject: [coreboot] build service results for r4047
In-Reply-To: <dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de> <49D55971.1090801@gmx.net>
	<dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>
Message-ID: <49D57192.9000409@gmx.net>

On 03.04.2009 03:41, Corey Osgood wrote:
> On Thu, Apr 2, 2009 at 8:33 PM, Carl-Daniel Hailfinger wrote:
>   
>> Although the breakage itself is not something to be celebrated, we now
>> have a list of boards using ROMCC by default. Now if we could convert
>> them to CAR, we'd win big time.
>>     
>
> As good as that would be, we know the ROMCC code works, and we don't know if
> we can find people with boards to test new ports for all of them. That, and
> CAR is so much easier to work with in v3, so let's concentrate our efforts
> there. My 2 cents, at least.
>   

Absolutely agreed about ease of use of v3 CAR.
My hope was to simplify porting to v3 by switching v2 targets to CAR.
But v2 CAR is horribly complicated, so your point about concentrating
efforts on v3 is very valid.
Now if some targets can be converted easily to v2 CAR (less than 30
minutes per board), my idea still might make sense, if only to
differentiate between hard/impossible and easy CAR conversions from the
hardware POV.

And to be honest, I want to test how well Urbez' gcc+xmmstack solution
works out for the hard targets.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Fri Apr  3 04:18:24 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 04:18:24 +0200
Subject: [coreboot] [v2] r4048 - in trunk/coreboot-v2/src/mainboard/tyan:
	s2735 s2850
Message-ID: <mailman.2925.1355071508.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-04-03 04:18:23 +0200 (Fri, 03 Apr 2009)
New Revision: 4048

Modified:
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
Log:
There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping dead
code around. Kill it.

This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
tyan/s2850.

Abuild build log with and without the patch is completely identical.

More patches of the same type can be done, hopefully making
ROMCC dependencies a bit more clear for v2.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb	2009-04-02 23:08:16 UTC (rev 4047)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb	2009-04-03 02:18:23 UTC (rev 4048)
@@ -35,7 +35,6 @@
 
 arch i386 end 
 
-
 ##
 ## Build the objects we have code for in this directory.
 ##
@@ -44,8 +43,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 object reset.o
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -63,39 +60,13 @@
 end
 
 end
-else
 
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -103,7 +74,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/x86/car/cache_as_ram.lds
         end
-end
 
 
 ##
@@ -117,24 +87,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/x86/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -142,36 +104,18 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-# ROMCC
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb	2009-04-02 23:08:16 UTC (rev 4047)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb	2009-04-03 02:18:23 UTC (rev 4048)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 04:19:01 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 04:19:01 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <13426df10904021902g7db0c5d7jfa843a35f69fe33a@mail.gmail.com>
References: <49D56D64.3000303@gmx.net>
	<13426df10904021902g7db0c5d7jfa843a35f69fe33a@mail.gmail.com>
Message-ID: <49D57215.9080204@gmx.net>

On 03.04.2009 04:02, ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>   

Thanks, r4048.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From info at coresystems.de  Fri Apr  3 04:38:31 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 04:38:31 +0200
Subject: [coreboot] build service results for r4048
Message-ID: <E1LpZId-0002Wi-Je@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "hailfinger" checked in revision 4048 to
the coreboot repository. This caused the following 
changes:

Change Log:
There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping dead
code around. Kill it.

This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
tyan/s2850.

Abuild build log with and without the patch is completely identical.

More patches of the same type can be done, hopefully making
ROMCC dependencies a bit more clear for v2.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=rumba&vendor=amd&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:mew-am is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=winnetp680&vendor=bcom&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=s1850&vendor=dell&num=2
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm586seg is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=msm586seg&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=5bcm&vendor=eaglelion&num=2
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of iei:juki-511p is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=juki-511p&vendor=iei&num=2
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=nova4899r&vendor=iei&num=2
Compilation of intel:jarrell is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=xe7501devkit&vendor=intel&num=2
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=j7f24&vendor=jetway&num=2
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=frontrunner&vendor=lippert&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=ms6178&vendor=msi&num=2
Compilation of nec:powermate2000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=powermate2000&vendor=nec&num=2
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=rev_a&vendor=olpc&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=rm4100&vendor=rca&num=2
Compilation of supermicro:x6dai_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=ip1000&vendor=thomson&num=2
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=s1846&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=epia&vendor=via&num=2
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=epia-m&vendor=via&num=2
Compilation of via:pc2500e is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4048&device=pc2500e&vendor=via&num=2


If something broke during this checkin please be a pain 
in hailfinger's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From samuel.verstraete at gmail.com  Fri Apr  3 07:11:22 2009
From: samuel.verstraete at gmail.com (samuel)
Date: Fri, 3 Apr 2009 07:11:22 +0200
Subject: [coreboot] [PATCH] First support for HP DL145 G3
In-Reply-To: <2831fecf0904021400g3bbacf43q2242c410370bd4c0@mail.gmail.com>
References: <49D2224D.8000207@uni-hd.de> <49D24B42.5030705@coresystems.de>
	<57947bf80903311148s442ca349u8743a742b6020dde@mail.gmail.com>
	<49D31404.1070603@uni-hd.de>
	<bc122a250904021012u3edaf80ep92af901c3074a7f1@mail.gmail.com>
	<bc122a250904021138w551598ceq2192e2e97cb756bf@mail.gmail.com>
	<534e5dc20904021154x3a28d59ayb11d72262dff3e76@mail.gmail.com>
	<bc122a250904021243j56b3c91at68137b88d79b745c@mail.gmail.com>
	<bc122a250904021345nfe918efu636855959ae507aa@mail.gmail.com>
	<2831fecf0904021400g3bbacf43q2242c410370bd4c0@mail.gmail.com>
Message-ID: <bc122a250904022211g29303000y4ade4486b635a5da@mail.gmail.com>

On Thu, Apr 2, 2009 at 11:00 PM, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Apr 2, 2009 at 2:45 PM, samuel <samuel.verstraete at gmail.com> wrote:
>> Anyone has any hints on how to get the vga port going?
>
> I don't see it getting initialized. ?I don't see a line where the ROM
> is being run in your log.
>
> Have you tried extracting the VGA BIOS?
>
> Do you have a vga card to try?

I will try that

>
>> and another thing...
>> I'm trying to get filo/grub to autoload my config file i made... i
>> stored it on /dev/sda1 (together with the kernel) but it is not
>> loading that file... it simply goes straight to the prompt. No error
>> nothing...
>>
>> the config i made looks like this:
>> #
>> timeout 10
>> default 0
>> fallback 1
>>
>> title 2.6.28.8-x86_64
>> kernel /dev/sda1/2.6.28.8-x86_64 root=/dev/md1 console=tty0 console=ttyS0,115200
> /dev/sda1 looks wrong here. ?Have you tried hda1 (like your working boot line)?

But shouldn't it at least show the menu? Even if the entry is completely wrong?


>
> Myles
>



From svn at coreboot.org  Fri Apr  3 10:54:52 2009
From: svn at coreboot.org (coreboot)
Date: Fri, 03 Apr 2009 08:54:52 -0000
Subject: [coreboot]  #126: inteltool: error: PCI_FILL_IDENT undeclared
Message-ID: <045.126f34c4ff07df3d865d0ca506da059f@coreboot.org>

#126: inteltool: error: PCI_FILL_IDENT undeclared
---------------------------------+------------------------------------------
   Reporter:  anonymous          |          Owner:  somebody
       Type:  defect             |         Status:  new     
   Priority:  major              |      Milestone:          
  Component:  misc               |        Version:  v2      
   Keywords:                     |   Dependencies:          
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 inteltool from svn revision 4048.
 $ make
 (lot of warnings)
 inteltool.c:210: erreur: ?PCI_FILL_IDENT? undeclared (first use in this
 function)

 What and where are the values of PCI_FILL_IDENT PCI_FILL_BASES
 PCI_FILL_SIZES PCI_FILL_CLASS, please ?

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/126>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Apr  3 11:48:28 2009
From: svn at coreboot.org (coreboot)
Date: Fri, 03 Apr 2009 09:48:28 -0000
Subject: [coreboot] #126: inteltool: error: PCI_FILL_IDENT undeclared
In-Reply-To: <045.126f34c4ff07df3d865d0ca506da059f@coreboot.org>
References: <045.126f34c4ff07df3d865d0ca506da059f@coreboot.org>
Message-ID: <054.bc01a744ed4ec46bbf045d4724d7ea11@coreboot.org>

#126: inteltool: error: PCI_FILL_IDENT undeclared
---------------------------+------------------------------------------------
    Reporter:  anonymous   |         Owner:  somebody         
        Type:  defect      |        Status:  closed           
    Priority:  major       |     Milestone:                   
   Component:  misc        |       Version:  v2               
  Resolution:  worksforme  |      Keywords:                   
Dependencies:              |   Patchstatus:  there is no patch
---------------------------+------------------------------------------------
Changes (by stepan):

  * status:  new => closed
  * resolution:  => worksforme


Comment:

 Did you install pciutils and pciutils-devel? They're required to build
 inteltool.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/126#comment:1>
coreboot <http://www.coreboot.org/>


From stepan at coresystems.de  Fri Apr  3 11:51:20 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 11:51:20 +0200
Subject: [coreboot] build service results for r4047
In-Reply-To: <49D57192.9000409@gmx.net>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de>
	<49D55971.1090801@gmx.net>	<dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>
	<49D57192.9000409@gmx.net>
Message-ID: <49D5DC18.3070207@coresystems.de>

On 03.04.2009 4:16 Uhr, Carl-Daniel Hailfinger wrote:
> And to be honest, I want to test how well Urbez' gcc+xmmstack solution
> works out for the hard targets.
>   

Any idea where to get that one? All I could ever find was a single web
page talking about it.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From stepan at coresystems.de  Fri Apr  3 11:52:42 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 11:52:42 +0200
Subject: [coreboot] [v2] r4048 - in
 trunk/coreboot-v2/src/mainboard/tyan: s2735 s2850
Message-ID: <49D5DC6A.7080106@coresystems.de>

On 03.04.2009 4:18 Uhr, svn at coreboot.org wrote:
> Author: hailfinger
> Date: 2009-04-03 04:18:23 +0200 (Fri, 03 Apr 2009)
> New Revision: 4048
>
> Modified:
>    trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
>    trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
> Log:
> There are more than a dozen targets in the v2 tree which refer to ROMCC
> in their Config.lb but never use it. There's no point in keeping dead
> code around. Kill it.
>
> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
> tyan/s2850.
>
> Abuild build log with and without the patch is completely identical.
>
> More patches of the same type can be done, hopefully making
> ROMCC dependencies a bit more clear for v2.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
>   

Consequently you could also wipe auto.c and potential other romcc
remainders from those boards.

Best regards,
Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 12:27:07 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 12:27:07 +0200
Subject: [coreboot]  xmmstack
In-Reply-To: <49D5DC18.3070207@coresystems.de>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de>
	<49D55971.1090801@gmx.net>	<dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>
	<49D57192.9000409@gmx.net> <49D5DC18.3070207@coresystems.de>
Message-ID: <49D5E47B.3090100@gmx.net>

On 03.04.2009 11:51, Stefan Reinauer wrote:
> On 03.04.2009 4:16 Uhr, Carl-Daniel Hailfinger wrote:
>   
>> And to be honest, I want to test how well Urbez' gcc+xmmstack solution
>> works out for the hard targets.
>>   
>>     
>
> Any idea where to get that one? All I could ever find was a single web
> page talking about it.
>   

Urbez mailed it to me a few weeks ago with the following explanation:
> Remember that in some CPU's you must activate in CR4 the 9 bit, for work
> correctly.
>
>         movl    0x200,%eax #CR4 bit 9 for SSE
>         movl    %eax,%cr4
>
>
> The application is too primitive, but works fine.
> It uses pcre, for easy parse the *.s generated with gcc, in the Code
> of xmmstack.c say's the options that i use for generate the *.s assembly
> code:
>
> gcc -fomit-frame-pointer -fno-stack-protector *.c
>
> if you will you can delete the code for mmx registers, but can be util
> for another person.
>   

It's attached to this mail.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

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From mjt at nysv.org  Fri Apr  3 12:42:57 2009
From: mjt at nysv.org (Markus Törnqvist)
Date: Fri, 3 Apr 2009 13:42:57 +0300
Subject: [coreboot] VIA Epia-MII stuff
In-Reply-To: <dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>
References: <20090402221156.GN638@nysv.org>
	<dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>
Message-ID: <20090403104257.GO638@nysv.org>

On Thu, Apr 02, 2009 at 06:46:47PM -0400, Corey Osgood wrote:
>2009/4/2 Markus T?rnqvist <mjt at nysv.org>
>

>> http://www.coreboot.org/VIA_EPIA-MII

>> The web says:
>> "The configuration as set up by the buildtarget process will create a
>> coreboot
>> file which is exactly 196608 bytes long, which is exactly 64K bytes short
>> of
>> what needs to go into the 256K flash rom."

>> root at coraline:/usr/src/coreboot-v2-4046/targets/via/epia-m/epia-m# ls -l
>> normal/coreboot.rom fallback/coreboot.rom
>> -rw-r--r-- 1 root src 131072 Apr  2 20:46 fallback/coreboot.rom
>> -rw-r--r-- 1 root src 131072 Apr  2 20:46 normal/coreboot.rom

>> Q1: Why is there a mismatch here?
>
>Because with the open source xf86-unichrome and Luc Verhaegan's kernel
>driver, it's now possible for the kernel to initialize a framebuffer console
>and X video without the need for the VGA BIOS, so someone decided to change

xf86-unichrome is about drivers for the mobo's integrated vga, right?

>the default to build a 256k image and remove the commented out line with the
>192k size. I believe the console driver is included with recent kernels, but
>I couldn't tell you the exact version. If you want to use a different
>driver, modify this line:
>
>option ROM_SIZE=256*1024
>
>to be
>
>option ROM_SIZE=192*1024

So this should be safest as I'm hoping to use, at least for starters,
a regular Ubuntu kernel, which might not be the latest one but saves
me the trouble of compiling my own?

>Then, re-run buildtarget, make clean, and make. You should end up with a
>128k fallback image and 64k normal image

So I tried ROM_SIZE=192*1024

Payload: 36804 coreboot: 65536 ROM size: 131072 Left space: 28732

Both images are still 128k ...

>(yes, it's a nasty solution, part
>of the reason for v3), and a 192k image in build directory (the one you ran
>make from), that's the image you should probably use. If you want to
>continue using your current solution, you should probably use the fallback
>coreboot.rom, as there is code that will attempt to boot from the fallback
>image in the event of an error, and if there is no fallback image to boot
>from, nasty things could happen. 

... but the build dir coreboot.rom is 256k, not 192k!

I don't know what happened actually, but not surprisingly, it didn't boot,
was just black and nonresponsive.

Maybe I should do the weird-yet-ugly vga-bios-twice hack then, for now.

>If anything's not clear, let me know, I'm
>terrible at explaining things.

Heh, and this should end up on the wiki in some non-confusing format
too so the next guy won't have to ask the same questions :)

Thanks!

-- 
mjt




From peter at stuge.se  Fri Apr  3 12:50:00 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 12:50:00 +0200
Subject: [coreboot] VIA Epia-MII stuff
In-Reply-To: <20090403104257.GO638@nysv.org>
References: <20090402221156.GN638@nysv.org>
	<dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>
	<20090403104257.GO638@nysv.org>
Message-ID: <20090403105000.18859.qmail@stuge.se>

Markus T?rnqvist wrote:
> So I tried ROM_SIZE=192*1024
..
> Heh, and this should end up on the wiki in some non-confusing
> format too so the next guy won't have to ask the same questions :)

The exact way the five or ten different SIZE options in v2 interact
is still a mystery to me after many years of occasional tweaking.
It's horrible.


//Peter



From patrick.georgi at coresystems.de  Fri Apr  3 12:57:29 2009
From: patrick.georgi at coresystems.de (Patrick Georgi)
Date: Fri, 03 Apr 2009 12:57:29 +0200
Subject: [coreboot] VIA Epia-MII stuff
In-Reply-To: <20090403105000.18859.qmail@stuge.se>
References: <20090402221156.GN638@nysv.org>	<dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>	<20090403104257.GO638@nysv.org>
	<20090403105000.18859.qmail@stuge.se>
Message-ID: <49D5EB99.5000005@coresystems.de>

Am 03.04.2009 12:50, schrieb Peter Stuge:
> The exact way the five or ten different SIZE options in v2 interact
> is still a mystery to me after many years of occasional tweaking.
> It's horrible.
>    
A romfs capable target can hide most of the SIZE options from the user. 
That one is easy to do and can be done for every single target.
In another step, after all targets are romfs, it could be fixed properly 
so that only one SIZE option remains: total image size. That one is more 
complex, but worth it in my opinion.

But there's still some small romfs patch pending, that I want to clean 
up and post soonish.
After that, targets could be moved to romfs, and I'll try to post some 
guidelines for that when the infrastructure work is done.


Regards,
Patrick



From Zheng.Bao at amd.com  Fri Apr  3 13:01:07 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Fri, 3 Apr 2009 19:01:07 +0800
Subject: [coreboot] command uuid in grub.conf
In-Reply-To: <61326240904021329u1e7727f6ud518d9d3a56538c7@mail.gmail.com>
References: <DD1CC71B621B004FA76856E5129D6B17028CF088@sbjgexmb1.amd.com>
	<20090402201435.9403.qmail@stuge.se>
	<61326240904021329u1e7727f6ud518d9d3a56538c7@mail.gmail.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B17028CF3FC@sbjgexmb1.amd.com>

base on current FILO, which is a simplified GRUB, the root device
is decided when the parameter of command root is given. Before the
kernel 
or initrd command is executed, it doesnet need to really access device.

If UUID is needed,
the filo should probe all the available devices and find matched UUID. 
It seems to need a big change on current code.

Zheng

________________________________________
From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of
Vikram Hegde
Sent: Friday, April 03, 2009 4:30 AM
To: coreboot at coreboot.org
Subject: Re: [coreboot] command uuid in grub.conf

Hi,

Solaris now uses findroot command (also available only in patched GRUB).
Both findroot and uuid commands were created because the root command
(specifically "hd") is fiendishly difficult to determine from an OS. The
"hd" is the BIOS disk ID which the BIOS can assign as it pleases and
very difficult for the OS to determine what the mapping from BIOS ID to
disk is particularly when you change boot disks.

Vikram
On Thu, Apr 2, 2009 at 1:14 PM, Peter Stuge <peter at stuge.se> wrote:
Bao, Zheng wrote:
> Either current stable version of grub2 or filo doesn't support
> command UUID.
> I am wondering if it is an issue that you guys have already known.
I can confirm that FILO does not support UUID.


> Any plan I don't know?
The issue of UUIDs has not come up before. There's no plan. I think
it would be a useful improvement.


//Peter

--
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot





From peter at stuge.se  Fri Apr  3 13:12:55 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 13:12:55 +0200
Subject: [coreboot] command uuid in grub.conf
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17028CF3FC@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17028CF088@sbjgexmb1.amd.com>
	<20090402201435.9403.qmail@stuge.se>
	<61326240904021329u1e7727f6ud518d9d3a56538c7@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B17028CF3FC@sbjgexmb1.amd.com>
Message-ID: <20090403111255.27275.qmail@stuge.se>

Bao, Zheng wrote:
> If UUID is needed, the filo should probe all the available devices
> and find matched UUID.

That's correct. Good observation!


> It seems to need a big change on current code.

I think it could be relatively simple to scan over all devices, but
another point that has been mentioned in this context is that it will
take some time, because the ATA driver in FILO, while now certainly
better than it used to be, is not very fast.


//Peter



From uwe at hermann-uwe.de  Fri Apr  3 13:22:08 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Apr 2009 13:22:08 +0200
Subject: [coreboot] xmmstack
In-Reply-To: <49D5E47B.3090100@gmx.net>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de> <49D55971.1090801@gmx.net>
	<dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>
	<49D57192.9000409@gmx.net> <49D5DC18.3070207@coresystems.de>
	<49D5E47B.3090100@gmx.net>
Message-ID: <20090403112208.GB25703@greenwood>

On Fri, Apr 03, 2009 at 12:27:07PM +0200, Carl-Daniel Hailfinger wrote:
> /*
>     XMM-STACK: convert the stack to a XMM registers for gcc x86 assembler codes
>     Copyright (C) 2008  Urbez Santana i Roma
> 
>     This program is free software: you can redistribute it and/or modify
>     it under the terms of the GNU General Public License as published by
>     the Free Software Foundation, either version 3 of the License, or
>     (at your option) any later version.

Ouch, GPLv3-or-later. Can you please ask him if he likes to relicense it to
GPLv2-or-later as we can't use it otherwise (at most for inspiration,
but not the code itself). Yes, GPLv2 and GPLv3 are incompatible, which
sucks.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 13:26:56 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 13:26:56 +0200
Subject: [coreboot] xmmstack
In-Reply-To: <20090403112208.GB25703@greenwood>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de> <49D55971.1090801@gmx.net>
	<dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>
	<49D57192.9000409@gmx.net> <49D5DC18.3070207@coresystems.de>
	<49D5E47B.3090100@gmx.net> <20090403112208.GB25703@greenwood>
Message-ID: <49D5F280.9080702@gmx.net>

On 03.04.2009 13:22, Uwe Hermann wrote:
> On Fri, Apr 03, 2009 at 12:27:07PM +0200, Carl-Daniel Hailfinger wrote:
>   
>> /*
>>     XMM-STACK: convert the stack to a XMM registers for gcc x86 assembler codes
>>     Copyright (C) 2008  Urbez Santana i Roma
>>
>>     This program is free software: you can redistribute it and/or modify
>>     it under the terms of the GNU General Public License as published by
>>     the Free Software Foundation, either version 3 of the License, or
>>     (at your option) any later version.
>>     
>
> Ouch, GPLv3-or-later. Can you please ask him if he likes to relicense it to
> GPLv2-or-later as we can't use it otherwise (at most for inspiration,
> but not the code itself). Yes, GPLv2 and GPLv3 are incompatible, which
> sucks.
>   

AFAICS xmmstack is an external tool like gcc. We don't care about the
license of gcc because gcc is not incorporated into the final binary.
Why would xmmstack be different?


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mjt at nysv.org  Fri Apr  3 13:29:20 2009
From: mjt at nysv.org (Markus Törnqvist)
Date: Fri, 3 Apr 2009 14:29:20 +0300
Subject: [coreboot] VIA Epia-MII stuff
In-Reply-To: <20090403105000.18859.qmail@stuge.se>
References: <20090402221156.GN638@nysv.org>
	<dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>
	<20090403104257.GO638@nysv.org>
	<20090403105000.18859.qmail@stuge.se>
Message-ID: <20090403112920.GP638@nysv.org>

On Fri, Apr 03, 2009 at 12:50:00PM +0200, Peter Stuge wrote:
>Markus T?rnqvist wrote:
>> So I tried ROM_SIZE=192*1024
>..
>> Heh, and this should end up on the wiki in some non-confusing
>> format too so the next guy won't have to ask the same questions :)
>
>The exact way the five or ten different SIZE options in v2 interact
>is still a mystery to me after many years of occasional tweaking.
>It's horrible.

I'll try to test v3 when the epia-mii gets some support there :)

-- 
mjt




From stepan at coresystems.de  Fri Apr  3 13:54:49 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 3 Apr 2009 13:54:49 +0200
Subject: [coreboot] VIA Epia-MII stuff
In-Reply-To: <20090403112920.GP638@nysv.org>
References: <20090402221156.GN638@nysv.org>
	<dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>
	<20090403104257.GO638@nysv.org>
	<20090403105000.18859.qmail@stuge.se>
	<20090403112920.GP638@nysv.org>
Message-ID: <DBA7397B-4E19-414D-9857-27E03663D0F6@coresystems.de>



On 03.04.2009, at 13:29,  wrote:

> On Fri, Apr 03, 2009 at 12:50:00PM +0200, Peter Stuge wrote:
>> Markus T?rnqvist wrote:
>>> So I tried ROM_SIZE=192*1024
>> ..
>>> Heh, and this should end up on the wiki in some non-confusing
>>> format too so the next guy won't have to ask the same questions :)
>>
>> The exact way the five or ten different SIZE options in v2 interact
>> is still a mystery to me after many years of occasional tweaking.
>> It's horrible.
>
> I'll try to test v3 when the epia-mii gets some support there :)
>
> --  
> mjt
>

It's unlikely to ever see that happen.. The c3, unlike the c7, is said  
to be incapable of Cache As Ram... That's the reason v3 looks so much  
simpler, it will never support CPUs without CAR capability..

Stefan


>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot



From patrick at georgi-clan.de  Fri Apr  3 14:04:20 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 03 Apr 2009 14:04:20 +0200
Subject: [coreboot] [PATCH]romfs final patch
Message-ID: <49D5FB44.10708@georgi-clan.de>

Hi,

the attached patch is the last infrastructure change necessary for romfs.
Everything else to make a target romfs aware happens in the targets.

What the patch does:
1. missing romfs.h include
2. special handling while creating coreboot.rom
While the romfs code path in the makefile doesn't actually use the file, 
it's possible that the build of coreboot.rom fails in a romfs setup, 
because the individual buildrom image is too small to host both coreboot 
and payloads (as the payloads aren't supposed to be there). Thus, a 
special case to replace the payload with /dev/null in case of a romfs build.
There would be cleaner ways, but they're not easily encoded in the 
Config.lb format.
3. config.g is changed to create rules for a romfs build

Targets should still build (they do for me)

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Regards,
Patrick
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: romfs-final.diff
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090403/bdb4252c/attachment.ksh>

From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 14:18:40 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 14:18:40 +0200
Subject: [coreboot] VIA Epia-MII stuff
In-Reply-To: <DBA7397B-4E19-414D-9857-27E03663D0F6@coresystems.de>
References: <20090402221156.GN638@nysv.org>	<dd3c80060904021546u5fd3efd5scad570509062bae4@mail.gmail.com>	<20090403104257.GO638@nysv.org>	<20090403105000.18859.qmail@stuge.se>	<20090403112920.GP638@nysv.org>
	<DBA7397B-4E19-414D-9857-27E03663D0F6@coresystems.de>
Message-ID: <49D5FEA0.3020809@gmx.net>

On 03.04.2009 13:54, Stefan Reinauer wrote:
>
>
> On 03.04.2009, at 13:29,  wrote:
>
>> On Fri, Apr 03, 2009 at 12:50:00PM +0200, Peter Stuge wrote:
>>> Markus T?rnqvist wrote:
>>>> So I tried ROM_SIZE=192*1024
>>> ..
>>>> Heh, and this should end up on the wiki in some non-confusing
>>>> format too so the next guy won't have to ask the same questions :)
>>>
>>> The exact way the five or ten different SIZE options in v2 interact
>>> is still a mystery to me after many years of occasional tweaking.
>>> It's horrible.
>>
>> I'll try to test v3 when the epia-mii gets some support there :)
>
> It's unlikely to ever see that happen.. The c3, unlike the c7, is said
> to be incapable of Cache As Ram... That's the reason v3 looks so much
> simpler, it will never support CPUs without CAR capability..

I still hope CAR can be made to work on the C3. IIRC C3 CAR was "just"
totally unreliable and not broken. To be honest, with our current CAR
code, it is very easy to break it by accident (even in v3) and I suspect
that happened when testing C3 CAR. And even if we get CAR to work
reliably on the C3, it will be extremely _slow_ (maybe even slower than
with ROMCC) until RAM is turned on.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Fri Apr  3 14:23:11 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 14:23:11 +0200
Subject: [coreboot] [PATCH]romfs final patch
In-Reply-To: <49D5FB44.10708@georgi-clan.de>
References: <49D5FB44.10708@georgi-clan.de>
Message-ID: <49D5FFAF.4090906@coresystems.de>

On 03.04.2009 14:04 Uhr, Patrick Georgi wrote:
> Hi,
>
> the attached patch is the last infrastructure change necessary for romfs.
> Everything else to make a target romfs aware happens in the targets.
>
> What the patch does:
> 1. missing romfs.h include
> 2. special handling while creating coreboot.rom
> While the romfs code path in the makefile doesn't actually use the
> file, it's possible that the build of coreboot.rom fails in a romfs
> setup, because the individual buildrom image is too small to host both
> coreboot and payloads (as the payloads aren't supposed to be there).
> Thus, a special case to replace the payload with /dev/null in case of
> a romfs build.
> There would be cleaner ways, but they're not easily encoded in the
> Config.lb format.
> 3. config.g is changed to create rules for a romfs build
>
> Targets should still build (they do for me)
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>
> Regards,
> Patrick
Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 14:39:28 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 14:39:28 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D56D64.3000303@gmx.net>
References: <49D56D64.3000303@gmx.net>
Message-ID: <49D60380.4040207@gmx.net>

On 03.04.2009 03:59, Carl-Daniel Hailfinger wrote:
> There are more than a dozen targets in the v2 tree which refer to ROMCC
> in their Config.lb but never use it. There's no point in keeping dead
> code around. Kill it.
>
> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
> tyan/s2850.
>
> Abuild build log with and without the patch is completely identical.
>
> If this patch is OK, I'll create more of the same type, hopefully making
> ROMCC dependencies a bit more clear for v2.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

Next step. Kill auto.c and failover.c and clean up Config.lb for
tyan/s2735
tyan/s2850
tyan/s2875
tyan/s2880
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895

Abuild log is completely identical with and without the patch.


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/failover.c	(working copy)
@@ -1,89 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else   
-        unsigned nodeid;
-#endif          
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-#if CONFIG_LOGICAL_CPUS==1
-        id = get_node_core_id_x();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(id.nodeid)) {
-#else
-        nodeid = lapicid();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto cpu_reset;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- cpu_reset:
-#if 0
-	asm volatile ("jmp __cpu_reset"
-		: /* outputs */ 
-		: "a"(bist) /* inputs */
-		: /* clobbers */
-		);
-#endif
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2850/auto.c	(working copy)
@@ -1,203 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-#define REV_B_RESET 0
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (0 << 0), SMBUS_IO_BASE + 0xc0 + 16);	//REVC_MEMRST_EN=0
-	} else {
-		outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 16);	//REVC_MEMRST_EN=1
-	}
-	outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
-	     (0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 17);	//REVB_MEMRST_L=1
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#endif
-
-static void main(unsigned long bist)
-{
-	/*
-	 * GPIO28 of 8111 will control H0_MEMRESET_L
-	 * GPIO29 of 8111 will control H1_MEMRESET_L
-	 */
-	static const struct mem_controller cpu[] = {
-		{
-		 .node_id = 0,
-		 .f0 = PCI_DEV(0, 0x18, 0),
-		 .f1 = PCI_DEV(0, 0x18, 1),
-		 .f2 = PCI_DEV(0, 0x18, 2),
-		 .f3 = PCI_DEV(0, 0x18, 3),
-		 .channel0 = {(0xa << 3) | 0, (0xa << 3) | 2, 0, 0},
-		 .channel1 = {(0xa << 3) | 1, (0xa << 3) | 3, 0, 0},
-		 },
-	};
-
-	int needs_reset;
-
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-
-        if (bist == 0) {
-                /* Skip this if there was a built in self test failure */
-                amd_early_mtrr_init();
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-#endif
-
-                enable_lapic();
-                init_timer();
-
-#if CONFIG_LOGICAL_CPUS==1
-                id = get_node_core_id_x();
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-                                asm volatile ("jmp __cpu_reset");
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                nodeid = lapicid();
-                if (cpu_init_detected(nodeid)) {
-                        asm volatile ("jmp __cpu_reset");
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-                        stop_this_cpu(); 
-                }
-        }
-                        
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-        report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
-        start_other_cores();
-#endif
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/failover.c	(working copy)
@@ -1,47 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/intel/i82801er/cmos_failover.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else  {
-
-		check_cmos_failed();		
-
-		if (do_normal_boot()) {
-			goto normal_image;
-		}
-		else {
-			goto fallback_image;
-		}
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
-#if 0
- cpu_reset:
-	asm volatile ("jmp __cpu_reset"
-		: /* outputs */ 
-		: "a"(bist) /* inputs */
-		: /* clobbers */
-		);
-#endif
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2735/auto.c	(working copy)
@@ -1,145 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-
-#include "arch/i386/lib/console.c"
-
-#include "ram/ramtest.c"
-#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/e7501/raminit.h"
-#if 0
-#include "cpu/intel/model_f2x/apic_timer.c"
-#include "lib/delay.c"
-#endif
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-        outb(0x0e, 0x0cf9);
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-
-#include "northbridge/intel/e7501/raminit.c"
-#include "northbridge/intel/e7501/reset_test.c"
-#include "sdram/generic_sdram.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller memctrl[] = {
-		{
-			.d0 = PCI_DEV(0, 0, 0),
-			.d0f1 = PCI_DEV(0, 0, 1),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
-			.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
-		},
-	};
-
-        if (bist == 0) {
-                /* Skip this if there was a built in self test failure */
-                early_mtrr_init();
-                enable_lapic();
-//                init_timer();
-
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-
-        /* Halt if there was a built in self test failure */
-//	report_bist_failure(bist);
-
-//        setup_default_resource_map();
-#if 0
-	print_pci_devices();
-#endif
-	if(!bios_reset_detected()) {
-        	enable_smbus();
-#if 0
-    		dump_spd_registers(&memctrl[0]);
-//        	dump_smbus_registers();
-#endif
-
-		memreset_setup();
-		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-	} 
-#if 0
-	else {
-		        /* clear memory 1meg */
-        __asm__ volatile(
-                "1: \n\t"
-                "movl %0, %%fs:(%1)\n\t"
-                "addl $4,%1\n\t"
-                "subl $4,%2\n\t"
-                "jnz 1b\n\t"
-                :
-                : "a" (0), "D" (0), "c" (1024*1024)
-                ); 
-	
-	}
-#endif
-
-#if 0
-	dump_pci_devices();
-#endif
-#if 1
-	dump_pci_device(PCI_DEV(0, 0, 0));
-#endif
-
-#if 0
-	msr_t msr;
-	msr = rdmsr(TOP_MEM2);
-	print_debug("TOP_MEM2: ");
-	print_debug_hex32(msr.hi);
-	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
-#endif
-
-#if 0
-	ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#endif
-
-#if 0
-	// Check 16MB of memory @ 0
-	ram_check(0x00000000, 0x01000000);
-	// Check 16MB of memory @ 2GB 
-//	ram_check(0x80000000, 0x81000000);
-#endif
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/Config.lb	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/Config.lb	(working copy)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/failover.c	(working copy)
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2880/auto.c	(working copy)
@@ -1,173 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-#include "northbridge/amd/amdk8/resourcemap.c" 
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#endif
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, 0, 0, 0 },
-			.channel1 = { (0xa<<3)|5, 0, 0, 0 },
-		},
-#endif
-	};
-        int needs_reset;
-
-        if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-        }
-                        
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_default_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/Config.lb	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/Config.lb	(working copy)
@@ -44,7 +44,6 @@
 object get_bus_conf.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
 
 if CONFIG_USE_INIT
 
@@ -63,33 +62,7 @@
 end
 
 end
-else
-
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/failover.c	(working copy)
@@ -1,69 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2881/auto.c	(working copy)
@@ -1,178 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-        int needs_reset;
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-
-        if (bist == 0) {
-                k8_init_and_stop_secondaries();
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-//        report_bist_failure(bist);
-
-        setup_s2881_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-        // automatically set that for you, but you might meet tight space
-        needs_reset |= ht_setup_chains_x();
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-	enable_smbus();
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/failover.c	(working copy)
@@ -1,96 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0) | (1<<1);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if 1
-        dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
-        dword |= (1<<16);  
-        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
-
-#endif
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected(nodeid)) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/auto.c	(working copy)
@@ -1,151 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-#define K8_HT_FREQ_1G_SUPPORT 0
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-#if 1
-	/* link reset */
-	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU	1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-#if CONFIG_LOGICAL_CPUS==1
-	struct node_core_id id;
-#else
-	unsigned nodeid;
-#endif
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_s2891_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-	needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/Config.lb	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/Config.lb	(working copy)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/failover.c	(working copy)
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2882/auto.c	(working copy)
@@ -1,182 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-#define REV_B_RESET 0
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	/*
-	 * GPIO28 of 8111 will control H0_MEMRESET_L
-	 * GPIO29 of 8111 will control H1_MEMRESET_L
-	 */
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-        
-	int needs_reset;
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-
-        if (bist == 0) {
-        	k8_init_and_stop_secondaries();
-	}
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-
-        /* Halt if there was a built in self test failure */
-//        report_bist_failure(bist);
-
-        setup_default_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-        needs_reset |= ht_setup_chains_x();
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }	
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/failover.c	(working copy)
@@ -1,90 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/auto.c	(working copy)
@@ -1,153 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-#define K8_HT_FREQ_1G_SUPPORT 1
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-#if 1
-	/* link reset */
-	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU	1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-//set GPIO to input mode
-#define CK804_MB_SETUP \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
-
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-//	report_bist_failure(bist);
-
-	setup_s2892_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-	needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/Config.lb	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/Config.lb	(working copy)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-  
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/failover.c	(working copy)
@@ -1,69 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2875/auto.c	(working copy)
@@ -1,173 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
- 
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-        int needs_reset;
-
-        if (bist == 0) {
-		k8_init_and_stop_secondaries();
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_default_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-
-	enable_smbus();
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/Config.lb	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/Config.lb	(working copy)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-  
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/failover.c	(working copy)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-	/* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-	/* Is this a cpu only reset? */
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2885/auto.c	(working copy)
@@ -1,186 +0,0 @@
-#define ASSEMBLY 1
- 
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue;
-                }
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {
-                        return (config_map >> 16) & 0xff;
-                }
-        }
-        return 0;
-}
-
-static void hard_reset(void)
-{
-	device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-	set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else                   
-        #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c" 
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-static void main(unsigned long bist)
-{
-        static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-                        .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-                },
-#endif
-#if SECOND_CPU
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-                        .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-                },
-#endif
-        };
-
-        int needs_reset;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_s2885_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-
-	// automatically set that for you, but you might meet tight space
-        needs_reset |= ht_setup_chains_x();
-
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-
-	enable_smbus();
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/failover.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/failover.c	(working copy)
@@ -1,108 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-
-#include <device/pnp_def.h>  
-
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);  
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<29)|(1<<0);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if  1
-        lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-
-	value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
-	value &= 0xbf;
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-#endif
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/auto.c	(revision 4048)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/auto.c	(working copy)
@@ -1,178 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-//#define K8_HT_FREQ_1G_SUPPORT 1
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/model_fxx/model_fxx_msr.h"
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-#if 1
-	/* link reset */
-	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-	
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void sio_gpio_setup(void){
-
-	unsigned value;
-
-//	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
-	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU	1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 2
-#define CK804B_BUSN 0x80
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-//set GPIO to input mode
-#define CK804_MB_SETUP \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-
-	lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	sio_gpio_setup();
-
-	setup_s2895_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-	needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}


-- 
http://www.hailfinger.org/
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From patrick at georgi-clan.de  Fri Apr  3 14:51:06 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 03 Apr 2009 14:51:06 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D60380.4040207@gmx.net>
References: <49D56D64.3000303@gmx.net> <49D60380.4040207@gmx.net>
Message-ID: <49D6063A.5090108@georgi-clan.de>

Am 03.04.2009 14:39, schrieb Carl-Daniel Hailfinger:
> Next step. Kill auto.c and failover.c and clean up Config.lb for
> tyan/s2735
> tyan/s2850
> tyan/s2875
> tyan/s2880
> tyan/s2881
> tyan/s2882
> tyan/s2885
> tyan/s2891
> tyan/s2892
> tyan/s2895
>
> Abuild log is completely identical with and without the patch.
>
>
> Signed-off-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006 at gmx.net>
>    
Yay!
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



From svn at coreboot.org  Fri Apr  3 14:52:43 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 14:52:43 +0200
Subject: [coreboot] [v2] r4049 - in trunk/coreboot-v2: src/arch/i386
	src/boot util/newconfig
Message-ID: <mailman.2926.1355071509.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-03 14:52:43 +0200 (Fri, 03 Apr 2009)
New Revision: 4049

Modified:
   trunk/coreboot-v2/src/arch/i386/Config.lb
   trunk/coreboot-v2/src/boot/hardwaremain.c
   trunk/coreboot-v2/util/newconfig/config.g
Log:
the attached patch is the last infrastructure change necessary for
romfs.
Everything else to make a target romfs aware happens in the targets.

What the patch does:
1. missing romfs.h include
2. special handling while creating coreboot.rom
While the romfs code path in the makefile doesn't actually use the file,
it's possible that the build of coreboot.rom fails in a romfs setup,
because the individual buildrom image is too small to host both coreboot
and payloads (as the payloads aren't supposed to be there). Thus, a
special case to replace the payload with /dev/null in case of a romfs
build.
There would be cleaner ways, but they're not easily encoded in the
Config.lb format.
3. config.g is changed to create rules for a romfs build

Targets should still build (they do for me)

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Config.lb	2009-04-03 02:18:23 UTC (rev 4048)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb	2009-04-03 12:52:43 UTC (rev 4049)
@@ -79,8 +79,8 @@
 	end
 else
 	makerule coreboot.rom 
-		depends	"coreboot.strip buildrom $(PAYLOAD-1)" 
-		action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
+		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
+		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_ROMFS) -eq 1 ]; then PAYLOAD=/dev/null; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
 	end
 end
 

Modified: trunk/coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- trunk/coreboot-v2/src/boot/hardwaremain.c	2009-04-03 02:18:23 UTC (rev 4048)
+++ trunk/coreboot-v2/src/boot/hardwaremain.c	2009-04-03 12:52:43 UTC (rev 4049)
@@ -36,6 +36,7 @@
 #include <part/hard_reset.h>
 #include <part/init_timer.h>
 #include <boot/elf.h>
+#include <romfs.h>
 
 /**
  * @brief Main function of the DRAM part of coreboot.

Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2009-04-03 02:18:23 UTC (rev 4048)
+++ trunk/coreboot-v2/util/newconfig/config.g	2009-04-03 12:52:43 UTC (rev 4049)
@@ -22,7 +22,9 @@
 global_exported_options = []
 romimages = {}
 buildroms = []
+rommapping = {}
 curimage = 0
+bootblocksize = 0
 alloptions = 0 # override uses at top level
 
 local_path = re.compile(r'^\.')
@@ -277,8 +279,11 @@
 		self.arch = arch
 
 	def setpayload(self, payload):
+		global rommapping
 		self.payload = payload
 
+		rommapping[self.name] = payload
+
 	def setinitfile(self, initfile):
 		self.initfile = initfile
 
@@ -1351,7 +1356,10 @@
 
 def endromimage():
 	global curimage
+	global bootblocksize
 	mainboard()
+	imagesize = getoption("ROM_IMAGE_SIZE", curimage)
+	bootblocksize += imagesize
 	print "End ROMIMAGE"
 	curimage = 0
 	#curpart = 0
@@ -2209,16 +2217,22 @@
 
 #
 def writemakefile(path):
+	global rommapping
+	global bootblocksize
 	makefilepath = os.path.join(path, "Makefile")
 	print "Creating", makefilepath
 	file = safe_open(makefilepath, 'w+')
 	writemakefileheader(file, makefilepath)
 
 	# main rule
-	file.write("\nall:")
+	file.write("\nall: romtool")
 	for i in buildroms:
-		file.write(" %s" % i.name)
+		file.write(" %sfs" % i.name)
 	file.write("\n\n")	
+
+	# romtool rules
+	file.write("\nromtool:\n\tcd $(TOP)/util/romtool; make\n")
+
 	file.write("include Makefile.settings\n\n")
 	for i, o in romimages.items():
 		file.write("%s/coreboot.rom:\n" % o.getname())
@@ -2245,9 +2259,26 @@
 		for j in i.roms:
 			file.write(" %s/coreboot.rom " % j)
 		file.write("> %s\n\n" %i.name)
+		# build the bootblock here as well. 
+		file.write("\n")
+		file.write("\t cat ")
+		for j in i.roms:
+			file.write(" %s/coreboot.strip " % j)
+		file.write("> %s.bootblock\n\n" %i.name)
 
+	romsize = getoption("ROM_SIZE", image)
+	# i.name? That can not be right, can it? 
+	file.write("%sfs: %s $(TOP)/util/romtool/romtool\n" %(i.name,i.name));
+	file.write("\trm -f coreboot.romfs\n");
+	file.write("\t$(TOP)/util/romtool/romtool %sfs create %s %s %s.bootblock\n" % (i.name, romsize, bootblocksize, i.name))
+	for i in buildroms:
+		for j in i.roms:
+			#failover is a hack that will go away soon. 
+			if (j != "failover") and (rommapping[j] != "/dev/null"):
+				file.write("\t $(TOP)/util/romtool/romtool %sfs add-payload %s %s/payload\n" % (i.name, rommapping[j], j))
+		file.write("\t $(TOP)/util/romtool/romtool %sfs print\n" % i.name)
 
-	file.write(".PHONY: all clean")
+	file.write(".PHONY: all clean romtool")
 	for i in romimages.keys():
 		file.write(" %s-clean" % i)
 	for i, o in romimages.items():




From stepan at coresystems.de  Fri Apr  3 14:52:41 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 14:52:41 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D60380.4040207@gmx.net>
References: <49D56D64.3000303@gmx.net> <49D60380.4040207@gmx.net>
Message-ID: <49D60699.4080403@coresystems.de>

On 03.04.2009 14:39 Uhr, Carl-Daniel Hailfinger wrote:
> On 03.04.2009 03:59, Carl-Daniel Hailfinger wrote:
>   
>> There are more than a dozen targets in the v2 tree which refer to ROMCC
>> in their Config.lb but never use it. There's no point in keeping dead
>> code around. Kill it.
>>
>> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
>> tyan/s2850.
>>
>> Abuild build log with and without the patch is completely identical.
>>
>> If this patch is OK, I'll create more of the same type, hopefully making
>> ROMCC dependencies a bit more clear for v2.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>   
>>     
>
> Next step. Kill auto.c and failover.c and clean up Config.lb for
> tyan/s2735
> tyan/s2850
> tyan/s2875
> tyan/s2880
> tyan/s2881
> tyan/s2882
> tyan/s2885
> tyan/s2891
> tyan/s2892
> tyan/s2895
>
> Abuild log is completely identical with and without the patch.
>
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
>   
Acked-by: Stefan Reinauer <stepan at coresystems.de>



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From svn at coreboot.org  Fri Apr  3 14:55:55 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 14:55:55 +0200
Subject: [coreboot] [v2] r4050 - in trunk/coreboot-v2/src/mainboard/tyan:
	s2735 s2850 s2875 s2880 s2881 s2882 s2885 s2891 s2892 s2895
Message-ID: <mailman.2927.1355071509.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-03 14:55:55 +0200 (Fri, 03 Apr 2009)
New Revision: 4050

Removed:
   trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2735/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2850/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2875/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2880/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2880/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2881/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2882/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2885/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2891/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2895/failover.c
Modified:
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
Log:
Next step. Kill auto.c and failover.c and clean up Config.lb for
tyan/s2735
tyan/s2850
tyan/s2875
tyan/s2880
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895

Abuild log is completely identical with and without the patch.


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,145 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-
-#include "arch/i386/lib/console.c"
-
-#include "ram/ramtest.c"
-#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/e7501/raminit.h"
-#if 0
-#include "cpu/intel/model_f2x/apic_timer.c"
-#include "lib/delay.c"
-#endif
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-        outb(0x0e, 0x0cf9);
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-
-#include "northbridge/intel/e7501/raminit.c"
-#include "northbridge/intel/e7501/reset_test.c"
-#include "sdram/generic_sdram.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller memctrl[] = {
-		{
-			.d0 = PCI_DEV(0, 0, 0),
-			.d0f1 = PCI_DEV(0, 0, 1),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
-			.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
-		},
-	};
-
-        if (bist == 0) {
-                /* Skip this if there was a built in self test failure */
-                early_mtrr_init();
-                enable_lapic();
-//                init_timer();
-
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-
-        /* Halt if there was a built in self test failure */
-//	report_bist_failure(bist);
-
-//        setup_default_resource_map();
-#if 0
-	print_pci_devices();
-#endif
-	if(!bios_reset_detected()) {
-        	enable_smbus();
-#if 0
-    		dump_spd_registers(&memctrl[0]);
-//        	dump_smbus_registers();
-#endif
-
-		memreset_setup();
-		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-	} 
-#if 0
-	else {
-		        /* clear memory 1meg */
-        __asm__ volatile(
-                "1: \n\t"
-                "movl %0, %%fs:(%1)\n\t"
-                "addl $4,%1\n\t"
-                "subl $4,%2\n\t"
-                "jnz 1b\n\t"
-                :
-                : "a" (0), "D" (0), "c" (1024*1024)
-                ); 
-	
-	}
-#endif
-
-#if 0
-	dump_pci_devices();
-#endif
-#if 1
-	dump_pci_device(PCI_DEV(0, 0, 0));
-#endif
-
-#if 0
-	msr_t msr;
-	msr = rdmsr(TOP_MEM2);
-	print_debug("TOP_MEM2: ");
-	print_debug_hex32(msr.hi);
-	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
-#endif
-
-#if 0
-	ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#endif
-
-#if 0
-	// Check 16MB of memory @ 0
-	ram_check(0x00000000, 0x01000000);
-	// Check 16MB of memory @ 2GB 
-//	ram_check(0x80000000, 0x81000000);
-#endif
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2735/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,47 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/intel/i82801er/cmos_failover.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else  {
-
-		check_cmos_failed();		
-
-		if (do_normal_boot()) {
-			goto normal_image;
-		}
-		else {
-			goto fallback_image;
-		}
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
-#if 0
- cpu_reset:
-	asm volatile ("jmp __cpu_reset"
-		: /* outputs */ 
-		: "a"(bist) /* inputs */
-		: /* clobbers */
-		);
-#endif
- fallback_image:
-	return bist;
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,203 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-#define REV_B_RESET 0
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (0 << 0), SMBUS_IO_BASE + 0xc0 + 16);	//REVC_MEMRST_EN=0
-	} else {
-		outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 16);	//REVC_MEMRST_EN=1
-	}
-	outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
-	     (0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 17);	//REVB_MEMRST_L=1
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#endif
-
-static void main(unsigned long bist)
-{
-	/*
-	 * GPIO28 of 8111 will control H0_MEMRESET_L
-	 * GPIO29 of 8111 will control H1_MEMRESET_L
-	 */
-	static const struct mem_controller cpu[] = {
-		{
-		 .node_id = 0,
-		 .f0 = PCI_DEV(0, 0x18, 0),
-		 .f1 = PCI_DEV(0, 0x18, 1),
-		 .f2 = PCI_DEV(0, 0x18, 2),
-		 .f3 = PCI_DEV(0, 0x18, 3),
-		 .channel0 = {(0xa << 3) | 0, (0xa << 3) | 2, 0, 0},
-		 .channel1 = {(0xa << 3) | 1, (0xa << 3) | 3, 0, 0},
-		 },
-	};
-
-	int needs_reset;
-
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-
-        if (bist == 0) {
-                /* Skip this if there was a built in self test failure */
-                amd_early_mtrr_init();
-
-#if CONFIG_LOGICAL_CPUS==1
-                set_apicid_cpuid_lo();
-#endif
-
-                enable_lapic();
-                init_timer();
-
-#if CONFIG_LOGICAL_CPUS==1
-                id = get_node_core_id_x();
-                if(id.coreid == 0) {
-                        if (cpu_init_detected(id.nodeid)) {
-                                asm volatile ("jmp __cpu_reset");
-                        }
-                        distinguish_cpu_resets(id.nodeid);
-                }
-#else
-                nodeid = lapicid();
-                if (cpu_init_detected(nodeid)) {
-                        asm volatile ("jmp __cpu_reset");
-                }
-                distinguish_cpu_resets(nodeid);
-#endif
-
-                if (!boot_cpu()
-#if CONFIG_LOGICAL_CPUS==1 
-                        || (id.coreid != 0)
-#endif
-                ) {
-                        stop_this_cpu(); 
-                }
-        }
-                        
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-        report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
-        start_other_cores();
-#endif
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2850/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,89 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else   
-        unsigned nodeid;
-#endif          
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-#if CONFIG_LOGICAL_CPUS==1
-        id = get_node_core_id_x();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(id.nodeid)) {
-#else
-        nodeid = lapicid();
-        /* Is this a cpu only reset? */
-        if (cpu_init_detected(nodeid)) {
-#endif
-
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto cpu_reset;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- cpu_reset:
-#if 0
-	asm volatile ("jmp __cpu_reset"
-		: /* outputs */ 
-		: "a"(bist) /* inputs */
-		: /* clobbers */
-		);
-#endif
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb	2009-04-03 12:55:55 UTC (rev 4050)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-  
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,173 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
- 
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-        int needs_reset;
-
-        if (bist == 0) {
-		k8_init_and_stop_secondaries();
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_default_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-
-	enable_smbus();
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2875/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,69 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb	2009-04-03 12:55:55 UTC (rev 4050)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2880/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,173 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-#include "northbridge/amd/amdk8/resourcemap.c" 
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#include "cpu/amd/dualcore/dualcore.c"
-#endif
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, 0, 0, 0 },
-			.channel1 = { (0xa<<3)|5, 0, 0, 0 },
-		},
-#endif
-	};
-        int needs_reset;
-
-        if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-        }
-                        
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_default_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2880/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb	2009-04-03 12:55:55 UTC (rev 4050)
@@ -44,7 +44,6 @@
 object get_bus_conf.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
 
 if CONFIG_USE_INIT
 
@@ -63,33 +62,7 @@
 end
 
 end
-else
-
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,178 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-        int needs_reset;
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-
-        if (bist == 0) {
-                k8_init_and_stop_secondaries();
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-//        report_bist_failure(bist);
-
-        setup_s2881_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-        // automatically set that for you, but you might meet tight space
-        needs_reset |= ht_setup_chains_x();
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-	enable_smbus();
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2881/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,69 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb	2009-04-03 12:55:55 UTC (rev 4050)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,182 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-#define REV_B_RESET 0
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	/*
-	 * GPIO28 of 8111 will control H0_MEMRESET_L
-	 * GPIO29 of 8111 will control H1_MEMRESET_L
-	 */
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-        
-	int needs_reset;
-#if CONFIG_LOGICAL_CPUS==1
-        struct node_core_id id;
-#else
-        unsigned nodeid;
-#endif
-
-        if (bist == 0) {
-        	k8_init_and_stop_secondaries();
-	}
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-
-        /* Halt if there was a built in self test failure */
-//        report_bist_failure(bist);
-
-        setup_default_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-        needs_reset |= ht_setup_chains_x();
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }	
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2882/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb	2009-04-03 12:55:55 UTC (rev 4050)
@@ -45,8 +45,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -64,32 +62,7 @@
 end
 
 end
-else
-  
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -99,7 +72,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,7 +79,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -145,13 +108,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -160,29 +118,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,186 +0,0 @@
-#define ASSEMBLY 1
- 
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue;
-                }
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {
-                        return (config_map >> 16) & 0xff;
-                }
-        }
-        return 0;
-}
-
-static void hard_reset(void)
-{
-	device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-	set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else                   
-        #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c" 
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-static void main(unsigned long bist)
-{
-        static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-                        .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-                },
-#endif
-#if SECOND_CPU
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-                        .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-                },
-#endif
-        };
-
-        int needs_reset;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_s2885_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-
-	// automatically set that for you, but you might meet tight space
-        needs_reset |= ht_setup_chains_x();
-
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-
-	enable_smbus();
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2885/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-	/* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-	/* Is this a cpu only reset? */
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,151 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-#define K8_HT_FREQ_1G_SUPPORT 0
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-#if 1
-	/* link reset */
-	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU	1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-#if CONFIG_LOGICAL_CPUS==1
-	struct node_core_id id;
-#else
-	unsigned nodeid;
-#endif
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_s2891_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-	needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2891/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,96 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0) | (1<<1);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if 1
-        dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
-        dword |= (1<<16);  
-        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
-
-#endif
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected(nodeid)) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,153 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-#define K8_HT_FREQ_1G_SUPPORT 1
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-#if 1
-	/* link reset */
-	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU	1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-//set GPIO to input mode
-#define CK804_MB_SETUP \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
-
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-//	report_bist_failure(bist);
-
-	setup_s2892_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-	needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2892/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,90 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<0);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/auto.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,178 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-//#define K8_HT_FREQ_1G_SUPPORT 1
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/model_fxx/model_fxx_msr.h"
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* full reset */
-	outb(0x0a, 0x0cf9);
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-#if 1
-	/* link reset */
-	outb(0x02, 0x0cf9);
-	outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-	
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void sio_gpio_setup(void){
-
-	unsigned value;
-
-//	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
-	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU	1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 2
-#define CK804B_BUSN 0x80
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-//set GPIO to input mode
-#define CK804_MB_SETUP \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/	\
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-
-	lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	sio_gpio_setup();
-
-	setup_s2895_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-	needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Deleted: trunk/coreboot-v2/src/mainboard/tyan/s2895/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/failover.c	2009-04-03 12:52:43 UTC (rev 4049)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/failover.c	2009-04-03 12:55:55 UTC (rev 4050)
@@ -1,108 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-
-#include <device/pnp_def.h>  
-
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);  
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<29)|(1<<0);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if  1
-        lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-
-	value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
-	value &= 0xbf;
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-#endif
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}




From info at coresystems.de  Fri Apr  3 15:13:08 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 15:13:08 +0200
Subject: [coreboot] build service results for r4049
Message-ID: <E1LpjCm-0001MW-8z@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4049 to
the coreboot repository. This caused the following 
changes:

Change Log:
the attached patch is the last infrastructure change necessary for
romfs.
Everything else to make a target romfs aware happens in the targets.

What the patch does:
1. missing romfs.h include
2. special handling while creating coreboot.rom
While the romfs code path in the makefile doesn't actually use the file,
it's possible that the build of coreboot.rom fails in a romfs setup,
because the individual buildrom image is too small to host both coreboot
and payloads (as the payloads aren't supposed to be there). Thus, a
special case to replace the payload with /dev/null in case of a romfs
build.
There would be cleaner ways, but they're not easily encoded in the
Config.lb format.
3. config.g is changed to create rules for a romfs build

Targets should still build (they do for me)

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=db800&vendor=amd&num=2
Compilation of amd:norwich has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=norwich&vendor=amd&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=rumba&vendor=amd&num=2
Compilation of artecgroup:dbe61 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:mew-am is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=winnetp680&vendor=bcom&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=s1850&vendor=dell&num=2
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm586seg is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=msm586seg&vendor=digitallogic&num=2
Compilation of digitallogic:msm800sev has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=5bcm&vendor=eaglelion&num=2
Configuration of embeddedplanet:ep405pc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of iei:juki-511p is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=juki-511p&vendor=iei&num=2
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:jarrell is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=xe7501devkit&vendor=intel&num=2
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=j7f24&vendor=jetway&num=2
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=frontrunner&vendor=lippert&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=ms6178&vendor=msi&num=2
Compilation of nec:powermate2000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=powermate2000&vendor=nec&num=2
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=rev_a&vendor=olpc&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=rm4100&vendor=rca&num=2
Compilation of supermicro:x6dai_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=ip1000&vendor=thomson&num=2
Configuration of totalimpact:briq has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=briq&vendor=totalimpact&num=1
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=s1846&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=epia&vendor=via&num=2
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=epia-m&vendor=via&num=2
Compilation of via:pc2500e is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4049&device=pc2500e&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From stepan at coresystems.de  Fri Apr  3 15:33:44 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 15:33:44 +0200
Subject: [coreboot] [PATCH] romcc --include=settings.h support
Message-ID: <49D61038.4060407@coresystems.de>

I figured we really want to have settings.h, so I added support for it
to romcc.

See patch.


Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From info at coresystems.de  Fri Apr  3 15:36:45 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 15:36:45 +0200
Subject: [coreboot] build service results for r4050
Message-ID: <E1LpjZd-0005Ja-Dz@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4050 to
the coreboot repository. This caused the following 
changes:

Change Log:
Next step. Kill auto.c and failover.c and clean up Config.lb for
tyan/s2735
tyan/s2850
tyan/s2875
tyan/s2880
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895

Abuild log is completely identical with and without the patch.


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=db800&vendor=amd&num=2
Compilation of amd:norwich is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=norwich&vendor=amd&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=rumba&vendor=amd&num=2
Compilation of artecgroup:dbe61 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:mew-am is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=winnetp680&vendor=bcom&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=s1850&vendor=dell&num=2
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm586seg is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=msm586seg&vendor=digitallogic&num=2
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=5bcm&vendor=eaglelion&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of iei:juki-511p is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=juki-511p&vendor=iei&num=2
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:jarrell is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=xe7501devkit&vendor=intel&num=2
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=j7f24&vendor=jetway&num=2
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=frontrunner&vendor=lippert&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=ms6178&vendor=msi&num=2
Compilation of nec:powermate2000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=powermate2000&vendor=nec&num=2
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=rev_a&vendor=olpc&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=rm4100&vendor=rca&num=2
Compilation of supermicro:x6dai_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=ip1000&vendor=thomson&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=briq&vendor=totalimpact&num=1
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=s1846&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=epia&vendor=via&num=2
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=epia-m&vendor=via&num=2
Compilation of via:pc2500e is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4050&device=pc2500e&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Fri Apr  3 15:38:11 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 15:38:11 +0200
Subject: [coreboot] [v2] r4049 - in trunk/coreboot-v2:
	src/arch/i386	src/boot util/newconfig
Message-ID: <20090403133811.9640.qmail@stuge.se>

svn at coreboot.org wrote:
> the attached patch is the last infrastructure change necessary for
> romfs.

Since coresystems is clearly actively working with this code I think
you guys are the only ones in a good position to create the name
change patch. I will ack it swiftly should you feel the need. (Please
don't forget the tool.)

I was thinking to produce the patch, but I'm not sure working against
the public repo would make much sense?


//Peter



From peter at stuge.se  Fri Apr  3 15:42:01 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 15:42:01 +0200
Subject: [coreboot] [PATCH] romcc --include=settings.h support
In-Reply-To: <49D61038.4060407@coresystems.de>
References: <49D61038.4060407@coresystems.de>
Message-ID: <20090403134201.10659.qmail@stuge.se>

Stefan Reinauer wrote:
> +++ util/romcc/romcc.c	(working copy)
> @@ -24998,7 +24998,10 @@
>  	/* Enter the globl definition scope */
>  	start_scope(&state);
>  	register_builtins(&state);
> +
>  	compile_file(&state, filename, 1);
> +	if (includefile)
> +		compile_file(&state, includefile, 1);

Shouldn't the include be compiled before the actual file?


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 15:44:55 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 15:44:55 +0200
Subject: [coreboot] [PATCH] romcc --include=settings.h support
In-Reply-To: <49D61038.4060407@coresystems.de>
References: <49D61038.4060407@coresystems.de>
Message-ID: <49D612D7.8070305@gmx.net>

On 03.04.2009 15:33, Stefan Reinauer wrote:
> I figured we really want to have settings.h, so I added support for it
> to romcc.
>   

Awesome, thanks!

> This patch implements --include=file.h for romcc.
>   

Please add --include to the romcc usage messsage as well.

> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>
> Index: util/romcc/romcc.c
> ===================================================================
> --- util/romcc/romcc.c	(revision 4046)
> +++ util/romcc/romcc.c	(working copy)
> @@ -3,8 +3,8 @@
>  #undef RELEASE_DATE
>  #undef VERSION
>  #define VERSION_MAJOR "0"
> -#define VERSION_MINOR "70"
> -#define RELEASE_DATE "23 October 2007"
> +#define VERSION_MINOR "71"
> +#define RELEASE_DATE "03 April 2009"
>  #define VERSION VERSION_MAJOR "." VERSION_MINOR
>  
>  #include <stdarg.h>
> @@ -24925,7 +24925,7 @@
>  	}
>  }
>  
> -static void compile(const char *filename, 
> +static void compile(const char *filename, const char *includefile,
>  	struct compiler_state *compiler, struct arch_state *arch)
>  {
>  	int i;
> @@ -24998,7 +24998,10 @@
>  	/* Enter the globl definition scope */
>  	start_scope(&state);
>  	register_builtins(&state);
> +
>  	compile_file(&state, filename, 1);
> +	if (includefile)
> +		compile_file(&state, includefile, 1);
>   

This looks strange. Do we really want to compile the include file
_after_ compiling the .c file? Wouldn't that make all #defines ineffective?

>  
>  	/* Stop if all we want is preprocessor output */
>  	if (state.compiler->flags & COMPILER_PP_ONLY) {
> @@ -25065,6 +25068,7 @@
>  int main(int argc, char **argv)
>  {
>  	const char *filename;
> +	const char *includefile = NULL;
>  	struct compiler_state compiler;
>  	struct arch_state arch;
>  	int all_opts;
> @@ -25114,6 +25118,14 @@
>  			else if (strncmp(argv[1], "-m", 2) == 0) {
>  				result = arch_encode_flag(&arch, argv[1]+2);
>  			}
> +			else if (strncmp(argv[1], "--include=", 10) == 0) {
> +				if (includefile) {
> +					arg_error("Only one --include option may be specified.\n");
> +				} else {
> +					includefile = argv[1] + 10;
> +					result = 0;
> +				}
> +			}
>  			if (result < 0) {
>  				arg_error("Invalid option specified: %s\n",
>  					argv[1]);
> @@ -25133,7 +25145,7 @@
>  	if (!filename) {
>  		arg_error("No filename specified\n");
>  	}
> -	compile(filename, &compiler, &arch);
> +	compile(filename, includefile, &compiler, &arch);
>  
>  	return 0;
>  }
>   

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From patrick at georgi-clan.de  Fri Apr  3 15:45:21 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 03 Apr 2009 15:45:21 +0200
Subject: [coreboot] [PATCH] romcc --include=settings.h support
In-Reply-To: <49D61038.4060407@coresystems.de>
References: <49D61038.4060407@coresystems.de>
Message-ID: <49D612F1.6000505@georgi-clan.de>

Am 03.04.2009 15:33, schrieb Stefan Reinauer:
> I figured we really want to have settings.h, so I added support for it
> to romcc.
>
>    
Works for me, even though the compile_file order looks funny.
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



From stepan at coresystems.de  Fri Apr  3 15:46:40 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 15:46:40 +0200
Subject: [coreboot] [PATCH] romcc --include=settings.h support
In-Reply-To: <20090403134201.10659.qmail@stuge.se>
References: <49D61038.4060407@coresystems.de>
	<20090403134201.10659.qmail@stuge.se>
Message-ID: <49D61340.6000906@coresystems.de>

On 03.04.2009 15:42 Uhr, Peter Stuge wrote:
> Stefan Reinauer wrote:
>   
>> +++ util/romcc/romcc.c	(working copy)
>> @@ -24998,7 +24998,10 @@
>>  	/* Enter the globl definition scope */
>>  	start_scope(&state);
>>  	register_builtins(&state);
>> +
>>  	compile_file(&state, filename, 1);
>> +	if (includefile)
>> +		compile_file(&state, includefile, 1);
>>     
>
> Shouldn't the include be compiled before the actual file?
>   

Yes, but romcc seems to parse it the other way round. My tests showed
the above produces correct results, while turning the statements around
does not (the first version of my patch looked that way)

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From peter at stuge.se  Fri Apr  3 15:54:21 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 15:54:21 +0200
Subject: [coreboot] [PATCH] romcc --include=settings.h support
In-Reply-To: <49D61340.6000906@coresystems.de>
References: <49D61038.4060407@coresystems.de>
	<20090403134201.10659.qmail@stuge.se>
	<49D61340.6000906@coresystems.de>
Message-ID: <20090403135421.14056.qmail@stuge.se>

Stefan Reinauer wrote:
> >>  	compile_file(&state, filename, 1);
> >> +	if (includefile)
> >> +		compile_file(&state, includefile, 1);
> >
> > Shouldn't the include be compiled before the actual file?
> 
> Yes, but romcc seems to parse it the other way round. My tests
> showed the above produces correct results, while turning the
> statements around does not (the first version of my patch looked
> that way)

Hah! Ok. :) I guess it builds some kind of data structure which is
finally processed in reverse order.

Thanks for explaining it - please put a note in the commit message.

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Fri Apr  3 16:04:07 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 16:04:07 +0200
Subject: [coreboot] [v2] r4051 - trunk/coreboot-v2/util/romcc
Message-ID: <mailman.2928.1355071509.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-03 16:04:06 +0200 (Fri, 03 Apr 2009)
New Revision: 4051

Modified:
   trunk/coreboot-v2/util/romcc/romcc.c
Log:
This patch implements --include=file.h for romcc.

The compile_file calls seem to be in the wrong order, but
romcc actually requires it that (probably some stack-like
file processing)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/util/romcc/romcc.c
===================================================================
--- trunk/coreboot-v2/util/romcc/romcc.c	2009-04-03 12:55:55 UTC (rev 4050)
+++ trunk/coreboot-v2/util/romcc/romcc.c	2009-04-03 14:04:06 UTC (rev 4051)
@@ -3,8 +3,8 @@
 #undef RELEASE_DATE
 #undef VERSION
 #define VERSION_MAJOR "0"
-#define VERSION_MINOR "70"
-#define RELEASE_DATE "23 October 2007"
+#define VERSION_MINOR "71"
+#define RELEASE_DATE "03 April 2009"
 #define VERSION VERSION_MAJOR "." VERSION_MINOR
 
 #include <stdarg.h>
@@ -24925,7 +24925,7 @@
 	}
 }
 
-static void compile(const char *filename, 
+static void compile(const char *filename, const char *includefile,
 	struct compiler_state *compiler, struct arch_state *arch)
 {
 	int i;
@@ -24998,7 +24998,10 @@
 	/* Enter the globl definition scope */
 	start_scope(&state);
 	register_builtins(&state);
+
 	compile_file(&state, filename, 1);
+	if (includefile)
+		compile_file(&state, includefile, 1);
 
 	/* Stop if all we want is preprocessor output */
 	if (state.compiler->flags & COMPILER_PP_ONLY) {
@@ -25065,6 +25068,7 @@
 int main(int argc, char **argv)
 {
 	const char *filename;
+	const char *includefile = NULL;
 	struct compiler_state compiler;
 	struct arch_state arch;
 	int all_opts;
@@ -25114,6 +25118,14 @@
 			else if (strncmp(argv[1], "-m", 2) == 0) {
 				result = arch_encode_flag(&arch, argv[1]+2);
 			}
+			else if (strncmp(argv[1], "--include=", 10) == 0) {
+				if (includefile) {
+					arg_error("Only one --include option may be specified.\n");
+				} else {
+					includefile = argv[1] + 10;
+					result = 0;
+				}
+			}
 			if (result < 0) {
 				arg_error("Invalid option specified: %s\n",
 					argv[1]);
@@ -25133,7 +25145,7 @@
 	if (!filename) {
 		arg_error("No filename specified\n");
 	}
-	compile(filename, &compiler, &arch);
+	compile(filename, includefile, &compiler, &arch);
 
 	return 0;
 }




From patrick at georgi-clan.de  Fri Apr  3 16:12:38 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 03 Apr 2009 16:12:38 +0200
Subject: [coreboot] [PATCH]romfs: avoid build errors for non-romfs targets,
 and support lzma compression for romfs targets
Message-ID: <49D61956.8050400@georgi-clan.de>

Hi,

I thought that romfs infrastructure is done now, but there were some 
issues (see buildbot).
The romfs image was always built, and sometimes broke (because of the 
different image layouts) for buildrom images. After the patch, these 
issues are avoided by not adding payloads to the romfs image (they 
wouldn't be read anyway). Both workarounds (in buildrom code for romfs 
and vice-versa) aren't very pretty, but that's what our buildsystem 
requires.
As I had to create a "communication channel" (via the romfs-support 
files), I took the chance to also use it for compression information, so 
if you configure lzma support, you'll get lzma compressed payloads in romfs.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>


Patrick
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From svn at coreboot.org  Fri Apr  3 17:02:08 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 17:02:08 +0200
Subject: [coreboot] [v2] r4052 - trunk/coreboot-v2/src/stream
Message-ID: <mailman.2929.1355071509.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-03 17:02:08 +0200 (Fri, 03 Apr 2009)
New Revision: 4052

Modified:
   trunk/coreboot-v2/src/stream/rom_stream.c
Log:
Print a pointer as pointer, it's really trivial.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/src/stream/rom_stream.c
===================================================================
--- trunk/coreboot-v2/src/stream/rom_stream.c	2009-04-03 14:04:06 UTC (rev 4051)
+++ trunk/coreboot-v2/src/stream/rom_stream.c	2009-04-03 15:02:08 UTC (rev 4052)
@@ -94,7 +94,7 @@
 	 * long term, this has got to be fixed. 
 	 */
 	dest  = (unsigned char *) (16 * 1024 * 1024);
-        printk_debug("Uncompressing to RAM 0x%08lx ", dest);
+        printk_debug("Uncompressing to RAM %p ", dest);
         olen = uncompress((uint8_t *) rom_start, (uint8_t *)dest );
 	printk_debug(" olen = 0x%08lx done.\n", olen);
 	if (olen != 0) {




From patrick at georgi-clan.de  Fri Apr  3 17:15:40 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 03 Apr 2009 17:15:40 +0200
Subject: [coreboot] [PATCH]handle both oldstyle and newstyle lzma(1) utility
Message-ID: <49D6281C.4060001@georgi-clan.de>

The attached patch tries new style compression first and runs old style 
compression if the command returned an error code (happens if you run an 
old lzma with the new arguments)

Tested on new-style lzma only (as I lack a build environment with old 
lzma), but I tested that the old lzma returns with an error code.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From rminnich at gmail.com  Fri Apr  3 17:39:56 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 3 Apr 2009 08:39:56 -0700
Subject: [coreboot] [PATCH]romfs final patch
In-Reply-To: <49D5FFAF.4090906@coresystems.de>
References: <49D5FB44.10708@georgi-clan.de> <49D5FFAF.4090906@coresystems.de>
Message-ID: <13426df10904030839n5818425fm43b3d9cc4e2e9b4@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From stepan at coresystems.de  Fri Apr  3 17:44:02 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 17:44:02 +0200
Subject: [coreboot] [PATCH]handle both oldstyle and newstyle lzma(1)
	utility
In-Reply-To: <49D6281C.4060001@georgi-clan.de>
References: <49D6281C.4060001@georgi-clan.de>
Message-ID: <49D62EC2.3010306@coresystems.de>

On 03.04.2009 17:15 Uhr, Patrick Georgi wrote:
> The attached patch tries new style compression first and runs old
> style compression if the command returned an error code (happens if
> you run an old lzma with the new arguments)
>
> Tested on new-style lzma only (as I lack a build environment with old
> lzma), but I tested that the old lzma returns with an error code.
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From info at coresystems.de  Fri Apr  3 17:45:39 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 17:45:39 +0200
Subject: [coreboot] build service results for r4051
Message-ID: <E1LplaN-0007Vg-EY@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4051 to
the coreboot repository. This caused the following 
changes:

Change Log:
This patch implements --include=file.h for romcc.

The compile_file calls seem to be in the wrong order, but
romcc actually requires it that (probably some stack-like
file processing)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=db800&vendor=amd&num=2
Compilation of amd:norwich is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=norwich&vendor=amd&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=rumba&vendor=amd&num=2
Compilation of artecgroup:dbe61 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:mew-am has been fixed
Compilation of asus:mew-vm has been fixed
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 has been fixed
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 has been fixed
Compilation of digitallogic:adl855pc has been fixed
Compilation of digitallogic:msm586seg has been fixed
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=5bcm&vendor=eaglelion&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of emulation:qemu-x86 has been fixed
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of iei:juki-511p has been fixed
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:jarrell has been fixed
Compilation of intel:mtarvon has been fixed
Compilation of intel:truxton has been fixed
Compilation of intel:xe7501devkit has been fixed
Compilation of jetway:j7f24 has been fixed
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=frontrunner&vendor=lippert&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 has been fixed
Compilation of nec:powermate2000 has been fixed
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=rev_a&vendor=olpc&num=2
Compilation of rca:rm4100 has been fixed
Compilation of supermicro:x6dai_g has been fixed
Compilation of supermicro:x6dhe_g has been fixed
Compilation of supermicro:x6dhe_g2 has been fixed
Compilation of supermicro:x6dhr_ig has been fixed
Compilation of supermicro:x6dhr_ig2 has been fixed
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 has been fixed
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=briq&vendor=totalimpact&num=1
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=s1846&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4051&device=epia&vendor=via&num=2
Compilation of via:epia-cn has been fixed
Compilation of via:epia-m has been fixed
Compilation of via:pc2500e has been fixed


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Apr  3 17:57:59 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 17:57:59 +0200
Subject: [coreboot] [v2] r4053 - trunk/coreboot-v2/src/arch/i386
Message-ID: <mailman.2930.1355071509.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-03 17:57:58 +0200 (Fri, 03 Apr 2009)
New Revision: 4053

Modified:
   trunk/coreboot-v2/src/arch/i386/Config.lb
Log:
The attached patch tries new style compression first and runs old
style compression if the command returned an error code (happens if
you run an old lzma with the new arguments)

Tested on new-style lzma only (as I lack a build environment with
old lzma), but I tested that the old lzma returns with an error code.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Config.lb	2009-04-03 15:02:08 UTC (rev 4052)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb	2009-04-03 15:57:58 UTC (rev 4053)
@@ -48,7 +48,7 @@
 # unlike nrv2b, lzma is a huge build mess. If they want lzma, they have to have built it
 makerule payload.lzma
 	depends "$(PAYLOAD) "
-	action  "lzma e $(PAYLOAD) $@"
+	action  "lzma -zc $(PAYLOAD) > $@ || lzma e $(PAYLOAD) $@"
 end
 
 




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 18:13:13 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 18:13:13 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D60699.4080403@coresystems.de>
References: <49D56D64.3000303@gmx.net> <49D60380.4040207@gmx.net>
	<49D60699.4080403@coresystems.de>
Message-ID: <49D63599.1000106@gmx.net>

On 03.04.2009 14:52, Stefan Reinauer wrote:
> On 03.04.2009 14:39 Uhr, Carl-Daniel Hailfinger wrote:
>   
>> On 03.04.2009 03:59, Carl-Daniel Hailfinger wrote:
>>   
>>     
>>> There are more than a dozen targets in the v2 tree which refer to ROMCC
>>> in their Config.lb but never use it. There's no point in keeping dead
>>> code around. Kill it.
>>>
>>> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
>>> tyan/s2850.
>>>
>>> Abuild build log with and without the patch is completely identical.
>>>
>>> If this patch is OK, I'll create more of the same type, hopefully making
>>> ROMCC dependencies a bit more clear for v2.
>>>
>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>   
>>>     
>>>       
>> Next step. Kill auto.c and failover.c and clean up Config.lb for
>> tyan/s2735
>> tyan/s2850
>> tyan/s2875
>> tyan/s2880
>> tyan/s2881
>> tyan/s2882
>> tyan/s2885
>> tyan/s2891
>> tyan/s2892
>> tyan/s2895
>>
>> Abuild log is completely identical with and without the patch.
>>
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>
>>   
>>     
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
>   

Thanks, committed in r4050.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From info at coresystems.de  Fri Apr  3 18:13:29 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 18:13:29 +0200
Subject: [coreboot] build service results for r4052
Message-ID: <E1Lpm1J-0004ZT-A4@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4052 to
the coreboot repository. This caused the following 
changes:

Change Log:
Print a pointer as pointer, it's really trivial.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=db800&vendor=amd&num=2
Compilation of amd:norwich is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=norwich&vendor=amd&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=rumba&vendor=amd&num=2
Compilation of artecgroup:dbe61 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=winnet100&vendor=bcom&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=5bcm&vendor=eaglelion&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=frontrunner&vendor=lippert&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=ms6147&vendor=msi&num=2
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=rev_a&vendor=olpc&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=tc7020&vendor=televideo&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=briq&vendor=totalimpact&num=1
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=s1846&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4052&device=epia&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From stepan at coresystems.de  Fri Apr  3 18:15:37 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 18:15:37 +0200
Subject: [coreboot] [PATCH]romfs: avoid build errors for non-romfs
 targets, and support lzma compression for romfs targets
In-Reply-To: <49D61956.8050400@georgi-clan.de>
References: <49D61956.8050400@georgi-clan.de>
Message-ID: <49D63629.2080101@coresystems.de>

On 03.04.2009 16:12 Uhr, Patrick Georgi wrote:
> Hi,
>
> I thought that romfs infrastructure is done now, but there were some
> issues (see buildbot).
> The romfs image was always built, and sometimes broke (because of the
> different image layouts) for buildrom images. After the patch, these
> issues are avoided by not adding payloads to the romfs image (they
> wouldn't be read anyway). Both workarounds (in buildrom code for romfs
> and vice-versa) aren't very pretty, but that's what our buildsystem
> requires.
> As I had to create a "communication channel" (via the romfs-support
> files), I took the chance to also use it for compression information,
> so if you configure lzma support, you'll get lzma compressed payloads
> in romfs.
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Fri Apr  3 18:17:05 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 18:17:05 +0200
Subject: [coreboot] [v2] r4054 - in trunk/coreboot-v2: src/arch/i386
	util/newconfig
Message-ID: <mailman.2931.1355071509.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-03 18:17:05 +0200 (Fri, 03 Apr 2009)
New Revision: 4054

Modified:
   trunk/coreboot-v2/src/arch/i386/Config.lb
   trunk/coreboot-v2/util/newconfig/config.g
Log:
I thought that romfs infrastructure is done now, but there were some
issues (see buildbot).
The romfs image was always built, and sometimes broke (because of
the different image layouts) for buildrom images. After the patch, these
issues are avoided by not adding payloads to the romfs image (they
wouldn't be read anyway). Both workarounds (in buildrom code for
romfs and vice-versa) aren't very pretty, but that's what our buildsystem
requires.
As I had to create a "communication channel" (via the romfs-support
files), I took the chance to also use it for compression
information, so if you configure lzma support, you'll get lzma
compressed payloads in romfs.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Config.lb	2009-04-03 15:57:58 UTC (rev 4053)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
@@ -80,7 +80,8 @@
 else
 	makerule coreboot.rom 
 		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
-		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_ROMFS) -eq 1 ]; then PAYLOAD=/dev/null; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
+		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_ROMFS) -eq 1 ]; then PAYLOAD=/dev/null; touch romfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
+		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_ROMFS) -eq 1 ]; then echo l > romfs-support; fi"
 	end
 end
 

Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2009-04-03 15:57:58 UTC (rev 4053)
+++ trunk/coreboot-v2/util/newconfig/config.g	2009-04-03 16:17:05 UTC (rev 4054)
@@ -2275,7 +2275,7 @@
 		for j in i.roms:
 			#failover is a hack that will go away soon. 
 			if (j != "failover") and (rommapping[j] != "/dev/null"):
-				file.write("\t $(TOP)/util/romtool/romtool %sfs add-payload %s %s/payload\n" % (i.name, rommapping[j], j))
+				file.write("\tif [ -f %s/romfs-support ]; then $(TOP)/util/romtool/romtool %sfs add-payload %s %s/payload `cat %s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j))
 		file.write("\t $(TOP)/util/romtool/romtool %sfs print\n" % i.name)
 
 	file.write(".PHONY: all clean romtool")




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 18:17:48 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 18:17:48 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D60380.4040207@gmx.net>
References: <49D56D64.3000303@gmx.net> <49D60380.4040207@gmx.net>
Message-ID: <49D636AC.6090203@gmx.net>

On 03.04.2009 14:39, Carl-Daniel Hailfinger wrote:
> On 03.04.2009 03:59, Carl-Daniel Hailfinger wrote:
>   
>> There are more than a dozen targets in the v2 tree which refer to ROMCC
>> in their Config.lb but never use it. There's no point in keeping dead
>> code around. Kill it.
>>
>> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
>> tyan/s2850.
>>
>> Abuild build log with and without the patch is completely identical.
>>
>> If this patch is OK, I'll create more of the same type, hopefully making
>> ROMCC dependencies a bit more clear for v2.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>   
>>     
>
> Next step. Kill auto.c and failover.c and clean up Config.lb for
> tyan/s2735
> tyan/s2850
> tyan/s2875
> tyan/s2880
> tyan/s2881
> tyan/s2882
> tyan/s2885
> tyan/s2891
> tyan/s2892
> tyan/s2895
>
> Abuild log is completely identical with and without the patch.
>
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

You know the drill...

arima/hdama
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms9282
newisys/khepri
sunw/ultra40
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882

Abuild log is completely identical with and without the patch.

With this patch, the last ROMCC remainders for K8 boards are gone.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Patrick, this time I want to commit the patch :-P


Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/Config.lb	(working copy)
@@ -50,8 +50,6 @@
 ## ATI Rage XL framebuffering graphics driver
 dir /drivers/ati/ragexl
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -69,31 +67,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -104,7 +78,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -112,7 +85,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -125,24 +97,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -150,13 +114,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -165,28 +124,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/failover.c	(working copy)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/auto.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/auto.c	(working copy)
@@ -1,159 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	} else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */	
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-	
-#if 0
-	print_pci_devices();
-#endif
-
-	enable_smbus();
-
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
-	dump_pci_devices();
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/Config.lb	(working copy)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,31 +64,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -101,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -109,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/failover.c	(working copy)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/auto.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/auto.c	(working copy)
@@ -1,189 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-	else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-#if 0
-	print_pci_devices();
-#endif
-	enable_smbus();
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 1
-	dump_pci_devices();
-#endif
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-	/* Check all of memory */
-#if 0
-	msr_t msr;
-	msr = rdmsr(TOP_MEM);
-	print_debug("TOP_MEM: ");
-	print_debug_hex32(msr.hi);
-	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
-#endif
-#if 0
-	ram_check(0x00000000, msr.lo);
-#endif
-#if 0
-	static const struct {
-		unsigned long lo, hi;
-	} check_addrs[] = {
-		/* Check 16MB of memory @ 0*/
-		{ 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
-		/* Check 16MB of memory @ 2GB */
-		{ 0x80000000, 0x81000000 },
-#endif
-	};
-	int i;
-	for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
-		ram_check(check_addrs[i].lo, check_addrs[i].hi);
-	}
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/Config.lb	(working copy)
@@ -43,7 +43,6 @@
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
 
 	if CONFIG_USE_INIT
 
@@ -61,44 +60,7 @@
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 			end
 	end
-else
 
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-	        depends "$(MAINBOARD)/failover.c ../romcc"
-        	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	##
-	## Setup RAM
-	##
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-	mainboardinit arch/i386/lib/jmp_auto_out.inc
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -109,7 +71,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -117,9 +78,7 @@
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
-
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
@@ -131,25 +90,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -157,32 +107,18 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
 		ldscript /arch/i386/lib/failover.lds
-	else
-       		ldscript /arch/i386/lib/failover.lds
-	        mainboardinit ./failover.inc
-	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-
-	# ROMCC
-	mainboardinit arch/i386/lib/jmp_auto.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/failover.c	(working copy)
@@ -1,69 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-               if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/auto.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/auto.c	(working copy)
@@ -1,233 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
-        unsigned device=(ctrl->channel0[0])>>8;
-        smbus_write_byte(SMBUS_HUB , 0x01, device);
-        smbus_write_byte(SMBUS_HUB , 0x03, 0);
-}
-#if 0
-static inline void change_i2c_mux(unsigned device)
-{
-#define SMBUS_HUB 0x18
-        smbus_write_byte(SMBUS_HUB , 0x01, device);
-        smbus_write_byte(SMBUS_HUB , 0x03, 0);
-}
-#endif
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-
-#define THIRD_CPU  1 
-#define FOURTH_CPU 1 
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
-
-#define RC0 ((1<<1)<<8)
-#define RC1 ((1<<2)<<8)
-#define RC2 ((1<<3)<<8)
-#define RC3 ((1<<4)<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-        
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
-                        .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
-                },
-#endif
-#if SECOND_CPU
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { RC1|DIMM0, 0 , 0, 0 },
-                        .channel1 = { RC1|DIMM1, 0, 0, 0 },
-
-                },
-#endif
-
-#if THIRD_CPU
-                {
-                        .node_id = 2,
-                        .f0 = PCI_DEV(0, 0x1a, 0),
-                        .f1 = PCI_DEV(0, 0x1a, 1),
-                        .f2 = PCI_DEV(0, 0x1a, 2),
-                        .f3 = PCI_DEV(0, 0x1a, 3),
-                        .channel0 = { RC2|DIMM0, 0, 0, 0 },
-                        .channel1 = { RC2|DIMM1, 0, 0, 0 },
-
-                },
-#endif
-#if FOURTH_CPU
-                {
-                        .node_id = 3,
-                        .f0 = PCI_DEV(0, 0x1b, 0),
-                        .f1 = PCI_DEV(0, 0x1b, 1),
-                        .f2 = PCI_DEV(0, 0x1b, 2),
-                        .f3 = PCI_DEV(0, 0x1b, 3),
-                        .channel0 = { RC3|DIMM0, 0, 0, 0 },
-                        .channel1 = { RC3|DIMM1, 0, 0, 0 },
-
-                },
-#endif
-	};
-	int i;
-        int needs_reset;
-
-        if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_s4880_resource_map();
-
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chains_x();
-	
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-#if 0
-	dump_pci_devices();
-#endif
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/Config.lb	(working copy)
@@ -63,8 +63,6 @@
 	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
 end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 	makerule ./auto.o
 		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -79,32 +77,6 @@
 	end
 end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -115,7 +87,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
 	end
@@ -123,7 +94,6 @@
 	if CONFIG_USE_INIT
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -136,12 +106,6 @@
 	ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -156,12 +120,10 @@
 	ldscript /southbridge/nvidia/ck804/romstrap.lds
 end
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -170,10 +132,6 @@
 ###
 if USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
-	if USE_DCACHE_RAM
-	else
-		mainboardinit ./failover.inc
-	end
 end
 
 ###
@@ -183,25 +141,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/Config.lb	(working copy)
@@ -63,8 +63,6 @@
 	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
 end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 	makerule ./auto.o
 		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -79,32 +77,6 @@
 	end
 end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -115,7 +87,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
 	end
@@ -123,7 +94,6 @@
 	if CONFIG_USE_INIT
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -136,12 +106,6 @@
 	ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -156,12 +120,10 @@
 	ldscript /southbridge/nvidia/ck804/romstrap.lds
 end
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -169,12 +131,7 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
 		ldscript /arch/i386/lib/failover.lds
-	else
-		ldscript /arch/i386/lib/failover.lds
-		mainboardinit ./failover.inc
-	end
 end
 
 ###
@@ -184,25 +141,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/Config.lb	(working copy)
@@ -43,7 +43,6 @@
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
 
 	if CONFIG_USE_INIT
 
@@ -61,44 +60,7 @@
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 			end
 	end
-else
 
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-	        depends "$(MAINBOARD)/failover.c ../romcc"
-        	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	##
-	## Setup RAM
-	##
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-	mainboardinit arch/i386/lib/jmp_auto_out.inc
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -109,7 +71,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -117,9 +78,7 @@
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
-
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
@@ -131,25 +90,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -157,32 +107,18 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
 		ldscript /arch/i386/lib/failover.lds
-	else
-       		ldscript /arch/i386/lib/failover.lds
-	        mainboardinit ./failover.inc
-	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-
-	# ROMCC
-	mainboardinit arch/i386/lib/jmp_auto.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/failover.c	(working copy)
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/auto.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/auto.c	(working copy)
@@ -1,233 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
-	int ret,i;
-        unsigned device=(ctrl->channel0[0])>>8;
-	/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-	i=2;
-	do {
-	        ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-	} while ((ret!=0) && (i-->0));
-
-        smbus_write_byte(SMBUS_HUB, 0x03, 0);
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#if 0           
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else                   
-        #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-
-#define THIRD_CPU  1 
-#define FOURTH_CPU 1 
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
-
-#define RC0 ((1<<2)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<4)<<8)
-#define RC3 ((1<<3)<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-        
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
-                        .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
-                },
-#endif
-#if SECOND_CPU
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
-                        .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
-
-                },
-#endif
-
-#if THIRD_CPU
-                {
-                        .node_id = 2,
-                        .f0 = PCI_DEV(0, 0x1a, 0),
-                        .f1 = PCI_DEV(0, 0x1a, 1),
-                        .f2 = PCI_DEV(0, 0x1a, 2),
-                        .f3 = PCI_DEV(0, 0x1a, 3),
-                        .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
-                        .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
-
-                },
-#endif
-#if FOURTH_CPU
-                {
-                        .node_id = 3,
-                        .f0 = PCI_DEV(0, 0x1b, 0),
-                        .f1 = PCI_DEV(0, 0x1b, 1),
-                        .f2 = PCI_DEV(0, 0x1b, 2),
-                        .f3 = PCI_DEV(0, 0x1b, 3),
-                        .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
-                        .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
-
-                },
-#endif
-	};
-	int i;
-        int needs_reset;
-        
-        if (bist == 0) {
-		k8_init_and_stop_secondaries();
-        }
-                        
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-        report_bist_failure(bist);
-	
-        setup_s4882_resource_map();
-
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chains_x();
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-	
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/Config.lb	(working copy)
@@ -72,8 +72,6 @@
 	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
 end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 	makerule ./auto.o
 		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -88,32 +86,6 @@
 	end
 end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -131,7 +103,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
 	end
@@ -139,7 +110,6 @@
 	if CONFIG_USE_INIT
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -162,12 +132,6 @@
     end
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -189,12 +153,10 @@
 	end
 end
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -203,42 +165,23 @@
 ###
 if HAVE_FAILOVER_BOOT
 	if USE_FAILOVER_IMAGE
-		if USE_DCACHE_RAM
 			ldscript /arch/i386/lib/failover_failover.lds
-		end
 	end
 else
 	if USE_FALLBACK_IMAGE
-		if USE_DCACHE_RAM
 			ldscript /arch/i386/lib/failover.lds
-		else
-			mainboardinit ./failover.inc
-		end
 	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/Config.lb	(working copy)
@@ -75,8 +75,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -94,34 +92,8 @@
 end
 
 end
-else
 
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-
-end
-
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -131,7 +103,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript /cpu/x86/32bit/entry32.lds
        end
@@ -139,7 +110,6 @@
        if CONFIG_USE_INIT
                ldscript      /cpu/amd/car/cache_as_ram.lds
        end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -152,12 +122,6 @@
        ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -172,12 +136,10 @@
        ldscript /southbridge/nvidia/mcp55/romstrap.lds
 end
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -185,13 +147,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-       mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -200,25 +157,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-# ROMCC
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/failover.c	(working copy)
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static void sio_setup(void)
-{
-
-        unsigned value;
-       uint32_t dword;
-       uint8_t byte;
-
-        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-       dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-       dword |= (1<<0);
-       pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-               if (last_boot_normal()) {
-                       goto normal_image;
-               } else {
-                       goto fallback_image;
-               }
-       }
-
-       /* Is this a secondary cpu? */
-       if (!boot_cpu()) {
-               if (last_boot_normal()) {
-                       goto normal_image;
-               } else {
-                       goto fallback_image;
-               }
-       }
-
-       /* Nothing special needs to be done to find bus 0 */
-       /* Allow the HT devices to be found */
-
-       enumerate_ht_chain();
-
-       sio_setup();
-
-       /* Setup the mcp55 */
-       mcp55_enable_rom();
-
-       /* Is this a deliberate reset by the bios */
-       if (bios_reset_detected() && last_boot_normal()) {
-               goto normal_image;
-       }
-       /* This is the primary cpu how should I boot? */
-       else if (do_normal_boot()) {
-               goto normal_image;
-       }
-       else {
-               goto fallback_image;
-       }
- normal_image:
-       asm volatile ("jmp __normal_image"
-               : /* outputs */
-               : "a" (bist) /* inputs */
-               : /* clobbers */
-               );
- fallback_image:
-       return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/Config.lb	(working copy)
@@ -46,8 +46,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -65,31 +63,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -100,7 +74,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -108,7 +81,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -121,24 +93,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -146,13 +110,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -161,28 +120,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/failover.c	(working copy)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-	unsigned nodeid;
-
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	nodeid = lapicid() & 0xf;
-
-	/* Is this a cpu only reset? */
-	if (cpu_init_detected(nodeid)) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/auto.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/auto.c	(working copy)
@@ -1,179 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-
-static void hard_reset(void)
-{
-	device_t dev;
-
-	/* Find the device */
-	dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-	
-	/* enable cf9 */
-	pci_write_config8(dev, 0x41, 0xf1);
-
-	/* reset */
-	set_bios_reset();
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	device_t dev;
-	
-	/* Find the device */
-	dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-	/* Reset */
-	set_bios_reset();
-	pci_write_config8(dev, 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-	else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "debug.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-#if 0
-	print_pci_devices();
-#endif
-	enable_smbus();
-#if 0
-	dump_spd_registers(ARRAY_SIZE(cpu), cpu);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-	
-#if 0
-	dump_pci_devices();
-#endif
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-	dump_pci_device(PCI_DEV(0, 0x18, 3));
-#endif
-
-#if 0
-	/* Check the first 1M */
-	ram_check(0x00000000, 0x000100000);
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/Config.lb	(working copy)
@@ -47,8 +47,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT	
 		makerule ./auto.o
 		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -63,32 +61,6 @@
 		end
 	end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -99,7 +71,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,9 +78,7 @@
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
-
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
@@ -121,12 +90,6 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -141,14 +104,10 @@
 	ldscript /southbridge/nvidia/ck804/romstrap.lds
 end
 
-
-
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -157,34 +116,17 @@
 ###
 if USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
-	if USE_DCACHE_RAM
-	else
-	        mainboardinit ./failover.inc
-	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/failover.c	(working copy)
@@ -1,118 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-
-#include <device/pnp_def.h>  
-
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-#define SUPERIO_COM1_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-#define SUPERIO_COM1_IO_BASE 0x3f8
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);  
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<29)|(1<<0);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if  1
-        lpc47b397_enable_serial(SUPERIO_COM1_DEV, SUPERIO_COM1_IO_BASE);
-
-#if 0
-/* what's this?
-	value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
-	value &= 0xbf;
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-*/
-#endif
-#endif
-
-}
-
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-
-static unsigned long main(unsigned long bist)
-{
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/auto.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/auto.c	(working copy)
@@ -1,198 +0,0 @@
-#define ASSEMBLY 1
- 
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-#include <cpu/amd/model_fxx_rev.h>
-//#define K8_HT_FREQ_1G_SUPPORT 1
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_msr.h>
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-static void hard_reset(void)
-{
-        set_bios_reset();
-
-        /* full reset */
-	outb(0x0a, 0x0cf9);
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        set_bios_reset();
-#if 1
-        /* link reset */
-	outb(0x02, 0x0cf9);
-        outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-        
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void sio_gpio_setup(void){
-
-	unsigned value;
-
-//	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
-
-#if 1
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
-	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-#endif
-	
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-
-#include "northbridge/amd/amdk8/raminit.c"
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else
-        #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* maybe does not want the default */
-#include "resourcemap.c"
-
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 2
-#define CK804B_BUSN 0x80
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-
-//set GPIO to input mode
-#define CK804_MB_SETUP \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-		
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-        int needs_reset;
-
-        if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-        }
-
-	// post_code(0x32);
-
-        lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-	
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	sio_gpio_setup();
-
-        setup_ultra40_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();	
-
-       	if (needs_reset) {
-               	print_info("ht reset -\r\n");
-               	soft_reset();
-       	}
-
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/Config.lb	(working copy)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,32 +64,7 @@
 end
 
 end
-else
- 
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -102,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -110,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -123,23 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-### Should this be in the northbridge code?
-if USE_DCACHE_RAM
-else
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
 	ldscript /arch/i386/lib/failover.lds
-else
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,29 +121,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
-##
-## Setup RAM
-##
-
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 config chip.h
 
 # FIXME: ROM for onboard VGA
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/failover.c	(working copy)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-	unsigned nodeid;
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	nodeid=lapicid();
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/auto.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/auto.c	(working copy)
@@ -1,155 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-	else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-
-#include "sdram/generic_sdram.c"
-
-/* newisys khepri does not want the default */
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define NODE_RAM(x)                     \
-	.node_id = 0+x,                 \
-	.f0 = PCI_DEV(0, 0x18+x, 0),    \
-	.f1 = PCI_DEV(0, 0x18+x, 1),    \
-	.f2 = PCI_DEV(0, 0x18+x, 2),    \
-	.f3 = PCI_DEV(0, 0x18+x, 3)
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-		{
-			NODE_RAM(0),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-		{
-			NODE_RAM(1),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_khepri_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset=ht_setup_chains_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-#if 0
-	print_pci_devices();
-#endif
-	enable_smbus();
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
-	dump_pci_devices();
-#endif
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-#if 0
-	/* Check the first 1M */
-	ram_check(0x00000000, 0x000100000);
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/Config.lb	(working copy)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,31 +64,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -101,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -109,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/failover.c	(working copy)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-        nodeid = lapicid() & 0xf;
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/Config.lb	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/Config.lb	(working copy)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,31 +64,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -101,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -109,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/failover.c	(revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/failover.c	(working copy)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-        nodeid = lapicid() & 0xf;
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}


-- 
http://www.hailfinger.org/

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From patrick at georgi-clan.de  Fri Apr  3 18:20:01 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 03 Apr 2009 18:20:01 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D636AC.6090203@gmx.net>
References: <49D56D64.3000303@gmx.net> <49D60380.4040207@gmx.net>
	<49D636AC.6090203@gmx.net>
Message-ID: <49D63731.80004@georgi-clan.de>

Am 03.04.2009 18:17, schrieb Carl-Daniel Hailfinger:
> You know the drill...
>
> arima/hdama
> ibm/e325
> ibm/e326
> iwill/dk8s2
> iwill/dk8x
> msi/ms9282
> newisys/khepri
> sunw/ultra40
> tyan/s2891
> tyan/s2892
> tyan/s2895
> tyan/s4880
> tyan/s4882
>
> Abuild log is completely identical with and without the patch.
>
> With this patch, the last ROMCC remainders for K8 boards are gone.
>
> Signed-off-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006 at gmx.net>
>
> Patrick, this time I want to commit the patch :-P
>    
Hah, okay.
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>



From uwe at hermann-uwe.de  Fri Apr  3 18:21:18 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Apr 2009 18:21:18 +0200
Subject: [coreboot] xmmstack
In-Reply-To: <49D5F280.9080702@gmx.net>
References: <E1LpWKX-0000zs-CV@ra.coresystems.de> <49D55971.1090801@gmx.net>
	<dd3c80060904021841l320fb99ds6c0d2f27be9af2b2@mail.gmail.com>
	<49D57192.9000409@gmx.net> <49D5DC18.3070207@coresystems.de>
	<49D5E47B.3090100@gmx.net> <20090403112208.GB25703@greenwood>
	<49D5F280.9080702@gmx.net>
Message-ID: <20090403162118.GA28506@greenwood>

On Fri, Apr 03, 2009 at 01:26:56PM +0200, Carl-Daniel Hailfinger wrote:
> AFAICS xmmstack is an external tool like gcc. We don't care about the
> license of gcc because gcc is not incorporated into the final binary.

Ah, I see. If it's an external tool (not meant to be linked against
other coreboot code) then there's no problem.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From stepan at coresystems.de  Fri Apr  3 18:24:44 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 03 Apr 2009 18:24:44 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D636AC.6090203@gmx.net>
References: <49D56D64.3000303@gmx.net> <49D60380.4040207@gmx.net>
	<49D636AC.6090203@gmx.net>
Message-ID: <49D6384C.4070608@coresystems.de>

On 03.04.2009 18:17 Uhr, Carl-Daniel Hailfinger wrote:
> On 03.04.2009 14:39, Carl-Daniel Hailfinger wrote:
>   
>> On 03.04.2009 03:59, Carl-Daniel Hailfinger wrote:
>>   
>>     
>>> There are more than a dozen targets in the v2 tree which refer to ROMCC
>>> in their Config.lb but never use it. There's no point in keeping dead
>>> code around. Kill it.
>>>
>>> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
>>> tyan/s2850.
>>>
>>> Abuild build log with and without the patch is completely identical.
>>>
>>> If this patch is OK, I'll create more of the same type, hopefully making
>>> ROMCC dependencies a bit more clear for v2.
>>>
>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>   
>>>     
>>>       
>> Next step. Kill auto.c and failover.c and clean up Config.lb for
>> tyan/s2735
>> tyan/s2850
>> tyan/s2875
>> tyan/s2880
>> tyan/s2881
>> tyan/s2882
>> tyan/s2885
>> tyan/s2891
>> tyan/s2892
>> tyan/s2895
>>
>> Abuild log is completely identical with and without the patch.
>>
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>   
>>     
>
> You know the drill...
>
> arima/hdama
> ibm/e325
> ibm/e326
> iwill/dk8s2
> iwill/dk8x
> msi/ms9282
> newisys/khepri
> sunw/ultra40
> tyan/s2891
> tyan/s2892
> tyan/s2895
> tyan/s4880
> tyan/s4882
>
> Abuild log is completely identical with and without the patch.
>
> With this patch, the last ROMCC remainders for K8 boards are gone.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
> Patrick, this time I want to commit the patch :-P
>   

Acked-by: Stefan Reinauer <stepan at coresystems.de>


I guess now we can start renaming those files called
"cache_as_ram_auto.c" (and possibly even amd64_main on non-amd systems)

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From svn at coreboot.org  Fri Apr  3 18:29:35 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 18:29:35 +0200
Subject: [coreboot] [v2] r4055 - in trunk/coreboot-v2/src/mainboard:
	arima/hdama ibm/e325 ibm/e326 iwill/dk8s2 iwill/dk8x
	msi/ms9282 newisys/khepri sunw/ultra40 tyan/s2891 tyan/s2892
	tyan/s2895 tyan/s4880 tyan/s4882
Message-ID: <mailman.2932.1355071510.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-04-03 18:29:35 +0200 (Fri, 03 Apr 2009)
New Revision: 4055

Modified:
   trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
   trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c
   trunk/coreboot-v2/src/mainboard/arima/hdama/failover.c
   trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e325/failover.c
   trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e326/failover.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/failover.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/failover.c
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/failover.c
   trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb
   trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c
   trunk/coreboot-v2/src/mainboard/newisys/khepri/failover.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s4880/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s4882/failover.c
Log:
There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping
dead code around.

This patch removes ROMCC remainders from Config.lb and kills orphaned
auto.c and failover.c in the affected mainboard directories.

arima/hdama
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms9282
newisys/khepri
sunw/ultra40
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882

Abuild log is completely identical with and without the patch.

With this patch, the last ROMCC remainders for K8 boards are gone.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de> 


Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -46,8 +46,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -65,31 +63,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -100,7 +74,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -108,7 +81,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -121,24 +93,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -146,13 +110,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -161,28 +120,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,179 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-
-static void hard_reset(void)
-{
-	device_t dev;
-
-	/* Find the device */
-	dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-	
-	/* enable cf9 */
-	pci_write_config8(dev, 0x41, 0xf1);
-
-	/* reset */
-	set_bios_reset();
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	device_t dev;
-	
-	/* Find the device */
-	dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-	/* Reset */
-	set_bios_reset();
-	pci_write_config8(dev, 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-	else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "debug.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-#if 0
-	print_pci_devices();
-#endif
-	enable_smbus();
-#if 0
-	dump_spd_registers(ARRAY_SIZE(cpu), cpu);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-	
-#if 0
-	dump_pci_devices();
-#endif
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-	dump_pci_device(PCI_DEV(0, 0x18, 3));
-#endif
-
-#if 0
-	/* Check the first 1M */
-	ram_check(0x00000000, 0x000100000);
-#endif
-}

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-	unsigned nodeid;
-
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	nodeid = lapicid() & 0xf;
-
-	/* Is this a cpu only reset? */
-	if (cpu_init_detected(nodeid)) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,31 +64,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -101,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -109,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-        nodeid = lapicid() & 0xf;
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,31 +64,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -101,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -109,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-        nodeid = lapicid() & 0xf;
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -50,8 +50,6 @@
 ## ATI Rage XL framebuffering graphics driver
 dir /drivers/ati/ragexl
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -69,31 +67,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -104,7 +78,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -112,7 +85,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -125,24 +97,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -150,13 +114,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -165,28 +124,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,159 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	} else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-		k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */	
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-	
-#if 0
-	print_pci_devices();
-#endif
-
-	enable_smbus();
-
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
-	dump_pci_devices();
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-}

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,31 +64,7 @@
 end
 
 end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -101,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -109,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-        mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
 ##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,189 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-	else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_default_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-#if 0
-	print_pci_devices();
-#endif
-	enable_smbus();
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 1
-	dump_pci_devices();
-#endif
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-	/* Check all of memory */
-#if 0
-	msr_t msr;
-	msr = rdmsr(TOP_MEM);
-	print_debug("TOP_MEM: ");
-	print_debug_hex32(msr.hi);
-	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
-#endif
-#if 0
-	ram_check(0x00000000, msr.lo);
-#endif
-#if 0
-	static const struct {
-		unsigned long lo, hi;
-	} check_addrs[] = {
-		/* Check 16MB of memory @ 0*/
-		{ 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
-		/* Check 16MB of memory @ 2GB */
-		{ 0x80000000, 0x81000000 },
-#endif
-	};
-	int i;
-	for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
-		ram_check(check_addrs[i].lo, check_addrs[i].hi);
-	}
-#endif
-}

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-        unsigned nodeid;
-
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -75,8 +75,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -94,34 +92,8 @@
 end
 
 end
-else
 
 ##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-
-end
-
-##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 if USE_FALLBACK_IMAGE
@@ -131,7 +103,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript /cpu/x86/32bit/entry32.lds
        end
@@ -139,7 +110,6 @@
        if CONFIG_USE_INIT
                ldscript      /cpu/amd/car/cache_as_ram.lds
        end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -152,12 +122,6 @@
        ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -172,12 +136,10 @@
        ldscript /southbridge/nvidia/mcp55/romstrap.lds
 end
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -185,13 +147,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
        ldscript /arch/i386/lib/failover.lds
-else
-       ldscript /arch/i386/lib/failover.lds
-       mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -200,25 +157,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-# ROMCC
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static void sio_setup(void)
-{
-
-        unsigned value;
-       uint32_t dword;
-       uint8_t byte;
-
-        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-       dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-       dword |= (1<<0);
-       pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-               if (last_boot_normal()) {
-                       goto normal_image;
-               } else {
-                       goto fallback_image;
-               }
-       }
-
-       /* Is this a secondary cpu? */
-       if (!boot_cpu()) {
-               if (last_boot_normal()) {
-                       goto normal_image;
-               } else {
-                       goto fallback_image;
-               }
-       }
-
-       /* Nothing special needs to be done to find bus 0 */
-       /* Allow the HT devices to be found */
-
-       enumerate_ht_chain();
-
-       sio_setup();
-
-       /* Setup the mcp55 */
-       mcp55_enable_rom();
-
-       /* Is this a deliberate reset by the bios */
-       if (bios_reset_detected() && last_boot_normal()) {
-               goto normal_image;
-       }
-       /* This is the primary cpu how should I boot? */
-       else if (do_normal_boot()) {
-               goto normal_image;
-       }
-       else {
-               goto fallback_image;
-       }
- normal_image:
-       asm volatile ("jmp __normal_image"
-               : /* outputs */
-               : "a" (bist) /* inputs */
-               : /* clobbers */
-               );
- fallback_image:
-       return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -47,8 +47,6 @@
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 
 makerule ./auto.o
@@ -66,32 +64,7 @@
 end
 
 end
-else
- 
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -102,7 +75,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -110,7 +82,6 @@
         if CONFIG_USE_INIT
                 ldscript      /cpu/amd/car/cache_as_ram.lds
         end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -123,23 +94,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-### Should this be in the northbridge code?
-if USE_DCACHE_RAM
-else
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-if USE_DCACHE_RAM
 ##
 ## Setup Cache-As-Ram
 ##
 mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -147,13 +111,8 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
 	ldscript /arch/i386/lib/failover.lds
-else
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
 end
-end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
@@ -162,29 +121,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 initobject auto.o
 else
 mainboardinit ./auto.inc
 end
 
-else
-
-##
-## Setup RAM
-##
-
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 config chip.h
 
 # FIXME: ROM for onboard VGA

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,155 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-	else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-
-#include "sdram/generic_sdram.c"
-
-/* newisys khepri does not want the default */
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define NODE_RAM(x)                     \
-	.node_id = 0+x,                 \
-	.f0 = PCI_DEV(0, 0x18+x, 0),    \
-	.f1 = PCI_DEV(0, 0x18+x, 1),    \
-	.f2 = PCI_DEV(0, 0x18+x, 2),    \
-	.f3 = PCI_DEV(0, 0x18+x, 3)
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-		{
-			NODE_RAM(0),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-		{
-			NODE_RAM(1),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	setup_khepri_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset=ht_setup_chains_x();
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-#if 0
-	print_pci_devices();
-#endif
-	enable_smbus();
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
-	dump_pci_devices();
-#endif
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-#if 0
-	/* Check the first 1M */
-	ram_check(0x00000000, 0x000100000);
-#endif
-}

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-	unsigned nodeid;
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	nodeid=lapicid();
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -47,8 +47,6 @@
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT	
 		makerule ./auto.o
 		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -63,32 +61,6 @@
 		end
 	end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -99,7 +71,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -107,9 +78,7 @@
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
-
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
@@ -121,12 +90,6 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -141,14 +104,10 @@
 	ldscript /southbridge/nvidia/ck804/romstrap.lds
 end
 
-
-
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -157,34 +116,17 @@
 ###
 if USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
-	if USE_DCACHE_RAM
-	else
-	        mainboardinit ./failover.inc
-	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,198 +0,0 @@
-#define ASSEMBLY 1
- 
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-#include <cpu/amd/model_fxx_rev.h>
-//#define K8_HT_FREQ_1G_SUPPORT 1
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_msr.h>
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-static void hard_reset(void)
-{
-        set_bios_reset();
-
-        /* full reset */
-	outb(0x0a, 0x0cf9);
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        set_bios_reset();
-#if 1
-        /* link reset */
-	outb(0x02, 0x0cf9);
-        outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-        
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void sio_gpio_setup(void){
-
-	unsigned value;
-
-//	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
-
-#if 1
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
-	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-#endif
-	
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-
-#include "northbridge/amd/amdk8/raminit.c"
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else
-        #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* maybe does not want the default */
-#include "resourcemap.c"
-
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 2
-#define CK804B_BUSN 0x80
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-
-//set GPIO to input mode
-#define CK804_MB_SETUP \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-		
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-        int needs_reset;
-
-        if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-        }
-
-	// post_code(0x32);
-
-        lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-	
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	sio_gpio_setup();
-
-        setup_ultra40_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chains_x();
-
-	needs_reset |= ck804_early_setup_x();	
-
-       	if (needs_reset) {
-               	print_info("ht reset -\r\n");
-               	soft_reset();
-       	}
-
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-
-}

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,118 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-
-#include <device/pnp_def.h>  
-
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-#define SUPERIO_COM1_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-#define SUPERIO_COM1_IO_BASE 0x3f8
-
-static void sio_setup(void)
-{
-        
-        unsigned value;
-	uint32_t dword;
-	uint8_t byte;
-
-        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);  
-
-        byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
-        pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-	
-	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
-	dword |= (1<<29)|(1<<0);  
-	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if  1
-        lpc47b397_enable_serial(SUPERIO_COM1_DEV, SUPERIO_COM1_IO_BASE);
-
-#if 0
-/* what's this?
-	value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
-	value &= 0xbf;
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-*/
-#endif
-#endif
-
-}
-
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-
-static unsigned long main(unsigned long bist)
-{
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	
-	enumerate_ht_chain();
-
-	sio_setup();
-
-	/* Setup the ck804 */
-	ck804_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -63,8 +63,6 @@
 	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
 end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 	makerule ./auto.o
 		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -79,32 +77,6 @@
 	end
 end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -115,7 +87,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
 	end
@@ -123,7 +94,6 @@
 	if CONFIG_USE_INIT
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -136,12 +106,6 @@
 	ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -156,12 +120,10 @@
 	ldscript /southbridge/nvidia/ck804/romstrap.lds
 end
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -170,10 +132,6 @@
 ###
 if USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
-	if USE_DCACHE_RAM
-	else
-		mainboardinit ./failover.inc
-	end
 end
 
 ###
@@ -183,25 +141,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -63,8 +63,6 @@
 	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
 end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 	makerule ./auto.o
 		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -79,32 +77,6 @@
 	end
 end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -115,7 +87,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
 	end
@@ -123,7 +94,6 @@
 	if CONFIG_USE_INIT
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -136,12 +106,6 @@
 	ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -156,12 +120,10 @@
 	ldscript /southbridge/nvidia/ck804/romstrap.lds
 end
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -169,12 +131,7 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
 		ldscript /arch/i386/lib/failover.lds
-	else
-		ldscript /arch/i386/lib/failover.lds
-		mainboardinit ./failover.inc
-	end
 end
 
 ###
@@ -184,25 +141,12 @@
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -72,8 +72,6 @@
 	#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
 end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
 	makerule ./auto.o
 		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -88,32 +86,6 @@
 	end
 end
 
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -131,7 +103,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
 	if CONFIG_USE_INIT
 		ldscript /cpu/x86/32bit/entry32.lds
 	end
@@ -139,7 +110,6 @@
 	if CONFIG_USE_INIT
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -162,12 +132,6 @@
     end
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -189,12 +153,10 @@
 	end
 end
 
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -203,42 +165,23 @@
 ###
 if HAVE_FAILOVER_BOOT
 	if USE_FAILOVER_IMAGE
-		if USE_DCACHE_RAM
 			ldscript /arch/i386/lib/failover_failover.lds
-		end
 	end
 else
 	if USE_FALLBACK_IMAGE
-		if USE_DCACHE_RAM
 			ldscript /arch/i386/lib/failover.lds
-		else
-			mainboardinit ./failover.inc
-		end
 	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-	# ROMCC
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -43,7 +43,6 @@
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
 
 	if CONFIG_USE_INIT
 
@@ -61,44 +60,7 @@
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 			end
 	end
-else
 
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-	        depends "$(MAINBOARD)/failover.c ../romcc"
-        	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	##
-	## Setup RAM
-	##
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-	mainboardinit arch/i386/lib/jmp_auto_out.inc
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -109,7 +71,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -117,9 +78,7 @@
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
-
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
@@ -131,25 +90,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -157,32 +107,18 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
 		ldscript /arch/i386/lib/failover.lds
-	else
-       		ldscript /arch/i386/lib/failover.lds
-	        mainboardinit ./failover.inc
-	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-
-	# ROMCC
-	mainboardinit arch/i386/lib/jmp_auto.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,233 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
-        unsigned device=(ctrl->channel0[0])>>8;
-        smbus_write_byte(SMBUS_HUB , 0x01, device);
-        smbus_write_byte(SMBUS_HUB , 0x03, 0);
-}
-#if 0
-static inline void change_i2c_mux(unsigned device)
-{
-#define SMBUS_HUB 0x18
-        smbus_write_byte(SMBUS_HUB , 0x01, device);
-        smbus_write_byte(SMBUS_HUB , 0x03, 0);
-}
-#endif
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-
-#define THIRD_CPU  1 
-#define FOURTH_CPU 1 
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
-
-#define RC0 ((1<<1)<<8)
-#define RC1 ((1<<2)<<8)
-#define RC2 ((1<<3)<<8)
-#define RC3 ((1<<4)<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-        
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
-                        .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
-                },
-#endif
-#if SECOND_CPU
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { RC1|DIMM0, 0 , 0, 0 },
-                        .channel1 = { RC1|DIMM1, 0, 0, 0 },
-
-                },
-#endif
-
-#if THIRD_CPU
-                {
-                        .node_id = 2,
-                        .f0 = PCI_DEV(0, 0x1a, 0),
-                        .f1 = PCI_DEV(0, 0x1a, 1),
-                        .f2 = PCI_DEV(0, 0x1a, 2),
-                        .f3 = PCI_DEV(0, 0x1a, 3),
-                        .channel0 = { RC2|DIMM0, 0, 0, 0 },
-                        .channel1 = { RC2|DIMM1, 0, 0, 0 },
-
-                },
-#endif
-#if FOURTH_CPU
-                {
-                        .node_id = 3,
-                        .f0 = PCI_DEV(0, 0x1b, 0),
-                        .f1 = PCI_DEV(0, 0x1b, 1),
-                        .f2 = PCI_DEV(0, 0x1b, 2),
-                        .f3 = PCI_DEV(0, 0x1b, 3),
-                        .channel0 = { RC3|DIMM0, 0, 0, 0 },
-                        .channel1 = { RC3|DIMM1, 0, 0, 0 },
-
-                },
-#endif
-	};
-	int i;
-        int needs_reset;
-
-        if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-        }
-
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_s4880_resource_map();
-
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chains_x();
-	
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-#if 0
-	dump_pci_devices();
-#endif
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,69 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        /* Make cerain my local apic is useable */
-        enable_lapic();
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-               if (last_boot_normal()) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-        /* Is this a secondary cpu? */
-        if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb	2009-04-03 16:29:35 UTC (rev 4055)
@@ -43,7 +43,6 @@
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
 
 	if CONFIG_USE_INIT
 
@@ -61,44 +60,7 @@
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 			end
 	end
-else
 
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-        	depends "$(MAINBOARD)/failover.c ../romcc"
-	        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./failover.inc
-	        depends "$(MAINBOARD)/failover.c ../romcc"
-        	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-	end
-
-	makerule ./auto.E
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	makerule ./auto.inc
-        	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	        action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-	end
-
-	##
-	## Setup RAM
-	##
-	mainboardinit cpu/x86/fpu/enable_fpu.inc
-	mainboardinit cpu/x86/mmx/enable_mmx.inc
-	mainboardinit cpu/x86/sse/enable_sse.inc
-	mainboardinit ./auto.inc
-	mainboardinit cpu/x86/sse/disable_sse.inc
-	mainboardinit cpu/x86/mmx/disable_mmx.inc
-	mainboardinit arch/i386/lib/jmp_auto_out.inc
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -109,7 +71,6 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
         if CONFIG_USE_INIT
                 ldscript /cpu/x86/32bit/entry32.lds
         end
@@ -117,9 +78,7 @@
         if CONFIG_USE_INIT
                 ldscript /cpu/amd/car/cache_as_ram.lds
         end
-end
 
-
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
@@ -131,25 +90,16 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-if USE_DCACHE_RAM
-else
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
-
-if USE_DCACHE_RAM
 	##
 	## Setup Cache-As-Ram
 	##
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup 
@@ -157,32 +107,18 @@
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
 		ldscript /arch/i386/lib/failover.lds
-	else
-       		ldscript /arch/i386/lib/failover.lds
-	        mainboardinit ./failover.inc
-	end
 end
 
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
 	if CONFIG_USE_INIT
 		initobject auto.o
 	else
 		mainboardinit ./auto.inc
 	end
 
-else
-
-	# ROMCC
-	mainboardinit arch/i386/lib/jmp_auto.inc
-
-end
-
 ##
 ## Include the secondary Configuration files 
 ##

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,233 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-        
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue; 
-                }       
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {       
-                        return (config_map >> 16) & 0xff;
-                }       
-        }       
-        return 0;
-}       
-
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
-	int ret,i;
-        unsigned device=(ctrl->channel0[0])>>8;
-	/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-	i=2;
-	do {
-	        ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-	} while ((ret!=0) && (i-->0));
-
-        smbus_write_byte(SMBUS_HUB, 0x03, 0);
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#if 0           
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else                   
-        #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-
-#define THIRD_CPU  1 
-#define FOURTH_CPU 1 
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
-
-#define RC0 ((1<<2)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<4)<<8)
-#define RC3 ((1<<3)<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-        
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
-                        .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
-                },
-#endif
-#if SECOND_CPU
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
-                        .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
-
-                },
-#endif
-
-#if THIRD_CPU
-                {
-                        .node_id = 2,
-                        .f0 = PCI_DEV(0, 0x1a, 0),
-                        .f1 = PCI_DEV(0, 0x1a, 1),
-                        .f2 = PCI_DEV(0, 0x1a, 2),
-                        .f3 = PCI_DEV(0, 0x1a, 3),
-                        .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
-                        .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
-
-                },
-#endif
-#if FOURTH_CPU
-                {
-                        .node_id = 3,
-                        .f0 = PCI_DEV(0, 0x1b, 0),
-                        .f1 = PCI_DEV(0, 0x1b, 1),
-                        .f2 = PCI_DEV(0, 0x1b, 2),
-                        .f3 = PCI_DEV(0, 0x1b, 3),
-                        .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
-                        .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
-
-                },
-#endif
-	};
-	int i;
-        int needs_reset;
-        
-        if (bist == 0) {
-		k8_init_and_stop_secondaries();
-        }
-                        
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();    
-        console_init(); 
-                
-        /* Halt if there was a built in self test failure */
-        report_bist_failure(bist);
-	
-        setup_s4882_resource_map();
-
-        needs_reset = setup_coherent_ht_domain();
-
-        needs_reset |= ht_setup_chains_x();
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }
-	
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-	
-}

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/failover.c	2009-04-03 16:17:05 UTC (rev 4054)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/failover.c	2009-04-03 16:29:35 UTC (rev 4055)
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif  
-        
-                
-static unsigned long main(unsigned long bist)
-{       
-        
-        /* Is this a cpu only reset? */
-        if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}




From svn at coreboot.org  Fri Apr  3 18:31:02 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 18:31:02 +0200
Subject: [coreboot] [v2] r4056 - trunk/coreboot-v2/src/cpu/x86/lapic
Message-ID: <mailman.2933.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-03 18:31:01 +0200 (Fri, 03 Apr 2009)
New Revision: 4056

Modified:
   trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
Log:
drop another shadow variable (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-04-03 16:29:35 UTC (rev 4055)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-04-03 16:31:01 UTC (rev 4056)
@@ -291,14 +291,14 @@
 {
 	int timeout;
 	unsigned long send_status;
-	unsigned long lapicid;
+	unsigned long id;
 
-	lapicid = lapic_read(LAPIC_ID) >> 24;
+	id = lapic_read(LAPIC_ID) >> 24;
 
-	printk_debug("CPU %ld going down...\n", lapicid);
+	printk_debug("CPU %ld going down...\n", id);
 
 	/* send an LAPIC INIT to myself */
-	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));
+	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
 
 	/* wait for the ipi send to finish */
@@ -322,7 +322,7 @@
 
 	printk_spew("Deasserting INIT.\n");
 	/* Deassert the LAPIC INIT */
-	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));	
+	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));	
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 
 	printk_spew("Waiting for send to finish...\n");




From svn at coreboot.org  Fri Apr  3 18:33:50 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 18:33:50 +0200
Subject: [coreboot] [v2] r4057 - trunk/coreboot-v2/src/cpu/x86/smm
Message-ID: <mailman.2934.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-03 18:33:50 +0200 (Fri, 03 Apr 2009)
New Revision: 4057

Modified:
   trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c
Log:
drop unused variables in generic smm handler. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c	2009-04-03 16:31:01 UTC (rev 4056)
+++ trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c	2009-04-03 16:33:50 UTC (rev 4057)
@@ -159,10 +159,6 @@
 
 void smi_handler(u32 smm_revision)
 {
-	u8 reg8;
-	u16 pmctrl;
-	u16 pm1_sts;
-	u32 smi_sts, gpe0_sts, tco_sts;
 	unsigned int node;
 	smm_state_save_area_t state_save;
 




From info at coresystems.de  Fri Apr  3 18:40:30 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 18:40:30 +0200
Subject: [coreboot] build service results for r4053
Message-ID: <E1LpmRS-00041P-B2@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4053 to
the coreboot repository. This caused the following 
changes:

Change Log:
The attached patch tries new style compression first and runs old
style compression if the command returned an error code (happens if
you run an old lzma with the new arguments)

Tested on new-style lzma only (as I lack a build environment with
old lzma), but I tested that the old lzma returns with an error code.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=db800&vendor=amd&num=2
Compilation of amd:norwich is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=norwich&vendor=amd&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=rumba&vendor=amd&num=2
Compilation of artecgroup:dbe61 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=winnet100&vendor=bcom&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=5bcm&vendor=eaglelion&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=frontrunner&vendor=lippert&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=ms6147&vendor=msi&num=2
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=rev_a&vendor=olpc&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=tc7020&vendor=televideo&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=briq&vendor=totalimpact&num=1
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=s1846&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4053&device=epia&vendor=via&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Apr  3 18:40:45 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 18:40:45 +0200
Subject: [coreboot] [v2] r4058 - in trunk/coreboot-v2/src/mainboard:
	arima/hdama ibm/e325 ibm/e326 iwill/dk8s2 iwill/dk8x
	msi/ms9282 newisys/khepri sunw/ultra40 tyan/s4880 tyan/s4882
Message-ID: <mailman.2935.1355071510.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-04-03 18:40:44 +0200 (Fri, 03 Apr 2009)
New Revision: 4058

Removed:
   trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c
   trunk/coreboot-v2/src/mainboard/arima/hdama/failover.c
   trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c
   trunk/coreboot-v2/src/mainboard/ibm/e325/failover.c
   trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c
   trunk/coreboot-v2/src/mainboard/ibm/e326/failover.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/auto.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/failover.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/auto.c
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/failover.c
   trunk/coreboot-v2/src/mainboard/msi/ms9282/failover.c
   trunk/coreboot-v2/src/mainboard/newisys/khepri/auto.c
   trunk/coreboot-v2/src/mainboard/newisys/khepri/failover.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/auto.c
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s4880/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s4880/failover.c
   trunk/coreboot-v2/src/mainboard/tyan/s4882/auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s4882/failover.c
Log:
Fix up the incomplete commit in r4055.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Deleted: trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c	2009-04-03 16:33:50 UTC (rev 4057)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/auto.c	2009-04-03 16:40:44 UTC (rev 4058)
@@ -1,181 +0,0 @@
-#define ASSEMBLY 1
-#define DEFAULT_CONSOLE_LOGLEVEL 8
-#define MAXIMUM_CONSOLE_LOGLEVEL 8
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/nsc/pc87366/pc87366_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-	} else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "mainboard/ibm/e325/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-	pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-#if 0
-	print_pci_devices();
-#endif
-
-	setup_ibm_e325_resource_map();
-
-#if 0
-	print_debug("after setting resource\n");
-	print_pci_devices();
-#endif
-
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
-
-#if 0
-	print_debug("after ht stuff\n");
-	print_pci_devices();
-#endif
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-#if 0
-	print_pci_devices();
-#endif
-
-	enable_smbus();
-
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
-	dump_pci_devices();
-#endif
-
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-#if 0
-	/* Check the first 1M */
-	ram_check(0x00000000, 0x001000000);
-#endif
-}

Deleted: trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c	2009-04-03 16:33:50 UTC (rev 4057)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/auto.c	2009-04-03 16:40:44 UTC (rev 4058)
@@ -1,181 +0,0 @@
-#define ASSEMBLY 1
-#define DEFAULT_CONSOLE_LOGLEVEL 8
-#define MAXIMUM_CONSOLE_LOGLEVEL 8
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/nsc/pc87366/pc87366_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-	} else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
-		udelay(90);
-	}
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "mainboard/ibm/e326/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-        unsigned nodeid;
-
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-	pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-#if 0
-	print_pci_devices();
-#endif
-
-	setup_ibm_e326_resource_map();
-
-#if 0
-	print_debug("after setting resource\n");
-	print_pci_devices();
-#endif
-
-	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
-
-#if 0
-	print_debug("after ht stuff\n");
-	print_pci_devices();
-#endif
-
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-#if 0
-	print_pci_devices();
-#endif
-
-	enable_smbus();
-
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
-	dump_pci_devices();
-#endif
-
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-#if 0
-	/* Check the first 1M */
-	ram_check(0x00000000, 0x001000000);
-#endif
-}




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 18:46:28 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 18:46:28 +0200
Subject: [coreboot] [PATCH] Kill unused ROMCC dependencies
In-Reply-To: <49D6384C.4070608@coresystems.de>
References: <49D56D64.3000303@gmx.net>
	<49D60380.4040207@gmx.net>	<49D636AC.6090203@gmx.net>
	<49D6384C.4070608@coresystems.de>
Message-ID: <49D63D64.5030609@gmx.net>

On 03.04.2009 18:24, Stefan Reinauer wrote:
> On 03.04.2009 18:17 Uhr, Carl-Daniel Hailfinger wrote:
>   
>> On 03.04.2009 14:39, Carl-Daniel Hailfinger wrote:
>>   
>>     
>>> On 03.04.2009 03:59, Carl-Daniel Hailfinger wrote:
>>>   
>>>     
>>>       
>>>> There are more than a dozen targets in the v2 tree which refer to ROMCC
>>>> in their Config.lb but never use it. There's no point in keeping dead
>>>> code around. Kill it.
>>>>
>>>> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
>>>> tyan/s2850.
>>>>
>>>> Abuild build log with and without the patch is completely identical.
>>>>
>>>> If this patch is OK, I'll create more of the same type, hopefully making
>>>> ROMCC dependencies a bit more clear for v2.
>>>>
>>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>>   
>>>>     
>>>>       
>>>>         
>>> Next step. Kill auto.c and failover.c and clean up Config.lb for
>>> tyan/s2735
>>> tyan/s2850
>>> tyan/s2875
>>> tyan/s2880
>>> tyan/s2881
>>> tyan/s2882
>>> tyan/s2885
>>> tyan/s2891
>>> tyan/s2892
>>> tyan/s2895
>>>
>>> Abuild log is completely identical with and without the patch.
>>>
>>>
>>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>>   
>>>     
>>>       
>> You know the drill...
>>
>> arima/hdama
>> ibm/e325
>> ibm/e326
>> iwill/dk8s2
>> iwill/dk8x
>> msi/ms9282
>> newisys/khepri
>> sunw/ultra40
>> tyan/s2891
>> tyan/s2892
>> tyan/s2895
>> tyan/s4880
>> tyan/s4882
>>
>> Abuild log is completely identical with and without the patch.
>>
>> With this patch, the last ROMCC remainders for K8 boards are gone.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>
>> Patrick, this time I want to commit the patch :-P
>>   
>>     
>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
>   

Thanks, committed in r4055.


> I guess now we can start renaming those files called
> "cache_as_ram_auto.c" (and possibly even amd64_main on non-amd systems)
>   

Looks like a good idea, but right now I'd prefer to have an easy way to
differentiate between CAR and ROMCC targets. And it looks like the
filename does that nicely (with 4 exceptions, though).

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Fri Apr  3 19:05:28 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 03 Apr 2009 19:05:28 +0200
Subject: [coreboot] Remaining ROMCC targets
Message-ID: <49D641D8.1080403@gmx.net>

This is a list of targets using ROMCC together with the CPU type used
for ROMCC.

bcom/winnetp680 c3
jetway/j7f24 c3
via/epia c3
via/epia-cn c3
via/epia-m c3
via/pc2500e c3
asi/mb_5blmp i386
digitallogic/msm586seg i386
eaglelion/5bcm i386
emulation/qemu-x86 i386
iei/juki-511p i386
iei/nova4899r i386
lippert/frontrunner i386
technologic/ts5300 i386
abit/be6-ii_v2_0 p2
amd/rumba p2
asus/mew-am p2
asus/mew-vm p2
asus/p2b-ds p2
asus/p2b-f p2
asus/p2b p2
asus/p3b-f p2
a-trend/atc-6220 p2
a-trend/atc-6240 p2
azza/pt-6ibd p2
biostar/m6tba p2
compaq/deskpro_en_sff_p600 p2
gigabyte/ga-6bxc p2
msi/ms6119 p2
msi/ms6147 p2
msi/ms6178 p2
nec/powermate2000 p2
olpc/btest p2
olpc/rev_a p2
tyan/s1846 p2
digitallogic/adl855pc p3
rca/rm4100 p3
thomson/ip1000 p3
dell/s1850 p4
intel/jarrell p4
intel/mtarvon p4
intel/truxton p4
intel/xe7501devkit p4
supermicro/x6dai_g p4
supermicro/x6dhe_g2 p4
supermicro/x6dhe_g p4
supermicro/x6dhr_ig2 p4
supermicro/x6dhr_ig p4

Does anybody own any of these boards? If so, which?

I hope to use CAR on at least some of them.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From info at coresystems.de  Fri Apr  3 19:09:30 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 19:09:30 +0200
Subject: [coreboot] build service results for r4054
Message-ID: <E1LpmtW-0001zj-LK@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4054 to
the coreboot repository. This caused the following 
changes:

Change Log:
I thought that romfs infrastructure is done now, but there were some
issues (see buildbot).
The romfs image was always built, and sometimes broke (because of
the different image layouts) for buildrom images. After the patch, these
issues are avoided by not adding payloads to the romfs image (they
wouldn't be read anyway). Both workarounds (in buildrom code for
romfs and vice-versa) aren't very pretty, but that's what our buildsystem
requires.
As I had to create a "communication channel" (via the romfs-support
files), I took the chance to also use it for compression
information, so if you configure lzma support, you'll get lzma
compressed payloads in romfs.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4054&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 has been fixed
Compilation of abit:be6-ii_v2_0 has been fixed
Compilation of advantech:pcm-5820 has been fixed
Compilation of amd:db800 has been fixed
Compilation of amd:norwich has been fixed
Compilation of amd:rumba has been fixed
Compilation of artecgroup:dbe61 has been fixed
Compilation of asi:mb_5blgp has been fixed
Compilation of asi:mb_5blmp has been fixed
Compilation of asus:p2b has been fixed
Compilation of asus:p2b-ds has been fixed
Compilation of asus:p2b-f has been fixed
Compilation of asus:p3b-f has been fixed
Compilation of axus:tc320 has been fixed
Compilation of azza:pt-6ibd has been fixed
Compilation of bcom:winnet100 has been fixed
Compilation of biostar:m6tba has been fixed
Compilation of compaq:deskpro_en_sff_p600 has been fixed
Compilation of digitallogic:msm800sev has been fixed
Compilation of eaglelion:5bcm has been fixed
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4054&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of gigabyte:ga-6bxc has been fixed
Compilation of iei:nova4899r has been fixed
Compilation of iei:pcisa-lx-800-r10 has been fixed
Compilation of lippert:frontrunner has been fixed
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4054&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 has been fixed
Compilation of msi:ms6147 has been fixed
Compilation of olpc:btest has been fixed
Compilation of olpc:rev_a has been fixed
Compilation of technologic:ts5300 has been fixed
Compilation of televideo:tc7020 has been fixed
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4054&device=briq&vendor=totalimpact&num=1
Compilation of tyan:s1846 has been fixed
Compilation of via:epia has been fixed


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Fri Apr  3 19:31:25 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 3 Apr 2009 10:31:25 -0700
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <49D641D8.1080403@gmx.net>
References: <49D641D8.1080403@gmx.net>
Message-ID: <13426df10904031031h3127a3b7je5fff12c76fa52d2@mail.gmail.com>

On Fri, Apr 3, 2009 at 10:05 AM, Carl-Daniel Hailfinger


> digitallogic/msm586seg i386

That's me IIRC. I don't know if I have these around.

> emulation/qemu-x86 i386

I'm going to rip romcc out of this, so just hang on.


> technologic/ts5300 i386

That was me. I don't have any left.


> amd/rumba p2

That was me, but it's a dead product, we could safely remove it.



> olpc/btest p2
> olpc/rev_a p2

Those first came from me, let's not to anything just yet.


> digitallogic/adl855pc p3

This should be removed. It never worked.

> dell/s1850 p4
This should be removed. It never worked.

> I hope to use CAR on at least some of them.

Car should be fine on all the geode targets of course.

ron



From info at coresystems.de  Fri Apr  3 19:42:11 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 19:42:11 +0200
Subject: [coreboot] build service results for r4055
Message-ID: <E1LpnP9-0000Na-Hl@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "hailfinger" checked in revision 4055 to
the coreboot repository. This caused the following 
changes:

Change Log:
There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping
dead code around.

This patch removes ROMCC remainders from Config.lb and kills orphaned
auto.c and failover.c in the affected mainboard directories.

arima/hdama
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms9282
newisys/khepri
sunw/ultra40
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882

Abuild log is completely identical with and without the patch.

With this patch, the last ROMCC remainders for K8 boards are gone.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4055&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4055&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4055&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4055&device=briq&vendor=totalimpact&num=1


If something broke during this checkin please be a pain 
in hailfinger's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Fri Apr  3 20:13:50 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 20:13:50 +0200
Subject: [coreboot] build service results for r4056
Message-ID: <E1Lpntm-0006WF-VM@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4056 to
the coreboot repository. This caused the following 
changes:

Change Log:
drop another shadow variable (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4056&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4056&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4056&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4056&device=briq&vendor=totalimpact&num=1


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Fri Apr  3 20:19:18 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 20:19:18 +0200
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <49D641D8.1080403@gmx.net>
References: <49D641D8.1080403@gmx.net>
Message-ID: <20090403181918.1605.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> via/epia c3

I might be able to test on it, I had one but have sold it to a
friend who is using it.


> via/epia-cn c3

I have this right here. It has a C7.


//Peter



From joe at settoplinux.org  Fri Apr  3 20:20:24 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 03 Apr 2009 14:20:24 -0400
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <49D641D8.1080403@gmx.net>
References: <49D641D8.1080403@gmx.net>
Message-ID: <cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>




On Fri, 03 Apr 2009 19:05:28 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> This is a list of targets using ROMCC together with the CPU type used
> for ROMCC.
> 
> bcom/winnetp680 c3
> jetway/j7f24 c3
> via/epia c3
> via/epia-cn c3
> via/epia-m c3
> via/pc2500e c3
> asi/mb_5blmp i386
> digitallogic/msm586seg i386
> eaglelion/5bcm i386
> emulation/qemu-x86 i386
> iei/juki-511p i386
> iei/nova4899r i386
> lippert/frontrunner i386
> technologic/ts5300 i386
> abit/be6-ii_v2_0 p2
> amd/rumba p2
> asus/mew-am p2
> asus/mew-vm p2
> asus/p2b-ds p2
> asus/p2b-f p2
> asus/p2b p2
> asus/p3b-f p2
> a-trend/atc-6220 p2
> a-trend/atc-6240 p2
> azza/pt-6ibd p2
> biostar/m6tba p2
> compaq/deskpro_en_sff_p600 p2
> gigabyte/ga-6bxc p2
> msi/ms6119 p2
> msi/ms6147 p2
> msi/ms6178 p2
> nec/powermate2000 p2
> olpc/btest p2
> olpc/rev_a p2
> tyan/s1846 p2
> digitallogic/adl855pc p3
> rca/rm4100 p3
> thomson/ip1000 p3
> dell/s1850 p4
> intel/jarrell p4
> intel/mtarvon p4
> intel/truxton p4
> intel/xe7501devkit p4
> supermicro/x6dai_g p4
> supermicro/x6dhe_g2 p4
> supermicro/x6dhe_g p4
> supermicro/x6dhr_ig2 p4
> supermicro/x6dhr_ig p4
> 
> Does anybody own any of these boards? If so, which?
> 
> I hope to use CAR on at least some of them.
> 
Yes,
rca/rm4100 p3
thomson/ip1000 p3
Are my doings. I would love to see them using CAR instead of ROMCC, but I
wouldn't even know where to start....

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From info at coresystems.de  Fri Apr  3 20:46:53 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 20:46:53 +0200
Subject: [coreboot] build service results for r4057
Message-ID: <E1LpoPl-00057b-96@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4057 to
the coreboot repository. This caused the following 
changes:

Change Log:
drop unused variables in generic smm handler. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4057&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4057&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4057&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4057&device=briq&vendor=totalimpact&num=1


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From corey.osgood at gmail.com  Fri Apr  3 21:08:17 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 3 Apr 2009 15:08:17 -0400
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
Message-ID: <dd3c80060904031208w4b9d74dr4d43f95e81b6fdda@mail.gmail.com>

I'll test anything on the jetway j7f2, as long as you don't mind waiting for
a weekend.

-Corey

On Fri, Apr 3, 2009 at 2:20 PM, Joseph Smith <joe at settoplinux.org> wrote:

>
>
>
> On Fri, 03 Apr 2009 19:05:28 +0200, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> > This is a list of targets using ROMCC together with the CPU type used
> > for ROMCC.
> >
> > bcom/winnetp680 c3
> > jetway/j7f24 c3
> > via/epia c3
> > via/epia-cn c3
> > via/epia-m c3
> > via/pc2500e c3
> > asi/mb_5blmp i386
> > digitallogic/msm586seg i386
> > eaglelion/5bcm i386
> > emulation/qemu-x86 i386
> > iei/juki-511p i386
> > iei/nova4899r i386
> > lippert/frontrunner i386
> > technologic/ts5300 i386
> > abit/be6-ii_v2_0 p2
> > amd/rumba p2
> > asus/mew-am p2
> > asus/mew-vm p2
> > asus/p2b-ds p2
> > asus/p2b-f p2
> > asus/p2b p2
> > asus/p3b-f p2
> > a-trend/atc-6220 p2
> > a-trend/atc-6240 p2
> > azza/pt-6ibd p2
> > biostar/m6tba p2
> > compaq/deskpro_en_sff_p600 p2
> > gigabyte/ga-6bxc p2
> > msi/ms6119 p2
> > msi/ms6147 p2
> > msi/ms6178 p2
> > nec/powermate2000 p2
> > olpc/btest p2
> > olpc/rev_a p2
> > tyan/s1846 p2
> > digitallogic/adl855pc p3
> > rca/rm4100 p3
> > thomson/ip1000 p3
> > dell/s1850 p4
> > intel/jarrell p4
> > intel/mtarvon p4
> > intel/truxton p4
> > intel/xe7501devkit p4
> > supermicro/x6dai_g p4
> > supermicro/x6dhe_g2 p4
> > supermicro/x6dhe_g p4
> > supermicro/x6dhr_ig2 p4
> > supermicro/x6dhr_ig p4
> >
> > Does anybody own any of these boards? If so, which?
> >
> > I hope to use CAR on at least some of them.
> >
> Yes,
> rca/rm4100 p3
> thomson/ip1000 p3
> Are my doings. I would love to see them using CAR instead of ROMCC, but I
> wouldn't even know where to start....
>
> --
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From info at coresystems.de  Fri Apr  3 21:13:38 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 21:13:38 +0200
Subject: [coreboot] build service results for r4058
Message-ID: <E1Lpope-0002vw-2f@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "hailfinger" checked in revision 4058 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix up the incomplete commit in r4055.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4058&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4058&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4058&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4058&device=briq&vendor=totalimpact&num=1


If something broke during this checkin please be a pain 
in hailfinger's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From ward at gnu.org  Fri Apr  3 21:33:15 2009
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 3 Apr 2009 15:33:15 -0400
Subject: [coreboot] Fix some PCI issues on M57SLI v2
In-Reply-To: <200904022201.41702.harald.gutmann@gmx.net>
References: <200903241854.53171.harald.gutmann@gmx.net>
	<20090331155740.GA29619@localdomain>
	<200904020022.36806.harald.gutmann@gmx.net>
	<200904022201.41702.harald.gutmann@gmx.net>
Message-ID: <20090403193315.GA7651@localdomain>

On Thu, Apr 02, 2009 at 10:01:36PM +0200, Harald Gutmann wrote:
> The last patch had a mistake somewhere because patch complains about a malform 
> patch format.
> 
> This one is the same, and just comments have been modified slightly.

OK, so this one makes the second (black) pcie x16 slot happy:

[    6.126711] 0000:02:00.0: eth2: (PCI Express:2.5GB/s:Width x4)
00:15:17:0b:d4:9e
[    6.128034] 0000:02:00.0: eth2: Intel(R) PRO/1000 Network Connection
[    6.132110] 0000:02:00.0: eth2: MAC: 0, PHY: 4, PBA No: d50868-001
[    6.136087] e1000e 0000:02:00.1: setting latency timer to 64
[    6.318689] 0000:02:00.1: eth3: (PCI Express:2.5GB/s:Width x4)
00:15:17:0b:d4:9f
[    6.320033] 0000:02:00.1: eth3: Intel(R) PRO/1000 Network Connection
[    6.324106] 0000:02:00.1: eth3: MAC: 0, PHY: 4, PBA No: d50868-001

I tested by copying a large (400M) file at wirespeed from both of those interfaces.
No problems.

I also have an old 3com nic in this machine, in one of the PCI slots (the one
closest to the edge). I also copied that large file from that nic, without
problems.

However, I got this after having the machine up for a while:

[  999.664992] Uhhuh. NMI received for unknown reason 00.
[  999.665144] Uhhuh. NMI received for unknown reason a1.
[  999.665147] You have some hardware problem, likely on the PCI bus.
[  999.665149] Dazed and confused, but trying to continue
[  999.667309] Do you have a strange power saving mode enabled?
[  999.667309] Dazed and confused, but trying to continue

This was right after I did 

  cat /proc/interrupts

a couple times - but that may have been a coincidence.

Ideas?

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From svn at coreboot.org  Fri Apr  3 22:14:59 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  3 Apr 2009 22:14:59 +0200
Subject: [coreboot] [v2] r4059 - trunk/coreboot-v2/src/arch/ppc/include
Message-ID: <mailman.2936.1355071510.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-03 22:14:59 +0200 (Fri, 03 Apr 2009)
New Revision: 4059

Modified:
   trunk/coreboot-v2/src/arch/ppc/include/stdint.h
Log:
Add u64 typedef to ppc (trivial)

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/src/arch/ppc/include/stdint.h
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/include/stdint.h	2009-04-03 16:40:44 UTC (rev 4058)
+++ trunk/coreboot-v2/src/arch/ppc/include/stdint.h	2009-04-03 20:14:59 UTC (rev 4059)
@@ -51,5 +51,6 @@
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
+typedef uint64_t u64;
 
 #endif /* PPC_STDINT_H */




From info at coresystems.de  Fri Apr  3 22:36:08 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 03 Apr 2009 22:36:08 +0200
Subject: [coreboot] build service results for r4059
Message-ID: <E1Lpq7U-0000DP-HS@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4059 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add u64 typedef to ppc (trivial)

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4059&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4059&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4059&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4059&device=briq&vendor=totalimpact&num=1


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Fri Apr  3 23:03:24 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 3 Apr 2009 14:03:24 -0700
Subject: [coreboot] changes to romfs for expansion rom loading
Message-ID: <13426df10904031403n4e9ae74fvabb161c21665010@mail.gmail.com>

attached.

ron
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From mylesgw at gmail.com  Fri Apr  3 23:40:53 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 3 Apr 2009 15:40:53 -0600
Subject: [coreboot] changes to romfs for expansion rom loading
In-Reply-To: <13426df10904031403n4e9ae74fvabb161c21665010@mail.gmail.com>
References: <13426df10904031403n4e9ae74fvabb161c21665010@mail.gmail.com>
Message-ID: <2831fecf0904031440m4062780bg57e19b62f04e52e@mail.gmail.com>

On Fri, Apr 3, 2009 at 3:03 PM, ron minnich <rminnich at gmail.com> wrote:
> attached.

 	if (romfs_decompress(ntohl(orom->compression),
-			     ((unsigned char *) orom) +
-			     sizeof(struct romfs_optionrom),
+			     (void *) src,
 			     (void *) dest,
 			     ntohl(orom->len)))
 		return -1;

It looks like you missed a couple of return statements.  This one
above was supposed to return NULL and the next one dest?

With that fixed:
Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles



From mjt at nysv.org  Fri Apr  3 23:57:26 2009
From: mjt at nysv.org (Markus Törnqvist)
Date: Sat, 4 Apr 2009 00:57:26 +0300
Subject: [coreboot] VIA Epia-MII CF question
Message-ID: <20090403215726.GR638@nysv.org>

Hi again!

Another point from http://www.coreboot.org/VIA_EPIA-MII
is the need to recreate the initrd.

When I install the system with Ubuntu's 2.6.24-22-generic kernel
and initrd, the installation environment recognizes the cf
as ata3.

There it works.

When I boot through FILO, using the below line, no such luck.

    CONFIG_AUTOBOOT_FILE="hde1:/vmlinuz initrd=/initrd.img root=/dev/sdb1"

The wiki "lets me" either use the CF slot as standard ide or through
pcmcia-utils.

This standard-ide approach, as said, did not work.

Is the wiki wrong?

Can there be something wrong with FILO that would cause this
ata3 not found?

PS:

After ata1/ata2 detection, I get dropped into an initramfs shell,
missing the root device node.

I couldn't find anything about pcmcia-utils in the initrd, which would
screw the bus up.

I then created a modified initrd with yenta_socket and friends, and
pata_pcmcia didn't not get automatically installed.

On manual installation of everything that was involved in the installation,
like pata_pcmcia and whatever, nothing happened. (!)

Anything?

Thanks!

-- 
mjt




From peter at stuge.se  Fri Apr  3 23:58:00 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Apr 2009 23:58:00 +0200
Subject: [coreboot] Name change for romfs
Message-ID: <20090403215800.2751.qmail@stuge.se>

Is someone owning this issue?

If not, will anything else happen with the code this weekend?


Thanks

//Peter



From stepan at coresystems.de  Sat Apr  4 00:21:52 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 04 Apr 2009 00:21:52 +0200
Subject: [coreboot] Name change for romfs
In-Reply-To: <20090403215800.2751.qmail@stuge.se>
References: <20090403215800.2751.qmail@stuge.se>
Message-ID: <49D68C00.5040403@coresystems.de>

Peter Stuge wrote:
> Is someone owning this issue?
>
>   
Yes, Jordan wrote the code, he should decide. That's how we handled such
cases before.

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Sat Apr  4 00:23:34 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 00:23:34 +0200
Subject: [coreboot] [v2] r4060 - in trunk/coreboot-v2/src: include lib
Message-ID: <mailman.2937.1355071510.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-04-04 00:23:34 +0200 (Sat, 04 Apr 2009)
New Revision: 4060

Modified:
   trunk/coreboot-v2/src/include/romfs.h
   trunk/coreboot-v2/src/lib/romfs.c
Log:
These are some cleanups and changes. These are build and boot tested on qemu.
Some changes for option roms: 
- don't make users pick the name. Names for option roms are in the v3-defined
format of pci%04x,%04x.rom with the vendor and device id filling in the 
%04x. 
- users pass in vendor and device id. 
- users pass in a dest. If the dest is 0, the address of the ROM image in 
FLASH is returned. If the address is non-zero, then the decmpressor is called,
and it will make sure the ROM image is copied to the destination (even 
in the uncompressed case).

And some type and print cleanup. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>




Modified: trunk/coreboot-v2/src/include/romfs.h
===================================================================
--- trunk/coreboot-v2/src/include/romfs.h	2009-04-03 20:14:59 UTC (rev 4059)
+++ trunk/coreboot-v2/src/include/romfs.h	2009-04-03 22:23:34 UTC (rev 4060)
@@ -162,8 +162,7 @@
 void * romfs_load_stage(const char *name);
 int romfs_execute_stage(const char *name);
 void * romfs_get_file(const char *name);
-int romfs_load_optionrom(const char *name, u32 dest);
-
+void *romfs_load_optionrom(u16 vendor, u16 device, void * dest);
 int run_address(void *f);
 
 #endif

Modified: trunk/coreboot-v2/src/lib/romfs.c
===================================================================
--- trunk/coreboot-v2/src/lib/romfs.c	2009-04-03 20:14:59 UTC (rev 4059)
+++ trunk/coreboot-v2/src/lib/romfs.c	2009-04-03 22:23:34 UTC (rev 4060)
@@ -73,7 +73,7 @@
 {
 	struct romfs_header *header;
 
-	unsigned long ptr = *((unsigned long *) ROMFS_HEADPTR_ADDR);
+	void *ptr = (void *)*((unsigned long *) ROMFS_HEADPTR_ADDR);
 	printk_debug("Check ROMFS header at %p\n", ptr);
 	header = (struct romfs_header *) ptr;
 
@@ -130,22 +130,39 @@
 	return (void *) ROMFS_SUBHEADER(file);
 }
 
-int romfs_load_optionrom(const char *name, u32 dest)
+void *romfs_load_optionrom(u16 vendor, u16 device, void * dest)
 {
-	struct romfs_optionrom *orom = (struct romfs_optionrom *)
+	char name[17];
+	struct romfs_optionrom *orom;
+	u8 *src;
+
+	sprintf(name,"pci%04x,%04x.rom", vendor, device);
+
+	orom = (struct romfs_optionrom *)
 		romfs_find_file(name, ROMFS_TYPE_OPTIONROM);
 
 	if (orom == NULL)
-		return -1;
+		return NULL;
 
+	/* They might have specified a dest address. If so, we can decompress. 
+	 * If not, there's not much hope of decompressing or relocating the rom.
+	 * in the common case, the expansion rom is uncompressed, we
+	 * pass 0 in for the dest, and all we have to do is find the rom and 
+	 * return a pointer to it. 
+ 	 */
+
+	src = ((unsigned char *) orom) + sizeof(struct romfs_optionrom);
+
+	if (! dest)
+		return src;
+
 	if (romfs_decompress(ntohl(orom->compression),
-			     ((unsigned char *) orom) +
-			     sizeof(struct romfs_optionrom),
-			     (void *) dest,
+			     src,
+			     dest,
 			     ntohl(orom->len)))
-		return -1;
+		return NULL;
 
-	return 0;
+	return dest;
 }
 
 void * romfs_load_payload(struct lb_memory *lb_mem, const char *name)




From rminnich at gmail.com  Sat Apr  4 00:24:27 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 3 Apr 2009 15:24:27 -0700
Subject: [coreboot] Name change for romfs
In-Reply-To: <49D68C00.5040403@coresystems.de>
References: <20090403215800.2751.qmail@stuge.se>
	<49D68C00.5040403@coresystems.de>
Message-ID: <13426df10904031524l400eb948sdb5ac4fa54021828@mail.gmail.com>

On Fri, Apr 3, 2009 at 3:21 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
> Peter Stuge wrote:
>> Is someone owning this issue?
>>
>>
> Yes, Jordan wrote the code, he should decide. That's how we handled such
> cases before.
>
> Stefan
>

Jordan, don't know if you saw the discussion, one possibility was to
change to cbfs (coreboot fs)

ron



From rminnich at gmail.com  Sat Apr  4 00:24:49 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 3 Apr 2009 15:24:49 -0700
Subject: [coreboot] changes to romfs for expansion rom loading
In-Reply-To: <2831fecf0904031440m4062780bg57e19b62f04e52e@mail.gmail.com>
References: <13426df10904031403n4e9ae74fvabb161c21665010@mail.gmail.com>
	<2831fecf0904031440m4062780bg57e19b62f04e52e@mail.gmail.com>
Message-ID: <13426df10904031524q32b05e5gccf24fe4a5f0c843@mail.gmail.com>

r4060

thanks

ron



From c-d.hailfinger.devel.2006 at gmx.net  Sat Apr  4 00:26:19 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 04 Apr 2009 00:26:19 +0200
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
Message-ID: <49D68D0B.1010800@gmx.net>

On 03.04.2009 20:20, Joseph Smith wrote:
>
> On Fri, 03 Apr 2009 19:05:28 +0200, Carl-Daniel Hailfinger wrote:
>   
>> This is a list of targets using ROMCC together with the CPU type used
>> for ROMCC.
>>
>>     
> rca/rm4100 p3
> thomson/ip1000 p3
> Are my doings. I would love to see them using CAR instead of ROMCC, but I
> wouldn't even know where to start....
>   

Great. Will a bad reflash hurt you?

What you need to try this one out:
- a POST card or another way to fetch POST codes.
- tell me whether POST works by default or you need special setup.
- a will to try out v3 with some patches

The idea is to test the v3 intel CAR code which has not been on real
hardware yet, but it is a much cleaner and more readable implementation
compared to v2. I'm hoping we don't need chipset specific stuff for POST
to work.

I need info on the cache size of your processor, though. Unreliable CAR
is not nearly as much fun as reliable CAR.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From patrick at georgi-clan.de  Sat Apr  4 00:36:36 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 04 Apr 2009 00:36:36 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds the
	romtool utility
Message-ID: <49D68F74.40100@georgi-clan.de>

Hi,

right now, we still have one victim to the romfs change in the build 
test, the first board in the list. Concurrent build, absolute paths and 
make's inability to combine these two unusual traits of a makefile come 
into play.
The following patch fixes that, and creates a romtool per-build (even 
though that should not be necessary).
Whitespace might be off, I can do a commit tomorrow, if I get an ack.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Index: util/newconfig/config.g
===================================================================
--- util/newconfig/config.g     (Revision 4059)
+++ util/newconfig/config.g     (Arbeitskopie)
@@ -2225,13 +2225,15 @@
         writemakefileheader(file, makefilepath)

         # main rule
-       file.write("\nall: romtool")
+       file.write("\nall: ")
         for i in buildroms:
                 file.write(" %sfs" % i.name)
         file.write("\n\n")

         # romtool rules
-       file.write("\nromtool:\n\tcd $(TOP)/util/romtool; make\n")
+       file.write("\nromtool:\n\t$(MAKE) -C $(TOP)/util/romtool clean 
all\n\tmkdir -p tools\n")
+       file.write("\tcp $(TOP)/util/romtool/tools/rom-mkpayload 
$(TOP)/util/romtool/tools/rom-mkstage tools\n\tcp 
$(TOP)/util/romtool/romtool romtool\n")
+       file.write("\t$(MAKE) -C $(TOP)/util/romtool clean\n")

         file.write("include Makefile.settings\n\n")
         for i, o in romimages.items():
@@ -2268,15 +2270,15 @@

         romsize = getoption("ROM_SIZE", image)
         # i.name? That can not be right, can it?
-       file.write("%sfs: %s $(TOP)/util/romtool/romtool\n" 
%(i.name,i.name));
+       file.write("%sfs: %s romtool\n" %(i.name,i.name));
         file.write("\trm -f coreboot.romfs\n");
-       file.write("\t$(TOP)/util/romtool/romtool %sfs create %s %s 
%s.bootblock\n" % (i.name, romsize, bootblocksize, i.name))
+       file.write("\t./romtool %sfs create %s %s %s.bootblock\n" % 
(i.name, romsize, bootblocksize, i.name))
         for i in buildroms:
                 for j in i.roms:
                         #failover is a hack that will go away soon.
                         if (j != "failover") and (rommapping[j] != 
"/dev/null"):
-                               file.write("\tif [ -f %s/romfs-support 
]; then $(TOP)/util/romtool/romtool %sfs add-payload %s %s/payload `cat 
%s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j))
-               file.write("\t $(TOP)/util/romtool/romtool %sfs print\n" 
% i.name)
+                               file.write("\tif [ -f %s/romfs-support 
]; then ./romtool %sfs add-payload %s %s/payload `cat %s/romfs-support`; 
fi\n" % (j, i.name, rommapping[j], j, j))
+               file.write("\t ./romtool %sfs print\n" % i.name)

         file.write(".PHONY: all clean romtool")
         for i in romimages.keys():




From info at coresystems.de  Sat Apr  4 00:45:14 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 00:45:14 +0200
Subject: [coreboot] build service results for r4060
Message-ID: <E1Lps8Q-0006uG-4b@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4060 to
the coreboot repository. This caused the following 
changes:

Change Log:
These are some cleanups and changes. These are build and boot tested on qemu.
Some changes for option roms:
- don't make users pick the name. Names for option roms are in the v3-defined
format of pci%04x,%04x.rom with the vendor and device id filling in the
%04x.
- users pass in vendor and device id.
- users pass in a dest. If the dest is 0, the address of the ROM image in
FLASH is returned. If the address is non-zero, then the decmpressor is called,
and it will make sure the ROM image is copied to the destination (even
in the uncompressed case).

And some type and print cleanup.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>




Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4060&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4060&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4060&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4060&device=briq&vendor=totalimpact&num=1


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Sat Apr  4 01:06:04 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 4 Apr 2009 01:06:04 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds
	the	romtool utility
In-Reply-To: <49D68F74.40100@georgi-clan.de>
References: <49D68F74.40100@georgi-clan.de>
Message-ID: <20090403230604.19908.qmail@stuge.se>

Patrick Georgi wrote:
> romtool per-build

Is it too much for us to ask that the cbfs tool is built and
installed into the build system? I think that would be ok.


//Peter



From joe at settoplinux.org  Sat Apr  4 01:06:20 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 03 Apr 2009 19:06:20 -0400
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <49D68D0B.1010800@gmx.net>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
	<49D68D0B.1010800@gmx.net>
Message-ID: <47e9e7602cf26cc106ec3f0c92228886@imap.1and1.com>




On Sat, 04 Apr 2009 00:26:19 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 03.04.2009 20:20, Joseph Smith wrote:
>>
>> On Fri, 03 Apr 2009 19:05:28 +0200, Carl-Daniel Hailfinger wrote:
>>
>>> This is a list of targets using ROMCC together with the CPU type used
>>> for ROMCC.
>>>
>>>
>> rca/rm4100 p3
>> thomson/ip1000 p3
>> Are my doings. I would love to see them using CAR instead of ROMCC, but
> I
>> wouldn't even know where to start....
>>
> 
> Great. Will a bad reflash hurt you?
>
No, as long as it doesn't blow the thing up :-0
> 
> What you need to try this one out:
> - a POST card or another way to fetch POST codes.
> - tell me whether POST works by default or you need special setup.
> - a will to try out v3 with some patches
> 
Ok, I have a PCI/Parallel Post Card. The RM4100 doesn't have eithor, the
IP1000 does have a PCI slot so we can use that for testing.
> 
> The idea is to test the v3 intel CAR code which has not been on real
> hardware yet, but it is a much cleaner and more readable implementation
> compared to v2. I'm hoping we don't need chipset specific stuff for POST
> to work.
>
Not sure, serial output works fine.
> 
> I need info on the cache size of your processor, though. Unreliable CAR
> is not nearly as much fun as reliable CAR.
>
512k

http://processorfinder.intel.com/details.aspx?sSpec=SL68W 

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From rminnich at gmail.com  Sat Apr  4 01:08:20 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 3 Apr 2009 16:08:20 -0700
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds the
	romtool utility
In-Reply-To: <20090403230604.19908.qmail@stuge.se>
References: <49D68F74.40100@georgi-clan.de>
	<20090403230604.19908.qmail@stuge.se>
Message-ID: <13426df10904031608o3dc003edtf97d8bd603af5b02@mail.gmail.com>

On Fri, Apr 3, 2009 at 4:06 PM, Peter Stuge <peter at stuge.se> wrote:
> Patrick Georgi wrote:
>> romtool per-build
>
> Is it too much for us to ask that the cbfs tool is built and
> installed into the build system? I think that would be ok.

that's a reasonable idea.

Just tell people that the tool needs to be executable and in PATH

ron



From c-d.hailfinger.devel.2006 at gmx.net  Sat Apr  4 01:19:33 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 04 Apr 2009 01:19:33 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds the
 romtool utility
In-Reply-To: <13426df10904031608o3dc003edtf97d8bd603af5b02@mail.gmail.com>
References: <49D68F74.40100@georgi-clan.de>	<20090403230604.19908.qmail@stuge.se>
	<13426df10904031608o3dc003edtf97d8bd603af5b02@mail.gmail.com>
Message-ID: <49D69985.3020504@gmx.net>

On 04.04.2009 01:08, ron minnich wrote:
> On Fri, Apr 3, 2009 at 4:06 PM, Peter Stuge <peter at stuge.se> wrote:
>   
>> Patrick Georgi wrote:
>>     
>>> romtool per-build
>>>       
>> Is it too much for us to ask that the cbfs tool is built and
>> installed into the build system? I think that would be ok.
>>     
>
> that's a reasonable idea.
>
> Just tell people that the tool needs to be executable and in PATH
>   

Please don't. That will make incompatible changes for romtool
impossible. Just think of the child^Wpain we had with multiple lzma
implementations. v3 avoids the lzma problem by building lzma in the
build dir so we always know the lzma version.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sat Apr  4 02:21:59 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 04 Apr 2009 02:21:59 +0200
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <47e9e7602cf26cc106ec3f0c92228886@imap.1and1.com>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
	<49D68D0B.1010800@gmx.net>
	<47e9e7602cf26cc106ec3f0c92228886@imap.1and1.com>
Message-ID: <49D6A827.6080503@gmx.net>

On 04.04.2009 01:06, Joseph Smith wrote:
>
> On Sat, 04 Apr 2009 00:26:19 +0200, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> [ROMCC->CAR]
>> Great. Will a bad reflash hurt you?
>>
>>     
> No, as long as it doesn't blow the thing up :-0
>   

Heh. That won't happen unless an endless loop is too much for your
cooling setup.


>> What you need to try this one out:
>> - a POST card or another way to fetch POST codes.
>> - tell me whether POST works by default or you need special setup.
>> - a will to try out v3 with some patches.
>>     
> Ok, I have a PCI/Parallel Post Card. The RM4100 doesn't have eithor, the
> IP1000 does have a PCI slot so we can use that for testing.
>   

Good. Can you verify that the PCI POST card works?

>> The idea is to test the v3 intel CAR code which has not been on real
>> hardware yet, but it is a much cleaner and more readable implementation
>> compared to v2. I'm hoping we don't need chipset specific stuff for POST
>> to work.
>>     
> Not sure, serial output works fine.
>   

We'll debug very early code, before serial can be set up.

>> I need info on the cache size of your processor, though. Unreliable CAR
>> is not nearly as much fun as reliable CAR.
>>     
> 512k
>
> http://processorfinder.intel.com/details.aspx?sSpec=SL68W 
>   

Thanks. Can you find out L1 cache sizes as well? The spec page was not
clear about that. And is the processor hyperthreading capable?

I'll follow up with a patch on Wednesday or Thursday.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Sat Apr  4 02:36:55 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 3 Apr 2009 17:36:55 -0700
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds the
	romtool utility
In-Reply-To: <49D69985.3020504@gmx.net>
References: <49D68F74.40100@georgi-clan.de>
	<20090403230604.19908.qmail@stuge.se>
	<13426df10904031608o3dc003edtf97d8bd603af5b02@mail.gmail.com>
	<49D69985.3020504@gmx.net>
Message-ID: <13426df10904031736j1e9e4616g3013622a2f311c86@mail.gmail.com>

On Fri, Apr 3, 2009 at 4:19 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Please don't. That will make incompatible changes for romtool
> impossible. Just think of the child^Wpain we had with multiple lzma
> implementations. v3 avoids the lzma problem by building lzma in the
> build dir so we always know the lzma version.

actually, I installed lar in my path on v3 and only had trouble with
that setup once. In fact, the long term vision for tools like LAR and
romtool is that they be usable and functional outside the build tree.

But this is not a burning issue for me either way.

ron



From corey.osgood at gmail.com  Sat Apr  4 04:18:13 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Fri, 3 Apr 2009 22:18:13 -0400
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <49D6A827.6080503@gmx.net>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
	<49D68D0B.1010800@gmx.net>
	<47e9e7602cf26cc106ec3f0c92228886@imap.1and1.com>
	<49D6A827.6080503@gmx.net>
Message-ID: <dd3c80060904031918x514e659bvf9b73c50f81bb671@mail.gmail.com>

On Fri, Apr 3, 2009 at 8:21 PM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> On 04.04.2009 01:06, Joseph Smith wrote:
> >
> > On Sat, 04 Apr 2009 00:26:19 +0200, Carl-Daniel Hailfinger
> > <c-d.hailfinger.devel.2006 at gmx.net> wrote:
> >
> >> [ROMCC->CAR]
> >> Great. Will a bad reflash hurt you?
> >>
> >>
> > No, as long as it doesn't blow the thing up :-0
> >
>
> Heh. That won't happen unless an endless loop is too much for your
> cooling setup.
>
>
> >> What you need to try this one out:
> >> - a POST card or another way to fetch POST codes.
> >> - tell me whether POST works by default or you need special setup.
> >> - a will to try out v3 with some patches.
> >>
> > Ok, I have a PCI/Parallel Post Card. The RM4100 doesn't have eithor, the
> > IP1000 does have a PCI slot so we can use that for testing.
> >
>
> Good. Can you verify that the PCI POST card works?
>
> >> The idea is to test the v3 intel CAR code which has not been on real
> >> hardware yet, but it is a much cleaner and more readable implementation
> >> compared to v2. I'm hoping we don't need chipset specific stuff for POST
> >> to work.
> >>
> > Not sure, serial output works fine.
> >
>
> We'll debug very early code, before serial can be set up.
>
> >> I need info on the cache size of your processor, though. Unreliable CAR
> >> is not nearly as much fun as reliable CAR.
> >>
> > 512k
> >
> > http://processorfinder.intel.com/details.aspx?sSpec=SL68W
> >
>
> Thanks. Can you find out L1 cache sizes as well? The spec page was not
> clear about that. And is the processor hyperthreading capable?
>
> I'll follow up with a patch on Wednesday or Thursday.


 All P2 & P3s should be 32k L1 cache, and between the p2s, p3s, and celerons
based on them, they have 128, 256, or 512k of L2 cache (Xeons also had 1 or
2MB). I think if it runs on Joe's system, and can handle the different cache
sizes, the different cores are similar enough that it might just work on the
whole range. I have a few boards kicking around, 440BX and i810 alike, I can
test stuff on if you need me to.

-Corey
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From joe at settoplinux.org  Sat Apr  4 04:56:44 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 03 Apr 2009 22:56:44 -0400
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <49D6A827.6080503@gmx.net>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
	<49D68D0B.1010800@gmx.net>
	<47e9e7602cf26cc106ec3f0c92228886@imap.1and1.com>
	<49D6A827.6080503@gmx.net>
Message-ID: <565811b253d296cd93241cbc20c56339@imap.1and1.com>




On Sat, 04 Apr 2009 02:21:59 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 04.04.2009 01:06, Joseph Smith wrote:
>>
>> On Sat, 04 Apr 2009 00:26:19 +0200, Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>>
>>> [ROMCC->CAR]
>>> Great. Will a bad reflash hurt you?
>>>
>>>
>> No, as long as it doesn't blow the thing up :-0
>>
> 
> Heh. That won't happen unless an endless loop is too much for your
> cooling setup.
> 
> 
>>> What you need to try this one out:
>>> - a POST card or another way to fetch POST codes.
>>> - tell me whether POST works by default or you need special setup.
>>> - a will to try out v3 with some patches.
>>>
>> Ok, I have a PCI/Parallel Post Card. The RM4100 doesn't have eithor, the
>> IP1000 does have a PCI slot so we can use that for testing.
>>
> 
> Good. Can you verify that the PCI POST card works?
>
Sure
>
>>> The idea is to test the v3 intel CAR code which has not been on real
>>> hardware yet, but it is a much cleaner and more readable implementation
>>> compared to v2. I'm hoping we don't need chipset specific stuff for
> POST
>>> to work.
>>>
>> Not sure, serial output works fine.
>>
> 
> We'll debug very early code, before serial can be set up.
> 
Oh ok.

>>> I need info on the cache size of your processor, though. Unreliable CAR
>>> is not nearly as much fun as reliable CAR.
>>>
>> 512k
>>
>> http://processorfinder.intel.com/details.aspx?sSpec=SL69K
>>
> 
> Thanks. Can you find out L1 cache sizes as well? The spec page was not
> clear about that. 
> 

Hmm, Datasheet does not say:
http://download.intel.com/design/PentiumIII/datashts/27367305.pdf

It just says:
? On-die primary (L1) instruction and data caches
  ? 4-way set associative, 32-byte line size, 1 line per sector
  ? 16-Kbyte instruction cache and 16-Kbyte write-back data cache
  ? Cacheable range controlled by processor programmable registers
? On-die second level (L2) cache
  ? 8-way set associative, 32-byte line size, 1 line per sector
  ? Operates at full core speed
  ? 512-Kbyte ECC protected cache data array

> And is the processor hyperthreading capable?
> 
No, hyperthreading was not introduced until later P4's

> I'll follow up with a patch on Wednesday or Thursday.
> 
Cool. I am going out of town this weekend but I will test out the post card
as soon as I can.
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Sat Apr  4 05:03:12 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 03 Apr 2009 23:03:12 -0400
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <565811b253d296cd93241cbc20c56339@imap.1and1.com>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
	<49D68D0B.1010800@gmx.net>
	<47e9e7602cf26cc106ec3f0c92228886@imap.1and1.com>
	<49D6A827.6080503@gmx.net>
	<565811b253d296cd93241cbc20c56339@imap.1and1.com>
Message-ID: <a363118b10739dd64232e8421a861295@imap.1and1.com>



> http://download.intel.com/design/PentiumIII/datashts/27367305.pdf
> 
> It just says:
> ? On-die primary (L1) instruction and data caches
>   ? 4-way set associative, 32-byte line size, 1 line per sector
>   ? 16-Kbyte instruction cache and 16-Kbyte write-back data cache
>   ? Cacheable range controlled by processor programmable registers
> ? On-die second level (L2) cache
>   ? 8-way set associative, 32-byte line size, 1 line per sector
>   ? Operates at full core speed
>   ? 512-Kbyte ECC protected cache data array
> 
Oh does that mean the L1 cache is 16K? That seems so small...

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From jordan at cosmicpenguin.net  Sat Apr  4 06:24:54 2009
From: jordan at cosmicpenguin.net (jordan at cosmicpenguin.net)
Date: Fri, 3 Apr 2009 22:24:54 -0600 (MDT)
Subject: [coreboot] Name change for romfs
In-Reply-To: <13426df10904031524l400eb948sdb5ac4fa54021828@mail.gmail.com>
References: <20090403215800.2751.qmail@stuge.se>
	<49D68C00.5040403@coresystems.de>
	<13426df10904031524l400eb948sdb5ac4fa54021828@mail.gmail.com>
Message-ID: <36720.192.168.0.103.1238819094.squirrel@mail.cosmicpenguin.net>

> On Fri, Apr 3, 2009 at 3:21 PM, Stefan Reinauer <stepan at coresystems.de>
> wrote:
>> Peter Stuge wrote:
>>> Is someone owning this issue?
>>>
>>>
>> Yes, Jordan wrote the code, he should decide. That's how we handled such
>> cases before.
>>
>> Stefan
>>
>
> Jordan, don't know if you saw the discussion, one possibility was to
> change to cbfs (coreboot fs)
>
> ron

Normally, I wouldn't want to make a unilateral decision like this - I'm
not in the community any longer, and you guys have to live with the name. 
But in this case, I honestly think that that the romfs concept is
essential to the long term health of the project, and I don't want to
derail it over something silly like a name.  Lets go with cbfs.

Jordan





From joe at settoplinux.org  Sat Apr  4 06:30:37 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 04 Apr 2009 00:30:37 -0400
Subject: [coreboot] Name change for romfs
In-Reply-To: <36720.192.168.0.103.1238819094.squirrel@mail.cosmicpenguin.net>
References: <20090403215800.2751.qmail@stuge.se>
	<49D68C00.5040403@coresystems.de>
	<13426df10904031524l400eb948sdb5ac4fa54021828@mail.gmail.com>
	<36720.192.168.0.103.1238819094.squirrel@mail.cosmicpenguin.net>
Message-ID: <d4f3ccc1bce1a285e37cb1f7db05fbdc@imap.1and1.com>




On Fri, 3 Apr 2009 22:24:54 -0600 (MDT), jordan at cosmicpenguin.net wrote:
> I'm not in the community any longer,

Why not? Did something happen to discourage you Jordan?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From corey.osgood at gmail.com  Sat Apr  4 07:21:14 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 4 Apr 2009 01:21:14 -0400
Subject: [coreboot] Quick questions on the mtrr setup code
Message-ID: <dd3c80060904032221u50d4a682i6154dc411a2eaf3c@mail.gmail.com>

I'm poking around mtrr.c (v2 and v3 are almost identical, but I'm looking at
v3), and I'm trying to understand set_var_mtrr_resource(). It looks to me
like the code is setting up the mtrrs for the var_mtrr_state struct, then
setting var_mtrr_state struct to equal the values passed by the resource
struct, so it's always one base/size behind. This then has to be corrected
for in x86_setup_var_mtrrs(), which writes the last mtrr. It would make more
sense to me for var_mtrr_state to be the state of the mtrrs AFTER the
function runs, and for the function to be setting up the mtrrs for the
resource it was just passed. It would also make the code to automagically
figure out if it's better to use additive or subtractive mtrrs marginally
simpler to write. Is there any reason for it to work this way, or was it
just pulled from kernel source that way?

Also, does anyone know of any CPUs or situations where a subtractive MTRR
setup would break things?

Thanks,
Corey
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From patrick at georgi-clan.de  Sat Apr  4 09:33:31 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 04 Apr 2009 09:33:31 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds	the
 romtool utility
In-Reply-To: <20090403230604.19908.qmail@stuge.se>
References: <49D68F74.40100@georgi-clan.de>
	<20090403230604.19908.qmail@stuge.se>
Message-ID: <49D70D4B.7010006@georgi-clan.de>

Am 04.04.2009 01:06, schrieb Peter Stuge:
> Patrick Georgi wrote:
>    
>> romtool per-build
>>      
>
> Is it too much for us to ask that the cbfs tool is built and
> installed into the build system? I think that would be ok.
>    
"into the build system"?

With this patch, it's built in util/romtools and then "installed" into 
the coreboot-build/*/ directories.


Patrick
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From yinghailu at gmail.com  Sat Apr  4 09:43:24 2009
From: yinghailu at gmail.com (yhlu)
Date: Sat, 4 Apr 2009 00:43:24 -0700
Subject: [coreboot] Remaining ROMCC targets
In-Reply-To: <a363118b10739dd64232e8421a861295@imap.1and1.com>
References: <49D641D8.1080403@gmx.net>
	<cefd5d1aa49bcdd966496e92d25c0e73@imap.1and1.com>
	<49D68D0B.1010800@gmx.net>
	<47e9e7602cf26cc106ec3f0c92228886@imap.1and1.com>
	<49D6A827.6080503@gmx.net>
	<565811b253d296cd93241cbc20c56339@imap.1and1.com>
	<a363118b10739dd64232e8421a861295@imap.1and1.com>
Message-ID: <2ea3fae10904040043v4a1af9fdyf46d1af017ad0cc7@mail.gmail.com>

On Fri, Apr 3, 2009 at 8:03 PM, Joseph Smith <joe at settoplinux.org> wrote:

>
>
> > http://download.intel.com/design/PentiumIII/datashts/27367305.pdf
> >
> > It just says:
> > ? On-die primary (L1) instruction and data caches
> >   ? 4-way set associative, 32-byte line size, 1 line per sector
> >   ? 16-Kbyte instruction cache and 16-Kbyte write-back data cache
> >   ? Cacheable range controlled by processor programmable registers
> > ? On-die second level (L2) cache
> >   ? 8-way set associative, 32-byte line size, 1 line per sector
> >   ? Operates at full core speed
> >   ? 512-Kbyte ECC protected cache data array
> >
> Oh does that mean the L1 cache is 16K? That seems so small...
>

4k should be enough

YH
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From yinghailu at gmail.com  Sat Apr  4 09:47:20 2009
From: yinghailu at gmail.com (yhlu)
Date: Sat, 4 Apr 2009 00:47:20 -0700
Subject: [coreboot] Quick questions on the mtrr setup code
In-Reply-To: <dd3c80060904032221u50d4a682i6154dc411a2eaf3c@mail.gmail.com>
References: <dd3c80060904032221u50d4a682i6154dc411a2eaf3c@mail.gmail.com>
Message-ID: <2ea3fae10904040047ue08b416rc47df5e85ac24707@mail.gmail.com>

On Fri, Apr 3, 2009 at 10:21 PM, Corey Osgood <corey.osgood at gmail.com>wrote:

>
> Also, does anyone know of any CPUs or situations where a subtractive MTRR
> setup would break things?
>

you may not add range for write-combing for some X server...
because UC will take first sequence.

YH
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From peter at stuge.se  Sat Apr  4 11:10:17 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 4 Apr 2009 11:10:17 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds
	the	romtool utility
In-Reply-To: <49D70D4B.7010006@georgi-clan.de>
References: <49D68F74.40100@georgi-clan.de>
	<20090403230604.19908.qmail@stuge.se>
	<49D70D4B.7010006@georgi-clan.de>
Message-ID: <20090404091017.9934.qmail@stuge.se>

Patrick Georgi wrote:
>> Is it too much for us to ask that the cbfs tool is built and
>> installed into the build system? I think that would be ok.
>
> "into the build system"?

"on the build system" then.


> With this patch, it's built in util/romtools and then "installed"
> into the coreboot-build/*/ directories.

I meant build the tool, then install to /usr/local/bin
I like that for romcc as well.


If that fails, I think it's ok to at least build each of them in
their util/ directory and run them there.

It would be trivial if we did not insist on build directories, but I
don't believe they will go away.


At any rate, isn't it actually very easy to build all neccessary
tools in a common place and then depend on these in each board?

That way they would only be built once.


//Peter



From patrick at georgi-clan.de  Sat Apr  4 11:50:50 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 04 Apr 2009 11:50:50 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds	the
 romtool utility
In-Reply-To: <20090404091017.9934.qmail@stuge.se>
References: <49D68F74.40100@georgi-clan.de>	<20090403230604.19908.qmail@stuge.se>	<49D70D4B.7010006@georgi-clan.de>
	<20090404091017.9934.qmail@stuge.se>
Message-ID: <49D72D7A.20103@georgi-clan.de>

That whole discussion is so unrelated to the actual issue the patch 
attempts to solve, it isn't funny.

To reduce the impact of the patch, here's an updated version that 
doesn't change the behaviour in util/romtool at all.
The only thing it fixes is the concurrency issue that currently kills 
the first target in the list of the autobuilder.

Feel free to continue to debate the merit of default install locations 
etc (btw: Solaris wants SVr4 style, ie /opt/coreboot/bin or so. 
/usr/local/bin is not part of their file system standard. Please take 
that into account, if you really want to go down that route), I don't 
think romfs should be considered stable (in terms of interfaces and file 
formats) enough for installation yet, so I'll stay away from that.

Again, the patch is probably not whitespace clean (copy&pasted), but I 
will commit as soon as I get an ack.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Index: util/newconfig/config.g
===================================================================
--- util/newconfig/config.g     (Revision 4060)
+++ util/newconfig/config.g     (Arbeitskopie)
@@ -2225,13 +2225,14 @@
         writemakefileheader(file, makefilepath)

         # main rule
-       file.write("\nall: romtool")
+       file.write("\nall: ")
         for i in buildroms:
                 file.write(" %sfs" % i.name)
         file.write("\n\n")

         # romtool rules
-       file.write("\nromtool:\n\tcd $(TOP)/util/romtool; make\n")
+       file.write("\nromtool:\n\t$(MAKE) -C 
$(TOP)/util/romtool\n\tmkdir -p tools\n")
+       file.write("\tcp $(TOP)/util/romtool/tools/rom-mkpayload 
$(TOP)/util/romtool/tools/rom-mkstage tools\n\tcp 
$(TOP)/util/romtool/romtool romtool\n")

         file.write("include Makefile.settings\n\n")
         for i, o in romimages.items():
@@ -2268,15 +2269,15 @@

         romsize = getoption("ROM_SIZE", image)
         # i.name? That can not be right, can it?
-       file.write("%sfs: %s $(TOP)/util/romtool/romtool\n" 
%(i.name,i.name));
+       file.write("%sfs: %s romtool\n" %(i.name,i.name));
         file.write("\trm -f coreboot.romfs\n");
-       file.write("\t$(TOP)/util/romtool/romtool %sfs create %s %s 
%s.bootblock\n" % (i.name, romsize, bootblocksize, i.name))
+       file.write("\t./romtool %sfs create %s %s %s.bootblock\n" % 
(i.name, romsize, bootblocksize, i.name))
         for i in buildroms:
                 for j in i.roms:
                         #failover is a hack that will go away soon.
                         if (j != "failover") and (rommapping[j] != 
"/dev/null"):
-                               file.write("\tif [ -f %s/romfs-support 
]; then $(TOP)/util/romtool/romtool %sfs add-payload %s %s/payload `cat 
%s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j))
-               file.write("\t $(TOP)/util/romtool/romtool %sfs print\n" 
% i.name)
+                               file.write("\tif [ -f %s/romfs-support 
]; then ./romtool %sfs add-payload %s %s/payload `cat %s/romfs-support`; 
fi\n" % (j, i.name, rommapping[j], j, j))
+               file.write("\t ./romtool %sfs print\n" % i.name)

         file.write(".PHONY: all clean romtool")
         for i in romimages.keys():




From stepan at coresystems.de  Sat Apr  4 11:53:19 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 04 Apr 2009 11:53:19 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds	the
 romtool utility
In-Reply-To: <20090404091017.9934.qmail@stuge.se>
References: <49D68F74.40100@georgi-clan.de>	<20090403230604.19908.qmail@stuge.se>	<49D70D4B.7010006@georgi-clan.de>
	<20090404091017.9934.qmail@stuge.se>
Message-ID: <49D72E0F.20606@coresystems.de>

On 04.04.2009 11:10 Uhr, Peter Stuge wrote:
> Patrick Georgi wrote:
>   
>>> Is it too much for us to ask that the cbfs tool is built and
>>> installed into the build system? I think that would be ok.
>>>       
>> "into the build system"?
>>     
>
> "on the build system" then.
>
>
>   
>> With this patch, it's built in util/romtools and then "installed"
>> into the coreboot-build/*/ directories.
>>     
>
> I meant build the tool, then install to /usr/local/bin
> I like that for romcc as well.
>
>   
This -- imho -- makes little sense for a tool that roughly takes about a
second to compile and serves no other purpose than being a build
requirement for coreboot. It would require us to do version checks of
the utilities, maintain feature lists of working versions, etc. What a
nightmare. Why would we even consider this? Then where would we look for
the binaries? /usr/local/bin? /opt/coreboot/bin on non-linux systems?
What about Darwin? What about Windows? I really don't think we want to care.

Besides, this discussion has nothing to do with the bug fixed by
Patrick's patch.

> If that fails, I think it's ok to at least build each of them in
> their util/ directory and run them there.
>   

We ought to keep our source tree clean and only put objects and binaries
to target/.../ but that's as far as we should go.

> It would be trivial if we did not insist on build directories, but I
> don't believe they will go away.
>   

I suppose you meant it is trivial if we use build directories and build
everything in there?

> At any rate, isn't it actually very easy to build all neccessary
> tools in a common place and then depend on these in each board?
>
> That way they would only be built once.
>   
Not sure if I get right what you are suggesting. The build tools romcc
and romfs are only built once per image.
Optimizing 1s per image/target by introducing a whole bunch of new
problems and dependencies is an incredibly bad idea.

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Sat Apr  4 11:56:26 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 04 Apr 2009 11:56:26 +0200
Subject: [coreboot] [PATCH]romfs: change the mechanism that builds	the
 romtool utility
In-Reply-To: <49D72D7A.20103@georgi-clan.de>
References: <49D68F74.40100@georgi-clan.de>	<20090403230604.19908.qmail@stuge.se>	<49D70D4B.7010006@georgi-clan.de>	<20090404091017.9934.qmail@stuge.se>
	<49D72D7A.20103@georgi-clan.de>
Message-ID: <49D72ECA.1040105@coresystems.de>

On 04.04.2009 11:50 Uhr, Patrick Georgi wrote:
> That whole discussion is so unrelated to the actual issue the patch
> attempts to solve, it isn't funny.
>
> To reduce the impact of the patch, here's an updated version that
> doesn't change the behaviour in util/romtool at all.
> The only thing it fixes is the concurrency issue that currently kills
> the first target in the list of the autobuilder.
>
> Feel free to continue to debate the merit of default install locations
> etc (btw: Solaris wants SVr4 style, ie /opt/coreboot/bin or so.
> /usr/local/bin is not part of their file system standard. Please take
> that into account, if you really want to go down that route), I don't
> think romfs should be considered stable (in terms of interfaces and
> file formats) enough for installation yet, so I'll stay away from that.
>
> Again, the patch is probably not whitespace clean (copy&pasted), but I
> will commit as soon as I get an ack.
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

>
> Index: util/newconfig/config.g
> ===================================================================
> --- util/newconfig/config.g     (Revision 4060)
> +++ util/newconfig/config.g     (Arbeitskopie)
> @@ -2225,13 +2225,14 @@
>         writemakefileheader(file, makefilepath)
>
>         # main rule
> -       file.write("\nall: romtool")
> +       file.write("\nall: ")
>         for i in buildroms:
>                 file.write(" %sfs" % i.name)
>         file.write("\n\n")
>
>         # romtool rules
> -       file.write("\nromtool:\n\tcd $(TOP)/util/romtool; make\n")
> +       file.write("\nromtool:\n\t$(MAKE) -C
> $(TOP)/util/romtool\n\tmkdir -p tools\n")
> +       file.write("\tcp $(TOP)/util/romtool/tools/rom-mkpayload
> $(TOP)/util/romtool/tools/rom-mkstage tools\n\tcp
> $(TOP)/util/romtool/romtool romtool\n")
>
>         file.write("include Makefile.settings\n\n")
>         for i, o in romimages.items():
> @@ -2268,15 +2269,15 @@
>
>         romsize = getoption("ROM_SIZE", image)
>         # i.name? That can not be right, can it?
> -       file.write("%sfs: %s $(TOP)/util/romtool/romtool\n"
> %(i.name,i.name));
> +       file.write("%sfs: %s romtool\n" %(i.name,i.name));
>         file.write("\trm -f coreboot.romfs\n");
> -       file.write("\t$(TOP)/util/romtool/romtool %sfs create %s %s
> %s.bootblock\n" % (i.name, romsize, bootblocksize, i.name))
> +       file.write("\t./romtool %sfs create %s %s %s.bootblock\n" %
> (i.name, romsize, bootblocksize, i.name))
>         for i in buildroms:
>                 for j in i.roms:
>                         #failover is a hack that will go away soon.
>                         if (j != "failover") and (rommapping[j] !=
> "/dev/null"):
> -                               file.write("\tif [ -f %s/romfs-support
> ]; then $(TOP)/util/romtool/romtool %sfs add-payload %s %s/payload
> `cat %s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j))
> -               file.write("\t $(TOP)/util/romtool/romtool %sfs
> print\n" % i.name)
> +                               file.write("\tif [ -f %s/romfs-support
> ]; then ./romtool %sfs add-payload %s %s/payload `cat
> %s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j))
> +               file.write("\t ./romtool %sfs print\n" % i.name)
>
>         file.write(".PHONY: all clean romtool")
>         for i in romimages.keys():
>
>


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Sat Apr  4 12:01:21 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 12:01:21 +0200
Subject: [coreboot] [v2] r4061 - trunk/coreboot-v2/util/newconfig
Message-ID: <mailman.2938.1355071510.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-04-04 12:01:21 +0200 (Sat, 04 Apr 2009)
New Revision: 4061

Modified:
   trunk/coreboot-v2/util/newconfig/config.g
Log:
Fix the concurrency issue of building romtool.
romtool is still built in util/romtool, as happens without this patch.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2009-04-03 22:23:34 UTC (rev 4060)
+++ trunk/coreboot-v2/util/newconfig/config.g	2009-04-04 10:01:21 UTC (rev 4061)
@@ -2225,13 +2225,14 @@
 	writemakefileheader(file, makefilepath)
 
 	# main rule
-	file.write("\nall: romtool")
+	file.write("\nall: ")
 	for i in buildroms:
 		file.write(" %sfs" % i.name)
 	file.write("\n\n")	
 
 	# romtool rules
-	file.write("\nromtool:\n\tcd $(TOP)/util/romtool; make\n")
+	file.write("\nromtool:\n\t$(MAKE) -C $(TOP)/util/romtool\n\tmkdir -p tools\n")
+	file.write("\tcp $(TOP)/util/romtool/tools/rom-mkpayload $(TOP)/util/romtool/tools/rom-mkstage tools\n\tcp $(TOP)/util/romtool/romtool romtool\n")
 
 	file.write("include Makefile.settings\n\n")
 	for i, o in romimages.items():
@@ -2268,15 +2269,15 @@
 
 	romsize = getoption("ROM_SIZE", image)
 	# i.name? That can not be right, can it? 
-	file.write("%sfs: %s $(TOP)/util/romtool/romtool\n" %(i.name,i.name));
+	file.write("%sfs: %s romtool\n" %(i.name,i.name));
 	file.write("\trm -f coreboot.romfs\n");
-	file.write("\t$(TOP)/util/romtool/romtool %sfs create %s %s %s.bootblock\n" % (i.name, romsize, bootblocksize, i.name))
+	file.write("\t./romtool %sfs create %s %s %s.bootblock\n" % (i.name, romsize, bootblocksize, i.name))
 	for i in buildroms:
 		for j in i.roms:
 			#failover is a hack that will go away soon. 
 			if (j != "failover") and (rommapping[j] != "/dev/null"):
-				file.write("\tif [ -f %s/romfs-support ]; then $(TOP)/util/romtool/romtool %sfs add-payload %s %s/payload `cat %s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j))
-		file.write("\t $(TOP)/util/romtool/romtool %sfs print\n" % i.name)
+				file.write("\tif [ -f %s/romfs-support ]; then ./romtool %sfs add-payload %s %s/payload `cat %s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j))
+		file.write("\t ./romtool %sfs print\n" % i.name)
 
 	file.write(".PHONY: all clean romtool")
 	for i in romimages.keys():




From info at coresystems.de  Sat Apr  4 12:23:12 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 12:23:12 +0200
Subject: [coreboot] build service results for r4061
Message-ID: <E1Lq31s-0006K4-Lu@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4061 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix the concurrency issue of building romtool.
romtool is still built in util/romtool, as happens without this patch.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4061&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4061&device=ep405pc&vendor=embeddedplanet&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4061&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4061&device=briq&vendor=totalimpact&num=1


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From harald.gutmann at gmx.net  Sat Apr  4 12:54:52 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Sat, 4 Apr 2009 12:54:52 +0200
Subject: [coreboot] Fix some PCI issues on M57SLI v2
In-Reply-To: <20090403193315.GA7651@localdomain>
References: <200903241854.53171.harald.gutmann@gmx.net>
	<200904022201.41702.harald.gutmann@gmx.net>
	<20090403193315.GA7651@localdomain>
Message-ID: <200904041254.57545.harald.gutmann@gmx.net>

On Friday 03 April 2009 21:33:15 Ward Vandewege wrote:
The first part of your message was fine to read, but this one worries me a 
little bit.

> However, I got this after having the machine up for a while:
>
> [  999.664992] Uhhuh. NMI received for unknown reason 00.
> [  999.665144] Uhhuh. NMI received for unknown reason a1.
> [  999.665147] You have some hardware problem, likely on the PCI bus.
> [  999.665149] Dazed and confused, but trying to continue
> [  999.667309] Do you have a strange power saving mode enabled?
> [  999.667309] Dazed and confused, but trying to continue
>
> This was right after I did
>
>   cat /proc/interrupts
>
> a couple times - but that may have been a coincidence.
I think it could have been a coincidence, but i'd be interested in further 
details, as this is maybe a result of a "wrong" mptable setup.

Which kernel version did you use on which distribution?
dmesg output, lspci output, /proc/interrupts, and anything else which could be 
interesting. :)

> Ideas?
Right now, not really, but i saw according to your last outputs of m57sli 
which you gave to me, that something with the interrupts is different on v1 and 
v2 and proprietary bios. This could also be a related to different bios 
versions we use, but also it could be a hardware difference which we should 
take care about.

I think for simplifying/sorting out things, it would be good if you could 
switch to the same vendor bios version that i use and resend me your 
acpidump/dmesg/lspci from the vendor bios.
I use version FG for v2 which is dated on 2008/03/07 and, i think, is equal to 
F14 of v1 which is dated on the same day.

Maybe it will be necessary to introduce some config value like:
CONFIG_M57SLI_HARDWARE_REVISION
to get the interrupt problem fixed on both versions of m57sli.
A hardware difference could also have been the reason why Soft-Poweroff didn't 
work on your v1 while it worked fine on my v2.

I hope we can avoid that step and the mistake is located somewhere else, but 
we'll see.

> Thanks,
> Ward.
Thanks for testing,
kind regards
Harald

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From dimitri.pekarovsky at gmail.com  Sat Apr  4 14:04:58 2009
From: dimitri.pekarovsky at gmail.com (Dimitri Pekarovsky)
Date: Sat, 4 Apr 2009 15:04:58 +0300
Subject: [coreboot] Will coreboot work on GIGABYTE I945 chipset?
Message-ID: <6f7a5ee80904040504t377dba50pe469ff8086b9c739@mail.gmail.com>

Hi, dear ALL.

Could anyone say me if coreboot will work on my GIGABYTE
GA-945GCM-S2L, 945GC / Socket 775?

Data, as described in Wiki, is below.

//W.respect. D.P.



From dimitri.pekarovsky at gmail.com  Sat Apr  4 14:11:44 2009
From: dimitri.pekarovsky at gmail.com (Dimitri Pekarovsky)
Date: Sat, 4 Apr 2009 15:11:44 +0300
Subject: [coreboot] Will coreboot work on GIGABYTE I945 chipset?
In-Reply-To: <6f7a5ee80904040504t377dba50pe469ff8086b9c739@mail.gmail.com>
References: <6f7a5ee80904040504t377dba50pe469ff8086b9c739@mail.gmail.com>
Message-ID: <6f7a5ee80904040511o3523a2bcmfd384b586dabc78f@mail.gmail.com>

Sorry, for double post.
I forgotten to attach listings.

Could anyone say me if coreboot will work on my GIGABYTE
GA-945GCM-S2L, 945GC / Socket 775?
Data, as described in Wiki, is below.
//W.respect. D.P.

motherboard page:
http://www.gigabyte.eu/Products/Motherboard/Products_Spec.aspx?ProductID=2669

Intel(R) Pentium(R) Dual  CPU  E2180  @ 2.00GHz stepping 0d

# flashrom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH7/ICH7R", enabling flash write... OK.
Found chip "Macronix MX25L4005" (512 KB) at physical address 0xfff80000.
No operations were specified.

$ /sbin/lspci
00:00.0 Host bridge: Intel Corporation 82945G/GZ/P/PL Memory
Controller Hub (rev 02)
00:02.0 VGA compatible controller: Intel Corporation 82945G/GZ
Integrated Graphics Controller (rev 02)
00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High
Definition Audio Controller (rev 01)
00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
Port 1 (rev 01)
00:1c.1 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express
Port 2 (rev 01)
00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #1 (rev 01)
00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #2 (rev 01)
00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #3 (rev 01)
00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB
UHCI Controller #4 (rev 01)
00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2
EHCI Controller (rev 01)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1)
00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
Interface Bridge (rev 01)
00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE
Controller (rev 01)
00:1f.2 IDE interface: Intel Corporation 82801GB/GR/GH (ICH7 Family)
SATA IDE Controller (rev 01)
00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 02)



From svn at coreboot.org  Sat Apr  4 14:52:28 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 14:52:28 +0200
Subject: [coreboot] [v2] r4062 - in trunk/coreboot-v2/src/mainboard:
	embeddedplanet/ep405pc totalimpact/briq
Message-ID: <mailman.2939.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-04 14:52:28 +0200 (Sat, 04 Apr 2009)
New Revision: 4062

Modified:
   trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb
   trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb
Log:
fix configuration step of totalimpact briq and embeddedplanet ep405pc.
(trivial).

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb	2009-04-04 10:01:21 UTC (rev 4061)
+++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb	2009-04-04 12:52:28 UTC (rev 4062)
@@ -33,6 +33,7 @@
 #uses IDE_SWAB
 uses IDE_OFFSET 
 uses ROM_SIZE
+uses ROM_IMAGE_SIZE
 uses _RESET
 uses _EXCEPTION_VECTORS
 uses _ROMBASE

Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb	2009-04-04 10:01:21 UTC (rev 4061)
+++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb	2009-04-04 12:52:28 UTC (rev 4062)
@@ -24,6 +24,7 @@
 uses IDE_BOOT_DRIVE
 uses IDE_SWAB IDE_OFFSET 
 uses ROM_SIZE
+uses ROM_IMAGE_SIZE
 uses _RESET
 uses _EXCEPTION_VECTORS
 uses _ROMBASE




From svn at coreboot.org  Sat Apr  4 15:05:18 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 15:05:18 +0200
Subject: [coreboot] [v2] r4063 - trunk/coreboot-v2/util/romtool
Message-ID: <mailman.2940.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-04 15:05:18 +0200 (Sat, 04 Apr 2009)
New Revision: 4063

Modified:
   trunk/coreboot-v2/util/romtool/Makefile
Log:
use $(MAKE) instead of hardcoded "make".. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/util/romtool/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 12:52:28 UTC (rev 4062)
+++ trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 13:05:18 UTC (rev 4063)
@@ -9,7 +9,7 @@
 	$(CC) -o $@ $(OBJ)
 
 tools/rom-mkpayload tools/rom-mkstage:
-	make -C tools/ $(patsubst tools/%, %, $@)
+	$(MAKE) -C tools/ $(patsubst tools/%, %, $@)
 
 %.o: %.c
 	$(CC) -g -Wall -Werror -c -o $@ $<
@@ -23,5 +23,5 @@
 tags: 
 	ctags *.[ch] */*.[ch]
 clean:
-	make -C tools/ clean
+	$(MAKE) -C tools/ clean
 	rm -f *.o romtool




From info at coresystems.de  Sat Apr  4 15:15:09 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 15:15:09 +0200
Subject: [coreboot] build service results for r4062
Message-ID: <E1Lq5iH-00029l-0t@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4062 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix configuration step of totalimpact briq and embeddedplanet ep405pc.
(trivial).

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4062&device=atc-6220&vendor=a-trend&num=2
Configuration of embeddedplanet:ep405pc has been fixed
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4062&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Configuration of totalimpact:briq has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Apr  4 15:20:33 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 15:20:33 +0200
Subject: [coreboot] [v2] r4064 - trunk/coreboot-v2/util/romcc
Message-ID: <mailman.2941.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-04 15:20:33 +0200 (Sat, 04 Apr 2009)
New Revision: 4064

Modified:
   trunk/coreboot-v2/util/romcc/romcc.c
Log:
fix some warnings by casting safely. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/util/romcc/romcc.c
===================================================================
--- trunk/coreboot-v2/util/romcc/romcc.c	2009-04-04 13:05:18 UTC (rev 4063)
+++ trunk/coreboot-v2/util/romcc/romcc.c	2009-04-04 13:20:33 UTC (rev 4064)
@@ -20340,8 +20340,8 @@
 	struct ssa_edge *sedge)
 {
 	if (state->compiler->debug & DEBUG_SCC_TRANSFORM2) {
-		fprintf(state->errout, "adding sedge: %5d (%4d -> %5d)\n",
-			sedge - scc->ssa_edges,
+		fprintf(state->errout, "adding sedge: %5ld (%4d -> %5d)\n",
+			(long)(sedge - scc->ssa_edges),
 			sedge->src->def->id,
 			sedge->dst->def->id);
 	}
@@ -20350,8 +20350,8 @@
 		(sedge->work_prev != sedge)) {
 
 		if (state->compiler->debug & DEBUG_SCC_TRANSFORM2) {
-			fprintf(state->errout, "dupped sedge: %5d\n",
-				sedge - scc->ssa_edges);
+			fprintf(state->errout, "dupped sedge: %5ld\n",
+				(long)(sedge - scc->ssa_edges));
 		}
 		return;
 	}
@@ -23843,12 +23843,12 @@
 	long ref;
 	ref = next_label(state);
 	fprintf(fp, ".section \"" DATA_SECTION "\"\n");
-	fprintf(fp, ".balign %d\n", align_of_in_bytes(state, ins->type));
+	fprintf(fp, ".balign %ld\n", align_of_in_bytes(state, ins->type));
 	fprintf(fp, "L%s%lu:\n", state->compiler->label_prefix, ref);
 	print_const(state, ins, fp);
 	fill_bytes = bits_to_bytes(size - size_of(state, ins->type));
 	if (fill_bytes) {
-		fprintf(fp, ".fill %d, 1, 0\n", fill_bytes);
+		fprintf(fp, ".fill %ld, 1, 0\n", fill_bytes);
 	}
 	fprintf(fp, ".section \"" TEXT_SECTION "\"\n");
 	return ref;
@@ -24657,7 +24657,7 @@
 	struct triple *ins, FILE *fp)
 {
 	fprintf(fp, ".section \"" DATA_SECTION "\"\n");
-	fprintf(fp, ".balign %d\n", align_of_in_bytes(state, ins->type));
+	fprintf(fp, ".balign %ld\n", align_of_in_bytes(state, ins->type));
 	fprintf(fp, "L%s%lu:\n", 
 		state->compiler->label_prefix, (unsigned long)(ins->u.cval));
 	print_const(state, MISC(ins, 0), fp);




From svn at coreboot.org  Sat Apr  4 15:28:41 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 15:28:41 +0200
Subject: [coreboot] [v2] r4065 - trunk/coreboot-v2/src/lib
Message-ID: <mailman.2942.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-04 15:28:40 +0200 (Sat, 04 Apr 2009)
New Revision: 4065

Modified:
   trunk/coreboot-v2/src/lib/lzmadecode.c
Log:
fix variable shadowing in lzmadecode.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/lib/lzmadecode.c
===================================================================
--- trunk/coreboot-v2/src/lib/lzmadecode.c	2009-04-04 13:20:33 UTC (rev 4064)
+++ trunk/coreboot-v2/src/lib/lzmadecode.c	2009-04-04 13:28:40 UTC (rev 4065)
@@ -53,7 +53,7 @@
 
 #define RangeDecoderBitTreeDecode(probs, numLevels, res) \
   { int i = numLevels; res = 1; \
-  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
+  do { CProb *cp = probs + res; RC_GET_BIT(cp, res) } while(--i != 0); \
   res -= (1 << numLevels); }
 
 




From info at coresystems.de  Sat Apr  4 15:38:19 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 15:38:19 +0200
Subject: [coreboot] build service results for r4063
Message-ID: <E1Lq64h-0007yv-HQ@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4063 to
the coreboot repository. This caused the following 
changes:

Change Log:
use $(MAKE) instead of hardcoded "make".. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4063&device=atc-6220&vendor=a-trend&num=2
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4063&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4063&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4063&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Apr  4 16:02:24 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 16:02:24 +0200
Subject: [coreboot] build service results for r4064
Message-ID: <E1Lq6S0-0004vS-8H@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4064 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix some warnings by casting safely. (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 has been fixed
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4064&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4064&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4064&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Apr  4 16:30:11 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 16:30:11 +0200
Subject: [coreboot] build service results for r4065
Message-ID: <E1Lq6st-0002ng-B4@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4065 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix variable shadowing in lzmadecode.c (trivial)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4065&device=atc-6220&vendor=a-trend&num=2
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4065&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4065&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4065&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Sat Apr  4 17:52:11 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 4 Apr 2009 08:52:11 -0700
Subject: [coreboot] Will coreboot work on GIGABYTE I945 chipset?
In-Reply-To: <6f7a5ee80904040504t377dba50pe469ff8086b9c739@mail.gmail.com>
References: <6f7a5ee80904040504t377dba50pe469ff8086b9c739@mail.gmail.com>
Message-ID: <13426df10904040852q4f488690g712d734f6a568873@mail.gmail.com>

On Sat, Apr 4, 2009 at 5:04 AM, Dimitri Pekarovsky
<dimitri.pekarovsky at gmail.com> wrote:
> Hi, dear ALL.
>
> Could anyone say me if coreboot will work on my GIGABYTE
> GA-945GCM-S2L, 945GC / Socket 775?

It looks like it ought to work.

ron



From stepan at coresystems.de  Sat Apr  4 18:24:29 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 04 Apr 2009 18:24:29 +0200
Subject: [coreboot] Will coreboot work on GIGABYTE I945 chipset?
In-Reply-To: <6f7a5ee80904040511o3523a2bcmfd384b586dabc78f@mail.gmail.com>
References: <6f7a5ee80904040504t377dba50pe469ff8086b9c739@mail.gmail.com>
	<6f7a5ee80904040511o3523a2bcmfd384b586dabc78f@mail.gmail.com>
Message-ID: <49D789BD.50702@coresystems.de>

On 04.04.2009 14:11 Uhr, Dimitri Pekarovsky wrote:
> Sorry, for double post.
> I forgotten to attach listings.
>
> Could anyone say me if coreboot will work on my GIGABYTE
> GA-945GCM-S2L, 945GC / Socket 775?
> Data, as described in Wiki, is below.
> //W.respect. D.P.
>
> motherboard page:
> http://www.gigabyte.eu/Products/Motherboard/Products_Spec.aspx?ProductID=2669
>
> Intel(R) Pentium(R) Dual  CPU  E2180  @ 2.00GHz stepping 0d
>   

You might run into trouble because the i945 code has only been running
on mobile chipsets so far (FSB 667 vs FSB 1066).

It shouldn't be a big deal to get this working, but you should
definitely make sure you have an SPI writer (such as the dediprog sf100)
around in case something goes wrong. Alternatively you can try to put a
socket or a second bios chip on the board, see
http://www.coreboot.org/GIGABYTE_GA-M57SLI-S4_Build_Tutorial#SOIC_hardware_hack
for more details.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Sat Apr  4 20:16:12 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 20:16:12 +0200
Subject: [coreboot] [v2] r4066 - trunk/coreboot-v2/util/abuild
Message-ID: <mailman.2943.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-04 20:16:11 +0200 (Sat, 04 Apr 2009)
New Revision: 4066

Modified:
   trunk/coreboot-v2/util/abuild/abuild
Log:
fix cross compilation in abuild for certain scenarios 
(coreboot.org build system internal)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/util/abuild/abuild
===================================================================
--- trunk/coreboot-v2/util/abuild/abuild	2009-04-04 13:28:40 UTC (rev 4065)
+++ trunk/coreboot-v2/util/abuild/abuild	2009-04-04 18:16:11 UTC (rev 4066)
@@ -5,7 +5,7 @@
 #  This script builds coreboot images for all available targets.
 #
 #  (C) 2004 by Stefan Reinauer <stepan at openbios.org>
-#  (C) 2006-2008 by coresystems GmbH <info at coresystems.de>
+#  (C) 2006-2009 by coresystems GmbH <info at coresystems.de>
 #
 #  This file is subject to the terms and conditions of the GNU General
 #  Public License. See the file COPYING in the main directory of this
@@ -14,8 +14,8 @@
 
 #set -x # Turn echo on....
 
-ABUILD_DATE="May 27th, 2008"
-ABUILD_VERSION="0.7"
+ABUILD_DATE="April 3rd, 2009"
+ABUILD_VERSION="0.8"
 
 # Where shall we place all the build trees?
 TARGET=$( pwd )/coreboot-builds
@@ -110,8 +110,9 @@
 {
 	VENDOR=$1
 	MAINBOARD=$2
-	cat $LBROOT/src/mainboard/$VENDOR/$MAINBOARD/Config.lb | \
-		grep ^arch | cut -f 2 -d\ 
+	ARCH=`cat $LBROOT/src/mainboard/$VENDOR/$MAINBOARD/Config.lb | \
+		grep ^arch | cut -f 2 -d\ `
+	echo $ARCH | sed s/ppc/powerpc/
 }
 
 function create_config
@@ -335,12 +336,11 @@
 	found_crosscompiler=false
 	if which $TARCH-elf-gcc 2>/dev/null >/dev/null; then
 		# i386-elf target needs --divide, for i386-linux, that's the default
-		CC="$TARCH-elf-gcc"
 		if [ "$TARCH" = "i386" ]; then
 			CC="$CC -Wa,--divide"
 		fi
-		echo using $CC
 		CROSS_COMPILE="$TARCH-elf-"
+		echo using $CROSS_COMPILE$CC
 		found_crosscompiler=true
 	fi
 




From svn at coreboot.org  Sat Apr  4 20:24:21 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 20:24:21 +0200
Subject: [coreboot] [v2] r4067 - in trunk/coreboot-v2/util: newconfig
	romtool romtool/tools romtool/tools/lzma
Message-ID: <mailman.2944.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-04 20:24:21 +0200 (Sat, 04 Apr 2009)
New Revision: 4067

Modified:
   trunk/coreboot-v2/util/newconfig/config.g
   trunk/coreboot-v2/util/romtool/Makefile
   trunk/coreboot-v2/util/romtool/tools/Makefile
   trunk/coreboot-v2/util/romtool/tools/lzma/Makefile
Log:
build romtool in mainboard target directory.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2009-04-04 18:16:11 UTC (rev 4066)
+++ trunk/coreboot-v2/util/newconfig/config.g	2009-04-04 18:24:21 UTC (rev 4067)
@@ -2231,8 +2231,7 @@
 	file.write("\n\n")	
 
 	# romtool rules
-	file.write("\nromtool:\n\t$(MAKE) -C $(TOP)/util/romtool\n\tmkdir -p tools\n")
-	file.write("\tcp $(TOP)/util/romtool/tools/rom-mkpayload $(TOP)/util/romtool/tools/rom-mkstage tools\n\tcp $(TOP)/util/romtool/romtool romtool\n")
+	file.write("\nromtool:\n\tmkdir -p tools/lzma\n\t$(MAKE) -C $(TOP)/util/romtool obj=$(shell pwd)\n\n")
 
 	file.write("include Makefile.settings\n\n")
 	for i, o in romimages.items():

Modified: trunk/coreboot-v2/util/romtool/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 18:16:11 UTC (rev 4066)
+++ trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 18:24:21 UTC (rev 4067)
@@ -1,27 +1,38 @@
+#
+#
+#
+
+obj ?= $(shell pwd)
+
 COMMANDS=create.o bootblock.o delete.o add.o print.o resize.o
-OBJ= $(COMMANDS) romtool.o util.o fs.o
+OBJ=$(COMMANDS) romtool.o util.o fs.o
+
+CC=gcc
+CFLAGS=-g -Wall -W #-Werror
+
 H=romtool.h
-DESTDIR=/usr/local/bin
+DESTDIR ?= /usr/local/bin
 
-all: romtool tools/rom-mkpayload tools/rom-mkstage
+all: $(obj)/romtool $(obj)/tools/rom-mkpayload $(obj)/tools/rom-mkstage
 
-romtool: $(OBJ) 
-	$(CC) -o $@ $(OBJ)
+$(obj)/romtool: $(patsubst %,$(obj)/%,$(OBJ))
+	$(CC) -o $@ $(patsubst %,$(obj)/%,$(OBJ))
 
-tools/rom-mkpayload tools/rom-mkstage:
-	$(MAKE) -C tools/ $(patsubst tools/%, %, $@)
+$(obj)/tools/rom-mkpayload $(obj)/tools/rom-mkstage:
+	$(MAKE) -C tools/ obj=$(obj)/tools $(patsubst tools/%, %, $@)
 
-%.o: %.c
-	$(CC) -g -Wall -Werror -c -o $@ $<
+$(obj)/%.o: %.c
+	$(CC) $(CFLAGS) -c -o $@ $<
 
-install: romtool tools/rom-mkpayload tools/rom-mkstage
+install: $(obj)/romtool $(obj)/tools/rom-mkpayload $(obj)/tools/rom-mkstage
 	@ install -d $(DESTDIR)
-	@ install -m 0755 romtool $(DESTDIR)/romtool
-	@ install -m 0755 tools/rom-mkstage $(DESTDIR)/rom-mkstage
-	@ install -m 0755 tools/rom-mkpayload $(DESTDIR)/rom-mkpayload
+	@ install -m 0755 $(obj)/romtool $(DESTDIR)/romtool
+	@ install -m 0755 $(obj)/tools/rom-mkstage $(DESTDIR)/rom-mkstage
+	@ install -m 0755 $(obj)/tools/rom-mkpayload $(DESTDIR)/rom-mkpayload
 
 tags: 
 	ctags *.[ch] */*.[ch]
+
 clean:
 	$(MAKE) -C tools/ clean
-	rm -f *.o romtool
+	rm -f $(patsubst %,$(obj)/%,$(OBJ)) $(obj)/romtool

Modified: trunk/coreboot-v2/util/romtool/tools/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/tools/Makefile	2009-04-04 18:16:11 UTC (rev 4066)
+++ trunk/coreboot-v2/util/romtool/tools/Makefile	2009-04-04 18:24:21 UTC (rev 4067)
@@ -1,27 +1,25 @@
+obj ?= $(shell pwd)
+
 CC=gcc
-CFLAGS=-Wall -Werror -g
+CFLAGS=-Wall -W -Werror -g
 
-LZMA_OBJ := lzma/LZMAEncoder.o lzma/LZInWindow.o
-LZMA_OBJ += lzma/RangeCoderBit.o lzma/StreamUtils.o
-LZMA_OBJ += lzma/OutBuffer.o lzma/Alloc.o
-LZMA_OBJ += lzma/CRC.o
-LZMA_OBJ += lzma/lzma-compress.o
+all: rom-mkstage rom-mkpayload
 
+include lzma/Makefile
+
 COMMON= common.o compress.o $(LZMA_OBJ)
 
-all: rom-mkstage rom-mkpayload
 
-rom-mkstage: rom-mkstage.o $(COMMON)
-	$(CXX) -g -o $@ rom-mkstage.o $(COMMON)
+$(obj)/rom-mkstage: $(obj)/rom-mkstage.o $(patsubst %,$(obj)/%,$(COMMON))
+	$(CXX) -g -o $@ $(obj)/rom-mkstage.o $(patsubst %,$(obj)/%,$(COMMON))
 
-rom-mkpayload: rom-mkpayload.o $(COMMON)
-	$(CXX) -o $@ rom-mkpayload.o $(COMMON)
+$(obj)/rom-mkpayload: $(obj)/rom-mkpayload.o $(patsubst %,$(obj)/%,$(COMMON))
+	$(CXX) -o $@ $(obj)/rom-mkpayload.o $(patsubst %,$(obj)/%,$(COMMON))
 
-include lzma/Makefile
-
-%.o: %.c
+$(obj)/%.o: %.c
 	$(CC) -Wall -Werror -g -c -o $@ $<
 
 clean:
 	@ rm -f rom-mkpayload.o rom-mkstage.o $(COMMON)
 	@ rm -f rom-mkpayload rom-mkstage
+

Modified: trunk/coreboot-v2/util/romtool/tools/lzma/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/tools/lzma/Makefile	2009-04-04 18:16:11 UTC (rev 4066)
+++ trunk/coreboot-v2/util/romtool/tools/lzma/Makefile	2009-04-04 18:24:21 UTC (rev 4067)
@@ -24,27 +24,27 @@
 LZMA_OBJ += lzma/CRC.o
 LZMA_OBJ += lzma/lzma-compress.o
 
-lzma/lzma-compress.o: lzma/minilzma.cc
+$(obj)/lzma/lzma-compress.o: lzma/minilzma.cc
 	g++ -o $@ -c -DCOMPACT $<
 
-lzma/%.o: lzma/C/7zip/Compress/LZMA/%.cpp
+$(obj)/lzma/%.o: lzma/C/7zip/Compress/LZMA/%.cpp
 	g++ -o $@ -c $<
 
-lzma/%.o: lzma/C/7zip/Compress/LZ/%.cpp
+$(obj)/lzma/%.o: lzma/C/7zip/Compress/LZ/%.cpp
 	g++ -o $@ -c $<
 
-lzma/%.o: lzma/C/7zip/Compress/RangeCoder/%.cpp
+$(obj)/lzma/%.o: lzma/C/7zip/Compress/RangeCoder/%.cpp
 	g++ -o $@ -c $<
 
-lzma/%.o: lzma/C/7zip/Decompress/%.cpp
+$(obj)/lzma/%.o: lzma/C/7zip/Decompress/%.cpp
 	g++ -o $@ -c $<
 
-lzma/%.o: lzma/C/7zip/Common/%.cpp
+$(obj)/lzma/%.o: lzma/C/7zip/Common/%.cpp
 	g++ -o $@ -c $<
 
-lzma/%.o: lzma/C/Common/%.cpp
+$(obj)/lzma/%.o: lzma/C/Common/%.cpp
 	g++ -o $@ -c $<
 
-lzma/%.o: lzma/%.cc
+$(obj)/lzma/%.o: lzma/%.cc
 	g++ -o $@ -c $<
 




From info at coresystems.de  Sat Apr  4 20:37:41 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 20:37:41 +0200
Subject: [coreboot] build service results for r4066
Message-ID: <E1LqAkP-0007Vy-35@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4066 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix cross compilation in abuild for certain scenarios
(coreboot.org build system internal)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 has been fixed
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4066&device=ep405pc&vendor=embeddedplanet&num=2
Board motorola:sandpoint has been added.
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4066&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4066&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Apr  4 20:40:46 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  4 Apr 2009 20:40:46 +0200
Subject: [coreboot] [v2] r4068 - trunk/coreboot-v2/src/arch/ppc
Message-ID: <mailman.2945.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-04 20:40:46 +0200 (Sat, 04 Apr 2009)
New Revision: 4068

Modified:
   trunk/coreboot-v2/src/arch/ppc/Config.lb
Log:
small workaround for romtool incompatibility with ppc ports

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/arch/ppc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-04-04 18:24:21 UTC (rev 4067)
+++ trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-04-04 18:40:46 UTC (rev 4068)
@@ -1,10 +1,15 @@
 ldscript init/ldscript.lb
 
-makerule coreboot.rom 
+makerule coreboot.strip 
 	depends	"coreboot" 
 	action	"cp $< $@"
 end
 
+makerule coreboot.rom 
+	depends	"coreboot.strip" 
+	action "cp $< $@"
+end
+
 dir init
 dir lib
 dir boot




From info at coresystems.de  Sat Apr  4 21:06:43 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 21:06:43 +0200
Subject: [coreboot] build service results for r4067
Message-ID: <E1LqBCV-0000VM-7T@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4067 to
the coreboot repository. This caused the following 
changes:

Change Log:
build romtool in mainboard target directory.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of a-trend:atc-6240 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=atc-6240&vendor=a-trend&num=2
Compilation of advantech:pcm-5820 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=db800&vendor=amd&num=2
Compilation of amd:rumba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=rumba&vendor=amd&num=2
Compilation of amd:serengeti_cheetah has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=serengeti_cheetah&vendor=amd&num=2
Compilation of asi:mb_5blmp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:mew-vm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=mew-vm&vendor=asus&num=2
Compilation of digitallogic:msm800sev has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=msm800sev&vendor=digitallogic&num=2
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of emulation:qemu-x86 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga_2761gxdk has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=ga_2761gxdk&vendor=gigabyte&num=2
Compilation of gigabyte:m57sli has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=m57sli&vendor=gigabyte&num=2
Compilation of iei:juki-511p has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=juki-511p&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:truxton has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=truxton&vendor=intel&num=2
Compilation of iwill:dk8x has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=dk8x&vendor=iwill&num=2
Compilation of lippert:roadrunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=roadrunner-lx&vendor=lippert&num=2
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6178 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=ms6178&vendor=msi&num=2
Compilation of msi:ms7135 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=ms7135&vendor=msi&num=2
Compilation of msi:ms9282 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=ms9282&vendor=msi&num=2
Compilation of olpc:rev_a has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=rev_a&vendor=olpc&num=2
Compilation of supermicro:h8dmr has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=h8dmr&vendor=supermicro&num=2
Compilation of televideo:tc7020 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=tc7020&vendor=televideo&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=briq&vendor=totalimpact&num=2
Compilation of tyan:s2875 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=s2875&vendor=tyan&num=2
Compilation of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4067&device=s2895&vendor=tyan&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Apr  4 21:32:47 2009
From: info at coresystems.de (coreboot information)
Date: Sat, 04 Apr 2009 21:32:47 +0200
Subject: [coreboot] build service results for r4068
Message-ID: <E1LqBbj-0000Cc-7x@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4068 to
the coreboot repository. This caused the following 
changes:

Change Log:
small workaround for romtool incompatibility with ppc ports

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 has been fixed
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 has been fixed
Compilation of amd:norwich has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=norwich&vendor=amd&num=2
Compilation of amd:rumba has been fixed
Compilation of amd:serengeti_cheetah has been fixed
Compilation of arima:hdama has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=hdama&vendor=arima&num=2
Compilation of asi:mb_5blgp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp has been fixed
Compilation of asus:a8v-e_se has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=a8v-e_se&vendor=asus&num=2
Compilation of asus:mew-vm has been fixed
Compilation of asus:p2b-ds has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=p2b-ds&vendor=asus&num=2
Compilation of bcom:winnet100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=winnet100&vendor=bcom&num=2
Compilation of digitallogic:adl855pc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=msm800sev&vendor=digitallogic&num=2
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga_2761gxdk is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=ga_2761gxdk&vendor=gigabyte&num=2
Compilation of gigabyte:m57sli has been fixed
Compilation of ibm:e325 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=e325&vendor=ibm&num=2
Compilation of iei:juki-511p has been fixed
Compilation of iei:pcisa-lx-800-r10 has been fixed
Compilation of intel:truxton has been fixed
Compilation of iwill:dk8x is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=dk8x&vendor=iwill&num=2
Compilation of lippert:roadrunner-lx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=roadrunner-lx&vendor=lippert&num=2
Compilation of lippert:spacerunner-lx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=spacerunner-lx&vendor=lippert&num=2
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6147 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 has been fixed
Compilation of msi:ms7135 has been fixed
Compilation of msi:ms7260 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=ms7260&vendor=msi&num=2
Compilation of msi:ms9282 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=ms9282&vendor=msi&num=2
Compilation of nec:powermate2000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=powermate2000&vendor=nec&num=2
Compilation of olpc:rev_a has been fixed
Compilation of supermicro:h8dmr has been fixed
Compilation of technologic:ts5300 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=ip1000&vendor=thomson&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=briq&vendor=totalimpact&num=2
Compilation of tyan:s1846 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=s1846&vendor=tyan&num=2
Compilation of tyan:s2875 has been fixed
Compilation of tyan:s2880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=s2880&vendor=tyan&num=2
Compilation of tyan:s2885 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=s2885&vendor=tyan&num=2
Compilation of tyan:s2895 has been fixed
Compilation of tyan:s4880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=s4880&vendor=tyan&num=2
Compilation of tyan:s4882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4068&device=s4882&vendor=tyan&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mjt at nysv.org  Sat Apr  4 22:38:32 2009
From: mjt at nysv.org (Markus Törnqvist)
Date: Sat, 4 Apr 2009 23:38:32 +0300
Subject: [coreboot] VIA Epia-MII CF question
In-Reply-To: <20090403215726.GR638@nysv.org>
References: <20090403215726.GR638@nysv.org>
Message-ID: <20090404203832.GS638@nysv.org>

On Sat, Apr 04, 2009 at 12:57:26AM +0300, Markus T?rnqvist wrote:
>Hi again!

[...]

>The wiki "lets me" either use the CF slot as standard ide or through
>pcmcia-utils.
>
>This standard-ide approach, as said, did not work.
>
>Is the wiki wrong?

Did some Sherlocking around and it seems the wiki is outdated.
And slightly wrong.

The mentioned scripts there, mkcfinitrd and pcinitrd are
apparently for pcmcia-cs, because they use cardmgr, which
was apparently deprecated at kernel 2.6.13

http://www.kernel.org/pub/linux/utils/kernel/pcmcia/cardmgr-to-pcmciautils.html

Also, the wiki says "the mkcfinitrd script is at the end of the howto",
which it is not, and was found only through Google at
http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/documentation/HOWTO/EPIA-M-howto#L467

There's a HOWTO which is really helpful when doing pcmcia stuff for
the first time
http://www.kernel.org/pub/linux/utils/kernel/pcmcia/howto.html

and itwould be nice if the wiki reflected how this is relevant to
booting off the cf nowadays.

Also the parts about probing for ide don't seem to be true, no such
bootparam is needed here.

So here's what had to be done for this to work with Ubuntu, should
be pretty distro-generic even for non-debian-based systems:

### Extract initrd for work
root at install:/target/boot/initrd# zcat ../initrd.img-2.6.24-22-generic | cpio -i
32850 blocks


### Copy missing things over
root at install:/target/boot/initrd# cp /lib/modules/2.6.24-22-generic/kernel/drivers/pcmcia/yenta_socket.ko /lib/modules/2.6.24-22-generic/kernel/drivers/pcmcia/rsrc_nonstatic.ko lib/modules/2.6.24-22-generic/kernel/drivers/pcmcia/

### Copy udev file
root at install:/target/boot/initrd# cp /etc/udev/rules.d/85-pcmcia.rules etc/udev/rules.d/

### Copy helpers
root at install:/target/boot/initrd# cp /lib/udev/pcmcia-socket-startup /lib/udev/pcmcia-check-broken-cis lib/udev/

### Copy libsysfs so we can execute
root at install:/target/boot/initrd# cp -p /lib/libsysfs.so.2* lib/

### Copy options
root at install:/target/boot/initrd# mkdir etc/pcmcia
root at install:/target/boot/initrd# cp /etc/pcmcia/config.opts etc/pcmcia/


### Create initrd
root at install:/target/boot/initrd# find . | cpio -H newc -o > ../initrd.img-2.6.24-22-generic.mjt.cpio
root at install:/target/boot/initrd# cd ..
root at install:/target/boot# gzip initrd.img-2.6.24-22-generic.mjt.cpio
root at install:/target/boot# cd ..
root at install:/target# ln -sf boot/initrd.img-2.6.24-22-generic.mjt.cpio.gz initrd.img

Thanks!

-- 
mjt




From stepan at coresystems.de  Sun Apr  5 00:14:38 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 05 Apr 2009 00:14:38 +0200
Subject: [coreboot] [PATCH] fix race in romtool makefiles.
Message-ID: <49D7DBCE.1070509@coresystems.de>

See attachment

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

-------------- next part --------------
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Name: romtool-race.diff
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090405/bdbd101a/attachment.ksh>

From svn at coreboot.org  Sun Apr  5 00:18:26 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Apr 2009 00:18:26 +0200
Subject: [coreboot] [v2] r4069 - in trunk/coreboot-v2/util/romtool: . tools
	tools/lzma
Message-ID: <mailman.2946.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-05 00:18:26 +0200 (Sun, 05 Apr 2009)
New Revision: 4069

Modified:
   trunk/coreboot-v2/util/romtool/Makefile
   trunk/coreboot-v2/util/romtool/tools/Makefile
   trunk/coreboot-v2/util/romtool/tools/lzma/Makefile
   trunk/coreboot-v2/util/romtool/tools/rom-mkpayload.c
Log:
This fixes a race condition (revealed by my other check-in r4067) in the
romtool by changing the Makefiles to be no longer recursive (once again,
recursive make is to be considered harmful).  Tried to (quickly) unify most of
the Makefile code, but medium-term this is going to be worked on for Kconfig
support anyways.

Also fix a sign cast error in rom-mkpayload in case people want to compile this
with -W -Werror

Patch relative to coreboot-v2/util/romtool

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
and
Acked-by: Stefan Reinauer <stepan at coresystems.de>
in order to get the tree working decently asap



Modified: trunk/coreboot-v2/util/romtool/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 18:40:46 UTC (rev 4068)
+++ trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 22:18:26 UTC (rev 4069)
@@ -6,11 +6,11 @@
 
 COMMANDS=create.o bootblock.o delete.o add.o print.o resize.o
 OBJ=$(COMMANDS) romtool.o util.o fs.o
+INC=romtool.h romfs.h
 
 CC=gcc
-CFLAGS=-g -Wall -W #-Werror
+CFLAGS=-g -Wall # -W -Werror
 
-H=romtool.h
 DESTDIR ?= /usr/local/bin
 
 all: $(obj)/romtool $(obj)/tools/rom-mkpayload $(obj)/tools/rom-mkstage
@@ -18,10 +18,12 @@
 $(obj)/romtool: $(patsubst %,$(obj)/%,$(OBJ))
 	$(CC) -o $@ $(patsubst %,$(obj)/%,$(OBJ))
 
-$(obj)/tools/rom-mkpayload $(obj)/tools/rom-mkstage:
-	$(MAKE) -C tools/ obj=$(obj)/tools $(patsubst tools/%, %, $@)
+tobj = $(obj)/tools
+tsrc = $(shell pwd)/tools
 
-$(obj)/%.o: %.c
+include tools/Makefile
+
+$(obj)/%.o: %.c $(INC)
 	$(CC) $(CFLAGS) -c -o $@ $<
 
 install: $(obj)/romtool $(obj)/tools/rom-mkpayload $(obj)/tools/rom-mkstage
@@ -33,6 +35,6 @@
 tags: 
 	ctags *.[ch] */*.[ch]
 
-clean:
-	$(MAKE) -C tools/ clean
+clean: tools-clean
 	rm -f $(patsubst %,$(obj)/%,$(OBJ)) $(obj)/romtool
+

Modified: trunk/coreboot-v2/util/romtool/tools/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/tools/Makefile	2009-04-04 18:40:46 UTC (rev 4068)
+++ trunk/coreboot-v2/util/romtool/tools/Makefile	2009-04-04 22:18:26 UTC (rev 4069)
@@ -1,25 +1,24 @@
-obj ?= $(shell pwd)
+tobj ?= $(shell pwd)
+tsrc ?= $(shell pwd)
 
-CC=gcc
-CFLAGS=-Wall -W -Werror -g
+TARGETS += $(tobj)/rom-mkstage $(tobj)/rom-mkpayload
 
-all: rom-mkstage rom-mkpayload
+tools: $(tobj)/rom-mkstage $(tobj)/rom-mkpayload
 
-include lzma/Makefile
+include $(tobj)/lzma/Makefile
 
-COMMON= common.o compress.o $(LZMA_OBJ)
+COMMON = common.o compress.o $(LZMA_OBJ)
 
+$(tobj)/rom-mkstage: $(tobj)/rom-mkstage.o $(patsubst %,$(tobj)/%,$(COMMON))
+	$(CXX) $(CFLAGS) -o $@ $^
 
-$(obj)/rom-mkstage: $(obj)/rom-mkstage.o $(patsubst %,$(obj)/%,$(COMMON))
-	$(CXX) -g -o $@ $(obj)/rom-mkstage.o $(patsubst %,$(obj)/%,$(COMMON))
+$(tobj)/rom-mkpayload: $(tobj)/rom-mkpayload.o $(patsubst %,$(tobj)/%,$(COMMON))
+	$(CXX) $(CFLAGS) -o $@ $^
 
-$(obj)/rom-mkpayload: $(obj)/rom-mkpayload.o $(patsubst %,$(obj)/%,$(COMMON))
-	$(CXX) -o $@ $(obj)/rom-mkpayload.o $(patsubst %,$(obj)/%,$(COMMON))
+$(tobj)/%.o: %.c
+	$(CC) $(CFLAGS) -c -o $@ $<
 
-$(obj)/%.o: %.c
-	$(CC) -Wall -Werror -g -c -o $@ $<
+tools-clean:
+	rm -f $(tobj)/rom-mkpayload.o $(tobj)/rom-mkstage.o $(patsubst %,$(tobj)/%,$(COMMON))
+	rm -f $(tobj)/rom-mkpayload $(tobj)/rom-mkstage
 
-clean:
-	@ rm -f rom-mkpayload.o rom-mkstage.o $(COMMON)
-	@ rm -f rom-mkpayload rom-mkstage
-

Modified: trunk/coreboot-v2/util/romtool/tools/lzma/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/tools/lzma/Makefile	2009-04-04 18:40:46 UTC (rev 4068)
+++ trunk/coreboot-v2/util/romtool/tools/lzma/Makefile	2009-04-04 22:18:26 UTC (rev 4069)
@@ -24,27 +24,27 @@
 LZMA_OBJ += lzma/CRC.o
 LZMA_OBJ += lzma/lzma-compress.o
 
-$(obj)/lzma/lzma-compress.o: lzma/minilzma.cc
-	g++ -o $@ -c -DCOMPACT $<
+$(tobj)/lzma/lzma-compress.o: $(tsrc)/lzma/minilzma.cc
+	$(CXX) $(CFLAGS) -o $@ -c -DCOMPACT $<
 
-$(obj)/lzma/%.o: lzma/C/7zip/Compress/LZMA/%.cpp
-	g++ -o $@ -c $<
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Compress/LZMA/%.cpp
+	$(CXX) $(CFLAGS) -o $@ -c $<
 
-$(obj)/lzma/%.o: lzma/C/7zip/Compress/LZ/%.cpp
-	g++ -o $@ -c $<
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Compress/LZ/%.cpp
+	$(CXX) $(CFLAGS) -o $@ -c $<
 
-$(obj)/lzma/%.o: lzma/C/7zip/Compress/RangeCoder/%.cpp
-	g++ -o $@ -c $<
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Compress/RangeCoder/%.cpp
+	$(CXX) $(CFLAGS) -o $@ -c $<
 
-$(obj)/lzma/%.o: lzma/C/7zip/Decompress/%.cpp
-	g++ -o $@ -c $<
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Decompress/%.cpp
+	$(CXX) $(CFLAGS) -o $@ -c $<
 
-$(obj)/lzma/%.o: lzma/C/7zip/Common/%.cpp
-	g++ -o $@ -c $<
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Common/%.cpp
+	$(CXX) $(CFLAGS) -o $@ -c $<
 
-$(obj)/lzma/%.o: lzma/C/Common/%.cpp
-	g++ -o $@ -c $<
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/Common/%.cpp
+	$(CXX) $(CFLAGS) -o $@ -c $<
 
-$(obj)/lzma/%.o: lzma/%.cc
-	g++ -o $@ -c $<
+$(tobj)/lzma/%.o: $(tsrc)/lzma/%.cc
+	$(CXX) $(CFLAGS) -o $@ -c $<
 

Modified: trunk/coreboot-v2/util/romtool/tools/rom-mkpayload.c
===================================================================
--- trunk/coreboot-v2/util/romtool/tools/rom-mkpayload.c	2009-04-04 18:40:46 UTC (rev 4068)
+++ trunk/coreboot-v2/util/romtool/tools/rom-mkpayload.c	2009-04-04 22:18:26 UTC (rev 4069)
@@ -163,7 +163,7 @@
 		/* If the compressed section is larger, then use the
 		   original stuff */
 
-		if (len > phdr[i].p_filesz) {
+		if ((unsigned int)len > phdr[i].p_filesz) {
 			segs[segments].compression = 0;
 			segs[segments].len = htonl(phdr[i].p_filesz);
 




From svn at coreboot.org  Sun Apr  5 00:24:24 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Apr 2009 00:24:24 +0200
Subject: [coreboot] [v2] r4070 -
	trunk/coreboot-v2/src/southbridge/winbond/w83c553
Message-ID: <mailman.2947.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-05 00:24:23 +0200 (Sun, 05 Apr 2009)
New Revision: 4070

Modified:
   trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
   trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f_ide.c
Log:
fix this warning for the embedded planet ep405pc

/tmp/ccilLWBf.s: Assembler messages:
/tmp/ccilLWBf.s:144: Warning: setting incorrect section attributes for .rodata.pci_driver

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c	2009-04-04 22:18:26 UTC (rev 4069)
+++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c	2009-04-04 22:24:23 UTC (rev 4070)
@@ -188,7 +188,7 @@
 	enable_childrens_resources(dev);
 }
 
-struct device_operations w83c553_ops  = {
+static struct device_operations w83c553_ops  = {
         .read_resources   = pci_dev_read_resources,
         .set_resources    = pci_dev_set_resources,
         .enable_resources = w83c553_enable_resources,
@@ -196,7 +196,7 @@
         .scan_bus         = scan_static_bus,
 };
 
-struct pci_driver w83c553f_pci_driver __pci_driver = {
+static const struct pci_driver w83c553f_pci_driver __pci_driver = {
 	/* w83c553f */
 	.ops = &w83c553_ops,
 	.device = PCI_DEVICE_ID_WINBOND_83C553,

Modified: trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f_ide.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f_ide.c	2009-04-04 22:18:26 UTC (rev 4069)
+++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f_ide.c	2009-04-04 22:24:23 UTC (rev 4070)
@@ -97,7 +97,7 @@
 	printk_info("IDE configuration complete\n");
 }
 
-struct device_operations w83c553_ide_ops  = {
+static struct device_operations w83c553_ide_ops  = {
         .read_resources   = pci_dev_read_resources,
         .set_resources    = pci_dev_set_resources,
         .enable_resources = pci_dev_enable_resources,
@@ -105,7 +105,7 @@
         .scan_bus         = 0,
 };
 
-struct pci_driver w83c553f_ide_pci_driver __pci_driver = {
+static const struct pci_driver w83c553f_ide_pci_driver __pci_driver = {
 	/* w83c553f_ide */
 	.ops = &w83c553_ide_ops,
 	.device = PCI_DEVICE_ID_WINBOND_82C105,




From svn at coreboot.org  Sun Apr  5 00:27:10 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Apr 2009 00:27:10 +0200
Subject: [coreboot] [v2] r4071 - trunk/coreboot-v2/src/stream
Message-ID: <mailman.2948.1355071510.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-05 00:27:10 +0200 (Sun, 05 Apr 2009)
New Revision: 4071

Modified:
   trunk/coreboot-v2/src/stream/ide_stream.c
Log:
fix this warning:
coreboot-v2-4067//src/stream/ide_stream.c: In function 'stream_ide_read':
coreboot-v2-4067//src/stream/ide_stream.c:47: warning: declaration of 'offset' shadows a global declaration
coreboot-v2-4067//src/stream/ide_stream.c:13: warning: shadowed declaration is here

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/stream/ide_stream.c
===================================================================
--- trunk/coreboot-v2/src/stream/ide_stream.c	2009-04-04 22:24:23 UTC (rev 4070)
+++ trunk/coreboot-v2/src/stream/ide_stream.c	2009-04-04 22:27:10 UTC (rev 4071)
@@ -11,6 +11,7 @@
 #endif
 
 static unsigned long offset;
+
 int stream_init(void)
 {
 	int i,res;
@@ -44,7 +45,8 @@
 static unsigned char buffer[512];
 static unsigned int block_num = 0;
 static unsigned int first_fill = 1;
-static byte_offset_t stream_ide_read(void *vdest, byte_offset_t offset, byte_offset_t count)
+
+static byte_offset_t stream_ide_read(void *vdest, byte_offset_t offs, byte_offset_t count)
 {
 	byte_offset_t bytes = 0;
 	unsigned char *dest = vdest;
@@ -54,14 +56,14 @@
 		unsigned int byte_offset, len;
 
 		/* The block is not cached in memory or frist time called */
-		if (block_num != offset / 512 || first_fill) {
-			block_num  = offset / 512;
+		if (block_num != offs / 512 || first_fill) {
+			block_num  = offs / 512;
 			printk_notice (".");
 			ide_read(IDE_BOOT_DRIVE, block_num, buffer);
 			first_fill = 0;
 		}
 
-		byte_offset = offset % 512;
+		byte_offset = offs % 512;
 		len = 512 - byte_offset;
 		if (len > (count - bytes)) {
 			len = (count - bytes);
@@ -69,7 +71,7 @@
 
 		memcpy(dest, buffer + byte_offset, len);
 
-		offset += len;
+		offs += len;
 		bytes += len;
 		dest += len;
 




From rminnich at gmail.com  Sun Apr  5 00:28:41 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 4 Apr 2009 15:28:41 -0700
Subject: [coreboot] [PATCH] fix race in romtool makefiles.
In-Reply-To: <49D7DBCE.1070509@coresystems.de>
References: <49D7DBCE.1070509@coresystems.de>
Message-ID: <13426df10904041528p35404678wa36ba4a99e9b100b@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From info at coresystems.de  Sun Apr  5 00:40:15 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Apr 2009 00:40:15 +0200
Subject: [coreboot] build service results for r4069
Message-ID: <E1LqEX9-0001IN-Vd@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4069 to
the coreboot repository. This caused the following 
changes:

Change Log:
This fixes a race condition (revealed by my other check-in r4067) in the
romtool by changing the Makefiles to be no longer recursive (once again,
recursive make is to be considered harmful).  Tried to (quickly) unify most of
the Makefile code, but medium-term this is going to be worked on for Kconfig
support anyways.

Also fix a sign cast error in rom-mkpayload in case people want to compile this
with -W -Werror

Patch relative to coreboot-v2/util/romtool

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
and
Acked-by: Stefan Reinauer <stepan at coresystems.de>
in order to get the tree working decently asap



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=db800&vendor=amd&num=2
Compilation of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=dbm690t&vendor=amd&num=2
Compilation of amd:norwich is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=norwich&vendor=amd&num=2
Compilation of amd:pistachio has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=pistachio&vendor=amd&num=2
Compilation of amd:rumba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=rumba&vendor=amd&num=2
Compilation of amd:serengeti_cheetah has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=serengeti_cheetah&vendor=amd&num=2
Compilation of amd:serengeti_cheetah_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=serengeti_cheetah_fam10&vendor=amd&num=2
Compilation of arima:hdama is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=hdama&vendor=arima&num=2
Compilation of artecgroup:dbe61 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:a8n_e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=a8n_e&vendor=asus&num=2
Compilation of asus:a8v-e_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=a8v-e_se&vendor=asus&num=2
Compilation of asus:m2v-mx_se has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=m2v-mx_se&vendor=asus&num=2
Compilation of asus:mew-am has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=winnetp680&vendor=bcom&num=2
Compilation of biostar:m6tba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=m6tba&vendor=biostar&num=2
Compilation of broadcom:blast has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=blast&vendor=broadcom&num=2
Compilation of compaq:deskpro_en_sff_p600 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s1850&vendor=dell&num=2
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm586seg has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=msm586seg&vendor=digitallogic&num=2
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=5bcm&vendor=eaglelion&num=2
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga-6bxc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of gigabyte:ga_2761gxdk is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ga_2761gxdk&vendor=gigabyte&num=2
Compilation of gigabyte:m57sli has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=m57sli&vendor=gigabyte&num=2
Compilation of ibm:e325 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=e325&vendor=ibm&num=2
Compilation of ibm:e326 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=e326&vendor=ibm&num=2
Compilation of iei:juki-511p has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=juki-511p&vendor=iei&num=2
Compilation of iei:nova4899r has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:jarrell has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=xe7501devkit&vendor=intel&num=2
Compilation of iwill:dk8_htx has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=dk8_htx&vendor=iwill&num=2
Compilation of iwill:dk8s2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=dk8s2&vendor=iwill&num=2
Compilation of iwill:dk8x is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=dk8x&vendor=iwill&num=2
Compilation of jetway:j7f24 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=j7f24&vendor=jetway&num=2
Compilation of kontron:986lcd-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=986lcd-m&vendor=kontron&num=2
Compilation of lippert:frontrunner has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=frontrunner&vendor=lippert&num=2
Compilation of lippert:roadrunner-lx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=roadrunner-lx&vendor=lippert&num=2
Compilation of lippert:spacerunner-lx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=spacerunner-lx&vendor=lippert&num=2
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ms6178&vendor=msi&num=2
Compilation of msi:ms7135 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ms7135&vendor=msi&num=2
Compilation of msi:ms7260 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ms7260&vendor=msi&num=2
Compilation of msi:ms9185 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ms9185&vendor=msi&num=2
Compilation of msi:ms9282 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ms9282&vendor=msi&num=2
Compilation of nec:powermate2000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=powermate2000&vendor=nec&num=2
Compilation of newisys:khepri has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=khepri&vendor=newisys&num=2
Compilation of nvidia:l1_2pvv has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=l1_2pvv&vendor=nvidia&num=2
Compilation of olpc:btest has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=rev_a&vendor=olpc&num=2
Compilation of pcengines:alix1c has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=alix1c&vendor=pcengines&num=2
Compilation of rca:rm4100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=rm4100&vendor=rca&num=2
Compilation of sunw:ultra40 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ultra40&vendor=sunw&num=2
Compilation of supermicro:h8dme has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=h8dme&vendor=supermicro&num=2
Compilation of supermicro:h8dmr has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=h8dmr&vendor=supermicro&num=2
Compilation of supermicro:x6dai_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=ip1000&vendor=thomson&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=briq&vendor=totalimpact&num=2
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s1846&vendor=tyan&num=2
Compilation of tyan:s2735 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2735&vendor=tyan&num=2
Compilation of tyan:s2850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2850&vendor=tyan&num=2
Compilation of tyan:s2875 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2875&vendor=tyan&num=2
Compilation of tyan:s2880 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2880&vendor=tyan&num=2
Compilation of tyan:s2881 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2881&vendor=tyan&num=2
Compilation of tyan:s2882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2882&vendor=tyan&num=2
Compilation of tyan:s2885 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2885&vendor=tyan&num=2
Compilation of tyan:s2891 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2891&vendor=tyan&num=2
Compilation of tyan:s2892 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2892&vendor=tyan&num=2
Compilation of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2895&vendor=tyan&num=2
Compilation of tyan:s2912 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2912&vendor=tyan&num=2
Compilation of tyan:s2912_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s2912_fam10&vendor=tyan&num=2
Compilation of tyan:s4880 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s4880&vendor=tyan&num=2
Compilation of tyan:s4882 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=s4882&vendor=tyan&num=2
Compilation of via:epia has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=epia&vendor=via&num=2
Compilation of via:epia-cn has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=epia-m&vendor=via&num=2
Compilation of via:pc2500e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4069&device=pc2500e&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sun Apr  5 00:55:49 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Apr 2009 00:55:49 +0200
Subject: [coreboot] [v2] r4072 - in trunk/coreboot-v2/util/romtool: . tools
Message-ID: <mailman.2949.1355071511.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-05 00:55:49 +0200 (Sun, 05 Apr 2009)
New Revision: 4072

Modified:
   trunk/coreboot-v2/util/romtool/Makefile
   trunk/coreboot-v2/util/romtool/tools/Makefile
Log:
Makefile includes were mixed up.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/util/romtool/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 22:27:10 UTC (rev 4071)
+++ trunk/coreboot-v2/util/romtool/Makefile	2009-04-04 22:55:49 UTC (rev 4072)
@@ -21,7 +21,7 @@
 tobj = $(obj)/tools
 tsrc = $(shell pwd)/tools
 
-include tools/Makefile
+include $(tsrc)/Makefile
 
 $(obj)/%.o: %.c $(INC)
 	$(CC) $(CFLAGS) -c -o $@ $<

Modified: trunk/coreboot-v2/util/romtool/tools/Makefile
===================================================================
--- trunk/coreboot-v2/util/romtool/tools/Makefile	2009-04-04 22:27:10 UTC (rev 4071)
+++ trunk/coreboot-v2/util/romtool/tools/Makefile	2009-04-04 22:55:49 UTC (rev 4072)
@@ -5,7 +5,7 @@
 
 tools: $(tobj)/rom-mkstage $(tobj)/rom-mkpayload
 
-include $(tobj)/lzma/Makefile
+include $(tsrc)/lzma/Makefile
 
 COMMON = common.o compress.o $(LZMA_OBJ)
 




From info at coresystems.de  Sun Apr  5 01:05:55 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Apr 2009 01:05:55 +0200
Subject: [coreboot] build service results for r4070
Message-ID: <E1LqEvz-0001OI-Qn@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4070 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix this warning for the embedded planet ep405pc

/tmp/ccilLWBf.s: Assembler messages:
/tmp/ccilLWBf.s:144: Warning: setting incorrect section attributes for .rodata.pci_driver

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=db800&vendor=amd&num=2
Compilation of amd:dbm690t is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=dbm690t&vendor=amd&num=2
Compilation of amd:norwich is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=norwich&vendor=amd&num=2
Compilation of amd:pistachio is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=pistachio&vendor=amd&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=rumba&vendor=amd&num=2
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=serengeti_cheetah&vendor=amd&num=2
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=serengeti_cheetah_fam10&vendor=amd&num=2
Compilation of arima:hdama is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=hdama&vendor=arima&num=2
Compilation of artecgroup:dbe61 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:a8n_e is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=a8n_e&vendor=asus&num=2
Compilation of asus:a8v-e_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=a8v-e_se&vendor=asus&num=2
Compilation of asus:m2v-mx_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=m2v-mx_se&vendor=asus&num=2
Compilation of asus:mew-am is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=winnetp680&vendor=bcom&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=m6tba&vendor=biostar&num=2
Compilation of broadcom:blast is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=blast&vendor=broadcom&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s1850&vendor=dell&num=2
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm586seg is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=msm586seg&vendor=digitallogic&num=2
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=5bcm&vendor=eaglelion&num=2
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of gigabyte:ga_2761gxdk is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ga_2761gxdk&vendor=gigabyte&num=2
Compilation of gigabyte:m57sli is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=m57sli&vendor=gigabyte&num=2
Compilation of ibm:e325 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=e325&vendor=ibm&num=2
Compilation of ibm:e326 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=e326&vendor=ibm&num=2
Compilation of iei:juki-511p is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=juki-511p&vendor=iei&num=2
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:jarrell is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=xe7501devkit&vendor=intel&num=2
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=dk8_htx&vendor=iwill&num=2
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=dk8s2&vendor=iwill&num=2
Compilation of iwill:dk8x is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=dk8x&vendor=iwill&num=2
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=j7f24&vendor=jetway&num=2
Compilation of kontron:986lcd-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=986lcd-m&vendor=kontron&num=2
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=frontrunner&vendor=lippert&num=2
Compilation of lippert:roadrunner-lx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=roadrunner-lx&vendor=lippert&num=2
Compilation of lippert:spacerunner-lx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=spacerunner-lx&vendor=lippert&num=2
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ms6178&vendor=msi&num=2
Compilation of msi:ms7135 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ms7135&vendor=msi&num=2
Compilation of msi:ms7260 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ms7260&vendor=msi&num=2
Compilation of msi:ms9185 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ms9185&vendor=msi&num=2
Compilation of msi:ms9282 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ms9282&vendor=msi&num=2
Compilation of nec:powermate2000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=powermate2000&vendor=nec&num=2
Compilation of newisys:khepri is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=khepri&vendor=newisys&num=2
Compilation of nvidia:l1_2pvv is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=l1_2pvv&vendor=nvidia&num=2
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=rev_a&vendor=olpc&num=2
Compilation of pcengines:alix1c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=alix1c&vendor=pcengines&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=rm4100&vendor=rca&num=2
Compilation of sunw:ultra40 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ultra40&vendor=sunw&num=2
Compilation of supermicro:h8dme is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=h8dme&vendor=supermicro&num=2
Compilation of supermicro:h8dmr is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=h8dmr&vendor=supermicro&num=2
Compilation of supermicro:x6dai_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=ip1000&vendor=thomson&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=briq&vendor=totalimpact&num=2
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s1846&vendor=tyan&num=2
Compilation of tyan:s2735 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2735&vendor=tyan&num=2
Compilation of tyan:s2850 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2850&vendor=tyan&num=2
Compilation of tyan:s2875 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2875&vendor=tyan&num=2
Compilation of tyan:s2880 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2880&vendor=tyan&num=2
Compilation of tyan:s2881 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2881&vendor=tyan&num=2
Compilation of tyan:s2882 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2882&vendor=tyan&num=2
Compilation of tyan:s2885 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2885&vendor=tyan&num=2
Compilation of tyan:s2891 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2891&vendor=tyan&num=2
Compilation of tyan:s2892 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2892&vendor=tyan&num=2
Compilation of tyan:s2895 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2895&vendor=tyan&num=2
Compilation of tyan:s2912 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2912&vendor=tyan&num=2
Compilation of tyan:s2912_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s2912_fam10&vendor=tyan&num=2
Compilation of tyan:s4880 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s4880&vendor=tyan&num=2
Compilation of tyan:s4882 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=s4882&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=epia&vendor=via&num=2
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=epia-m&vendor=via&num=2
Compilation of via:pc2500e is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4070&device=pc2500e&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sun Apr  5 01:29:57 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Apr 2009 01:29:57 +0200
Subject: [coreboot] build service results for r4071
Message-ID: <E1LqFJF-00071E-MT@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4071 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix this warning:
coreboot-v2-4067//src/stream/ide_stream.c: In function 'stream_ide_read':
coreboot-v2-4067//src/stream/ide_stream.c:47: warning: declaration of 'offset' shadows a global declaration
coreboot-v2-4067//src/stream/ide_stream.c:13: warning: shadowed declaration is here

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of advantech:pcm-5820 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=pcm-5820&vendor=advantech&num=2
Compilation of amd:db800 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=db800&vendor=amd&num=2
Compilation of amd:dbm690t is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=dbm690t&vendor=amd&num=2
Compilation of amd:norwich is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=norwich&vendor=amd&num=2
Compilation of amd:pistachio is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=pistachio&vendor=amd&num=2
Compilation of amd:rumba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=rumba&vendor=amd&num=2
Compilation of amd:serengeti_cheetah is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=serengeti_cheetah&vendor=amd&num=2
Compilation of amd:serengeti_cheetah_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=serengeti_cheetah_fam10&vendor=amd&num=2
Compilation of arima:hdama is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=hdama&vendor=arima&num=2
Compilation of artecgroup:dbe61 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=dbe61&vendor=artecgroup&num=2
Compilation of asi:mb_5blgp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=mb_5blgp&vendor=asi&num=2
Compilation of asi:mb_5blmp is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=mb_5blmp&vendor=asi&num=2
Compilation of asus:a8n_e is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=a8n_e&vendor=asus&num=2
Compilation of asus:a8v-e_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=a8v-e_se&vendor=asus&num=2
Compilation of asus:m2v-mx_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=m2v-mx_se&vendor=asus&num=2
Compilation of asus:mew-am is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=p2b-f&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=p3b-f&vendor=asus&num=2
Compilation of axus:tc320 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=tc320&vendor=axus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=pt-6ibd&vendor=azza&num=2
Compilation of bcom:winnet100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=winnet100&vendor=bcom&num=2
Compilation of bcom:winnetp680 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=winnetp680&vendor=bcom&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=m6tba&vendor=biostar&num=2
Compilation of broadcom:blast is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=blast&vendor=broadcom&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of dell:s1850 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s1850&vendor=dell&num=2
Compilation of digitallogic:adl855pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=adl855pc&vendor=digitallogic&num=2
Compilation of digitallogic:msm586seg is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=msm586seg&vendor=digitallogic&num=2
Compilation of digitallogic:msm800sev is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=msm800sev&vendor=digitallogic&num=2
Compilation of eaglelion:5bcm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=5bcm&vendor=eaglelion&num=2
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=qemu-x86&vendor=emulation&num=2
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of gigabyte:ga_2761gxdk is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ga_2761gxdk&vendor=gigabyte&num=2
Compilation of gigabyte:m57sli is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=m57sli&vendor=gigabyte&num=2
Compilation of ibm:e325 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=e325&vendor=ibm&num=2
Compilation of ibm:e326 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=e326&vendor=ibm&num=2
Compilation of iei:juki-511p is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=juki-511p&vendor=iei&num=2
Compilation of iei:nova4899r is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=nova4899r&vendor=iei&num=2
Compilation of iei:pcisa-lx-800-r10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=pcisa-lx-800-r10&vendor=iei&num=2
Compilation of intel:jarrell is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=jarrell&vendor=intel&num=2
Compilation of intel:mtarvon is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=mtarvon&vendor=intel&num=2
Compilation of intel:truxton is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=truxton&vendor=intel&num=2
Compilation of intel:xe7501devkit is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=xe7501devkit&vendor=intel&num=2
Compilation of iwill:dk8_htx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=dk8_htx&vendor=iwill&num=2
Compilation of iwill:dk8s2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=dk8s2&vendor=iwill&num=2
Compilation of iwill:dk8x is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=dk8x&vendor=iwill&num=2
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=j7f24&vendor=jetway&num=2
Compilation of kontron:986lcd-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=986lcd-m&vendor=kontron&num=2
Compilation of lippert:frontrunner is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=frontrunner&vendor=lippert&num=2
Compilation of lippert:roadrunner-lx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=roadrunner-lx&vendor=lippert&num=2
Compilation of lippert:spacerunner-lx is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=spacerunner-lx&vendor=lippert&num=2
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6178 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ms6178&vendor=msi&num=2
Compilation of msi:ms7135 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ms7135&vendor=msi&num=2
Compilation of msi:ms7260 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ms7260&vendor=msi&num=2
Compilation of msi:ms9185 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ms9185&vendor=msi&num=2
Compilation of msi:ms9282 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ms9282&vendor=msi&num=2
Compilation of nec:powermate2000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=powermate2000&vendor=nec&num=2
Compilation of newisys:khepri is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=khepri&vendor=newisys&num=2
Compilation of nvidia:l1_2pvv is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=l1_2pvv&vendor=nvidia&num=2
Compilation of olpc:btest is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=btest&vendor=olpc&num=2
Compilation of olpc:rev_a is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=rev_a&vendor=olpc&num=2
Compilation of pcengines:alix1c is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=alix1c&vendor=pcengines&num=2
Compilation of rca:rm4100 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=rm4100&vendor=rca&num=2
Compilation of sunw:ultra40 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ultra40&vendor=sunw&num=2
Compilation of supermicro:h8dme is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=h8dme&vendor=supermicro&num=2
Compilation of supermicro:h8dmr is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=h8dmr&vendor=supermicro&num=2
Compilation of supermicro:x6dai_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=x6dai_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=x6dhe_g&vendor=supermicro&num=2
Compilation of supermicro:x6dhe_g2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=x6dhe_g2&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=x6dhr_ig&vendor=supermicro&num=2
Compilation of supermicro:x6dhr_ig2 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=x6dhr_ig2&vendor=supermicro&num=2
Compilation of technologic:ts5300 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ts5300&vendor=technologic&num=2
Compilation of televideo:tc7020 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=tc7020&vendor=televideo&num=2
Compilation of thomson:ip1000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=ip1000&vendor=thomson&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=briq&vendor=totalimpact&num=2
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s1846&vendor=tyan&num=2
Compilation of tyan:s2735 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2735&vendor=tyan&num=2
Compilation of tyan:s2850 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2850&vendor=tyan&num=2
Compilation of tyan:s2875 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2875&vendor=tyan&num=2
Compilation of tyan:s2880 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2880&vendor=tyan&num=2
Compilation of tyan:s2881 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2881&vendor=tyan&num=2
Compilation of tyan:s2882 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2882&vendor=tyan&num=2
Compilation of tyan:s2885 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2885&vendor=tyan&num=2
Compilation of tyan:s2891 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2891&vendor=tyan&num=2
Compilation of tyan:s2892 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2892&vendor=tyan&num=2
Compilation of tyan:s2895 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2895&vendor=tyan&num=2
Compilation of tyan:s2912 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2912&vendor=tyan&num=2
Compilation of tyan:s2912_fam10 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s2912_fam10&vendor=tyan&num=2
Compilation of tyan:s4880 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s4880&vendor=tyan&num=2
Compilation of tyan:s4882 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=s4882&vendor=tyan&num=2
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=epia&vendor=via&num=2
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=epia-cn&vendor=via&num=2
Compilation of via:epia-m is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=epia-m&vendor=via&num=2
Compilation of via:pc2500e is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4071&device=pc2500e&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From corey.osgood at gmail.com  Sun Apr  5 01:39:35 2009
From: corey.osgood at gmail.com (Corey Osgood)
Date: Sat, 4 Apr 2009 19:39:35 -0400
Subject: [coreboot] VIA Epia-MII CF question
In-Reply-To: <20090404203832.GS638@nysv.org>
References: <20090403215726.GR638@nysv.org> <20090404203832.GS638@nysv.org>
Message-ID: <dd3c80060904041639k303ea3e6j79b6321bc1ac43cf@mail.gmail.com>

On Sat, Apr 4, 2009 at 4:38 PM, Markus T?rnqvist <mjt at nysv.org> wrote:

> On Sat, Apr 04, 2009 at 12:57:26AM +0300, Markus T?rnqvist wrote:
> >Hi again!
>
> [...]
>
> >The wiki "lets me" either use the CF slot as standard ide or through
> >pcmcia-utils.
> >
> >This standard-ide approach, as said, did not work.
> >
> >Is the wiki wrong?
>
> Did some Sherlocking around and it seems the wiki is outdated.
> And slightly wrong.


If you have a little time, please contact Ron Minnich or Stefan Reinauer
about getting a wiki account and update the wiki page(s).

Thanks,
Corey
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From info at coresystems.de  Sun Apr  5 02:00:03 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Apr 2009 02:00:03 +0200
Subject: [coreboot] build service results for r4072
Message-ID: <E1LqFmN-0007cD-Ju@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4072 to
the coreboot repository. This caused the following 
changes:

Change Log:
Makefile includes were mixed up.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 has been fixed
Compilation of a-trend:atc-6240 has been fixed
Compilation of abit:be6-ii_v2_0 has been fixed
Compilation of advantech:pcm-5820 has been fixed
Compilation of amd:db800 has been fixed
Compilation of amd:dbm690t has been fixed
Compilation of amd:norwich has been fixed
Compilation of amd:pistachio has been fixed
Compilation of amd:rumba has been fixed
Compilation of amd:serengeti_cheetah has been fixed
Compilation of amd:serengeti_cheetah_fam10 has been fixed
Compilation of arima:hdama has been fixed
Compilation of artecgroup:dbe61 has been fixed
Compilation of asi:mb_5blgp has been fixed
Compilation of asi:mb_5blmp has been fixed
Compilation of asus:a8n_e has been fixed
Compilation of asus:a8v-e_se has been fixed
Compilation of asus:m2v-mx_se has been fixed
Compilation of asus:mew-am has been fixed
Compilation of asus:mew-vm has been fixed
Compilation of asus:p2b has been fixed
Compilation of asus:p2b-ds has been fixed
Compilation of asus:p2b-f has been fixed
Compilation of asus:p3b-f has been fixed
Compilation of axus:tc320 has been fixed
Compilation of azza:pt-6ibd has been fixed
Compilation of bcom:winnet100 has been fixed
Compilation of bcom:winnetp680 has been fixed
Compilation of biostar:m6tba has been fixed
Compilation of broadcom:blast has been fixed
Compilation of compaq:deskpro_en_sff_p600 has been fixed
Compilation of dell:s1850 has been fixed
Compilation of digitallogic:adl855pc has been fixed
Compilation of digitallogic:msm586seg has been fixed
Compilation of digitallogic:msm800sev has been fixed
Compilation of eaglelion:5bcm has been fixed
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4072&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of emulation:qemu-x86 has been fixed
Compilation of gigabyte:ga-6bxc has been fixed
Compilation of gigabyte:ga_2761gxdk has been fixed
Compilation of gigabyte:m57sli has been fixed
Compilation of ibm:e325 has been fixed
Compilation of ibm:e326 has been fixed
Compilation of iei:juki-511p has been fixed
Compilation of iei:nova4899r has been fixed
Compilation of iei:pcisa-lx-800-r10 has been fixed
Compilation of intel:jarrell has been fixed
Compilation of intel:mtarvon has been fixed
Compilation of intel:truxton has been fixed
Compilation of intel:xe7501devkit has been fixed
Compilation of iwill:dk8_htx has been fixed
Compilation of iwill:dk8s2 has been fixed
Compilation of iwill:dk8x has been fixed
Compilation of jetway:j7f24 has been fixed
Compilation of kontron:986lcd-m has been fixed
Compilation of lippert:frontrunner has been fixed
Compilation of lippert:roadrunner-lx has been fixed
Compilation of lippert:spacerunner-lx has been fixed
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4072&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4072&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6119 has been fixed
Compilation of msi:ms6147 has been fixed
Compilation of msi:ms6178 has been fixed
Compilation of msi:ms7135 has been fixed
Compilation of msi:ms7260 has been fixed
Compilation of msi:ms9185 has been fixed
Compilation of msi:ms9282 has been fixed
Compilation of nec:powermate2000 has been fixed
Compilation of newisys:khepri has been fixed
Compilation of nvidia:l1_2pvv has been fixed
Compilation of olpc:btest has been fixed
Compilation of olpc:rev_a has been fixed
Compilation of pcengines:alix1c has been fixed
Compilation of rca:rm4100 has been fixed
Compilation of sunw:ultra40 has been fixed
Compilation of supermicro:h8dme has been fixed
Compilation of supermicro:h8dmr has been fixed
Compilation of supermicro:x6dai_g has been fixed
Compilation of supermicro:x6dhe_g has been fixed
Compilation of supermicro:x6dhe_g2 has been fixed
Compilation of supermicro:x6dhr_ig has been fixed
Compilation of supermicro:x6dhr_ig2 has been fixed
Compilation of technologic:ts5300 has been fixed
Compilation of televideo:tc7020 has been fixed
Compilation of thomson:ip1000 has been fixed
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4072&device=briq&vendor=totalimpact&num=2
Compilation of tyan:s1846 has been fixed
Compilation of tyan:s2735 has been fixed
Compilation of tyan:s2850 has been fixed
Compilation of tyan:s2875 has been fixed
Compilation of tyan:s2880 has been fixed
Compilation of tyan:s2881 has been fixed
Compilation of tyan:s2882 has been fixed
Compilation of tyan:s2885 has been fixed
Compilation of tyan:s2891 has been fixed
Compilation of tyan:s2892 has been fixed
Compilation of tyan:s2895 has been fixed
Compilation of tyan:s2912 has been fixed
Compilation of tyan:s2912_fam10 has been fixed
Compilation of tyan:s4880 has been fixed
Compilation of tyan:s4882 has been fixed
Compilation of via:epia has been fixed
Compilation of via:epia-cn has been fixed
Compilation of via:epia-m has been fixed
Compilation of via:pc2500e has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Sun Apr  5 02:42:24 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 05 Apr 2009 02:42:24 +0200
Subject: [coreboot] romtool and makefile breakage
In-Reply-To: <20090404184107.14577gmx1@mx035.gmx.net>
References: <20090404184107.14577gmx1@mx035.gmx.net>
Message-ID: <49D7FE70.20808@gmx.net>

On 04.04.2009 20:40, svn at coreboot.org wrote:
> Author: stepan
> Date: 2009-04-04 20:40:46 +0200 (Sat, 04 Apr 2009)
> New Revision: 4068
>
> Modified:
>    trunk/coreboot-v2/src/arch/ppc/Config.lb
> Log:
> small workaround for romtool incompatibility with ppc ports
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
>   

No offense intended, but almost every commit intended to fix the build
since the introduction of romtool broke the build for some boards.

I'm very tempted to simply suggest reverting romtool until someone
figures out how to get a reliable and stable abuild.

I mean, look at the commits which tried to fix romtool breakage:
4049, 4054, 4061, 4062, 4067, 4068
and the build is still broken!

It seems the cause of the breakage is not understood.

Can we please require a full _parallel_ abuild on a
_multicore/multiprocessor_ machine for each "bugfix" before it is committed?

By the way, each of the make rules in the code snippet below is a pure
race condition:

> Modified: trunk/coreboot-v2/src/arch/ppc/Config.lb
> ===================================================================
> --- trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-04-04 18:24:21 UTC (rev 4067)
> +++ trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-04-04 18:40:46 UTC (rev 4068)
> @@ -1,10 +1,15 @@
>  ldscript init/ldscript.lb
>  
> -makerule coreboot.rom 
> +makerule coreboot.strip 
>  	depends	"coreboot" 
>  	action	"cp $< $@"
>  end
>  
> +makerule coreboot.rom 
> +	depends	"coreboot.strip" 
> +	action "cp $< $@"
> +end
> +
>  dir init
>  dir lib
>  dir boot
>   

"cp" and "cat" should be banned in makefiles. They are not atomic and if
they touch any files specified in any dependency rule, they WILL
randomly BREAK parallel compilation (or just result in silently
corrupted images) and work without problems if compilation is not
parallelized. Since almost everybody doesn't run abuild in parallel mode
on a multicore machine (except our build-bot), the breakage happens only
on the build-bot.

I just checked our v2 makefiles and every single usage of cp and every
single usage of cat looks broken.

Solution:
If you really have to use cp and cat, make sure the destination file is
not mentioned in any dependency rule. Use temporary files as destination
files and rename (mv) them to the real destination file. Make sure the
temp file and the destination file are in the same directory

Example:
Broken rule:

makerule a
	depends	"b"
	action "cp $< $@"
end

Fixed rule:
makerule a
	depends	"b"
	action "cp $< $someuniquetempname"
	action "mv $someuniquetempname $@"
end


someuniquetempname must be created (in the same directory as the
destination file of the rule) with mkstemp (or mktemp, if mkstemp is
unavailable) in that rule (not globally, or you get another race
condition), but my make-fu is too weak for this.

And while we're on the topic of makefile race conditions, please note
that gcc is smart enough to create output files atomically, but almost
every other program (romcc, romtool, cat, cp) is not. Non-smart programs
MUST (in the RFC sense) always output to files not specified in any
dependency rule. Creating smart programs is hard.


Sorry for the lengthy mail, it's meant to be helpful.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From patrick at georgi-clan.de  Sun Apr  5 08:32:11 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 05 Apr 2009 08:32:11 +0200
Subject: [coreboot] romtool and makefile breakage
In-Reply-To: <49D7FE70.20808@gmx.net>
References: <20090404184107.14577gmx1@mx035.gmx.net> <49D7FE70.20808@gmx.net>
Message-ID: <49D8506B.9010807@georgi-clan.de>

Am 05.04.2009 02:42, schrieb Carl-Daniel Hailfinger:
> No offense intended, but almost every commit intended to fix the build
> since the introduction of romtool broke the build for some boards.
>    
As long as someone works on it, I think it's fine. If problems arise and 
no-one works on fixing them, that's a serious issue and code should be 
rolled back.
That's why this is a development repository. And people who fear that 
their local copy might break can look at the autobuilder.
> It seems the cause of the breakage is not understood.
>
> Can we please require a full _parallel_ abuild on a
> _multicore/multiprocessor_ machine for each "bugfix" before it is committed?
>    
Doesn't necessarily help. Many of my patches were tested exactly that 
way, and they worked fine on _my_ box when built that way. What more 
should I do?
If you want an "tree-always-works" process, I can recommend aegis 
(http://aegis.sf.net)
> "cp" and "cat" should be banned in makefiles. They are not atomic and if
> [...]
>    
> And while we're on the topic of makefile race conditions, please note
> that gcc is smart enough to create output files atomically, but almost
> every other program (romcc, romtool, cat, cp) is not. Non-smart programs
> MUST (in the RFC sense) always output to files not specified in any
> dependency rule. Creating smart programs is hard.
>    
How about just banning make, if it doesn't manage such a trivial thing 
such as looking if the job make itself created finished, before assuming 
that the file is ready to be used?
This isn't rocket science.


Patrick



From stepan at coresystems.de  Sun Apr  5 10:13:48 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 05 Apr 2009 10:13:48 +0200
Subject: [coreboot] romtool and makefile breakage
In-Reply-To: <49D7FE70.20808@gmx.net>
References: <20090404184107.14577gmx1@mx035.gmx.net> <49D7FE70.20808@gmx.net>
Message-ID: <49D8683C.4090408@coresystems.de>

On 05.04.2009 2:42 Uhr, Carl-Daniel Hailfinger wrote:
> No offense intended, but almost every commit intended to fix the build
> since the introduction of romtool broke the build for some boards.
>
> I'm very tempted to simply suggest reverting romtool until someone
> figures out how to get a reliable and stable abuild.
>
>   
Please accept my apologies. If someone else did what I did last night, I
would have been writing this mail, quite sure ;-)

We did test romtool/romfs over the last two weeks in a separate
repository, and it never exposed the issues we were seeing. 
> I mean, look at the commits which tried to fix romtool breakage:
> 4049, 4054, 4061, 4062, 4067, 4068
> and the build is still broken!
>   
It should all be fixed again now. (Missing: Some PPC stuff). The
revisions you list mostly fix different issues that did not show up in
our tests before.
Plus, the problem is we didn't have a ppc cross compiler installed on
our development abuild boxes)

> It seems the cause of the breakage is not understood.
>   
The cause_s_ were quite simple. However, there were several.

> Can we please require a full _parallel_ abuild on a
> _multicore/multiprocessor_ machine for each "bugfix" before it is committed?
>
> Example:
> Broken rule:
>
> makerule a
> 	depends	"b"
> 	action "cp $< $@"
> end
>
> Fixed rule:
> makerule a
> 	depends	"b"
> 	action "cp $< $someuniquetempname"
> 	action "mv $someuniquetempname $@"
> end
>   

I have to agree with Patrick here: If make can't handle trivial stuff
like copying a file around without introducing a race condition or
adding severe workarounds, it is probably not the tool of our choice.

> And while we're on the topic of makefile race conditions, please note
> that gcc is smart enough to create output files atomically, but almost
> every other program (romcc, romtool, cat, cp) is not. Non-smart programs
> MUST (in the RFC sense) always output to files not specified in any
> dependency rule. Creating smart programs is hard.
>   

I don't like a BIOS to be smart about Make processes. Autoconf and
libtool tried that, and failed. How could a BIOS ever succeed.

Maybe fixing GNU make instead would be an option, too? If make has a
production rule for a target, it MUST (in the RFC sense) never ever
execute a rule depending on that one, while the rule is still running.
That's just broken behavior, by design or implementation, and I don't
think our two layers of python on top of it should be fixing it. ;-)

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Sun Apr  5 10:39:13 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Apr 2009 10:39:13 +0200
Subject: [coreboot] [v2] r4073 - in trunk/coreboot-v2/src:
	mainboard/totalimpact/briq southbridge/winbond/w83c553
Message-ID: <mailman.2950.1355071511.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-05 10:39:13 +0200 (Sun, 05 Apr 2009)
New Revision: 4073

Modified:
   trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb
   trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.h
Log:
two more totalimpact briq fixes. Gets us back to the romfs breakage on PPC

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb	2009-04-04 22:55:49 UTC (rev 4072)
+++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb	2009-04-05 08:39:13 UTC (rev 4073)
@@ -64,6 +64,11 @@
 ##
 default TTYS0_BASE=0x3f8
 
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc"
+default HOSTCC="gcc"
 ## use a cross compiler
 #default CROSS_COMPILE="powerpc-eabi-"
 #default CROSS_COMPILE="ppc_74xx-"

Modified: trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.h	2009-04-04 22:55:49 UTC (rev 4072)
+++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.h	2009-04-05 08:39:13 UTC (rev 4073)
@@ -195,6 +195,4 @@
 #define W83C553F_DMA2_CM		0xDC
 #define W83C553F_DMA2_RWAMB		0xDE
 
-extern struct device_operations w83c553_ops;
-
 #endif /* _W83C553_H */




From svn at coreboot.org  Sun Apr  5 10:43:45 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Apr 2009 10:43:45 +0200
Subject: [coreboot] [v2] r4074 -
	trunk/coreboot-v2/src/mainboard/motorola/sandpoint
Message-ID: <mailman.2951.1355071511.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-05 10:43:44 +0200 (Sun, 05 Apr 2009)
New Revision: 4074

Modified:
   trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb
Log:
cross compilation fix for motorola sandpoint based boards

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb	2009-04-05 08:39:13 UTC (rev 4073)
+++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb	2009-04-05 08:43:44 UTC (rev 4074)
@@ -60,7 +60,11 @@
 default PNP_CFGDATA=0x15d
 default _IO_BASE=ISA_IO_BASE
 
-
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc"
+default HOSTCC="gcc"
 ## use a cross compiler
 #default CROSS_COMPILE="powerpc-eabi-"
 #default CROSS_COMPILE="ppc_74xx-"




From info at coresystems.de  Sun Apr  5 11:01:46 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Apr 2009 11:01:46 +0200
Subject: [coreboot] build service results for r4073
Message-ID: <E1LqOEc-0008GY-4q@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4073 to
the coreboot repository. This caused the following 
changes:

Change Log:
two more totalimpact briq fixes. Gets us back to the romfs breakage on PPC

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4073&device=ep405pc&vendor=embeddedplanet&num=2
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4073&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4073&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4073&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sun Apr  5 11:25:31 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Apr 2009 11:25:31 +0200
Subject: [coreboot] build service results for r4074
Message-ID: <E1LqObb-0008LM-3g@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4074 to
the coreboot repository. This caused the following 
changes:

Change Log:
cross compilation fix for motorola sandpoint based boards

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4074&device=ep405pc&vendor=embeddedplanet&num=2
Configuration of motorola:sandpoint is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4074&device=sandpoint&vendor=motorola&num=1
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4074&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4074&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From uwe at hermann-uwe.de  Sun Apr  5 18:36:11 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 5 Apr 2009 18:36:11 +0200
Subject: [coreboot] build service results for r4069
In-Reply-To: <E1LqEX9-0001IN-Vd@ra.coresystems.de>
References: <E1LqEX9-0001IN-Vd@ra.coresystems.de>
Message-ID: <20090405163611.GC25703@greenwood>

On Sun, Apr 05, 2009 at 12:40:15AM +0200, coreboot information wrote:
> recursive make is to be considered harmful).  Tried to (quickly) unify most of
> the Makefile code, but medium-term this is going to be worked on for Kconfig
> support anyways.

Just a quick note -- if someone starts doing a kconfig for v2, please
use the copies from libpayload or coreinfo as a basis, _not_ the copy we
currently have in v3 (that's _ancient_), so we'll have all our kconfigs
at the exact same version, which makes comparisons, upgrades, etc.
much simpler.


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From c-d.hailfinger.devel.2006 at gmx.net  Mon Apr  6 01:05:27 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 06 Apr 2009 01:05:27 +0200
Subject: [coreboot] [PATCH] Asus M2A-VM
Message-ID: <49D93937.4060802@gmx.net>

This is the state of my v2 tree with Asus M2A-VM support. The patch is
against the AMD DBM690T, so you have to compile the amd/dbm690t target
for your Asus M2A-VM.

Notes:
- If you want a working NIC, revert the part enabling MMCONFIG in
LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c.
- If you want a working NIC and ACPI support for SATA, go to
LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl and
enable the SB5 EVIL HACK and comment out the active
"OperationRegion(SB5..." instead.
- Thermal setup is wrong.
- More than 2 GB RAM will not work (SATA will hang).
- FILO will usually work. Sometimes, you may have to poke the reset
button first.

Suggestions:
- Revert the MMCONFIG stuff. Ignore ACPI for SATA.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c	(Arbeitskopie)
@@ -63,8 +63,8 @@
 
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c);
-	/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
-		     dev->path.pci.devfn);*/
+	printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.pci.devfn << 12 | reg_pos;
 
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb	(Arbeitskopie)
@@ -195,7 +195,7 @@
 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
+		chip cpu/amd/socket_AM2
 		device apic 0 on end
 		end
 	end
@@ -211,7 +211,7 @@
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					#device pci 3.0 off end # PCIE P2P bridge	0x791b
 					device pci 4.0 on end # PCIE P2P bridge 0x7914
 					device pci 5.0 on end # PCIE P2P bridge 0x7915
 					device pci 6.0 on end # PCIE P2P bridge 0x7916
@@ -255,9 +255,9 @@
 					device pci 14.3 on # LPC	0x438d
 						chip superio/ite/it8712f
 							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
+								#io 0x60 = 0x3f0
+								#irq 0x70 = 6
+								#drq 0x74 = 2
 							end
 							device pnp 2e.1 on #  Com1
 								io 0x60 = 0x3f8
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c	(Arbeitskopie)
@@ -54,7 +54,7 @@
 extern u8 bus_isa;
 extern u8 bus_rs690[8];
 extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
+extern u32 sbdn_sb600;
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c	(Arbeitskopie)
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-static void setup_dbm690t_resource_map(void)
+static void setup_mb_resource_map(void)
 {
 	static const unsigned int register_values[] = {
 		/* Careful set limit registers before base registers which contain the enables */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl	(Arbeitskopie)
@@ -33,8 +33,8 @@
 	/* FIXME the patching is not done yet! */
 	/* Memory related values */
 	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
+	Name(PBAD, 0xFFF00000)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x00100000)	/* Length of BIOS area (1 MB hardcoded) */
 
 	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
@@ -273,7 +273,7 @@
 			   * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 			*/
 			Offset(0x00090024),	/* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
-			STB5, 32,
+			STB5, 32,		/* Address of SATA_BAR5 */
 			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 			PT0D, 1,
 			PT1D, 1,
@@ -297,7 +297,9 @@
 			P92E, 1,		/* Port92 decode enable */
 		}
 
-		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+		/* FIXME: EVIL HACK. SB5 address is hardcoded to 0xfc409000 in the hope the OS won't touch it. */
+		/*OperationRegion(SB5, SystemMemory, 0xfc409000, 0x1000)*/ /* SATA_BAR5 (ABAR) */
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000) /* SATA_BAR5 (ABAR) */
 			Field(SB5, AnyAcc, NoLock, Preserve)
 			{
 			/* Port 0 */
@@ -308,9 +310,9 @@
 			, 3,
 			P0BY, 1,
 			Offset(0x128),		/* Port 0 Serial ATA status */
-			P0DD, 4,
+			P0DD, 4,		/* Port 0 Device Detection (DET) */
 			, 4,
-			P0IS, 4,
+			P0IS, 4,		/* Port 0 Interface Power Management (IPM) */
 			Offset(0x12C),		/* Port 0 Serial ATA control */
 			P0DI, 4,
 			Offset(0x130),		/* Port 0 Serial ATA error */
@@ -1493,23 +1495,24 @@
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
 				/* DRAM Memory from 1MB to TopMem */
-				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem, the length is filled out when DMLL is calculated */
 
 				/* BIOS space just below 4GB */
 				DWORDMemory(
 					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
 					0x00,			/* Granularity */
 					0x00000000,		/* Min */
-					0x00000000,		/* Max */
+					0xFFFFFFFF,		/* Max */
 					0x00000000,		/* Translation */
 					0x00000000,		/* Max-Min, RLEN */
 					,,
-					PCBM
+					PCBM,
+					AddressRangeReserved
 				)
 
 				/* DRAM memory from 4GB to TopMem2 */
 				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0xFFFFFFFF,		/* Granularity */
+					0x3FFFFFFF,		/* Granularity must be 1 GB or lower! Due to hoisting, RLEN will always be 2k+1 GB */
 					0x00000000,		/*  Min */
 					0x00000000,		/* Max */
 					0x00000000,		/* Translation */
@@ -1543,6 +1546,7 @@
 
 				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
 				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^DMHI._MAX, DMHM)
 				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
 				CreateQWordField(CRES, ^PEBM._LEN, EBML)
 
@@ -1554,23 +1558,16 @@
 				/* Set size of memory from 1MB to TopMem */
 				Subtract(TOM1, 0x100000, DMLL)
 
-				/*
-				* If(LNotEqual(TOM2, 0x00000000)){
-				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	Subtract(TOM2, 0x100000000, DMHL)
-				* }
-				*/
-
-				/* If there is no memory above 4GB, put the BIOS just below 4GB */
-				If(LEqual(TOM2, 0x00000000)){
-					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
-					Store(PBLN,PBML)
+				If(LNotEqual(TOM2, 0x00000000)){
+					Store(0x100000000,DMHB)			/* DRAM from 4GB to TopMem2 */
+					Subtract(TOM2, 0x100000000, DMHL)
+					Subtract(TOM2, 0x1, DMHM)
 				}
-				Else {  /* Otherwise, put the BIOS just below 16EB */
-					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
-					Store(PBLN,EBML)
-				}
 
+				/* Put the BIOS just below 4GB */
+				Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+				Store(PBLN,PBML)
+
 				Return(CRES) /* note to change the Name buffer */
 			}  /* end of Method(_SB.PCI0._CRS) */
 
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c	(Arbeitskopie)
@@ -89,6 +89,31 @@
 	outb(byte, 0xC52);
 }
 
+/*
+ * This is a totally gross hack to be able to use pci_{read,write}_config*
+ * early during boot when the device tree is not yet set up completely.
+ */
+void devicetree_early_fixup(struct device *dev)
+{
+	struct bus *pbus = dev->bus;
+	while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
+		if (pbus == pbus->dev->bus)
+			break;
+		pbus = pbus->dev->bus;
+	}
+	if (ops_pci_bus(pbus)) {
+		printk_info("%s not needed\n", __func__);
+		return;
+	}
+	if (pbus && pbus->dev && pbus->dev->ops) {
+		printk_info("%s fixing up root bus pci ops\n", __func__);
+		pbus->dev->ops->ops_pci_bus = &pci_cf8_conf1;
+		return;
+	}
+	printk_info("%s failed\n", __func__);
+	return;
+}
+
 /********************************************************
 * dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
 * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
@@ -97,32 +122,25 @@
 static void get_ide_dma66()
 {
 	u8 byte;
-	/*u32 sm_dev, ide_dev; */
-	device_t sm_dev, ide_dev;
-	struct bus pbus;
+	struct device *sm_dev;
+	struct device *ide_dev;
 
+	printk_info("%s.\n", __func__);
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	devicetree_early_fixup(sm_dev);
 
-	byte =
-	    pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
-				sm_dev->path.pci.devfn, 0xA9);
+	byte = pci_read_config8(sm_dev, 0xA9);
 	byte |= (1 << 5);	/* Set Gpio9 as input */
-	pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
-			     sm_dev->path.pci.devfn, 0xA9, byte);
+	pci_write_config8(sm_dev, 0xA9, byte);
 
 	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
-	byte =
-	    pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
-				ide_dev->path.pci.devfn, 0x56);
+	byte = pci_read_config8(ide_dev, 0x56);
 	byte &= ~(7 << 0);
-	if ((1 << 5) & pci_cf8_conf1.
-	    read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn,
-		  0xAA))
+	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
 		byte |= 2 << 0;	/* mode 2 */
 	else
 		byte |= 5 << 0;	/* mode 5 */
-	pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
-			     ide_dev->path.pci.devfn, 0x56, byte);
+	pci_write_config8(ide_dev, 0x56, byte);
 }
 
 /*
@@ -133,7 +151,6 @@
 	u8 byte;
 	u16 word;
 	device_t sm_dev;
-	struct bus pbus;
 
 	/* set ADT 7461 */
 	ADT7461_write_byte(0x0B, 0x50);	/* Local Temperature Hight limit */
@@ -156,12 +173,9 @@
 
 	/* set GPIO 64 to input */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word =
-	    pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
-				 sm_dev->path.pci.devfn, 0x56);
+	word = pci_read_config16(sm_dev, 0x56);
 	word |= 1 << 7;
-	pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
-			      sm_dev->path.pci.devfn, 0x56, word);
+	pci_write_config16(sm_dev, 0x56, word);
 
 	/* set GPIO 64 internal pull-up */
 	byte = pm2_ioread(0xf0);
@@ -197,12 +211,12 @@
 * enable the dedicated function in dbm690t board.
 * This function called early than rs690_enable.
 *************************************************/
-void dbm690t_enable(device_t dev)
+void mb_enable(device_t dev)
 {
 	struct mainboard_config *mainboard =
 	    (struct mainboard_config *)dev->chip_info;
 
-	printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev);
+	printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
@@ -264,6 +278,6 @@
 }
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("AMD DBM690T   Mainboard")
-	.enable_dev = dbm690t_enable,
+	CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")
+	.enable_dev = mb_enable,
 };
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(Arbeitskopie)
@@ -32,6 +32,8 @@
 
 #define DIMM0 0x50
 #define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
 
 #define ICS951462_ADDRESS	0x69
 #define SMBUS_HUB 0x71
@@ -137,7 +139,7 @@
 normal_image:
 	post_code(0x23);
 	__asm__ volatile ("jmp __normal_image":	/* outputs */
-			  :"a" (bist), "b"(cpu_init_detectedx)	/* inputs */);
+			  :"a" (bist), "b"(cpu_init_detectedx));	/* inputs */
 
 fallback_image:
 	post_code(0x25);
@@ -157,14 +159,14 @@
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
+	static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	int needs_reset = 0;
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +
+				 DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	}
@@ -181,7 +183,7 @@
 	report_bist_failure(bist);
 	printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
 
-	setup_dbm690t_resource_map();
+	setup_mb_resource_map();
 
 	setup_coherent_ht_domain();
 
Index: LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c	(Arbeitskopie)
@@ -37,6 +37,7 @@
 #include <part/init_timer.h>
 #include <boot/elf.h>
 #include <romfs.h>
+#include "../southbridge/amd/rs690/rs690.h"
 
 /**
  * @brief Main function of the DRAM part of coreboot.
@@ -50,6 +51,7 @@
 void hardwaremain(int boot_complete)
 {
 	struct lb_memory *lb_mem;
+	device_t nb_dev;
 
 	post_code(0x80);
 
@@ -84,6 +86,8 @@
 	dev_initialize();
 	post_code(0x89);
 
+	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
 	/* Now that we have collected all of our information
 	 * write our configuration tables.
 	 */
Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h	(Arbeitskopie)
@@ -1,6 +1,8 @@
 #ifndef __ASM_MPSPEC_H
 #define __ASM_MPSPEC_H
 
+#include <device/device.h>
+
 #if HAVE_MP_TABLE==1
 
 /*
Index: LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb	(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb	(Arbeitskopie)
@@ -7,9 +7,12 @@
 option CROSS_COMPILE="CROSS_PREFIX"
 option HOSTCC="CROSS_HOSTCC"
 
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
 __COMPRESSION__
 
-option ROM_SIZE=1024*1024
+option ROM_SIZE = 1024*1024 - 54784
 romimage "normal"
 	option USE_FALLBACK_IMAGE=0
 	option ROM_IMAGE_SIZE=0x20000


-- 
http://www.hailfinger.org/

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From peter at stuge.se  Mon Apr  6 01:09:20 2009
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Apr 2009 01:09:20 +0200
Subject: [coreboot] [PATCH] Asus M2A-VM
In-Reply-To: <49D93937.4060802@gmx.net>
References: <49D93937.4060802@gmx.net>
Message-ID: <20090405230920.29815.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> This is the state of my v2 tree with Asus M2A-VM support.

Nice!


> The patch is against the AMD DBM690T
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

That makes it difficult to commit as is though. Hm, is there a lot of
code that would be duplicated if a copy is made of the dbm690t
target?


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Mon Apr  6 01:12:23 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 06 Apr 2009 01:12:23 +0200
Subject: [coreboot] [Bochs-developers] Has anyone used a real BIOS image?
In-Reply-To: <grbaiv$lpr$1@ger.gmane.org>
References: <grbaiv$lpr$1@ger.gmane.org>
Message-ID: <49D93AD7.5040905@gmx.net>

Hi Mark,

you have some coreboot questions in the mail below. I'm quoting it in
full and adding the coreboot mailing list to CC.

On 06.04.2009 00:15, Mark Marshall wrote:
> For various reasons (mainly out of curiosity) I've been spending a while 
> to see if I can get Bochs to boot (and maybe then run) with a real 
> (unaltered) BIOS.  Has anyone done this in the past?  What BIOS did they 
> use?  How much did they need to tweak things to get it to work?  (I need 
> PCI for this to be interesting to me).
>
> I've been playing around trying to get an ASUS P2B to boot.  I've got as 
> far as it getting the graphics up and running (by mapping in the VGA 
> cards BIOS) but it seems to hang while it's running some sort of test on 
> the PIT.  The POST code has counted up from 0x05 to 0x14 but then hangs. 
>   (The Award docs I've found on the net all say that 0x14 means it's 
> doing something with the PIT).
>   

Are you trying to get an Asus P2B (hardware) to work or do you want to
execute the P2B BIOS in Bochs? Given your first sentence, it seems you
want the latter.


> To get this far I've had to tweak a few things, mainly to move the PCI 
> hardware up to 440BX standard.  I've also created a skeleton SuperIO.
>
> This is the sort of generation of hardware that I wanted to go for, but 
> I had no real requirements.  It seemed that the P2B was well understood 
> (It's the generation of Intel chip-set that seems to be best documented).
>
> I had to add a little more support to the SMBus stuff, but I still don't 
> really know what values I should return to mean what - there's a good 
> chance I've told the BIOS that I have gigs of RAM.
>
> Has anyone ever used a coreboot BIOS with Bochs?  Does this work?  Do 
> the coreboot guys even use Bochs to get things going (if they don't yet, 
> then I suspect that they would really appreciate Bochs emulation being 
> improved to the point where this is possible).
>   

The standard coreboot target for development without hardware is Qemu. I
believe coreboot runs in Bochs as well, but it's been a long time since
I tried and I don't really remember the results.

> I first got interested in Bochs because I've been writing the VGA BIOS 
> for the OGD1 project.  For this I wanted a development cycle that didn't 
> involve re-flashing a board and then power-cycling a PC.  Bochs has been 
> great for this, so thanks.
>
> MM
>
>
> PS.
> I will at some point have a few patches to send up-stream, but I have 
> slightly large questions about the configuration mechanism used in Bochs 
> at the moment.  I'd like to be able to give it configuration files that 
> matched different _real_ hardware - I'm not convinced that we can do 
> that at the moment. (A P2B, a A7N8x, etc.).
>   

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Mon Apr  6 02:00:46 2009
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Apr 2009 02:00:46 +0200
Subject: [coreboot] [Bochs-developers] Has anyone used a real BIOS	image?
In-Reply-To: <49D93AD7.5040905@gmx.net>
References: <grbaiv$lpr$1@ger.gmane.org> <49D93AD7.5040905@gmx.net>
Message-ID: <20090406000046.10649.qmail@stuge.se>

> On 06.04.2009 00:15, Mark Marshall wrote:
> > I first got interested in Bochs because I've been writing the VGA
> > BIOS for the OGD1 project.

Interesting! One of the coreboot GSoC project ideas is an open source
VGA BIOS for the Geode LX. I am sure your work and experience would
be very valuable for that project!


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Mon Apr  6 02:08:54 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 06 Apr 2009 02:08:54 +0200
Subject: [coreboot] [PATCH] Asus M2A-VM
In-Reply-To: <20090405230920.29815.qmail@stuge.se>
References: <49D93937.4060802@gmx.net> <20090405230920.29815.qmail@stuge.se>
Message-ID: <49D94816.1030504@gmx.net>

On 06.04.2009 01:09, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> This is the state of my v2 tree with Asus M2A-VM support.
>>     
>
> Nice!
>   

Thanks.


>> The patch is against the AMD DBM690T
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> That makes it difficult to commit as is though. Hm, is there a lot of
> code that would be duplicated if a copy is made of the dbm690t
> target?
>   

I have some pending cleanups for DBM690T and Pistachio before I want to
commit this. After the cleanups are tested and acked, the diff between
the various 690/SB600 boards will be really small and adding the M2A-VM
will be mostly a "svn cp".

And I'd like to solve the MMCONFIG related bug by adding proper support
for MMCONFIG without the gross hacks and then debugging it. The in-tree
690/SB600 targets would benefit from this as well. And maybe a correct
MMCONFIG setup fixes the bug with >2GB RAM as well.

GART setup may need some tweaking as well if the Linux boot messages are
any indication.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From fishbaoz at hotmail.com  Mon Apr  6 04:34:21 2009
From: fishbaoz at hotmail.com (Zheng Bao)
Date: Mon, 6 Apr 2009 02:34:21 +0000
Subject: [coreboot] [PATCH] Asus M2A-VM
In-Reply-To: <49D93937.4060802@gmx.net>
References: <49D93937.4060802@gmx.net>
Message-ID: <COL112-W3B6AB5A2BC52308B5D8ECCD840@phx.gbl>


Hi, 

Why the Socket S1G1 is changed to AM2?

 

Joe


 
> Date: Mon, 6 Apr 2009 01:05:27 +0200
> From: c-d.hailfinger.devel.2006 at gmx.net
> To: coreboot at coreboot.org
> Subject: [coreboot] [PATCH] Asus M2A-VM
> 
> This is the state of my v2 tree with Asus M2A-VM support. The patch is
> against the AMD DBM690T, so you have to compile the amd/dbm690t target
> for your Asus M2A-VM.
> 
> Notes:
> - If you want a working NIC, revert the part enabling MMCONFIG in
> LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c.
> - If you want a working NIC and ACPI support for SATA, go to
> LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl and
> enable the SB5 EVIL HACK and comment out the active
> "OperationRegion(SB5..." instead.
> - Thermal setup is wrong.
> - More than 2 GB RAM will not work (SATA will hang).
> - FILO will usually work. Sometimes, you may have to poke the reset
> button first.
> 
> Suggestions:
> - Revert the MMCONFIG stuff. Ignore ACPI for SATA.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> 
> Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c (Arbeitskopie)
> @@ -63,8 +63,8 @@
> 
> /*get BAR3 base address for nbcfg0x1c */
> u32 addr = pci_read_config32(nb_dev, 0x1c);
> - /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
> - dev->path.pci.devfn);*/
> + printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
> + dev->path.pci.devfn);
> addr |= dev->bus->secondary << 20 | /* bus num */
> dev->path.pci.devfn << 12 | reg_pos;
> 
> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Arbeitskopie)
> @@ -195,7 +195,7 @@
> #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
> chip northbridge/amd/amdk8/root_complex
> device apic_cluster 0 on
> - chip cpu/amd/socket_S1G1
> + chip cpu/amd/socket_AM2
> device apic 0 on end
> end
> end
> @@ -211,7 +211,7 @@
> end
> end
> device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
> - device pci 3.0 off end # PCIE P2P bridge 0x791b
> + #device pci 3.0 off end # PCIE P2P bridge 0x791b
> device pci 4.0 on end # PCIE P2P bridge 0x7914
> device pci 5.0 on end # PCIE P2P bridge 0x7915
> device pci 6.0 on end # PCIE P2P bridge 0x7916
> @@ -255,9 +255,9 @@
> device pci 14.3 on # LPC 0x438d
> chip superio/ite/it8712f
> device pnp 2e.0 off # Floppy
> - io 0x60 = 0x3f0
> - irq 0x70 = 6
> - drq 0x74 = 2
> + #io 0x60 = 0x3f0
> + #irq 0x70 = 6
> + #drq 0x74 = 2
> end
> device pnp 2e.1 on # Com1
> io 0x60 = 0x3f8
> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c (Arbeitskopie)
> @@ -54,7 +54,7 @@
> extern u8 bus_isa;
> extern u8 bus_rs690[8];
> extern u8 bus_sb600[2];
> -extern unsigned long sbdn_sb600;
> +extern u32 sbdn_sb600;
> 
> unsigned long write_pirq_routing_table(unsigned long addr)
> {
> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c (Arbeitskopie)
> @@ -17,7 +17,7 @@
> * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> */
> 
> -static void setup_dbm690t_resource_map(void)
> +static void setup_mb_resource_map(void)
> {
> static const unsigned int register_values[] = {
> /* Careful set limit registers before base registers which contain the enables */
> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl (Arbeitskopie)
> @@ -33,8 +33,8 @@
> /* FIXME the patching is not done yet! */
> /* Memory related values */
> Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
> - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
> - Name(PBLN, 0x0) /* Length of BIOS area */
> + Name(PBAD, 0xFFF00000) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
> + Name(PBLN, 0x00100000) /* Length of BIOS area (1 MB hardcoded) */
> 
> Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
> Name(HPBA, 0xFED00000) /* Base address of HPET table */
> @@ -273,7 +273,7 @@
> * The 8 comes from 8 functions per device, and 4096 bytes per function config space
> */
> Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
> - STB5, 32,
> + STB5, 32, /* Address of SATA_BAR5 */
> Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
> PT0D, 1,
> PT1D, 1,
> @@ -297,7 +297,9 @@
> P92E, 1, /* Port92 decode enable */
> }
> 
> - OperationRegion(SB5, SystemMemory, STB5, 0x1000)
> + /* FIXME: EVIL HACK. SB5 address is hardcoded to 0xfc409000 in the hope the OS won't touch it. */
> + /*OperationRegion(SB5, SystemMemory, 0xfc409000, 0x1000)*/ /* SATA_BAR5 (ABAR) */
> + OperationRegion(SB5, SystemMemory, STB5, 0x1000) /* SATA_BAR5 (ABAR) */
> Field(SB5, AnyAcc, NoLock, Preserve)
> {
> /* Port 0 */
> @@ -308,9 +310,9 @@
> , 3,
> P0BY, 1,
> Offset(0x128), /* Port 0 Serial ATA status */
> - P0DD, 4,
> + P0DD, 4, /* Port 0 Device Detection (DET) */
> , 4,
> - P0IS, 4,
> + P0IS, 4, /* Port 0 Interface Power Management (IPM) */
> Offset(0x12C), /* Port 0 Serial ATA control */
> P0DI, 4,
> Offset(0x130), /* Port 0 Serial ATA error */
> @@ -1493,23 +1495,24 @@
> Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
> 
> /* DRAM Memory from 1MB to TopMem */
> - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
> + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem, the length is filled out when DMLL is calculated */
> 
> /* BIOS space just below 4GB */
> DWORDMemory(
> ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> 0x00, /* Granularity */
> 0x00000000, /* Min */
> - 0x00000000, /* Max */
> + 0xFFFFFFFF, /* Max */
> 0x00000000, /* Translation */
> 0x00000000, /* Max-Min, RLEN */
> ,,
> - PCBM
> + PCBM,
> + AddressRangeReserved
> )
> 
> /* DRAM memory from 4GB to TopMem2 */
> QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> - 0xFFFFFFFF, /* Granularity */
> + 0x3FFFFFFF, /* Granularity must be 1 GB or lower! Due to hoisting, RLEN will always be 2k+1 GB */
> 0x00000000, /* Min */
> 0x00000000, /* Max */
> 0x00000000, /* Translation */
> @@ -1543,6 +1546,7 @@
> 
> CreateQWordField(CRES, ^DMHI._MIN, DMHB)
> CreateQWordField(CRES, ^DMHI._LEN, DMHL)
> + CreateQWordField(CRES, ^DMHI._MAX, DMHM)
> CreateQWordField(CRES, ^PEBM._MIN, EBMB)
> CreateQWordField(CRES, ^PEBM._LEN, EBML)
> 
> @@ -1554,23 +1558,16 @@
> /* Set size of memory from 1MB to TopMem */
> Subtract(TOM1, 0x100000, DMLL)
> 
> - /*
> - * If(LNotEqual(TOM2, 0x00000000)){
> - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
> - * Subtract(TOM2, 0x100000000, DMHL)
> - * }
> - */
> -
> - /* If there is no memory above 4GB, put the BIOS just below 4GB */
> - If(LEqual(TOM2, 0x00000000)){
> - Store(PBAD,PBMB) /* Reserve the "BIOS" space */
> - Store(PBLN,PBML)
> + If(LNotEqual(TOM2, 0x00000000)){
> + Store(0x100000000,DMHB) /* DRAM from 4GB to TopMem2 */
> + Subtract(TOM2, 0x100000000, DMHL)
> + Subtract(TOM2, 0x1, DMHM)
> }
> - Else { /* Otherwise, put the BIOS just below 16EB */
> - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
> - Store(PBLN,EBML)
> - }
> 
> + /* Put the BIOS just below 4GB */
> + Store(PBAD,PBMB) /* Reserve the "BIOS" space */
> + Store(PBLN,PBML)
> +
> Return(CRES) /* note to change the Name buffer */
> } /* end of Method(_SB.PCI0._CRS) */
> 
> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie)
> @@ -89,6 +89,31 @@
> outb(byte, 0xC52);
> }
> 
> +/*
> + * This is a totally gross hack to be able to use pci_{read,write}_config*
> + * early during boot when the device tree is not yet set up completely.
> + */
> +void devicetree_early_fixup(struct device *dev)
> +{
> + struct bus *pbus = dev->bus;
> + while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
> + if (pbus == pbus->dev->bus)
> + break;
> + pbus = pbus->dev->bus;
> + }
> + if (ops_pci_bus(pbus)) {
> + printk_info("%s not needed\n", __func__);
> + return;
> + }
> + if (pbus && pbus->dev && pbus->dev->ops) {
> + printk_info("%s fixing up root bus pci ops\n", __func__);
> + pbus->dev->ops->ops_pci_bus = &pci_cf8_conf1;
> + return;
> + }
> + printk_info("%s failed\n", __func__);
> + return;
> +}
> +
> /********************************************************
> * dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
> * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
> @@ -97,32 +122,25 @@
> static void get_ide_dma66()
> {
> u8 byte;
> - /*u32 sm_dev, ide_dev; */
> - device_t sm_dev, ide_dev;
> - struct bus pbus;
> + struct device *sm_dev;
> + struct device *ide_dev;
> 
> + printk_info("%s.\n", __func__);
> sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
> + devicetree_early_fixup(sm_dev);
> 
> - byte =
> - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
> - sm_dev->path.pci.devfn, 0xA9);
> + byte = pci_read_config8(sm_dev, 0xA9);
> byte |= (1 << 5); /* Set Gpio9 as input */
> - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
> - sm_dev->path.pci.devfn, 0xA9, byte);
> + pci_write_config8(sm_dev, 0xA9, byte);
> 
> ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
> - byte =
> - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
> - ide_dev->path.pci.devfn, 0x56);
> + byte = pci_read_config8(ide_dev, 0x56);
> byte &= ~(7 << 0);
> - if ((1 << 5) & pci_cf8_conf1.
> - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn,
> - 0xAA))
> + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
> byte |= 2 << 0; /* mode 2 */
> else
> byte |= 5 << 0; /* mode 5 */
> - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
> - ide_dev->path.pci.devfn, 0x56, byte);
> + pci_write_config8(ide_dev, 0x56, byte);
> }
> 
> /*
> @@ -133,7 +151,6 @@
> u8 byte;
> u16 word;
> device_t sm_dev;
> - struct bus pbus;
> 
> /* set ADT 7461 */
> ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
> @@ -156,12 +173,9 @@
> 
> /* set GPIO 64 to input */
> sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
> - word =
> - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
> - sm_dev->path.pci.devfn, 0x56);
> + word = pci_read_config16(sm_dev, 0x56);
> word |= 1 << 7;
> - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
> - sm_dev->path.pci.devfn, 0x56, word);
> + pci_write_config16(sm_dev, 0x56, word);
> 
> /* set GPIO 64 internal pull-up */
> byte = pm2_ioread(0xf0);
> @@ -197,12 +211,12 @@
> * enable the dedicated function in dbm690t board.
> * This function called early than rs690_enable.
> *************************************************/
> -void dbm690t_enable(device_t dev)
> +void mb_enable(device_t dev)
> {
> struct mainboard_config *mainboard =
> (struct mainboard_config *)dev->chip_info;
> 
> - printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev);
> + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=%p\n", dev);
> 
> #if (CONFIG_GFXUMA == 1)
> msr_t msr, msr2;
> @@ -264,6 +278,6 @@
> }
> 
> struct chip_operations mainboard_ops = {
> - CHIP_NAME("AMD DBM690T Mainboard")
> - .enable_dev = dbm690t_enable,
> + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")
> + .enable_dev = mb_enable,
> };
> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie)
> @@ -32,6 +32,8 @@
> 
> #define DIMM0 0x50
> #define DIMM1 0x51
> +#define DIMM2 0x52
> +#define DIMM3 0x53
> 
> #define ICS951462_ADDRESS 0x69
> #define SMBUS_HUB 0x71
> @@ -137,7 +139,7 @@
> normal_image:
> post_code(0x23);
> __asm__ volatile ("jmp __normal_image": /* outputs */
> - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
> + :"a" (bist), "b"(cpu_init_detectedx)); /* inputs */
> 
> fallback_image:
> post_code(0x25);
> @@ -157,14 +159,14 @@
> 
> void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
> {
> - static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
> + static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
> int needs_reset = 0;
> u32 bsp_apicid = 0;
> msr_t msr;
> struct cpuid_result cpuid1;
> - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
> + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +
> + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
> 
> -
> if (bist == 0) {
> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
> }
> @@ -181,7 +183,7 @@
> report_bist_failure(bist);
> printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
> 
> - setup_dbm690t_resource_map();
> + setup_mb_resource_map();
> 
> setup_coherent_ht_domain();
> 
> Index: LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Arbeitskopie)
> @@ -37,6 +37,7 @@
> #include <part/init_timer.h>
> #include <boot/elf.h>
> #include <romfs.h>
> +#include "../southbridge/amd/rs690/rs690.h"
> 
> /**
> * @brief Main function of the DRAM part of coreboot.
> @@ -50,6 +51,7 @@
> void hardwaremain(int boot_complete)
> {
> struct lb_memory *lb_mem;
> + device_t nb_dev;
> 
> post_code(0x80);
> 
> @@ -84,6 +86,8 @@
> dev_initialize();
> post_code(0x89);
> 
> + nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
> + enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
> /* Now that we have collected all of our information
> * write our configuration tables.
> */
> Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h (Arbeitskopie)
> @@ -1,6 +1,8 @@
> #ifndef __ASM_MPSPEC_H
> #define __ASM_MPSPEC_H
> 
> +#include <device/device.h>
> +
> #if HAVE_MP_TABLE==1
> 
> /*
> Index: LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
> ===================================================================
> --- LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb (Revision 4074)
> +++ LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb (Arbeitskopie)
> @@ -7,9 +7,12 @@
> option CROSS_COMPILE="CROSS_PREFIX"
> option HOSTCC="CROSS_HOSTCC"
> 
> +option DEFAULT_CONSOLE_LOGLEVEL = 9
> +option MAXIMUM_CONSOLE_LOGLEVEL = 9
> +
> __COMPRESSION__
> 
> -option ROM_SIZE=1024*1024
> +option ROM_SIZE = 1024*1024 - 54784
> romimage "normal"
> option USE_FALLBACK_IMAGE=0
> option ROM_IMAGE_SIZE=0x20000
> 
> 
> -- 
> http://www.hailfinger.org/
> 

_________________________________________________________________
Drag n? drop?Get easy photo sharing with Windows Live? Photos.

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From vinuxes at gmail.com  Mon Apr  6 08:37:20 2009
From: vinuxes at gmail.com (vinuxesgmail)
Date: Mon, 06 Apr 2009 12:07:20 +0530
Subject: [coreboot] flashrom fails to write/erase on VIA VT8237
In-Reply-To: <49D4534A.2080506@gmail.com>
References: <49D05438.4040102@gmail.com>
	<49D09607.6010808@gmail.com>	<20090330115759.6344.qmail@stuge.se>
	<49D19BAE.3060009@gmail.com>	<20090331043750.4384.qmail@stuge.se>
	<49D1A3A7.7050703@gmail.com>	<fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>
	<20090401170617.5933.qmail@stuge.se> <49D4534A.2080506@gmail.com>
Message-ID: <49D9A320.8040803@gmail.com>

Hello [again] Peter,
    Could u derives anything from the output that i have sent? Awaiting 
reply!

Rgds,
Vinod

vinuxesgmail wrote:
> Hi Peter,
>    Here's the output of all the commands:
>
> stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l
>    00
>    00000401
>
> >> Extract 8-15 bits from long value: 04
>
> stress:/tmp # ./io r044f
>    r0x044f=ff
>
> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -r backup.bin
>    Calibrating delay loop... OK.
>    No coreboot table found.
>    Found chipset "VIA VT8237", enabling flash write... OK.
>    Found board "Portwell PPAP-2020VL", enabling flash write... OK.
>    Found chip "SST SST49LF004A/B" (512 KB) at physical address 
> 0xfff80000.
>    Reading flash... done.
>
> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E             
> Calibrating delay loop... OK.
>    No coreboot table found.
>    Found chipset "VIA VT8237", enabling flash write... OK.
>    Found board "Portwell PPAP-2020VL", enabling flash write... OK.
>    Found chip "SST SST49LF004A/B" (512 KB) at physical address 
> 0xfff80000.
>    Erasing flash chip... ERASE FAILED!
>    FAILED!
>    ERROR at 0x00000000: Expected=0xff, Read=0x49
>
> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin
>    Calibrating delay loop... OK.
>    No coreboot table found.
>    Found chipset "VIA VT8237", enabling flash write... OK.
>    Found board "Portwell PPAP-2020VL", enabling flash write... OK.
>    Found chip "SST SST49LF004A/B" (512 KB) at physical address 
> 0xfff80000.
>    Flash image seems to be a legacy BIOS. Disabling checks.
>    ERASE FAILED!
>
> stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l
>    00
>    00000401
>
> stress:/tmp # ./io r044f
>    r0x044f=ff
>
> Rgds,
> Vinod
>
> Peter Stuge wrote:
>> Ok. I guess my board enable code doesn't work properly. Maybe you can
>> help me look into the relevant registers manually?
>>
>> Please download http://stuge.se/io.c and compile it using:
>> gcc -O2 -o io io.c
>>
>> Please run:
>> setpci -d 1106:3227 e6.b 88.l
>>
>> The command should print one hexadecimal byte and one hex long.
>> Please save these values.
>>
>> Use bits 8-15 as port bits 8-15 and use 4f as bits 0-7, then please
>> run io:
>> ./io r__4f
>>
>> (Replace __ here with bits 8-15 from the hex long value from setpci.)
>>
>> After this, please run flashrom with the patch. (It will still fail.)
>>
>> Then please run the setpci and io command again, and finally send an
>> email with the output from all commands.
>>
>>
>> Thanks for your help!
>>
>> //Peter
>




From peter at stuge.se  Mon Apr  6 10:25:28 2009
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Apr 2009 10:25:28 +0200
Subject: [coreboot] [PATCH] Asus M2A-VM
In-Reply-To: <COL112-W3B6AB5A2BC52308B5D8ECCD840@phx.gbl>
References: <49D93937.4060802@gmx.net>
	<COL112-W3B6AB5A2BC52308B5D8ECCD840@phx.gbl>
Message-ID: <20090406082528.13319.qmail@stuge.se>

Hi Joe,

Zheng Bao wrote:
> Why the Socket S1G1 is changed to AM2?

The patch is not a proposed change for the dbm690t target.

This is Carl-Daniel's work in progress for the ASUS M2A-VM board.
M2A-VM has an AM2 socket but is very similar to dbm690t in everything
else, so the dbm690t target was the best starting point.

Eventually this work will become a new target asus/m2a-vm.

Carl-Daniel has also made some good general 690/600 improvements
which affect all other boards that have this chipset, but that's a
separate thing. Point is that the changes in this patch will become a
new target, this is just an easy way to work with the tree.


//Peter



From daniel at dmhome.net  Mon Apr  6 13:18:27 2009
From: daniel at dmhome.net (Daniel Toussaint)
Date: Mon, 6 Apr 2009 19:18:27 +0800
Subject: [coreboot] Technexion TIM-8960 patch
Message-ID: <6cb69d4a0904060418p2bd98ffvd84a4a968d932084@mail.gmail.com>

Dear All,

As I mentioned a few weeks ago, I am in the process of porting this board:

http://www.technexion.com/products/embedded_boards/tim-8690-mt.html

This board has a dual BIOS , choosable with a jumper - much like the BIOS
savier from before - so it is a pleasure to work with as a linuxbios
developer.

It is still a work in progress, however , I already submit the patch.
All on board devices and slots work as expected, only need some more stress
testing with the RAM, acpi ,etc..


*Signed-off-by: Daniel Toussaint <daniel at dmhome.net>


*
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From c-d.hailfinger.devel.2006 at gmx.net  Mon Apr  6 13:55:20 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 06 Apr 2009 13:55:20 +0200
Subject: [coreboot] [Bochs-developers] Has anyone used a real BIOS image?
In-Reply-To: <121971.90095.qm@web51501.mail.re2.yahoo.com>
References: <121971.90095.qm@web51501.mail.re2.yahoo.com>
Message-ID: <49D9EDA8.4040303@gmx.net>

Hi Scott,

allow me to forward your mail to the coreboot list as well.

Regards,
Carl-Daniel

On 06.04.2009 04:17, Scott Duplichan wrote:
> Hello Carl-Daniel,
>
> In 2004 I modified bochs to boot an unmodified HP ProLiant DL-145 BIOS. I was able to DOS and also BIOS setup. I could probably dig it up if you like. The DL145 of that generation uses AMD Opteron and 8111 southbridge. 
>
> Thanks,
> Scott
-- 
http://www.hailfinger.org/




From peter at stuge.se  Mon Apr  6 14:48:21 2009
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Apr 2009 14:48:21 +0200
Subject: [coreboot] flashrom fails to write/erase on VIA VT8237
In-Reply-To: <49D9A320.8040803@gmail.com>
References: <49D05438.4040102@gmail.com> <49D09607.6010808@gmail.com>
	<20090330115759.6344.qmail@stuge.se> <49D19BAE.3060009@gmail.com>
	<20090331043750.4384.qmail@stuge.se> <49D1A3A7.7050703@gmail.com>
	<fc39681d0904010327s6a24f99vc14bb35aeec78431@mail.gmail.com>
	<20090401170617.5933.qmail@stuge.se>
	<49D4534A.2080506@gmail.com> <49D9A320.8040803@gmail.com>
Message-ID: <20090406124821.1323.qmail@stuge.se>

Hi Vinod,

vinuxesgmail wrote:
> Could u derives anything from the output that i have sent? Awaiting
> reply!

The output is surprising. If I interpret the 8237 datasheet
correctly, GPO24 should already be high, and the chip should be
writable.

These are open drain outputs however so if the GPIOA net does not
have a pullup resistor (should be on page 14 in the schematic) that
could explain the behavior we are seeing.

Another explanation is that the correct IO register is actually
offset 0x4c and not 0x4f. Then I have simply misunderstood the byte
ordering of the GPOVAL, that is definately a possibility.

Suggestions:

* Check for a pullup on the GPIOA net. If it is missing, try adding one.
* Run ./io r44c r44d r44e r44f
  If the first byte has some bits unset, I misunderstood the byte order.


I hope this brings us closer to a solution!


//Peter



From stepan at coresystems.de  Mon Apr  6 15:32:33 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 06 Apr 2009 15:32:33 +0200
Subject: [coreboot] [Bochs-developers] Has anyone used a real BIOS image?
In-Reply-To: <49D9EDA8.4040303@gmx.net>
References: <121971.90095.qm@web51501.mail.re2.yahoo.com>
	<49D9EDA8.4040303@gmx.net>
Message-ID: <49DA0471.3050309@coresystems.de>

Hi, Scott,

did you emulate a complete K8 / AMD8111 chipset in Bochs?

Best wishes,

Stefan

On 06.04.2009 13:55 Uhr, Carl-Daniel Hailfinger wrote:
> Hi Scott,
>
> allow me to forward your mail to the coreboot list as well.
>
> Regards,
> Carl-Daniel
>
> On 06.04.2009 04:17, Scott Duplichan wrote:
>   
>> Hello Carl-Daniel,
>>
>> In 2004 I modified bochs to boot an unmodified HP ProLiant DL-145 BIOS. I was able to DOS and also BIOS setup. I could probably dig it up if you like. The DL145 of that generation uses AMD Opteron and 8111 southbridge. 
>>
>> Thanks,
>> Scott
>>     


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From bernie at codewiz.org  Mon Apr  6 14:17:23 2009
From: bernie at codewiz.org (Bernie Innocenti)
Date: Mon, 06 Apr 2009 14:17:23 +0200
Subject: [coreboot] [PATCH] Build fixes for buildrom
Message-ID: <49D9F2D3.5050708@codewiz.org>

Build fixes for buildrom

 - switch from "git-foo" to "git foo" for git 1.6
 - add a fallback for when tempfile is missing

Signed-off-by: Bernie Innocenti <bernie at codewiz.org>

Index: bin/fetchgit.sh
===================================================================
--- bin/fetchgit.sh	(revision 261)
+++ bin/fetchgit.sh	(working copy)
@@ -11,7 +11,7 @@
 
 if [ ! -d $DIR/.git ]; then 
 	echo "Cloning $URL..."
-	git-clone $URL $DIR
+	git clone $URL $DIR
 	if [ $? -ne 0 ]; then
 		echo "Couldn't clone $URL."
 		exit 1
@@ -22,10 +22,10 @@
 
 export GIT_DIR=$DIR/.git
 
-git-fetch $URL
-git-fetch --tags $URL
-git-prune-packed
-git-pack-redundant --all | xargs -r rm
+git fetch $URL
+git fetch --tags $URL
+git prune-packed
+git pack-redundant --all | xargs -r rm
 
 # Make the tarball 
-git-tar-tree $TAG $NAME-$TAG | bzip2 > $TARBALL
+git tar-tree $TAG $NAME-$TAG | bzip2 > $TARBALL
Index: bin/show-instructions.sh
===================================================================
--- bin/show-instructions.sh	(revision 261)
+++ bin/show-instructions.sh	(working copy)
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-tmp=`tempfile`
+tmp=`tempfile 2>/dev/null | echo /tmp/show-instructions.$$`
 cat $1 | sed -e "s:%DESTFILE%:$2:" > $tmp
 
 if [ -x `dirname $0`/../scripts/kconfig/lxdialog/lxdialog ]; then

-- 
   // Bernie Innocenti - http://www.codewiz.org/
 \X/  Sugar Labs       - http://www.sugarlabs.org/



From bernie at codewiz.org  Mon Apr  6 14:36:31 2009
From: bernie at codewiz.org (Bernie Innocenti)
Date: Mon, 06 Apr 2009 14:36:31 +0200
Subject: [coreboot] [PATCH] Drop the CONFIG_PCI_BUS_COUNT tweak for seabios
Message-ID: <49D9F74F.3080204@codewiz.org>



This configuration option does no longer exist since when PCI
handling was reworked in seabios.

Signed-off-by: Bernie Innocenti <bernie at codewiz.org>

Index: packages/seabios/hardcode.diff
===================================================================
--- packages/seabios/hardcode.diff	(revision 261)
+++ packages/seabios/hardcode.diff	(working copy)
@@ -17,12 +17,3 @@

  // Support for int13 floppy drive access
  #define CONFIG_FLOPPY_SUPPORT 1
-@@ -36,7 +36,7 @@
- // Support int 1a/b1 PCI BIOS calls
- #define CONFIG_PCIBIOS 1
- // Maximum number of PCI busses.
--#define CONFIG_PCI_BUS_COUNT 2
-+#define CONFIG_PCI_BUS_COUNT 6
- // Support int 15/53 APM BIOS calls
- #define CONFIG_APMBIOS 1
- // Support int 19/18 system bootup support

-- 
   // Bernie Innocenti - http://www.codewiz.org/
 \X/  Sugar Labs       - http://www.sugarlabs.org/



From svn at coreboot.org  Mon Apr  6 15:38:54 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  6 Apr 2009 15:38:54 +0200
Subject: [coreboot] [v2] r4075 - in trunk/coreboot-v2: src/mainboard
	src/mainboard/technexion src/mainboard/technexion/tim8690
	src/mainboard/technexion/tim8690/acpi targets
	targets/technexion targets/technexion/tim8690
Message-ID: <mailman.2952.1355071511.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-04-06 15:38:54 +0200 (Mon, 06 Apr 2009)
New Revision: 4075

Added:
   trunk/coreboot-v2/src/mainboard/technexion/
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/debug.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/doit.sh
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/dsdt.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/globutil.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/ide.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/routing.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/sata.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/statdef.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/usb.asl
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/chip.h
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/fadt.c
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/irq_tables.c
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/mptable.c
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/resourcemap.c
   trunk/coreboot-v2/targets/technexion/
   trunk/coreboot-v2/targets/technexion/tim8690/
   trunk/coreboot-v2/targets/technexion/tim8690/Config.lb
Log:
Daniel Toussaint wrote:

As I mentioned a few weeks ago, I am in the process of porting this board:

http://www.technexion.com/products/embedded_boards/tim-8690-mt.html

This board has a dual BIOS , choosable with a jumper - much like the BIOS
savier from before - so it is a pleasure to work with as a linuxbios developer.

It is still a work in progress, however , I already submit the patch.
All on board devices and slots work as expected, only need some more stress
testing with the RAM, acpi, etc..

Signed-off-by: Daniel Toussaint <daniel at dmhome.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Added: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb	2009-04-06 13:38:54 UTC (rev 4075)
@@ -0,0 +1,312 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+##
+##
+
+
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The coreboot bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreboot will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#dir /drivers/si/3114
+
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE
+	object get_bus_conf.o
+	object irq_tables.o
+end
+
+if HAVE_ACPI_TABLES
+	object acpi_tables.o
+	object fadt.o
+	makerule dsdt.c
+		depends "$(MAINBOARD)/acpi/*.asl"
+		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
+		action  "mv dsdt.hex dsdt.c"
+	end
+	object ./dsdt.o
+end
+
+#object reset.o
+
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+
+		makerule ./cache_as_ram_auto.o
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+		end
+
+	else
+
+		makerule ./cache_as_ram_auto.inc
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
+			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+		end
+
+	end
+
+end
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+if USE_DCACHE_RAM
+	if CONFIG_USE_INIT
+		ldscript /cpu/x86/32bit/entry32.lds
+	end
+
+	if CONFIG_USE_INIT
+		ldscript      /cpu/amd/car/cache_as_ram.lds
+	end
+end
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	else
+		ldscript /arch/i386/lib/failover.lds
+		mainboardinit ./failover.inc
+	end
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject cache_as_ram_auto.o
+	else
+		mainboardinit ./cache_as_ram_auto.inc
+	end
+
+end
+
+##
+## Include the secondary Configuration files
+##
+config chip.h
+
+#The variables belong to mainboard are defined here.
+
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff80000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+#					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#Define gfx_dual_slot, 0: single slot, 1: dual slot
+#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
+#Define gfx_tmds, 0: didn't support TMDS, 1: support
+#Define gfx_compliance, 0: didn't support compliance, 1: support
+#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
+#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_S1G1
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge
+				chip southbridge/amd/rs690
+					device pci 0.0 on end # HT  	0x7910
+					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
+						chip drivers/pci/onboard
+							device pci 5.0 on end	# Internal Graphics 0x791F
+							register "rom_address" = "0xfff80000"
+						end
+					end
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
+					device pci 5.0 on end # PCIE P2P bridge 0x7915
+					device pci 6.0 on end # PCIE P2P bridge 0x7916
+					device pci 7.0 on end # PCIE P2P bridge 0x7917
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					register "vga_rom_address" = "0xfff80000"
+					register "gpp_configuration" = "4"
+					register "port_enable" = "0xfc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
+	 				device pci 14.0 on # SM        0x4385
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x438c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x438d
+						chip superio/ite/it8712f
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.4 off end #  EC
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.6 on #  Mouse
+								irq 0x70 = 12
+							end
+							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
+							end
+							device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+							device pnp 2e.a off end #  CIR
+						end	#superio/ite/it8712f
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # ACI 0x4382
+					device pci 14.6 on end # MCI 0x438e
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb600
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

Added: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainb