[coreboot] VIA Epia-MII stuff

[Markus Törnqvist]

Hi

I dug out my abandoned Epia to see if I could do something with it,
and based the stuff on

http://www.coreboot.org/VIA_EPIA-MII

There were some things I found weird and I'm hoping someone could
shed light on them..

The web says:
"The configuration as set up by the buildtarget process will create a coreboot
file which is exactly 196608 bytes long, which is exactly 64K bytes short of
what needs to go into the 256K flash rom."

For me, that's not true.
root at coraline:/usr/src/coreboot-v2-4046/targets/via/epia-m/epia-m# ls -l
normal/coreboot.rom fallback/coreboot.rom 
-rw-r--r-- 1 root src 131072 Apr  2 20:46 fallback/coreboot.rom
-rw-r--r-- 1 root src 131072 Apr  2 20:46 normal/coreboot.rom

Q1: Why is there a mismatch here?

Also, when encouraged to change the cat like
    cat fallback/coreboot.rom > coreboot.rom
to
    cat /video.bios.bin fallback/coreboot.rom >coreboot.rom

it wasn't accurate; the line is
    cat  normal/coreboot.rom  fallback/coreboot.rom > ./coreboot.rom

Let's remember those two are 262144 bytes, because now the wiki
tells us to add the 64k video.

It obviously doesn't fit in 256k, if we're there already, so what I
actually did was cat the video bios TWICE(!!) and then the normal
bios to make it 256k.

That seems kludgy but I got a FILO prompt :)

Q2: Ideas on why I had to do that?

Here's the Config.lb, where I just changed the FILO payload
to /filo.nohting.elf (to reflect the fact nothing seems to fit
in a rom this small ;)

Thanks!

# Sample config file for EPIA-M
# This will make a target directory of ./epia-m

target epia-m

mainboard via/epia-m

option  MAXIMUM_CONSOLE_LOGLEVEL=8
option  DEFAULT_CONSOLE_LOGLEVEL=8
option  CONFIG_CONSOLE_SERIAL8250=1

option ROM_SIZE=256*1024

option HAVE_OPTION_TABLE=1
option CONFIG_ROM_PAYLOAD=1
option HAVE_FALLBACK_BOOT=1

###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072

## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000

#
###
### Compute the start location and size size of
### The coreboot bootloader.
###

#
# EPIA-M
#

romimage "fallback" 
  option USE_FALLBACK_IMAGE=1
  option ROM_IMAGE_SIZE=0x10000
  option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf  
# payload ../../../../../lnxieepro100.ebi
  payload /filo.nothing.elf
end

romimage "normal" 
  option USE_FALLBACK_IMAGE=1
  option ROM_IMAGE_SIZE=0x10000
  option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf  
# payload ../../../../../lnxieepro100.ebi
  payload /filo.nothing.elf
end

buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

-- 
mjt