[coreboot] [PATCH] Kill unused ROMCC dependencies
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Fri Apr 3 18:17:48 CEST 2009
On 03.04.2009 14:39, Carl-Daniel Hailfinger wrote:
> On 03.04.2009 03:59, Carl-Daniel Hailfinger wrote:
>
>> There are more than a dozen targets in the v2 tree which refer to ROMCC
>> in their Config.lb but never use it. There's no point in keeping dead
>> code around. Kill it.
>>
>> This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
>> tyan/s2850.
>>
>> Abuild build log with and without the patch is completely identical.
>>
>> If this patch is OK, I'll create more of the same type, hopefully making
>> ROMCC dependencies a bit more clear for v2.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>
>>
>
> Next step. Kill auto.c and failover.c and clean up Config.lb for
> tyan/s2735
> tyan/s2850
> tyan/s2875
> tyan/s2880
> tyan/s2881
> tyan/s2882
> tyan/s2885
> tyan/s2891
> tyan/s2892
> tyan/s2895
>
> Abuild log is completely identical with and without the patch.
>
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
You know the drill...
arima/hdama
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms9282
newisys/khepri
sunw/ultra40
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882
Abuild log is completely identical with and without the patch.
With this patch, the last ROMCC remainders for K8 boards are gone.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Patrick, this time I want to commit the patch :-P
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/Config.lb (working copy)
@@ -50,8 +50,6 @@
## ATI Rage XL framebuffering graphics driver
dir /drivers/ati/ragexl
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -69,31 +67,7 @@
end
end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -104,7 +78,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -112,7 +85,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -125,24 +97,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -150,13 +114,8 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
end
-end
###
### O.k. We aren't just an intermediary anymore!
@@ -165,28 +124,13 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
## Include the secondary Configuration files
##
config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/failover.c (working copy)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
-
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/auto.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8s2/auto.c (working copy)
@@ -1,159 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- } else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
- unsigned nodeid;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
- /* Setup the console */
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-
-#if 0
- print_pci_devices();
-#endif
-
- enable_smbus();
-
-#if 0
- dump_spd_registers(&cpu[0]);
-#endif
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
- dump_pci_devices();
- dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/Config.lb (working copy)
@@ -47,8 +47,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -66,31 +64,7 @@
end
end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -101,7 +75,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -109,7 +82,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -147,13 +111,8 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
end
-end
###
### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
## Include the secondary Configuration files
##
config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/failover.c (working copy)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
-
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/auto.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/iwill/dk8x/auto.c (working copy)
@@ -1,189 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-
-static void hard_reset(void)
-{
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
- unsigned nodeid;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
- /* Setup the console */
- pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-
-#if 0
- print_pci_devices();
-#endif
- enable_smbus();
-#if 0
- dump_spd_registers(&cpu[0]);
-#endif
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 1
- dump_pci_devices();
-#endif
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
- /* Check all of memory */
-#if 0
- msr_t msr;
- msr = rdmsr(TOP_MEM);
- print_debug("TOP_MEM: ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\r\n");
-#endif
-#if 0
- ram_check(0x00000000, msr.lo);
-#endif
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
- /* Check 16MB of memory @ 2GB */
- { 0x80000000, 0x81000000 },
-#endif
- };
- int i;
- for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/Config.lb (working copy)
@@ -43,7 +43,6 @@
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
@@ -61,44 +60,7 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-else
- ##
- ## Romcc output
- ##
- makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- ##
- ## Setup RAM
- ##
- mainboardinit cpu/x86/fpu/enable_fpu.inc
- mainboardinit cpu/x86/mmx/enable_mmx.inc
- mainboardinit cpu/x86/sse/enable_sse.inc
- mainboardinit ./auto.inc
- mainboardinit cpu/x86/sse/disable_sse.inc
- mainboardinit cpu/x86/mmx/disable_mmx.inc
- mainboardinit arch/i386/lib/jmp_auto_out.inc
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -109,7 +71,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -117,9 +78,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -131,25 +90,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -157,32 +107,18 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
- end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
- # ROMCC
- mainboardinit arch/i386/lib/jmp_auto.inc
-
-end
-
##
## Include the secondary Configuration files
##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/failover.c (working copy)
@@ -1,69 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-
-static unsigned long main(unsigned long bist)
-{
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/auto.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4880/auto.c (working copy)
@@ -1,233 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
- unsigned reg;
-
- for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
- unsigned config_map;
- config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
- if ((config_map & 3) != 3) {
- continue;
- }
- if ((((config_map >> 4) & 7) == node) &&
- (((config_map >> 8) & 3) == link))
- {
- return (config_map >> 16) & 0xff;
- }
- }
- return 0;
-}
-
-static void hard_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(dev, 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
- set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
- udelay(90);
- }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
- unsigned device=(ctrl->channel0[0])>>8;
- smbus_write_byte(SMBUS_HUB , 0x01, device);
- smbus_write_byte(SMBUS_HUB , 0x03, 0);
-}
-#if 0
-static inline void change_i2c_mux(unsigned device)
-{
-#define SMBUS_HUB 0x18
- smbus_write_byte(SMBUS_HUB , 0x01, device);
- smbus_write_byte(SMBUS_HUB , 0x03, 0);
-}
-#endif
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-
-#define THIRD_CPU 1
-#define FOURTH_CPU 1
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
-
-#define RC0 ((1<<1)<<8)
-#define RC1 ((1<<2)<<8)
-#define RC2 ((1<<3)<<8)
-#define RC3 ((1<<4)<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
- .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { RC1|DIMM0, 0 , 0, 0 },
- .channel1 = { RC1|DIMM1, 0, 0, 0 },
-
- },
-#endif
-
-#if THIRD_CPU
- {
- .node_id = 2,
- .f0 = PCI_DEV(0, 0x1a, 0),
- .f1 = PCI_DEV(0, 0x1a, 1),
- .f2 = PCI_DEV(0, 0x1a, 2),
- .f3 = PCI_DEV(0, 0x1a, 3),
- .channel0 = { RC2|DIMM0, 0, 0, 0 },
- .channel1 = { RC2|DIMM1, 0, 0, 0 },
-
- },
-#endif
-#if FOURTH_CPU
- {
- .node_id = 3,
- .f0 = PCI_DEV(0, 0x1b, 0),
- .f1 = PCI_DEV(0, 0x1b, 1),
- .f2 = PCI_DEV(0, 0x1b, 2),
- .f3 = PCI_DEV(0, 0x1b, 3),
- .channel0 = { RC3|DIMM0, 0, 0, 0 },
- .channel1 = { RC3|DIMM1, 0, 0, 0 },
-
- },
-#endif
- };
- int i;
- int needs_reset;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
-
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_s4880_resource_map();
-
- needs_reset = setup_coherent_ht_domain();
-
- needs_reset |= ht_setup_chains_x();
-
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-
-#if 0
- dump_pci_devices();
-#endif
- enable_smbus();
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2891/Config.lb (working copy)
@@ -63,8 +63,6 @@
#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -79,32 +77,6 @@
end
end
-else
- ##
- ## Romcc output
- ##
- makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -115,7 +87,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -123,7 +94,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -136,12 +106,6 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
@@ -156,12 +120,10 @@
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -170,10 +132,6 @@
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
- if USE_DCACHE_RAM
- else
- mainboardinit ./failover.inc
- end
end
###
@@ -183,25 +141,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
- # ROMCC
- mainboardinit cpu/x86/fpu/enable_fpu.inc
- mainboardinit cpu/x86/mmx/enable_mmx.inc
- mainboardinit cpu/x86/sse/enable_sse.inc
- mainboardinit ./auto.inc
- mainboardinit cpu/x86/sse/disable_sse.inc
- mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
##
## Include the secondary Configuration files
##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2892/Config.lb (working copy)
@@ -63,8 +63,6 @@
#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -79,32 +77,6 @@
end
end
-else
- ##
- ## Romcc output
- ##
- makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -115,7 +87,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -123,7 +94,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -136,12 +106,6 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
@@ -156,12 +120,10 @@
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -169,12 +131,7 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
- end
end
###
@@ -184,25 +141,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
- # ROMCC
- mainboardinit cpu/x86/fpu/enable_fpu.inc
- mainboardinit cpu/x86/mmx/enable_mmx.inc
- mainboardinit cpu/x86/sse/enable_sse.inc
- mainboardinit ./auto.inc
- mainboardinit cpu/x86/sse/disable_sse.inc
- mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
##
## Include the secondary Configuration files
##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/Config.lb (working copy)
@@ -43,7 +43,6 @@
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
@@ -61,44 +60,7 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-else
- ##
- ## Romcc output
- ##
- makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- ##
- ## Setup RAM
- ##
- mainboardinit cpu/x86/fpu/enable_fpu.inc
- mainboardinit cpu/x86/mmx/enable_mmx.inc
- mainboardinit cpu/x86/sse/enable_sse.inc
- mainboardinit ./auto.inc
- mainboardinit cpu/x86/sse/disable_sse.inc
- mainboardinit cpu/x86/mmx/disable_mmx.inc
- mainboardinit arch/i386/lib/jmp_auto_out.inc
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -109,7 +71,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -117,9 +78,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -131,25 +90,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -157,32 +107,18 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
- end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
- # ROMCC
- mainboardinit arch/i386/lib/jmp_auto.inc
-
-end
-
##
## Include the secondary Configuration files
##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/failover.c (working copy)
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-
-static unsigned long main(unsigned long bist)
-{
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/auto.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s4882/auto.c (working copy)
@@ -1,233 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
- unsigned reg;
-
- for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
- unsigned config_map;
- config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
- if ((config_map & 3) != 3) {
- continue;
- }
- if ((((config_map >> 4) & 7) == node) &&
- (((config_map >> 8) & 3) == link))
- {
- return (config_map >> 16) & 0xff;
- }
- }
- return 0;
-}
-
-static void hard_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
-
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(dev, 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
-
- set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
- udelay(90);
- }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
- int ret,i;
- unsigned device=(ctrl->channel0[0])>>8;
- /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
- i=2;
- do {
- ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- } while ((ret!=0) && (i-->0));
-
- smbus_write_byte(SMBUS_HUB, 0x03, 0);
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define QRANK_DIMM_SUPPORT 1
-#include "northbridge/amd/amdk8/raminit.c"
-#if 0
- #define ENABLE_APIC_EXT_ID 1
- #define APIC_ID_OFFSET 0x10
- #define LIFT_BSP_APIC_ID 0
-#else
- #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-
-#define THIRD_CPU 1
-#define FOURTH_CPU 1
-
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
-
-#define RC0 ((1<<2)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<4)<<8)
-#define RC3 ((1<<3)<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
- .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
- .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
-
- },
-#endif
-
-#if THIRD_CPU
- {
- .node_id = 2,
- .f0 = PCI_DEV(0, 0x1a, 0),
- .f1 = PCI_DEV(0, 0x1a, 1),
- .f2 = PCI_DEV(0, 0x1a, 2),
- .f3 = PCI_DEV(0, 0x1a, 3),
- .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
- .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
-
- },
-#endif
-#if FOURTH_CPU
- {
- .node_id = 3,
- .f0 = PCI_DEV(0, 0x1b, 0),
- .f1 = PCI_DEV(0, 0x1b, 1),
- .f2 = PCI_DEV(0, 0x1b, 2),
- .f3 = PCI_DEV(0, 0x1b, 3),
- .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
- .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
-
- },
-#endif
- };
- int i;
- int needs_reset;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
-
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_s4882_resource_map();
-
- needs_reset = setup_coherent_ht_domain();
-
- needs_reset |= ht_setup_chains_x();
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-
- enable_smbus();
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/tyan/s2895/Config.lb (working copy)
@@ -72,8 +72,6 @@
#./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -88,32 +86,6 @@
end
end
-else
- ##
- ## Romcc output
- ##
- makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -131,7 +103,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -139,7 +110,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -162,12 +132,6 @@
end
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
@@ -189,12 +153,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -203,42 +165,23 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- mainboardinit ./failover.inc
- end
end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
- # ROMCC
- mainboardinit cpu/x86/fpu/enable_fpu.inc
- mainboardinit cpu/x86/mmx/enable_mmx.inc
- mainboardinit cpu/x86/sse/enable_sse.inc
- mainboardinit ./auto.inc
- mainboardinit cpu/x86/sse/disable_sse.inc
- mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
##
## Include the secondary Configuration files
##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/Config.lb (working copy)
@@ -75,8 +75,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -94,34 +92,8 @@
end
end
-else
##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-
-end
-
-##
## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
@@ -131,7 +103,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -139,7 +110,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -152,12 +122,6 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
@@ -172,12 +136,10 @@
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -185,13 +147,8 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
end
-end
###
### O.k. We aren't just an intermediary anymore!
@@ -200,25 +157,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-# ROMCC
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
##
## Include the secondary Configuration files
##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/msi/ms9282/failover.c (working copy)
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static void sio_setup(void)
-{
-
- unsigned value;
- uint32_t dword;
- uint8_t byte;
-
- byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-
-}
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#endif
-
-static unsigned long main(unsigned long bist)
-{
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
-
- enumerate_ht_chain();
-
- sio_setup();
-
- /* Setup the mcp55 */
- mcp55_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/Config.lb (working copy)
@@ -46,8 +46,6 @@
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -65,31 +63,7 @@
end
end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -100,7 +74,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -108,7 +81,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -121,24 +93,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -146,13 +110,8 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
end
-end
###
### O.k. We aren't just an intermediary anymore!
@@ -161,28 +120,13 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
## Include the secondary Configuration files
##
config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/failover.c (working copy)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
-
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- nodeid = lapicid() & 0xf;
-
- /* Is this a cpu only reset? */
- if (cpu_init_detected(nodeid)) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/auto.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/arima/hdama/auto.c (working copy)
@@ -1,179 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-
-static void hard_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
- /* enable cf9 */
- pci_write_config8(dev, 0x41, 0xf1);
-
- /* reset */
- set_bios_reset();
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
- /* Reset */
- set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "debug.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
- /* Setup the console */
- pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-#if 0
- print_pci_devices();
-#endif
- enable_smbus();
-#if 0
- dump_spd_registers(ARRAY_SIZE(cpu), cpu);
-#endif
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
- dump_pci_devices();
-#endif
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 2));
- dump_pci_device(PCI_DEV(0, 0x18, 3));
-#endif
-
-#if 0
- /* Check the first 1M */
- ram_check(0x00000000, 0x000100000);
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/Config.lb (working copy)
@@ -47,8 +47,6 @@
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -63,32 +61,6 @@
end
end
-else
- ##
- ## Romcc output
- ##
- makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
- end
-
- makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
- makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
- end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -99,7 +71,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -107,9 +78,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -121,12 +90,6 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
@@ -141,14 +104,10 @@
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
-
-
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -157,34 +116,17 @@
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
- if USE_DCACHE_RAM
- else
- mainboardinit ./failover.inc
- end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
- # ROMCC
- mainboardinit cpu/x86/fpu/enable_fpu.inc
- mainboardinit cpu/x86/mmx/enable_mmx.inc
- mainboardinit cpu/x86/sse/enable_sse.inc
- mainboardinit ./auto.inc
- mainboardinit cpu/x86/sse/disable_sse.inc
- mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
##
## Include the secondary Configuration files
##
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/failover.c (working copy)
@@ -1,118 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-
-#include <device/pnp_def.h>
-
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-#define SUPERIO_COM1_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-#define SUPERIO_COM1_IO_BASE 0x3f8
-
-static void sio_setup(void)
-{
-
- unsigned value;
- uint32_t dword;
- uint8_t byte;
-
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
-
- byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<29)|(1<<0);
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
-#if 1
- lpc47b397_enable_serial(SUPERIO_COM1_DEV, SUPERIO_COM1_IO_BASE);
-
-#if 0
-/* what's this?
- value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
- value &= 0xbf;
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-*/
-#endif
-#endif
-
-}
-
-
-#if CONFIG_LOGICAL_CPUS==1
-#include "cpu/amd/dualcore/dualcore_id.c"
-#else
-#include "cpu/amd/model_fxx/node_id.c"
-#endif
-
-
-static unsigned long main(unsigned long bist)
-{
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
-
- enumerate_ht_chain();
-
- sio_setup();
-
- /* Setup the ck804 */
- ck804_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/auto.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/sunw/ultra40/auto.c (working copy)
@@ -1,198 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-
-#include <cpu/amd/model_fxx_rev.h>
-//#define K8_HT_FREQ_1G_SUPPORT 1
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_msr.h>
-#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
-static void hard_reset(void)
-{
- set_bios_reset();
-
- /* full reset */
- outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
-#if 1
- /* link reset */
- outb(0x02, 0x0cf9);
- outb(0x06, 0x0cf9);
-#endif
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
-static void sio_gpio_setup(void){
-
- unsigned value;
-
-// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
-
-#if 1
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
- value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-#endif
-
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#define QRANK_DIMM_SUPPORT 1
-
-#include "northbridge/amd/amdk8/raminit.c"
-#if 0
- #define ENABLE_APIC_EXT_ID 1
- #define APIC_ID_OFFSET 0x10
- #define LIFT_BSP_APIC_ID 0
-#else
- #define ENABLE_APIC_EXT_ID 0
-#endif
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "sdram/generic_sdram.c"
-
-/* maybe does not want the default */
-#include "resourcemap.c"
-
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-
-#define CK804_NUM 2
-#define CK804B_BUSN 0x80
-#define CK804_USE_NIC 1
-#define CK804_USE_ACI 1
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-
-//set GPIO to input mode
-#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
-
- // post_code(0x32);
-
- lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- sio_gpio_setup();
-
- setup_ultra40_resource_map();
-
- needs_reset = setup_coherent_ht_domain();
-
- needs_reset |= ht_setup_chains_x();
-
- needs_reset |= ck804_early_setup_x();
-
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-
-
- enable_smbus();
-
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/Config.lb (working copy)
@@ -47,8 +47,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -66,32 +64,7 @@
end
end
-else
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -102,7 +75,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -110,7 +82,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -123,23 +94,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-### Should this be in the northbridge code?
-if USE_DCACHE_RAM
-else
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -147,13 +111,8 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
end
-end
###
### O.k. We aren't just an intermediary anymore!
@@ -162,29 +121,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
-##
-## Setup RAM
-##
-
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
config chip.h
# FIXME: ROM for onboard VGA
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/failover.c (working copy)
@@ -1,66 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- nodeid=lapicid();
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/auto.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/auto.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/newisys/khepri/auto.c (working copy)
@@ -1,155 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-
-#include "sdram/generic_sdram.c"
-
-/* newisys khepri does not want the default */
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define NODE_RAM(x) \
- .node_id = 0+x, \
- .f0 = PCI_DEV(0, 0x18+x, 0), \
- .f1 = PCI_DEV(0, 0x18+x, 1), \
- .f2 = PCI_DEV(0, 0x18+x, 2), \
- .f3 = PCI_DEV(0, 0x18+x, 3)
-
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
- {
- NODE_RAM(0),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
- {
- NODE_RAM(1),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
- };
-
- int needs_reset;
- unsigned nodeid;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
- /* Setup the console */
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_khepri_resource_map();
- needs_reset = setup_coherent_ht_domain();
- needs_reset=ht_setup_chains_x();
-
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-#if 0
- print_pci_devices();
-#endif
- enable_smbus();
-#if 0
- dump_spd_registers(&cpu[0]);
-#endif
- memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-#if 0
- dump_pci_devices();
-#endif
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-#if 0
- /* Check the first 1M */
- ram_check(0x00000000, 0x000100000);
-#endif
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/Config.lb (working copy)
@@ -47,8 +47,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -66,31 +64,7 @@
end
end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -101,7 +75,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -109,7 +82,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -147,13 +111,8 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
end
-end
###
### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
## Include the secondary Configuration files
##
config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e326/failover.c (working copy)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- nodeid = lapicid() & 0xf;
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/Config.lb
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/Config.lb (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/Config.lb (working copy)
@@ -47,8 +47,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -66,31 +64,7 @@
end
end
-else
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -101,7 +75,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -109,7 +82,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -122,24 +94,16 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -147,13 +111,8 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
end
-end
###
### O.k. We aren't just an intermediary anymore!
@@ -162,28 +121,13 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-end
-
-##
## Include the secondary Configuration files
##
config chip.h
Index: coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/failover.c
===================================================================
--- coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/failover.c (revision 4052)
+++ coreboot-v2-kill-orphan-romcc/src/mainboard/ibm/e325/failover.c (working copy)
@@ -1,67 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- nodeid = lapicid() & 0xf;
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
--
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