[coreboot] Timing via serial port
c-d.hailfinger.devel.2006 at gmx.net
Sun Apr 19 11:40:07 CEST 2009
On 19.04.2009 04:23, Kevin O'Connor wrote:
> On Sat, Apr 18, 2009 at 09:40:56PM -0400, Kevin O'Connor wrote:
>> On Sat, Apr 18, 2009 at 09:14:06PM -0400, Kevin O'Connor wrote:
>>> On my epia-cn machine, it takes coreboot-v2 8.7 seconds to launch
>>> SeaBIOS. It looks like about 4 seconds is lost due to a reboot
>>> half-way through the startup - I'm guessing a watchdog timer is
>>> kicking in. As to why it takes so long to boot - maybe rom caching is
>> Nope - looks like calibrate_tsc is taking 2.9 seconds to calibrate:
>> 00.608: Jumping to coreboot.
>> 00.609: coreboot-2.0.0-epiacn Sat Apr 18 21:34:47 EDT 2009 booting...
>> 00.612: Calibrating delay loop...
> If I add the following to Config.lb:
> option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
> then the problem goes away - coreboot takes only 1.8 seconds.
Still, 1.8 seconds can surely be trimmed down further. Our early startup
code has some variants performing totally nonsensical operations which
easily account for 200 ms or more. (One variant does nothing except
switch CAR on, fill the cache slowly, switch CAR off again and hope that
CAR works although it is switched off.) The big problem here is that
early startup is considered magic and the accumulated cruft is legendary.
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