From asbjorn at asbjorn.biz Sat Aug 1 01:27:30 2009 From: asbjorn at asbjorn.biz (=?ISO-8859-1?Q?Asbj=F8rn_Sloth_T=F8nnesen?=) Date: Fri, 31 Jul 2009 23:27:30 +0000 Subject: [coreboot] [LinuxBIOS] ASUS M2N-E (Non-SLI) Motherboard Message-ID: <4A737DE2.1080902@asbjorn.biz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, In reply to: http://www.coreboot.org/pipermail/coreboot/2007-May/021716.html On Fri, May 25, 2007 at 09:40:47PM -0200, Uwe Hermann wrote: > On Tue, May 22, 2007 at 06:57:07PM -0500, Jonathan King wrote: >> Yes I am willing and able to help in any way needed! Me too, for a long time I have wanted a MB that I could run coreboot on, so I might just as well enable this one to run coreboot. That way I can also run it without an election heater ( > 8MiB GPU). Since it's being used as a home server. > Please post some more information about the mainboard: > > - lspci -n > - lspci -vv > - lspci -tv > - lspnp -v > - cat /proc/cpuinfo - dmesg - dmidecode - sensors-detect http://asbjorn.it/pub/coreboot/m2n-e/mbinfo/ > As far as I can see this board is very similar to the GIGABYTE > GA-M57SLI-S4, so for now we'll just modify that one. > > Please apply the attached patch (which doesn't really change very much). I have updated the patch to v2 trunk, and filled in the PCI bridge ids http://asbjorn.it/pub/coreboot/m2n-e/v2_asus_m2n_e_r4478.patch > Then build a FILO payload which is configured to display serial > debugging, and use the GRUB from your hard drive to boot the kernel. > Enable the maximum amount of debugging. > The result should be a /tmp/filo.elf file. FILO config: http://asbjorn.it/pub/coreboot/m2n-e/filo_config libpayload config: http://asbjorn.it/pub/coreboot/m2n-e/libpayload_config > Then build the linuxbios.rom image by doing > > $ cd targets > $ ./buildtarget gigabyte/m57sli > $ cd targets/gigabyte/m57sli/m57sli > $ make > > Please record all the serial output in a file and post it here... http://asbjorn.it/pub/coreboot/m2n-e/take1.txt CPU and chassis fans all stops shortly before loading the payload, leading to the hardware watchdog restarting the system after af couple of minutes. I didn't got past LILO because I only had SATA drives in the machine and SATA didn't work. What's the next step? How do I continue? How do I fix SATA? - -- Best regards Asbj?rn Sloth T?nnesen -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkpzfeIACgkQSViWlxucwuqmywCfd3kV+vKk+9hmMxb1ZZA6Y25o W8kAn0HYtXiDDTCWRtNyp+s22aezW2Pz =+TAq -----END PGP SIGNATURE----- From peter at stuge.se Sat Aug 1 03:45:47 2009 From: peter at stuge.se (Peter Stuge) Date: Sat, 1 Aug 2009 03:45:47 +0200 Subject: [coreboot] x86{,_64} ABI links Message-ID: <20090801014547.23208.qmail@stuge.se> http://refspecs.freestandards.org/elf/abi386-4.pdf http://www.x86-64.org/documentation/ //Peter From c-d.hailfinger.devel.2006 at gmx.net Sat Aug 1 03:55:20 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 01 Aug 2009 03:55:20 +0200 Subject: [coreboot] [PATCH] cld before call In-Reply-To: <20090728223627.GA4592@thorin> References: <20090728223627.GA4592@thorin> Message-ID: <4A73A088.8090206@gmx.net> On 29.07.2009 00:36, Robert Millan wrote: > The Multiboot spec is a bit too permissive about this, as it doesn't > specify the state of direction flag when payload is called. Some payloads > (we found this in ReactOS FreeLDR) assume it is cleared, and fail otherwise. > > We adjusted GRUB to be sure it's always cleared. I think coreboot should do > the same. Here's a patch for v3. > > Signed-off-by: Robert Millan > Thanks to the explanation provided by Segher, I now know your patch is the right thing to do. Robert, thanks for digging this up. Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From powerschorsch21 at yahoo.de Sat Aug 1 13:16:55 2009 From: powerschorsch21 at yahoo.de (Maxmimilian Niedernhuber) Date: Sat, 01 Aug 2009 13:16:55 +0200 Subject: [coreboot] Add VGA BIOS failed. Message-ID: <1249125415.3569.10.camel@Schorschmobile> Hello, i want to add the VGA bios to my coreboot.rom. But it fails. /root/coreboot/coreboot-v2-4475/util/cbfstool/cbfstool coreboot-read.bin add vgabios.bin pci1078,0104.rom 0 (cbfstool) E: This does not appear to be a valid ROM (cbfstool) E: Problem while reading the ROM Thank you for your answers. -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot.rom Type: application/x-executable Size: 262144 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: vgabios.bin Type: application/octet-stream Size: 32768 bytes Desc: not available URL: From rmh at aybabtu.com Sat Aug 1 16:14:12 2009 From: rmh at aybabtu.com (Robert Millan) Date: Sat, 1 Aug 2009 16:14:12 +0200 Subject: [coreboot] [PATCH] cld before call In-Reply-To: <4A73A088.8090206@gmx.net> References: <20090728223627.GA4592@thorin> <4A73A088.8090206@gmx.net> Message-ID: <20090801141412.GA22776@thorin> On Sat, Aug 01, 2009 at 03:55:20AM +0200, Carl-Daniel Hailfinger wrote: > On 29.07.2009 00:36, Robert Millan wrote: > > The Multiboot spec is a bit too permissive about this, as it doesn't > > specify the state of direction flag when payload is called. Some payloads > > (we found this in ReactOS FreeLDR) assume it is cleared, and fail otherwise. > > > > We adjusted GRUB to be sure it's always cleared. I think coreboot should do > > the same. Here's a patch for v3. > > > > Signed-off-by: Robert Millan > > > > Thanks to the explanation provided by Segher, I now know your patch is > the right thing to do. > Robert, thanks for digging this up. You're welcome. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all." From peter at stuge.se Sat Aug 1 16:40:40 2009 From: peter at stuge.se (Peter Stuge) Date: Sat, 1 Aug 2009 16:40:40 +0200 Subject: [coreboot] Add VGA BIOS failed. In-Reply-To: <1249125415.3569.10.camel@Schorschmobile> References: <1249125415.3569.10.camel@Schorschmobile> Message-ID: <20090801144040.16318.qmail@stuge.se> Maxmimilian Niedernhuber wrote: > Hello, i want to add the VGA bios to my coreboot.rom. But it fails. > > /root/coreboot/coreboot-v2-4475/util/cbfstool/cbfstool coreboot-read.bin > add vgabios.bin pci1078,0104.rom 0 > (cbfstool) E: This does not appear to be a valid ROM > (cbfstool) E: Problem while reading the ROM > > Thank you for your answers. You're providing much too little information to get any good answers. Where did you get coreboot-read.bin ? //Peter From kevin at koconnor.net Sat Aug 1 17:58:53 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Sat, 1 Aug 2009 11:58:53 -0400 Subject: [coreboot] PMM support in SeaBIOS Message-ID: <20090801155853.GA7520@morn.localdomain> The latest SeaBIOS git now supports Post Memory Manager (PMM) calls. These calls are used by optionroms to allocate memory during bootup. If anyone has had trouble with the execution of an optionrom, I suggest retrying with the latest SeaBIOS git. It's possible the addition of PMM may improve execution. Also, for those with working optionroms I suggest testing the latest SeaBIOS git to verify there has been no regressions. Finally, for further info on SeaBIOS with coreboot see: http://www.coreboot.org/SeaBIOS -Kevin From patrick at georgi-clan.de Sat Aug 1 19:10:40 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 01 Aug 2009 19:10:40 +0200 Subject: [coreboot] [PATCH]es: enable CBFS for all boards Message-ID: <4A747710.8010602@georgi-clan.de> Hi, attached patches enable CBFS for all boards and fix various related issues. 20090801-1-model_lx-should-use-generic-copy-and-run cpu/amd/model_lx uses its own routine for copying coreboot_ram, I tried to make it use the generic infrastructure, but I can't test it due to lack of hardware. 20090801-2-fix-cpp-scope-of-strings This patch fixes the generic code for copying and running coreboot_ram in case certain configuration options are disabled. the strings were just at the wrong place. 20090801-3-only-fix-romstream-stuff-if-romstream-is-possible Two boards fix up some variables for romstream. This isn't necessary (or possible) when CBFS is active, as there is no romstream. It would be nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any invariant that forces that to be inactive if CBFS is active, and this patch is supposed to be small, esp. as the stream loaders are on the way out. 20090801-4-enable-cbfs-for-all-boards Big patch touching nearly every board, to enable CBFS. Everything built, but that's all testing I could do, as the boards I have available already have CBFS activated. Signed-off-by: Patrick Georgi Regards, Patrick -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090801-1-model_lx-should-use-generic-copy-and-run URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090801-2-fix-cpp-scope-of-strings URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090801-3-only-fix-romstream-stuff-if-romstream-is-possible URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090801-4-enable-cbfs-for-all-boards URL: From rminnich at gmail.com Sat Aug 1 19:22:55 2009 From: rminnich at gmail.com (ron minnich) Date: Sat, 1 Aug 2009 10:22:55 -0700 Subject: [coreboot] [PATCH]es: enable CBFS for all boards In-Reply-To: <4A747710.8010602@georgi-clan.de> References: <4A747710.8010602@georgi-clan.de> Message-ID: <13426df10908011022k3f9fba6cv47aea7f3503f5ab5@mail.gmail.com> I realize this is going to be a little painful, but we have to start moving forward. We really need cbfs, it's going to help us move out of the nasty arithmetic and hand sizing we do now. Stefan had an idea that we should start bumping the version number. I think this change means we are now coreboot 2.1 Acked-by: Ronald G. Minnich From Cristi.Magherusan at net.utcluj.ro Sat Aug 1 20:40:33 2009 From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan) Date: Sat, 01 Aug 2009 21:40:33 +0300 Subject: [coreboot] [PATCH]es: enable CBFS for all boards In-Reply-To: <4A747710.8010602@georgi-clan.de> References: <4A747710.8010602@georgi-clan.de> Message-ID: <1249152033.22970.4.camel@ufo> Hi Patrick, On Sat, 2009-08-01 at 19:10 +0200, Patrick Georgi wrote: > Hi, > > attached patches enable CBFS for all boards and fix various related issues. I'm eager to see it merged in the main v2 tree. Any timeframe? > 20090801-1-model_lx-should-use-generic-copy-and-run > cpu/amd/model_lx uses its own routine for copying coreboot_ram, I tried > to make it use the generic infrastructure, but I can't test it due to > lack of hardware. > > 20090801-2-fix-cpp-scope-of-strings > This patch fixes the generic code for copying and running coreboot_ram > in case certain configuration options are disabled. the strings were > just at the wrong place. > > 20090801-3-only-fix-romstream-stuff-if-romstream-is-possible > Two boards fix up some variables for romstream. This isn't necessary (or > possible) when CBFS is active, as there is no romstream. It would be > nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any > invariant that forces that to be inactive if CBFS is active, and this > patch is supposed to be small, esp. as the stream loaders are on the way > out. > > 20090801-4-enable-cbfs-for-all-boards > Big patch touching nearly every board, to enable CBFS. Everything built, > but that's all testing I could do, as the boards I have available > already have CBFS activated. I'll test it with Asus M2V-MX-SE and with qemu and LAB payloads. Thanks, Cristi. -- Ing. Cristi M?gheru?an, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part URL: From powerschorsch21 at yahoo.de Sat Aug 1 21:52:41 2009 From: powerschorsch21 at yahoo.de (Maxmimilian Niedernhuber) Date: Sat, 01 Aug 2009 21:52:41 +0200 Subject: [coreboot] Add VGA BIOS failed. Message-ID: <1249156361.3576.22.camel@Schorschmobile> Hallo, thanks for your answer. I had the coreboot-read.bin from the coreboot source "coreboot-v2-4475", it is just renamed (coreboot.rom). I used the target for IEI_JUKI_511P board because it is near the same as I have. I have two EEProm Chips ... it should be safe to test coreboot on this board. I changed the Config.lb, because I want to use seabios: payload /root/coreboot/bios.bin.elf-0.4.1 And I had a problem with the Rom size. ... I changed this: option CONFIG_COMPRESS=1 Then coreboot.rom compiled without an error. The next Step was to add the VGA bios. But it dosnt worked. Sorry for my bad english. From wangqingpei at gmail.com Sat Aug 1 22:27:36 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Sun, 2 Aug 2009 04:27:36 +0800 Subject: [coreboot] malloc.c problems of option rom Message-ID: Hi all, I added some printf message into malloc.c, and find that the function setup() which used to init the memory seems not executed very well. I put my own malloc.c and the log attached to this mail. Hope some one can help me to find out the problems. static void setup(void) { int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; *((hdrtype_t *) hstart) = FREE_BLOCK(size); printf("%s the memory size:0x%x,begin:0x%x end:0x%x, hstart:0x%x\n",__func__,size,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int )*((hdrtype_t *) hstart)); } static void *alloc(int len) { hdrtype_t header; void *ptr = hstart; printf("%s length=0x%x, the ptr=0x%x\n",__func__,len,(unsigned int )*((hdrtype_t*)ptr)); printf("%s the memory begin:0x%x end:0x%x, hstart:0x%x\n",__func__,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int )*((hdrtype_t *) hstart)); /* Align the size. */ len = (len + 3) & ~3; if (!len || len > 0xffffff) return (void *)NULL; /* Make sure the region is setup correctly. */ if (!HAS_MAGIC(*((hdrtype_t *) ptr))) setup(); if (!HAS_MAGIC(*((hdrtype_t *) ptr))){ printf("set up failed,ptr=0x%x\n",(unsigned int)*((hdrtype_t *) ptr)); } /* Find some free space. */ do { header = *((hdrtype_t *) ptr); int size = SIZE(header); if (!HAS_MAGIC(header) || size == 0) { printf("memory allocator panic!!! the size=0x%x. header=0x%x\n",size,(unsigned int)header); halt(); } if (header & FLAG_FREE) { if (len <= size) { void *nptr = ptr + (HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, * then mark it as such otherwise account * the whole space for that block. */ if (nsize > 0) { /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(len); /* Create a new free block. */ *((hdrtype_t *) nptr) = FREE_BLOCK(nsize); } else { /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(size); } return (void *)(ptr + HDRSIZE); } } ptr += HDRSIZE + size; } while (ptr < hend); /* Nothing available. */ return (void *)NULL; } log: Attempting to init PCI bdf 06:05.0 (dev/ven 30381106) Copying option rom (size 130560) from 0xfff00000 to ce000 Checking rom 0x000ce000 (sig aa55 size 255) Running option rom at ce00:0003 hello, initialize_usb 00:13.0 4387:1002.0 OHCI controller Not supported. 00:13.1 4388:1002.1 OHCI controller Not supported. 00:13.2 4389:1002.2 OHCI controller Not supported. 00:13.3 438a:1002.3 OHCI controller Not supported. 00:13.4 438b:1002.4 OHCI controller Not supported. 00:13.5 4386:1002.5 EHCI controller Not supported. 00:05.0 3038:1106.0 UHCI controller alloc length=0x238, the ptr=0x0 alloc the memory begin:0x7860 end:0x57860, hstart:0x0 setup the memory size:0x4fffc,begin:0x7860 end:0x57860, hstart:0xaa04fffc set up failed,ptr=0x0 memory allocator panic!!! the size=0x0. header=0x0 -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- /* * This file is part of the libpayload project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * This is a classically weak malloc() implementation. We have a relatively * small and static heap, so we take the easy route with an O(N) loop * through the tree for every malloc() and free(). Obviously, this doesn't * scale past a few hundred KB (if that). * * We're also susceptible to the usual buffer overrun poisoning, though the * risk is within acceptable ranges for this implementation (don't overrun * your buffers, kids!). */ #include extern char _heap, _eheap; /* Defined in the ldscript. */ static void *hstart = (void *)&_heap; static void *hend = (void *)&_eheap; typedef unsigned int hdrtype_t; #define MAGIC (0x2a << 26) #define FLAG_FREE (1 << 25) #define FLAG_USED (1 << 24) #define SIZE(_h) ((_h) & 0xFFFFFF) #define _HEADER(_s, _f) ((hdrtype_t) (MAGIC | (_f) | ((_s) & 0xFFFFFF))) #define FREE_BLOCK(_s) _HEADER(_s, FLAG_FREE) #define USED_BLOCK(_s) _HEADER(_s, FLAG_USED) #define HDRSIZE (sizeof(hdrtype_t)) #define IS_FREE(_h) (((_h) & (MAGIC | FLAG_FREE)) == (MAGIC | FLAG_FREE)) #define HAS_MAGIC(_h) (((_h) & MAGIC) == MAGIC) static int free_aligned(void* addr); void print_malloc_map(void); static void setup(void) { int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; *((hdrtype_t *) hstart) = FREE_BLOCK(size); printf("%s the memory size:0x%x,begin:0x%x end:0x%x, hstart:0x%x\n",__func__,size,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int )*((hdrtype_t *) hstart)); } static void *alloc(int len) { hdrtype_t header; void *ptr = hstart; printf("%s length=0x%x, the ptr=0x%x\n",__func__,len,(unsigned int )*((hdrtype_t*)ptr)); printf("%s the memory begin:0x%x end:0x%x, hstart:0x%x\n",__func__,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int )*((hdrtype_t *) hstart)); /* Align the size. */ len = (len + 3) & ~3; if (!len || len > 0xffffff) return (void *)NULL; /* Make sure the region is setup correctly. */ if (!HAS_MAGIC(*((hdrtype_t *) ptr))) setup(); if (!HAS_MAGIC(*((hdrtype_t *) ptr))){ printf("set up failed,ptr=0x%x\n",(unsigned int)*((hdrtype_t *) ptr)); } /* Find some free space. */ do { header = *((hdrtype_t *) ptr); int size = SIZE(header); if (!HAS_MAGIC(header) || size == 0) { printf("memory allocator panic!!! the size=0x%x. header=0x%x\n",size,(unsigned int)header); halt(); } if (header & FLAG_FREE) { if (len <= size) { void *nptr = ptr + (HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, * then mark it as such otherwise account * the whole space for that block. */ if (nsize > 0) { /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(len); /* Create a new free block. */ *((hdrtype_t *) nptr) = FREE_BLOCK(nsize); } else { /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(size); } return (void *)(ptr + HDRSIZE); } } ptr += HDRSIZE + size; } while (ptr < hend); /* Nothing available. */ return (void *)NULL; } static void _consolidate(void) { void *ptr = hstart; while (ptr < hend) { void *nptr; hdrtype_t hdr = *((hdrtype_t *) ptr); unsigned int size = 0; if (!IS_FREE(hdr)) { ptr += HDRSIZE + SIZE(hdr); continue; } size = SIZE(hdr); nptr = ptr + HDRSIZE + SIZE(hdr); while (nptr < hend) { hdrtype_t nhdr = *((hdrtype_t *) nptr); if (!(IS_FREE(nhdr))) break; size += SIZE(nhdr) + HDRSIZE; *((hdrtype_t *) nptr) = 0; nptr += (HDRSIZE + SIZE(nhdr)); } *((hdrtype_t *) ptr) = FREE_BLOCK(size); ptr = nptr; } } void free(void *ptr) { hdrtype_t hdr; if (free_aligned(ptr)) return; ptr -= HDRSIZE; /* Sanity check. */ if (ptr < hstart || ptr >= hend) return; hdr = *((hdrtype_t *) ptr); /* Not our header (we're probably poisoned). */ if (!HAS_MAGIC(hdr)) return; /* Double free. */ if (hdr & FLAG_FREE) return; *((hdrtype_t *) ptr) = FREE_BLOCK(SIZE(hdr)); _consolidate(); } void *malloc(size_t size) { return alloc(size); } void *calloc(size_t nmemb, size_t size) { size_t total = nmemb * size; void *ptr = alloc(total); if (ptr) memset(ptr, 0, total); return ptr; } void *realloc(void *ptr, size_t size) { void *ret, *pptr; unsigned int osize; if (ptr == NULL) return alloc(size); pptr = ptr - HDRSIZE; if (!HAS_MAGIC(*((hdrtype_t *) pptr))) return NULL; /* Get the original size of the block. */ osize = SIZE(*((hdrtype_t *) pptr)); /* * Free the memory to update the tables - this won't touch the actual * memory, so we can still use it for the copy after we have * reallocated the new space. */ free(ptr); ret = alloc(size); /* * if ret == NULL, then doh - failure. * if ret == ptr then woo-hoo! no copy needed. */ if (ret == NULL || ret == ptr) return ret; /* Copy the memory to the new location. */ memcpy(ret, ptr, osize > size ? size : osize); return ret; } struct align_region_t { int alignment; /* start in memory, and size in bytes */ void* start; int size; /* layout within a region: - num_elements bytes, 0: free, 1: used, 2: used, combines with next - padding to alignment - data section - waste space start_data points to the start of the data section */ void* start_data; /* number of free blocks sized "alignment" */ int free; struct align_region_t *next; }; static struct align_region_t* align_regions = 0; static struct align_region_t *allocate_region(struct align_region_t *old_first, int alignment, int num_elements) { struct align_region_t *new_region = malloc(sizeof(struct align_region_t)); new_region->alignment = alignment; new_region->start = malloc((num_elements+1) * alignment + num_elements); new_region->start_data = (void*)((u32)(new_region->start + num_elements + alignment - 1) & (~(alignment-1))); new_region->size = num_elements * alignment; new_region->free = num_elements; new_region->next = old_first; memset(new_region->start, 0, num_elements); return new_region; } static int free_aligned(void* addr) { struct align_region_t *reg = align_regions; while (reg != 0) { if ((addr >= reg->start_data) && (addr < reg->start_data + reg->size)) { int i = (addr-reg->start_data)/reg->alignment; while (((u8*)reg->start)[i]==2) { ((u8*)reg->start)[i++]=0; reg->free++; } ((u8*)reg->start)[i]=0; reg->free++; return 1; } reg = reg->next; } return 0; } void *memalign(size_t align, size_t size) { if (size == 0) return 0; if (align_regions == 0) { align_regions = malloc(sizeof(struct align_region_t)); if (align_regions == NULL) return NULL; memset(align_regions, 0, sizeof(struct align_region_t)); } struct align_region_t *reg = align_regions; look_further: while (reg != 0) { if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align)) { break; } reg = reg->next; } if (reg == 0) { align_regions = allocate_region(align_regions, align, (size/align<99)?100:((size/align)+1)); reg = align_regions; } int i, count = 0, target = (size+align-1)/align; for (i = 0; i < (reg->size/align); i++) { if (((u8*)reg->start)[i] == 0) { count++; if (count == target) { count = i+1-count; for (i=0; istart)[count+i]=2; } ((u8*)reg->start)[count+target-1]=1; reg->free -= target; return reg->start_data+(align*count); } } else { count = 0; } } goto look_further; // end condition is once a new region is allocated - it always has enough space } /* This is for debugging purposes. */ #ifdef TEST void print_malloc_map(void) { void *ptr = hstart; while (ptr < hend) { hdrtype_t hdr = *((hdrtype_t *) ptr); if (!HAS_MAGIC(hdr)) { printf("Poisoned magic - we're toast\n"); break; } /* FIXME: Verify the size of the block. */ printf("%x: %s (%x bytes)\n", (unsigned int)(ptr - hstart), hdr & FLAG_FREE ? "FREE" : "USED", SIZE(hdr)); ptr += HDRSIZE + SIZE(hdr); } } #endif -------------- next part -------------- coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 starting... bsp_apicid=0x0 core0 started: 01SBLink=00 NC node|link=00 rs690_early_setup() get_cpu_rev EAX=0x60f82. CPU Rev is K8_G0. NB Revision is A12. k8_optimization() rs690_por_init sb600_early_setup() sb600_devices_por_init() sb600_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is 0x13 sb600_devices_por_init(): IDE Device, BDF:0-20-1 sb600_devices_por_init(): LPC Device, BDF:0-20-3 sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 sb600_devices_por_init(): SATA Device, BDF:0-18-0 sb600_pmio_por_init() begin msr fid, vid: hi=0x32111e1e, lo=0x110d0000 Current fid_cur: 0x0, fid_max: 0xd Requested fid_new: 0xd FidVid table step fidvid: 0xa FidVid table step fidvid: 0xa 200MHZ step fidvid: 0xc 200MHZ step fidvid: 0xc 200MHZ step fidvid: 0xc 200MHZ step fidvid: 0xc 100MHZ step fidvid: 0xd end msr fid, vid: hi=0x32111e11, lo=0x110d000d needs_reset=0x1 ht reset - coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 starting... bsp_apicid=0x0 core0 started: 01SBLink=00 NC node|link=00 rs690_early_setup() get_cpu_rev EAX=0x60f82. CPU Rev is K8_G0. NB Revision is A12. k8_optimization() rs690_por_init sb600_early_setup() sb600_devices_por_init() sb600_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is 0x13 sb600_devices_por_init(): IDE Device, BDF:0-20-1 sb600_devices_por_init(): LPC Device, BDF:0-20-3 sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 sb600_devices_por_init(): SATA Device, BDF:0-18-0 sb600_pmio_por_init() begin msr fid, vid: hi=0x32111e11, lo=0x110d000d end msr fid, vid: hi=0x32111e11, lo=0x110d000d needs_reset=0x0 sysinfo->nodes: 1 sysinfo->ctrl: cf188 spd_addr: ffffa348 Ram1.00 Ram2.00 sdram_set_spd_registers: paramx :000cece4 Unbuffered 400MHz 400MHz RAM: 0x00100000 kB Ram3 sdram_enable: tsc0[8]: 000ceda4Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 1024MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=15 done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce870 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=2c done DQS SAVE NVRAM: c2000 DQS Training:tsc[00]=0000000018251b35 DQS Training:tsc[01]=00000000193f8558 DQS Training:tsc[02]=000000001946b6a3 DQS Training:tsc[03]=000000003adf7190 DQS Training:tsc[04]=000000003c163939 Ram4 v_esp=000cee78 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing image to RAM. Jumping to image. coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 booting... Enumerating buses... Mainboard DBM690T Enable. dev=0x00025690 dbm690t_enable, TOP MEM: msr.lo = 0x40000000, msr.hi = 0x00000000 dbm690t_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000 dbm690t_enable: uma size 0x08000000, memory start 0x38000000 enable_onboard_nic. Init adt7461 end , status 0x02 00 APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled rs690_enable: dev=00027908, VID_DID=0x79101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x00027908, dev=0x00029b68, port=0x8 PCI: 00:00.0 [1002/7910] enabled PCI: 00:00.0 [1002/7910] enabled next_unitid: 0015 PCI: pci_scan_bus for bus 00 rs690_enable: dev=00027908, VID_DID=0x79101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x00027908, dev=0x00029b68, port=0x8 PCI: 00:00.0 [1002/7910] enabled rs690_enable: dev=00027d54, VID_DID=0x79121002 Bus-0, Dev-1, Fun-0. PCI: 00:01.0 [1002/7912] enabled rs690_enable: dev=000281a0, VID_DID=0x79131002 Bus-0, Dev-2,3, Fun-0. enable=1 rs690_gfx_init, nb_dev=0x00027908, dev=0x000281a0, port=0x2. rs690_gfx_init step0. rs690_gfx_init step1. rs690_gfx_init step2. rs690_gfx_init step4. rs690_gfx_init step8.1. rs690_gfx_init step8.2. rs690_gfx_init step8.3. rs690_gfx_init step8.4. rs690_gfx_init step8.5. rs690_gfx_init step8.6. rs690_gfx_init step8.8. rs690_gfx_init step8.9. rs690_gfx_init step8.10. rs690_gfx_init step8.11. rs690_gfx_init step8.12. rs690_gfx_init step8.13. rs690_gfx_init single_port_configuration. PcieLinkTraining port=2:lc current state=2030400 rs690_gfx_init single_port_configuration step12. rs690_gfx_init single_port_configuration step13. rs690_gfx_init single_port_configuration step14. Disabling static device: PCI: 00:02.0 rs690_enable: dev=000285ec, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=0 rs690_enable: dev=00028a38, VID_DID=0x79141002 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x00027908, dev=0x00028a38, port=0x4 PcieLinkTraining port=4:lc current state=4000102 PcieTrainPort port=0x4 result=0 PCI: 00:04.0 subbordinate bus PCI Express PCI: 00:04.0 [1002/7914] enabled rs690_enable: dev=00028e84, VID_DID=0x79151002 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x00027908, dev=0x00028e84, port=0x5 PcieLinkTraining port=5:lc current state=4000102 PcieTrainPort port=0x5 result=0 PCI: 00:05.0 subbordinate bus PCI Express PCI: 00:05.0 [1002/7915] enabled rs690_enable: dev=000292d0, VID_DID=0x79161002 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x00027908, dev=0x000292d0, port=0x6 PcieLinkTraining port=6:lc current state=4000102 PcieTrainPort port=0x6 result=0 PCI: 00:06.0 subbordinate bus PCI Express PCI: 00:06.0 [1002/7916] enabled rs690_enable: dev=0002971c, VID_DID=0x79171002 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x00027908, dev=0x0002971c, port=0x7 PcieLinkTraining port=7:lc current state=a0b0f10 addr=e0000004,bus=0,devfn=38 PcieTrainPort reg=0x0 PcieTrainPort port=0x7 result=1 PCI: 00:07.0 subbordinate bus PCI Express PCI: 00:07.0 [1002/7917] enabled rs690_enable: dev=00029b68, VID_DID=0x79181002 Bus-0, Dev-8, Fun-0. enable=0 disable_pcie_bar3() sb600_enable() PCI: 00:12.0 [1002/4380] enabled sb600_enable() PCI: 00:13.0 [1002/4387] enabled sb600_enable() PCI: 00:13.1 [1002/4388] enabled sb600_enable() PCI: 00:13.2 [1002/4389] enabled sb600_enable() PCI: 00:13.3 [1002/438a] enabled sb600_enable() PCI: 00:13.4 [1002/438b] enabled sb600_enable() PCI: 00:13.5 [1002/4386] enabled sb600_enable() PCI: 00:14.0 [1002/4385] enabled sb600_enable() PCI: 00:14.1 [1002/438c] enabled sb600_enable() PCI: 00:14.2 [1002/4383] enabled sb600_enable() PCI: 00:14.3 [1002/438d] enabled sb600_enable() PCI: 00:14.4 [1002/4384] enabled sb600_enable() PCI: 00:14.5 [1002/4382] enabled sb600_enable() PCI: 00:14.6 [1002/438e] enabled PCI: pci_scan_bus for bus 01 rs690_internal_gfx_enable dev=0x00029fb8, nb_dev=0x00027908. nb_dev, 0x8c=0x10002333 PCI: 01:05.0 [1002/791f] enabled PCI: 01:05.2 [1002/7919] enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus for bus 05 PCI: 05:00.0 [14e4/169d] enabled PCI: pci_scan_bus returning with max=005 PCIe: tuning PCI: 05:00.0 smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 disabled PNP: 002e.4 disabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PCI: pci_scan_bus for bus 06 PCI: 06:05.0 [1106/3038] enabled PCI: 06:05.1 [1106/3038] enabled PCI: 06:05.2 [1106/3104] enabled PCI: pci_scan_bus returning with max=006 PCI: pci_scan_bus returning with max=006 PCI: pci_scan_bus returning with max=006 done Allocating resources... Reading resources... PCI: 00:00.0 register 1c(e0000004), read-only ignoring it rs690_gfx_read_resources. PCI: 00:04.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:05.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 03 io PCI: 00:05.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:05.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:06.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 04 io PCI: 00:06.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:06.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:07.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 05 io PCI: 00:07.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:14.4 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 06 prefmem Done reading resources. Allocating VGA resource PCI: 01:05.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... 0: mmio_basek=003c0000, basek=00000300, limitk=00100000 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io PCI: 00:18.0 1b8 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 prefmem PCI: 00:18.0 1b0 <- [0x00fc000000 - 0x00fc4fffff] size 0x00500000 gran 0x14 mem PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 01:05.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem64 PCI: 01:05.0 18 <- [0x00fc100000 - 0x00fc10ffff] size 0x00010000 gran 0x10 mem64 PCI: 01:05.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:05.0 24 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 mem PCI: 01:05.0 30 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x00 romem PCI: 01:05.2 10 <- [0x00fc110000 - 0x00fc113fff] size 0x00004000 gran 0x0e mem64 PCI: 00:07.0 20 <- [0x00fc200000 - 0x00fc2fffff] size 0x00100000 gran 0x14 bus 05 mem PCI: 05:00.0 10 <- [0x00fc200000 - 0x00fc20ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:12.0 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io PCI: 00:12.0 14 <- [0x0000003060 - 0x0000003063] size 0x00000004 gran 0x02 io PCI: 00:12.0 18 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io PCI: 00:12.0 1c <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io PCI: 00:12.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran 0x04 io PCI: 00:12.0 24 <- [0x00fc409000 - 0x00fc4093ff] size 0x00000400 gran 0x0a mem PCI: 00:13.0 10 <- [0x00fc404000 - 0x00fc404fff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00fc405000 - 0x00fc405fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00fc406000 - 0x00fc406fff] size 0x00001000 gran 0x0c mem PCI: 00:13.3 10 <- [0x00fc407000 - 0x00fc407fff] size 0x00001000 gran 0x0c mem PCI: 00:13.4 10 <- [0x00fc408000 - 0x00fc408fff] size 0x00001000 gran 0x0c mem PCI: 00:13.5 10 <- [0x00fc40a000 - 0x00fc40a0ff] size 0x00000100 gran 0x08 mem ERROR: PCI: 00:14.0 74 mem size: 0x0000001000 not assigned ERROR: PCI: 00:14.0 14 mem size: 0x0000000400 not assigned ERROR: PCI: 00:14.0 10 io size: 0x0000000010 not assigned PCI: 00:14.1 10 <- [0x0000003040 - 0x0000003047] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000003080 - 0x0000003083] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000003010 - 0x000000301f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00fc400000 - 0x00fc403fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00fc40d000 - 0x00fc40d01f] size 0x00000020 gran 0x05 mem PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PCI: 00:14.4 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 06 io PCI: 00:14.4 20 <- [0x00fc300000 - 0x00fc3fffff] size 0x00100000 gran 0x14 bus 06 mem PCI: 06:05.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 06:05.1 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io PCI: 06:05.2 10 <- [0x00fc300000 - 0x00fc3000ff] size 0x00000100 gran 0x08 mem PCI: 00:14.5 10 <- [0x00fc40b000 - 0x00fc40b0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.6 10 <- [0x00fc40c000 - 0x00fc40c0ff] size 0x00000100 gran 0x08 mem PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem Done setting resources. Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:00.0 subsystem <- 1022/3050 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 01:05.0 subsystem <- 1022/3050 PCI: 01:05.0 cmd <- 03 PCI: 01:05.2 cmd <- 02 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:05.0 bridge ctrl <- 0003 PCI: 00:05.0 cmd <- 00 PCI: 00:06.0 bridge ctrl <- 0003 PCI: 00:06.0 cmd <- 00 PCI: 00:07.0 bridge ctrl <- 0003 PCI: 00:07.0 cmd <- 06 PCI: 05:00.0 cmd <- 02 PCI: 00:12.0 cmd <- 03 PCI: 00:13.0 subsystem <- 1022/3050 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1022/3050 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1022/3050 PCI: 00:13.2 cmd <- 02 PCI: 00:13.3 subsystem <- 1022/3050 PCI: 00:13.3 cmd <- 02 PCI: 00:13.4 subsystem <- 1022/3050 PCI: 00:13.4 cmd <- 02 PCI: 00:13.5 subsystem <- 1022/3050 PCI: 00:13.5 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/3050 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1022/3050 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1022/3050 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1022/3050 PCI: 00:14.3 cmd <- 0f sb600 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff sb600 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 sb600 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 07 PCI: 06:05.0 cmd <- 01 PCI: 06:05.1 cmd <- 01 PCI: 06:05.2 cmd <- 02 PCI: 00:14.5 subsystem <- 1022/3050 PCI: 00:14.5 cmd <- 02 PCI: 00:14.6 subsystem <- 1022/3050 PCI: 00:14.6 cmd <- 02 PCI: 00:18.1 subsystem <- 1022/3050 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/3050 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device 60f82 CPU: family 0f, model 68, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB Setting variable MTRR 1, base: 1024MB, range: 128MB, type WB Setting variable MTRR 2, base: 896MB, range: 128MB, type UC DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Turion(tm) 64 X2 Mobile Technology TL-62 Setting up local apic... apic_id: 0x00 done. ECC Disabled CPU #0 initialized Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device 60f82 CPU: family 0f, model 68, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB Setting variable MTRR 1, base: 1024MB, range: 128MB, type WB Setting variable MTRR 2, base: 896MB, range: 128MB, type UC DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Turion(tm) 64 X2 Mobile Technology TL-62 Setting up local apic... apic_id: 0x01 done. CPU #1 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:00.0 init pcie_init in rs690_ht.c PCI: 01:05.0 init internal_gfx_pci_dev_init device=791f, vendor=1002, vga_rom_address=0xfff00000. On mainboard, rom address for PCI: 01:05.0 = fff00000 Device or Vendor ID mismatch Vendor 1002, Device 4387 PCI: 00:12.0 init No Primary Master SATA drive on Slot0 No Primary Slave SATA drive on Slot1 No Secondary Master SATA drive on Slot2 No Secondary Slave SATA drive on Slot3 PCI: 00:13.0 init PCI: 00:13.1 init PCI: 00:13.2 init PCI: 00:13.3 init PCI: 00:13.4 init PCI: 00:13.5 init usb2_bar0=fc40a000 PCI: 00:14.0 init sm_init(). lapicid = 0000000000000000 set power on after power fail ++++++++++no set NMI+++++ RTC Init 3.11, ABCFG:0x54 3.12, ABCFG:0x54 sm_init() end PCI: 00:14.1 init On mainboard, rom address for PCI: 00:14.1 = 0 PCI: 00:14.2 init base = fc400000 codec_mask = 04 codec viddid: 10ec0882 Dev=PCI: 00:14.2 Default viddid=10ec0882 Reading viddid=10ec0882 verb_size: 48 verb loaded! PCI: 00:14.3 init PNP: 002e.1 init PNP: 002e.5 init Keyboard init... Keyboard selftest failed ACK: 0xfe PNP: 002e.6 init PCI: 00:14.4 init PCI: 00:18.1 init On mainboard, rom address for PCI: 00:18.1 = 0 PCI: 00:18.2 init On mainboard, rom address for PCI: 00:18.2 = 0 PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 01:05.2 init On card, rom address for PCI: 01:05.2 = 0 PCI: 05:00.0 init On card, rom address for PCI: 05:00.0 = 0 PCI: 06:05.0 init On card, rom address for PCI: 06:05.0 = 0 PCI: 06:05.1 init On card, rom address for PCI: 06:05.1 = 0 PCI: 06:05.2 init On card, rom address for PCI: 06:05.2 = 0 Devices initialized High Tables Base is 3fff0000. Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. Writing IRQ routing tables to 0x3fff0000...write_pirq_routing_table done. ACPI: Writing ACPI tables at 3fff0400... ACPI: * HPET ACPI: added table 1/9 Length now 40 ACPI: * MADT ACPI: added table 2/9 Length now 44 ACPI: * SSDT processor_brand=AMD Turion(tm) 64 X2 Mobile Technology TL-62 Pstates Algorithm ... Pstate_freq[0] = 2100MHz Pstate_vid[0] = 19 Pstate_volt[0] = 1075mv Pstate_power[0] = 35 000mw Pstate_freq[1] = 2000MHz Pstate_vid[1] = 20 Pstate_volt[1] = 1050mv Pstate_power[1] = 31 800mw Pstate_freq[2] = 1800MHz Pstate_vid[2] = 21 Pstate_volt[2] = 1025mv Pstate_power[2] = 27 274mw Pstate_freq[3] = 1600MHz Pstate_vid[3] = 22 Pstate_volt[3] = 1000mv Pstate_power[3] = 23 075mw Pstate_freq[4] = 800MHz Pstate_vid[4] = 30 Pstate_volt[4] = 800mv Pstate_power[4] = 7384mw ACPI: added table 3/9 Length now 48 ACPI: * FACS ACPI: * DSDT ACPI: * DSDT @ 3fff08ba Length 267c ACPI: * FADT pm_base: 0x0800 ACPI: added table 4/9 Length now 52 ACPI: done. Wrote the mp table end at: 00000020 - 00000134 Wrote the mp table end at: 3fff3410 - 3fff3524 Moving GDT to 0x3fff3800...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 83df New low_table_end: 0x00000500 Now going to write high coreboot table at 0x3fff3c00 rom_table_end = 0x3fff3c00 Adjust low_table_end from 0x00000500 to 0x00001000 Adjust rom_table_end from 0x3fff3c00 to 0x40000000 Adding high table area uma_memory_base=0x38000000, uma_memory_size=0x8000000 Wrote coreboot table at: 3fff3c00 - 3fff3de4 checksum b52b elfboot: Attempting to load payload. rom_stream: 0xfffc0000 - 0xfffdffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000 (cleaned up) New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000 Dropping non PT_LOAD segment Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x0000000000010000 Jumping to boot code at 000fc275 Start bios init ivt init bda init pic init timer tsc calibrate start=3490835980 end=3494443139 diff=3607159 CPU Mhz=2101 math cp init bios_table_addr: 0x000fd500 end=0x000fdd00 Find memory size Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map init SMBIOS tables SMBIOS table addr=0x000fd500 Ram Size=0x38000000 Found 2 cpu(s) init PNPBIOS table Scan for VGA option rom Attempting to init PCI bdf 01:05.0 (dev/ven 791f1002) Copying option rom (size 55808) from 0xfff1fe00 to c0000 Checking rom 0x000c0000 (sig aa55 size 109) Running option rom at c000:0003 fail handle_15XX:314(86): a=01284e08 b=00000080 c=00000000 d=0000c000 ds=c000 es=f000 ss=0000 si=0000abac di=0000b24c bp=00000000 sp=00007a6a cs=c000 ip=2ca6 f=0046 fail handle_15XX:314(86): a=07ff4e08 b=00000005 c=00004e17 d=0000c002 ds=c000 es=f000 ss=0000 si=00002d3c di=0000b24c bp=00007a4e sp=00007a6a cs=c000 ip=2c43 f=0046 fail handle_15XX:314(86): a=00004e08 b=00000000 c=0000a401 d=00000080 ds=c000 es=f000 ss=0000 si=0000abac di=0000b24c bp=00007a4e sp=00007a68 cs=c000 ip=2bfd f=0046 Turning on vga console Starting SeaBIOS init keyboard i8042 ctr old=0 new=20 Got ps2 nak (status=51); continuing ps2_recvbyte timeout keyboard command 2ff failed init lpt Found 0 lpt ports init serial Found 1 serial ports init mouse e820 map has 5 items: 0: 0000000000000000 - 000000000009fc00 = 1 1: 000000000009fc00 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 0000000038000000 = 1 4: 0000000038000000 - 0000000040000000 = 2 final bios_table_addr: 0x000fd5e3 (used 11%) init boot device ordering init floppy drives init hard drives ATA controller 0 at 3020/3060 (dev 90 prog_if 8f) ATA controller 1 at 3030/3070 (dev 90 prog_if 8f) ATA controller 2 at 1f0/3f0 (dev a1 prog_if 8a) ATA controller 3 at 170/370 (dev a1 prog_if 8a) powerup iobase=3020 st=7f powerup iobase=3020 st=7f ata_detect drive=0 sc=7f sn=7f dh=7f powerup iobase=3020 st=7f powerup iobase=3020 st=7f ata_detect drive=1 sc=7f sn=7f dh=7f powerup iobase=3030 st=7f powerup iobase=3030 st=7f ata_detect drive=2 sc=7f sn=7f dh=7f powerup iobase=3030 st=7f powerup iobase=3030 st=7f ata_detect drive=3 sc=7f sn=7f dh=7f powerup IDE floating powerup IDE floating ata_detect drive=4 sc=ff sn=ff dh=ff powerup IDE floating powerup IDE floating ata_detect drive=5 sc=ff sn=ff dh=ff powerup IDE floating powerup IDE floating ata_detect drive=6 sc=ff sn=ff dh=ff powerup IDE floating powerup IDE floating ata_detect drive=7 sc=ff sn=ff dh=ff Scan for option roms Attempting to init PCI bdf 00:00.0 (dev/ven 79101002) Attempting to map option rom on dev 00:00.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:01.0 (dev/ven 79121002) Attempting to map option rom on dev 00:01.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:04.0 (dev/ven 79141002) Attempting to map option rom on dev 00:04.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:05.0 (dev/ven 79151002) Attempting to map option rom on dev 00:05.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:06.0 (dev/ven 79161002) Attempting to map option rom on dev 00:06.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:07.0 (dev/ven 79171002) Attempting to map option rom on dev 00:07.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:13.0 (dev/ven 43871002) Attempting to map option rom on dev 00:13.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:13.1 (dev/ven 43881002) Attempting to map option rom on dev 00:13.1 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:13.2 (dev/ven 43891002) Attempting to map option rom on dev 00:13.2 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:13.3 (dev/ven 438a1002) Attempting to map option rom on dev 00:13.3 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:13.4 (dev/ven 438b1002) Attempting to map option rom on dev 00:13.4 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:13.5 (dev/ven 43861002) Attempting to map option rom on dev 00:13.5 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:14.0 (dev/ven 43851002) Attempting to map option rom on dev 00:14.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:14.2 (dev/ven 43831002) Attempting to map option rom on dev 00:14.2 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:14.3 (dev/ven 438d1002) Attempting to map option rom on dev 00:14.3 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:14.4 (dev/ven 43841002) Attempting to map option rom on dev 00:14.4 Skipping non-normal pci device (type=81) Attempting to init PCI bdf 00:18.0 (dev/ven 11001022) Attempting to map option rom on dev 00:18.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:18.1 (dev/ven 11011022) Attempting to map option rom on dev 00:18.1 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:18.2 (dev/ven 11021022) Attempting to map option rom on dev 00:18.2 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:18.3 (dev/ven 11031022) Attempting to map option rom on dev 00:18.3 Option rom sizing returned 0 0 Attempting to init PCI bdf 01:05.2 (dev/ven 79191002) Attempting to map option rom on dev 01:05.2 Option rom sizing returned 0 0 Attempting to init PCI bdf 05:00.0 (dev/ven 169d14e4) Attempting to map option rom on dev 05:00.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 06:05.0 (dev/ven 30381106) Copying option rom (size 130560) from 0xfff00000 to ce000 Checking rom 0x000ce000 (sig aa55 size 255) Running option rom at ce00:0003 hello, initialize_usb 00:13.0 4387:1002.0 OHCI controller Not supported. 00:13.1 4388:1002.1 OHCI controller Not supported. 00:13.2 4389:1002.2 OHCI controller Not supported. 00:13.3 438a:1002.3 OHCI controller Not supported. 00:13.4 438b:1002.4 OHCI controller Not supported. 00:13.5 4386:1002.5 EHCI controller Not supported. 00:05.0 3038:1106.0 UHCI controller alloc length=0x238, the ptr=0x0 alloc the memory begin:0x7860 end:0x57860, hstart:0x0 setup the memory size:0x4fffc,begin:0x7860 end:0x57860, hstart:0xaa04fffc set up failed,ptr=0x0 memory allocator panic!!! the size=0x0. header=0x0 From rminnich at gmail.com Sat Aug 1 22:45:13 2009 From: rminnich at gmail.com (ron minnich) Date: Sat, 1 Aug 2009 13:45:13 -0700 Subject: [coreboot] Add VGA BIOS failed. In-Reply-To: <1249156361.3576.22.camel@Schorschmobile> References: <1249156361.3576.22.camel@Schorschmobile> Message-ID: <13426df10908011345t1cc1b159j688e7afdf5abf768@mail.gmail.com> I had this problem too. I wonder: add vgabios.bin pci1078,0104.rom 0 ^ is that a letter "O" or a number "0". It looks like a zero. I think it needs to be an o? Sorry, I am running on memory here, and can't test it right now, can you verify that you are using the right "type" as the final argument? ron From mylesgw at gmail.com Sun Aug 2 01:23:05 2009 From: mylesgw at gmail.com (Myles Watson) Date: Sat, 1 Aug 2009 17:23:05 -0600 Subject: [coreboot] Add VGA BIOS failed. In-Reply-To: <1249156361.3576.22.camel@Schorschmobile> References: <1249156361.3576.22.camel@Schorschmobile> Message-ID: <266BF50461ED4521AC258042F6FFA621@chimp> > Hallo, thanks for your answer. I had the coreboot-read.bin from the > coreboot source "coreboot-v2-4475", it is just renamed (coreboot.rom). I > used the target for IEI_JUKI_511P board because it is near the same as I > have. Does this board have CBFS support? If it didn't, try this again with Patrick's patches. The error looks like cbfstool didn't find CBFS in your ROM image. Thanks, Myles From rminnich at gmail.com Sun Aug 2 01:46:49 2009 From: rminnich at gmail.com (ron minnich) Date: Sat, 1 Aug 2009 16:46:49 -0700 Subject: [coreboot] Add VGA BIOS failed. In-Reply-To: <266BF50461ED4521AC258042F6FFA621@chimp> References: <1249156361.3576.22.camel@Schorschmobile> <266BF50461ED4521AC258042F6FFA621@chimp> Message-ID: <13426df10908011646ge05fe7dicf0f1225302b8182@mail.gmail.com> On Sat, Aug 1, 2009 at 4:23 PM, Myles Watson wrote: > >> Hallo, thanks for your answer. I had the coreboot-read.bin from the >> coreboot source "coreboot-v2-4475", it is just renamed (coreboot.rom). I >> used the target for IEI_JUKI_511P board because it is near the same as I >> have. > > Does this board have CBFS support? ?If it didn't, try this again with > Patrick's patches. ?The error looks like cbfstool didn't find CBFS in your > ROM image. yes, what was I thinking? Do what Myles said :-) The one test worth always making cbfstool print That can tell you right away what's going on. ron From powerschorsch21 at yahoo.de Sun Aug 2 10:46:13 2009 From: powerschorsch21 at yahoo.de (Maxmimilian Niedernhuber) Date: Sun, 02 Aug 2009 10:46:13 +0200 Subject: [coreboot] Add VGA BIOS failed. In-Reply-To: References: Message-ID: <1249202773.3633.4.camel@Schorschmobile> Thanks for your answers! Where I can get the CBFS patches? From kevin at koconnor.net Sun Aug 2 10:57:55 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Sun, 2 Aug 2009 04:57:55 -0400 Subject: [coreboot] vga not working In-Reply-To: <2831fecf0907300856x69d67d80maf569e43b526b1bd@mail.gmail.com> References: <20090726134838.GA30132@morn.localdomain> <4A6D5B8C.1090806@4dsp.com> <4A6ED806.3080401@4dsp.com> <20090729005752.GA11700@morn.localdomain> <4A7008FF.4000306@4dsp.com> <2831fecf0907300856x69d67d80maf569e43b526b1bd@mail.gmail.com> Message-ID: <20090802085755.GA10680@morn.localdomain> On Thu, Jul 30, 2009 at 09:56:20AM -0600, Myles Watson wrote: > On Wed, Jul 29, 2009 at 2:31 AM, Arnaud Maye wrote: > > We are talking about the GFX cards legacy ranges, right? I think > > Myles looked at the PCI allocation already it seems everything is > > fine there. > > Actually I said that it wouldn't be related to the allocator because the > legacy VGA ranges are not aren't allocated there. This is the place to > start to look for that: [...] > 1. Make sure that that's the path to your graphics card. > 2. Make sure that the correct bits get set in each device so that the I/O to > the graphics card gets there. > - The PCI_BRIDGE_CTL_VGA bit is in the device structure, so it doesn't > affect hardware > - Many bridges need some bit set to decode those ranges In addition to making sure the legacy IO ranges are correct, you also need to verify the legacy vga memory range (0xa0000 - 0xc0000) is properly configured in the bridges. Also, the chipset needs to have this range be a pci hole - it must not have memory mapped there. -Kevin From paulepanter at users.sourceforge.net Sun Aug 2 12:25:12 2009 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Sun, 02 Aug 2009 12:25:12 +0200 Subject: [coreboot] Add VGA BIOS failed. In-Reply-To: <1249202773.3633.4.camel@Schorschmobile> References: <1249202773.3633.4.camel@Schorschmobile> Message-ID: <1249208712.6685.10.camel@mattotaupa.wohnung.familie-menzel.net> Dear Maximilian, Am Sonntag, den 02.08.2009, 10:46 +0200 schrieb Maxmimilian Niedernhuber: [typo in your name in your Evolution account] [?] > Where I can get the CBFS patches? I believe they talk about these patches [1]. Bests, Paul [1] http://www.coreboot.org/pipermail/coreboot/2009-August/051071.html -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: Dies ist ein digital signierter Nachrichtenteil URL: From peka at min-epost.net Sun Aug 2 13:31:13 2009 From: peka at min-epost.net (pk) Date: Sun, 02 Aug 2009 13:31:13 +0200 Subject: [coreboot] Interesting subject on /. Message-ID: <4A757901.4050506@min-epost.net> http://it.slashdot.org/story/09/08/01/2247225/Bootkit-Bypasses-TrueCrypt-Encryption Thought it might be of interest to people on coreboot... (if not I apologize). Best regards Peter K From wangqingpei at gmail.com Sun Aug 2 15:37:38 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Sun, 2 Aug 2009 21:37:38 +0800 Subject: [coreboot] malloc.c problems of option rom In-Reply-To: References: Message-ID: updated the new, which changed the display value static void setup(void) { int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; *((hdrtype_t *) hstart) = FREE_BLOCK(size); // printf("%s memory size:0x%x,begin:0x%x end:0x%x, hstart:0x%x\n",__func__,size,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int )*((hdrtype_t *) hstart)); } static void *alloc(int len) { hdrtype_t header; void *ptr = hstart; printf("%s %d length:0x%x,ptr=0x%x \n",__func__,__LINE__,len,(unsigned int )ptr); printf("%s %d memory begin:0x%x end:0x%x, hstart:0x%x\n",__func__,__LINE__,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int ) hstart); /* Align the size. */ len = (len + 3) & ~3; if (!len || len > 0xffffff) return (void *)NULL; // while(1); /* Make sure the region is setup correctly. */ if (!HAS_MAGIC(*((hdrtype_t *) ptr))){ setup(); } if (!HAS_MAGIC(*((hdrtype_t *) ptr))){ printf("set up error,*ptr=0x%x\n",(unsigned int)*((hdrtype_t *) ptr)); } /* Find some free space. */ do { header = *((hdrtype_t *) ptr); int size = SIZE(header); if (!HAS_MAGIC(header) || size == 0) { printf("memory allocator panic!!! the size=0x%x. header=0x%x\n",size,(unsigned int)header); halt(); } if (header & FLAG_FREE) { if (len <= size) { void *nptr = ptr + (HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, * then mark it as such otherwise account * the whole space for that block. */ if (nsize > 0) { /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(len); /* Create a new free block. */ *((hdrtype_t *) nptr) = FREE_BLOCK(nsize); } else { /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(size); } return (void *)(ptr + HDRSIZE); } } ptr += HDRSIZE + size; } while (ptr < hend); /* Nothing available. */ return (void *)NULL; } result log: Running option rom at ce00:0003 hello, initialize_usb 00:13.0 4387:1002.0 OHCI controller Not supported. 00:13.1 4388:1002.1 OHCI controller Not supported. 00:13.2 4389:1002.2 OHCI controller Not supported. 00:13.3 438a:1002.3 OHCI controller Not supported. 00:13.4 438b:1002.4 OHCI controller Not supported. 00:13.5 4386:1002.5 EHCI controller Not supported. 00:05.0 3038:1106.0 UHCI controller alloc 82 length:0x238,ptr=0x3077e0 alloc 83 memory begin:0x77e0 end:0x577e0, hstart:0x300000 set up error,*ptr=0xa2c0e2cc memory allocator panic!!! the size=0xc0e2cc. header=0xa2c0e2cc On Sun, Aug 2, 2009 at 4:27 AM, Jason Wang wrote: > > Hi all, > I added some printf message into malloc.c, and find that the function > setup() which used to init the memory seems not executed very well. > I put my own malloc.c and the log attached to this mail. Hope some one can > help me to find out the problems. > > static void setup(void) > { > int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; > > *((hdrtype_t *) hstart) = FREE_BLOCK(size); > printf("%s the memory size:0x%x,begin:0x%x end:0x%x, > hstart:0x%x\n",__func__,size,(unsigned int)&_heap,(unsigned > int)&_eheap,(unsigned int )*((hdrtype_t *) hstart)); > > > } > > static void *alloc(int len) > { > hdrtype_t header; > void *ptr = hstart; > printf("%s length=0x%x, the ptr=0x%x\n",__func__,len,(unsigned int > )*((hdrtype_t*)ptr)); > printf("%s the memory begin:0x%x end:0x%x, > hstart:0x%x\n",__func__,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned > int )*((hdrtype_t *) hstart)); > /* Align the size. */ > len = (len + 3) & ~3; > > if (!len || len > 0xffffff) > return (void *)NULL; > > /* Make sure the region is setup correctly. */ > if (!HAS_MAGIC(*((hdrtype_t *) ptr))) > setup(); > if (!HAS_MAGIC(*((hdrtype_t *) ptr))){ > printf("set up failed,ptr=0x%x\n",(unsigned int)*((hdrtype_t *) > ptr)); > } > /* Find some free space. */ > do { > header = *((hdrtype_t *) ptr); > int size = SIZE(header); > > if (!HAS_MAGIC(header) || size == 0) { > printf("memory allocator panic!!! the size=0x%x. > header=0x%x\n",size,(unsigned int)header); > halt(); > } > > if (header & FLAG_FREE) { > if (len <= size) { > void *nptr = ptr + (HDRSIZE + len); > int nsize = size - (HDRSIZE + len); > > /* If there is still room in this block, > * then mark it as such otherwise account > * the whole space for that block. > */ > > if (nsize > 0) { > /* Mark the block as used. */ > *((hdrtype_t *) ptr) = USED_BLOCK(len); > > /* Create a new free block. */ > *((hdrtype_t *) nptr) = > FREE_BLOCK(nsize); > } else { > /* Mark the block as used. */ > *((hdrtype_t *) ptr) = USED_BLOCK(size); > } > > return (void *)(ptr + HDRSIZE); > } > } > > ptr += HDRSIZE + size; > > } while (ptr < hend); > > /* Nothing available. */ > return (void *)NULL; > } > log: > Attempting to init PCI bdf 06:05.0 (dev/ven 30381106) > Copying option rom (size 130560) from 0xfff00000 to ce000 > Checking rom 0x000ce000 (sig aa55 size 255) > Running option rom at ce00:0003 > hello, initialize_usb > 00:13.0 4387:1002.0 OHCI controller > Not supported. > 00:13.1 4388:1002.1 OHCI controller > Not supported. > 00:13.2 4389:1002.2 OHCI controller > Not supported. > 00:13.3 438a:1002.3 OHCI controller > Not supported. > 00:13.4 438b:1002.4 OHCI controller > Not supported. > 00:13.5 4386:1002.5 EHCI controller > Not supported. > 00:05.0 3038:1106.0 UHCI controller > alloc length=0x238, the ptr=0x0 > alloc the memory begin:0x7860 end:0x57860, hstart:0x0 > setup the memory size:0x4fffc,begin:0x7860 end:0x57860, hstart:0xaa04fffc > set up failed,ptr=0x0 > memory allocator panic!!! the size=0x0. header=0x0 > > -- > Jason Wang > Peking University > -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: From rminnich at gmail.com Sun Aug 2 17:39:49 2009 From: rminnich at gmail.com (ron minnich) Date: Sun, 2 Aug 2009 08:39:49 -0700 Subject: [coreboot] [GSoC] Re: malloc.c problems of option rom In-Reply-To: References: Message-ID: <13426df10908020839q3204e6cau94017648e335485a@mail.gmail.com> On Sun, Aug 2, 2009 at 6:37 AM, Jason Wang wrote: > updated the new, which changed the display value > static void setup(void) > { > ??? int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; > ??? *((hdrtype_t *) hstart) = FREE_BLOCK(size); > //??? printf("%s memory size:0x%x,begin:0x%x end:0x%x, > hstart:0x%x\n",__func__,size,(unsigned int)&_heap,(unsigned > int)&_eheap,(unsigned int )*((hdrtype_t *) hstart)); > > > } > > static void *alloc(int len) > { > ??? hdrtype_t header; > ??? void *ptr = hstart; > ??? printf("%s %d? length:0x%x,ptr=0x%x \n",__func__,__LINE__,len,(unsigned > int )ptr); > ??? printf("%s %d memory begin:0x%x end:0x%x, > hstart:0x%x\n",__func__,__LINE__,(unsigned int)&_heap,(unsigned > int)&_eheap,(unsigned int ) hstart); > ??? /* Align the size. */ > ??? len = (len + 3) & ~3; > > ??? if (!len || len > 0xffffff) > ??? ??? return (void *)NULL; > //??? while(1); > > ??? /* Make sure the region is setup correctly. */ > ??? if (!HAS_MAGIC(*((hdrtype_t *) ptr))){ > ??? ??? setup(); > ??? } > ??? if (!HAS_MAGIC(*((hdrtype_t *) ptr))){ > ??? printf("set up error,*ptr=0x%x\n",(unsigned int)*((hdrtype_t *) ptr)); > ??? } > > ??? /* Find some free space. */ > ??? do { > ??? ??? header = *((hdrtype_t *) ptr); > ??? ??? int size = SIZE(header); > > ??? ??? if (!HAS_MAGIC(header) || size == 0) { > ??? ??? ??? printf("memory allocator panic!!! the size=0x%x. > header=0x%x\n",size,(unsigned int)header); > ??? ??? ??? halt(); > ??? ??? } > > ??? ??? if (header & FLAG_FREE) { > ??? ??? ??? if (len <= size) { > ??? ??? ??? ??? void *nptr = ptr + (HDRSIZE + len); > ??? ??? ??? ??? int nsize = size - (HDRSIZE + len); > > ??? ??? ??? ??? /* If there is still room in this block, > ??? ??? ??? ??? ?* then mark it as such otherwise account > ??? ??? ??? ??? ?* the whole space for that block. > ??? ??? ??? ??? ?*/ > > ??? ??? ??? ??? if (nsize > 0) { > ??? ??? ??? ??? ??? /* Mark the block as used. */ > ??? ??? ??? ??? ??? *((hdrtype_t *) ptr) = USED_BLOCK(len); > > ??? ??? ??? ??? ??? /* Create a new free block. */ > ??? ??? ??? ??? ??? *((hdrtype_t *) nptr) = > ??? ??? ??? ??? ??? ??? FREE_BLOCK(nsize); > ??? ??? ??? ??? } else { > ??? ??? ??? ??? ??? /* Mark the block as used. */ > ??? ??? ??? ??? ??? *((hdrtype_t *) ptr) = USED_BLOCK(size); > ??? ??? ??? ??? } > > ??? ??? ??? ??? return (void *)(ptr + HDRSIZE); > ??? ??? ??? } > ??? ??? } > > ??? ??? ptr += HDRSIZE + size; > > ??? } while (ptr < hend); > > ??? /* Nothing available. */ > ??? return (void *)NULL; > } > result log: > Running option rom at ce00:0003 > hello, initialize_usb > 00:13.0 4387:1002.0 OHCI controller > Not supported. > 00:13.1 4388:1002.1 OHCI controller > Not supported. > 00:13.2 4389:1002.2 OHCI controller > Not supported. > 00:13.3 438a:1002.3 OHCI controller > Not supported. > 00:13.4 438b:1002.4 OHCI controller > Not supported. > 00:13.5 4386:1002.5 EHCI controller > Not supported. > 00:05.0 3038:1106.0 UHCI controller > alloc 82? length:0x238,ptr=0x3077e0 > alloc 83 memory begin:0x77e0 end:0x577e0, hstart:0x300000 > set up error,*ptr=0xa2c0e2cc > memory allocator panic!!! the size=0xc0e2cc. header=0xa2c0e2cc You're trying to allocate 1.25 Mbytes of memory? Why is that? ron From peter at stuge.se Sun Aug 2 19:42:40 2009 From: peter at stuge.se (Peter Stuge) Date: Sun, 2 Aug 2009 19:42:40 +0200 Subject: [coreboot] [GSoC] Re: malloc.c problems of option rom In-Reply-To: <13426df10908020839q3204e6cau94017648e335485a@mail.gmail.com> References: <13426df10908020839q3204e6cau94017648e335485a@mail.gmail.com> Message-ID: <20090802174240.17590.qmail@stuge.se> ron minnich wrote: > > alloc 82? length:0x238,ptr=0x3077e0 > > alloc 83 memory begin:0x77e0 end:0x577e0, hstart:0x300000 > > set up error,*ptr=0xa2c0e2cc > > memory allocator panic!!! the size=0xc0e2cc. header=0xa2c0e2cc > > You're trying to allocate 1.25 Mbytes of memory? I think that's some kind of corruption. 0x238 is the original allocation length. We looked into this a little on IRC and the two values ptr and hstart (lines 82/83 above) should be the same. There's an assignment ptr=hstart right before the prints in the source Jason sent. It's possible that some source changes may have been left out in the running build - I don't know exactly what's going on. I suggested reverting back to a version of the memory allocator which has a known behavior, even if it is known to fail I think it will be easier to debug and fix than this problem. //Peter From baboo at inbox.com Sun Aug 2 19:54:14 2009 From: baboo at inbox.com (gordon daniels) Date: Sun, 2 Aug 2009 09:54:14 -0800 Subject: [coreboot] support for quanta Message-ID: <16E53B69154.0000027Ebaboo@inbox.com> An HTML attachment was scrubbed... URL: From stepan at coresystems.de Mon Aug 3 02:19:36 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Mon, 03 Aug 2009 02:19:36 +0200 Subject: [coreboot] [GSoC] Re: malloc.c problems of option rom In-Reply-To: <20090802174240.17590.qmail@stuge.se> References: <13426df10908020839q3204e6cau94017648e335485a@mail.gmail.com> <20090802174240.17590.qmail@stuge.se> Message-ID: <4A762D18.1030702@coresystems.de> Peter Stuge wrote: > ron minnich wrote: > >>> alloc 82 length:0x238,ptr=0x3077e0 >>> alloc 83 memory begin:0x77e0 end:0x577e0, hstart:0x300000 >>> set up error,*ptr=0xa2c0e2cc >>> memory allocator panic!!! the size=0xc0e2cc. header=0xa2c0e2cc >>> >> You're trying to allocate 1.25 Mbytes of memory? >> > > I think that's some kind of corruption. > > 0x238 is the original allocation length. We looked into this a little > on IRC and the two values ptr and hstart (lines 82/83 above) should > be the same. There's an assignment ptr=hstart right before the prints > in the source Jason sent. It's possible that some source changes may > have been left out in the running build - I don't know exactly what's > going on. > > I suggested reverting back to a version of the memory allocator which > has a known behavior, even if it is known to fail I think it will be > easier to debug and fix than this problem. > The latest upstream version is working fine with FILO here. It might be worth trying to start with FILO and reduce stack and heap until it's possible to reproduce the problems... Problems with parameter passing sounds a lot like stack corruption. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From arnaud.maye at 4dsp.com Mon Aug 3 11:44:14 2009 From: arnaud.maye at 4dsp.com (Arnaud Maye) Date: Mon, 03 Aug 2009 11:44:14 +0200 Subject: [coreboot] vga not working In-Reply-To: <20090802085755.GA10680@morn.localdomain> References: <20090726134838.GA30132@morn.localdomain> <4A6D5B8C.1090806@4dsp.com> <4A6ED806.3080401@4dsp.com> <20090729005752.GA11700@morn.localdomain> <4A7008FF.4000306@4dsp.com> <2831fecf0907300856x69d67d80maf569e43b526b1bd@mail.gmail.com> <20090802085755.GA10680@morn.localdomain> Message-ID: <4A76B16E.6030807@4dsp.com> Hello Gents, Thank you for your pointers. I will not be able to work on the BIOS until late August. We have a few other things in //. I will investigate around this and keep you updated as soon am back to this project :) Thank you Arnaud Kevin O'Connor wrote: > On Thu, Jul 30, 2009 at 09:56:20AM -0600, Myles Watson wrote: > >> On Wed, Jul 29, 2009 at 2:31 AM, Arnaud Maye wrote: >> >>> We are talking about the GFX cards legacy ranges, right? I think >>> Myles looked at the PCI allocation already it seems everything is >>> fine there. >>> >> Actually I said that it wouldn't be related to the allocator because the >> legacy VGA ranges are not aren't allocated there. This is the place to >> start to look for that: >> > [...] > >> 1. Make sure that that's the path to your graphics card. >> 2. Make sure that the correct bits get set in each device so that the I/O to >> the graphics card gets there. >> - The PCI_BRIDGE_CTL_VGA bit is in the device structure, so it doesn't >> affect hardware >> - Many bridges need some bit set to decode those ranges >> > > In addition to making sure the legacy IO ranges are correct, you also > need to verify the legacy vga memory range (0xa0000 - 0xc0000) is > properly configured in the bridges. Also, the chipset needs to have > this range be a pci hole - it must not have memory mapped there. > > -Kevin > > * * From rminnich at gmail.com Tue Aug 4 06:47:43 2009 From: rminnich at gmail.com (ron minnich) Date: Mon, 3 Aug 2009 21:47:43 -0700 Subject: [coreboot] seabios and serengeti cheetah Message-ID: <13426df10908032147t1962e32ek307bb74e0f55e3d2@mail.gmail.com> anybody tried to boot an iso on secondary master on serengeti? I get this error 0003 when it fails. one thing that seabios could do when everything has failed and we've given up is drop is into a menu or even the chance to change something and try again, without a reset cycle. Just a thought. Only matters on simulators I guess. ron From peter at stuge.se Tue Aug 4 12:49:46 2009 From: peter at stuge.se (Peter Stuge) Date: Tue, 4 Aug 2009 12:49:46 +0200 Subject: [coreboot] seabios and serengeti cheetah In-Reply-To: <13426df10908032147t1962e32ek307bb74e0f55e3d2@mail.gmail.com> References: <13426df10908032147t1962e32ek307bb74e0f55e3d2@mail.gmail.com> Message-ID: <20090804104947.3288.qmail@stuge.se> ron minnich wrote: > anybody tried to boot an iso on secondary master on serengeti? I > get this error 0003 when it fails. Can you choose the drive if you press F12? //Peter From rminnich at gmail.com Tue Aug 4 16:44:38 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 4 Aug 2009 07:44:38 -0700 Subject: [coreboot] seabios and serengeti cheetah In-Reply-To: <20090804104947.3288.qmail@stuge.se> References: <13426df10908032147t1962e32ek307bb74e0f55e3d2@mail.gmail.com> <20090804104947.3288.qmail@stuge.se> Message-ID: <13426df10908040744n25dff5b9x6c6d6d50e0753a15@mail.gmail.com> On Tue, Aug 4, 2009 at 3:49 AM, Peter Stuge wrote: > ron minnich wrote: >> anybody tried to boot an iso on secondary master on serengeti? I >> get this error 0003 when it fails. > > Can you choose the drive if you press F12? yes, it finds the drive. It just can not read it for some reason. ron From daliu87 at gmail.com Tue Aug 4 21:34:43 2009 From: daliu87 at gmail.com (Daniel Liu) Date: Tue, 4 Aug 2009 12:34:43 -0700 Subject: [coreboot] SerialICE 1.0 - QEMU stops responding Message-ID: Hey, I've been trying to use SerialICE to trace through some BIOS code, but periodically QEMU stops responding. The SerialICE rom loaded onto the target motherboard's bios chip still responds to serial commands. It's not a specific instruction that causes it to stop, it seems to stop at random points when running normally and when debugging with GDB. Does anyone know why this might be happening? I setup SerialICE following the README instructions for QEMU 0.10.4. My host system with QEMU is running Debian Linux 2.6.30-1-amd64. My target board is an ASUS P5Q-EM DO based on the Q45 Chipset with an ICH10. I'm using the intel_d945gclf.c mainboard configuration (which works fine with the newer chipset). Thanks, Daniel Liu -------------- next part -------------- An HTML attachment was scrubbed... URL: From kevin at koconnor.net Wed Aug 5 00:35:53 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Tue, 4 Aug 2009 18:35:53 -0400 Subject: [coreboot] seabios and serengeti cheetah In-Reply-To: <13426df10908032147t1962e32ek307bb74e0f55e3d2@mail.gmail.com> References: <13426df10908032147t1962e32ek307bb74e0f55e3d2@mail.gmail.com> Message-ID: <20090804223553.GA22186@morn.localdomain> On Mon, Aug 03, 2009 at 09:47:43PM -0700, ron minnich wrote: > anybody tried to boot an iso on secondary master on serengeti? I get > this error 0003 when it fails. Hi Ron, Can you post the log? I know simnow had a weird error with its emulation of cdroms - though I think I read that it was fixed in a later version. > one thing that seabios could do when everything has failed and we've > given up is drop is into a menu or even the chance to change something > and try again, without a reset cycle. Just a thought. Only matters on > simulators I guess. You should be able to press ctrl+alt+delete to just restart seabios. It's also possible to add a "recovery" payload to the flash, and then make it the last thing seabios tries to boot. -Kevin From stepan at coresystems.de Wed Aug 5 08:07:37 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 5 Aug 2009 08:07:37 +0200 Subject: [coreboot] SerialICE 1.0 - QEMU stops responding In-Reply-To: References: Message-ID: <45578DFD-26E2-4A00-95D9-A0EE6B777C97@coresystems.de> Hi Daniel, On 04.08.2009, at 21:34, Daniel Liu wrote: > I've been trying to use SerialICE to trace through some BIOS code, > but periodically QEMU stops responding. The SerialICE rom loaded > onto the target motherboard's bios chip still responds to serial > commands. It's not a specific instruction that causes it to stop, > it seems to stop at random points when running normally and when > debugging with GDB. Does anyone know why this might be happening? This is very odd.. The communication code in qemu's serialice.c is a bit fragile due to working around some qemu peculiarities. I have not seen this before, however it sounds a lot like qemu is waiting for data that SerialICE does not attempt to send, or that got lost.. There are a number of debugging statements in Qemu's serialice.c - maybe enabling them can shed some light on this... Stefan From svn at coreboot.org Wed Aug 5 12:48:43 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 5 Aug 2009 12:48:43 +0200 Subject: [coreboot] [v2] r4494 - in trunk/coreboot-v2/src: arch/i386/init mainboard/digitallogic/msm586seg mainboard/technologic/ts5300 Message-ID: Author: oxygene Date: 2009-08-05 12:48:43 +0200 (Wed, 05 Aug 2009) New Revision: 4494 Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c Log: Fix the generic code for copying and running coreboot_ram in case certain configuration options are disabled. The strings were just at the wrong place. Two boards fix up some variables for romstream. This isn't necessary (or possible) when CBFS is active, as there is no romstream. It would be nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any invariant that forces that to be inactive if CBFS is active, and this patch is supposed to be small, esp. as the stream loaders are on the way out. Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2009-08-05 09:20:02 UTC (rev 4493) +++ trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2009-08-05 10:48:43 UTC (rev 4494) @@ -70,6 +70,7 @@ * Normally this is copying from FLASH ROM to RAM. */ movl %ebp, %esi + /* FIXME: look for a proper place for the stack */ movl $0x4000000, %esp movl %esp, %ebp pushl %esi @@ -142,6 +143,11 @@ #else str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" #endif +str_pre_main: .string "Jumping to coreboot.\r\n" +.previous + +#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ + #if CONFIG_CBFS == 1 # if CONFIG_USE_FALLBACK_IMAGE == 1 str_coreboot_ram_name: .string "fallback/coreboot_ram" @@ -149,9 +155,5 @@ str_coreboot_ram_name: .string "normal/coreboot_ram" # endif #endif -str_pre_main: .string "Jumping to coreboot.\r\n" -.previous -#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ - #endif /* CONFIG_USE_DCACHE_RAM */ Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c 2009-08-05 09:20:02 UTC (rev 4493) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c 2009-08-05 10:48:43 UTC (rev 4494) @@ -35,7 +35,9 @@ - set ADDDECTL (now done in raminit.c in cpu/amd/sc520 */ static void enable_dev(struct device *dev) { +#if !CONFIG_CBFS extern unsigned char *rom_start, *rom_end; +#endif volatile struct mmcrpic *pic = MMCRPIC; volatile struct mmcr *mmcr = MMCRDEFAULT; @@ -134,10 +136,12 @@ /* follow fuctory here */ mmcr->dmacontrol.extchanmapa = 0x3210; +#if !CONFIG_CBFS /* hack for IDIOTIC need to fix rom_start */ printk_err("Patching rom_start due to sc520 limits\n"); rom_start = 0x2000000 + 0x40000; rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; +#endif } Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c 2009-08-05 09:20:02 UTC (rev 4493) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c 2009-08-05 10:48:43 UTC (rev 4494) @@ -35,7 +35,9 @@ - set ADDDECTL (now done in raminit.c in cpu/amd/sc520 */ static void enable_dev(struct device *dev) { +#if !CONFIG_CBFS extern unsigned char *rom_start, *rom_end; +#endif volatile struct mmcrpic *pic = MMCRPIC; volatile struct mmcr *mmcr = MMCRDEFAULT; @@ -139,10 +141,12 @@ mmcr->dmacontrol.extchanmapa = 0xf210; mmcr->dmacontrol.extchanmapb = 0xffff; +#if !CONFIG_CBFS /* hack for IDIOTIC need to fix rom_start */ printk_err("Patching rom_start due to sc520 limits\n"); rom_start = 0x09400000 + 0xe0000; rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; +#endif printk_err("TS5300 EXIT %s\n", __func__); From patrick at georgi-clan.de Wed Aug 5 12:52:42 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 Aug 2009 12:52:42 +0200 Subject: [coreboot] [PATCH]es: enable CBFS for all boards In-Reply-To: <4A747710.8010602@georgi-clan.de> References: <4A747710.8010602@georgi-clan.de> Message-ID: <4A79647A.2030905@georgi-clan.de> These patches are in r4494. They have no impact except fixing compile errors in certain corner cases, so they're in. 20090801-2-fix-cpp-scope-of-strings This patch fixes the generic code for copying and running coreboot_ram in case certain configuration options are disabled. the strings were just at the wrong place. 20090801-3-only-fix-romstream-stuff-if-romstream-is-possible Two boards fix up some variables for romstream. This isn't necessary (or possible) when CBFS is active, as there is no romstream. It would be nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any invariant that forces that to be inactive if CBFS is active, and this patch is supposed to be small, esp. as the stream loaders are on the way out. These patches are still in my queue. The first might break cpu/amd/model_lx boards, and I didn't get any feedback on it, the other one converts the entire tree to CBFS - so it has a big impact. Thus I'll have them wait in my queue for a bit until kconfig is in, so people can work with/on kconfig without having to care about issues that might come from these patches. > 20090801-1-model_lx-should-use-generic-copy-and-run > cpu/amd/model_lx uses its own routine for copying coreboot_ram, I tried > to make it use the generic infrastructure, but I can't test it due to > lack of hardware. > > > 20090801-4-enable-cbfs-for-all-boards > Big patch touching nearly every board, to enable CBFS. Everything built, > but that's all testing I could do, as the boards I have available > already have CBFS activated Patrick From patrick at georgi-clan.de Wed Aug 5 13:04:45 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 Aug 2009 13:04:45 +0200 Subject: [coreboot] [PATCH]es: Various changes from the kconfig branch Message-ID: <4A79674D.7050306@georgi-clan.de> Hi, as preparation for the kconfig merge, here are some changes from the kconfig tree that are unrelated to kconfig itself. 20090805-1-ttys0-rename Takes care of the different CONFIG_* names of the variable containing the serial I/O port 20090805-2-config-prefixes Some more CONFIG_* prefixes that were missing 20090805-3-empty-files These changes exist mostly to make diff happy, which ignores empty files (or rather: Make Patrick happy when he's using diff). Maybe the right way would be to delete those files. Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090805-1-ttys0-rename URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090805-2-config-prefixes URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090805-3-empty-files URL: From patrick at georgi-clan.de Wed Aug 5 13:59:40 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 Aug 2009 13:59:40 +0200 Subject: [coreboot] [PATCH]Rename COREBOOT_V2 to CONFIG_COREBOOT_V2 Message-ID: <4A79742C.5000003@georgi-clan.de> Hi, another patch to prepare for kconfig. This one renames COREBOOT_V2 to CONFIG_COREBOOT_V2 and adapts its user (x86emu) to match. Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090805-4-config_coreboot_v2 URL: From c-d.hailfinger.devel.2006 at gmx.net Wed Aug 5 14:11:46 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 05 Aug 2009 14:11:46 +0200 Subject: [coreboot] [PATCH]Rename COREBOOT_V2 to CONFIG_COREBOOT_V2 In-Reply-To: <4A79742C.5000003@georgi-clan.de> References: <4A79742C.5000003@georgi-clan.de> Message-ID: <4A797702.2020704@gmx.net> On 05.08.2009 13:59, Patrick Georgi wrote: > another patch to prepare for kconfig. This one renames COREBOOT_V2 to > CONFIG_COREBOOT_V2 and adapts its user (x86emu) to match. > > Signed-off-by: Patrick Georgi > Acked-by: Carl-Daniel Hailfinger -- http://www.hailfinger.org/ From svn at coreboot.org Wed Aug 5 14:15:46 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 5 Aug 2009 14:15:46 +0200 Subject: [coreboot] [v3] r1175 - in coreboot-v3/util/x86emu: . pcbios x86emu yabel yabel/compat Message-ID: Author: oxygene Date: 2009-08-05 14:15:46 +0200 (Wed, 05 Aug 2009) New Revision: 1175 Modified: coreboot-v3/util/x86emu/biosemu.c coreboot-v3/util/x86emu/pcbios/pcibios.c coreboot-v3/util/x86emu/x86.c coreboot-v3/util/x86emu/x86_interrupts.c coreboot-v3/util/x86emu/x86emu/sys.c coreboot-v3/util/x86emu/yabel/biosemu.c coreboot-v3/util/x86emu/yabel/compat/functions.c coreboot-v3/util/x86emu/yabel/debug.c coreboot-v3/util/x86emu/yabel/debug.h coreboot-v3/util/x86emu/yabel/device.c coreboot-v3/util/x86emu/yabel/device.h coreboot-v3/util/x86emu/yabel/interrupt.c coreboot-v3/util/x86emu/yabel/io.c coreboot-v3/util/x86emu/yabel/mem.c coreboot-v3/util/x86emu/yabel/pmm.c coreboot-v3/util/x86emu/yabel/vbe.c Log: Prepare for kconfig: Rename COREBOOT_V2 to CONFIG_COREBOOT_V2 and adapt its user (x86emu) to match. Signed-off-by: Patrick Georgi Acked-by: Carl-Daniel Hailfinger Modified: coreboot-v3/util/x86emu/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/biosemu.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/biosemu.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -36,7 +36,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include #include #else Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c =================================================================== --- coreboot-v3/util/x86emu/pcbios/pcibios.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/pcbios/pcibios.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -35,7 +35,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include #else #include @@ -65,7 +65,7 @@ break; case FIND_PCI_DEVICE: /* FixME: support SI != 0 */ -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 dev = dev_find_device(X86_DX, X86_CX, dev); #else dev = dev_find_pci_device(X86_DX, X86_CX, dev); Modified: coreboot-v3/util/x86emu/x86.c =================================================================== --- coreboot-v3/util/x86emu/x86.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/x86.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -20,7 +20,7 @@ #include #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include #include #define printk(x...) do_printk(x) Modified: coreboot-v3/util/x86emu/x86_interrupts.c =================================================================== --- coreboot-v3/util/x86emu/x86_interrupts.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/x86_interrupts.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -23,7 +23,7 @@ #include #include #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include #include #define printk(x...) do_printk(x) @@ -87,7 +87,7 @@ vendorid = regs->edx; devindex = regs->esi; dev = 0; -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 while ((dev = dev_find_device(vendorid, devid, dev))) { #else while ((dev = dev_find_pci_device(vendorid, devid, dev))) { Modified: coreboot-v3/util/x86emu/x86emu/sys.c =================================================================== --- coreboot-v3/util/x86emu/x86emu/sys.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/x86emu/sys.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -46,7 +46,7 @@ #include "debug.h" #include "prim_ops.h" #if 1 /* Coreboot needs to map prinkf to printk. */ -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "arch/io.h" #else #include "io.h" Modified: coreboot-v3/util/x86emu/yabel/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/yabel/biosemu.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/biosemu.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -14,7 +14,7 @@ #include #include -#ifndef COREBOOT_V2 +#ifndef CONFIG_COREBOOT_V2 #include #endif @@ -22,7 +22,7 @@ #include #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include // for push_word @@ -35,7 +35,7 @@ #include "device.h" #include "pmm.h" -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "compat/rtas.h" #else #include Modified: coreboot-v3/util/x86emu/yabel/compat/functions.c =================================================================== --- coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -14,7 +14,7 @@ */ #include -#ifndef COREBOOT_V2 +#ifndef CONFIG_COREBOOT_V2 #include #endif #include Modified: coreboot-v3/util/x86emu/yabel/debug.c =================================================================== --- coreboot-v3/util/x86emu/yabel/debug.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/debug.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -11,7 +11,7 @@ * IBM Corporation - initial implementation *****************************************************************************/ -#ifndef COREBOOT_V2 +#ifndef CONFIG_COREBOOT_V2 #include #endif Modified: coreboot-v3/util/x86emu/yabel/debug.h =================================================================== --- coreboot-v3/util/x86emu/yabel/debug.h 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/debug.h 2009-08-05 12:15:46 UTC (rev 1175) @@ -20,7 +20,7 @@ extern void x86emu_dump_xregs(void); /* printf is not available in coreboot... use printk */ -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include #else #include Modified: coreboot-v3/util/x86emu/yabel/device.c =================================================================== --- coreboot-v3/util/x86emu/yabel/device.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/device.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -13,7 +13,7 @@ #include "device.h" -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "compat/rtas.h" #else #include "rtas.h" @@ -397,7 +397,7 @@ { u8 rval = 0; //init bios_device struct -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 DEBUG_PRINTF("%s\n", __func__); #else DEBUG_PRINTF("%s(%s)\n", __func__, device->dtsname); Modified: coreboot-v3/util/x86emu/yabel/device.h =================================================================== --- coreboot-v3/util/x86emu/yabel/device.h 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/device.h 2009-08-05 12:15:46 UTC (rev 1175) @@ -15,7 +15,7 @@ #define DEVICE_LIB_H #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include #include "compat/of.h" #else Modified: coreboot-v3/util/x86emu/yabel/interrupt.c =================================================================== --- coreboot-v3/util/x86emu/yabel/interrupt.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/interrupt.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -11,7 +11,7 @@ * IBM Corporation - initial implementation *****************************************************************************/ -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "compat/rtas.h" #else #include @@ -24,7 +24,7 @@ #include "pmm.h" #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include @@ -350,7 +350,7 @@ __func__, M.x86.R_AX); /* FixME: support SI != 0 */ #if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); #else dev = dev_find_pci_device(M.x86.R_DX, M.x86.R_CX, 0); Modified: coreboot-v3/util/x86emu/yabel/io.c =================================================================== --- coreboot-v3/util/x86emu/yabel/io.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/io.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -12,7 +12,7 @@ *****************************************************************************/ #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "compat/rtas.h" #include "compat/time.h" #else Modified: coreboot-v3/util/x86emu/yabel/mem.c =================================================================== --- coreboot-v3/util/x86emu/yabel/mem.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/mem.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -12,14 +12,14 @@ *****************************************************************************/ #include -#ifndef COREBOOT_V2 +#ifndef CONFIG_COREBOOT_V2 #include #endif #include "debug.h" #include "device.h" #include "x86emu/x86emu.h" #include "biosemu.h" -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "compat/time.h" #else #include Modified: coreboot-v3/util/x86emu/yabel/pmm.c =================================================================== --- coreboot-v3/util/x86emu/yabel/pmm.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/pmm.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -10,7 +10,7 @@ ****************************************************************************/ #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include Modified: coreboot-v3/util/x86emu/yabel/vbe.c =================================================================== --- coreboot-v3/util/x86emu/yabel/vbe.c 2009-07-19 00:21:19 UTC (rev 1174) +++ coreboot-v3/util/x86emu/yabel/vbe.c 2009-08-05 12:15:46 UTC (rev 1175) @@ -13,7 +13,7 @@ #include #include -#ifndef COREBOOT_V2 +#ifndef CONFIG_COREBOOT_V2 #include #endif @@ -21,7 +21,7 @@ #include #include -#ifdef COREBOOT_V2 +#ifdef CONFIG_COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include // for push_word From svn at coreboot.org Wed Aug 5 14:16:02 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 5 Aug 2009 14:16:02 +0200 Subject: [coreboot] [v2] r4496 - trunk/coreboot-v2/src/config Message-ID: Author: oxygene Date: 2009-08-05 14:16:01 +0200 (Wed, 05 Aug 2009) New Revision: 4496 Modified: trunk/coreboot-v2/src/config/Options.lb Log: Prepare for kconfig: Rename COREBOOT_V2 to CONFIG_COREBOOT_V2 and adapt its user (x86emu) to match. Signed-off-by: Patrick Georgi Acked-by: Carl-Daniel Hailfinger Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-08-05 11:57:43 UTC (rev 4495) +++ trunk/coreboot-v2/src/config/Options.lb 2009-08-05 12:16:01 UTC (rev 4496) @@ -176,7 +176,7 @@ comment "Use stage 1 initialization code" end -define COREBOOT_V2 +define CONFIG_COREBOOT_V2 default 1 export always comment "This is used by code to determine v2 vs v3" From c-d.hailfinger.devel.2006 at gmx.net Wed Aug 5 14:18:29 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 05 Aug 2009 14:18:29 +0200 Subject: [coreboot] [PATCH]es: Various changes from the kconfig branch In-Reply-To: <4A79674D.7050306@georgi-clan.de> References: <4A79674D.7050306@georgi-clan.de> Message-ID: <4A797895.9030503@gmx.net> Hi Patrick, On 05.08.2009 13:04, Patrick Georgi wrote: > as preparation for the kconfig merge, here are some changes from the > kconfig tree that are unrelated to kconfig itself. > > 20090805-1-ttys0-rename > Takes care of the different CONFIG_* names of the variable containing > the serial I/O port > There should only be one config variable for this. Wouldn't a global search/replace be able to standardize on either CONFIG_TTYS0_BASE or CONFIG_SERIAL_IOBASE? > 20090805-2-config-prefixes > Some more CONFIG_* prefixes that were missing > I don't particularly like the CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL #define, but since that code already looks like this and you only added a prefix, it is Acked-by: Carl-Daniel Hailfinger > 20090805-3-empty-files > These changes exist mostly to make diff happy, which ignores empty files > (or rather: Make Patrick happy when he's using diff). Maybe the right > way would be to delete those files. > If deleting these files doesn't break abuild, please delete them. For the deletion, you can use my ack. > Signed-off-by: Patrick Georgi > Regards, Carl-Daniel -- http://www.hailfinger.org/ From patrick at georgi-clan.de Wed Aug 5 14:19:43 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 Aug 2009 14:19:43 +0200 Subject: [coreboot] [PATCH]Rename COREBOOT_V2 to CONFIG_COREBOOT_V2 In-Reply-To: <4A797702.2020704@gmx.net> References: <4A79742C.5000003@georgi-clan.de> <4A797702.2020704@gmx.net> Message-ID: <4A7978DF.7030100@georgi-clan.de> Carl-Daniel Hailfinger schrieb: > Acked-by: Carl-Daniel Hailfinger > Thanks, r1175 in the v3 repo for x86emu, r4496 in the v2 repo. From svn at coreboot.org Wed Aug 5 14:24:23 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 5 Aug 2009 14:24:23 +0200 Subject: [coreboot] [v2] r4497 - trunk/coreboot-v2/src/southbridge/intel/i82801gx Message-ID: Author: oxygene Date: 2009-08-05 14:24:23 +0200 (Wed, 05 Aug 2009) New Revision: 4497 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c Log: Add some more CONFIG_* prefixes that were missing. Signed-off-by: Patrick Georgi Acked-by: Carl-Daniel Hailfinger Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-08-05 12:16:01 UTC (rev 4496) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-08-05 12:24:23 UTC (rev 4497) @@ -273,7 +273,7 @@ /* Set up power management block and determine sleep mode */ pmbase = pci_read_config16(dev, 0x40) & 0xfffe; reg32 = inl(pmbase + 0x04); // PM1_CNT -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0; printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n", reg32, acpi_slp_type); Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h 2009-08-05 12:16:01 UTC (rev 4496) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h 2009-08-05 12:24:23 UTC (rev 4497) @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c 2009-08-05 12:16:01 UTC (rev 4496) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c 2009-08-05 12:24:23 UTC (rev 4497) @@ -300,7 +300,7 @@ * CMOS or even better from GNVS. Right now it's hard * coded at compile time. */ - u8 s5pwr = MAINBOARD_POWER_ON_AFTER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); From patrick at georgi-clan.de Wed Aug 5 14:25:19 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 Aug 2009 14:25:19 +0200 Subject: [coreboot] [PATCH]es: Various changes from the kconfig branch In-Reply-To: <4A797895.9030503@gmx.net> References: <4A79674D.7050306@georgi-clan.de> <4A797895.9030503@gmx.net> Message-ID: <4A797A2F.1080903@georgi-clan.de> Carl-Daniel Hailfinger schrieb: > Hi Patrick, > > On 05.08.2009 13:04, Patrick Georgi wrote: > >> as preparation for the kconfig merge, here are some changes from the >> kconfig tree that are unrelated to kconfig itself. >> >> 20090805-1-ttys0-rename >> Takes care of the different CONFIG_* names of the variable containing >> the serial I/O port >> >> > > There should only be one config variable for this. Wouldn't a global > search/replace be able to standardize on either CONFIG_TTYS0_BASE or > CONFIG_SERIAL_IOBASE? > I _think_ the CONFIG_SERIAL_IOBASE was introduced in the kconfig stuff to be more similar to v3. Once we decide on one or the other, I can replace the respective occurrences. I don't care much and would go for CONFIG_TTYS0_BASE as that is what exists in the codebase. I'll prepare a patch. >> 20090805-2-config-prefixes >> Some more CONFIG_* prefixes that were missing >> >> > > I don't particularly like the CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL > #define, but since that code already looks like this and you only added > a prefix, it is > Acked-by: Carl-Daniel Hailfinger > Maybe we can get rid of this eventually, but for now this gets in. One battle at a time. r4497 >> 20090805-3-empty-files >> These changes exist mostly to make diff happy, which ignores empty files >> (or rather: Make Patrick happy when he's using diff). Maybe the right >> way would be to delete those files. >> >> > > If deleting these files doesn't break abuild, please delete them. For > the deletion, you can use my ack. > It will require some more work, as these empty files are still included at some places I think. I'll keep this open for discussion. Thanks, Patrick From svn at coreboot.org Wed Aug 5 15:10:39 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 5 Aug 2009 15:10:39 +0200 Subject: [coreboot] [v2] r4499 - trunk/payloads/libpayload/libc Message-ID: Author: stepan Date: 2009-08-05 15:10:38 +0200 (Wed, 05 Aug 2009) New Revision: 4499 Modified: trunk/payloads/libpayload/libc/string.c Log: fix buggy comment in libpayload's strncat function Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/payloads/libpayload/libc/string.c =================================================================== --- trunk/payloads/libpayload/libc/string.c 2009-08-05 13:06:37 UTC (rev 4498) +++ trunk/payloads/libpayload/libc/string.c 2009-08-05 13:10:38 UTC (rev 4499) @@ -165,7 +165,7 @@ * * @param d The destination string. * @param s The source string. - * @param n The target string will have a length of n characters at most. + * @param n Not more than n characters from s will be appended to d. * @return A pointer to the destination string. */ char *strncat(char *d, const char *s, size_t n) From patrick.georgi at coresystems.de Wed Aug 5 17:21:27 2009 From: patrick.georgi at coresystems.de (Patrick Georgi) Date: Wed, 05 Aug 2009 17:21:27 +0200 Subject: [coreboot] [PATCH]Kconfig for v2 Message-ID: <4A79A377.7040403@coresystems.de> Hi, I think it's time to push the Kconfig branch to trunk. As the patch is ~1MB, I won't add it to the list, it is available from https://www.coresystems.de/~patrick/20090805-5-kconfig It's kconfig, a kbuild-style build system (quite similar, with a twist), sconfig (a new tool to compile the devicetree structures that were in the mainboard's Config.lb so far), and just enough Kconfig/Makefile stuff to make kontron/986lcd-m and emulation/qemu-x86 work. Everything else is stubbed or missing, and I expect that some of the future changes will require some bigger changes and data moved between the Kconfig files (in particular). The patch doesn't affect abuild, except for ignoring "Kconfig" files in the mainboard hierarchy (so it doesn't try to build "emulation/Kconfig"), so there is no loss in functionality in the tree. Kconfig has no support for non-CBFS boards, and that's on purpose: The old rom layout is deprecated, and maintaining both systems would have increased the effort. Overview of the new files: Makefile contains the common rules, and machinery to import the Makefile fragments from the tree. No more generated Makefiles (except inside gnu make) */Makefile.inc The various Makefile fragments */Kconfig Configuration files, compatible to Linux's util/kconfig The Kconfig utilities util/sconfig compiles devicetree.cb files into data structures suitable for compilation */devicetree.cb The devicetree that formerly resided in src/mainboard/*/*/Config.lb. Just without the build system crap util/xcompile support utility to find a suitable cross compiler and various GNU tools Regards, Patrick From wangqingpei at gmail.com Wed Aug 5 17:36:28 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Wed, 5 Aug 2009 23:36:28 +0800 Subject: [coreboot] filo compile errors Message-ID: hi all it seems there is a variable are not included in /include/grub/shard.h which would caused error with main/grub/completions.c UNIQUE_BUF undefined details are patched. Index: include/grub/shared.h =================================================================== --- include/grub/shared.h (revision 103) +++ include/grub/shared.h (working copy) @@ -55,6 +55,7 @@ #define COMPLETION_BUFLEN MAX_CMDLINE /* The buffer for the unique string. */ +extern char UNIQUE_BUF[]; #define UNIQUE_BUFLEN MAX_CMDLINE /* The buffer for the menu entries. */ -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: debug.patch Type: application/octet-stream Size: 386 bytes Desc: not available URL: From stepan at coresystems.de Wed Aug 5 17:46:35 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 05 Aug 2009 17:46:35 +0200 Subject: [coreboot] filo compile errors In-Reply-To: References: Message-ID: <4A79A95B.4040905@coresystems.de> Jason Wang wrote: > > hi all > it seems there is a variable are not included in > /include/grub/shard.h which would caused error with > main/grub/completions.c UNIQUE_BUF undefined > details are patched. > CONFIG_EXPERIMENTAL is broken and should not be used. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 250 bytes Desc: OpenPGP digital signature URL: From jacobs at itd.nrl.navy.mil Wed Aug 5 19:48:33 2009 From: jacobs at itd.nrl.navy.mil (Jeffrey C. Jacobs) Date: Wed, 05 Aug 2009 13:48:33 -0400 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <4A6EF23A.5090705@georgi-clan.de> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> Message-ID: <4A79C5F1.6050601@itd.nrl.navy.mil> Danke vielmals Patrick and many thanks to everyone else, So, I decided to take your advice about switching (back to) FILO using the latest version (svn 103) and latest libpayload (svn 4505) but am still having problems recognizing my First Partition on the Primary Master IDE device, namely hda1. Specifically, using the FILO build settings specified here: http://coreboot.pastebin.com/f4e644a72 I got the boot sequence found at: http://coreboot.pastebin.com/f5b707efb Now, in that sequence, at the very end, where I've highlighted, I get the 'boot:' prompt instead of it loading what's in my menu.lst file (whose path is highlighted in the first link under the FILO configuration options). Also, note in the configuration that I am trying to build FILO in GRUB mode and have specified a prompt of "filo-as-grub", not "boot", which you see in my boot sequence. In fact, when I first tried to built the latest FILO, I found it would not build because the build/config.h file was generated improperly. The file was missing the CONFIG_PROMPT definition, which I also hardcoded to "filo-as-grub". None the less, when I boot, I still get "boot". Anyway, since my menu.lst could not be loaded, I typed in the full boot command replete with kernel boot parameters, and as you can see I got a generic error stating that FILO could not find Device 0 (obviously meaning it could not find hda1). So, I'm not sure if this is a problem with FILO, but it seems much more likely I have some errant settings in Coreboot which is not allowing FILO to see my drives. Does anyone have any ideas? Thanks in advance, Jeffrey. Patrick Georgi wrote: > Jeffrey C. Jacobs schrieb: >> I would update my GRUB checkout but every time I try to, I get "svn: >> Server sent unexpected return value (502 Bad Gateway) in response to >> OPTIONS request for 'http://svn.savannah.gnu.org/svn/grub/trunk'" and >> even in verbose mode I can't figure that one out. But since we're >> talking GRUB 2 and a version within the last 3 months, I think it >> should be compatible with HIMEM. So why, when I try it with >> LinuxBIOS, GRUB is able to load, but when I do with CoreBoot, it fails >> to jump to the boot loader? > Given that there is absolutely no output by GRUB, that might as well be > another problem - but it might also be high tables support. > I don't know if they support it, as I don't monitor their efforts. > However, I don't think there are any developers left that work on both > codebases, so that feature in coreboot might have happened without them > noticing. As not all boards use high tables yet, they might have missed > the need to implement support for it. > > One option for now could be to disable HAVE_HIGH_TABLES in your coreboot > build. Eventually, this config flag will disappear, with high tables > activated in all of coreboot, so this would mostly be something to get > past that road bump _for now_. > > You could also try the current, maintained FILO tree. See > http://www.coreboot.org/FILO for information on how to fetch it. > > > Regards, > Patrick From patrick at georgi-clan.de Wed Aug 5 22:24:01 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 05 Aug 2009 22:24:01 +0200 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <4A79C5F1.6050601@itd.nrl.navy.mil> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> <4A79C5F1.6050601@itd.nrl.navy.mil> Message-ID: <4A79EA61.5020106@georgi-clan.de> Jeffrey C. Jacobs schrieb: > Danke vielmals Patrick and many thanks to everyone else, > > So, I decided to take your advice about switching (back to) FILO using > the latest version (svn 103) and latest libpayload (svn 4505) but am > still having problems recognizing my First Partition on the Primary > Master IDE device, namely hda1. Specifically, using the FILO build > settings specified here: http://coreboot.pastebin.com/f4e644a72 How did you change that configuration, simply by editing .config, or by going through the "make config" routine? Editing .config doesn't adapt the files in build/, so it should always be completed with a "make oldconfig" (and then look if it took your values or overwrote it with something else due to dependencies) To be extra careful, always run "make clean" after changing the configuration to force a full build. > Anyway, since my menu.lst could not be loaded, I typed in the full > boot command replete with kernel boot parameters, and as you can see I > got a generic error stating that FILO could not find Device 0 > (obviously meaning it could not find hda1). So, I'm not sure if this > is a problem with FILO, but it seems much more likely I have some > errant settings in Coreboot which is not allowing FILO to see my > drives. Does anyone have any ideas? The device numbering might be weird at times. It's reasonably stable once you found the right device name, but it can differ from what you see elsewhere, so try hdb, hdc, and hdd, too. Patrick From rminnich at gmail.com Wed Aug 5 23:32:04 2009 From: rminnich at gmail.com (ron minnich) Date: Wed, 5 Aug 2009 14:32:04 -0700 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <4A79C5F1.6050601@itd.nrl.navy.mil> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> <4A79C5F1.6050601@itd.nrl.navy.mil> Message-ID: <13426df10908051432t7edd9e90sb0c25381e8da79bb@mail.gmail.com> A simple question which I can not tell from your boot line. Is this disk partitioned? ron From r.marek at assembler.cz Wed Aug 5 23:32:15 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Wed, 05 Aug 2009 23:32:15 +0200 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <4A79C5F1.6050601@itd.nrl.navy.mil> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> <4A79C5F1.6050601@itd.nrl.navy.mil> Message-ID: <4A79FA5F.1070104@assembler.cz> Hi, Maybe it is a filesystem issue. I had some problems with ext3 volumes. Why don;t you try SeaBIOS payload instead and boot with classic grub? It would show if it is this or another issue. Rudolf From wangqingpei at gmail.com Thu Aug 6 00:40:18 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Thu, 6 Aug 2009 06:40:18 +0800 Subject: [coreboot] usb rom progress Message-ID: Hi all Since the usb rom can detect the USB devices, but i am bloced after the UHCI initialization, in set_address function it failed at can not communicate with the USB device. Is there any one who can help me about that? Or give me some advices about how to deal with this.... hello, initialize_usb 00:13.0 4387:1002.0 OHCI controller Not supported. 00:13.1 4388:1002.1 OHCI controller Not supported. 00:13.2 4389:1002.2 OHCI controller Not supported. 00:13.3 438a:1002.3 OHCI controller Not supported. 00:13.4 438b:1002.4 OHCI controller Not supported. 00:13.5 4386:1002.5 EHCI controller Not supported. 00:05.0 3038:1106.0 UHCI controller hstart:55b0,size:ffffc 00:05.1 3038:1106.1 UHCI controller fullspeed device control packet, req 500 SETUP packet (at 6ad00) to 0.0 failed td (counter at 3) returns: bitstuff err: 0, CRC err: 0, NAK rcvd: 0, Babble: 0, Data Buffer err : 0, Stalled: 0, Active: 1 still active - timeout? set_address failed fullspeed device control packet, req 500 SETUP packet (at 6ad00) to 0.0 failed td (counter at 3) returns: bitstuff err: 0, CRC err: 0, NAK rcvd: 0, Babble: 0, Data Buffer err : 0, Stalled: 0, Active: 1 still active - timeout? set_address failed fullspeed device control packet, req 500 SETUP packet (at 6ad00) to 0.0 failed td (counter at 3) returns: bitstuff err: 0, CRC err: 0, NAK rcvd: 0, Babble: 0, Data Buffer err : 0, Stalled: 0, Active: 1 still active - timeout? set_address failed fullspeed device -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: From daliu87 at gmail.com Thu Aug 6 01:03:15 2009 From: daliu87 at gmail.com (Daniel Liu) Date: Wed, 5 Aug 2009 16:03:15 -0700 Subject: [coreboot] SerialICE 1.0 - QEMU stops responding In-Reply-To: <45578DFD-26E2-4A00-95D9-A0EE6B777C97@coresystems.de> References: <45578DFD-26E2-4A00-95D9-A0EE6B777C97@coresystems.de> Message-ID: Hi Stefan, I think I found the issue.? In the function serialice.c:76 serialice_write(), if writing a character fails, the program will be stuck in the readback while loop: write(fd, buffer + i, 1); while (read(fd, &c, 1) != 1) ; I changed the write to keep trying until the write succeeds, which fixed the issue for now. static int serialice_write(int fd, const void *buf, size_t nbyte) { char *buffer = (char *) buf; char c; int i; for (i = 0; i < (int)nbyte; i++) { while (write(fd, buffer + i, 1) != 1) ; while (read(fd, &c, 1) != 1) ; if (c != buffer[i]) { printf("Readback error! %x/%x\n", c, buffer[i]); } } return nbyte; } -Daniel Liu From Zheng.Bao at amd.com Thu Aug 6 04:26:38 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Thu, 6 Aug 2009 10:26:38 +0800 Subject: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2 In-Reply-To: <20090720195806.GA23502@countzero.vandewege.net> References: <20090720195806.GA23502@countzero.vandewege.net> Message-ID: I am trying to port the ddr3 feature. I will submit a full patch to replace this one. Zheng -----Original Message----- From: Ward Vandewege [mailto:ward at gnu.org] Sent: Tuesday, July 21, 2009 3:58 AM To: Bao, Zheng Cc: Coreboot Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2 On Thu, Jul 16, 2009 at 03:40:49PM +0800, Bao, Zheng wrote: > This patch is about the DA-C2 and RB-C2. Chip with install processor > Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly > defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied > to > them are almost the same. > > Issues: > 1. I really dont know what their nicknames are (Shanghai C2 or > something). > 2. About the mc_patch_01000086.h, I dont know if it is allowed to be > released. > If you really need it, please contact AMD Inc to see if it is public. > 3. I haven't made coreboot go thoroughly on this RB-C2. This patch is > just half tested. > I am not confident it is 100% correct. > > Zheng > > > Signed-off-by: Zheng Bao With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs - Opteron 2372HE. Acked-by: Ward Vandewege Thanks, Ward. -- Ward Vandewege From Zheng.Bao at amd.com Thu Aug 6 05:00:28 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Thu, 6 Aug 2009 11:00:28 +0800 Subject: [coreboot] [patch] Fix CONFIG_GFXUMA in mtrr.c Message-ID: The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1. We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0. Signed-off-by: Zheng Bao Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 4505) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -418,7 +418,7 @@ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); -#ifdef CONFIG_GFXUMA +#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ // For now we assume the UMA space is at the end of memory if (var_state.hole_startk || var_state.hole_sizek) { printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); -------------- next part -------------- A non-text attachment was scrubbed... Name: fix_config_gfxuma.patch Type: application/octet-stream Size: 841 bytes Desc: fix_config_gfxuma.patch URL: From svn at coreboot.org Thu Aug 6 12:21:42 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 6 Aug 2009 12:21:42 +0200 Subject: [coreboot] [FILO] r104 - trunk/filo/drivers Message-ID: Author: stepan Date: 2009-08-06 12:21:41 +0200 (Thu, 06 Aug 2009) New Revision: 104 Modified: trunk/filo/drivers/intel.c Log: fix physical memory access in intel driver.. Modified: trunk/filo/drivers/intel.c =================================================================== --- trunk/filo/drivers/intel.c 2009-07-30 17:10:26 UTC (rev 103) +++ trunk/filo/drivers/intel.c 2009-08-06 10:21:41 UTC (rev 104) @@ -24,7 +24,7 @@ #define DEBUG_THIS CONFIG_DEBUG_INTEL #include -#define DEFAULT_RCBA 0xfed1c000 +#define DEFAULT_RCBA phys_to_virt(0xfed1c000) #define PM1_STS 0x00 #define PWRBTN_STS (1 << 8) From jon.harrison at selexgalileo.com Thu Aug 6 12:56:40 2009 From: jon.harrison at selexgalileo.com (Harrison, Jon (SELEX GALILEO, UK)) Date: Thu, 6 Aug 2009 11:56:40 +0100 Subject: [coreboot] Recent wpdchanges to acpi_write_rsdp In-Reply-To: References: Message-ID: <8E520A5E7FB8D647BFDA039F6031C1C605B00DAD@desmdswms201.des.grplnk.net> Hi guys, I've finally got my EPIA-N/CN400 port booting all of the way into linux (fc9 2.6.25) I've been merging my latest back into a copy of the current trunk (R4506)to get patches together, but I've found that ACPI is now broken in my build. It appear that the API to acpi_write_rsdp has changed to allow an xsdt table to be written. I have tried including and xsdt and also setting the pointer NULL the results are both the same. Is there some other table revision issue or perhaps alignment issue that needs to be taken care of ?? Thanks for any help. I'm on hols from tomorrow and would like to get the patch out before I go. Before acpi_write_rsdp API change::: High Tables Base is 3bff0000. Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x3bff0000... done. ACPI: Writing ACPI tables at 3bff0400... ACPI: * FACS ACPI: * DSDT ACPI: * DSDT @ 3bff04c0 Length 11fc ACPI: * FADT ACPI: added table 1/8 Length now 40 ACPI: * MADT ACPI: Creating lapic entry for CPU #0 in MADT ACPI: added table 2/8 Length now 44 ACPI: done. Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp table end at: 3bff1c10 - 3bff1d30 Moving GDT to 0x3bff2000...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 9fdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum ad2e After acpi_write_rsdp API change::: High Tables Base is 3bff0000. Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x3bff0000... done. ACPI: Writing ACPI tables at 3bff0400... ACPI: * FACS ACPI: * DSDT ACPI: * DSDT @ 3bff04c0 Length 11fc ACPI: * FADT ACPI: Error: Could not add ACPI table, too many tables. ACPI: * MADT ACPI: Error: Could not add ACPI table, too many tables. ACPI: done. Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp table end at: 3bff1c10 - 3bff1d30 Moving GDT to 0x3bff2000...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 9fdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum 9a77 SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ******************************************************************** From jon.harrison at selexgalileo.com Thu Aug 6 13:09:14 2009 From: jon.harrison at selexgalileo.com (Harrison, Jon (SELEX GALILEO, UK)) Date: Thu, 6 Aug 2009 12:09:14 +0100 Subject: [coreboot] Recent wpdchanges to acpi_write_rsdp References: Message-ID: <8E520A5E7FB8D647BFDA039F6031C1C605B00DDA@desmdswms201.des.grplnk.net> OK, I think I've seen it now. The API to acpi_add_table has changed too. It's now passed the rsdp as the root of the table structs rather than rsdt. Shouldn't we really have an announces list to advertise fairly fundamental API changes like this ? > -----Original Message----- > From: Harrison, Jon (SELEX GALILEO, UK) > Sent: 06 August 2009 11:57 > To: 'coreboot at coreboot.org' > Subject: Recent wpdchanges to acpi_write_rsdp > > > Hi guys, > > I've finally got my EPIA-N/CN400 port booting all of the way > into linux (fc9 2.6.25) > > I've been merging my latest back into a copy of the current > trunk (R4506)to get patches together, but I've found that > ACPI is now broken in my build. > > It appear that the API to acpi_write_rsdp has changed to > allow an xsdt table to be written. > > I have tried including and xsdt and also setting the pointer > NULL the results are both the same. > > Is there some other table revision issue or perhaps alignment > issue that needs to be taken care of ?? > > Thanks for any help. I'm on hols from tomorrow and would like > to get the patch out before I go. > > Before acpi_write_rsdp API change::: > > High Tables Base is 3bff0000. > Copying Interrupt Routing Table to 0x000f0000... done. > Copying Interrupt Routing Table to 0x3bff0000... done. > ACPI: Writing ACPI tables at 3bff0400... > ACPI: * FACS > ACPI: * DSDT > ACPI: * DSDT @ 3bff04c0 Length 11fc > ACPI: * FADT > ACPI: added table 1/8 Length now 40 > ACPI: * MADT > ACPI: Creating lapic entry for CPU #0 in MADT > ACPI: added table 2/8 Length now 44 > ACPI: done. > Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp > table end at: 3bff1c10 - 3bff1d30 Moving GDT to > 0x3bff2000...ok Multiboot Information structure has been written. > Writing high table forward entry at 0x00000500 Wrote coreboot > table at: 00000500 - 00000518 checksum 9fdf New > low_table_end: 0x00000518 Now going to write high coreboot > table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust > low_table_end from 0x00000518 to 0x00001000 Adjust > rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table > area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum ad2e > > After acpi_write_rsdp API change::: > > High Tables Base is 3bff0000. > Copying Interrupt Routing Table to 0x000f0000... done. > Copying Interrupt Routing Table to 0x3bff0000... done. > ACPI: Writing ACPI tables at 3bff0400... > ACPI: * FACS > ACPI: * DSDT > ACPI: * DSDT @ 3bff04c0 Length 11fc > ACPI: * FADT > ACPI: Error: Could not add ACPI table, too many tables. > ACPI: * MADT > ACPI: Error: Could not add ACPI table, too many tables. > ACPI: done. > Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp > table end at: 3bff1c10 - 3bff1d30 Moving GDT to > 0x3bff2000...ok Multiboot Information structure has been written. > Writing high table forward entry at 0x00000500 Wrote coreboot > table at: 00000500 - 00000518 checksum 9fdf New > low_table_end: 0x00000518 Now going to write high coreboot > table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust > low_table_end from 0x00000518 to 0x00001000 Adjust > rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table > area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum 9a77 SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ******************************************************************** From jacobs at itd.nrl.navy.mil Thu Aug 6 13:28:35 2009 From: jacobs at itd.nrl.navy.mil (Jeffrey C. Jacobs) Date: Thu, 06 Aug 2009 07:28:35 -0400 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <13426df10908051432t7edd9e90sb0c25381e8da79bb@mail.gmail.com> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> <4A79C5F1.6050601@itd.nrl.navy.mil> <13426df10908051432t7edd9e90sb0c25381e8da79bb@mail.gmail.com> Message-ID: <4A7ABE63.8030405@itd.nrl.navy.mil> ron minnich wrote: > A simple question which I can not tell from your boot line. Is this > disk partitioned? Sorry that was confusing; yes, it is partitioned using standard MBR partition tables (fdisk) and the first partition on the disk is an ext3fs partition containing my kernel and initrd. Jeffrey. From svn at coreboot.org Thu Aug 6 13:36:33 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 6 Aug 2009 13:36:33 +0200 Subject: [coreboot] [v2] r4507 - trunk/coreboot-v2/src/pc80 Message-ID: Author: stepan Date: 2009-08-06 13:36:33 +0200 (Thu, 06 Aug 2009) New Revision: 4507 Modified: trunk/coreboot-v2/src/pc80/serial.c Log: fix for the case that CONFIG_TTYS0_DIV is defined in mainboard's Config.lb Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/pc80/serial.c =================================================================== --- trunk/coreboot-v2/src/pc80/serial.c 2009-08-06 04:22:12 UTC (rev 4506) +++ trunk/coreboot-v2/src/pc80/serial.c 2009-08-06 11:36:33 UTC (rev 4507) @@ -13,7 +13,9 @@ #error Bad ttys0 baud rate #endif +#ifndef CONFIG_TTYS0_DIV #define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif /* Line Control Settings */ #ifndef CONFIG_TTYS0_LCS From jon.harrison at selexgalileo.com Thu Aug 6 13:46:10 2009 From: jon.harrison at selexgalileo.com (Harrison, Jon (SELEX GALILEO, UK)) Date: Thu, 6 Aug 2009 12:46:10 +0100 Subject: [coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R In-Reply-To: References: Message-ID: <8E520A5E7FB8D647BFDA039F6031C1C605B00E2C@desmdswms201.des.grplnk.net> Dear Corebooters, Please find attached a number of patches that get the Via EPIA-N(L)/CN400 to a reasonable level of maturity:: Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25 kernel) from SATA HDD. ACPI is working for PCI interrupt routing, some memory stuff and Soft-Off. USB/SATA Working VGA Console Working X Working via Onboard AGP There are a total of four patches:: ********************* pci_ids.patch (apply at src/include level):: Adds a couple of VT8237R Ids for the USB UHCI/EHCI interfaces. This is a dependency for all that follows. ********************* vt8237r.patch (apply at src/southbridge level):: This uses the CONFIG_EPIA_VT8237R_INIT option to customise SB init for the EPIA-N The main differences between the EPIA-N init and what is already there is that the Via C3 CPU uses the secondary APIC bus rather than FSB for IOAPIC to LAPIC comms. There are a few other EPIA MoBo specific tweaks in there too. This is a dependency for all that follows ********************* cn400.patch (apply at src/northbridge level):: Fixes for Vlink, RAM, Performance and Video This is a dependency for all that follows. ********************* epia-n.patch (apply at src/motherboard level):: Adds ACPI/APIC Support to EPIA-N irq_tables.c is chaged to one generated from an earlier version of getpir in reponse to issues raised with other ports on the code header from newer versions of the tool ********************* I have tried to keep any whitespace/comment only changes to a minimum. Signed-off-by: Jon Harrison SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ******************************************************************** -------------- next part -------------- A non-text attachment was scrubbed... Name: cn400.patch Type: application/octet-stream Size: 29343 bytes Desc: cn400.patch URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: epia-n.patch Type: application/octet-stream Size: 123855 bytes Desc: epia-n.patch URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: pci_ids.patch Type: application/octet-stream Size: 549 bytes Desc: pci_ids.patch URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: vt8237r.patch Type: application/octet-stream Size: 19848 bytes Desc: vt8237r.patch URL: From ward at gnu.org Thu Aug 6 17:39:59 2009 From: ward at gnu.org (Ward Vandewege) Date: Thu, 6 Aug 2009 11:39:59 -0400 Subject: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2 In-Reply-To: References: <20090720195806.GA23502@countzero.vandewege.net> Message-ID: <20090806153959.GA29508@countzero.vandewege.net> On Thu, Aug 06, 2009 at 10:26:38AM +0800, Bao, Zheng wrote: > I am trying to port the ddr3 feature. I will submit a full patch to > replace this one. Sounds good, thanks. I won't be able to test until the end of August though, but perhaps someone else can ack before then. Thanks, Ward. -- Ward Vandewege From jacobs at itd.nrl.navy.mil Thu Aug 6 17:53:52 2009 From: jacobs at itd.nrl.navy.mil (Jeffrey C. Jacobs) Date: Thu, 06 Aug 2009 11:53:52 -0400 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <4A79EA61.5020106@georgi-clan.de> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> <4A79C5F1.6050601@itd.nrl.navy.mil> <4A79EA61.5020106@georgi-clan.de> Message-ID: <4A7AFC90.3040007@itd.nrl.navy.mil> Patrick et al., Thanks again for the help and advice. Rudolf, I may try to look into your solution since I too am trying to boot off an ext3fs system but Patrick you have been a great help so far. I don't as a rule manually edit .config scripts, they're just convenient for reviewing settings. Actually, I used "make menuconfig", which is what is suggested in the FILO README, but that did not seem to generate build/config.h correctly so I tried the basic "make config" as you suggested and that seems to have generated the correct build. So I loaded up my CoreBoot+FILO payload and booted and got the result listed in: http://coreboot.pastebin.com/f432f39bc Now, with all those ANSI Escape Codes, I tried to clean up the last bit which has my FILO prompt and output: http://coreboot.pastebin.com/f7cb33b5 It's probably so busy because I have all the debugging output turned on. All that said, the bad news is that I still can't boot and it looks like it still doesn't recognize my hard drive. I've highlighted a few lines that I think may be relevant. Firstly, we have: ERROR: No such CMOS option (boot_devices) menu: hda1:/boot/filo/menu.lst I guess we can safely ignore the first line since we've not AFAICT entered the IDE probe yet and the second line just reiterates the menu.lst location. There follows a series of probes of memory addresses which are mostly uneventful. The exception is a failure to access the bridge at 01:09.00: Misconfigured bridge at 01:09.00 skipped. It seems to reprint this each time it tries to scan that memory area. I'm not sure what this represents, but I guess it's okay to ignore for the time being. Finally, we have a better description of my error: found PCI IDE controller 8086:24cb prog_if=0x8a primary channel: compatibility mode skipping 0 native PCI controllers, new index=0 cmd_base=0x1f0 ctrl_base=0x3f4 init_controller: drive 0 Detected floating bus No drive detected on IDE channel 0 Failed to open IDE. dev=hda1, path=/boot/filo/menu.lst Drive 0 does not exist Failed to open IDE. Could not open menu.lst file 'hda1:/boot/filo/menu.lst'. Entering command line. So I get this "No drive detected on IDE channel 0", which implies to me it's something lower-level that the file system. So, does anyone have any better idea, given this new information, why this version of FILO can't detect my hard drive? Thanks in Advance! Jeffrey. Patrick Georgi wrote: > Jeffrey C. Jacobs schrieb: >> Danke vielmals Patrick and many thanks to everyone else, >> >> So, I decided to take your advice about switching (back to) FILO using >> the latest version (svn 103) and latest libpayload (svn 4505) but am >> still having problems recognizing my First Partition on the Primary >> Master IDE device, namely hda1. Specifically, using the FILO build >> settings specified here: http://coreboot.pastebin.com/f4e644a72 > How did you change that configuration, simply by editing .config, or by > going through the "make config" routine? > Editing .config doesn't adapt the files in build/, so it should always > be completed with a "make oldconfig" (and then look if it took your > values or overwrote it with something else due to dependencies) > To be extra careful, always run "make clean" after changing the > configuration to force a full build. >> Anyway, since my menu.lst could not be loaded, I typed in the full >> boot command replete with kernel boot parameters, and as you can see I >> got a generic error stating that FILO could not find Device 0 >> (obviously meaning it could not find hda1). So, I'm not sure if this >> is a problem with FILO, but it seems much more likely I have some >> errant settings in Coreboot which is not allowing FILO to see my >> drives. Does anyone have any ideas? > The device numbering might be weird at times. It's reasonably stable > once you found the right device name, but it can differ from what you > see elsewhere, so try hdb, hdc, and hdd, too. > > > Patrick From andrew.k.s at gmail.com Wed Aug 5 18:06:55 2009 From: andrew.k.s at gmail.com (Andrew Suessmuth) Date: Wed, 5 Aug 2009 12:06:55 -0400 Subject: [coreboot] 790GX lspci output Message-ID: The output from lspci -nnvvvxxxx run on an MSI DKA790GX-Platinum, as requested by Carl-Daniel Hailfinger. -------------- next part -------------- A non-text attachment was scrubbed... Name: lspci-nnvvvxxxx Type: application/octet-stream Size: 43383 bytes Desc: not available URL: From tomwardathome at googlemail.com Thu Aug 6 18:17:29 2009 From: tomwardathome at googlemail.com (Thomas Ward) Date: Thu, 06 Aug 2009 17:17:29 +0100 Subject: [coreboot] ASUS KFN4D16 - K8 FAM10 In-Reply-To: <985851.32063.qm@web26106.mail.ukl.yahoo.com> References: <985851.32063.qm@web26106.mail.ukl.yahoo.com> Message-ID: <4A7B0219.3020603@yahoo.co.uk> 1. I can report that flashrom v0.9.0-r670 works with KFN4-D16 I flashed an ASUS ROM (3.02) and halted the computer and rebooted, computer booted up as normal. Should I formally inform someone so that the documentation can be updated to reflect the fact that flashwom works with this board? 2. I am struggling to configure coreboot for this board based on Myles Watson's recommendation of using the tyans2892 as a template. 2.1 in acpi_tables.c resourcemap.c mptable.c dsdt.dsl there are references to AMD8131, this board does not have an AMD8131, should I remove these references? 2.2 in Options.lb default CONFIG_MAINBOARD_PART_NUMBER="s2892" default CONFIG_MAINBOARD_VENDOR="Tyan" default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 Do I need to edit? 2.3 in dsdt.dsl there are references to onboard ATI RAGE, this board has an ES1000 and to an INTELL NIC, this board has broadcom 2.4 in Config.lb 2.4.1 there are references to 8 DIMMS, this board has 16 should I add 8 more from 58 to 65? chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end end 2.4.2 the SMBUS has ADT7463A and WINBOND monitors, do I need to edit this to reflect the KFN4-DE16?, How do I find out what the KFN4-D16 has 2.4.3 Do I just remove the references to AMD8131? Do I replace with anything? 2.4.4 Do I need to add info about the PCI-E to PCI bridge and the ATI ES1000 VGA? 02:00.0 PCI bridge: Intel Corporation 6702PXH PCI Express-to-PCI Bridge A (rev 09) 04:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5721 Gigabit Ethernet PCI Express (rev 21) 05:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5721 Gigabit Ethernet PCI Express (rev 21) 06:05.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) thanks again for your help Tom Ward thomas ward wrote: > Thanks Myles! > > Your reply is very helpfull to me (especailly the part about using v2 - I was unsure which of v2 or v3 was appropriate) and very clear. I will follow the "destructions" (probably not till August becasue busy in June and holiday most of July) and once I have blown up the board will post the results to this list. > > regards, > > Tom. > > > > --- On Wed, 17/6/09, Myles Watson wrote: > >> From: Myles Watson >> Subject: Re: [coreboot] ASUS KFN4D16 - K8 FAM10 >> To: "Thomas Ward" >> Cc: "coreboot at coreboot.org" >> Date: Wednesday, 17 June, 2009, 5:13 PM >> >> >> On Tue, Jun 16, 2009 at 3:36 AM, >> Thomas Ward >> wrote: >> >> Hello, >> >> I realise your list is very technical and this is probably >> a daft set of question so please forgive me if it is >> cluttering up your list but I couldn't find a more >> appropriate place to ask,.. >> >> ... so here goes. >> >> >> >> My questions are about running coreboot on an ASUS KFN4-D16 >> with an NVIDIA CK804 chipset and a SST SST49LF080A (BIOS?) >> chip 33-4C-NHE 0631138-B >> >> I have 2 cpus one is a 65nm dual core opteron 2210, the >> second CPU is a quad core 45nm "Shanghai" opteron >> 2376 - this CPU isn't supported by the ASUS BIOS. >> >> My aim is to get the board to boot with the quad core CPU, >> I would be happy if it boots with support for all the RAM >> and at least one of the ethernet ports, I can live without >> PCI, SATA, USB etc.They should all work. >> >> >> >> My plan is to use a BIOS saviour and buy a second >> SST49LF080A chip and then >> >> >> >> 1. flash coreboot for K8 (?) with flashrom to verify that >> coreboot works on this board >> >> 2. flash coreboot for fam10 (?) with flashrom >> >> >> >> does this sound like a good plan?Yes. >> >> >> I have a couple of other questions >> >> E. what sort of BIOS chip / bios saviour kit should I use >> with this board?RD1 >> >> >> >> output from flashrom, superiotool and lspci appended >> below, >> >> >> >> many thanks for any help and good luck with your project, >> >> >> >> Tom Ward >> >> >> >> root at shed:/home/tom/coreboot/flashrom# ./flashrom >> >> flashrom v0.9.0-r555 >> >> No coreboot table found. >> >> Found chipset "NVIDIA CK804", enabling flash >> write... OK. >> >> Calibrating delay loop... OK. >> >> Found chip "SST SST49LF080A" (1024 KB) at >> physical address 0xfff00000.Hopefully this >> chip is socketed. >> >> >> superiotool r3695 >> >> Found Winbond W83627THF/THG (id=0x82, rev=0x84) at >> 0x2eThis SuperIO is supported. >> >> >> 00:00.0 Memory controller: nVidia Corporation CK804 Memory >> Controller (rev a4) >> >> This board is very similar to the >> tyan/s2892. >> >> If I were you, my first step would be to get the BIOS >> savior (or just use the pushpin method) >> >> http://www.coreboot.org/Developer_Manual >> >> >> Once you can recover from a bad flash, >> >> check out the latest coreboot-v2 >> mkdir src/mainboard/asus/kfn4-d16 >> svn cp src/mainboard/tyan/s2892/* >> src/mainboard/asus/kfn4-d16/ >> mkdir targets/asus/kfn4-d16 >> >> svn cp targets/tyan/s2892/Config.lb targets/asus/kfn4-d16/ >> >> edit src/mainboard/asus/kfn4-d16/Config.lb >> >> Enable devices that are in your lspci, disable any that >> don't show up. Don't worry about cards that you >> plug in, they'll be found automatically. >> >> Change the SuperIO from chip superio/winbond/w83627hf to >> superio/winbond/w83627thf and change any settings there that >> you need to. >> Change socket_940 to socket_F >> >> (When you're ready to switch to fam10) >> Change amdk8 to amdfam10 everywhere (may need some other >> small fixups) >> >> >> edit targets/asus/kfn4-d16/Config.lb >> Change s2892 to kfn4-d16 >> make sure ROM_SIZE matches the chip you're using. >> >> >> >> cd targets >> >> ./buildtarget asus/kfn4-d16 >> >> make a payload (Maybe seabios) >> cp your_payload targets/asus/kfn4-d16/kfn4-d16/payload.elf >> >> make -C asus/kfn4-d16/kfn4-d16 >> >> Last step is to send your patches to the list with a >> Signed-off-by: line. >> >> >> Thanks, >> Myles >> >> >> -----Inline Attachment Follows----- >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > From patrick.georgi at coresystems.de Fri Aug 7 12:22:36 2009 From: patrick.georgi at coresystems.de (Patrick Georgi) Date: Fri, 07 Aug 2009 12:22:36 +0200 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <4A7AFC90.3040007@itd.nrl.navy.mil> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> <4A79C5F1.6050601@itd.nrl.navy.mil> <4A79EA61.5020106@georgi-clan.de> <4A7AFC90.3040007@itd.nrl.navy.mil> Message-ID: <1532cb2f2f06081ad57ef0cce8395af0@localhost> On Thu, 06 Aug 2009 11:53:52 -0400, "Jeffrey C. Jacobs" wrote: > There follows a series of probes of memory addresses which are mostly > uneventful. The exception is a failure to access the bridge at 01:09.00: > > Misconfigured bridge at 01:09.00 skipped. > > It seems to reprint this each time it tries to scan that memory area. > I'm not sure what this represents, but I guess it's okay to ignore for > the time being. This means that there is some bridge that claims is new client bus has the bus id 0. That leads to an endless loop (as any bridge is a child of bus 0 directly or indirectly) > Detected floating bus This indicates that you're using the "old" IDE driver. You could also try CONFIG_IDE_NEW_DISK, which is another IDE driver that sometimes helps and sometimes doesn't. It's worth a try. Regards, Patrick From jacobs at itd.nrl.navy.mil Fri Aug 7 16:01:11 2009 From: jacobs at itd.nrl.navy.mil (Jeffrey C. Jacobs) Date: Fri, 07 Aug 2009 10:01:11 -0400 Subject: [coreboot] Problem jumping to Boot Loader In-Reply-To: <1532cb2f2f06081ad57ef0cce8395af0@localhost> References: <4A6DB478.4090705@itd.nrl.navy.mil> <4A6DB726.2000001@georgi-clan.de> <4A6EEDD1.1070606@itd.nrl.navy.mil> <4A6EF23A.5090705@georgi-clan.de> <4A79C5F1.6050601@itd.nrl.navy.mil> <4A79EA61.5020106@georgi-clan.de> <4A7AFC90.3040007@itd.nrl.navy.mil> <1532cb2f2f06081ad57ef0cce8395af0@localhost> Message-ID: <4A7C33A7.4060206@itd.nrl.navy.mil> Patrick Georgi wrote: > On Thu, 06 Aug 2009 11:53:52 -0400, "Jeffrey C. Jacobs" wrote: >> Detected floating bus > This indicates that you're using the "old" IDE driver. You could also try > CONFIG_IDE_NEW_DISK, which is another IDE driver that sometimes helps and > sometimes doesn't. It's worth a try. Hmm. Okay, so I updated to the latest coreboot v2 just in case and then since that option is for FILO I ran make config and activated the new disk driver and made clean and then all. None the less, I still get: found PCI IDE controller 8086:24cb prog_if=0x8a primary channel: compatibility mode skipping 0 native PCI controllers, new index=0 Failed to open IDE. Could not open menu.lst file 'hda1:/boot/filo/menu.lst'. Entering command line. Alas. Do you have any other ideas, Patrick? Or anyone else? Thanks in advance, Jeffrey. From luja at openhardware.de Fri Aug 7 18:53:20 2009 From: luja at openhardware.de (Ludwig Jaffe) Date: Fri, 07 Aug 2009 18:53:20 +0200 Subject: [coreboot] Question: Is there a tpm enabled chain of trust to boot trusted grub? Message-ID: <4A7C5C00.10109@openhardware.de> Hi folks! Question: Is there a tpm enabled chain of trust to boot trusted grub? Does Coreboot support the infineon tpm which is supported by kernel? I want to have trusted-grub as payload? Any Ideas? Many thanks! LuJa From stepan at coresystems.de Sat Aug 8 01:51:17 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Sat, 08 Aug 2009 01:51:17 +0200 Subject: [coreboot] Question: Is there a tpm enabled chain of trust to boot trusted grub? In-Reply-To: <4A7C5C00.10109@openhardware.de> References: <4A7C5C00.10109@openhardware.de> Message-ID: <4A7CBDF5.30603@coresystems.de> On 8/7/09 6:53 PM, Ludwig Jaffe wrote: > Hi folks! > > > Question: Is there a tpm enabled chain of trust to boot trusted grub? > Does Coreboot support the infineon tpm which is supported by kernel? I > want to have trusted-grub as payload? > We had a signature checking grub2 a year or two ago. Didn't use TPMs though, as they didn't seem to add much to the security though. It's still available at http://www.coresystems.de/~stepan/grub2-coresystems.diff but we didn't update it to newer svn revisions than r1756 when it became clear that the grub2 development team would not be interested to allow our work go into their upstream repository. So it would be a bit work to get it up to date with a recent grub2 again. Best regards, Stefan From c-d.hailfinger.devel.2006 at gmx.net Sat Aug 8 03:14:43 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 08 Aug 2009 03:14:43 +0200 Subject: [coreboot] AMD RS780 docs released, coreboot support coming Message-ID: <4A7CD183.2020205@gmx.net> The coreboot community, which includes government organizations, corporations, research labs and individuals from around the world, is very excited to expand on our existing and decade-long collaboration with AMD. This collaboration has, over the years, resulted in the inclusion of coreboot into everything from some of the largest AMD-based supercomputers in the world to some of the smallest embedded systems. Together with the recent SB700/SB710/SB750 documentation release, the Developer Guide release for the RS780 family of Integrated Chipset/ Graphics Processors enables the coreboot community to support any board with AMD chipsets out there, from embedded to enthusiast desktop and high-end server boards. This new release once again demonstrates AMD's commitment to open standards and software that provides an improved user experience and Total Cost of Ownership for users in every walk of life. One cornerstone of this openness is the availability of documentation without NDA, enabling everyone to contribute. Coreboot is a BIOS/EFI alternative with optional BIOS/EFI backwards compatibility. Not only does coreboot enable extremely fast booting with well under one second spent inside coreboot, and total four second boot time from poweron to a working desktop, it also has superior reliability and realtime performance. Coreboot developers have embedded various operating systems, among them Linux and Plan 9, directly into onboard ROM chips yielding systems without moving parts and built-in network manageability. Virtualization is made easier by optionally embedding the KVM hypervisor into the ROM as well. Military strength encryption and access protection add-ons exist for environments where security is key. Its extended diagnostics in plain English are second to none. Of course, coreboot supports Windows XP/Vista/7 as well as Linux, *BSD and Plan 9. Coreboot is open source, so every interested developer or user can modify, tweak and extend it to their heart's content. An additional benefit of this documentation release is flashrom support for all AMD chipsets which enables users to reflash their BIOS/firmware/coreboot from within Linux and *BSD without rebooting. Coreboot code for the SB700 and 780 chipset family is already being worked on by Zheng Bao at AMD in his spare time and the coreboot community is happy to work with him on finishing and integrating the code into the official coreboot codebase. We'd like to thank Sharon Troia at AMD for making these documentation releases possible. The developer guides are available at http://developer.amd.com/documentation/guides/Pages/default.aspx#chipset More information about coreboot is available at http://www.coreboot.org/ From fishbaoz at hotmail.com Sat Aug 8 11:43:20 2009 From: fishbaoz at hotmail.com (Zheng Bao) Date: Sat, 8 Aug 2009 09:43:20 +0000 Subject: [coreboot] AMD RS780 docs released, coreboot support coming In-Reply-To: <4A7CD183.2020205@gmx.net> References: <4A7CD183.2020205@gmx.net> Message-ID: Great. I will submit my code after this weekend. I can't wait the coming of the new era. Zheng. > Date: Sat, 8 Aug 2009 03:14:43 +0200 > From: c-d.hailfinger.devel.2006 at gmx.net > To: coreboot-announce at coreboot.org > CC: coreboot at coreboot.org > Subject: [coreboot] AMD RS780 docs released, coreboot support coming > > The coreboot community, which includes government organizations, > corporations, research labs and individuals from around the world, is > very excited to expand on our existing and decade-long collaboration > with AMD. This collaboration has, over the years, resulted in the > inclusion of coreboot into everything from some of the largest AMD-based > supercomputers in the world to some of the smallest embedded systems. > > Together with the recent SB700/SB710/SB750 documentation release, the > Developer Guide release for the RS780 family of Integrated Chipset/ > Graphics Processors enables the coreboot community to support any board > with AMD chipsets out there, from embedded to enthusiast desktop and > high-end server boards. > > This new release once again demonstrates AMD's commitment to open > standards and software that provides an improved user experience and > Total Cost of Ownership for users in every walk of life. One cornerstone > of this openness is the availability of documentation without NDA, > enabling everyone to contribute. > > Coreboot is a BIOS/EFI alternative with optional BIOS/EFI backwards > compatibility. Not only does coreboot enable extremely fast booting with > well under one second spent inside coreboot, and total four second boot > time from poweron to a working desktop, it also has superior reliability > and realtime performance. Coreboot developers have embedded various > operating systems, among them Linux and Plan 9, directly into onboard > ROM chips yielding systems without moving parts and built-in network > manageability. Virtualization is made easier by optionally embedding the > KVM hypervisor into the ROM as well. Military strength encryption and > access protection add-ons exist for environments where security is key. > Its extended diagnostics in plain English are second to none. Of course, > coreboot supports Windows XP/Vista/7 as well as Linux, *BSD and Plan 9. > > Coreboot is open source, so every interested developer or user can > modify, tweak and extend it to their heart's content. > > An additional benefit of this documentation release is flashrom support > for all AMD chipsets which enables users to reflash their > BIOS/firmware/coreboot from within Linux and *BSD without rebooting. > > Coreboot code for the SB700 and 780 chipset family is already being > worked on by Zheng Bao at AMD in his spare time and the coreboot > community is happy to work with him on finishing and integrating the > code into the official coreboot codebase. > > We'd like to thank Sharon Troia at AMD for making these documentation > releases possible. > > The developer guides are available at > http://developer.amd.com/documentation/guides/Pages/default.aspx#chipset > > More information about coreboot is available at http://www.coreboot.org/ > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot _________________________________________________________________ With Windows Live, you can organize, edit, and share your photos. http://www.microsoft.com/middleeast/windows/windowslive/products/photo-gallery-edit.aspx -------------- next part -------------- An HTML attachment was scrubbed... URL: From fishbaoz at hotmail.com Sat Aug 8 11:46:22 2009 From: fishbaoz at hotmail.com (Zheng Bao) Date: Sat, 8 Aug 2009 09:46:22 +0000 Subject: [coreboot] AMD RS780 docs released, coreboot support coming In-Reply-To: <4A7CD183.2020205@gmx.net> References: <4A7CD183.2020205@gmx.net> Message-ID: Oh, by the way, please add a 780 entry in the http://www.coreboot.org/Datasheets. Thanks a lot. Zheng > Date: Sat, 8 Aug 2009 03:14:43 +0200 > From: c-d.hailfinger.devel.2006 at gmx.net > To: coreboot-announce at coreboot.org > CC: coreboot at coreboot.org > Subject: [coreboot] AMD RS780 docs released, coreboot support coming > > The coreboot community, which includes government organizations, > corporations, research labs and individuals from around the world, is > very excited to expand on our existing and decade-long collaboration > with AMD. This collaboration has, over the years, resulted in the > inclusion of coreboot into everything from some of the largest AMD-based > supercomputers in the world to some of the smallest embedded systems. > > Together with the recent SB700/SB710/SB750 documentation release, the > Developer Guide release for the RS780 family of Integrated Chipset/ > Graphics Processors enables the coreboot community to support any board > with AMD chipsets out there, from embedded to enthusiast desktop and > high-end server boards. > > This new release once again demonstrates AMD's commitment to open > standards and software that provides an improved user experience and > Total Cost of Ownership for users in every walk of life. One cornerstone > of this openness is the availability of documentation without NDA, > enabling everyone to contribute. > > Coreboot is a BIOS/EFI alternative with optional BIOS/EFI backwards > compatibility. Not only does coreboot enable extremely fast booting with > well under one second spent inside coreboot, and total four second boot > time from poweron to a working desktop, it also has superior reliability > and realtime performance. Coreboot developers have embedded various > operating systems, among them Linux and Plan 9, directly into onboard > ROM chips yielding systems without moving parts and built-in network > manageability. Virtualization is made easier by optionally embedding the > KVM hypervisor into the ROM as well. Military strength encryption and > access protection add-ons exist for environments where security is key. > Its extended diagnostics in plain English are second to none. Of course, > coreboot supports Windows XP/Vista/7 as well as Linux, *BSD and Plan 9. > > Coreboot is open source, so every interested developer or user can > modify, tweak and extend it to their heart's content. > > An additional benefit of this documentation release is flashrom support > for all AMD chipsets which enables users to reflash their > BIOS/firmware/coreboot from within Linux and *BSD without rebooting. > > Coreboot code for the SB700 and 780 chipset family is already being > worked on by Zheng Bao at AMD in his spare time and the coreboot > community is happy to work with him on finishing and integrating the > code into the official coreboot codebase. > > We'd like to thank Sharon Troia at AMD for making these documentation > releases possible. > > The developer guides are available at > http://developer.amd.com/documentation/guides/Pages/default.aspx#chipset > > More information about coreboot is available at http://www.coreboot.org/ > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot _________________________________________________________________ Share your memories online with anyone you want. http://www.microsoft.com/middleeast/windows/windowslive/products/photos-share.aspx?tab=1 -------------- next part -------------- An HTML attachment was scrubbed... URL: From fishbaoz at hotmail.com Sat Aug 8 11:55:21 2009 From: fishbaoz at hotmail.com (Zheng Bao) Date: Sat, 8 Aug 2009 09:55:21 +0000 Subject: [coreboot] AMD RS780 docWs released, coreboot support coming In-Reply-To: <4A7CD183.2020205@gmx.net> References: <4A7CD183.2020205@gmx.net> Message-ID: I need to clarify that the main feature of the code was done in working time. What I did in my spare time is cleaning up and testing to make it stable. Zheng > Date: Sat, 8 Aug 2009 03:14:43 +0200 > From: c-d.hailfinger.devel.2006 at gmx.net > To: coreboot-announce at coreboot.org > CC: coreboot at coreboot.org > Subject: [coreboot] AMD RS780 docs released, coreboot support coming > > The coreboot community, which includes government organizations, > corporations, research labs and individuals from around the world, is > very excited to expand on our existing and decade-long collaboration > with AMD. This collaboration has, over the years, resulted in the > inclusion of coreboot into everything from some of the largest AMD-based > supercomputers in the world to some of the smallest embedded systems. > > Together with the recent SB700/SB710/SB750 documentation release, the > Developer Guide release for the RS780 family of Integrated Chipset/ > Graphics Processors enables the coreboot community to support any board > with AMD chipsets out there, from embedded to enthusiast desktop and > high-end server boards. > > This new release once again demonstrates AMD's commitment to open > standards and software that provides an improved user experience and > Total Cost of Ownership for users in every walk of life. One cornerstone > of this openness is the availability of documentation without NDA, > enabling everyone to contribute. > > Coreboot is a BIOS/EFI alternative with optional BIOS/EFI backwards > compatibility. Not only does coreboot enable extremely fast booting with > well under one second spent inside coreboot, and total four second boot > time from poweron to a working desktop, it also has superior reliability > and realtime performance. Coreboot developers have embedded various > operating systems, among them Linux and Plan 9, directly into onboard > ROM chips yielding systems without moving parts and built-in network > manageability. Virtualization is made easier by optionally embedding the > KVM hypervisor into the ROM as well. Military strength encryption and > access protection add-ons exist for environments where security is key. > Its extended diagnostics in plain English are second to none. Of course, > coreboot supports Windows XP/Vista/7 as well as Linux, *BSD and Plan 9. > > Coreboot is open source, so every interested developer or user can > modify, tweak and extend it to their heart's content. > > An additional benefit of this documentation release is flashrom support > for all AMD chipsets which enables users to reflash their > BIOS/firmware/coreboot from within Linux and *BSD without rebooting. > > Coreboot code for the SB700 and 780 chipset family is already being > worked on by Zheng Bao at AMD in his spare time and the coreboot > community is happy to work with him on finishing and integrating the > code into the official coreboot codebase. > > We'd like to thank Sharon Troia at AMD for making these documentation > releases possible. > > The developer guides are available at > http://developer.amd.com/documentation/guides/Pages/default.aspx#chipset > > More information about coreboot is available at http://www.coreboot.org/ > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot _________________________________________________________________ Drag n? drop?Get easy photo sharing with Windows Live? Photos. http://www.microsoft.com/windows/windowslive/products/photos.aspx -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Sat Aug 8 12:03:49 2009 From: peter at stuge.se (Peter Stuge) Date: Sat, 8 Aug 2009 12:03:49 +0200 Subject: [coreboot] AMD RS780 docWs released, coreboot support coming In-Reply-To: References: <4A7CD183.2020205@gmx.net> Message-ID: <20090808100350.3176.qmail@stuge.se> Hi Zheng, AMD, Zheng Bao wrote: > I need to clarify that the main feature of the code was done in > working time. What I did in my spare time is cleaning up and > testing to make it stable. That is really fantastic. A big thank you to AMD, and to you, for the great contribution to coreboot! //Peter From ward at gnu.org Sat Aug 8 12:12:08 2009 From: ward at gnu.org (Ward Vandewege) Date: Sat, 8 Aug 2009 06:12:08 -0400 Subject: [coreboot] AMD RS780 docs released, coreboot support coming In-Reply-To: References: <4A7CD183.2020205@gmx.net> Message-ID: <20090808101208.GA31630@countzero.vandewege.net> On Sat, Aug 08, 2009 at 09:46:22AM +0000, Zheng Bao wrote: > Oh, by the way, please add a 780 entry in the http://www.coreboot.org/Datasheets. Done. Many thanks! Ward. -- Ward Vandewege From harald.gutmann at gmx.net Sat Aug 8 13:12:14 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Sat, 8 Aug 2009 13:12:14 +0200 Subject: [coreboot] AMD RS780 docs released, coreboot support coming In-Reply-To: <4A7CD183.2020205@gmx.net> References: <4A7CD183.2020205@gmx.net> Message-ID: <200908081312.14120.harald.gutmann@gmx.net> On Saturday 08 August 2009 03:14:43 Carl-Daniel Hailfinger wrote: > Together with the recent SB700/SB710/SB750 documentation release, the > Developer Guide release for the RS780 family of Integrated Chipset/ > Graphics Processors enables the coreboot community to support any board > with AMD chipsets out there, from embedded to enthusiast desktop and > high-end server boards. > > This new release once again demonstrates AMD's commitment to open > standards and software that provides an improved user experience and > Total Cost of Ownership for users in every walk of life. One cornerstone > of this openness is the availability of documentation without NDA, > enabling everyone to contribute. I really love AMD for being so OpenSource friendly! Can someone give a statement which chipsets/mainboards can be supported with that information what AMD published? Or which chipsets are in the "RS780 family"? Kind regards, Harald From c-d.hailfinger.devel.2006 at gmx.net Sat Aug 8 13:42:55 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 08 Aug 2009 13:42:55 +0200 Subject: [coreboot] AMD RS780 docs released, coreboot support coming In-Reply-To: <200908081312.14120.harald.gutmann@gmx.net> References: <4A7CD183.2020205@gmx.net> <200908081312.14120.harald.gutmann@gmx.net> Message-ID: <4A7D64BF.5040601@gmx.net> On 08.08.2009 13:12, Harald Gutmann wrote: > On Saturday 08 August 2009 03:14:43 Carl-Daniel Hailfinger wrote: > >> Together with the recent SB700/SB710/SB750 documentation release, the >> Developer Guide release for the RS780 family of Integrated Chipset/ >> Graphics Processors enables the coreboot community to support any board >> with AMD chipsets out there, from embedded to enthusiast desktop and >> high-end server boards. >> > Can someone give a statement which chipsets/mainboards can be supported with > that information what AMD published? > Or which chipsets are in the "RS780 family"? > Sure. We now have docs for all AMD chipsets out there (except early ATI stuff like SB400 and the latest 785G), so any board with 690G/690V/740G/760G/770/780G/780M/780V/790FX/790GX/790X and SB600/SB700/SB710/SB750 is now supportable. Regards, Carl-Daniel -- http://www.hailfinger.org/ From harald.gutmann at gmx.net Sat Aug 8 14:53:44 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Sat, 8 Aug 2009 14:53:44 +0200 Subject: [coreboot] AMD RS780 docs released, coreboot support coming In-Reply-To: <4A7D64BF.5040601@gmx.net> References: <4A7CD183.2020205@gmx.net> <200908081312.14120.harald.gutmann@gmx.net> <4A7D64BF.5040601@gmx.net> Message-ID: <200908081453.44673.harald.gutmann@gmx.net> On Saturday 08 August 2009 13:42:55 Carl-Daniel Hailfinger wrote: > On 08.08.2009 13:12, Harald Gutmann wrote: > > On Saturday 08 August 2009 03:14:43 Carl-Daniel Hailfinger wrote: > >> Together with the recent SB700/SB710/SB750 documentation release, the > >> Developer Guide release for the RS780 family of Integrated Chipset/ > >> Graphics Processors enables the coreboot community to support any board > >> with AMD chipsets out there, from embedded to enthusiast desktop and > >> high-end server boards. > > > > Can someone give a statement which chipsets/mainboards can be supported > > with that information what AMD published? > > Or which chipsets are in the "RS780 family"? > > Sure. We now have docs for all AMD chipsets out there (except early ATI > stuff like SB400 and the latest 785G), so any board with > 690G/690V/740G/760G/770/780G/780M/780V/790FX/790GX/790X and Does anyone know if 790FX is covered by the docs? As stated on Wikipedia [1] the codename for 790FX is RD790 and this one is not stated in the docs. [1] http://en.wikipedia.org/wiki/AMD_700_chipset_series#790FX > SB600/SB700/SB710/SB750 is now supportable. Regards, Harald > Regards, > Carl-Daniel > > -- > http://www.hailfinger.org/ From peter at stuge.se Sat Aug 8 16:28:02 2009 From: peter at stuge.se (Peter Stuge) Date: Sat, 8 Aug 2009 16:28:02 +0200 Subject: [coreboot] ELC 2009 videos and slides Message-ID: <20090808142802.4877.qmail@stuge.se> http://free-electrons.com/blog/elc-2009-videos/ Some I found particularly interesting: Quantitative analysis of system initialization in embedded Linux systems, by Andre Puschmann http://tree.celinuxforum.org/CelfPubWiki/ELC2009Presentations?action=AttachFile&do=get&target=ELC09_boottime_reduction.pdf Building Embedded Linux Systems with Buildroot, by Thomas Petazzoni http://www.celinuxforum.org/CelfPubWiki/ELC2009Presentations?action=AttachFile&do=get&target=buildroot.pdf Ksplice: Rebootless kernel updates, by Jeff Arnold (if new to you) http://www.celinuxforum.org/CelfPubWiki/ELC2009Presentations?action=AttachFile&do=view&target=elc2009-ksplice.pdf //Peter From garyhunt at mnsi.net Sun Aug 9 02:02:43 2009 From: garyhunt at mnsi.net (GS Hunt) Date: Sat, 08 Aug 2009 20:02:43 -0400 Subject: [coreboot] 740G Info - Foxconn RS740M03A1-8EKRS2H Skt AM2 Motherboard Message-ID: <4A7E1223.3050605@mnsi.net> Attached info... flashrom -V lspci -nnvvvxxxx superiotool -edV dmidecode and a picture... http://bitzotech.com/images/B5757.jpg Cheers, Gary From garyhunt at mnsi.net Sun Aug 9 02:05:31 2009 From: garyhunt at mnsi.net (GS Hunt) Date: Sat, 08 Aug 2009 20:05:31 -0400 Subject: [coreboot] 740G Info - Foxconn RS740M03A1-8EKRS2H Skt AM2 Motherboard Message-ID: <4A7E12CB.70802@mnsi.net> okay stuff is REALLY attached this time gary -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: dmiecode.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom.v.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: lspci.nnvvvxxxx.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: superiotool.edV.txt URL: From tjourdan at neuf.fr Sun Aug 9 18:55:38 2009 From: tjourdan at neuf.fr (Thomas Jourdan) Date: Sun, 09 Aug 2009 18:55:38 +0200 Subject: [coreboot] Need new type for CBFS Message-ID: <1249836938.21731.22.camel@desktop> Hi guys I was playing with CBFS and I found an strange behavior. There are actually 4 types of files in a CBFS rom : stage, payload, option rom and NULL. The latest is used when we don't care of the component type. I guess if we want to embed a logo, payload specific data or other stuffs, we must use this NULL type. The problem is that the free space in the rom also has a NULL type. In the fs.c file, rom_alloc function, the code searches for a cbfs_file with type == CBFS_COMPONENT_NULL, and if it is large enough, it will store the file in it. Otherwise, it continues until finding a large enough NULL type file. If you want to add more than one NULL type file, it will work as long as you insert them from the smallest to the largest. Otherwise the NULL type file you are adding will overwrite an existing one. Example to reproduce the behavior : - create a dummy bootblock dd if=/dev/urandom of=bootblock.rom bs=64k count=1 - create a test cbfs archive ./cbfstool test.rom create 524288 65536 ./bootblock.rom - create 2 dummy files (64 and 128 KB) dd if=/dev/urandom of=dummy64K bs=64k count=1 dd if=/dev/urandom of=dummy128K bs=64k count=2 Now, if I add my files from the smallest to the largest : ./cbfstool test.rom add dummy64K dummy64K free ./cbfstool test.rom add dummy128K dummy128K free ./cbfstool test.rom print test.rom: 512 kB, bootblocksize 65536, romsize 524288, offset 0x0 Alignment: 16 bytes Name Offset Type Size dummy64K 0x0 free 65536 dummy128K 0x10030 free 131072 0x30060 free 261976 Everything works fine. But if I had the 128K file first, then the 64K file : ./cbfstool test.rom add dummy128K dummy128K free ./cbfstool test.rom add dummy64K dummy64K free ./cbfstool test.rom print test.rom: 512 kB, bootblocksize 65536, romsize 524288, offset 0x0 Alignment: 16 bytes Name Offset Type Size dummy64K 0x0 free 65536 0x10030 free 65496 0x20030 free 327560 I think it is required to make the distinction between a user or custom type for embedded data, and the free space. What do you think ? Regards, Thomas Bonus question : shouldn't the cbfs code (to parse, find a file...) be added to the libpayload ? From patrick at georgi-clan.de Sun Aug 9 19:36:32 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sun, 09 Aug 2009 19:36:32 +0200 Subject: [coreboot] Need new type for CBFS In-Reply-To: <1249836938.21731.22.camel@desktop> References: <1249836938.21731.22.camel@desktop> Message-ID: <1e69a5d6e0734b12b5e9c2f943595c49@localhost> On Sun, 09 Aug 2009 18:55:38 +0200, Thomas Jourdan wrote: > I was playing with CBFS and I found an strange behavior. There are > actually 4 types of files in a CBFS rom : stage, payload, option rom and > NULL. The latest is used when we don't care of the component type. No, the latest is used for free memory regions. You can define 256 different types, of which 4 are predefined, and there is some rough partitioning of the file type space - that you can honor, or not. > I guess if we want to embed a logo, payload specific data or other > stuffs, we must use this NULL type. The problem is that the free space As said, NULL is not suitable for that. So your conclusions are wrong. > What do you think ? Define whatever types you want, expect problems as the numbers might be reused at some point. CBFS isn't finished yet, and it isn't even clean enough at this point to define stable contracts about it (eg. file types beyond what we already have) > Bonus question : shouldn't the cbfs code (to parse, find a file...) be > added to the libpayload ? Yes, at some point. Properly licensed, and properly designed, once CBFS itself is stable enough. There are only 24 hours in a day (that also applies to CBFS development). CBFS is already an improvement over the old layout in its current state. You're moving beyond what CBFS can provide right now if you put any data into it that isn't supported by the coreboot build system. Future proof designs and implementations welcome. Patrick From rminnich at gmail.com Sun Aug 9 20:16:49 2009 From: rminnich at gmail.com (ron minnich) Date: Sun, 9 Aug 2009 11:16:49 -0700 Subject: [coreboot] Need new type for CBFS In-Reply-To: <1249836938.21731.22.camel@desktop> References: <1249836938.21731.22.camel@desktop> Message-ID: <13426df10908091116o7511f02ta1172e8a3ba3276a@mail.gmail.com> Definitely don't use NULL for anything -- it's a free space marker as patrick points out. The type is actually unsigned int type; I would make the following proposal: we reserve the range 0-255 for cbfs "system" (i.e. coreboot) use and open up the rest of the range for any other use. Then we allow people to register types on the wiki in some way. I can't believe coreboot will ever need more than 256 types, and I can't believe the community will ever need more than 16M. ron From Cristi.Magherusan at net.utcluj.ro Sun Aug 9 22:27:04 2009 From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan) Date: Sun, 09 Aug 2009 23:27:04 +0300 Subject: [coreboot] mkelfimage with CBFS? Message-ID: <1249849624.20255.18.camel@ufo> Hello, First of all, I'd like to know if mkelfimage is still needed when using CBFS and LAB payloads, and what would be its purpose once the kernel can already be compiled as an ELF vmlinux binary with initramfs included, using for example buildroot and the kernel buildsystem's features. Does it have anything to do with the multiboot specification, or why does coreboot need the ELF to be modified using the mkelfImage tool? Thanks, Cristi -- Ing. Cristi M?gheru?an, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part URL: From peter at stuge.se Sun Aug 9 22:33:20 2009 From: peter at stuge.se (Peter Stuge) Date: Sun, 9 Aug 2009 22:33:20 +0200 Subject: [coreboot] mkelfimage with CBFS? In-Reply-To: <1249849624.20255.18.camel@ufo> References: <1249849624.20255.18.camel@ufo> Message-ID: <20090809203320.23759.qmail@stuge.se> Cristi Magherusan wrote: > if mkelfimage is still needed I don't know. > ELF vmlinux binary with initramfs Yes, it's a good idea. Please try it and report if it works. Also see http://www.coreboot.org/Initramfs > Does it have anything to do with the multiboot specification, No, multiboot is a separate topic. > or why does coreboot need the ELF to be modified using the > mkelfImage tool? I am not sure that it does need that. Did you try using the plain vmlinux? Can you compare the vmlinux entry point with the entrypoint of an mkelfImaged ELF image? //Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: From Cristi.Magherusan at net.utcluj.ro Sun Aug 9 22:57:22 2009 From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan) Date: Sun, 09 Aug 2009 23:57:22 +0300 Subject: [coreboot] mkelfimage with CBFS? In-Reply-To: <20090809203320.23759.qmail@stuge.se> References: <1249849624.20255.18.camel@ufo> <20090809203320.23759.qmail@stuge.se> Message-ID: <1249851442.20255.31.camel@ufo> On Sun, 2009-08-09 at 22:33 +0200, Peter Stuge wrote: > Cristi Magherusan wrote: > > if mkelfimage is still needed > > I don't know. > > > > ELF vmlinux binary with initramfs > > Yes, it's a good idea. Please try it and report if it works. Also see > http://www.coreboot.org/Initramfs I have a similar image generated using buildroot(for the userland/initramfs), and the kernel's initramfs option that allows it to use a designated directory. It seems to fail with both approaches when using CBFS (qemu with LAB kernel). With mkelfimage qemu crashes, while without it freezes while trying to load the kernel. The same kernel boots in qemu when compiled as bzImage, and the userspace is loaded fine. > > > Does it have anything to do with the multiboot specification, > > No, multiboot is a separate topic. > > > or why does coreboot need the ELF to be modified using the > > mkelfImage tool? > > I am not sure that it does need that. Did you try using the plain > vmlinux? Yes, still fails. > Can you compare the vmlinux entry point with the entrypoint of an > mkelfImaged ELF image? It differs, I suppose mkelfimage adds its own binary glue that will run before calling the real kernel image. Here's the "readelf -h" output for both(first is with mkelfImage). File: ./buildroot-payload.elf ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: Intel 80386 Version: 0x1 Entry point address: 0x10000 Start of program headers: 52 (bytes into file) Start of section headers: 0 (bytes into file) Flags: 0x0 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) Number of program headers: 5 Size of section headers: 0 (bytes) Number of section headers: 0 Section header string table index: 0 File: ./vmlinux ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: Intel 80386 Version: 0x1 Entry point address: 0x100000 Start of program headers: 52 (bytes into file) Start of section headers: 4995368 (bytes into file) Flags: 0x0 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) Number of program headers: 3 Size of section headers: 40 (bytes) Number of section headers: 30 Section header string table index: 29 I'll try to make the kernel entry point the same as mkelfimage, but I doubt it will work. Any other ideas? If anyone decides to give it a try, the kernel images are available here: http://panzer.utcluj.ro/~alien/coreboot/elfs.tar.bz2 Thanks, Cristi -- Ing. Cristi M?gheru?an, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part URL: From rminnich at gmail.com Mon Aug 10 00:01:00 2009 From: rminnich at gmail.com (ron minnich) Date: Sun, 9 Aug 2009 15:01:00 -0700 Subject: [coreboot] mkelfimage with CBFS? In-Reply-To: <1249851442.20255.31.camel@ufo> References: <1249849624.20255.18.camel@ufo> <20090809203320.23759.qmail@stuge.se> <1249851442.20255.31.camel@ufo> Message-ID: <13426df10908091501m715a1118le04008af854a124f@mail.gmail.com> You should not need mkelfimage, and have not needed it for a long time. I'll take a look at those images. ron From tjourdan at neuf.fr Mon Aug 10 00:02:46 2009 From: tjourdan at neuf.fr (Thomas Jourdan) Date: Mon, 10 Aug 2009 00:02:46 +0200 Subject: [coreboot] Need new type for CBFS In-Reply-To: <13426df10908091116o7511f02ta1172e8a3ba3276a@mail.gmail.com> References: <1249836938.21731.22.camel@desktop> <13426df10908091116o7511f02ta1172e8a3ba3276a@mail.gmail.com> Message-ID: <1249855366.27335.7.camel@desktop> Hi guys Thanks for those clarifications. When I read the cbfs documentation, I understood that for custom types, NULL was the correct type to use. The documentation isn't really clear on this : "There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is the "don't care" component type. This can be used when the component type is not necessary (such as when the name of the component is unique. i.e. option_table). It is recommended that all components be assigned a unique type, but NULL can be used when the type does not matter." I thought that the type parameter you enter when adding a component in the cbfs file shall be one of the predefined string. I didn't know that it could be any integer number (except the predefined ones). Indeed, it works a lot better when I use a custom type. Regards, Thomas Le dimanche 09 ao?t 2009 ? 11:16 -0700, ron minnich a ?crit : > Definitely don't use NULL for anything -- it's a free space marker as > patrick points out. > > The type is actually > unsigned int type; > > I would make the following proposal: we reserve the range 0-255 for > cbfs "system" (i.e. coreboot) use and open up the rest of the range > for any other use. Then we allow people to register types on the wiki > in some way. > > I can't believe coreboot will ever need more than 256 types, and I > can't believe the community will ever need more than 16M. > > ron > From rminnich at gmail.com Mon Aug 10 00:13:37 2009 From: rminnich at gmail.com (ron minnich) Date: Sun, 9 Aug 2009 15:13:37 -0700 Subject: [coreboot] mkelfimage with CBFS? In-Reply-To: <13426df10908091501m715a1118le04008af854a124f@mail.gmail.com> References: <1249849624.20255.18.camel@ufo> <20090809203320.23759.qmail@stuge.se> <1249851442.20255.31.camel@ufo> <13426df10908091501m715a1118le04008af854a124f@mail.gmail.com> Message-ID: <13426df10908091513s5ae31dc8wd19967edd8c2055d@mail.gmail.com> Well, I think I see your problem. Check this out: ENTRY(startup_32) /* test KEEP_SEGMENTS flag to see if the bootloader is asking us to not reload segments */ testb $(1<<6), BP_loadflags(%esi) jnz 2f /* * Set segments to known values. */ lgdt pa(boot_gdt_descr) movl $(__BOOT_DS),%eax movl %eax,%ds movl %eax,%es movl %eax,%fs movl %eax,%gs 2: So things have changed a bit since the last time I did this type of thing. It's expecting esi to point somewhere sensible (is it?) and it's expecting that somewhere to have resonable boot flags. Now IIRC this kernel loads fine with Filo. Probably time to look and make sure you are doing what FILO does. ron From rminnich at gmail.com Mon Aug 10 00:14:50 2009 From: rminnich at gmail.com (ron minnich) Date: Sun, 9 Aug 2009 15:14:50 -0700 Subject: [coreboot] Need new type for CBFS In-Reply-To: <1249855366.27335.7.camel@desktop> References: <1249836938.21731.22.camel@desktop> <13426df10908091116o7511f02ta1172e8a3ba3276a@mail.gmail.com> <1249855366.27335.7.camel@desktop> Message-ID: <13426df10908091514s1930ed40wa2c3e87db96bb34d@mail.gmail.com> On Sun, Aug 9, 2009 at 3:02 PM, Thomas Jourdan wrote: > "There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is > the "don't care" component type. This can be used when the component > type is not necessary (such as when the name of the component is unique. > i.e. option_table). It is recommended that all components be assigned a > unique type, but NULL can be used when the type does not matter." Nice catch! My apologies -- turns out we needed NULL for empty space (this really cleaned things up) and this part of the doco is obsolete. I'll take a patch to fix it. ron From c-d.hailfinger.devel.2006 at gmx.net Mon Aug 10 00:28:13 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 10 Aug 2009 00:28:13 +0200 Subject: [coreboot] 10th anniversary celebration? Message-ID: <4A7F4D7D.7020303@gmx.net> Hi, I remember that coreboot will have its 10th birthday soon. Will there be any meetings, parties or summits related to that special occassion? Regards, Carl-Daniel -- http://www.hailfinger.org/ From r.marek at assembler.cz Mon Aug 10 00:33:05 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 10 Aug 2009 00:33:05 +0200 Subject: [coreboot] 10th anniversary celebration? In-Reply-To: <4A7F4D7D.7020303@gmx.net> References: <4A7F4D7D.7020303@gmx.net> Message-ID: <4A7F4EA1.7080202@assembler.cz> Hi all, I'm prepared to come to Germany ;) as we discussed earlier seems best target for a meeting. Rudolf From kevin at koconnor.net Mon Aug 10 01:41:24 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Sun, 9 Aug 2009 19:41:24 -0400 Subject: [coreboot] Need new type for CBFS In-Reply-To: <13426df10908091116o7511f02ta1172e8a3ba3276a@mail.gmail.com> References: <1249836938.21731.22.camel@desktop> <13426df10908091116o7511f02ta1172e8a3ba3276a@mail.gmail.com> Message-ID: <20090809234124.GA12490@morn.localdomain> On Sun, Aug 09, 2009 at 11:16:49AM -0700, ron minnich wrote: > Definitely don't use NULL for anything -- it's a free space marker as > patrick points out. > > The type is actually > unsigned int type; > > I would make the following proposal: we reserve the range 0-255 for > cbfs "system" (i.e. coreboot) use and open up the rest of the range > for any other use. Then we allow people to register types on the wiki > in some way. > > I can't believe coreboot will ever need more than 256 types, and I > can't believe the community will ever need more than 16M. I believe the community doesn't need any types. I fear we're creating work that doesn't need to be done. (Why maintain a wiki and/or build a standard around a feature that isn't needed?) Of the four types defined: null - can be implemented by setting the first character of the filename to 0 on deleted files. This is actually easier for file finding code because then it can just do a filename search and not have to worry about matching deleted files. stage - instead of having a type in the cbfs header, a signature can be added to cbfs_stage. The same validity check can then be done there. payload - same as 'stage' - add signature to cbfs_payload. optionrom - isn't actually in use. Both SeaBIOS and coreboot expect to find option roms without any special header. -Kevin From mylesgw at gmail.com Mon Aug 10 17:32:49 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 10 Aug 2009 09:32:49 -0600 Subject: [coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R In-Reply-To: <8E520A5E7FB8D647BFDA039F6031C1C605B00E2C@desmdswms201.des.grplnk.net> References: <8E520A5E7FB8D647BFDA039F6031C1C605B00E2C@desmdswms201.des.grplnk.net> Message-ID: <8A8FC8AE80F84C68A4F21717AFCA53DC@chimp> > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Harrison, Jon (SELEX GALILEO, UK) > Sent: Thursday, August 06, 2009 5:46 AM > To: coreboot at coreboot.org > Subject: [coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R > > Dear Corebooters, > > Please find attached a number of patches that get the Via > EPIA-N(L)/CN400 to a reasonable level of maturity:: > > Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25 > kernel) from SATA HDD. Good work! > ACPI is working for PCI interrupt routing, some memory stuff and > Soft-Off. > USB/SATA Working > VGA Console Working > X Working via Onboard AGP > > There are a total of four patches:: > > ********************* > pci_ids.patch (apply at src/include level):: > Adds a couple of VT8237R Ids for the USB UHCI/EHCI interfaces. Fine. > This is a dependency for all that follows. > ********************* > vt8237r.patch (apply at src/southbridge level):: > This uses the CONFIG_EPIA_VT8237R_INIT option to customise SB init for > the EPIA-N > The main differences between the EPIA-N init and what is already there > is that the Via C3 CPU uses the secondary APIC bus rather than FSB for > IOAPIC to LAPIC comms. res->base = VT8237R_APIC_BASE; res->size = 256; - res->limit = 0xffffffffUL; + res->limit = res->base + res->size - 1; + res->align = 8; + res->gran = 8; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; The limit should be 0xffffffff for mem resources unless they are 64 bit. - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Why did you want to remove this reserved region? It just makes it so that allocations have to be above 0x1000. It doesn't affect other fixed regions. > > There are a few other EPIA MoBo specific tweaks in there too. > > This is a dependency for all that follows > ********************* > cn400.patch (apply at src/northbridge level):: > Fixes for Vlink, RAM, Performance and Video > > This is a dependency for all that follows. > ********************* > epia-n.patch (apply at src/motherboard level):: > Adds ACPI/APIC Support to EPIA-N > irq_tables.c is chaged to one generated from an earlier version of > getpir in reponse to issues raised with other ports on the code header > from newer versions of the tool Why is the compiled dsdt in the tree? It looks like the source is there too. > I have tried to keep any whitespace/comment only changes to a minimum. I'd appreciate it if you'd remove any white space at the end of lines. You should be able to use find/replace in the patches. Search for + at the beginning of the line with whitespace at the end. in vi: /^+.*[\t ][\t ]*$ Thanks, Myles From mylesgw at gmail.com Mon Aug 10 17:33:18 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 10 Aug 2009 09:33:18 -0600 Subject: [coreboot] [patch] Fix CONFIG_GFXUMA in mtrr.c In-Reply-To: References: Message-ID: > The code between #if and #endif is only about UMA mode. The > CONFIG_GFXUMA should be 1. > We have another mode called side port mode. It is When the CONFIG_GFXUMA > is 0. > > Signed-off-by: Zheng Bao Acked-by: Myles Watson Thanks, Myles From peter at stuge.se Mon Aug 10 17:56:50 2009 From: peter at stuge.se (Peter Stuge) Date: Mon, 10 Aug 2009 17:56:50 +0200 Subject: [coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R In-Reply-To: <8A8FC8AE80F84C68A4F21717AFCA53DC@chimp> References: <8E520A5E7FB8D647BFDA039F6031C1C605B00E2C@desmdswms201.des.grplnk.net> <8A8FC8AE80F84C68A4F21717AFCA53DC@chimp> Message-ID: <20090810155650.25114.qmail@stuge.se> Myles Watson wrote: > > I have tried to keep any whitespace/comment only changes to a > > minimum. > > I'd appreciate it if you'd remove any white space at the end of > lines. You should be able to use find/replace in the patches. Since I guess Jon is on holiday now, what do you say about just applying his patches and then change the stuff you commented on right afterwards? //Peter From mylesgw at gmail.com Mon Aug 10 17:59:59 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 10 Aug 2009 09:59:59 -0600 Subject: [coreboot] ASUS KFN4D16 - K8 FAM10 In-Reply-To: <4A7B0532.4050308@yahoo.co.uk> References: <985851.32063.qm@web26106.mail.ukl.yahoo.com> <4A7B0532.4050308@yahoo.co.uk> Message-ID: > 1. > I can report that flashrom v0.9.0-r670 works with KFN4-D16 > I flashed an ASUS ROM (3.02) and halted the computer and rebooted, > computer booted up as normal. > > Should I formally inform someone so that the documentation can be updated > to reflect the fact that flashwom works with this board? If no one picks it up from this mail, you can send an email to the flashrom list and they'll update it. > 2. > I am struggling to configure coreboot for this board based on Myles > Watson's recommendation of using the tyans2892 as a template. > 2.1 > in acpi_tables.c resourcemap.c mptable.c dsdt.dsl there are references to > AMD8131, this board does not have an AMD8131, should I remove these > references? Yes. > > 2.2 in Options.lb > default CONFIG_MAINBOARD_PART_NUMBER="s2892" > default CONFIG_MAINBOARD_VENDOR="Tyan" > default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 > default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 > Do I need to edit? Yes. It won't matter much at first, but you'll want those correct. > 2.3 > in dsdt.dsl there are references to onboard ATI RAGE, this board has an > ES1000 > and to an INTELL NIC, this board has broadcom You'll need to change those as well. > > 2.4 > > in Config.lb > 2.4.1 there are references to 8 DIMMS, this board has 16 > should I add 8 more from 58 to 65? > chip drivers/generic/generic #dimm 1-1-1 > device i2c 57 on end > end I don't know enough about this. > 2.4.2 > the SMBUS has ADT7463A and WINBOND monitors, do I need to edit this to > reflect the KFN4-DE16?, How do I find out what the KFN4-D16 has > 2.4.3 > Do I just remove the references to AMD8131? Do I replace with anything? Only if the board has something there. Many boards only have one HT link used, which simplifies things. > 2.4.4 > Do I need to add info about the PCI-E to PCI bridge and the ATI ES1000 > VGA? > 02:00.0 PCI bridge: Intel Corporation 6702PXH PCI Express-to-PCI Bridge A > (rev 09) > 04:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5721 > Gigabit Ethernet PCI Express (rev 21) > 05:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5721 > Gigabit Ethernet PCI Express (rev 21) > 06:05.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) You only need to add devices that: 1. Won't be found otherwise 2. Need some specific initialization 3. Are soldered to the mainboard Everything else will be found and initialized automatically. Good luck, Myles From mylesgw at gmail.com Mon Aug 10 18:01:47 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 10 Aug 2009 10:01:47 -0600 Subject: [coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R In-Reply-To: <20090810155650.25114.qmail@stuge.se> References: <8E520A5E7FB8D647BFDA039F6031C1C605B00E2C@desmdswms201.des.grplnk.net><8A8FC8AE80F84C68A4F21717AFCA53DC@chimp> <20090810155650.25114.qmail@stuge.se> Message-ID: <620373A08EF34C6781C8D2F9980A3F70@chimp> > Myles Watson wrote: > > > I have tried to keep any whitespace/comment only changes to a > > > minimum. > > > > I'd appreciate it if you'd remove any white space at the end of > > lines. You should be able to use find/replace in the patches. > > Since I guess Jon is on holiday now, what do you say about just > applying his patches and then change the stuff you commented on > right afterwards? I don't have any problem with someone doing that. Thanks, Myles From rminnich at gmail.com Mon Aug 10 18:17:55 2009 From: rminnich at gmail.com (ron minnich) Date: Mon, 10 Aug 2009 09:17:55 -0700 Subject: [coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R In-Reply-To: <20090810155650.25114.qmail@stuge.se> References: <8E520A5E7FB8D647BFDA039F6031C1C605B00E2C@desmdswms201.des.grplnk.net> <8A8FC8AE80F84C68A4F21717AFCA53DC@chimp> <20090810155650.25114.qmail@stuge.se> Message-ID: <13426df10908100917q790f4e68web39857864bdf59e@mail.gmail.com> On Mon, Aug 10, 2009 at 8:56 AM, Peter Stuge wrote: > Myles Watson wrote: >> > I have tried to keep any whitespace/comment only changes to a >> > minimum. >> >> I'd appreciate it if you'd remove any white space at the end of >> lines. ?You should be able to use find/replace in the patches. > > Since I guess Jon is on holiday now, what do you say about just > applying his patches and then change the stuff you commented on > right afterwards? > Sure, but be sure to make the changes :-) Certainly you want to remove the compiled dsdt. Thanks, this is great news. ron From jaagar at gmail.com Tue Aug 11 03:56:18 2009 From: jaagar at gmail.com (=?EUC-KR?B?wK/Fw7+s?=) Date: Tue, 11 Aug 2009 10:56:18 +0900 Subject: [coreboot] coreboot generated .rom is not bootable. why? Message-ID: I followed instruction from http://www.coreboot.org/AMD_SimNow . All compilation was done with no error. But SimNow not accept my coreboot.rom. The error message is BIOS ROM file is the wrong size for this BSD. Please either point the memdevice to the correct BIOS ROM file, or configure the memdevice to be the correct size. I suposed this error was caused by header mismatch. Generic ROM file has '0xaa 0xbb 0xcc 0xdd' signature at address 0x00000000. But coreboot.rom does not. On real machine which has coreboot.rom flashed, stopped BIOS loading after first access. How do I get a correct coreboot.rom? -------------- next part -------------- An HTML attachment was scrubbed... URL: From mylesgw at gmail.com Tue Aug 11 04:06:15 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 10 Aug 2009 20:06:15 -0600 Subject: [coreboot] coreboot generated .rom is not bootable. why? In-Reply-To: References: Message-ID: <2831fecf0908101906o108544c1lccca0acc0ea8b243@mail.gmail.com> On Mon, Aug 10, 2009 at 7:56 PM, ??? wrote: > I followed instruction from http://www.coreboot.org/AMD_SimNow . > All compilation was done with no error. > But SimNow not accept my coreboot.rom. > > The error message is > > BIOS ROM file is the wrong size for this BSD. The default BIOS size for SimNOW isn't the same as the default size for Coreboot. > Please either point the memdevice to the correct BIOS ROM file, or > configure the memdevice to be the correct size. You can recompile Coreboot to be the same size as the original BIOS, or you can change the parameters of the memdevice. In the same window where you set the name of the file for the BIOS, set the size and the address to 0x100000000-size. For example, for a 512KB Coreboot image, you'll set the size to 0x80000 and the address to 0xfff80000. > I suposed this error was caused by header mismatch. > Generic ROM file has '0xaa 0xbb 0xcc 0xdd' signature at address 0x00000000. > But coreboot.rom does not. > There is no header check for the ROM. It just starts executing the code it finds at 0xfffffff0. > On real machine which has coreboot.rom flashed, stopped BIOS loading after > first access. Which real machine? Which ROM? > How do I get a correct coreboot.rom? Make sure the size of the image is correct, and that the board matches the board you're using. Good luck, Myles -------------- next part -------------- An HTML attachment was scrubbed... URL: From daniel at dmhome.net Tue Aug 11 04:57:21 2009 From: daniel at dmhome.net (Daniel Toussaint) Date: Tue, 11 Aug 2009 10:57:21 +0800 Subject: [coreboot] AMD RS690 TMDS Message-ID: <6cb69d4a0908101957tf4d11eeg5531d68aee71b86b@mail.gmail.com> Dear All, I am working on supporting yet another AMD 690E based board. We have everything working fine, except for the HDMI output. I can't seem to switch to an HDMI or DVI monitor with Xrandr. The RS690 Register programming requirements , page 65 (PCIE inititialization for TMDS) starts explaining the steps to get TMDS working - as far as I can see they are not implemented yet in southbridge/amd/rs690 ? Implemening those steps would bring up HDMI or are there other things that need to be taken care of ? The VBIOS binary is given to me by AMD and has HDMI support, so they say. The ASIC revisision of the chip is A12. Any comments / idea's are more than welcome. Greetings, Daniel Toussaint -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Tue Aug 11 05:18:11 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 11 Aug 2009 05:18:11 +0200 Subject: [coreboot] [v2] r4525 - trunk/coreboot-v2/src/cpu/x86/mtrr Message-ID: Author: zbao Date: 2009-08-11 05:18:11 +0200 (Tue, 11 Aug 2009) New Revision: 4525 Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c Log: The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1. We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0. Signed-off-by: Zheng Bao Acked-by: Myles Watson Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-08-10 15:57:05 UTC (rev 4524) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-08-11 03:18:11 UTC (rev 4525) @@ -418,7 +418,7 @@ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); -#ifdef CONFIG_GFXUMA +#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ // For now we assume the UMA space is at the end of memory if (var_state.hole_startk || var_state.hole_sizek) { printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); From Zheng.Bao at amd.com Tue Aug 11 05:21:23 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Tue, 11 Aug 2009 11:21:23 +0800 Subject: [coreboot] [patch] Fix CONFIG_GFXUMA in mtrr.c In-Reply-To: References: Message-ID: Thanks, Committed to r4525. -----Original Message----- From: Myles Watson [mailto:mylesgw at gmail.com] Sent: Monday, August 10, 2009 11:33 PM To: Bao, Zheng; 'Coreboot' Subject: RE: [coreboot] [patch] Fix CONFIG_GFXUMA in mtrr.c > The code between #if and #endif is only about UMA mode. The > CONFIG_GFXUMA should be 1. > We have another mode called side port mode. It is When the CONFIG_GFXUMA > is 0. > > Signed-off-by: Zheng Bao Acked-by: Myles Watson Thanks, Myles From Cristi.Magherusan at net.utcluj.ro Tue Aug 11 11:25:58 2009 From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan) Date: Tue, 11 Aug 2009 12:25:58 +0300 Subject: [coreboot] mkelfimage with CBFS? In-Reply-To: <13426df10908091501m715a1118le04008af854a124f@mail.gmail.com> References: <1249849624.20255.18.camel@ufo> <20090809203320.23759.qmail@stuge.se> <1249851442.20255.31.camel@ufo> <13426df10908091501m715a1118le04008af854a124f@mail.gmail.com> Message-ID: <1249982758.3640.59.camel@ufo> On Sun, 2009-08-09 at 15:01 -0700, ron minnich wrote: > You should not need mkelfimage, and have not needed it for a long time. > > I'll take a look at those images. > > ron Hello, I just noticed something interesting... The ROM with CBFS with vmlinux included (without using mkelfImage) seems to boot, or at least gets loaded by cbfs. After the VGA BIOS runs, the emulator shows up some kernel messages that appear when hardware discovery is performed (printed over of those of the VGA BIOS) but then it seems to hang, and the CPU is at 100% like in an infinite loop which looks much like a kernel panic. It seems there's smoething wrong in my kernel config, I'll check it again.. Cristi -- Ing. Cristi M?gheru?an, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part URL: From Maximilian.Thuermer at ziti.uni-heidelberg.de Tue Aug 11 16:12:39 2009 From: Maximilian.Thuermer at ziti.uni-heidelberg.de (Maximilian Thuermer) Date: Tue, 11 Aug 2009 16:12:39 +0200 Subject: [coreboot] Tyan S2912[Fam10] HTX problem Message-ID: <4A817C57.3090908@ziti.uni-heidelberg.de> Hi all, I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning. I am not familiar with the PCI subsystem and the procedures of coreboot regarding this matter, but when scanning through the code, I do not even see why the last line is printed out twice whereas the procedure including the printout only gets called once with the specified parameters. Does anyone have an idea where I could start searching for a possible solution to my problem. Thanks for the help in advance, Maximilian Thuermer coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 reexx other core - nodeid: 01 cores: cco0coorr3e -: x::s t: a r- ----t--e-d - { { a { p A A aPPApIIPCiCIIcICiDDI d D =:= = F000o12 u 3 NnNONdODO DDE3EIEI IDDD w = =or =x : 0rroo2o1---mm--Pm-i -ii-cc cs- trr{{r o{aoo c c rc toAoAoPdAedPdIeIePde::C:C:II C I DrDrIr01e e eD v=vv=A P = ii i ddsdc8 t 410 oo 3}}ccc} pp odB-dd----ee-ee -- g-ip na Vccrrtt cccFhhhImmmi!Dii!! r n!8!nd dDooccccpp ccpououuModSSdSdSeeeeRee:t:t:t 0A A A rMrxMrMeDeDecDM0vMvMv SS0 S iRiiRR1d 0 dd 0 7nnnooo1tt tF F0I dI fXxXffoooM0Monn coctcoawd 0.C0.C.i P P0nSiU0SUSk kt 3kiV iVi_fe0pepppprpirxis4isidnvni0nigogigo0 n3 n dm_m 6m iuiaiu04ncncpcr(r0krkonoso no is owodnddgnF ee Iee o1 oDVrppr)pa I aa ttntaDnc ococphihotht! !c!n d Bu teettPetpcccpPpp ppuuo,uo01rSSr SAte SMiM edFAAIdAM!!IMMCDD_D DM S ! ISdR:RRDFF I IXXo0MM0nEE eV ! FFAIPdC IoPCXX:MUPM ne0E UE!!1V CC nw awnongnsnUiUsiBtS o i_PVnVoe enfufr irsiudsnndvikii onokn=onndw o_ u1waunn0pn n(7kok n0rnos 0orto tgrn1t ote F1t ooos rru) s n unudapnop ppo3piottcor trsswiutuodeper:dpkd !ppc! ooi e MVeFFcdIdFIo!X!I rM XDEe sEI o!! D FFIIC o XPCnoXPU nMM Un EEA o!!VdV ePCeCr:ePrs Pisc0UU1i ene VVn t Wra rusniusiiktnokon nfnno woo uunrwnnn kA konPonro rowwns nnnot ao to gtorrse s u n1unpop:potto p raosrstpu_tuepdaeppp!pdo!o irc r teed En FddI !dX=! oM e! FFIIC ng ko PrXXiMMUenEi aE!!tVd b _eCraCfPscPiUdikU vo V=Vine edr_u1rssan0i1ipkon0o(nso7n tw0uuan1n eauppken1r noo) cwow nnomna ptm ooi ornrcs u_ indpfno:piott od ( 0rstps3u drttVdcpkpF!o eoIrD n0E )e eIF=IdDd! X! o1M ! PX: 70 FA dCIP0o ie UMnE e0W!aV C r tri sPnifiUtoo V_rne f iArusndPi kvinosntdo_w aagnun pe( konrs1o: tanw nago tpe1_o rs)a p uapinocppioticdr sti d=uepd: p2! 8 o t1 EFFIdIX! MDV !ID FI CXoPnUM E!VAP eCr: Ps8Ui o1Vn rerusniknoonw unn korn ownno t osru npopotr tsuepdp! o te ddo! ne uIiXnMitE_!f CiPdUvi dVe_rasp(isont augen1k)no wapni cori dn: o0t 2s FpIpDorVtIDe do! n AP d: o0ne2 n irt_efaidbdavicdk_ =a p2(s0t10a7g0e11) ( acpiocmimodn:_ 4f1id 1pFIaDcVkeIdD) o n= 1A0P:7 040 Wait for AP stage 1: ap_apicid = 3 readback = 3010701 common_fid(packed) = 10700 common_fid = 10700 FID Change Node:00, F3xD4: c3310f27 FID Change Node:01, F3xD4: c3310f27 End FIDVIDMSR 0xc0010071 0x00800003 0x30036040 mcp55_num:01 ...WARM RESET... coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 Start other core - nodeid: 01 cores: ccc0o3oorrr x:-xxxs::: ta r-t-----e-d -- { a{ { p AaAPApPIPIiCICcICiIDIDd D= : = = F0o300 uNn12dO DNNE3OOIDD DwEEo IIr=DD k - - ::- 2c3o1}d}r-c--P-r-m-m si o i {ctc{c{ o rar rod oAcAtceAP:PoPeoddI IdICeCe:CrIeI:I: 0 DvD D r1r =i=eAe= v d vP iniscc -cc }r o e o t - --p-ooB--e-a-ddee c tFmmmiciia! t oocc cIchDhcccrV!rrp! ScD fo oooeccdpddptMeASueeu:S:MRS: e e D rM0rtrteAeSxeAvMvMvRc0 D D iM0iMidSddS1 R R0 nd nn 0oo7oot1ttn ef0 fFodxoI !0d.i. t un0inE8ndned. gcnoodpd 0 C0S_SikfkSnP0iU3iikiit dppp_0Vvppifxeiipnini3rdgs_ngd0 v0 isg tmi3moinmaid60_c igcre4srucrno20toc aokc oao !:t e2dweieen c E an pipadppdoatrt:ai Fcc c tc0Iihnh!o!h3Dd I s upuSoRcucppM1pcupS 1SRSR Ser eStet0txeAtAdcMAMD!0DMDM 0MMS 0 0R F I7X1M E0F!x d0dI oC0oXM8Pnne0UeE! 0V kssoe0iinr3PnUiis 0ttiVox__fen3fiir 0d0dsuv0vinik3iondn0d_ _o0acuawpn np(( :epp ottrmaca wngpgn oe5e1ot15)_r ) n s aaunupppmotipi: 0cocis1irdtud te do!8cr 11 MVIFFFI!II XDDV oneEIDD!F I oCoXMnPnE U A!A P PV:eC: rP 8csU 11iV te r suinoknno uwnn knoor wnn otor sunpotpo rsutpedpo!r n d d! o Fe IXinMEi!t_ fCPidUv Vied_rssitaogn e2u nkapniowcnid o:r 0 2no t supported! done init_fidvid_ap(stage1) apicid: 41 FIDVID on AP: 41 fill_mem_ctrl() enable_smbus() raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 00000000 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000050 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000051 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000052 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000053 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00008003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00008000 AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000001 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000054 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000055 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000056 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000057 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 0001a003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 0001a000 AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000002 mctAutoInitMCT_D: mct_init Node 00000003 mctAutoInitMCT_D: mct_init Node 00000004 mctAutoInitMCT_D: mct_init Node 00000005 mctAutoInitMCT_D: mct_init Node 00000006 mctAutoInitMCT_D: mct_init Node 00000007 mctAutoInitMCT_D: SyncDCTsReady_D mct_SyncDCTsReady: Node 00000000 mct_SyncDCTsReady: DramEnabled mct_SyncDCTsReady: Node 00000001 mct_SyncDCTsReady: DramEnabled mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: ffffff BottomIO: e00000 Node: 01 base: 1200000 limit: 21fffff BottomIO: e00000 Copy dram map from Node 0 to Node 01 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:00e00000 CPUMemTyping: Bottom32bIO:00e00000 CPUMemTyping: Bottom40bIO:02200000 mctAutoInitMCT_D: DQSTiming_D DQSTiming_D: mct_BeforeDQSTrain_D: vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: step 2a vErrara350: step 2b vErrara350: step 3 vErrara350: step 4 vErrara350: step 4b vErrara350: step 5 DQSTiming_D: TrainReceiverEn_D FirstPass: TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001107 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001007 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done DQSTiming_D: mct_TrainDQSPos_D TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done DQSTiming_D: mctSetEccDQSRcvrEn_D DQSTiming_D: TrainMaxReadLatency_D DQSTiming_D: mct_EndDQSTraining_D DQSTiming_D: MCTMemClr_D mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 00001107 InterleaveNodes_D: ErrStatus 00000010 InterleaveNodes_D: ErrCode 00000000 InterleaveNodes_D: Done InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00000584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002003 InterleaveChannels_D: Node 00000000 InterleaveChannels_D: Status 00001107 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00012584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002002 InterleaveChannels_D: Node 00000001 InterleaveChannels_D: Status 00001007 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000002 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000003 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000004 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000005 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000006 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000007 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECCInit 0 ECC enabled on node: 00000000 ECC enabled on node: 00000001 ECCInit 1 ECCInit 2 ECCInit 3 mctAutoInitMCT_D: MCTMemClr_D mct_FinalMCT_D: Clr Cl, Wb All Done raminit_amdmct end: *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf18 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing image to RAM. Jumping to image. coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 11:11:04 CEST 2009 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.0 links increase to 8 PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:19.0 links increase to 8 PCI: 00:19.3 siblings=3 CPU: APIC: 04 enabled CPU: APIC: 05 enabled CPU: APIC: 06 enabled CPU: APIC: 07 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0369] enabled next_unitid: 0011 PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [10de/0369] enabled PCI: 00:02.0 [10de/0364] enabled PCI: 00:02.1 [10de/0368] enabled PCI: 00:02.2 [10de/036a] enabled PCI: 00:02.3 [10de/036b] enabled PCI: 00:03.0 [10de/036c] enabled PCI: 00:03.1 [10de/036d] enabled PCI: 00:05.0 [10de/036e] enabled PCI: 00:06.0 [10de/037f] enabled PCI: 00:06.1 [10de/037f] enabled PCI: 00:06.2 [10de/037f] enabled PCI: 00:07.0 [10de/0370] enabled PCI: 00:07.1 [10de/0371] disabled PCI: 00:09.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0373] enabled PCI: 00:0b.0 [10de/0376] enabled PCI: 00:0e.0 [10de/0378] enabled PCI: 00:10.0 [10de/0377] enabled PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled smbus: PCI: 00:02.1[0]->I2C: 01:50 enabled smbus: PCI: 00:02.1[0]->I2C: 01:51 enabled smbus: PCI: 00:02.1[0]->I2C: 01:52 enabled smbus: PCI: 00:02.1[0]->I2C: 01:53 enabled smbus: PCI: 00:02.1[0]->I2C: 01:54 enabled smbus: PCI: 00:02.1[0]->I2C: 01:55 enabled smbus: PCI: 00:02.1[0]->I2C: 01:56 enabled smbus: PCI: 00:02.1[0]->I2C: 01:57 enabled smbus: PCI: 00:02.1[1]->I2C: 02:51 enabled PCI: pci_scan_bus for bus 01 PCI: 01:04.0 [1002/515e] enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004 From rminnich at gmail.com Tue Aug 11 16:23:42 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 11 Aug 2009 07:23:42 -0700 Subject: [coreboot] 10th anniversary celebration? In-Reply-To: <4A7F4D7D.7020303@gmx.net> References: <4A7F4D7D.7020303@gmx.net> Message-ID: <13426df10908110723t3f4b1638q9990b095d4a831e6@mail.gmail.com> I wanted to come to germany for something but it seems my sched is going to make that impossible. We may have to do something in the Bay Area as well. Hoist a beer to our european friends I suppose. ron From mylesgw at gmail.com Tue Aug 11 16:42:13 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 11 Aug 2009 08:42:13 -0600 Subject: [coreboot] Tyan S2912[Fam10] HTX problem In-Reply-To: <4A817C57.3090908@ziti.uni-heidelberg.de> References: <4A817C57.3090908@ziti.uni-heidelberg.de> Message-ID: > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Maximilian Thuermer > Sent: Tuesday, August 11, 2009 8:13 AM > To: coreboot at coreboot.org > Subject: [coreboot] Tyan S2912[Fam10] HTX problem > > Hi all, > > I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 > System. > I tried both Barcelona and Shanghai CPUs and both system setups ended > booting > during PCI scanning. > I am not familiar with the PCI subsystem and the procedures of coreboot > regarding > this matter, but when scanning through the code, I do not even see why > the last > line is printed out twice whereas the procedure including the printout > only gets called > once with the specified parameters. Does anyone have an idea where I > could start > searching for a possible solution to my problem. I would print out the path to each bridge in the scan to see where it's getting stuck. You can get that with dev_path(bus->dev). It looks pretty normal up to that point. It looks like it found your chipset, 2 cpus, and a graphics card before it died. If that doesn't help you track it down, an lspci would be helpful with the information of which bridge it gets stuck scanning. The values of the Configuration Map registers 0xE0-EC might also help you track down where the PCI requests are being routed. > PCI: pci_scan_bus returning with max=004 > PCI: pci_scan_bus returning with max=004 I can't tell why it's printed twice either. Good luck, Myles From fishbaoz at hotmail.com Tue Aug 11 16:51:02 2009 From: fishbaoz at hotmail.com (Zheng Bao) Date: Tue, 11 Aug 2009 14:51:02 +0000 Subject: [coreboot] Tyan S2912[Fam10] HTX problem In-Reply-To: <4A817C57.3090908@ziti.uni-heidelberg.de> References: <4A817C57.3090908@ziti.uni-heidelberg.de> Message-ID: It seems that the chipset is nVidia nVidia Corporation MCP55 . > Date: Tue, 11 Aug 2009 16:12:39 +0200 > From: Maximilian.Thuermer at ziti.uni-heidelberg.de > To: coreboot at coreboot.org > Subject: [coreboot] Tyan S2912[Fam10] HTX problem > > Hi all, > > I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. > I tried both Barcelona and Shanghai CPUs and both system setups ended > booting > during PCI scanning. > I am not familiar with the PCI subsystem and the procedures of coreboot > regarding > this matter, but when scanning through the code, I do not even see why > the last > line is printed out twice whereas the procedure including the printout > only gets called > once with the specified parameters. Does anyone have an idea where I > could start > searching for a possible solution to my problem. > > Thanks for the help in advance, > > Maximilian Thuermer > > > > coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 > starting... > > BSP Family_Model: 00100f42 > *sysinfo range: [000cc000,000cdfa0] > bsp_apicid = 00 > cpu_init_detectedx = 00000000 > microcode: rev id not found. Skipping microcode patch! > cpuSetAMDMSR done > Enter amd_ht_init() > AMD_CB_EventNotify() > event class: 05 > event: 1004 > data: 04 00 00 01 > AMD_CB_ManualBUIDSwapList() > AMD_CB_EventNotify() > event class: 05 > event: 2006 > data: 04 00 02 ff > Exit amd_ht_init() > cpuSetAMDPCI 00 > On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, > link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e > cpuSetAMDPCI 01 > On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, > link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e > Prep FID/VID Node:00 > F3x80: e600a681 > F3x84: a0e641e6 > F3xD4: c3310f24 > F3xD8: 03000916 > F3xDC: 00005334 > Prep FID/VID Node:01 > F3x80: e600a681 > F3x84: a0e641e6 > F3xD4: c3310f24 > F3xD8: 03000916 > F3xDC: 00005334 > setup_remote_node: 01 done > Start node 01 done. > Wait all core0s started > Core0 started on node: 01 > Wait all core0s started done > start_other_cores() > init node: 00 cores: 03 > Start other core - nodeid: 00 cores: 03 > init node: 01 cores: 03 > reexx other core - nodeid: 01 cores: cco0coorr3e > -: x::s t: a r- ----t--e-d - { { a { p A A > aPPApIIPCiCIIcICiDDI d D =:= = F000o12 u 3 NnNONdODO DDE3EIEI IDDD w = > =or =x > : > > > 0rroo2o1---mm--Pm-i -ii-cc cs- trr{{r o{aoo c c rc > toAoAoPdAedPdIeIePde::C:C:II C I DrDrIr01e e eD v=vv=A P = ii i > ddsdc8 t 410 > oo 3}}ccc} > pp odB-dd----ee-ee -- g-ip > > na > Vccrrtt cccFhhhImmmi!Dii!! > > r > n!8!nd dDooccccpp ccpououuModSSdSdSeeeeRee:t:t:t 0A A A > rMrxMrMeDeDecDM0vMvMv SS0 S iRiiRR1d 0 dd 0 7nnnooo1tt tF F0I dI > fXxXffoooM0Monn > coctcoawd 0.C0.C.i P P0nSiU0SUSk kt 3kiV > iVi_fe0pepppprpirxis4isidnvni0nigogigo0 n3 n dm_m 6m > iuiaiu04ncncpcr(r0krkonoso no > is owodnddgnF ee Iee o1 oDVrppr)pa I aa ttntaDnc ococphihotht! !c!n > d > Bu > teettPetpcccpPpp ppuuo,uo01rSSr SAte > SMiM edFAAIdAM!!IMMCDD_D DM > S > ! ISdR:RRDFF I IXXo0MM0nEE > eV ! FFAIPdC IoPCXX:MUPM ne0E UE!!1V > CC > nw awnongnsnUiUsiBtS o i_PVnVoe enfufr irsiudsnndvikii onokn=onndw o_ > u1waunn0pn n(7kok n0rnos 0orto > tgrn1t ote F1t ooos rru) s n unudapnop ppo3piottcor > trsswiutuodeper:dpkd !ppc! ooi > e > > MVeFFcdIdFIo!X!I rM XDEe > sEI > o!! D FFIIC o XPCnoXPU nMM Un EEA o!!VdV ePCeCr:ePrs Pisc0UU1i > ene VVn > t Wra rusniusiiktnokon nfnno woo uunrwnnn kA konPonro rowwns nnnot > ao to gtorrse s u n1unpop:potto p raosrstpu_tuepdaeppp!pdo!o irc r > teed > En FddI !dX=! oM > e! > > FFIIC > ng ko PrXXiMMUenEi aE!!tVd b _eCraCfPscPiUdikU vo V=Vine > edr_u1rssan0i1ipkon0o(nso7n tw0uuan1n > eauppken1r noo) cwow nnomna ptm ooi ornrcs u_ indpfno:piott od ( > 0rstps3u > drttVdcpkpF!o eoIrD > n0E )e eIF=IdDd! X! o1M > ! > PX: 70 FA dCIP0o > ie UMnE e0W!aV > C > r tri sPnifiUtoo V_rne f iArusndPi kvinosntdo_w aagnun pe( konrs1o: > tanw nago tpe1_o rs)a p uapinocppioticdr sti d=uepd: p2! 8 o > t1 > > EFFIdIX! MDV > !ID FI CXoPnUM E!VAP eCr: Ps8Ui o1Vn > rerusniknoonw unn korn ownno t osru npopotr tsuepdp! o > te ddo! ne > > uIiXnMitE_!f CiPdUvi dVe_rasp(isont augen1k)no wapni cori dn: o0t 2s > FpIpDorVtIDe do! n > AP d: o0ne2 > > n irt_efaidbdavicdk_ =a p2(s0t10a7g0e11) > ( acpiocmimodn:_ 4f1id > 1pFIaDcVkeIdD) o n= 1A0P:7 040 > > Wait for AP stage 1: ap_apicid = 3 > readback = 3010701 > common_fid(packed) = 10700 > common_fid = 10700 > FID Change Node:00, F3xD4: c3310f27 > FID Change Node:01, F3xD4: c3310f27 > End FIDVIDMSR 0xc0010071 0x00800003 0x30036040 > mcp55_num:01 > ...WARM RESET... > > > > > coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 > starting... > > BSP Family_Model: 00100f42 > *sysinfo range: [000cc000,000cdfa0] > bsp_apicid = 00 > cpu_init_detectedx = 00000000 > microcode: rev id not found. Skipping microcode patch! > cpuSetAMDMSR done > Enter amd_ht_init() > AMD_CB_EventNotify() > event class: 05 > event: 1004 > data: 04 00 00 01 > AMD_CB_ManualBUIDSwapList() > AMD_CB_EventNotify() > event class: 05 > event: 2006 > data: 04 00 02 ff > Exit amd_ht_init() > cpuSetAMDPCI 00 > On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, > link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e > cpuSetAMDPCI 01 > On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, > link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e > Prep FID/VID Node:00 > F3x80: e600a681 > F3x84: a0e641e6 > F3xD4: c3310f27 > F3xD8: 03000916 > F3xDC: 00005334 > Prep FID/VID Node:01 > F3x80: e600a681 > F3x84: a0e641e6 > F3xD4: c3310f27 > F3xD8: 03000916 > F3xDC: 00005334 > setup_remote_node: 01 done > Start node 01 done. > Wait all core0s started > Core0 started on node: 01 > Wait all core0s started done > start_other_cores() > init node: 00 cores: 03 > Start other core - nodeid: 00 cores: 03 > init node: 01 cores: 03 > Start other core - nodeid: 01 cores: ccc0o3oorrr > x:-xxxs::: ta r-t-----e-d -- { a{ { p > AaAPApPIPIiCICcICiIDIDd D= : = = F0o300 uNn12dO DNNE3OOIDD DwEEo > IIr=DD k - > - > ::- > > 2c3o1}d}r-c--P-r-m-m si o i {ctc{c{ o rar rod > oAcAtceAP:PoPeoddI IdICeCe:CrIeI:I: 0 DvD D r1r =i=eAe= v d vP iniscc > -cc }r o e o > t - --p-ooB--e-a-ddee > c > > tFmmmiciia! t > oocc cIchDhcccrV!rrp! > ScD > fo oooeccdpddptMeASueeu:S:MRS: e e D rM0rtrteAeSxeAvMvMvRc0 D D > iM0iMidSddS1 R R0 nd nn 0oo7oot1ttn ef0 fFodxoI > !0d.i. t un0inE8ndned. > gcnoodpd 0 C0S_SikfkSnP0iU3iikiit dppp_0Vvppifxeiipnini3rdgs_ngd0 v0 > isg tmi3moinmaid60_c igcre4srucrno20toc aokc oao > !:t e2dweieen c E an pipadppdoatrt:ai Fcc c tc0Iihnh!o!h3Dd > > I > s > upuSoRcucppM1pcupS > 1SRSR Ser eStet0txeAtAdcMAMD!0DMDM 0MMS > 0 0R F I7X1M E0F!x d0dI oC0oXM8Pnne0UeE! > 0V > kssoe0iinr3PnUiis 0ttiVox__fen3fiir 0d0dsuv0vinik3iondn0d_ _o0acuawpn np(( > :epp ottrmaca wngpgn oe5e1ot15)_r ) n s aaunupppmotipi: 0cocis1irdtud > te do!8cr 11 > > > MVIFFFI!II XDDV > oneEIDD!F I oCoXMnPnE U A!A P PV:eC: rP 8csU 11iV > > te r suinoknno uwnn knoor wnn otor sunpotpo rsutpedpo!r > n d d! o > Fe > IXinMEi!t_ fCPidUv Vied_rssitaogn e2u nkapniowcnid o:r 0 2no > t supported! > done > init_fidvid_ap(stage1) apicid: 41 > FIDVID on AP: 41 > fill_mem_ctrl() > enable_smbus() > raminit_amdmct() > raminit_amdmct begin: > mctAutoInitMCT_D: mct_init Node 00000000 > mctAutoInitMCT_D: clear_legacy_Mode > mctAutoInitMCT_D: mct_InitialMCT_D > mct_InitialMCT_D: Set Cl, Wb > mctAutoInitMCT_D: mctSMBhub_Init > mctAutoInitMCT_D: mct_initDCT > mct_initDCT: DCTInit_D 0 > DIMMPresence: i=00000000 > DIMMPresence: smbaddr=00000050 > DIMMPresence: i=00000001 > DIMMPresence: smbaddr=00000051 > DIMMPresence: i=00000002 > DIMMPresence: smbaddr=00000052 > DIMMPresence: i=00000003 > DIMMPresence: smbaddr=00000053 > DIMMPresence: i=00000004 > DIMMPresence: smbaddr=00000000 > DIMMPresence: i=00000005 > DIMMPresence: smbaddr=00000000 > DIMMPresence: i=00000006 > DIMMPresence: smbaddr=00000000 > DIMMPresence: i=00000007 > DIMMPresence: smbaddr=00000000 > DIMMPresence: DIMMValid=0000000c > DIMMPresence: DIMMPresent=0000000c > DIMMPresence: RegDIMMPresent=0000000c > DIMMPresence: DimmECCPresent=0000000c > DIMMPresence: DimmPARPresent=0000000c > DIMMPresence: Dimmx4Present=00000000 > DIMMPresence: Dimmx8Present=0000000c > DIMMPresence: Dimmx16Present=00000000 > DIMMPresence: DimmPlPresent=0000000c > DIMMPresence: DimmDRPresent=0000000c > DIMMPresence: DimmQRPresent=00000000 > DIMMPresence: DATAload[0]=00000002 > DIMMPresence: MAload[0]=00000010 > DIMMPresence: MAdimms[0]=00000001 > DIMMPresence: DATAload[1]=00000002 > DIMMPresence: MAload[1]=00000010 > DIMMPresence: MAdimms[1]=00000001 > DIMMPresence: Status 00001007 > DIMMPresence: ErrStatus 00000000 > DIMMPresence: ErrCode 00000000 > DIMMPresence: Done > DCTInit_D: mct_DIMMPresence Done > SPDCalcWidth: Status 00001007 > SPDCalcWidth: ErrStatus 00000010 > SPDCalcWidth: ErrCode 00000000 > SPDCalcWidth: Done > DCTInit_D: mct_SPDCalcWidth Done > SPDGetTCL_D: DIMMCASL 00000003 > SPDGetTCL_D: DIMMAutoSpeed 00000003 > SPDGetTCL_D: Status 00001007 > SPDGetTCL_D: ErrStatus 00000010 > SPDGetTCL_D: ErrCode 00000000 > SPDGetTCL_D: Done > AutoCycTiming: DramTimingLo 0069ca24 > AutoCycTiming: DramTimingHi 01020300 > AutoCycTiming: Status 00001007 > AutoCycTiming: ErrStatus 00000010 > AutoCycTiming: ErrCode 00000000 > AutoCycTiming: Done > DCTInit_D: AutoCycTiming_D Done > AutoConfig_D: DCT: 00000000 > SPDSetBanks: Status 00001007 > SPDSetBanks: ErrStatus 00000010 > SPDSetBanks: ErrCode 00000000 > SPDSetBanks: Done > AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00008003 > AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00008000 > AfterStitch pDCTstat->NodeSysBase = 00000000 > mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff > StitchMemory: Status 00001007 > StitchMemory: ErrStatus 00000010 > StitchMemory: ErrCode 00000000 > StitchMemory: Done > InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 > InterleaveBanks_D: ErrStatus 00000010 > InterleaveBanks_D: ErrCode 00000000 > InterleaveBanks_D: Done > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > DramTimingLo: val=00000006 > DramTimingLo: val=00000004 > DramTimingLo: val=00000002 > DramTimingLo: val=00000000 > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > AutoConfig_D: DramControl: 00000005 > AutoConfig_D: DramTimingLo: ef69ca24 > AutoConfig_D: DramConfigMisc: 00000000 > AutoConfig_D: DramConfigMisc2: 00000002 > AutoConfig_D: DramConfigLo: 00080110 > AutoConfig_D: DramConfigHi: 6f48800a > AutoConfig: Status 00001007 > AutoConfig: ErrStatus 00000010 > AutoConfig: ErrCode 00000000 > AutoConfig: Done > DCTInit_D: AutoConfig_D Done > dct: 00000000 > Speed: 00000003 > CH_ODC_CTL: 20111222 > CH_ADDR_TMG: 00000000 > DCTInit_D: PlatformSpec_D Done > DCTInit_D: StartupDCT_D > StartupDCT_D: MemClkFreqVal > StartupDCT_D: DqsRcvEnTrain set > StartupDCT_D: DramInit > mct_initDCT: DCTInit_D 1 > DCTInit_D: mct_DIMMPresence Done > SPDCalcWidth: Status 00001007 > SPDCalcWidth: ErrStatus 00000010 > SPDCalcWidth: ErrCode 00000000 > SPDCalcWidth: Done > DCTInit_D: mct_SPDCalcWidth Done > AutoCycTiming: DramTimingLo 0069ca24 > AutoCycTiming: DramTimingHi 01020300 > AutoCycTiming: Status 00001007 > AutoCycTiming: ErrStatus 00000010 > AutoCycTiming: ErrCode 00000000 > AutoCycTiming: Done > DCTInit_D: AutoCycTiming_D Done > AutoConfig_D: DCT: 00000001 > SPDSetBanks: Status 00001007 > SPDSetBanks: ErrStatus 00000010 > SPDSetBanks: ErrCode 00000000 > SPDSetBanks: Done > AfterStitch pDCTstat->NodeSysBase = 00000000 > mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe > StitchMemory: Status 00001007 > StitchMemory: ErrStatus 00000010 > StitchMemory: ErrCode 00000000 > StitchMemory: Done > InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 > InterleaveBanks_D: ErrStatus 00000010 > InterleaveBanks_D: ErrCode 00000000 > InterleaveBanks_D: Done > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > DramTimingLo: val=00000006 > DramTimingLo: val=00000004 > DramTimingLo: val=00000002 > DramTimingLo: val=00000000 > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > AutoConfig_D: DramControl: 00000005 > AutoConfig_D: DramTimingLo: ef69ca24 > AutoConfig_D: DramConfigMisc: 00000000 > AutoConfig_D: DramConfigMisc2: 00000002 > AutoConfig_D: DramConfigLo: 00080110 > AutoConfig_D: DramConfigHi: 6f48800a > AutoConfig: Status 00001007 > AutoConfig: ErrStatus 00000010 > AutoConfig: ErrCode 00000000 > AutoConfig: Done > DCTInit_D: AutoConfig_D Done > dct: 00000001 > Speed: 00000003 > CH_ODC_CTL: 20111222 > CH_ADDR_TMG: 00000000 > DCTInit_D: PlatformSpec_D Done > DCTInit_D: StartupDCT_D > StartupDCT_D: MemClkFreqVal > StartupDCT_D: DqsRcvEnTrain set > StartupDCT_D: DramInit > mctAutoInitMCT_D: mct_init Node 00000001 > mctAutoInitMCT_D: clear_legacy_Mode > mctAutoInitMCT_D: mct_InitialMCT_D > mct_InitialMCT_D: Set Cl, Wb > mctAutoInitMCT_D: mctSMBhub_Init > mctAutoInitMCT_D: mct_initDCT > mct_initDCT: DCTInit_D 0 > DIMMPresence: i=00000000 > DIMMPresence: smbaddr=00000054 > DIMMPresence: i=00000001 > DIMMPresence: smbaddr=00000055 > DIMMPresence: i=00000002 > DIMMPresence: smbaddr=00000056 > DIMMPresence: i=00000003 > DIMMPresence: smbaddr=00000057 > DIMMPresence: i=00000004 > DIMMPresence: smbaddr=00000000 > DIMMPresence: i=00000005 > DIMMPresence: smbaddr=00000000 > DIMMPresence: i=00000006 > DIMMPresence: smbaddr=00000000 > DIMMPresence: i=00000007 > DIMMPresence: smbaddr=00000000 > DIMMPresence: DIMMValid=0000000c > DIMMPresence: DIMMPresent=0000000c > DIMMPresence: RegDIMMPresent=0000000c > DIMMPresence: DimmECCPresent=0000000c > DIMMPresence: DimmPARPresent=0000000c > DIMMPresence: Dimmx4Present=00000000 > DIMMPresence: Dimmx8Present=0000000c > DIMMPresence: Dimmx16Present=00000000 > DIMMPresence: DimmPlPresent=0000000c > DIMMPresence: DimmDRPresent=0000000c > DIMMPresence: DimmQRPresent=00000000 > DIMMPresence: DATAload[0]=00000002 > DIMMPresence: MAload[0]=00000010 > DIMMPresence: MAdimms[0]=00000001 > DIMMPresence: DATAload[1]=00000002 > DIMMPresence: MAload[1]=00000010 > DIMMPresence: MAdimms[1]=00000001 > DIMMPresence: Status 00001007 > DIMMPresence: ErrStatus 00000000 > DIMMPresence: ErrCode 00000000 > DIMMPresence: Done > DCTInit_D: mct_DIMMPresence Done > SPDCalcWidth: Status 00001007 > SPDCalcWidth: ErrStatus 00000010 > SPDCalcWidth: ErrCode 00000000 > SPDCalcWidth: Done > DCTInit_D: mct_SPDCalcWidth Done > SPDGetTCL_D: DIMMCASL 00000003 > SPDGetTCL_D: DIMMAutoSpeed 00000003 > SPDGetTCL_D: Status 00001007 > SPDGetTCL_D: ErrStatus 00000010 > SPDGetTCL_D: ErrCode 00000000 > SPDGetTCL_D: Done > AutoCycTiming: DramTimingLo 0069ca24 > AutoCycTiming: DramTimingHi 01020300 > AutoCycTiming: Status 00001007 > AutoCycTiming: ErrStatus 00000010 > AutoCycTiming: ErrCode 00000000 > AutoCycTiming: Done > DCTInit_D: AutoCycTiming_D Done > AutoConfig_D: DCT: 00000000 > SPDSetBanks: Status 00001007 > SPDSetBanks: ErrStatus 00000010 > SPDSetBanks: ErrCode 00000000 > SPDSetBanks: Done > AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 0001a003 > AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 0001a000 > AfterStitch pDCTstat->NodeSysBase = 01000000 > mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff > StitchMemory: Status 00001007 > StitchMemory: ErrStatus 00000010 > StitchMemory: ErrCode 00000000 > StitchMemory: Done > InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 > InterleaveBanks_D: ErrStatus 00000010 > InterleaveBanks_D: ErrCode 00000000 > InterleaveBanks_D: Done > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > DramTimingLo: val=00000006 > DramTimingLo: val=00000004 > DramTimingLo: val=00000002 > DramTimingLo: val=00000000 > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > AutoConfig_D: DramControl: 00000005 > AutoConfig_D: DramTimingLo: ef69ca24 > AutoConfig_D: DramConfigMisc: 00000000 > AutoConfig_D: DramConfigMisc2: 00000002 > AutoConfig_D: DramConfigLo: 00080110 > AutoConfig_D: DramConfigHi: 6f48800a > AutoConfig: Status 00001007 > AutoConfig: ErrStatus 00000010 > AutoConfig: ErrCode 00000000 > AutoConfig: Done > DCTInit_D: AutoConfig_D Done > dct: 00000000 > Speed: 00000003 > CH_ODC_CTL: 20111222 > CH_ADDR_TMG: 00000000 > DCTInit_D: PlatformSpec_D Done > DCTInit_D: StartupDCT_D > StartupDCT_D: MemClkFreqVal > StartupDCT_D: DqsRcvEnTrain set > StartupDCT_D: DramInit > mct_initDCT: DCTInit_D 1 > DCTInit_D: mct_DIMMPresence Done > SPDCalcWidth: Status 00001007 > SPDCalcWidth: ErrStatus 00000010 > SPDCalcWidth: ErrCode 00000000 > SPDCalcWidth: Done > DCTInit_D: mct_SPDCalcWidth Done > AutoCycTiming: DramTimingLo 0069ca24 > AutoCycTiming: DramTimingHi 01020300 > AutoCycTiming: Status 00001007 > AutoCycTiming: ErrStatus 00000010 > AutoCycTiming: ErrCode 00000000 > AutoCycTiming: Done > DCTInit_D: AutoCycTiming_D Done > AutoConfig_D: DCT: 00000001 > SPDSetBanks: Status 00001007 > SPDSetBanks: ErrStatus 00000010 > SPDSetBanks: ErrCode 00000000 > SPDSetBanks: Done > AfterStitch pDCTstat->NodeSysBase = 01000000 > mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe > StitchMemory: Status 00001007 > StitchMemory: ErrStatus 00000010 > StitchMemory: ErrCode 00000000 > StitchMemory: Done > InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 > InterleaveBanks_D: ErrStatus 00000010 > InterleaveBanks_D: ErrCode 00000000 > InterleaveBanks_D: Done > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > DramTimingLo: val=00000006 > DramTimingLo: val=00000004 > DramTimingLo: val=00000002 > DramTimingLo: val=00000000 > DramTimingLo: val=00000008 > DramTimingLo: val=00000008 > AutoConfig_D: DramControl: 00000005 > AutoConfig_D: DramTimingLo: ef69ca24 > AutoConfig_D: DramConfigMisc: 00000000 > AutoConfig_D: DramConfigMisc2: 00000002 > AutoConfig_D: DramConfigLo: 00080110 > AutoConfig_D: DramConfigHi: 6f48800a > AutoConfig: Status 00001007 > AutoConfig: ErrStatus 00000010 > AutoConfig: ErrCode 00000000 > AutoConfig: Done > DCTInit_D: AutoConfig_D Done > dct: 00000001 > Speed: 00000003 > CH_ODC_CTL: 20111222 > CH_ADDR_TMG: 00000000 > DCTInit_D: PlatformSpec_D Done > DCTInit_D: StartupDCT_D > StartupDCT_D: MemClkFreqVal > StartupDCT_D: DqsRcvEnTrain set > StartupDCT_D: DramInit > mctAutoInitMCT_D: mct_init Node 00000002 > mctAutoInitMCT_D: mct_init Node 00000003 > mctAutoInitMCT_D: mct_init Node 00000004 > mctAutoInitMCT_D: mct_init Node 00000005 > mctAutoInitMCT_D: mct_init Node 00000006 > mctAutoInitMCT_D: mct_init Node 00000007 > mctAutoInitMCT_D: SyncDCTsReady_D > mct_SyncDCTsReady: Node 00000000 > mct_SyncDCTsReady: DramEnabled > mct_SyncDCTsReady: Node 00000001 > mct_SyncDCTsReady: DramEnabled > mctAutoInitMCT_D: HTMemMapInit_D > Node: 00 base: 00 limit: ffffff BottomIO: e00000 > Node: 01 base: 1200000 limit: 21fffff BottomIO: e00000 > Copy dram map from Node 0 to Node 01 > mctAutoInitMCT_D: CPUMemTyping_D > CPUMemTyping: Cache32bTOP:00e00000 > CPUMemTyping: Bottom32bIO:00e00000 > CPUMemTyping: Bottom40bIO:02200000 > mctAutoInitMCT_D: DQSTiming_D > DQSTiming_D: mct_BeforeDQSTrain_D: > vErrara350: dummy read > vErrara350: dummy read > vErrara350: dummy read > vErrara350: dummy read > vErrara350: dummy read > vErrara350: dummy read > vErrara350: dummy read > vErrara350: dummy read > vErrara350: step 2a > vErrara350: step 2b > vErrara350: step 3 > vErrara350: step 4 > vErrara350: step 4b > vErrara350: step 5 > DQSTiming_D: TrainReceiverEn_D FirstPass: > TrainRcvrEn: 1 > TrainRcvrEn: 2 > TrainRcvrEn: 3 > TrainRcvrEn: 4 > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > TrainRcvrEn: mct_DisableDQSRcvEn_D > TrainRcvrEn: Status 00001107 > TrainRcvrEn: ErrStatus 00000010 > TrainRcvrEn: ErrCode 00000000 > TrainRcvrEn: Done > TrainRcvrEn: 1 > TrainRcvrEn: 2 > TrainRcvrEn: 3 > TrainRcvrEn: 4 > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > Rank not enabled_D > TrainRcvrEn: mct_DisableDQSRcvEn_D > TrainRcvrEn: Status 00001007 > TrainRcvrEn: ErrStatus 00000010 > TrainRcvrEn: ErrCode 00000000 > TrainRcvrEn: Done > DQSTiming_D: mct_TrainDQSPos_D > TrainDQSRdWrPos: Status 00001107 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > TrainDQSRdWrPos: Status 00001107 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > TrainDQSRdWrPos: Status 00001107 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > TrainDQSRdWrPos: Status 00001107 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > TrainDQSRdWrPos: Status 00001007 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > TrainDQSRdWrPos: Status 00001007 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > TrainDQSRdWrPos: Status 00001007 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > TrainDQSRdWrPos: Status 00001007 > TrainDQSRdWrPos: TrainErrors 00000000 > TrainDQSRdWrPos: ErrStatus 00000010 > TrainDQSRdWrPos: ErrCode 00000000 > TrainDQSRdWrPos: Done > DQSTiming_D: mctSetEccDQSRcvrEn_D > DQSTiming_D: TrainMaxReadLatency_D > DQSTiming_D: mct_EndDQSTraining_D > DQSTiming_D: MCTMemClr_D > mctAutoInitMCT_D: UMAMemTyping_D > mctAutoInitMCT_D: :OtherTiming > InterleaveNodes_D: Status 00001107 > InterleaveNodes_D: ErrStatus 00000010 > InterleaveNodes_D: ErrCode 00000000 > InterleaveNodes_D: Done > InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00000584 > InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002003 > InterleaveChannels_D: Node 00000000 > InterleaveChannels_D: Status 00001107 > InterleaveChannels_D: ErrStatus 00000010 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00012584 > InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002002 > InterleaveChannels_D: Node 00000001 > InterleaveChannels_D: Status 00001007 > InterleaveChannels_D: ErrStatus 00000010 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels_D: Node 00000002 > InterleaveChannels_D: Status 00001000 > InterleaveChannels_D: ErrStatus 00000000 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels_D: Node 00000003 > InterleaveChannels_D: Status 00001000 > InterleaveChannels_D: ErrStatus 00000000 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels_D: Node 00000004 > InterleaveChannels_D: Status 00001000 > InterleaveChannels_D: ErrStatus 00000000 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels_D: Node 00000005 > InterleaveChannels_D: Status 00001000 > InterleaveChannels_D: ErrStatus 00000000 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels_D: Node 00000006 > InterleaveChannels_D: Status 00001000 > InterleaveChannels_D: ErrStatus 00000000 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels_D: Node 00000007 > InterleaveChannels_D: Status 00001000 > InterleaveChannels_D: ErrStatus 00000000 > InterleaveChannels_D: ErrCode 00000000 > InterleaveChannels_D: Done > mctAutoInitMCT_D: ECCInit_D > ECCInit 0 > ECC enabled on node: 00000000 > ECC enabled on node: 00000001 > ECCInit 1 > ECCInit 2 > ECCInit 3 > mctAutoInitMCT_D: MCTMemClr_D > mct_FinalMCT_D: Clr Cl, Wb > All Done > raminit_amdmct end: > > *** Yes, the copy/decompress is taking a while, FIXME! > v_esp=000cbf18 > testx = 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... Done > testx = 5a5a5a5a > Disabling cache as ram now > Clearing initial memory region: Done > Uncompressing image to RAM. > Jumping to image. > coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 11:11:04 CEST 2009 booting... > Enumerating buses... > Show all devs...Before Device Enumeration. > Root Device: enabled 1, 0 resources > APIC_CLUSTER: 0: enabled 1, 0 resources > APIC: 00: enabled 1, 0 resources > PCI_DOMAIN: 0000: enabled 1, 0 resources > PCI: 00:18.0: enabled 1, 0 resources > PCI: 00:00.0: enabled 1, 0 resources > PCI: 00:01.0: enabled 1, 0 resources > PNP: 002e.0: enabled 0, 3 resources > PNP: 002e.1: enabled 0, 2 resources > PNP: 002e.2: enabled 1, 2 resources > PNP: 002e.3: enabled 1, 2 resources > PNP: 002e.5: enabled 1, 4 resources > PNP: 002e.6: enabled 0, 1 resources > PNP: 002e.7: enabled 0, 3 resources > PNP: 002e.8: enabled 0, 0 resources > PNP: 002e.9: enabled 0, 0 resources > PNP: 002e.a: enabled 0, 0 resources > PNP: 002e.b: enabled 1, 2 resources > PCI: 00:01.1: enabled 1, 0 resources > I2C: 00:50: enabled 1, 0 resources > I2C: 00:51: enabled 1, 0 resources > I2C: 00:52: enabled 1, 0 resources > I2C: 00:53: enabled 1, 0 resources > I2C: 00:54: enabled 1, 0 resources > I2C: 00:55: enabled 1, 0 resources > I2C: 00:56: enabled 1, 0 resources > I2C: 00:57: enabled 1, 0 resources > I2C: 00:51: enabled 1, 0 resources > PCI: 00:02.0: enabled 1, 0 resources > PCI: 00:02.1: enabled 1, 0 resources > PCI: 00:04.0: enabled 1, 0 resources > PCI: 00:05.0: enabled 1, 0 resources > PCI: 00:05.1: enabled 1, 0 resources > PCI: 00:05.2: enabled 1, 0 resources > PCI: 00:06.0: enabled 1, 0 resources > PCI: 00:04.0: enabled 1, 0 resources > PCI: 00:06.1: enabled 0, 0 resources > PCI: 00:08.0: enabled 1, 0 resources > PCI: 00:09.0: enabled 1, 0 resources > PCI: 00:0a.0: enabled 1, 0 resources > PCI: 00:0b.0: enabled 0, 0 resources > PCI: 00:0c.0: enabled 0, 0 resources > PCI: 00:0d.0: enabled 1, 0 resources > PCI: 00:0e.0: enabled 0, 0 resources > PCI: 00:0f.0: enabled 1, 0 resources > PCI: 00:18.1: enabled 1, 0 resources > PCI: 00:18.2: enabled 1, 0 resources > PCI: 00:18.3: enabled 1, 0 resources > PCI: 00:18.4: enabled 1, 0 resources > Compare with tree... > Root Device: enabled 1, 0 resources > APIC_CLUSTER: 0: enabled 1, 0 resources > APIC: 00: enabled 1, 0 resources > PCI_DOMAIN: 0000: enabled 1, 0 resources > PCI: 00:18.0: enabled 1, 0 resources > PCI: 00:00.0: enabled 1, 0 resources > PCI: 00:01.0: enabled 1, 0 resources > PNP: 002e.0: enabled 0, 3 resources > PNP: 002e.1: enabled 0, 2 resources > PNP: 002e.2: enabled 1, 2 resources > PNP: 002e.3: enabled 1, 2 resources > PNP: 002e.5: enabled 1, 4 resources > PNP: 002e.6: enabled 0, 1 resources > PNP: 002e.7: enabled 0, 3 resources > PNP: 002e.8: enabled 0, 0 resources > PNP: 002e.9: enabled 0, 0 resources > PNP: 002e.a: enabled 0, 0 resources > PNP: 002e.b: enabled 1, 2 resources > PCI: 00:01.1: enabled 1, 0 resources > I2C: 00:50: enabled 1, 0 resources > I2C: 00:51: enabled 1, 0 resources > I2C: 00:52: enabled 1, 0 resources > I2C: 00:53: enabled 1, 0 resources > I2C: 00:54: enabled 1, 0 resources > I2C: 00:55: enabled 1, 0 resources > I2C: 00:56: enabled 1, 0 resources > I2C: 00:57: enabled 1, 0 resources > I2C: 00:51: enabled 1, 0 resources > PCI: 00:02.0: enabled 1, 0 resources > PCI: 00:02.1: enabled 1, 0 resources > PCI: 00:04.0: enabled 1, 0 resources > PCI: 00:05.0: enabled 1, 0 resources > PCI: 00:05.1: enabled 1, 0 resources > PCI: 00:05.2: enabled 1, 0 resources > PCI: 00:06.0: enabled 1, 0 resources > PCI: 00:04.0: enabled 1, 0 resources > PCI: 00:06.1: enabled 0, 0 resources > PCI: 00:08.0: enabled 1, 0 resources > PCI: 00:09.0: enabled 1, 0 resources > PCI: 00:0a.0: enabled 1, 0 resources > PCI: 00:0b.0: enabled 0, 0 resources > PCI: 00:0c.0: enabled 0, 0 resources > PCI: 00:0d.0: enabled 1, 0 resources > PCI: 00:0e.0: enabled 0, 0 resources > PCI: 00:0f.0: enabled 1, 0 resources > PCI: 00:18.1: enabled 1, 0 resources > PCI: 00:18.2: enabled 1, 0 resources > PCI: 00:18.3: enabled 1, 0 resources > PCI: 00:18.4: enabled 1, 0 resources > APIC_CLUSTER: 0 enabled > PCI_DOMAIN: 0000 enabled > PCI: 00:18.0 links increase to 8 > PCI: 00:18.3 siblings=3 > CPU: APIC: 00 enabled > CPU: APIC: 01 enabled > CPU: APIC: 02 enabled > CPU: APIC: 03 enabled > PCI: 00:19.0 [1022/1200] enabled > PCI: 00:19.1 [1022/1201] enabled > PCI: 00:19.2 [1022/1202] enabled > PCI: 00:19.3 [1022/1203] enabled > PCI: 00:19.4 [1022/1204] enabled > PCI: 00:19.0 links increase to 8 > PCI: 00:19.3 siblings=3 > CPU: APIC: 04 enabled > CPU: APIC: 05 enabled > CPU: APIC: 06 enabled > CPU: APIC: 07 enabled > PCI: pci_scan_bus for bus 00 > PCI: 00:18.0 [1022/1200] enabled > PCI: 00:18.1 [1022/1201] enabled > PCI: 00:18.2 [1022/1202] enabled > PCI: 00:18.3 [1022/1203] enabled > PCI: 00:18.4 [1022/1204] enabled > PCI: 00:19.0 [1022/1200] enabled > PCI: 00:19.1 [1022/1201] enabled > PCI: 00:19.2 [1022/1202] enabled > PCI: 00:19.3 [1022/1203] enabled > PCI: 00:19.4 [1022/1204] enabled > PCI: 00:00.0 [10de/0369] enabled > PCI: 00:01.0 [10de/0369] enabled next_unitid: 0011 > PCI: pci_scan_bus for bus 00 > PCI: 00:01.0 [10de/0369] enabled > PCI: 00:02.0 [10de/0364] enabled > PCI: 00:02.1 [10de/0368] enabled > PCI: 00:02.2 [10de/036a] enabled > PCI: 00:02.3 [10de/036b] enabled > PCI: 00:03.0 [10de/036c] enabled > PCI: 00:03.1 [10de/036d] enabled > PCI: 00:05.0 [10de/036e] enabled > PCI: 00:06.0 [10de/037f] enabled > PCI: 00:06.1 [10de/037f] enabled > PCI: 00:06.2 [10de/037f] enabled > PCI: 00:07.0 [10de/0370] enabled > PCI: 00:07.1 [10de/0371] disabled > PCI: 00:09.0 [10de/0373] enabled > PCI: 00:0a.0 [10de/0373] enabled > PCI: 00:0b.0 [10de/0376] enabled > PCI: 00:0e.0 [10de/0378] enabled > PCI: 00:10.0 [10de/0377] enabled > PNP: 002e.0 disabled > PNP: 002e.1 disabled > PNP: 002e.2 enabled > PNP: 002e.3 enabled > PNP: 002e.5 enabled > PNP: 002e.6 disabled > PNP: 002e.7 disabled > PNP: 002e.8 disabled > PNP: 002e.9 disabled > PNP: 002e.a disabled > PNP: 002e.b enabled > smbus: PCI: 00:02.1[0]->I2C: 01:50 enabled > smbus: PCI: 00:02.1[0]->I2C: 01:51 enabled > smbus: PCI: 00:02.1[0]->I2C: 01:52 enabled > smbus: PCI: 00:02.1[0]->I2C: 01:53 enabled > smbus: PCI: 00:02.1[0]->I2C: 01:54 enabled > smbus: PCI: 00:02.1[0]->I2C: 01:55 enabled > smbus: PCI: 00:02.1[0]->I2C: 01:56 enabled > smbus: PCI: 00:02.1[0]->I2C: 01:57 enabled > smbus: PCI: 00:02.1[1]->I2C: 02:51 enabled > PCI: pci_scan_bus for bus 01 > PCI: 01:04.0 [1002/515e] enabled > PCI: pci_scan_bus returning with max=001 > PCI: pci_scan_bus for bus 02 > PCI: pci_scan_bus returning with max=002 > PCI: pci_scan_bus for bus 03 > PCI: pci_scan_bus returning with max=003 > PCI: pci_scan_bus for bus 04 > PCI: pci_scan_bus returning with max=004 > PCI: pci_scan_bus returning with max=004 > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot _________________________________________________________________ Share your memories online with anyone you want. http://www.microsoft.com/middleeast/windows/windowslive/products/photos-share.aspx?tab=1 -------------- next part -------------- An HTML attachment was scrubbed... URL: From ward at gnu.org Tue Aug 11 17:16:10 2009 From: ward at gnu.org (Ward Vandewege) Date: Tue, 11 Aug 2009 11:16:10 -0400 Subject: [coreboot] Tyan S2912[Fam10] HTX problem In-Reply-To: <4A817C57.3090908@ziti.uni-heidelberg.de> References: <4A817C57.3090908@ziti.uni-heidelberg.de> Message-ID: <20090811151610.GA29632@countzero.vandewege.net> Hi Maximilian, On Tue, Aug 11, 2009 at 04:12:39PM +0200, Maximilian Thuermer wrote: > I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. > I tried both Barcelona and Shanghai CPUs and both system setups ended > booting > during PCI scanning. Do you mean *re*booting? I've seen some of that. Are you using gcc 3.x or 4.x to compile, and on 32 or 64 bit? I've found there are issues with gcc 4.3 (even when built with the nice coresystems build-your-own-toolchain script). The most reliable compiler for coreboot in my experience is still gcc 3.4. Also, are you sure your CONFIG_HT_* settings are correct? I found that CONFIG_HT_CHAIN_UNITID_BASE really has to be 1 to get a bootable system with mcp55 on fam10. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator From rminnich at gmail.com Tue Aug 11 17:28:42 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 11 Aug 2009 08:28:42 -0700 Subject: [coreboot] Tyan S2912[Fam10] HTX problem In-Reply-To: <20090811151610.GA29632@countzero.vandewege.net> References: <4A817C57.3090908@ziti.uni-heidelberg.de> <20090811151610.GA29632@countzero.vandewege.net> Message-ID: <13426df10908110828k10066472r36dcd573ed38606@mail.gmail.com> On Tue, Aug 11, 2009 at 8:16 AM, Ward Vandewege wrote: > The most reliable compiler for > coreboot in my experience is still gcc 3.4. This is really getting to be a problem. Is 4.4 any better? Any idea what could have caused the breakage? I think we can trust that gcc is not going to stop changing just for us :-) ron From rminnich at gmail.com Tue Aug 11 17:53:29 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 11 Aug 2009 08:53:29 -0700 Subject: [coreboot] mkelfimage with CBFS? In-Reply-To: <1249982758.3640.59.camel@ufo> References: <1249849624.20255.18.camel@ufo> <20090809203320.23759.qmail@stuge.se> <1249851442.20255.31.camel@ufo> <13426df10908091501m715a1118le04008af854a124f@mail.gmail.com> <1249982758.3640.59.camel@ufo> Message-ID: <13426df10908110853k5f1a30aatceffa855187310e3@mail.gmail.com> On Tue, Aug 11, 2009 at 2:25 AM, Cristi Magherusan wrote: > I just noticed something interesting... The ROM with CBFS with vmlinux > included (without using mkelfImage) seems to boot, or at least gets > loaded by cbfs. we really need to try this on simnow. Try reconfiguring your kernel again and see what goes on. Also, are you trying the experiment of loading the kernel with gpxe/filo/whatever to see if it boots? ron From patrick.georgi at coresystems.de Tue Aug 11 18:15:16 2009 From: patrick.georgi at coresystems.de (Patrick Georgi) Date: Tue, 11 Aug 2009 18:15:16 +0200 Subject: [coreboot] [PATCH]Kconfig for v2 In-Reply-To: <4A79A377.7040403@coresystems.de> References: <4A79A377.7040403@coresystems.de> Message-ID: https://www.coresystems.de/~patrick/20090811-1-kconfig is an updated patch, with some AMD support by Ron. Signed-off-by: Patrick Georgi From daniel at dmhome.net Tue Aug 11 18:32:37 2009 From: daniel at dmhome.net (Daniel Toussaint) Date: Wed, 12 Aug 2009 00:32:37 +0800 Subject: [coreboot] AMD RS690 TMDS In-Reply-To: <312172.30130.qm@web57004.mail.re3.yahoo.com> References: <6cb69d4a0908101957tf4d11eeg5531d68aee71b86b@mail.gmail.com> <312172.30130.qm@web57004.mail.re3.yahoo.com> Message-ID: <6cb69d4a0908110932t4edc2fefs93822d7aa74d2c8c@mail.gmail.com> Hi, I am using the open source drivers , radeon and radeonhd. When I try it on a similar board with AMI bios , xrandr can switch on the HDMI port without any problems - with radeon and radeonhd. I guess I could give Catalyst a try to see if it makes any difference(maybe it does magic with the vga bios) I think however, that the problem lies in the fact that some config needs to be done in PCIE-GFX , so that one of the ports gets configured as TMDS. Right now, I am trying to get that to work - so far no results yet .... Another interesting fact is that I am working with this board that does not have another BIOS except for coreboot .... so I have nothing to compare register values with. Greetings, On Wed, Aug 12, 2009 at 12:08 AM, Dan Lykowski wrote: > Daniel, > I'm sorry I don't know the answer to your issue.. But I have a question? > Are you using the open source driver or Catalyst? Have you tried Catalyst > and does it run? > > Thanks > Dan Lykowski > > ------------------------------ > *From:* Daniel Toussaint > *To:* coreboot at coreboot.org > *Sent:* Mond,ay, August 10, 2009 7:57:21 PM > *Subject:* [coreboot] AMD RS690 TMDS > > Dear All, > > I am working on supporting yet another AMD 690E based board. We have > everything working fine, except for the HDMI output. I can't seem to switch > to an HDMI or DVI monitor with Xrandr. > The RS690 Register programming requirements , page 65 (PCIE > inititialization for TMDS) starts explaining the steps to get TMDS working - > as far as I can see they are not implemented yet in southbridge/amd/rs690 ? > Implemening those steps would bring up HDMI or are there other things that > need to be taken care of ? The VBIOS binary is given to me by AMD and has > HDMI support, so they say. > The ASIC revisision of the chip is A12. Any comments / idea's are more than > welcome. > > Greetings, > > Daniel Toussaint > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From tomwardathome at yahoo.co.uk Tue Aug 11 19:17:04 2009 From: tomwardathome at yahoo.co.uk (thomas ward) Date: Tue, 11 Aug 2009 17:17:04 +0000 (GMT) Subject: [coreboot] ASUS KFN4D16 - K8 FAM10 In-Reply-To: Message-ID: <882021.67822.qm@web26101.mail.ukl.yahoo.com> thanks Myles thats mostly clear but I have one question Can I start with only CPU, HTX, DIMMS and IDE listed in config.lb and then work up from there? Or do I need to list everything which is soldered to the mainboard even if I don't need them (to boot linux)? regards Tom > You only need to add devices that: > 1. Won't be found otherwise > 2. Need some specific initialization > 3. Are soldered to the mainboard > > Everything else will be found and initialized > automatically. > > Good luck, > Myles > > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From mylesgw at gmail.com Tue Aug 11 19:19:38 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 11 Aug 2009 11:19:38 -0600 Subject: [coreboot] ASUS KFN4D16 - K8 FAM10 In-Reply-To: <882021.67822.qm@web26101.mail.ukl.yahoo.com> References: <882021.67822.qm@web26101.mail.ukl.yahoo.com> Message-ID: <2831fecf0908111019v4eb0aaf7p3599f7fe23a9ae79@mail.gmail.com> On Tue, Aug 11, 2009 at 11:17 AM, thomas ward wrote: > thanks Myles > > > thats mostly clear but I have one question > > Can I start with only CPU, HTX, DIMMS and IDE listed in config.lb and then > work up from there? Yes. > Or do I need to list everything which is soldered to the mainboard even if > I don't need them (to boot linux)? No. You only need to list the things that need to be initialized by Coreboot. Devices that don't need special initialization need not be mentioned even if you need them. Thanks, Myles -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Tue Aug 11 19:32:26 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 11 Aug 2009 19:32:26 +0200 Subject: [coreboot] [v2] r4530 - trunk/coreboot-v2/src/cpu/amd/model_lx Message-ID: Author: oxygene Date: 2009-08-11 19:32:26 +0200 (Tue, 11 Aug 2009) New Revision: 4530 Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc Log: cpu/amd/model_lx used its own routine for copying coreboot_ram. This change makes it use the generic infrastructure. NOTE: If you're bisecting issues on geode-lx circa jumping to coreboot_ram, this change has a high probability to break that place - so look into it. Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2009-08-11 15:56:18 UTC (rev 4529) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2009-08-11 17:32:26 UTC (rev 4530) @@ -217,107 +217,25 @@ * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ -#if !CONFIG_COMPRESS + movl %ebp, %esi + /* FIXME: look for a proper place for the stack */ + movl $0x4000000, %esp + movl %esp, %ebp + pushl %esi +#if CONFIG_CBFS == 1 + pushl $str_coreboot_ram_name + call cbfs_and_run_core +#else movl $_liseg, %esi movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx - movb %cl, %al - shrl $2, %ecx - andb $3, %al - rep movsl - movb %al, %cl - rep movsb -#else - leal 4+_liseg, %esi - leal _iseg, %edi - movl %ebp, %esp /* preserve %ebp */ - movl $-1, %ebp /* last_m_off = -1 */ - jmp dcl1_n2b - -/* ------------- DECOMPRESSION ------------- - - Input: - %esi - source - %edi - dest - %ebp - -1 - cld - - Output: - %eax - 0 - %ecx - 0 -*/ - -.macro getbit bits -.if \bits == 1 - addl %ebx, %ebx - jnz 1f -.endif - movl (%esi), %ebx - subl $-4, %esi /* sets carry flag */ - adcl %ebx, %ebx -1: -.endm - -decompr_literals_n2b: - movsb - -decompr_loop_n2b: - addl %ebx, %ebx - jnz dcl2_n2b -dcl1_n2b: - getbit 32 -dcl2_n2b: - jc decompr_literals_n2b - xorl %eax, %eax - incl %eax /* m_off = 1 */ -loop1_n2b: - getbit 1 - adcl %eax, %eax /* m_off = m_off*2 + getbit() */ - getbit 1 - jnc loop1_n2b /* while(!getbit()) */ - xorl %ecx, %ecx - subl $3, %eax - jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */ - shll $8, %eax - movb (%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */ - incl %esi - xorl $-1, %eax - jz decompr_end_n2b /* if (m_off == 0xffffffff) goto decomp_end_n2b */ - movl %eax, %ebp /* last_m_off = m_off ?*/ -decompr_ebpeax_n2b: - getbit 1 - adcl %ecx, %ecx /* m_len = getbit() */ - getbit 1 - adcl %ecx, %ecx /* m_len = m_len*2 + getbit()) */ - jnz decompr_got_mlen_n2b /* if (m_len == 0) goto decompr_got_mlen_n2b */ - incl %ecx /* m_len++ */ -loop2_n2b: - getbit 1 - adcl %ecx, %ecx /* m_len = m_len*2 + getbit() */ - getbit 1 - jnc loop2_n2b /* while(!getbit()) */ - incl %ecx - incl %ecx /* m_len += 2 */ -decompr_got_mlen_n2b: - cmpl $-0xd00, %ebp - adcl $1, %ecx /* m_len = m_len + 1 + (last_m_off > 0xd00) */ - movl %esi, %edx - leal (%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */ - rep - movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */ - movl %edx, %esi - jmp decompr_loop_n2b -decompr_end_n2b: - intel_chip_post_macro(0x12) /* post 12 */ - - movl %esp, %ebp + pushl %ecx + pushl %edi + pushl %esi + call copy_and_run_core #endif - CONSOLE_DEBUG_TX_STRING($str_pre_main) - leal _iseg, %edi - jmp *%edi - .Lhlt: intel_chip_post_macro(0xee) /* post fail ee */ hlt @@ -377,3 +295,10 @@ .previous #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ +#if CONFIG_CBFS == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 +str_coreboot_ram_name: .string "fallback/coreboot_ram" +# else +str_coreboot_ram_name: .string "normal/coreboot_ram" +# endif +#endif From svn at coreboot.org Tue Aug 11 19:35:02 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 11 Aug 2009 19:35:02 +0200 Subject: [coreboot] [v2] r4531 - in trunk/coreboot-v2: src/config src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/norwich src/mainboard/amd/pistachio src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/artecgroup/dbe61 src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/asus/p2b src/mainboard/asus/p2b-d src/mainboard/asus/p2b-ds src/mainboard/asus/p2b-f src/mainboard/asus/p3b-f src/mainboard/axus/tc320 src/mainboard/azza/pt-6ibd src/mainboard/bcom/winnet100 src/mainboard/bcom/winnetp680 src/mainboard/biostar/m6tba src/mainboard/broadcom/blast src/mainboard/compaq/deskpro_en_sff_p600 src/mainboard/dell/s1850 src/mainboard/digitallogic/adl855pc src/mainboard/digitallogic/msm586seg src/mainboard/digitallogic/msm800sev src/mainboard/eaglelion/5bcm src/mainboard/embeddedplanet/ep405pc src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/iei/juki-511p src/mainboard/iei/nova4899r src/mainboard/iei/pcisa-lx-800-r10 src/mainboard/intel/jarrell src/mainboard/intel/mtarvon src/mainboard/intel/truxton src/mainboard/intel/xe7501devkit src/mainboard/iwill/dk8_htx src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x src/mainboard/jetway/j7f24 src/mainboard/lippert/frontrunner src/mainboard/lippert/roadrunner-lx src/mainboard/lippert/spacerunner-lx src/mainboard/mitac/6513wu src/mainboard/motorola/sandpoint src/mainboard/motorola/sandpointx3_altimus_mpc7410 src/mainboard/msi/ms6119 src/mainboard/msi/ms6147 src/mainboard/msi/ms7135 src/mainboard/msi/ms7260 src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/nec/powermate2000 src/mainboard/newisys/khepri src/mainboard/nvidia/l1_2pvv src/mainboard/olpc/btest src/mainboard/olpc/rev_a src/mainboard/pcengines/alix1c src/mainboard/rca/rm4100 src/mainboard/soyo/sy-6ba-plus-iii src/mainboard/sunw/ultra40 src/mainboard/supermicro/h8dme src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion/tim8690 src/mainboard/technologic/ts5300 src/mainboard/televideo/tc7020 src/mainboard/thomson/ip1000 src/mainboard/totalimpact/briq src/mainboard/tyan/s1846 src/mainboard/tyan/s2735 src/mainboard/tyan/s2850 src/mainboard/tyan/s2875 src/mainboard/tyan/s2880 src/mainboard/tyan/s2881 src/mainboard/tyan/s2882 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/mainboard/tyan/s2912 src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880 src/mainboard/tyan/s4882 src/mainboard/via/epia src/mainboard/via/epia-cn src/mainboard/via/epia-m src/mainboard/via/epia-m700 src/mainboard/via/epia-n src/mainboard/via/pc2500e targets/amd/db800 targets/amd/norwich targets/amd/rumba targets/amd/serengeti_cheetah targets/amd/serengeti_cheetah_fam10 targets/arima/hdama targets/artecgroup/dbe61 targets/asi/mb_5blmp targets/asus/a8n_e targets/asus/m2v-mx_se targets/digitallogic/msm586seg targets/gigabyte/ga_2761gxdk targets/gigabyte/m57sli targets/iei/juki-511p targets/iwill/dk8_htx targets/msi/ms7135 targets/msi/ms7260 targets/nvidia/l1_2pvv targets/supermicro/h8dme targets/technologic/ts5300 targets/tyan/s2895 targets/tyan/s2912 targets/tyan/s2912_fam10 Message-ID: Author: oxygene Date: 2009-08-11 19:35:02 +0200 (Tue, 11 Aug 2009) New Revision: 4531 Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb trunk/coreboot-v2/src/mainboard/via/epia/Options.lb trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb trunk/coreboot-v2/targets/amd/db800/Config.lb trunk/coreboot-v2/targets/amd/norwich/Config.lb trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb Log: Enable CBFS everywhere. All boards compiled for me (abuild tested), and we will fix issues as they appear. Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/config/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -693,7 +693,7 @@ comment "Enable FAT filesystem support" end define CONFIG_CBFS - default 0 + default 1 export always comment "The new CBFS file system" end Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,7 +78,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -102,5 +102,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -106,9 +106,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -305,5 +305,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -106,9 +106,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -305,5 +305,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -164,5 +164,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -105,12 +105,8 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 -#FAILOVER: 4K +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl @@ -239,7 +235,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -333,5 +329,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -130,11 +130,9 @@ ## #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 1024K - 8K -default CONFIG_FALLBACK_SIZE=0xFE000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 8k default CONFIG_FAILOVER_SIZE=0x02000 @@ -368,5 +366,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -76,7 +76,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -246,5 +246,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -166,5 +166,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -100,8 +100,8 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 252 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE = 4 * 1024 default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_HAVE_FAILOVER_BOOT = 1 @@ -171,5 +171,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -95,7 +95,7 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_HAVE_PIRQ_TABLE = 0 @@ -171,5 +171,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -173,9 +173,12 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" + +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 # # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -162,5 +162,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,7 +78,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -102,5 +102,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -81,7 +81,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -103,5 +103,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -81,7 +81,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -108,5 +108,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_PIRQ_ROUTE = 1 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_PIRQ_ROUTE = 1 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -84,7 +84,7 @@ default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -108,5 +108,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -81,9 +81,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -266,5 +264,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -130,7 +130,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 ## ## Use a small 8K stack @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -119,5 +119,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -1,5 +1,4 @@ default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = 0x10000 ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 32 * 1024 Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -93,7 +93,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -127,5 +127,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -91,7 +91,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -169,5 +169,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -148,5 +148,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -131,11 +131,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -261,7 +259,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -357,5 +355,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -132,11 +132,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -270,7 +268,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -365,6 +363,6 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 ### End Options.lb end Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -65,7 +65,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -225,5 +225,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -67,7 +67,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -231,5 +231,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -3,8 +3,6 @@ ## (coreboot plus bootloader) will live in the boot rom chip. ## default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_SIZE -default CONFIG_ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -150,5 +150,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -98,7 +98,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -177,5 +177,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ default CONFIG_PIRQ_ROUTE = 1 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_DCACHE_RAM = 1 default CONFIG_DCACHE_RAM_BASE = 0xc8000 default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 @@ -111,5 +111,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -161,7 +161,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -246,5 +246,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -18,7 +18,7 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -150,7 +150,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## coreboot C code runs at this location in RAM @@ -229,5 +229,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -18,7 +18,7 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -150,7 +150,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## coreboot C code runs at this location in RAM @@ -231,5 +231,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -1,5 +1,5 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -79,7 +79,7 @@ ## Build code for the fallback boot? ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## Delay timer options @@ -244,5 +244,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -105,11 +105,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-8K -default CONFIG_FALLBACK_SIZE=0x3e000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 8K default CONFIG_FAILOVER_SIZE=0x02000 @@ -238,7 +236,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -332,5 +330,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -66,7 +66,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -66,7 +66,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -231,5 +231,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -109,5 +109,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -164,5 +164,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,7 +129,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -215,5 +215,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,7 +129,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -215,5 +215,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -75,10 +75,10 @@ # ROM layout default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 # RAM layout default CONFIG_RAMBASE = 0x00004000 Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -130,5 +130,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -125,5 +125,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -112,7 +112,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=(252*1024) +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=(4*1024) @@ -228,8 +228,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = (64*1024) -#65536 +default CONFIG_ROM_IMAGE_SIZE = (64*1024) - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -325,5 +324,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = (256 * 1024) - (4 * 1024) +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE = 4 * 1024 default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. default CONFIG_HAVE_FALLBACK_BOOT = 1 @@ -169,7 +169,7 @@ default CONFIG_MAINBOARD_VENDOR = "MSI" default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE default CONFIG_STACK_SIZE = 0x2000 default CONFIG_HEAP_SIZE = 0x8000 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) @@ -190,5 +190,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -118,10 +118,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -334,5 +331,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -112,9 +112,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -313,5 +311,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,7 +74,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -100,5 +100,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -73,9 +73,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -249,5 +247,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,11 +129,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -259,7 +257,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -355,5 +353,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -89,7 +89,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -165,5 +165,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -89,7 +89,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -165,5 +165,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -119,7 +119,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -203,5 +203,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -68,7 +68,7 @@ default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_FALLBACK_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 @@ -100,5 +100,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -96,5 +96,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -82,9 +82,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -282,5 +280,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -133,11 +133,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -261,7 +259,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -357,5 +355,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -106,9 +106,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -108,7 +108,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -140,5 +140,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ default CONFIG_IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -108,5 +108,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -68,7 +68,7 @@ default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 @@ -100,5 +100,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -132,5 +132,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,7 +78,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -102,5 +102,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -76,7 +76,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -260,5 +260,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -250,5 +248,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## @@ -251,5 +249,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -250,5 +248,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -79,9 +79,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -267,5 +265,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -250,5 +248,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,9 +85,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -277,5 +275,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,9 +88,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -306,5 +304,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -82,9 +82,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -294,5 +292,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -91,11 +91,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -218,7 +216,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -313,5 +311,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,11 +129,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -261,7 +259,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -357,5 +355,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -20,7 +20,7 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/failovercalculation.lb arch i386 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -133,10 +133,8 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl @@ -270,7 +268,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = (128*1024) - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -366,5 +364,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,9 +78,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -259,5 +257,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,9 +78,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -258,5 +256,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -111,7 +111,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -146,5 +146,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -109,5 +109,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -148,5 +148,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -124,7 +124,7 @@ default CONFIG_HAVE_ACPI_TABLES = 1 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 16 * 1024 default CONFIG_HEAP_SIZE = 20 * 1024 @@ -137,7 +137,7 @@ default HOSTCC = "gcc" default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -98,7 +98,7 @@ #default CONFIG_PAYLOAD_SIZE = 125 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 default CONFIG_PAYLOAD_SIZE = 256 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE + CONFIG_PAYLOAD_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -123,5 +123,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,7 +74,7 @@ default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 @@ -117,5 +117,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/targets/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/db800/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/db800/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -32,7 +32,6 @@ # Leave 36k for VSA. option CONFIG_ROM_SIZE=512*1024-36*1024 # option CONFIG_ROM_SIZE=256*1024-36*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 Modified: trunk/coreboot-v2/targets/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/norwich/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/norwich/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -32,7 +32,6 @@ option CONFIG_ROM_SIZE=512*1024-36*1024 #option CONFIG_ROM_SIZE=256*1024-36*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 Modified: trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb =================================================================== --- trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -5,8 +5,6 @@ mainboard amd/rumba option CONFIG_ROM_SIZE=128*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -#option CONFIG_FALLBACK_SIZE=65535 #romimage "normal" # option CONFIG_USE_FALLBACK_IMAGE=0 Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "fallback" option CONFIG_PRECOMPRESSED_PAYLOAD=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 - option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_ROM_IMAGE_SIZE=0x1a000 option CONFIG_XIP_ROM_SIZE=0x40000 Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -31,7 +31,6 @@ # 1024KB ROM option CONFIG_ROM_SIZE=1024*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE-CONFIG_FAILOVER_SIZE romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 Modified: trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb =================================================================== --- trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ uses CONFIG_ROM_PAYLOAD_START uses CONFIG_UDELAY_TSC uses CPU_FIXUP -uses CONFIG_FALLBACK_SIZE uses CONFIG_HAVE_FALLBACK_BOOT uses CONFIG_HAVE_MP_TABLE uses CONFIG_HAVE_PIRQ_TABLE @@ -71,12 +70,6 @@ option CONFIG_ROM_PAYLOAD=1 option CONFIG_HAVE_FALLBACK_BOOT=1 -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE - ## Coreboot C code runs at this location in RAM option CONFIG_RAMBASE=0x00004000 Modified: trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -21,8 +21,6 @@ ## not including any payload. option CONFIG_ROM_IMAGE_SIZE=64*1024 -option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE - option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" Modified: trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -23,7 +23,6 @@ option CONFIG_ROM_SIZE = (256 * 1024) # option CONFIG_ROM_SIZE = (256 * 1024) - (32 * 1024) -# option CONFIG_FALLBACK_SIZE = (256 * 1024) - (32 * 1024) romimage "normal" option CONFIG_USE_FALLBACK_IMAGE = 0 Modified: trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -35,15 +35,6 @@ ## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -# Please note that 128KB is cached for (XIP) too - -option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 - -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image -## (including payload) will use. - -option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE - romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 payload __PAYLOAD__ Modified: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -41,11 +41,6 @@ option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image -## (including payload) will use. - -option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE - romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 payload ../payload.elf Modified: trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -9,9 +9,7 @@ __LOGLEVEL__ romimage "fallback" - option CONFIG_FALLBACK_SIZE = 256 * 1024 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE= 128 * 1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -34,8 +34,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x28000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end @@ -43,8 +41,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -9,22 +9,15 @@ __LOGLEVEL__ option CONFIG_ROM_SIZE=256*1024 -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -option CONFIG_FALLBACK_SIZE=128*1024 romimage "normal" option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -31,8 +31,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE = 0 option CONFIG_USE_FALLBACK_IMAGE = 0 - option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 - option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" payload __PAYLOAD__ end @@ -40,8 +38,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE = 0 option CONFIG_USE_FALLBACK_IMAGE = 1 - option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 - option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -9,9 +9,7 @@ __LOGLEVEL__ romimage "fallback" - option CONFIG_FALLBACK_SIZE = 256 * 1024 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=128 * 1024 # 0x10000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -31,8 +31,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x34000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end @@ -40,8 +38,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x34000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end From bzadow at web.de Tue Aug 11 19:43:23 2009 From: bzadow at web.de (bz) Date: Tue, 11 Aug 2009 19:43:23 +0200 Subject: [coreboot] Problem to build the rom image Message-ID: <4A81ADBB.7030508@web.de> Hello, I just tried to build coreboot.rom for an Axus TC 320 as described in the Build tutorial. ./buildtarget axus/tc320 until here everything works fine. LANG=C make The job stop with the following messages. objdump -dS coreboot > coreboot.disasm objcopy --gap-fill 0xff -O binary coreboot coreboot.strip make[1]: *** No rule to make target `../../../../../../../images/etherboot.elf', needed by `payload'. Stop. make[1]: Leaving directory `/home/bz/neu/coreboot-v2/targets/axus/tc320/tc320/normal' make: *** [normal/coreboot.rom] Error 2 What am i doing wrong? Can anyone help me? I try to do that with different revisions of Coreboot-V2 From mylesgw at gmail.com Tue Aug 11 19:51:42 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 11 Aug 2009 11:51:42 -0600 Subject: [coreboot] Problem to build the rom image In-Reply-To: <4A81ADBB.7030508@web.de> References: <4A81ADBB.7030508@web.de> Message-ID: <2831fecf0908111051n449e834h70c24bc2748b3dd7@mail.gmail.com> On Tue, Aug 11, 2009 at 11:43 AM, bz wrote: > Hello, > I just tried to build coreboot.rom for an Axus TC 320 as described in the > Build tutorial. > > ./buildtarget axus/tc320 > > until here everything works fine. > > LANG=C make > The job stop with the following messages. > > > > objdump -dS coreboot > coreboot.disasm > objcopy --gap-fill 0xff -O binary coreboot coreboot.strip > make[1]: *** No rule to make target > `../../../../../../../images/etherboot.elf', needed by `payload'. Stop. It can't find your payload. You need to change ../../../../../../../images/etherboot.elf to ../payload.elf and copy your payload (filo, SeaBIOS, etc) to targets/axus/tc320/tc320/payload.elf Thanks, Myles -------------- next part -------------- An HTML attachment was scrubbed... URL: From c-d.hailfinger.devel.2006 at gmx.net Tue Aug 11 20:01:18 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 11 Aug 2009 20:01:18 +0200 Subject: [coreboot] Problem to build the rom image In-Reply-To: <4A81ADBB.7030508@web.de> References: <4A81ADBB.7030508@web.de> Message-ID: <4A81B1EE.7030101@gmx.net> Hi Bj?rn, On 11.08.2009 19:43, bz wrote: > I just tried to build coreboot.rom for an Axus TC 320 as described in > the Build tutorial. > > ./buildtarget axus/tc320 20 minutes ago Patrick committed a change to payload handling which may help you. Please retry with latest subversion. Regards, Carl-Daniel -- http://www.hailfinger.org/ From info at coresystems.de Tue Aug 11 20:31:36 2009 From: info at coresystems.de (coreboot information) Date: Tue, 11 Aug 2009 20:31:36 +0200 Subject: [coreboot] build service results for r4531 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4531 to the coreboot repository. This caused the following changes: Change Log: Enable CBFS everywhere. All boards compiled for me (abuild tested), and we will fix issues as they appear. Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=atc-6220&vendor=a-trend&num=2 Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=atc-6240&vendor=a-trend&num=2 Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=be6-ii_v2_0&vendor=abit&num=2 Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b&vendor=asus&num=2 Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b-d&vendor=asus&num=2 Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b-ds&vendor=asus&num=2 Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b-f&vendor=asus&num=2 Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p3b-f&vendor=asus&num=2 Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=pt-6ibd&vendor=azza&num=2 Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=m6tba&vendor=biostar&num=2 Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=deskpro_en_sff_p600&vendor=compaq&num=2 Compilation of embeddedplanet:ep405pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ep405pc&vendor=embeddedplanet&num=2 Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ga-6bxc&vendor=gigabyte&num=2 Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=nova4899r&vendor=iei&num=2 Compilation of motorola:sandpointx3_altimus_mpc7410 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2 Compilation of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ms6119&vendor=msi&num=2 Compilation of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ms6147&vendor=msi&num=2 Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=sy-6ba-plus-iii&vendor=soyo&num=2 Compilation of totalimpact:briq has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=briq&vendor=totalimpact&num=2 Compilation of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=s1846&vendor=tyan&num=2 Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=epia-m&vendor=via&num=2 If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From harald.gutmann at gmx.net Tue Aug 11 20:38:08 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Tue, 11 Aug 2009 20:38:08 +0200 Subject: [coreboot] [PATCH]Kconfig for v2 In-Reply-To: References: <4A79A377.7040403@coresystems.de> Message-ID: <200908112038.08885.harald.gutmann@gmx.net> On Tuesday 11 August 2009 18:15:16 Patrick Georgi wrote: > https://www.coresystems.de/~patrick/20090811-1-kconfig is an updated patch, > with some AMD support by Ron. Fine to see your Kconfig patch. Right now I'm adding the gigabyte M57SLI target to Kconfig. And, there are in the coreboot-v2-kconfig branch some values wrong defined in Kconfig files. I've allready fixed that warnings, and hopefully your attached patch represents the state of which I get when checking out the coreboot-v2-kconfig branch. > Signed-off-by: Patrick Georgi Kind Regards, Harald From rminnich at gmail.com Tue Aug 11 21:35:26 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 11 Aug 2009 12:35:26 -0700 Subject: [coreboot] [PATCH]Kconfig for v2 In-Reply-To: <200908112038.08885.harald.gutmann@gmx.net> References: <4A79A377.7040403@coresystems.de> <200908112038.08885.harald.gutmann@gmx.net> Message-ID: <13426df10908111235k1f03da83m8462d0cb73aafa54@mail.gmail.com> Harald, there is a bit of documentation in there about usage of Kconfig and Makefile.config. It is not complete but I fill in a little each day. Please refer to it w.r.t. the use of mainboard and socket Kconfig. What if we apply this patch and get yours in next? ron From rminnich at gmail.com Tue Aug 11 21:41:01 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 11 Aug 2009 12:41:01 -0700 Subject: [coreboot] [PATCH]Kconfig for v2 In-Reply-To: References: <4A79A377.7040403@coresystems.de> Message-ID: <13426df10908111241g4e91ac0fx9297d33a62d90913@mail.gmail.com> Acked-by: Ronald G. Minnich Folks, please read and comment on documentation/Kconfig.tex This is a changing document but I'm happy to get any comments even in its current form. ron From harald.gutmann at gmx.net Tue Aug 11 21:58:35 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Tue, 11 Aug 2009 21:58:35 +0200 Subject: [coreboot] [PATCH]Kconfig for v2 In-Reply-To: <13426df10908111235k1f03da83m8462d0cb73aafa54@mail.gmail.com> References: <4A79A377.7040403@coresystems.de> <200908112038.08885.harald.gutmann@gmx.net> <13426df10908111235k1f03da83m8462d0cb73aafa54@mail.gmail.com> Message-ID: <200908112158.35661.harald.gutmann@gmx.net> On Tuesday 11 August 2009 21:35:26 ron minnich wrote: > Harald, there is a bit of documentation in there about usage of > Kconfig and Makefile.config. It is not complete but I fill in a little > each day. Please refer to it w.r.t. the use of mainboard and socket > Kconfig. > > What if we apply this patch and get yours in next? For my part I really welcome the Kconfig build system, and therefore I'd like to see it commited. My patch is right now not as far to get commited, I think it will take a few days more to get it in a fine shape. > > ron Regards, Harald From wangqingpei at gmail.com Tue Aug 11 21:59:02 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Wed, 12 Aug 2009 03:59:02 +0800 Subject: [coreboot] option rom progress and some issues Message-ID: Hi all Since USB ROM has already added into the booting menu list(IPL table), and the UHCI stack can be run well in usbrom now, i have some issues to confirm, any advices are welcome. 1) <>Page21, There is an r Return Status from Initialization Call of OPTION ROM. Which used to let the bios know the status. But it seems Seabios does not check the return code. Is that OK? 2) After Seabios make an far call into the BEV, the OPTION ROM should begin to load OS.if it failed, it can return back to BIOS. But it can not return back with my USB OPTION ROM, Is there any configuration I should set? 3) In my eyes, OPTION ROM hook int13 after jump into BEV, not in the initialization.But after that how does it jump into the booting code which located in the USB disk? BTW: Kevin: I looked the code of Seabios ata.c to learn how seabios booting OS from ata disk. some question i have: 1) ATA used add_bcv_hd to add ata disk into IPL table. it's type is IPL_TYPE_HARDDISK(0x02). It's vector is the driver id. how does seabios know the bootstrap vector based the driver ID? what does ata fill FDPT area for? Should my usbrom do the same? For my usbrom, i should not use add_bcv to add option rom into IPL ? or just take the ata as example? -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: From kevin at koconnor.net Wed Aug 12 02:18:02 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Tue, 11 Aug 2009 20:18:02 -0400 Subject: [coreboot] option rom progress and some issues In-Reply-To: References: Message-ID: <20090812001802.GA28392@morn.localdomain> On Wed, Aug 12, 2009 at 03:59:02AM +0800, Jason Wang wrote: > Hi all > Since USB ROM has already added into the booting menu list(IPL table), > and the UHCI stack can be run well in usbrom now, i have some issues to > confirm, any advices are welcome. > 1) <>Page21, There is an r Return Status > from Initialization Call of OPTION ROM. Which used to let the bios know the > status. But it seems Seabios does not > check the return code. Is that OK? SeaBIOS assumes the rom runs successfully - I think that is okay. If you wish to unload the optionrom, set its size to 0. > 2) After Seabios make an far call into the BEV, the OPTION ROM should begin > to load OS.if it failed, it can return back to BIOS. But it can not return > back with my USB OPTION ROM, Is there any configuration > I should set? You should not use BEV; you should use a BCV. I don't know why you can't return - it should work. Maybe the stack or gdt/idt was changed? > 3) In my eyes, OPTION ROM hook int13 after jump into BEV, not in the > initialization.But after that how does it jump into the booting code which > located in the USB disk? As above, define a BCV and hook int13 from the BCV handler. SeaBIOS will make int13 calls to load the OS and boot it. As long as your rom can handle the int13 calls, SeaBIOS will be able to boot an OS from usb. > BTW: > Kevin: I looked the code of Seabios ata.c to learn how seabios booting OS > from ata disk. some question i have: > 1) ATA used add_bcv_hd to add ata disk into IPL table. it's type is > IPL_TYPE_HARDDISK(0x02). It's vector is the driver id. how does seabios know > the bootstrap vector based the driver ID? add_bcv_hd() adds the drive to the BCV table, not the IPL table. SeaBIOS populates the BCV table with built-in harddrives and optionroms with a BCV. > what does ata fill FDPT area for? Should my usbrom do the same? It's some weird legacy thing. Nothing modern will require it. I don't know what legacy things will break without it. > For my usbrom, i should not use add_bcv to add option rom into IPL ? or just > take the ata as example? As above, you should use a BCV. > > -- > Jason Wang > Peking University -Kevin From wangqingpei at gmail.com Wed Aug 12 04:59:51 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Wed, 12 Aug 2009 10:59:51 +0800 Subject: [coreboot] option rom progress and some issues In-Reply-To: <20090812001802.GA28392@morn.localdomain> References: <20090812001802.GA28392@morn.localdomain> Message-ID: Hi Kevin, On Wed, Aug 12, 2009 at 8:18 AM, Kevin O'Connor wrote: > On Wed, Aug 12, 2009 at 03:59:02AM +0800, Jason Wang wrote: > > Hi all > > Since USB ROM has already added into the booting menu list(IPL > table), > > and the UHCI stack can be run well in usbrom now, i have some issues to > > confirm, any advices are welcome. > > 1) <>Page21, There is an r Return > Status > > from Initialization Call of OPTION ROM. Which used to let the bios know > the > > status. But it seems Seabios does not > > check the return code. Is that OK? > > SeaBIOS assumes the rom runs successfully - I think that is okay. If > you wish to unload the optionrom, set its size to 0. > > > 2) After Seabios make an far call into the BEV, the OPTION ROM should > begin > > to load OS.if it failed, it can return back to BIOS. But it can not > return > > back with my USB OPTION ROM, Is there any configuration > > I should set? > > You should not use BEV; you should use a BCV. > I use a BCV now, sorry for messing this two types. Which i use is BCV. I tried to put only an "lretw" in BCV. but still failed. > > I don't know why you can't return - it should work. Maybe the stack > or gdt/idt was changed? > > > 3) In my eyes, OPTION ROM hook int13 after jump into BEV, not in the > > initialization.But after that how does it jump into the booting code > which > > located in the USB disk? > > As above, define a BCV and hook int13 from the BCV handler. > So, BCV handler is used to hook int13, anything else that BCV should do? > > SeaBIOS will make int13 calls to load the OS and boot it. As long as > your rom can handle the int13 calls, SeaBIOS will be able to boot an > OS from usb. > > > BTW: > > Kevin: I looked the code of Seabios ata.c to learn how seabios booting > OS > > from ata disk. some question i have: > > 1) ATA used add_bcv_hd to add ata disk into IPL table. it's type is > > IPL_TYPE_HARDDISK(0x02). It's vector is the driver id. how does seabios > know > > the bootstrap vector based the driver ID? > > add_bcv_hd() adds the drive to the BCV table, not the IPL table. > > > SeaBIOS populates the BCV table with built-in harddrives and > optionroms with a BCV. > > > what does ata fill FDPT area for? Should my usbrom do the same? > > It's some weird legacy thing. Nothing modern will require it. I > don't know what legacy things will break without it. > > > For my usbrom, i should not use add_bcv to add option rom into IPL ? or > just > > take the ata as example? > > As above, you should use a BCV. > > > > > -- > > Jason Wang > > Peking University > > -Kevin > -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Wed Aug 12 09:29:06 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Wed, 12 Aug 2009 15:29:06 +0800 Subject: [coreboot] option rom progress and some issues In-Reply-To: References: <20090812001802.GA28392@morn.localdomain> Message-ID: Hi Kevin, The Seabios try to booting usbrom with IPL_TYPE_BEV, which i think should use IPL_TYPE_HARDDISK, right? Followed by BIOS BOOT Specification I think it can add #define IPL_TYPE_USBROM 0x05 to support BCV, how do you think about that? On Wed, Aug 12, 2009 at 10:59 AM, Jason Wang wrote: > Hi Kevin, > > > On Wed, Aug 12, 2009 at 8:18 AM, Kevin O'Connor wrote: > >> On Wed, Aug 12, 2009 at 03:59:02AM +0800, Jason Wang wrote: >> > Hi all >> > Since USB ROM has already added into the booting menu list(IPL >> table), >> > and the UHCI stack can be run well in usbrom now, i have some issues to >> > confirm, any advices are welcome. >> > 1) <>Page21, There is an r Return >> Status >> > from Initialization Call of OPTION ROM. Which used to let the bios know >> the >> > status. But it seems Seabios does not >> > check the return code. Is that OK? >> >> SeaBIOS assumes the rom runs successfully - I think that is okay. If >> you wish to unload the optionrom, set its size to 0. >> >> > 2) After Seabios make an far call into the BEV, the OPTION ROM should >> begin >> > to load OS.if it failed, it can return back to BIOS. But it can not >> return >> > back with my USB OPTION ROM, Is there any configuration >> > I should set? >> >> You should not use BEV; you should use a BCV. >> > I use a BCV now, sorry for messing this two types. Which i use is BCV. > I tried to put only an "lretw" in BCV. but still failed. > >> >> I don't know why you can't return - it should work. Maybe the stack >> or gdt/idt was changed? >> >> > 3) In my eyes, OPTION ROM hook int13 after jump into BEV, not in the >> > initialization.But after that how does it jump into the booting code >> which >> > located in the USB disk? >> >> As above, define a BCV and hook int13 from the BCV handler. >> > So, BCV handler is used to hook int13, anything else that BCV should do? > >> >> SeaBIOS will make int13 calls to load the OS and boot it. As long as >> your rom can handle the int13 calls, SeaBIOS will be able to boot an >> OS from usb. >> >> > BTW: >> > Kevin: I looked the code of Seabios ata.c to learn how seabios booting >> OS >> > from ata disk. some question i have: >> > 1) ATA used add_bcv_hd to add ata disk into IPL table. it's type is >> > IPL_TYPE_HARDDISK(0x02). It's vector is the driver id. how does seabios >> know >> > the bootstrap vector based the driver ID? >> >> add_bcv_hd() adds the drive to the BCV table, not the IPL table. >> > >> >> SeaBIOS populates the BCV table with built-in harddrives and >> optionroms with a BCV. >> >> > what does ata fill FDPT area for? Should my usbrom do the same? >> >> It's some weird legacy thing. Nothing modern will require it. I >> don't know what legacy things will break without it. >> >> > For my usbrom, i should not use add_bcv to add option rom into IPL ? or >> just >> > take the ata as example? >> >> As above, you should use a BCV. >> >> > >> > -- >> > Jason Wang >> > Peking University >> >> -Kevin >> > > > > -- > Jason Wang > Peking University > -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: From chriskindt at umbc.edu Wed Aug 12 12:02:08 2009 From: chriskindt at umbc.edu (Chris Kindt) Date: Wed, 12 Aug 2009 06:02:08 -0400 Subject: [coreboot] Geode LX VGA BIOS Patch Message-ID: <4A829320.4020606@umbc.edu> Hello coreboot These initial patches enable booting with the SeaBIOS VGA BIOS on Geode LX hardware. corebootv3-vga-msr.patch adds 3 vga legacy io routing msrs seabios-vgarom-geodelx.patch adds geodelx specific functions to the vgabios The rom will run from either coreboot/vm86 or SeaBIOS. When finished "GeodeLX GPL VGA BIOS" should be displayed on the screen. My test hardware is an Artec Group DBE-61. I have successfully built and used the rom with gcc-4.1.2/binutils-2.17 and gcc-4.3.3/binutils-2.18. VGA functionality has been tested with the linux vga console, svgalib utils, libpayload vga driver and SeaBIOS. I have also confirmed that linux lxfb and Xorg function correctly after the rom is loaded. Chris Kindt Signed-off-by: Chris Kindt -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: corebootv3-vga-msr.patch URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: seabios-vgarom-geodelx.patch URL: From kevin at koconnor.net Wed Aug 12 15:17:40 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Wed, 12 Aug 2009 09:17:40 -0400 Subject: [coreboot] option rom progress and some issues In-Reply-To: References: <20090812001802.GA28392@morn.localdomain> <20090812001802.GA28392@morn.localdomain> Message-ID: <20090812131740.GA2572@morn.localdomain> On Wed, Aug 12, 2009 at 03:29:06PM +0800, Jason Wang wrote: > Hi Kevin, > The Seabios try to booting usbrom with IPL_TYPE_BEV, which i think > should use IPL_TYPE_HARDDISK, right? Followed by BIOS BOOT Specification > I think it can add > #define IPL_TYPE_USBROM 0x05 to support BCV, how do you think about that? SeaBIOS is overloading those flags, and I agree it's confusing. The flags for BCV tables are only used in run_bcv(), add_bcv(), and add_bcv_hd(). It's not necessary to add a new flag. On Wed, Aug 12, 2009 at 10:59:51AM +0800, Jason Wang wrote: > I use a BCV now, sorry for messing this two types. Which i use is BCV. > I tried to put only an "lretw" in BCV. but still failed. > > > I don't know why you can't return - it should work. Maybe the stack > > or gdt/idt was changed? As before, I'd double check that you've restored the stack, segments, cr0, and gdt/idt. > > As above, define a BCV and hook int13 from the BCV handler. > > > So, BCV handler is used to hook int13, anything else that BCV should do? That should be it. -Kevin From svn at coreboot.org Wed Aug 12 17:00:51 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 12 Aug 2009 17:00:51 +0200 Subject: [coreboot] [v2] r4534 - in trunk/coreboot-v2: . documentation src src/arch/i386 src/arch/i386/boot src/arch/i386/init src/arch/i386/lib src/arch/i386/smp src/arch/ppc src/boot src/console src/cpu src/cpu/amd src/cpu/amd/socket_F src/cpu/emulation src/cpu/emulation/qemu-x86 src/cpu/intel src/cpu/intel/hyperthreading src/cpu/intel/microcode src/cpu/intel/model_69x src/cpu/intel/model_6dx src/cpu/intel/model_6ex src/cpu/intel/model_6fx src/cpu/intel/model_6xx src/cpu/intel/socket_PGA370 src/cpu/intel/socket_mFCPGA478 src/cpu/intel/speedstep src/cpu/ppc src/cpu/simple_init src/cpu/via src/cpu/via/model_c7 src/cpu/x86 src/cpu/x86/cache src/cpu/x86/fpu src/cpu/x86/lapic src/cpu/x86/mmx src/cpu/x86/mtrr src/cpu/x86/smm src/cpu/x86/sse src/cpu/x86/tsc src/devices src/drivers src/drivers/pci src/drivers/pci/onboard src/lib src/mainboard src/mainboard/a-trend src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech src/mainboard/advantech/pcm-5820 src/mainboard/amd src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/norwich src/mainboard/amd/pistachio src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima src/mainboard/arima/hdama src/mainboard/artecgroup src/mainboard/artecgroup/dbe61 src/mainboard/asi src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp src/mainboard/asus src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/asus/p2b src/mainboard/asus/p2b-d src/mainboard/asus/p2b-ds src/mainboard/asus/p2b-f src/mainboard/asus/p3b-f src/mainboard/axus src/mainboard/axus/tc320 src/mainboard/azza src/mainboard/azza/pt-6ibd src/mainboard/bcom src/mainboard/bcom/winnet100 src/mainboard/bcom/winnetp680 src/mainboard/biostar src/mainboard/biostar/m6tba src/mainboard/broadcom src/mainboard/broadcom/blast src/mainboard/compaq src/mainboard/compaq/deskpro_en_sff_p600 src/mainboard/dell src/mainboard/dell/s1850 src/mainboard/digitallogic src/mainboard/digitallogic/adl855pc src/mainboard/digitallogic/msm586seg src/mainboard/digitallogic/msm800sev src/mainboard/eaglelion src/mainboard/eaglelion/5bcm src/mainboard/embeddedplanet src/mainboard/embeddedplanet/ep405pc src/mainboard/emulation src/mainboard/emulation/qemu-x86 src/mainboard/gigabyte src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli src/mainboard/hp src/mainboard/hp/dl145_g3 src/mainboard/ibm src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/iei src/mainboard/iei/juki-511p src/mainboard/iei/nova4899r src/mainboard/iei/pcisa-lx-800-r10 src/mainboard/intel src/mainboard/intel/jarrell src/mainboard/intel/mtarvon src/mainboard/intel/truxton src/mainboard/intel/xe7501devkit src/mainboard/iwill src/mainboard/iwill/dk8_htx src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x src/mainboard/jetway src/mainboard/jetway/j7f24 src/mainboard/kontron src/mainboard/kontron/986lcd-m src/mainboard/lippert src/mainboard/lippert/frontrunner src/mainboard/lippert/roadrunner-lx src/mainboard/lippert/spacerunner-lx src/mainboard/mitac src/mainboard/motorola src/mainboard/motorola/sandpoint src/mainboard/motorola/sandpointx3_altimus_mpc7410 src/mainboard/msi src/mainboard/msi/ms6119 src/mainboard/msi/ms6147 src/mainboard/msi/ms6178 src/mainboard/msi/ms7135 src/mainboard/msi/ms7260 src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/nec src/mainboard/nec/powermate2000 src/mainboard/newisys src/mainboard/newisys/khepri src/mainboard/nvidia src/mainboard/nvidia/l1_2pvv src/mainboard/olpc src/mainboard/olpc/btest src/mainboard/olpc/rev_a src/mainboard/pcengines src/mainboard/pcengines/alix1c src/mainboard/rca src/mainboard/rca/rm4100 src/mainboard/soyo src/mainboard/sunw src/mainboard/sunw/ultra40 src/mainboard/supermicro src/mainboard/supermicro/h8dme src/mainboard/supermicro/h8dmr src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion src/mainboard/technexion/tim8690 src/mainboard/technologic src/mainboard/technologic/ts5300 src/mainboard/televideo src/mainboard/televideo/tc7020 src/mainboard/thomson src/mainboard/thomson/ip1000 src/mainboard/totalimpact src/mainboard/totalimpact/briq src/mainboard/tyan src/mainboard/tyan/s1846 src/mainboard/tyan/s2735 src/mainboard/tyan/s2850 src/mainboard/tyan/s2875 src/mainboard/tyan/s2880 src/mainboard/tyan/s2881 src/mainboard/tyan/s2882 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/mainboard/tyan/s2912 src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880 src/mainboard/tyan/s4882 src/mainboard/via src/mainboard/via/epia src/mainboard/via/epia-cn src/mainboard/via/epia-m src/mainboard/via/epia-m700 src/mainboard/via/pc2500e src/mainboard/via/vt8454c src/northbridge src/northbridge/amd src/northbridge/amd/amdk8 src/northbridge/amd/amdk8/root_complex src/northbridge/ibm src/northbridge/intel src/northbridge/intel/i82810 src/northbridge/intel/i945 src/northbridge/motorola src/northbridge/via src/northbridge/via/cx700 src/pc80 src/southbridge src/southbridge/amd src/southbridge/amd/amd8111 src/southbridge/broadcom src/southbridge/intel src/southbridge/intel/i82371eb src/southbridge/intel/i82801gx src/southbridge/intel/i82801xx src/southbridge/nvidia src/southbridge/ricoh src/southbridge/sis src/southbridge/via src/southbridge/winbond src/superio src/superio/fintek src/superio/fintek/f71805f src/superio/intel src/superio/intel/i3100 src/superio/ite src/superio/ite/it8661f src/superio/ite/it8671f src/superio/ite/it8673f src/superio/ite/it8705f src/superio/ite/it8712f src/superio/ite/it8716f src/superio/ite/it8718f src/superio/nsc src/superio/nsc/pc8374 src/superio/nsc/pc87309 src/superio/nsc/pc87351 src/superio/nsc/pc87360 src/superio/nsc/pc87366 src/superio/nsc/pc87417 src/superio/nsc/pc87427 src/superio/nsc/pc97307 src/superio/nsc/pc97317 src/superio/serverengines src/superio/smsc src/superio/smsc/fdc37m60x src/superio/smsc/lpc47b272 src/superio/smsc/lpc47b397 src/superio/smsc/lpc47m10x src/superio/smsc/lpc47n217 src/superio/smsc/smscsuperio src/superio/via src/superio/via/vt1211 src/superio/winbond src/superio/winbond/w83627dhg src/superio/winbond/w83627ehg src/superio/winbond/w83627hf src/superio/winbond/w83627thf src/superio/winbond/w83627thg src/superio/winbond/w83627uhg src/superio/winbond/w83697hf src/superio/winbond/w83977f src/superio/winbond/w83977tf targets/kontron/986lcd-m util util/abuild util/cbfstool util/cbfstool/tools util/cbfstool/tools/lzma util/kconfig util/kconfig/lxdialog util/sconfig util/x86emu util/x86emu/pcbios util/x86emu/x86emu util/xcompile Message-ID: Author: rminnich Date: 2009-08-12 17:00:51 +0200 (Wed, 12 Aug 2009) New Revision: 4534 Added: trunk/coreboot-v2/Makefile trunk/coreboot-v2/documentation/Kconfig.tex trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/arch/i386/Kconfig trunk/coreboot-v2/src/arch/i386/Makefile.inc trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc trunk/coreboot-v2/src/arch/i386/init/Makefile.inc trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc trunk/coreboot-v2/src/arch/ppc/Kconfig trunk/coreboot-v2/src/boot/Makefile.inc trunk/coreboot-v2/src/console/Kconfig trunk/coreboot-v2/src/console/Makefile.inc trunk/coreboot-v2/src/cpu/Kconfig trunk/coreboot-v2/src/cpu/Makefile.inc trunk/coreboot-v2/src/cpu/amd/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig trunk/coreboot-v2/src/cpu/emulation/Kconfig trunk/coreboot-v2/src/cpu/emulation/Makefile.inc trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc trunk/coreboot-v2/src/cpu/intel/Kconfig trunk/coreboot-v2/src/cpu/intel/Makefile.inc trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc trunk/coreboot-v2/src/cpu/ppc/Kconfig trunk/coreboot-v2/src/cpu/ppc/Makefile.inc trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc trunk/coreboot-v2/src/cpu/via/Kconfig trunk/coreboot-v2/src/cpu/via/Makefile.inc trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc trunk/coreboot-v2/src/cpu/x86/Kconfig trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc trunk/coreboot-v2/src/devices/Kconfig trunk/coreboot-v2/src/devices/Makefile.inc trunk/coreboot-v2/src/drivers/Makefile.inc trunk/coreboot-v2/src/drivers/pci/Makefile.inc trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc trunk/coreboot-v2/src/lib/Makefile.inc trunk/coreboot-v2/src/mainboard/Kconfig trunk/coreboot-v2/src/mainboard/a-trend/Kconfig trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb trunk/coreboot-v2/src/mainboard/abit/Kconfig trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb trunk/coreboot-v2/src/mainboard/advantech/Kconfig trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/Kconfig trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb trunk/coreboot-v2/src/mainboard/arima/Kconfig trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb trunk/coreboot-v2/src/mainboard/asi/Kconfig trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/Kconfig trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb 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trunk/coreboot-v2/src/mainboard/sunw/Kconfig trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb trunk/coreboot-v2/src/mainboard/technexion/Kconfig trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb trunk/coreboot-v2/src/mainboard/technologic/Kconfig trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb trunk/coreboot-v2/src/mainboard/televideo/Kconfig trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb 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trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/Kconfig trunk/coreboot-v2/src/northbridge/intel/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc trunk/coreboot-v2/src/northbridge/motorola/Kconfig trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc trunk/coreboot-v2/src/northbridge/via/Kconfig trunk/coreboot-v2/src/northbridge/via/Makefile.inc trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc trunk/coreboot-v2/src/pc80/Makefile.inc trunk/coreboot-v2/src/southbridge/Kconfig trunk/coreboot-v2/src/southbridge/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/Kconfig trunk/coreboot-v2/src/southbridge/amd/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/Kconfig trunk/coreboot-v2/src/southbridge/intel/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc trunk/coreboot-v2/src/southbridge/nvidia/Kconfig trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc trunk/coreboot-v2/src/southbridge/ricoh/Kconfig trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc trunk/coreboot-v2/src/southbridge/sis/Kconfig trunk/coreboot-v2/src/southbridge/sis/Makefile.inc trunk/coreboot-v2/src/southbridge/via/Kconfig trunk/coreboot-v2/src/southbridge/via/Makefile.inc trunk/coreboot-v2/src/southbridge/winbond/Kconfig trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc trunk/coreboot-v2/src/superio/Kconfig trunk/coreboot-v2/src/superio/Makefile.inc trunk/coreboot-v2/src/superio/fintek/Kconfig trunk/coreboot-v2/src/superio/fintek/Makefile.inc trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc trunk/coreboot-v2/src/superio/intel/Kconfig trunk/coreboot-v2/src/superio/intel/Makefile.inc trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc trunk/coreboot-v2/src/superio/ite/Kconfig trunk/coreboot-v2/src/superio/ite/Makefile.inc trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc trunk/coreboot-v2/src/superio/nsc/Kconfig trunk/coreboot-v2/src/superio/nsc/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc trunk/coreboot-v2/src/superio/serverengines/Kconfig trunk/coreboot-v2/src/superio/smsc/Kconfig trunk/coreboot-v2/src/superio/smsc/Makefile.inc trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc trunk/coreboot-v2/src/superio/via/Kconfig trunk/coreboot-v2/src/superio/via/Makefile.inc trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc trunk/coreboot-v2/src/superio/winbond/Kconfig trunk/coreboot-v2/src/superio/winbond/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc trunk/coreboot-v2/util/cbfstool/Makefile.inc trunk/coreboot-v2/util/cbfstool/tools/Makefile.inc trunk/coreboot-v2/util/cbfstool/tools/lzma/Makefile.inc trunk/coreboot-v2/util/kconfig/ trunk/coreboot-v2/util/kconfig/Makefile trunk/coreboot-v2/util/kconfig/POTFILES.in trunk/coreboot-v2/util/kconfig/check.sh trunk/coreboot-v2/util/kconfig/conf.c trunk/coreboot-v2/util/kconfig/confdata.c trunk/coreboot-v2/util/kconfig/expr.c trunk/coreboot-v2/util/kconfig/expr.h trunk/coreboot-v2/util/kconfig/gconf.c trunk/coreboot-v2/util/kconfig/gconf.glade trunk/coreboot-v2/util/kconfig/images.c trunk/coreboot-v2/util/kconfig/kconfig_load.c trunk/coreboot-v2/util/kconfig/kxgettext.c trunk/coreboot-v2/util/kconfig/lex.zconf.c_shipped trunk/coreboot-v2/util/kconfig/lkc.h trunk/coreboot-v2/util/kconfig/lkc_proto.h trunk/coreboot-v2/util/kconfig/lxdialog/ trunk/coreboot-v2/util/kconfig/lxdialog/BIG.FAT.WARNING trunk/coreboot-v2/util/kconfig/lxdialog/check-lxdialog.sh trunk/coreboot-v2/util/kconfig/lxdialog/checklist.c trunk/coreboot-v2/util/kconfig/lxdialog/dialog.h trunk/coreboot-v2/util/kconfig/lxdialog/inputbox.c trunk/coreboot-v2/util/kconfig/lxdialog/menubox.c trunk/coreboot-v2/util/kconfig/lxdialog/textbox.c trunk/coreboot-v2/util/kconfig/lxdialog/util.c trunk/coreboot-v2/util/kconfig/lxdialog/yesno.c trunk/coreboot-v2/util/kconfig/mconf.c trunk/coreboot-v2/util/kconfig/menu.c trunk/coreboot-v2/util/kconfig/qconf.cc trunk/coreboot-v2/util/kconfig/qconf.h trunk/coreboot-v2/util/kconfig/symbol.c trunk/coreboot-v2/util/kconfig/util.c trunk/coreboot-v2/util/kconfig/zconf.gperf trunk/coreboot-v2/util/kconfig/zconf.hash.c_shipped trunk/coreboot-v2/util/kconfig/zconf.l trunk/coreboot-v2/util/kconfig/zconf.tab.c_shipped trunk/coreboot-v2/util/kconfig/zconf.y trunk/coreboot-v2/util/sconfig/ trunk/coreboot-v2/util/sconfig/LICENSE trunk/coreboot-v2/util/sconfig/Makefile trunk/coreboot-v2/util/sconfig/NOTES trunk/coreboot-v2/util/sconfig/config.g trunk/coreboot-v2/util/sconfig/parsedesc.g trunk/coreboot-v2/util/sconfig/test.config trunk/coreboot-v2/util/sconfig/yapps2.py trunk/coreboot-v2/util/sconfig/yapps2.tex trunk/coreboot-v2/util/sconfig/yappsrt.py trunk/coreboot-v2/util/x86emu/Makefile.inc trunk/coreboot-v2/util/x86emu/pcbios/Makefile.inc trunk/coreboot-v2/util/x86emu/x86emu/Makefile.inc trunk/coreboot-v2/util/xcompile/ trunk/coreboot-v2/util/xcompile/xcompile Modified: trunk/coreboot-v2/documentation/Makefile trunk/coreboot-v2/src/console/console.c trunk/coreboot-v2/src/pc80/serial.c trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb trunk/coreboot-v2/util/abuild/abuild Log: Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi tested on abuild only. Acked-by: Ronald G. Minnich Added: trunk/coreboot-v2/Makefile =================================================================== --- trunk/coreboot-v2/Makefile (rev 0) +++ trunk/coreboot-v2/Makefile 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,299 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## Copyright (C) 2008 Uwe Hermann +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile))) +include .xcompile + +export top := $(shell pwd) +export src := $(top)/src +export srck := $(top)/util/kconfig +export obj := $(top)/build +export objk := $(top)/build/util/kconfig +export sconfig := $(top)/util/sconfig +export yapps2_py := $(sconfig)/yapps2.py +export config_g := $(sconfig)/config.g + + +export KERNELVERSION := 2.3 +export KCONFIG_AUTOHEADER := $(obj)/config.h +export KCONFIG_AUTOCONFIG := $(obj)/auto.conf +export COREBOOT_V2 := 1 + +CONFIG_SHELL := sh +KBUILD_DEFCONFIG := configs/defconfig +UNAME_RELEASE := $(shell uname -r) +HAVE_DOTCONFIG := $(wildcard .config) +MAKEFLAGS += -rR --no-print-directory + +# Make is silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E +HOSTCC = gcc +HOSTCXX = g++ +HOSTCFLAGS := -I$(srck) -I$(objk) -g +HOSTCXXFLAGS := -I$(srck) -I$(objk) + +DESTDIR = /opt + +DOXYGEN := doxygen +DOXYGEN_OUTPUT_DIR := doxygen + +ifeq ($(strip $(HAVE_DOTCONFIG)),) + +all: config + +else + +include $(top)/.config + +ARCHDIR-$(CONFIG_ARCH_X86) := i386 +ARCHDIR-$(CONFIG_ARCH_POWERPC) := ppc + +MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_DIR)) +export MAINBOARDDIR + +PLATFORM-y += src/arch/$(ARCHDIR-y) src/cpu src/mainboard/$(MAINBOARDDIR) +TARGETS-y := + +BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers util/x86emu +BUILD-y += util/cbfstool +BUILD-$(CONFIG_ARCH_X86) += src/pc80 + +# The primary target needs to be here before we include the +# other files + +all: coreboot + + +####################################################################### +# Build the tools + +CBFSTOOL:=$(obj)/util/cbfstool/cbfstool + +$(obj)/mainboard/$(MAINBOARDDIR)/config.py: $(yapps2_py) $(config_g) + $(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) + $(Q)python $(yapps2_py) $(config_g) $(obj)/mainboard/$(MAINBOARDDIR)/config.py + + +# needed objects that every mainboard uses +# Creation of these is architecture and mainboard independent +$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/Config.lb $(obj)/mainboard/$(MAINBOARDDIR)/config.py + $(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) + (cd $(obj)/mainboard/$(MAINBOARDDIR) ; PYTHONPATH=$(top)/util/sconfig export PYTHONPATH; python config.py $(MAINBOARDDIR) $(top) $(obj)/mainboard/$(MAINBOARDDIR)) + +$(obj)/mainboard/$(MAINBOARDDIR)/static.o: $(obj)/mainboard/$(MAINBOARDDIR)/static.c +# + +objs:=$(obj)/mainboard/$(MAINBOARDDIR)/static.o +initobjs:= +drivers:= +smmobjs:= +crt0s:= +ldscripts:= +types:=obj initobj driver smmobj +src_types:=crt0 ldscript +includemakefiles=$(foreach type,$(2), $(eval $(type)-y:=)) $(eval subdirs-y:=) $(eval include $(1)) $(if $(strip $(3)),$(foreach type,$(2),$(eval $(type)s+=$$(patsubst src/%,$(obj)/%,$$(addprefix $(dir $(1)),$$($(type)-y)))))) $(eval subdirs+=$$(subst $(PWD)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))) +evaluate_subdirs=$(eval cursubdirs:=$(subdirs)) $(eval subdirs:=) $(foreach dir,$(cursubdirs),$(eval $(call includemakefiles,$(dir)/Makefile.inc,$(types) $(src_types),$(1)))) $(if $(subdirs),$(eval $(call evaluate_subdirs, $(1)))) + +# collect all object files eligible for building +subdirs:=$(PLATFORM-y) $(BUILD-y) +$(eval $(call evaluate_subdirs, modify)) + +allobjs:=$(foreach var, $(addsuffix s,$(types)), $($(var))) +alldirs:=$(sort $(abspath $(dir $(allobjs)))) +source_with_ext=$(patsubst $(obj)/%.o,src/%.$(1),$(allobjs)) +allsrc=$(wildcard $(call source_with_ext,c) $(call source_with_ext,S)) + +POST_EVALUATION:=y + +# fetch rules (protected in POST_EVALUATION) that rely on the variables filled above +subdirs:=$(PLATFORM-y) $(BUILD-y) +$(eval $(call evaluate_subdirs)) + + +define objs_c_template +$(obj)/$(1)%.o: src/$(1)%.c + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$< +endef + +define objs_S_template +$(obj)/$(1)%.o: src/$(1)%.S + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< +endef + +define initobjs_c_template +$(obj)/$(1)%.o: src/$(1)%.c + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$< +endef + +define initobjs_S_template +$(obj)/$(1)%.o: src/$(1)%.S + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< +endef + +define drivers_c_template +$(obj)/$(1)%.o: src/$(1)%.c + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$< +endef + +define drivers_S_template +$(obj)/$(1)%.o: src/$(1)%.S + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< +endef + +define smmobjs_c_template +$(obj)/$(1)%.o: src/$(1)%.c + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$< +endef + +define smmobjs_S_template +$(obj)/$(1)%.o: src/$(1)%.S + $(Q)printf " CC $$(subst $$(shell pwd)/,,$$(@))\n" + $(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$< +endef + +usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d))))) +usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d))))) +$(eval $(call usetemplate,objs,c)) +$(eval $(call usetemplate,objs,S)) +$(eval $(call usetemplate,initobjs,c)) +$(eval $(call usetemplate,initobjs,S)) +$(eval $(call usetemplate,drivers,c)) +$(eval $(call usetemplate,drivers,S)) +$(eval $(call usetemplate,smmobjs,c)) +$(eval $(call usetemplate,smmobjs,S)) + +printall: + @echo objs:=$(objs) + @echo initobjs:=$(initobjs) + @echo drivers:=$(drivers) + @echo smmobjs:=$(smmobjs) + @echo alldirs:=$(alldirs) + @echo allsrc=$(allsrc) + +OBJS := $(patsubst %,$(obj)/%,$(TARGETS-y)) +INCLUDES := -I$(top)/src -I$(top)/src/include -I$(obj) -I$(top)/src/arch/$(ARCHDIR-y)/include +INCLUDES += -I$(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include +INCLUDES += -include $(obj)/build.h + +try-run= $(shell set -e; \ +TMP=".$$$$.tmp"; \ +if ($(1)) > /dev/null 2>&1; \ +then echo "$(2)"; \ +else echo "$(3)"; \ +fi; rm -rf "$$TMP") + +cc-option= $(call try-run,\ +$(CC) $(1) -S -xc /dev/null -o "$$TMP", $(1), $(2)) + +STACKPROTECT += $(call cc-option, -fno-stack-protector,) + +CFLAGS = $(STACKPROTECT) $(INCLUDES) $(MAINBOARD_OPTIONS) -Os -nostdinc +CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes +CFLAGS +=-Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS += -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow +CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer + +CBFS_COMPRESS_FLAG:= +ifeq "$(CONFIG_COMPRESSED_PAYLOAD_LZMA)" "1" +CBFS_COMPRESS_FLAG:=l +endif + +coreboot: prepare prepare2 $(obj)/coreboot.rom + +endif + +prepare: + $(Q)mkdir -p $(obj) + $(Q)mkdir -p $(obj)/util/kconfig/lxdialog + $(Q)test -n "$(alldirs)" && mkdir -p $(alldirs) || true + +prepare2: + $(Q)printf " GEN $(subst $(shell pwd)/,,$(obj)/build.h)\n" + $(Q)printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" > $(obj)/build.h + $(Q)printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_V2 \"$(COREBOOT_V2)\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.h + $(Q)printf "\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_COMPILE_BY \"$(shell PATH=$$PATH:/usr/ucb whoami)\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname)\"\n" >> $(obj)/build.h + $(Q)printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.h + $(Q)printf "#include \"config.h\"\n" >> $(obj)/build.h + +doxy: doxygen +doxygen: + $(Q)$(DOXYGEN) Doxyfile + +doxyclean: doxygen-clean +doxygen-clean: + $(Q)rm -rf $(DOXYGEN_OUTPUT_DIR) + +clean: doxygen-clean + $(Q)rm -f $(allobjs) build/coreboot* .xcompile + $(Q)rm -f build/option_table.* build/crt0_includes.h build/ldscript + $(Q)rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot + $(Q)rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm + $(Q)rmdir -p $(alldirs) 2>/dev/null >/dev/null || true + +distclean: clean + $(Q)rm -rf build + $(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* + +update: + $(Q)dongle.py -c /dev/term/1 build/coreboot.rom EOF + +# This include must come _before_ the pattern rules below! +# Order _does_ matter for pattern rules. +include util/kconfig/Makefile + +$(obj)/ldoptions: $(obj)/config.h +# cat $(obj)/config.h | grep -v \" |grep -v AUTOCONF_INCLUDED | grep \#define | sed s/\#define\ // | sed s/\ /\ =\ / | sed 's/$$/;/' > $(obj)/ldoptions + $(Q)awk '/^#define ([^"])* ([^"])*$$/ {print $$2 " = " $$3 ";";}' $< > $@ + +$(obj)/romcc: $(top)/util/romcc/romcc.c + $(Q)printf " HOSTCC romcc" + $(HOSTCC) -g -O2 -Wall -o $@ $< + +.PHONY: $(PHONY) prepare prepare2 clean distclean doxygen doxy coreboot + Added: trunk/coreboot-v2/documentation/Kconfig.tex =================================================================== --- trunk/coreboot-v2/documentation/Kconfig.tex (rev 0) +++ trunk/coreboot-v2/documentation/Kconfig.tex 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,464 @@ +\documentclass[10pt,letterpaper]{article} +\usepackage[latin1]{inputenc} +\usepackage{amsmath} +\usepackage{amsfonts} +\usepackage{amssymb} +\author{Ron Minnich} +\title{Kconfig usage in coreboot v2} +\begin{document} +\section{Introduction} +This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them. +\section{Kconfig variations} +Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard. + +For variables set by the user, see src/console/Kconfig. + +For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent. + +Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally. + +\section{Makefile and Makefile.inc} +There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y. + +Make is not recursive. There is only one make process. +\subsection{subdir usage} +Further includes of Makefile.inc, if needed, are done via subdir-y commands. As in Linux, the subdir can be conditional or unconditional. Conditional includes are done via subdir-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdir-y. + +We define the common rules for which variation to use below. +\subsection{object file specification} +There are several different types of objects specified in the tree. They are: +\begin{description} +\item[obj]objects for the ram part of the code +\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. +\item[initobj]seperately-compiled code for the ROM section of coreboot +\end{description} +These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax. + +\section{Example: AMD serengeti cheetah} +\subsection{mainboard/Kconfig} +Defines Vendor variables. Currently defined variables are: +Sources all Kconfig files in the vendor directories. +\input{ mainboardkconfig.tex} +\subsection{mainboard/Makefile.inc} +There is none at this time. +\subsection{mainboard//Kconfig} +We use the amd as a model. The only action currently taken is to source all Kconfig's in the +subdirectories. +\subsection{mainboard//Makefile.inc} +We use amd as a model. There is currently no Makefile.inc at this level. +\subsection{mainboard///Kconfig} +The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines +and rules in here determine everything about how a mainboard target is built. +We will use serengeti\_cheetah as a model. It defines these variables. +\input{ mainboardkconfig.tex} +\subsection{mainboard///Makefile.inc} +This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece. +Note that this is the mainboard as of August, 2009, and it may change over time. +\subsubsection{objects} +We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional: +\begin{verbatim} +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +#./ssdt.o is in northbridge/amd/amdk8/Config.lb +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o +driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +\end{verbatim} +\subsubsection{romcc legacy support} +We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define +crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the +old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally. +\begin{verbatim} +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +\end{verbatim} +\subsubsection{defines} +There are variables that should never be definable by users, as changing them will break the build or the image. These are set +in MAINBOARD\_OPTIONS. +\begin{verbatim} +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=0 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 +\end{verbatim} +\subsubsection{POST\_EVALUATION} +POST\_EVALUATION rules should be placed after this section: +\begin{verbatim} +ifdef POST_EVALUATION +\end{verbatim} +to ensure that the values of variables are correct. +Here are the post-evaluation rules for this mainboard: +\begin{verbatim} +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +\end{verbatim} +The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables. +\subsubsection{devicetree.cb} +Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard +properly, as it defines topology and chips that can be defined no other way. +Let's go through the tree. +\begin{verbatim} +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end +\end{verbatim} +This topology is always somewhat confusing to newcomers, and even to coreboot veterans. + +We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we +have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge +somewhere, since it runs memory. + + +What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the +CPU socket. So the tree is rooted at the northbridge, which has a link to an apic cluster, and then the CPU. The CPU contains +its own APIC, and will define any parameters needed. In this case, we have a northbridge of type +{\it northbridge/amd/amdk8/root\_complex}, with its won apic\_cluster device which we turn on, +which connects to a {\it cpu/amd/socket\_F}, +which has an apic, which is on. + +Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here +is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many +BIOSes) that the BSP be CPU 0; any CPU will do. +\begin{verbatim} + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 +\end{verbatim} +Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On +Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up. +\begin{verbatim} + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end +\end{verbatim} +This is the 8132, a bridge to a secondary PCI bus. +\begin{verbatim} + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end +\end{verbatim} +The 8111 is a bridge to other busses and to the legacy ISA devices such as superio. +\begin{verbatim} + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end +\end{verbatim} +The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the +2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN. +\begin{verbatim} + device pci 1.1 on end + device pci 1.2 on end +\end{verbatim} +More devices. These statements set up placeholders in the device tree. +\begin{verbatim} + device pci 1.3 on + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-2-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-2-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-3-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-3-1 + device i2c 57 on end + end + end + end + end # acpi +\end{verbatim} +These are the i2c devices. +\begin{verbatim} + device pci 1.5 off end + device pci 1.6 off end +\end{verbatim} +More placeholders. +\begin{verbatim} + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + +\end{verbatim} +These "register" commands set controls in the southbridge. +\begin{verbatim} + device pci 18.0 on end + device pci 18.0 on end +\end{verbatim} +These are the other two hypertransport links. +\begin{verbatim} + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end +\end{verbatim} +The 18.1 devices are, again, northbridge control for various k8 functions. +\begin{verbatim} + end + \end{verbatim} +That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here. +\begin{verbatim} + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + + +\end{verbatim} +\begin{verbatim} + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end +\end{verbatim} +This is a trick used to debug by creating entries in the device tree. + +\subsection{cpu socket} +The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only +the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus +of all defines and Makefile controls for building the CPU components of a board. + +\subsubsection{ /cpu/Kconfig} +Defines variables. Current variables are: +\input{cpukconfig.tex} +Sources all Kconfig files in the vendor directories. +\subsubsection{ /cpu/Makefile.inc} +Unconditionally sources all Makefile.inc in the vendor directories. + +\subsection{cpu//Kconfig} +The only action currently taken is to source all Kconfig's in the +subdirectories. +\subsection{cpu//Makefile.inc} +{\em Conditionally} source the socket directories. +Example: +\begin{verbatim} +subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F +\end{verbatim} +. +CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file. + +\subsection{cpu///Kconfig} +Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that +the socket, as much as possible, should control the models, because the models may plug into many sockets. +Socket\_F currently sets: +\input{socketfkconfig.tex} + +It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced. + +\subsection{cpu///Kconfig} +CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that +if needed. +\subsection{cpu///Makefile.inc} +The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional +compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all} +objects, because it is not possible to determine at build time what options may be needed for a given model CPU. +This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc. + +\subsection{northbridge} +\subsubsection{northbridge/Kconfig} +No variables. Source all vendor directory Kconfigs. +\subsubsection{northbridge/Kconfig} +No variables. unconditionally include all vendor Makefile.inc +\subsubsection{northbridge//Kconfig} +No variables. Source all chip directory Kconfigs. +\subsubsection{northbridge//Makefile.inc} +No variables. {\em Conditionally} include all chipset Makefile.inc. The variable +is the name of the part, e.g. +\begin{verbatim} +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 +\end{verbatim} +. +\subsubsection{northbridge///Kconfig} +Typically a small number of variables. One defines the part name. Here is an example +of the variables defined for the K8. +\begin{verbatim} +config NORTHBRIDGE_AMD_AMDK8 + bool + default n + +config AGP_APERTURE_SIZE + hex + default 0x4000000 + +config HAVE_HIGH_TABLES + int + default 1 +\end{verbatim} +\subsubsection{northbridge///Makefile.inc} +Typically very small set of rules, and very simple. +Since this file is already conditionally included, +we don't need to test for the chipset CONFIG variable. We +can therefore test other variables (which is part of the reason +we set up conditional inclusion of this file, instead +of unconditionally including it). Here is an example from AMD K8. +Note that we can make a variable conditional on the ACPI tables. +\begin{verbatim} +driver-y += northbridge.o +driver-y += misc_control.o +obj-y += get_sblk_pci1234.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o +\end{verbatim} + +\subsubsection{northbridge/Kconfig} + + + + +\subsubsection{vendor and part} +\subsection{southbridge} +\subsubsection{vendor and part} +\subsection{superio} +\subsection{i2cmux} +\subsubsection{vendor and part} + +\end{document} Modified: trunk/coreboot-v2/documentation/Makefile =================================================================== --- trunk/coreboot-v2/documentation/Makefile 2009-08-12 05:49:48 UTC (rev 4533) +++ trunk/coreboot-v2/documentation/Makefile 2009-08-12 15:00:51 UTC (rev 4534) @@ -7,7 +7,7 @@ FIGS=codeflow.pdf hypertransport.pdf -all: LinuxBIOS-AMD64.pdf +all: LinuxBIOS-AMD64.pdf Kconfig.pdf SVG2PDF=$(shell which svg2pdf) INKSCAPE=$(shell which inkscape) @@ -39,9 +39,34 @@ LinuxBIOS-AMD64.pdf: $(FIGS) LinuxBIOS-AMD64.tex LinuxBIOS-AMD64.toc $(PDFLATEX) LinuxBIOS-AMD64.tex +Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex + $(PDFLATEX) $< + +# quick, somebody! make me a macro! +mainboardkconfig.tex: ../src/mainboard/Kconfig + echo '\begin{verbatim}' > $@ + grep '^config' $< | awk '{print $2}' >>$@ + echo '\end{verbatim}' >> $@ + +skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig + echo '\begin{verbatim}' > $@ + grep '^config' $< | awk '{print $2}' >>$@ + echo '\end{verbatim}' >> $@ + +cpukconfig.tex: ../src/cpu/Kconfig + echo '\begin{verbatim}' > $@ + grep '^config' $< | awk '{print $2}' >>$@ + echo '\end{verbatim}' >> $@ + +socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig + echo '\begin{verbatim}' > $@ + grep '^config' $< | awk '{print $2}' >>$@ + echo '\end{verbatim}' >> $@ + + clean: - rm -f *.aux *.idx *.log *.toc *.out $(FIGS) + rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex distclean: clean - rm -f LinuxBIOS-AMD64.pdf + rm -f LinuxBIOS-AMD64.pdf mainboardkconfig.tex Added: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig (rev 0) +++ trunk/coreboot-v2/src/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,275 @@ +## +## This file is part of the coreboot repair project. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +mainmenu "Coreboot Configuration" + +source src/mainboard/Kconfig +source src/arch/i386/Kconfig +source src/arch/ppc/Kconfig +source src/devices/Kconfig +source src/northbridge/Kconfig +source src/southbridge/Kconfig +source src/superio/Kconfig +source src/cpu/Kconfig + +config CBFS + bool + default y + +config HAVE_HIGH_TABLES + bool + default y + +config PCI_BUS_SEGN_BITS + int + default 0 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0 + +config CPU_ADDR_BITS + int + default 36 + +config XIP_ROM_BASE + hex + default 0xfffe0000 + +config XIP_ROM_SIZE + hex + default 0x20000 + +config LB_CKS_RANGE_START + int + default 49 + +config LB_CKS_RANGE_END + int + default 125 + +config LB_CKS_LOC + int + default 126 + +config LOGICAL_CPUS + int + default 1 + +config PCI_ROM_RUN + int + default 0 + +config HT_CHAIN_UNITID_BASE + int + default 1 + +config HT_CHAIN_END_UNITID_BASE + int + default 32 + +config HEAP_SIZE + hex + default 0x2000 + +config COREBOOT_V2 + bool + default y + +config COREBOOT_V4 + bool + default y + +config DEBUG + bool + default n + +config USE_PRINTK_IN_CAR + bool + default n + +config USE_OPTION_TABLE + bool + default n + +config MAX_CPUS + int + default 1 + +config MMCONF_SUPPORT_DEFAULT + bool + default n + +config MMCONF_SUPPORT + bool + default n + +config LB_MEM_TOPK + int + default 2048 + +config MULTIBOOT + bool + default n + +config COMPRESSED_PAYLOAD_LZMA + bool + default y + +config COMPRESSED_PAYLOAD_NRV2B + bool + default n + +source src/console/Kconfig + +config HAVE_ACPI_RESUME + bool + default n + +config ACPI_SSDTX_NUM + int + default 0 + +config HAVE_ACPI_TABLES + bool + default n + +config HAVE_FALLBACK_BOOT + bool + default y + +config USE_FALLBACK_IMAGE + bool + default y + +config HAVE_HARD_RESET + bool + default n + +config HAVE_INIT_TIMER + bool + default n + +config HAVE_MAINBOARD_RESOURCES + bool + default n + +config HAVE_MOVNTI + bool + default y + +config HAVE_MP_TABLE + bool + default n + +config HAVE_OPTION_TABLE + bool + default y + +config HAVE_PIRQ_TABLE + bool + default n + +config PIRQ_ROUTE + bool + default n + +config HAVE_SMI_HANDLER + bool + default n + +config PCI_IO_CFG_EXT + bool + default n + +config IOAPIC + bool + default n + +menu "Drivers" + +endmenu + +menu "Payload" + +config COMPRESSED_PAYLOAD_LZMA + bool "Use LZMA compression for payloads" + default yes + +choice + prompt "Payload type" + default PAYLOAD_NONE + +config PAYLOAD_ELF + bool "An ELF executable payload file" + help + Select this option if you have a payload image (an ELF file) + which coreboot should run as soon as the basic hardware + initialization is completed. + + You will be able to specify the location and file name of the + payload image later. + +config PAYLOAD_NONE + bool "No payload" + help + Select this option if you want to create an "empty" coreboot + ROM image for a certain mainboard, i.e. a coreboot ROM image + which does not yet contain a payload. + + For such an image to be useful, you have to use the 'lar' tool + to add a payload to the ROM image later. + +endchoice + +config NORMAL_PAYLOAD_FILE + string "Normal payload path and filename" + depends on PAYLOAD_ELF + default "payload.elf" + help + The path and filename of the ELF executable file to use as normal payload. + +config FALLBACK_PAYLOAD_FILE + string "Fallback payload path and filename" + depends on PAYLOAD_ELF + default "payload.elf" + help + The path and filename of the ELF executable file to use as fallback payload. + +endmenu + +config GDB_STUB + bool "Enable GDB debugging support" + default y + help + If this is set, then you will be able to set breakpoints for gdb debugging. + See: src/arch/i386/lib/c_start.S + Added: trunk/coreboot-v2/src/arch/i386/Kconfig =================================================================== --- trunk/coreboot-v2/src/arch/i386/Kconfig (rev 0) +++ trunk/coreboot-v2/src/arch/i386/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +config ARCH_X86 + boolean + help + This option is used to set the architecture of a mainboard. + It is usually set in mainboard/*/Kconfig. + +config ARCH + string + default i386 + depends on ARCH_X86 + help + This is the name of the respective subdirectory in arch/. + +config ROMBASE + hex + default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048 + default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024 + default 0xfff80000 if COREBOOT_ROMSIZE_KB_512 + default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256 + default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128 + +config PAYLOAD_SIZE + hex + default 0 + +config ROM_PAYLOAD_START + hex + default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048 + default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024 + default 0xfff80000 if COREBOOT_ROMSIZE_KB_512 + default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256 + default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128 + +config ROM_IMAGE_SIZE + hex + default 0x200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x80000 if COREBOOT_ROMSIZE_KB_512 + default 0x40000 if COREBOOT_ROMSIZE_KB_256 + default 0x20000 if COREBOOT_ROMSIZE_KB_128 + +config RAMBASE + hex + default 0x100000 + +config STACK_SIZE + hex + default 0x8000 + + +menu "Misc Options" + +config MAX_REBOOT_CNT + int "Maximum Reboot Count" + default 3 + +endmenu + + Added: trunk/coreboot-v2/src/arch/i386/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/arch/i386/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,98 @@ +####################################################################### +# Take care of subdirectories +subdirs-y += boot +subdirs-y += init +subdirs-y += lib +subdirs-y += smp + +obj-y += ../../option_table.o + +ifdef POST_EVALUATION +####################################################################### +# Build the final rom image + +$(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL) + $(Q)rm -f $@ + $(Q)$(CBFSTOOL) $@ create $(shell expr 1024 \* $(CONFIG_COREBOOT_ROMSIZE_KB)) 131072 $(obj)/coreboot.bootblock + $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram normal/coreboot_ram $(CBFS_COMPRESS_FLAG) + $(Q)if [ -f fallback/coreboot_apc ]; \ + then \ + $(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \ + fi + $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram fallback/coreboot_ram $(CBFS_COMPRESS_FLAG) +ifeq ($(CONFIG_PAYLOAD_NONE),y) + $(Q)printf " PAYLOAD none (as specified by user)\n" +else + printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n" + $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_COMPRESS_FLAG) + printf " PAYLOAD $(CONFIG_NORMAL_PAYLOAD_FILE) $(COMPRESSFLAG)\n" + $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_NORMAL_PAYLOAD_FILE) normal/payload $(CBFS_COMPRESS_FLAG) + $(CBFSTOOL) ./build/coreboot.rom print +endif + + +####################################################################### +# Build the bootblock + +BOOTBLOCK_SIZE=65536 + +$(obj)/coreboot.bootblock: $(obj)/coreboot.strip + $(Q)printf " CREATE $(subst $(obj)/,,$(@))\n" + $(Q)dd if=$< of=$(obj)/coreboot.bootblock.one obs=$(BOOTBLOCK_SIZE) conv=sync + $(Q)cat $(obj)/coreboot.bootblock.one $(obj)/coreboot.bootblock.one > $(obj)/coreboot.bootblock + +$(obj)/coreboot.strip: $(obj)/coreboot + $(Q)printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(Q)$(OBJCOPY) -O binary $< $@ + +$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions + $(Q)printf 'INCLUDE "ldoptions"\n' > $@ + $(Q)printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript)"\n)' >> $@ + +$(obj)/crt0_includes.h: $(crt0s) + $(Q)printf '$(foreach crt0,$(obj)/config.h $(crt0s),#include "$(crt0)"\n)' > $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s + $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h + $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ + +$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld + $(Q)printf " LINK $(subst $(obj)/,,$(@))\n" + $(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs) + $(Q)$(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map + +####################################################################### +# i386 specific tools + +$(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout + $(Q)printf " OPTION $(subst $(obj)/,,$(@))\n" + $(Q)$(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c + +$(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h + $(Q)printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(Q)$(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $< -o $@ + +####################################################################### +# Build the coreboot_ram (stage 2) + +$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions + $(Q)printf " CC $(subst $(obj)/,,$(@))\n" + $(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o + $(Q)$(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map + +$(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) + $(Q)printf " CC $(subst $(obj)/,,$(@))\n" + $(Q)$(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-\( $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\) + +$(obj)/coreboot.a: $(objs) + $(Q)printf " AR $(subst $(obj)/,,$(@))\n" + $(Q)rm -f $(obj)/coreboot.a + $(Q)$(AR) cr $(obj)/coreboot.a $(objs) + + +####################################################################### +# done + +endif Added: trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,10 @@ + +obj-y += boot.o +obj-y += coreboot_table.o +obj-$(CONFIG_MULTIBOOT) += multiboot.o +obj-y += tables.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += pirq_routing.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.o +obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S + Added: trunk/coreboot-v2/src/arch/i386/init/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/arch/i386/init/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,15 @@ +obj-y += c_start.o +obj-y += cpu.o +obj-y += pci_ops_conf1.o +obj-y += pci_ops_conf2.o +obj-y += pci_ops_mmconf.o +obj-y += pci_ops_auto.o +obj-y += exception.o + +initobj-y += printk_init.o +initobj-y += cbfs_and_run.o + +ifdef POST_EVALUATION +$(obj)/arch/i386/lib/console.o :: $(obj)/build.h +endif + Added: trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,5 @@ +obj-$(CONFIG_HAVE_MP_TABLE) += mpspec.o +# what about this: how awkward. +#object ioapic.o CONFIG_IOAPIC + + Added: trunk/coreboot-v2/src/arch/ppc/Kconfig =================================================================== --- trunk/coreboot-v2/src/arch/ppc/Kconfig (rev 0) +++ trunk/coreboot-v2/src/arch/ppc/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,13 @@ +config ARCH_POWERPC + boolean + help + This option is used to set the architecture of a mainboard. + It is usually set in mainboard/*/Kconfig. + +config ARCH + string + default ppc + depends on ARCH_POWERPC + help + This is the name of the respective subdirectory in arch/. + Added: trunk/coreboot-v2/src/boot/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/boot/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/boot/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +obj-y += hardwaremain.o +obj-y += selfboot.o Added: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig (rev 0) +++ trunk/coreboot-v2/src/console/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,40 @@ +menu "Console Options" + +config SERIAL_CONSOLE + bool "See output on the serial port console" + default y + +config TTYS0_BASE + hex "I/O base for the serial port (default 0x3f8)" + depends on SERIAL_CONSOLE + default 0x3f8 + +config SERIAL_SET_SPEED + bool "Override the serial console baud rate" + default y + depends on SERIAL_CONSOLE + +config TTYS0_BAUD + int "Serial console baud rate (default 115200)" + depends on SERIAL_SET_SPEED + default 115200 + +config USBDEBUG_DIRECT + bool "Support a USB debug dongle. Not supported on all chipsets. FIX DEPENDENCY HERE" + default n + +config CONSOLE_VGA + bool + default n + +config MAXIMUM_CONSOLE_LOGLEVEL + int + default 9 + +config DEFAULT_CONSOLE_LOGLEVEL + int + default 9 + +endmenu + + Added: trunk/coreboot-v2/src/console/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/console/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/console/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,12 @@ +obj-y += printk.o +obj-y += console.o +obj-y += vtxprintf.o +obj-y += vsprintf.o +initobj-y += vtxprintf.o +initobj-y += vsprintf.o +driver-$(CONFIG_SERIAL_CONSOLE) += uart8250_console.o +driver-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct_console.o +driver-$(CONFIG_CONSOLE_VGA) += vga_console.o +driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o +driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o +driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o Modified: trunk/coreboot-v2/src/console/console.c =================================================================== --- trunk/coreboot-v2/src/console/console.c 2009-08-12 05:49:48 UTC (rev 4533) +++ trunk/coreboot-v2/src/console/console.c 2009-08-12 15:00:51 UTC (rev 4534) @@ -8,8 +8,6 @@ #include -static int initialized; - /* initialize the console */ void console_init(void) { @@ -22,7 +20,6 @@ continue; driver->init(); } - initialized = 1; } static void __console_tx_byte(unsigned char byte) @@ -45,8 +42,6 @@ void console_tx_byte(unsigned char byte) { - if (!initialized) - return; if (byte == '\n') __console_tx_byte('\r'); __console_tx_byte(byte); @@ -55,8 +50,6 @@ unsigned char console_rx_byte(void) { struct console_driver *driver; - if (!initialized) - return 0; for(driver = console_drivers; driver < econsole_drivers; driver++) { if (driver->tst_byte) break; @@ -70,8 +63,6 @@ int console_tst_byte(void) { struct console_driver *driver; - if (!initialized) - return 0; for(driver = console_drivers; driver < econsole_drivers; driver++) if (driver->tst_byte) return driver->tst_byte(); Added: trunk/coreboot-v2/src/cpu/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,18 @@ +#source src/cpu/amd/Kconfig +source src/cpu/emulation/Kconfig +source src/cpu/intel/Kconfig +source src/cpu/via/Kconfig +source src/cpu/x86/Kconfig +source src/cpu/ppc/Kconfig + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 if CPU_INTEL_CORE + +config DCACHE_RAM_SIZE + hex + default 0x8000 if CPU_INTEL_CORE + +config SMP + bool + default n Added: trunk/coreboot-v2/src/cpu/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,8 @@ +#input amd +subdirs-y += intel +subdirs-y += via +subdirs-y += emulation +#input ppc +#input simple_init +#input via +#input x86 Added: trunk/coreboot-v2/src/cpu/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,8 @@ +source src/cpu/amd/socket_754/Kconfig +source src/cpu/amd/socket_939/Kconfig +source src/cpu/amd/socket_940/Kconfig +source src/cpu/amd/socket_AM2/Kconfig +source src/cpu/amd/socket_AM2r2/Kconfig +source src/cpu/amd/socket_F/Kconfig +source src/cpu/amd/socket_F_1207/Kconfig +source src/cpu/amd/socket_S1G1/Kconfig Added: trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,3 @@ +config CPU_AMD_SOCKET_F + bool + default false Added: trunk/coreboot-v2/src/cpu/emulation/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/emulation/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +source src/cpu/emulation/qemu-x86/Kconfig + Added: trunk/coreboot-v2/src/cpu/emulation/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/emulation/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += qemu-x86 Added: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,4 @@ +config CPU_EMULATION_QEMU_X86 + bool + default false + Added: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +obj-$(CONFIG_CPU_EMULATION_QEMU_X86) += northbridge.o Added: trunk/coreboot-v2/src/cpu/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,4 @@ +source src/cpu/intel/model_6ex/Kconfig +source src/cpu/intel/model_6fx/Kconfig +source src/cpu/intel/socket_mFCPGA478/Kconfig +source src/cpu/intel/socket_PGA370/Kconfig \ No newline at end of file Added: trunk/coreboot-v2/src/cpu/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,14 @@ +# Note: from here on down, we are socket-centric. Socket choice determines what other cpu files are included. +# Therefore: +# ONLY include Makefile.inc from socket directories! + +subdirs-y += speedstep +subdirs-y += socket_mFCPGA478 +subdirs-y += socket_PGA370 + +#socket_mPGA478 +#socket_mPGA479M +#socket_mPGA603 +#socket_mPGA604 +#socket_mPGA604_533Mhz +#socket_mPGA604_800Mhz Added: trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +obj-y += intel_sibling.o Added: trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +obj-y += microcode.o Added: trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +driver-y += model_69x_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +driver-y += model_6dx_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,4 @@ +config CPU_INTEL_CORE + bool + default n + select SMP Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +driver-y += model_6ex_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# select HAVE_MOVNTI Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +driver-y += model_6fx_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ron Minnich +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += model_6xx_init.o + Added: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_INTEL_SOCKET_PGA370 + bool + default false Added: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_CPU_INTEL_SOCKET_PGA370),y) + obj-y += socket_PGA370.o + subdirs-y += ../model_6xx + subdirs-y += ../../x86/tsc + subdirs-y += ../../x86/mtrr + subdirs-y += ../../x86/fpu + subdirs-y += ../../x86/mmx + subdirs-y += ../../x86/sse + subdirs-y += ../../x86/lapic + subdirs-y += ../../x86/cache + subdirs-y += ../../x86/smm + subdirs-y += ../microcode +endif + Added: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,3 @@ +config CPU_INTEL_SOCKET_MFCPGA478 + bool + default false Added: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,17 @@ +ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478),y) + obj-y += socket_mFCPGA478.o + subdirs-y += ../model_69x + subdirs-y += ../model_6dx + subdirs-y += ../model_6ex + subdirs-y += ../model_6fx + subdirs-y += ../../x86/tsc + subdirs-y += ../../x86/mtrr + subdirs-y += ../../x86/fpu + subdirs-y += ../../x86/mmx + subdirs-y += ../../x86/sse + subdirs-y += ../../x86/lapic + subdirs-y += ../../x86/cache + subdirs-y += ../../x86/smm + subdirs-y += ../microcode + subdirs-y += ../hyperthreading +endif Added: trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_HAVE_ACPI_TABLES), y) +ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478), y) + obj-y += acpi.o +endif +endif Added: trunk/coreboot-v2/src/cpu/ppc/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/ppc/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/cpu/ppc/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/ppc/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,6 @@ +#subdirs-y += ../simple_init +#subdirs-y += mpc74xx +#subdirs-y += ppc4xx +#subdirs-y += ppc7xx +#subdirs-y += ppc970 + Added: trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +obj-y += simple_cpu_init.o Added: trunk/coreboot-v2/src/cpu/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/via/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/via/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +source src/cpu/via/model_c7/Kconfig Added: trunk/coreboot-v2/src/cpu/via/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/via/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/via/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#subdirs-y += model_c7 +subdirs-y += model_c7 Added: trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,3 @@ +config CPU_VIA_C7 + bool + default n Added: trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,13 @@ +ifeq ($(CONFIG_CPU_VIA_C7),y) + subdirs-y += ../../x86/tsc + subdirs-y += ../../x86/mtrr + subdirs-y += ../../x86/fpu + subdirs-y += ../../x86/mmx + subdirs-y += ../../x86/sse + subdirs-y += ../../x86/lapic + subdirs-y += ../../x86/cache + subdirs-y += ../../x86/smm + subdirs-y += ../../intel/microcode +endif + +obj-y += model_c7_init.o Added: trunk/coreboot-v2/src/cpu/x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/x86/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,11 @@ +config SERIAL_CPU_INIT + bool + default y + +config XIP_ROM_BASE + hex + default 0xfffe0000 + +config XIP_ROM_BASE + hex + default 0x2000 Added: trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +obj-y += cache.o Added: trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,4 @@ +obj-y += lapic.o +obj-y += lapic_cpu_init.o +obj-y += secondary.o + Added: trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +obj-y += mtrr.o Added: trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +##if CONFIG_HAVE_SMI_HANDLER +## object smmrelocate.S +## +## smmobject smmhandler.S +## smmobject smihandler.o +## +## makerule smm.o +## depends "$(SMM-OBJECTS) $(TOP)/src/console/printk.o $(TOP)/src/console/vtxprintf.o $(LIBGCC_FILE_NAME)" +## action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^" +## end +## +## makerule smm +## depends "smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" +## action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o" +## action "$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map" +## action "$(OBJCOPY) -O binary smm.elf smm" +## end +## +## makerule smm_bin.c +## depends "smm" +## action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';') > smm_bin.c" +## end +## +## object ./smm_bin.o +##end Added: trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,7 @@ +obj-y += delay_tsc.o + +# default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0 +# if CONFIG_UDELAY_TSC +# default CONFIG_HAVE_INIT_TIMER=1 +# object delay_tsc.o +# end Added: trunk/coreboot-v2/src/devices/Kconfig =================================================================== --- trunk/coreboot-v2/src/devices/Kconfig (rev 0) +++ trunk/coreboot-v2/src/devices/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +menu "Devices" + +config VGA_ROM_RUN + bool + help + Execute PCI/AGP option ROMs if available. This is required to + enable PCI/AGP VGA plugin cards. + +choice + prompt "Execute PCI Option ROMs" + default PCI_OPTION_ROM_RUN_REALMODE + help + Execute PCI/AGP option ROMs if available. You can choose to + execute PCI option ROMs natively (32bit x86 system required), + in an emulator (x86emu), or ignore option ROM execution. + + config PCI_OPTION_ROM_RUN_REALMODE + prompt "Run VGA ROMs" + bool + select VGA_ROM_RUN + help + Execute PCI/AGP option ROMs if available. This is required to + enable PCI/AGP VGA plugin cards. + + config NO_RUN + prompt "DO NOT Run VGA ROMs" + bool + help + Execute PCI/AGP option ROMs if available. This is required to + enable PCI/AGP VGA plugin cards. + +endchoice +endmenu Added: trunk/coreboot-v2/src/devices/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/devices/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/devices/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,21 @@ +obj-y += device.o +obj-y += root_device.o +obj-y += device_util.o +obj-y += pci_device.o +obj-y += hypertransport.o +obj-y += pcix_device.o +obj-y += pciexp_device.o +obj-y += agp_device.o +obj-y += cardbus_device.o +obj-y += pnp_device.o +obj-y += pci_ops.o +obj-y += smbus_ops.o + +ifeq ($(CONFIG_PCI_ROM_RUN),y) +obj-$(CONFIG_PCI_ROM_RUN) += pci_rom.o +subdirs-$(CONFIG_PCI_ROM_RUN) += ../../util/x86emu +else +obj-$(CONFIG_VGA_ROM_RUN) += pci_rom.o +subdirs-$(CONFIG_VGA_ROM_RUN) += ../../util/x86emu +endif + Added: trunk/coreboot-v2/src/drivers/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/drivers/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/drivers/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += pci Added: trunk/coreboot-v2/src/drivers/pci/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/drivers/pci/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/drivers/pci/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += onboard Added: trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +obj-y += onboard.o Added: trunk/coreboot-v2/src/lib/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/lib/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/lib/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,29 @@ +obj-y += clog2.o +obj-y += uart8250.o +obj-y += memset.o +obj-y += memcpy.o +obj-y += memcmp.o +obj-y += memmove.o +obj-y += malloc.o +obj-y += delay.o +obj-y += fallback_boot.o +obj-y += compute_ip_checksum.o +obj-y += version.o +obj-y += cbfs.o +obj-y += lzma.o +#obj-y += lzmadecode.o + +initobj-y += uart8250.o +initobj-y += memset.o +initobj-y += memcpy.o +initobj-y += memcmp.o +initobj-y += cbfs.o +initobj-y += lzma.o +#initobj-y += lzmadecode.o + +obj-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct.o +obj-$(CONFIG_COMPRESSED_PAYLOAD_LZMA) += lzma.o + +ifdef POST_EVALUATION +$(obj)/lib/version.o :: $(obj)/build.h +endif Added: trunk/coreboot-v2/src/mainboard/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,343 @@ + +menu "Mainboard" + +choice + prompt "Mainboard vendor" + default VENDOR_EMULATION + +config VENDOR_ATREND + bool "A-Trend" + help + Select this option for systems from the vendor. + +config VENDOR_ABIT + bool "ABIT" + help + Select this option for systems from the vendor. + +config VENDOR_ADVANTECH + bool "Advantech" + help + Select this option for systems from the vendor. + +config VENDOR_AGAMI + bool "Agami" + help + Select this option for systems from the vendor. + +config VENDOR_AMD + bool "AMD" + help + Select this option for systems from the vendor. + +config VENDOR_ARIMA + bool "Arima" + help + Select this option for systems from the vendor. + +config VENDOR_ARTEC + bool "Artec Group" + help + Select this option for systems from the vendor. + +config VENDOR_ASI + bool "ASI" + help + Select this option for systems from the vendor. + +config VENDOR_ASUS + bool "ASUS" + help + Select this option for systems from the vendor. + +config VENDOR_AXUS + bool "AXUS" + help + Select this option for systems from the vendor. + +config VENDOR_AZZA + bool "Azza" + help + Select this option for systems from the vendor. + +config VENDOR_BCOM + bool "BCOM" + help + Select this option for systems from the vendor. + +config VENDOR_BIOSTAR + bool "Biostar" + help + Select this option for systems from the vendor. + +config VENDOR_BROADCOM + bool "Broadcom" + help + Select this option for systems from the vendor. + +config VENDOR_COMPAQ + bool "Compaq" + help + Select this option for systems from the vendor. + +config VENDOR_DELL + bool "DELL" + help + Select this option for systems from the vendor. + +config VENDOR_DIGITALLOGIC + bool "Digital Logic" + help + Select this option for systems from the vendor. + +config VENDOR_EAGLELION + bool "Eagle Lion" + help + Select this option for systems from the vendor. + +config VENDOR_EMBEDDEDPLANET + bool "Embedded Planet" + help + Select this option for systems from the vendor. + +config VENDOR_EMULATION + bool "Emulation" + help + Select this option for various system emulators, such as QEMU. + +config VENDOR_GIGABYTE + bool "Gigabyte" + help + Select this option for systems from the vendor. + +config VENDOR_HP + bool "HP" + help + Select this option for systems from the vendor. + +config VENDOR_IBM + bool "IBM" + help + Select this option for systems from the vendor. + +config VENDOR_IEI + bool "IEI" + help + Select this option for systems from the vendor. + +config VENDOR_INTEL + bool "Intel" + help + Select this option for systems from the vendor. + +config VENDOR_IWILL + bool "Iwill" + help + Select this option for systems from the vendor. + +config VENDOR_JETWAY + bool "Jetway" + help + Select this option for systems from the vendor. + +config VENDOR_KONTRON + bool "Kontron" + help + Select this option for systems from the vendor. + +config VENDOR_LIPPERT + bool "Lippert" + help + Select this option for systems from the vendor. + +config VENDOR_MOTOROLA + bool "Motorola" + help + Select this option for systems from the vendor. + +config VENDOR_MSI + bool "MSI" + help + Select this option for systems from the vendor. + +config VENDOR_NEC + bool "NEC" + help + Select this option for systems from the vendor. + +config VENDOR_NEWISYS + bool "Newisys" + help + Select this option for systems from the vendor. + +config VENDOR_NVIDIA + bool "NVidia" + help + Select this option for systems from the vendor. + +config VENDOR_OLPC + bool "OLPC" + help + Select this option for systems from the vendor. + +config VENDOR_PCENGINES + bool "PC Engines" + help + Select this option for systems from the vendor. + +config VENDOR_RCA + bool "RCA" + help + Select this option for systems from the vendor. + +config VENDOR_SUNW + bool "SUN Microsystems" + help + Select this option for systems from the vendor. + +config VENDOR_SUPERMICRO + bool "Supermicro" + help + Select this option for systems from the vendor. + +config VENDOR_TECHNEXION + bool "Technexion" + help + Select this option for systems from the vendor. + +config VENDOR_THOMSON + bool "Thomson" + help + Select this option for systems from the vendor. + +config VENDOR_TOTALIMPACT + bool "Total Impact" + help + Select this option for systems from the vendor. + +config VENDOR_TYAN + bool "Tyan" + help + Select this option for systems from the vendor. + +config VENDOR_VIA + bool "VIA" + help + Select this option for systems from the vendor. + +endchoice + +config MAINBOARD_VENDOR + string + default "EMULATION" + depends on VENDOR_EMULATION + +config MAINBOARD_VENDOR + string + default "KONTRON" + depends on VENDOR_KONTRON + +config MAINBOARD_VENDOR + string + default "VIA" + depends on VENDOR_VIA + +config MAINBOARD_VENDOR + string + default "AMD" + depends on VENDOR_AMD + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1019 + depends on VENDOR_VIA + +source "src/mainboard/a-trend/Kconfig" +source "src/mainboard/abit/Kconfig" +source "src/mainboard/advantech/Kconfig" +source "src/mainboard/amd/Kconfig" +source "src/mainboard/arima/Kconfig" +source "src/mainboard/artecgroup/Kconfig" +source "src/mainboard/asi/Kconfig" +source "src/mainboard/asus/Kconfig" +source "src/mainboard/axus/Kconfig" +source "src/mainboard/azza/Kconfig" +source "src/mainboard/bcom/Kconfig" +source "src/mainboard/biostar/Kconfig" +source "src/mainboard/broadcom/Kconfig" +source "src/mainboard/compaq/Kconfig" +source "src/mainboard/dell/Kconfig" +source "src/mainboard/digitallogic/Kconfig" +source "src/mainboard/eaglelion/Kconfig" +source "src/mainboard/embeddedplanet/Kconfig" +source "src/mainboard/emulation/Kconfig" +source "src/mainboard/gigabyte/Kconfig" +source "src/mainboard/hp/Kconfig" +source "src/mainboard/ibm/Kconfig" +source "src/mainboard/iei/Kconfig" +source "src/mainboard/intel/Kconfig" +source "src/mainboard/iwill/Kconfig" +source "src/mainboard/jetway/Kconfig" +source "src/mainboard/kontron/Kconfig" +source "src/mainboard/lippert/Kconfig" +source "src/mainboard/motorola/Kconfig" +source "src/mainboard/msi/Kconfig" +source "src/mainboard/nec/Kconfig" +source "src/mainboard/newisys/Kconfig" +source "src/mainboard/nvidia/Kconfig" +source "src/mainboard/olpc/Kconfig" +source "src/mainboard/pcengines/Kconfig" +source "src/mainboard/rca/Kconfig" +source "src/mainboard/sunw/Kconfig" +source "src/mainboard/supermicro/Kconfig" +source "src/mainboard/technexion/Kconfig" +source "src/mainboard/technologic/Kconfig" +source "src/mainboard/televideo/Kconfig" +source "src/mainboard/thomson/Kconfig" +source "src/mainboard/totalimpact/Kconfig" +source "src/mainboard/tyan/Kconfig" +source "src/mainboard/via/Kconfig" + +choice + prompt "ROM chip size" + default COREBOOT_ROMSIZE_KB_256 + +config COREBOOT_ROMSIZE_KB_128 + bool "128 KB" + help + Choose this option if you have a 128 KB ROM chip. + +config COREBOOT_ROMSIZE_KB_256 + bool "256 KB" + help + Choose this option if you have a 256 KB ROM chip. + +config COREBOOT_ROMSIZE_KB_512 + bool "512 KB" + help + Choose this option if you have a 512 KB ROM chip. + +config COREBOOT_ROMSIZE_KB_1024 + bool "1024 KB (1 MB)" + help + Choose this option if you have a 1024 KB (1 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_2048 + bool "2048 KB (2 MB)" + help + Choose this option if you have a 2048 KB (2 MB) ROM chip. + +endchoice + +config COREBOOT_ROMSIZE_KB + int + default 128 if COREBOOT_ROMSIZE_KB_128 + default 256 if COREBOOT_ROMSIZE_KB_256 + default 512 if COREBOOT_ROMSIZE_KB_512 + default 1024 if COREBOOT_ROMSIZE_KB_1024 + default 2048 if COREBOOT_ROMSIZE_KB_2048 + help + Map the config names to an integer. + +endmenu + Added: trunk/coreboot-v2/src/mainboard/a-trend/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/a-trend/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,69 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83627hf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + io 0x60 = 0x00 + end + device pnp 3f0.7 on # Game port / MIDI / GPIO 1 + io 0x60 = 0x201 + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 3f0.8 off # GPIO 2 / WDT + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a off # ACPI + end + device pnp 3f0.b off # HWM (TODO) + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + device pci c.0 on end # Onboard audio (ES1371) + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/abit/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/abit/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE, UDMA/33 (part of 82371EB) + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + device pci 13.0 on end # IDE, UDMA/66 (HPT366 controller) + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/advantech/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/advantech/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,56 @@ +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 12.0 on # ISA bridge + chip superio/winbond/w83977f # SUper I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.4 on # RTC / On-Now control + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # IR + # TODO? + end + device pnp 3f0.7 on # GPIO 1 + # TODO? + end + device pnp 3f0.8 on # GPIO 2 + # TODO? + end + end + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio (onboard) + device pci 12.4 on end # VGA + device pci 13.0 on end # USB + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end + chip cpu/amd/model_gx1 # CPU + end +end Added: trunk/coreboot-v2/src/mainboard/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +source "src/mainboard/amd/serengeti_cheetah/Kconfig" \ No newline at end of file Added: trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,68 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet + device pci e.0 on end # Slot1 + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # Com2 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,117 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_S1G1 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff00000" + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff00000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex + Added: trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,41 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + register "lpc_serirq_enable" = "0x00001002" + register "lpc_serirq_polarity" = "0x0000EFFD" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "1" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci b.0 on end # Slot 3 + device pci c.0 on end # Slot 4 + device pci d.0 on end # Slot 1 + device pci e.0 on end # Slot 2 + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,77 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_AM2 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge, K8 HT Configuration + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + # device pci 0.1 off end # CLK + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff00000" + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff00000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 off end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 off end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 off end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x438d + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.1 on end # K8 Address Map + device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode + device pci 18.3 on end # K8 Miscellaneous Control + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex + Added: trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,21 @@ +chip northbridge/amd/gx2 + device apic_cluster 0 on + chip cpu/amd/model_gx2 + device apic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x80" # enabled with default timing + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.4 on end # UHCI + end + end +end + Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,49 @@ +choice + prompt "Mainboard model" + depends on VENDOR_AMD + +config BOARD_AMD_SERENGETI_CHEETAH + bool "SERENGETI_CHEETAH" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SUPERIO_WINBOND_W83627THF + select PIRQ_TABLE + select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + help + AMD Serengeti Series mainboards +endchoice + +config MAINBOARD_DIR + string + default amd/serengeti_cheetah + depends on BOARD_AMD_SERENGETI_CHEETAH + +#config DCACHE_RAM_BASE +# hex +# default 0xffdf8000 +# depends on BOARD_AMD_SERENGETI_CHEETAH +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_AMD_SERENGETI_CHEETAH + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_AMD_SERENGETI_CHEETAH + +config LB_CKS_LOC + int + default 123 + depends on BOARD_AMD_SERENGETI_CHEETAH + +config MAINBOARD_PART_NUMBER + string + default "Serengeti-Cheetah" + depends on BOARD_AMD_SERENGETI_CHEETAH Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,95 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +#./ssdt.o is in northbridge/amd/amdk8/Config.lb +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=1 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 \ + -DCONFIG_MMCONF_SUPPORT=1 \ + -DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,159 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-2-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-2-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-3-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-3-1 + device i2c 57 on end + end + end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + + + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end + + Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,152 @@ +chip northbridge/amd/amdfam10/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F_1207 #L1 and DDR2 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + end + end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end + end #pci_domain + #for node 32 to node 63 +# device pci_domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +# end #pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # hard reset +# device pnp 0.9 off end # mcp55 +# device pnp 0.a on end # GH ext table +# end + +end + + Added: trunk/coreboot-v2/src/mainboard/arima/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/arima/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,196 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on # PCIX bridge + ## On board NIC A + #chip drivers/generic/generic + # device pci 3.0 on + # irq 0 = 0x13 + # end + #end + ## On board NIC B + #chip drivers/generic/generic + # device pci 4.0 on + # irq 0 = 0x13 + # end + #end + ## PCI Slot 3 + #chip drivers/generic/generic + # device pci 1.0 on + # irq 0 = 0x11 + # irq 1 = 0x12 + # irq 2 = 0x13 + # irq 3 = 0x10 + # end + #end + ## PCI Slot 4 + #chip drivers/generic/generic + # device pci 2.0 on + # irq 0 = 0x12 + # irq 1 = 0x13 + # irq 2 = 0x10 + # irq 3 = 0x11 + # end + #end + end + device pci 0.1 on end # IOAPIC + device pci 1.0 on # PCIX bridge + ## PCI Slot 1 + #chip drivers/generic/generic + # device pci 1.0 on + # irq 0 = 0x11 + # irq 1 = 0x12 + # irq 2 = 0x13 + # irq 3 = 0x10 + # end + #end + ## PCI Slot 2 + #chip drivers/generic/generic + # device pci 2.0 on + # irq 0 = 0x12 + # irq 1 = 0x13 + # irq 2 = 0x10 + # irq 3 = 0x11 + # end + #end + end + device pci 1.1 on end # IOAPIC + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent of the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end # USB0 + device pci 0.1 on end # USB1 + device pci 0.2 off end # USB 2.0 + device pci 1.0 off end # LAN + chip drivers/pci/onboard + device pci 6.0 on end # ATI Rage XL + register "rom_address" = "0xfff80000" + end + ## PCI Slot 5 (correct?) + #chip drivers/generic/generic + # device pci 5.0 on + # irq 0 = 0x11 + # irq 1 = 0x12 + # irq 2 = 0x13 + # irq 3 = 0x10 + # end + #end + ## PCI Slot 6 (correct?) + #chip drivers/generic/generic + # device pci 4.0 on + # irq 0 = 0x10 + # irq 1 = 0x11 + # irq 2 = 0x12 + # irq 3 = 0x13 + # end + #end + + end + # LPC bridge + device pci 1.0 on + chip superio/nsc/pc87360 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # ACB + device pnp 2e.9 off end # FSCM + device pnp 2e.a off end # WDT + end + end + device pci 1.1 on end # IDE + device pci 1.2 on end # SMBus 2.0 + device pci 1.3 on # System Management + chip drivers/generic/generic + #phillips pca9545 smbus mux + device i2c 70 on + # analog_devices adm1026 + chip drivers/generic/generic + device i2c 2c on end + end + end + device i2c 70 on end + device i2c 70 on end + device i2c 70 on end + end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end + device pci 1.5 off end # AC97 Audio + device pci 1.6 on end # AC97 Modem + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end # LDT1 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # chip northbridge/amd/amdk8 + chip northbridge/amd/amdk8 + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,42 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + register "lpc_serirq_enable" = "0x00001002" + register "lpc_serirq_polarity" = "0x0000EFFD" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x2F8" + register "com1_irq" = "3" + register "com2_enable" = "1" + register "com2_address" = "0x3F8" + register "com2_irq" = "4" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci b.0 on end # Slot 3 + device pci c.0 on end # Slot 4 + device pci d.0 on end # Slot 1 + device pci e.0 on end # Slot 2 + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end + +end + Added: trunk/coreboot-v2/src/mainboard/asi/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,55 @@ +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 0f.0 on end # Ethernet + device pci 12.0 on # ISA bridge + chip superio/nsc/pc87351 # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.e on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # System wake-up control (SWC) + irq 0x60 = 0x500 + end + device pnp 2e.5 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 on # GPIO + irq 0x60 = 0x800 + end + device pnp 2e.8 on # Fan speed control + irq 0x60 = 0x900 + end + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA + device pci 13.0 on end # USB + register "ide0_enable" = "1" + register "ide1_enable" = "0" # No connector on this board + end + end + chip cpu/amd/model_gx1 # CPU + end +end Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,56 @@ +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 0f.0 off end # Ethernet (Realtek RTL8139B) + device pci 12.0 on # ISA bridge + chip superio/nsc/pc87351 # Super I/O + device pnp 2e.4 on # PS/2 keyboard (+ mouse?) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + # irq 0x72 = 12 + end + device pnp 2e.a on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.e on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.f off # Floppy + io 0x60 = 0x3f2 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.10 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.12 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA (onboard) + # device pci 12.4 on # VGA (onboard) + # chip drivers/pci/onboard + # device pci 12.4 on end + # register "rom_address" = "0xfffc0000" # 256 KB image + # # register "rom_address" = "0xfff80000" # 512 KB image + # # register "rom_address" = "0xfff00000" # 1 MB image + # end + # end + device pci 13.0 on end # USB + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end + chip cpu/amd/model_gx1 # CPU + end +end + Added: trunk/coreboot-v2/src/mainboard/asus/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,130 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device apic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # Socket 939 CPU + device apic 0 on end # APIC + end + end + + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x0000 + irq 0x70 = 0x00 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x71 = 2 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + irq 0x71 = 2 + end + device pnp 2e.7 on # GPIO config + io 0x60 = 0x0800 + # Set GPIO 1 & 2 + io 0x25 = 0x0000 + # Set GPIO 3 & 4 + io 0x27 = 0x2540 + # GPIO Polarity for Set 3 + io 0xb2 = 0x2100 + # GPIO Pin Internal Pull up for Set 3 + io 0xba = 0x0100 + # Simple I/O register config + io 0xc0 = 0x0000 + io 0xc2 = 0x2540 + io 0xc8 = 0x0000 + io 0xca = 0x0500 + end + device pnp 2e.8 on # Midi port + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.a off # IR (N/A on this board) + io 0x60 = 0x310 + irq 0x70 = 11 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic #dimm 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic #dimm 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic #dimm 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic #dimm 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic #dimm 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic #dimm 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic #dimm 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic #dimm 1-1-1 + # device i2c 57 on end + # end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI), N/A + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # register "mac_eeprom_smbus" = "3" + # register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,96 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device apic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard (off) + end + device pnp 2e.106 off # Serial flash + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO_PLED + end + device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,76 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device apic_cluster 0 on # APIC cluster + chip cpu/amd/socket_AM2 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" # Enable SB functions + register "fn_ctrl_hi" = "0x1d" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # PS/2 keyboard + device pnp 2e.6 off end # PS/2 mouse + device pnp 2e.7 off end # GPIO config + device pnp 2e.8 off end # Midi port + device pnp 2e.9 off end # Game port + device pnp 2e.a off end # IR + end + end + device pci 12.0 on end # VIA LAN + device pci 13.0 on end # br + device pci 13.1 on end # br2 need to have it here to discover it + end + chip southbridge/via/k8t890 # "Southbridge" K8M890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,60 @@ +chip northbridge/intel/i82810 # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) + device pci 1.0 on end # Chipset Graphics Controller (CGC) + chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.9 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.a on # Power-management events (PME) + io 0x60 = 0x600 + end + device pnp 2e.b on # MIDI port (MPU-401) + io 0x60 = 0x330 + irq 0x70 = 5 + end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMbus + device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) + device pci 1f.6 off end # AC'97 modem (N/A) + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,58 @@ +chip northbridge/intel/i82810 + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 on # Onboard Video + #chip drivers/pci/onboard + # device pci 1.0 on end + # register "rom_address" = "0xfff80000" + #end + end + chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + + device pci 1e.0 on # PCI Bridge + #chip drivers/pci/onboard + # device pci 1.0 on end + # register "rom_address" = "0xfff80000" + #end + end + device pci 1f.0 on # ISA/LPC? Bridge + chip superio/smsc/lpc47b272 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.a off end # ACPI + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # AC'97, no header on MEW-VM + device pci 1f.6 off end # AC'97 Modem (MC'97) + end + end + chip cpu/intel/socket_PGA370 + end +end + Added: trunk/coreboot-v2/src/mainboard/asus/p2b/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,62 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 1 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,63 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 1 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + device pci 6.0 on end # Onboard SCSI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/asus/p3b-f/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/axus/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/axus/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/axus/tc320/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,55 @@ +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 12.0 on # ISA bridge + chip superio/nsc/pc97317 # Super I/O + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC, advanced power control (APC) + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy (N/A on this board) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe800 + end + end + end + device pci 12.1 off end # SMI + device pci 12.2 off end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA (onboard) + device pci 13.0 on end # USB + # register "ide0_enable" = "1" + # register "ide1_enable" = "1" + end + end + chip cpu/amd/model_gx1 # CPU + end +end Added: trunk/coreboot-v2/src/mainboard/azza/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/azza/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/bcom/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/bcom/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/bcom/winnet100/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,56 @@ +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 0f.0 on end # Ethernet (onboard) + device pci 12.0 on # ISA bridge + chip superio/nsc/pc97317 # Super I/O + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC, Advanced power control (APC) + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy (N/A on this board) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 (used for smartcard reader) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe8 + end + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA (onboard) + device pci 13.0 on end # USB + register "ide0_enable" = "1" + register "ide1_enable" = "0" # Not available/needed on this board + end + end + chip cpu/amd/model_gx1 # CPU + end +end Added: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,64 @@ +chip northbridge/via/cn700 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci f.0 on end # IDE + device pci 10.0 on end # UHCI + device pci 10.1 on end # UHCI + device pci 10.2 on end # UHCI + device pci 10.3 on end # UHCI + device pci 10.4 on end # EHCI + device pci 11.0 on # Southbridge LPC + chip superio/winbond/w83697hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, GPIO 1 + device pnp 2e.8 off end # MIDI port, GPIO 5 + device pnp 2e.9 off end # GPIO 2-4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + end + end + device pci 11.5 on end # AC'97 audio + device pci 12.0 on end # Ethernet + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end Added: trunk/coreboot-v2/src/mainboard/biostar/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/biostar/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/biostar/m6tba/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,53 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.8 on # Aux I/O + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/broadcom/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/broadcom/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/broadcom/blast/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,148 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0 + chip southbridge/broadcom/bcm5780 # HT2000 + device pci 0.0 on end # PXB 1 0x0130 + device pci 1.0 on # PXB 2 0x0130 + device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 + end + device pci 2.0 on end # PCI E 1 #0x0132 + device pci 3.0 on end # PCI E 2 + device pci 4.0 on end # PCI E 3 + device pci 5.0 on end # PCI E 4 + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PPBX 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on # Legacy pci main 0x0205 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 71 on end #0 pca9554 0 + device i2c 71 on end #0 pca9554 1 + device i2c 71 on end #0 pca9554 2 + device i2c 71 on end #0 pca9554 3 + device i2c 71 on end #0 pca9554 4 + device i2c 71 on end #0 pca9554 5 + device i2c 71 on #0 pca9554 6 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 71 on #1 pca9554 7 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + end + end + + end + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.f off end # XBUS + device pnp 2e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end + end + device pci 1.3 on end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), + chip drivers/pci/onboard + device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address + # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 + register "rom_address" = "0xfff80000" + end + end + #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) +# chip drivers/pci/onboard +# device pci 0.0 on end # fake, will be disabled +# end +# chip drivers/pci/onboard +# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed +# register "rom_address" = "0xfff80000" +# end + + + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + + + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end + Added: trunk/coreboot-v2/src/mainboard/compaq/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/compaq/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,63 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + device pci a.0 on end # NIC (onboard) + chip southbridge/intel/i82371eb # Southbridge + device pci 14.0 on # ISA bridge + # chip superio/nsc/pc97307 # Super I/O + chip superio/nsc/pc97317 # Super I/O (FIXME: Should be PC97307!) + device pnp 15c.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 15c.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 15c.2 on # RTC, APC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 15c.3 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 15c.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 15c.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 15c.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 15c.7 on # GPIO 1 + end + device pnp 15c.8 on # Power management + end + end + end + device pci 14.1 on end # IDE + device pci 14.2 on end # USB + device pci 14.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/dell/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/dell/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/dell/s1850/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,71 @@ +chip northbridge/intel/e7520 # mch + device pci_domain 0 on + chip southbridge/intel/i82801er # i82801er + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + + # -> Bridge + device pci 1e.0 on end + + # -> ISA + device pci 1f.0 on + chip superio/nsc/pc8374 + device pnp 2e.0 off end + device pnp 2e.1 off end + device pnp 2e.2 off end + device pnp 2e.3 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.8 off end + end + end + # -> IDE + device pci 1f.1 on end + # -> SATA + device pci 1f.2 on end + device pci 1f.3 on end + + register "pirq_a_d" = "0x8a07030b" + register "pirq_e_h" = "0x85808080" + end + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + # Bus bridges and ioapics usually bus 1 + device pci 0.0 on + # On board gig e1000 + chip drivers/generic/generic + device pci 03.0 on end + device pci 03.1 on end + end + end + device pci 0.1 on end + device pci 0.2 on end + device pci 0.3 on end + end + end + device pci 04.0 on end + device pci 06.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # cpu 1 + device apic 6 on end + end + end + register "intrline" = "0x00070100" +end + Added: trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,61 @@ +chip northbridge/intel/i855pm + device pci_domain 0 on + device pci 0.0 on end + device pci 1.0 on end + chip southbridge/intel/i82801dbm +# pci 11.0 on end +# pci 11.1 on end +# pci 11.2 on end +# pci 11.3 on end +# pci 11.4 on end +# pci 11.5 on end +# pci 11.6 on end +# pci 12.0 on end + register "enable_usb" = "0" + register "enable_native_ide" = "0" + register "enable_usb" = "0" + register "enable_native_ide" = "0" + chip superio/winbond/w83627hf # link 1 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + register "com1" = "{1}" + # register "com1" = "{1, 0, 0x3f8, 4}" + # register "lpt" = "{1}" + end + end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA479M + device apic 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,16 @@ +chip cpu/amd/sc520 + device pci_domain 0 on + device pci 0.0 on end + + chip drivers/pci/onboard + device pci 12.0 on end # enet + end + chip drivers/pci/onboard + device pci 14.0 on end # 69000 + register "rom_address" = "0x2000000" + end +# register "com1" = "{1}" +# register "com1" = "{1, 0, 0x3f8, 4}" + end + +end Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,86 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + # How to get these? Boot linux and do this: + # rdmsr 0x51400025 + register "lpc_serirq_enable" = "0x0000105a" + # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits + register "lpc_serirq_polarity" = "0x0000EFA5" + # mode is high 10 bits (determined from code) + register "lpc_serirq_mode" = "1" + # Don't yet know how to find this. + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci f.1 on end # Flash controller + device pci f.2 on end # IDE controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end + +end + Added: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,54 @@ +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + device pci 12.0 on + chip superio/nsc/pc97317 + device pnp 2e.0 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # FDC + end + device pnp 2e.4 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power Management + io 0x60 = 0xe800 + end + register "com1" = "{115200}" + register "com2" = "{38400}" + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 off end # Audio + device pci 12.4 off end # VGA + end + end + end + + chip cpu/amd/model_gx1 + end + +end + Added: trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/embeddedplanet/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,17 @@ +chip cpu/ppc/ppc4xx + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/winbond/w83c553 + device pci 9.0 on end # ISA bridge + device pci 9.1 on end # IDE contoller + end + device pci e.0 on end + end +end + +## +## Build the objects we have code for in this directory. +## + +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" +makedefine CFLAGS += -msoft-float Added: trunk/coreboot-v2/src/mainboard/emulation/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/emulation/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,25 @@ +choice + prompt "Mainboard model" + depends on VENDOR_EMULATION + +config BOARD_EMULATION_QEMU_X86 + bool "QEMU x86" + select ARCH_X86 + select CPU_I586 + select SOUTHBRIDGE_INTEL_I82371EB + select CPU_EMULATION_QEMU_X86 + select CONSOLE_SERIAL8250 + help + x86 QEMU variant. + +endchoice + +config MAINBOARD_DIR + string + default emulation/qemu-x86 + depends on BOARD_EMULATION_QEMU_X86 + +config MAINBOARD_PART_NUMBER + string + default "QEMU-86" + depends on BOARD_EMULATION_QEMU_X86 Added: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,21 @@ +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += auto.inc + +obj-y += mainboard.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(obj)/romcc -mcpu=i386 -O $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + +endif Added: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,15 @@ +chip cpu/emulation/qemu-x86 + device pci_domain 0 on + device pci 0.0 on end + + chip southbridge/intel/i82371eb # southbridge + device pci 01.0 on end + device pci 01.1 on end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + +# register "com1" = "{1}" +# register "com1" = "{1, 0, 0x3f8, 4}" + end +end Added: trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,57 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/ite/it8671f # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.2 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # APC + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 3f0.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 3f0.7 on # GPIO + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,106 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_AM2 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/sis/sis966 + device pci 0.0 on end # Northbridge + device pci 1.0 on # AGP bridge + chip drivers/pci/onboard # Integrated VGA + device pci 0.0 on end + register "rom_address" = "0xfff80000" + end + end + device pci 2.0 on # LPC + chip superio/ite/it8716f + device pnp 2e.0 off # Floppy (N/A) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 (N/A) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel port (N/A) + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 off # PS/2 keyboard (N/A) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse (N/A) + irq 0x70 = 12 + end + device pnp 2e.8 off # MIDI (N/A) + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # GAME (N/A) + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR (N/A) + end + end + + device pci 2.5 off end # IDE (SiS5513) + device pci 2.6 off end # Modem (SiS7013) + device pci 2.7 off end # Audio (SiS7012) + device pci 3.0 on end # USB (SiS7001,USB1.1) + device pci 3.1 on end # USB (SiS7001,USB1.1) + device pci 3.3 on end # USB (SiS7002,USB2.0) + device pci 4.0 on end # NIC (SiS191) + device pci 5.0 on end # SATA (SiS1183,Native Mode) + device pci 6.0 on end # PCI-e x1 + device pci 7.0 on end # PCI-e x1 + device pci a.0 off end + device pci b.0 off end + device pci c.0 off end + device pci d.0 off end + device pci e.0 off end + device pci f.0 off end # HD Audio (SiS7502) + + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,202 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_AM2 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8716f + # Floppy and any LDN + device pnp 2e.0 off + # Watchdog from CLKIN, CLKIN = 24 MHz + irq 0x23 = 0x11 + # Serial Flash (SPI only) + #0x24 = 0x1a + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO, SPI flash + # pin 84 is not GP10 + irq 0x25 = 0x0 + # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x26 = 0x43 + # pin 13 is GP35 + irq 0x27 = 0x20 + # pin 70 is not GP46 + #irq 0x28 = 0x0 + # pin 6,3,128,127,126 is GP63,64,65,66,67 + irq 0x29 = 0x81 + # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + #irq 0x2c = 0x1f + # Simple I/O base + io 0x62 = 0x800 + # Serial Flash I/O (SPI only) + io 0x64 = 0x820 + # watch dog force timeout (parallel flash only) + #irq 0x71 = 0x1 + # No WDT interrupt + irq 0x72 = 0x0 + # GPIO pin set 1 disable internal pullup + irq 0xb8 = 0x0 + # GPIO pin set 5 enable internal pullup + irq 0xbc = 0x01 + # SIO pin set 1 alternate function + #irq 0xc0 = 0x0 + # SIO pin set 2 mixed function + irq 0xc1 = 0x43 + # SIO pin set 3 mixed function + irq 0xc2 = 0x20 + # SIO pin set 4 alternate function + #irq 0xc3 = 0x0 + # SIO pin set 1 input mode + #irq 0xc8 = 0x0 + # SIO pin set 2 input mode + irq 0xc9 = 0x0 + # SIO pin set 4 input mode + #irq 0xcb = 0x0 + # Generate SMI# on EC IRQ + #irq 0xf0 = 0x10 + # SMI# level trigger + #irq 0xf1 = 0x40 + # HWMON alert beep pin location + irq 0xf6 = 0x28 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM +#WTF?!? We already have device pci 1.1 in the section above + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 off end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/hp/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/hp/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,96 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 # northbridge + device pci 18.0 on # devices on link 0 + chip southbridge/broadcom/bcm21000 # HT2100 + device pci 0.0 on + end # bridge to slot PCI-E 4x ?? + device pci 1.0 on + end + device pci 2.0 on + end # unused + device pci 3.0 on # bridge to slot PCI-E 16x ?? + end + device pci 4.0 on + end # unused + device pci 5.0 on + device pci 4.0 on end # BCM5715 NIC + device pci 4.1 on end # BCM5715 NIC + end + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PCI/PCI-X bridge 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on end # Legacy pci main 0x0205 + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.3 off # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.4 off end # SWC + device pnp 4e.5 off end # Mouse + device pnp 4e.6 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.7 off end # GPIO + device pnp 4e.f off end # XBUS + device pnp 4e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end # end superio + end # end pci 1.2 + device pci 1.3 off end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 3.0 on end # VGA + + #bx_a013+ start + #chip drivers/pci/onboard #SATA2 + # device pci 5.0 on end + # device pci 5.1 on end + # device pci 5.2 on end + # device pci 5.3 on end + #end + #bx_a013+ end + end + end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # amdk8 + + end #pci_domain +end + + Added: trunk/coreboot-v2/src/mainboard/ibm/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/ibm/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/ibm/e325/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,81 @@ +chip northbridge/amd/amdk8/root_complex + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # LDT 0 + device pci 18.0 on # LDT 1 + chip southbridge/amd/amd8131 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/nsc/pc87366 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # ACB + device pnp 2e.9 off end # FSCM + device pnp 2e.a off end # WDT + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 off end + device pci 1.6 off end + end + end # device pci 18.0 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/ibm/e326/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,77 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # LDT 0 + device pci 18.0 on # LDT 1 + chip southbridge/amd/amd8131 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on end + device pci 1.0 off end + chip drivers/pci/onboard + device pci 5.0 on end # ATI Rage XL + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/nsc/pc87366 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # ACB + device pnp 2e.9 off end # FSCM + device pnp 2e.a off end # WDT + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/iei/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/iei/juki-511p/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + + device pci 12.0 on + chip superio/winbond/w83977f + device pnp 3f0.0 on # FDC + irq 0x70 = 6 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + register "com1" = "{115200}" + device pnp 3f0.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + register "com2" = "{115200}" + device pnp 3f0.4 on # RTC + io 0x60 = 0x070 + irq 0x70 = 8 + end + device pnp 3f0.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Int 1 for PS/2 keyboard + irq 0x72 = 12 # Int 12 for PS/2 mouse + end + device pnp 3f0.6 off # IR + end + device pnp 3f0.7 off # GPIO1 + end + device pnp 3f0.8 off # GPIO + end + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA onboard + + end + + device pci 0e.0 on end # ETH0 + device pci 13.0 on end # USB + + end + end + + chip cpu/amd/model_gx1 + end + +end + Added: trunk/coreboot-v2/src/mainboard/iei/nova4899r/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,66 @@ +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + device pci 0a.0 on end # ETH0 + device pci 0b.0 off end # ETH1 + device pci 0c.0 on end # ETH2 + device pci 0f.0 on end # PCI slot + device pci 12.0 on + chip superio/winbond/w83977tf + device pnp 2e.0 on # FDC + irq 0x70 = 6 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + register "com1" = "{115200}" + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + register "com2" = "{115200}" + device pnp 2e.4 off # Reserved + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 # Int 1 for PS/2 keyboard + irq 0x72 = 0x0c # Int 12 for PS/2 mouse + end + device pnp 2e.6 on # IR + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.7 on # GAME/MIDI/GPIO1 + io 0x60 = 0x290 + end + device pnp 2e.8 on # GPIO2 + io 0x60 = 0x110 + end + device pnp 2e.9 on # GPIO3 + io 0x60 = 0x120 + end + device pnp 2e.A on # Power Management + io 0x60 = 0xe800 + end + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA onboard + end + device pci 13.0 on end # USB + end + end + + chip cpu/amd/model_gx1 + end + +end + Added: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,76 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 9.0 on end # Slot1 + device pci a.0 on end # Slot2 + device pci b.0 on end # Slot3 + device pci c.0 on end # Slot4 + device pci e.0 on end # Ethernet 0 + device pci 10.0 on end # Ethernet 1 + device pci 11.0 on end # SATA + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/intel/jarrell/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,79 @@ +chip northbridge/intel/e7520 + device pci_domain 0 on + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + device pci 00.0 on end + device pci 00.1 on end + device pci 00.2 on + chip drivers/generic/generic + device pci 04.0 on end + device pci 04.1 on end + end + end + device pci 00.3 on end + end + end + device pci 06.0 on end + chip southbridge/intel/i82801er # i82801er + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 off end + device pci 1d.7 on end + device pci 1e.0 on + chip drivers/ati/ragexl + device pci 0c.0 on end + end + end + device pci 1f.0 on + chip superio/nsc/pc87427 + device pnp 2e.0 off end + device pnp 2e.2 on +# io 0x60 = 0x2f8 +# irq 0x70 = 3 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on +# io 0x60 = 0x3f8 +# irq 0x70 = 4 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 on + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a off end + device pnp 2e.f on end + device pnp 2e.10 off end + device pnp 2e.14 off end + end + end + device pci 1f.1 on end + device pci 1f.2 off end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 off end + register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO" + register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW" + register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT" + end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # cpu 1 + device apic 6 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/intel/mtarvon/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,44 @@ +chip northbridge/intel/i3100 + device pci_domain 0 on + device pci 00.0 on end # IMCH + device pci 00.1 on end # IMCH error status + device pci 01.0 on end # IMCH EDMA engine + device pci 02.0 on end # PCIe port A/A0 + device pci 03.0 on end # PCIe port A1 + chip southbridge/intel/i3100 + # PIRQ line -> legacy IRQ mappings + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + + device pci 1c.0 on end # PCIe port B0 + device pci 1c.1 on end # PCIe port B1 + device pci 1c.2 on end # PCIe port B2 + device pci 1c.3 on end # PCIe port B3 + device pci 1d.0 on end # USB (UHCI) 1 + device pci 1d.1 on end # USB (UHCI) 2 + device pci 1d.7 on end # USB (EHCI) + device pci 1e.0 on end # PCI bridge + device pci 1e.2 on end # audio + device pci 1e.3 on end # modem + device pci 1f.0 on # LPC bridge + chip superio/intel/i3100 + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA479M + device apic 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,41 @@ +chip northbridge/intel/i3100 + device pci_domain 0 on + device pci 00.0 on end # IMCH + device pci 00.1 on end # IMCH error status + device pci 01.0 on end # IMCH EDMA engine + device pci 02.0 on end # PCIe port A/A0 + device pci 03.0 on end # PCIe port A1 + device pci 04.0 on end # ? + device pci 08.0 off end # must be off to boot + device pci 0d.0 off end # must be off to boot + device pci 0d.1 off end # must be off to boot + chip southbridge/intel/i3100 + # PIRQ line -> legacy IRQ mappings + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + + device pci 1d.0 on end # USB (UHCI) + device pci 1d.7 on end # USB (EHCI) + device pci 1f.0 on # LPC bridge + chip superio/intel/i3100 + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + device pci 1f.4 on end # ? + end + end + device apic_cluster 0 on + chip cpu/intel/ep80579 + device apic 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,75 @@ +chip northbridge/intel/e7501 + device pci_domain 0 on + device pci 0.0 on end # Chipset host controller + device pci 0.1 on end # Host RASUM controller + device pci 2.0 on # Hub interface B + chip southbridge/intel/i82870 # P64H2 + device pci 1c.0 on end # IOAPIC - bus B + device pci 1d.0 on end # Hub to PCI-B bridge + device pci 1e.0 on end # IOAPIC - bus A + device pci 1f.0 on end # Hub to PCI-A bridge + end + end + device pci 3.0 off end # Hub interface C (82808AA connector - disable for now) + device pci 4.0 on # Hub interface D + chip southbridge/intel/i82870 # P64H2 + device pci 1c.0 on end # IOAPIC - bus B + device pci 1d.0 on end # Hub to PCI-B bridge + device pci 1e.0 on end # IOAPIC - bus A + device pci 1f.0 on end # Hub to PCI-A bridge + end + end + device pci 6.0 on end # E7501 Power management registers? (undocumented) + chip southbridge/intel/i82801ca + device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at) + device pci 1d.1 off end # USB (not populated) + device pci 1d.2 off end # USB (not populated) + device pci 1e.0 on # Hub to PCI bridge + chip drivers/pci/onboard # VGA ROM + device pci 0.0 on end + register "rom_address" = "_vgarom_start" + end + end + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47b272 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.a off end # ACPI + end + end + device pci 1f.1 on end # IDE + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # AC97 Audio + device pci 1f.6 off end # AC97 Modem + end # SB + end # PCI_DOMAIN + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 + device apic 6 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/iwill/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,133 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # northbridge + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + #chip drivers/pci/onboard + # device pci 6.0 on end + # register "rom_address" = "0xfff80000" + #end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 on # GPIO2 + io 0x07 = 0x08ff + io 0x30 = 0x01ff + io 0x2b = 0xd0ff + io 0xf0 = 0xef16 + end + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end + + Added: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,89 @@ +chip northbridge/amd/amdk8/root_complex + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # LDT 0 + chip southbridge/amd/amd8131 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + register "com1" = "{1}" + # register "com1" = "{1, 0, 0x3f8, 4}" + # register "lpt" = "{1}" + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 off end + device pci 1.6 off end + end + end # LDT0 + device pci 18.0 on end # LDT1 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/iwill/dk8x/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,68 @@ +chip northbridge/amd/amdk8/root_complex + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627thf + device pnp 2e.0 on end + device pnp 2e.1 on end + device pnp 2e.2 on end + device pnp 2e.3 on end + device pnp 2e.4 on end + device pnp 2e.5 on end + device pnp 2e.6 on end + device pnp 2e.7 on end + device pnp 2e.8 on end + device pnp 2e.9 on end + device pnp 2e.a on end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 off end + device pci 1.6 off end + end + end # LDT0 + device pci 18.0 on end # LDT1 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/jetway/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,62 @@ +chip northbridge/via/cn700 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci a.0 on end # Firewire + device pci f.0 on end # SATA + device pci f.1 on end # IDE + device pci 10.0 on end # OHCI + device pci 10.1 on end # OHCI + device pci 10.2 on end # OHCI + device pci 10.3 on end # OHCI + device pci 10.4 on end # EHCI + device pci 11.0 on # Southbridge LPC + chip superio/fintek/f71805f # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end + end + device pci 11.5 on end # AC'97 audio + # device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end # Ethernet + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,77 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +driver-y += mainboard.o +driver-y += rtl8168.o + +#obj-y += ../../../southbridge/intel/i82801gx/i82801gx_reset.c +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS=\ + -DCONFIG_AP_IN_SIPI_WAIT=1 \ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 \ + -DCONFIG_MMCONF_SUPPORT=1 \ + -DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,132 @@ +chip northbridge/intel/i945 + + device apic_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device apic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 01.0 off end # i945 PCIe root port + chip drivers/pci/onboard + device pci 02.0 on end # vga controller + # register "rom_address" = "0xfffc0000" # 256 KB image + # register "rom_address" = "0xfff80000" # 512 KB image + register "rom_address" = "0xfff00000" # 1 MB image + end + device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x07" + register "pirqc_routing" = "0x05" + register "pirqd_routing" = "0x07" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x06" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x1" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627thg + device pnp 2e.0 off # Floppy + end + device pnp 2e.1 off # Parport + end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + end + device pnp 2e.5 on # Keyboard+Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 # HW accel A20. + end + device pnp 2e.7 on # GPIO1, GAME, MIDI + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 2e.8 on # GPIO2 + # all default + end + device pnp 2e.9 on # GPIO3/4 + irq 0x30 = 0x03 # does this work? + irq 0xf0 = 0xfb # set inputs/outputs + irq 0xf1 = 0x66 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0xa00 + irq 0x70 = 0 + end + + end + chip superio/winbond/w83627thg + device pnp 4e.0 off # Floppy + end + device pnp 4e.1 off # Parport + end + device pnp 4e.2 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 11 + end + device pnp 4e.3 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 10 + end + device pnp 4e.5 off # Keyboard + end + device pnp 4e.7 off # GPIO1, GAME, MIDI + end + device pnp 4e.8 off # GPIO2 + end + device pnp 4e.9 off # GPIO3/4 + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b off # HWM + end + end + + end + #device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + #device pci 1f.4 off end # Realtek ID Codec + end + end +end Added: trunk/coreboot-v2/src/mainboard/kontron/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,48 @@ +choice + prompt "Mainboard model" + depends on VENDOR_KONTRON + +config BOARD_KONTRON_986LCD_M + bool "986LCD-M" + select ARCH_X86 + select CPU_INTEL_CORE + select CPU_INTEL_SOCKET_MFCPGA478 + select NORTHBRIDGE_INTEL_I945 + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627THG + select PIRQ_TABLE + select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + help + Kontron 986LCD-M Series mainboards +endchoice + +config MAINBOARD_DIR + string + default kontron/986lcd-m + depends on BOARD_KONTRON_986LCD_M + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_KONTRON_986LCD_M + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_KONTRON_986LCD_M + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_KONTRON_986LCD_M + +config LB_CKS_LOC + int + default 123 + depends on BOARD_KONTRON_986LCD_M + +config MAINBOARD_PART_NUMBER + string + default "986LCD-M" + depends on BOARD_KONTRON_986LCD_M Added: trunk/coreboot-v2/src/mainboard/lippert/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,18 @@ +chip northbridge/amd/gx2 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5535 + device pci 12.0 on + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 off end # Audio + device pci 12.4 off end # VGA + end + end + end + + chip cpu/amd/model_gx2 + end + +end + Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,89 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES + chip southbridge/amd/cs5536 # Southbridge + # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, + # UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 8.0 on end # Slot4 + device pci 9.0 on end # Slot3 + device pci a.0 on end # Slot2 + device pci b.0 on end # Slot1 + device pci c.0 on end # IT8888 + device pci e.0 on end # Ethernet + device pci f.0 on # ISA bridge + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 + # io 0x64 = 0x1200 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end + end + device pci f.2 on end # IDE controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,90 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, + # UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 + register "unwanted_vpci[1]" = "0" # End of list has a zero + device pci 8.0 on end # Slot4 + device pci 9.0 on end # Slot3 + device pci a.0 on end # Slot2 + device pci b.0 on end # Slot1 + device pci c.0 on end # IT8888 + device pci e.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 + io 0x64 = 0x1200 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end + end + device pci f.2 on end # IDE + device pci f.3 off end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/mitac/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/mitac/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/motorola/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/motorola/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,30 @@ +## +## Config file for the Motorola Sandpoint III development system. +## Note that this has only been tested with the Altimus 7410 PMC. +## + +## +## Early board initialization, called from ppc_main() +## +initobject init.o +initobject clock.o + +## +## Stage 2 timer support +## +object clock.o + +## +## Set our CONFIG_ARCH +## +arch ppc end + +## +## Build the objects we have code for in this directory. +## + +dir nvram +dir flash + +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" +makedefine CFLAGS += -g Added: trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,26 @@ +chip northbridge/motorola/mpc107 + device pci_domain 0 on + device pci 0.0 on end + device pci b.0 on + chip southbridge/winbond/w83c553 + chip superio/nsc/pc97307 + device pnp 15c.0 on end # Kyeboard + device pnp 15c.1 on end # Mouse + device pnp 15c.2 on end # Real-time Clock + device pnp 15c.3 on end # Floppy + device pnp 15c.4 on end # Parallel port + device pnp 15c.5 on end # com2 + device pnp 15c.6 on end # com1 + device pnp 15c.7 on end # gpio + device pnp 15c.8 on end # Power management + end + end + end # pci to isa bridge + device pci b.1 on end # pci ide controller + end + device cpu_bus 0 on + chip cpu/ppc/mpc74xx + device cpu 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_MSI + +config BOARD_MSI_MS6178 + bool "MS-6178" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801XX + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + help + MSI MS-6178 mainboard. +endchoice + +config MAINBOARD_DIR + string + default msi/ms6178 + depends on BOARD_MSI_MS6178 + Added: trunk/coreboot-v2/src/mainboard/msi/ms6119/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,60 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,60 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += mainboard.o + +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +initobj-y += ../../../arch/i386/init/entry.o +initobj-y += ../../../cpu/intel/model_6ex/car.o # FIXME. romcc. +# initobj-y += ../../../arch/i386/init/rombootstrap.o +# initobj-y += ../../../cpu/intel/model_6ex/disable_car.o +initobj-y += ../../../pc80/mc146818rtc_early.o +initobj-y += ../../../arch/i386/lib/console.o +initobj-y += ../../../arch/i386/lib/console_printk.o +# initobj-y += ../../../ram/ramtest.o # FIXME +initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_early_smbus.o +initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_reset.o +initobj-y += ../../../superio/winbond/w83627hf/w83627hf_early_serial.o +initobj-y += ../../../northbridge/intel/i82810/raminit.o + +ifdef POST_EVALUATION + +# FIXME: Drop DCACHE_RAM_BASE/DCACHE_RAM_SIZE, only here to make it build. +MAINBOARD_OPTIONS=\ + -DCONFIG_USE_PRINTK_IN_CAR=1 \ + -DCONFIG_HAVE_HIGH_TABLES=1 \ + -DCONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0 \ + -DCONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0 \ + -DCONFIG_MAINBOARD_VENDOR=\"MSI\" \ + -DCONFIG_MAINBOARD_PART_NUMBER=\"MS-6178\" \ + -DCONFIG_DCACHE_RAM_BASE=0xffdf8000 \ + -DCONFIG_DCACHE_RAM_SIZE=0x8000 + +endif + Added: trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,69 @@ +chip northbridge/intel/i82810 # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 off # Onboard video + # chip drivers/pci/onboard + # device pci 1.0 on end + # register "rom_address" = "0xfff80000" + # end + end + chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA/LPC bridge + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 (only header on board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.6 on end # Consumer IR (TODO) + device pnp 2e.7 on # Game port / MIDI / GPIO 1 + io 0x60 = 0x201 + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 2e.8 on end # GPIO 2 + device pnp 2e.9 on end # GPIO 3 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC'97 audio + device pci 1f.6 on end # AC'97 modem + end + end +end + Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,76 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device apic_cluster 0 on # APIC cluster + chip cpu/amd/socket_754 # Socket 754 CPU + device apic 0 on end # APIC + end + end + + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thf # Super I/O + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5 + device pnp 4e.8 off end # GPIO 2 + device pnp 4e.9 off end # GPIO 3, GPIO 4 + device pnp 4e.a off end # ACPI + device pnp 4e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1.1 on end # SMbus + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI) -- not wired out + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 -- not wired out + device pci c.0 off end # PCI E 2 -- not wired out + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # register "mac_eeprom_smbus" = "3" + # register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/ms7260/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,157 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device apic_cluster 0 on # APIC cluster + chip cpu/amd/socket_AM2 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / mc0 + device pci 18.0 on + # Devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # Com2 / IrDA + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard IRQ + irq 0x72 = 12 # PS/2 mouse IRQ + end + device pnp 4e.6 off # Serial flash interface + # io 0x62 = 0x100 + end + device pnp 4e.7 off # GPIO1/6, game port, MIDI port + # io 0x60 = 0x220 # Datasheet: 0x201 + # io 0x62 = 0x300 # Datasheet: 0x330 + # irq 0x70 = 9 + end + device pnp 4e.8 off # WDTO#, PLED + end + device pnp 4e.9 off # GPIO2/3/4/5, SUSLED + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b on # HWM (for lm-sensors) + io 0x60 = 0xa10 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + # TODO: Needed? + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # TODO: Check if the stuff below is correct / needed. + device pci 1.1 on # SM 1 + # PCI device SMBus address will depend on addon PCI device, + # do we need to scan_smbus_bus? + + # chip drivers/generic/generic # PCIXA Slot1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB Slot1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB Slot2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI Slot1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 off end # SATA 2 (N/A on this board) + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA (HD Audio) + device pci 8.0 on end # NIC + device pci 9.0 off end # NIC (N/A on this board) + device pci a.0 off end # PCI E 5 (N/A on this board?) + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # TODO: Check the two lines below. + register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + +# TODO +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end + +end Added: trunk/coreboot-v2/src/mainboard/msi/ms9185/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,120 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # northbridge + # devices on link 0 + chip southbridge/broadcom/bcm5780 # HT2000 + device pci 0.0 on end # PXB 1 0x0130 + device pci 1.0 on # PXB 2 0x0130 + device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 + end + device pci 2.0 on end # PCI E 1 #0x0132 + device pci 3.0 on end # PCI E 2 + device pci 4.0 on end # PCI E 3 + device pci 5.0 on end # PCI E 4 + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PPBX 0x0104 + device pci e.0 on end # SATA 0x024a + device pci e.1 on end # SATA 0x024a bx_a001 + device pci e.2 on end # SATA 0x024a bx_a001 + device pci e.3 on end # SATA 0x024a bx_a001 + end + device pci 1.0 on # Legacy pci main 0x0205 + end + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.f off end # XBUS + device pnp 2e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end + end + device pci 1.3 on end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), + chip drivers/pci/onboard + device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address + # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 + register "rom_address" = "0xfff80000" + end + #bx_a013+ start + #chip drivers/pci/onboard #SATA2 + # device pci 5.0 on end + # device pci 5.1 on end + # device pci 5.2 on end + # device pci 5.3 on end + #end + #bx_a013+ end + + end + #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) +# chip drivers/pci/onboard +# device pci 0.0 on end # fake, will be disabled +# end +# chip drivers/pci/onboard +# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed +# register "rom_address" = "0xfff80000" +# end + + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # amdk8 + end #pci_domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end + +end + + Added: trunk/coreboot-v2/src/mainboard/msi/ms9282/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,188 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SERIAL_FALSH + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 70 on #0 pca9554 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 57 on end + end + end + device i2c 70 on #0 pca9554 2 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 57 on end + end + end + end + end + device pci 1.1 on # SM 1 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 72 on #pca9554 channle1 + chip drivers/i2c/adm1027 #HWM ADT7476 1 + device i2c 2e on end + end + end + device i2c 72 on #pca9545 channel 2 + chip drivers/i2c/adm1027 #HWM ADT7463 + device i2c 2e on end + end + end + device i2c 72 on end #pca9545 channel 3 + device i2c 72 on #pca9545 channel 4 + chip drivers/i2c/adm1027 #HWM ADT7476 2 + device i2c 2e on end + end + end + end + end + + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on #P2P + chip drivers/pci/onboard + device pci 4.0 on end + register "rom_address" = "0xfff80000" + end + end # P2P + device pci 7.0 on end # reserve + device pci 8.0 on end # MAC0 + device pci 9.0 on end # MAC1 + device pci a.0 on + device pci 0.0 on + chip drivers/pci/onboard + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 + end + end + end # 0x376 + device pci b.0 on end # PCI E 0x374 + device pci c.0 on end + device pci d.0 on #SAS + chip drivers/pci/onboard + device pci 0.0 on end + end + end # PCI E 1 0x378 + device pci e.0 on end # PCI E 0 0x375 + device pci f.0 on end #PCI E 0x377 pci_E slot + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #mc0 + + end # pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end +# device pnp 0.1 off end +# device pnp 0.2 off end +# device pnp 0.3 off end +# device pnp 0.4 off end +# device pnp 0.5 on end +# end +end # root_complex Added: trunk/coreboot-v2/src/mainboard/nec/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/intel/i82810 # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 off # Onboard video + # chip drivers/pci/onboard + # device pci 1.0 on end + # register "rom_address" = "0xfff80000" + # end + end + chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA/LPC bridge + chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off end # Com2 (N/A) + device pnp 2e.7 on # PS/2 keyboard + irq 0x70 = 1 + irq 0x72 = 0 + end + device pnp 2e.9 off end # Game port (N/A) + device pnp 2e.a on # Power-management events (PME) + io 0x60 = 0x800 + end + device pnp 2e.b on # MIDI port + io 0x60 = 0x330 + irq 0x70 = 5 + end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC'97 audio + device pci 1f.6 off end # AC'97 modem (N/A) + end + end +end + Added: trunk/coreboot-v2/src/mainboard/newisys/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/newisys/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/newisys/khepri/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,92 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end + end + + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # LDT 0 + device pci 18.0 on # LDT 1 + chip southbridge/amd/amd8131 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on end + device pci 1.0 on end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 on end + device pci 1.6 on end + end + end # LDT1 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/nvidia/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/nvidia/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,178 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on + # devices on link 2, link 2 == LDT 2 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/olpc/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/olpc/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/olpc/btest/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,45 @@ +chip northbridge/amd/gx2 + register "irqmap" = "0xaa5b" + register "setupflash" = "0" + device apic_cluster 0 on + chip cpu/amd/model_gx2 + device apic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080. + # Frame Pulse Width = 4clocks + # IRQ Data Frames = 17Frames + # SIRQ Mode = continous , It would be better if the EC could operate in + # Active(Quiet) mode. Save power.... + # SIRQ Enable = Enabled + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + #register "lpc_irq" = "0x00001002" + #register "lpc_serirq_enable" = "0xEFFD0080" + #register "enable_gpio0_inta" = "1" + #register "enable_ide_nand_flash" = "1" + #register "enable_uarta" = "1" + #register "enable_USBP4_host" = "1" + #register "audio_irq" = "5" + #register "usbf4_irq" = "10" + #register "usbf5_irq" = "10" + #register "usbf6_irq" = "0" + #register "usbf7_irq" = "0" + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC + register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG + register "unwanted_vpci[2]" = "0" # End of list has a zero + end + end +end + Added: trunk/coreboot-v2/src/mainboard/olpc/rev_a/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,45 @@ +chip northbridge/amd/gx2 + register "irqmap" = "0xaa5b" + register "setupflash" = "0" + device apic_cluster 0 on + chip cpu/amd/model_gx2 + device apic 0 on end + end + end + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080. + # Frame Pulse Width = 4clocks + # IRQ Data Frames = 17Frames + # SIRQ Mode = continous , It would be better if the EC could operate in + # Active(Quiet) mode. Save power.... + # SIRQ Enable = Enabled + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + #register "lpc_irq" = "0x00001002" + #register "lpc_serirq_enable" = "0xEFFD0080" + #register "enable_gpio0_inta" = "1" + #register "enable_ide_nand_flash" = "1" + #register "enable_uarta" = "1" + #register "enable_USBP4_host" = "1" + #register "audio_irq" = "5" + #register "usbf4_irq" = "10" + #register "usbf5_irq" = "10" + #register "usbf6_irq" = "0" + #register "usbf7_irq" = "0" + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC + register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG + register "unwanted_vpci[2]" = "0" # End of list has a zero + end + end +end + Added: trunk/coreboot-v2/src/mainboard/pcengines/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/pcengines/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,86 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end + device pci 1.1 on end + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + # How to get these? Boot linux and do this: + # rdmsr 0x51400025 + register "lpc_serirq_enable" = "0x0000105a" + # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits + register "lpc_serirq_polarity" = "0x0000EFA5" + # mode is high 10 bits (determined from code) + register "lpc_serirq_mode" = "1" + # Don't yet know how to find this. + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 on end # GPIO2 + device pnp 2e.9 on end # GPIO3 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci f.1 on end # Flash controller + device pci f.2 on end # IDE controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end + +end + Added: trunk/coreboot-v2/src/mainboard/rca/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/rca/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/rca/rm4100/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,73 @@ +chip northbridge/intel/i82830 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip drivers/pci/onboard # Onboard VGA + device pci 2.0 on end # VGA (Intel 82830 CGC) + register "rom_address" = "0xfff00000" + end + chip southbridge/intel/i82801xx # Southbridge + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x06" + register "pirqc_routing" = "0x07" + register "pirqd_routing" = "0x09" + register "pirqe_routing" = "0x0a" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + + register "ide0_enable" = "1" + register "ide1_enable" = "1" + + device pci 1d.0 on end # USB UHCI Controller #1 + device pci 1d.1 on end # USB UHCI Controller #2 + device pci 1d.2 on end # USB UHCI Controller #3 + device pci 1d.7 on end # USB2 EHCI Controller + device pci 1e.0 on # PCI bridge + device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet + end + device pci 1f.0 on # ISA/LPC bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # Com2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.9 off end # Game port + device pnp 2e.a on # PME + io 0x60 = 0x800 + end + device pnp 2e.b off end # MPU-401 + end + end + device pci 1f.1 on end # IDE + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC'97 audio + device pci 1f.6 on end # AC'97 modem + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # Mobile Celeron Micro-FCBGA Socket 479 + device apic 0 on end # APIC + end + end +end + Added: trunk/coreboot-v2/src/mainboard/soyo/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/soyo/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/sunw/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/sunw/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,155 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on end # link 0 + device pci 18.0 on # link1 + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/lpc47m10x + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master CK804 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave CK804 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" +# register "nic_rom_address" = "0xfff80000" # 64k +# register "raid_rom_address" = "0xfff90000" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.0 on end # link 2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 + + chip northbridge/amd/amdk8 + device pci 19.0 on end # link 0 + device pci 19.0 on + # devices on link 1, link 1 == LDT 1 + chip southbridge/nvidia/ck804 + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 off end # SM + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 off end # IDE + device pci 7.0 off end # SATA 1 + device pci 8.0 off end # SATA 0 + device pci 9.0 off end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 +# register "nic_rom_address" = "0xfff80000" # 64k + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end # PCI domain + +end #root_complex Added: trunk/coreboot-v2/src/mainboard/supermicro/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,143 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 + device i2c 48 off end + device i2c 49 off end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff00000" #for 1M +# register "rom_address" = "0xfff80000" #for 512K + end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on #nec pci-x + end + device pci 0.1 on #nec pci-x + device pci 4.0 on end #scsi + device pci 4.1 on end #scsi + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 on end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,163 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff00000" #for 1M +# register "rom_address" = "0xfff80000" #for 512K + end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on #nec pci-x + end + device pci 0.1 on #nec pci-x + device pci 4.0 on end #scsi + device pci 4.1 on end #scsi + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 on end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,64 @@ +chip northbridge/intel/e7525 # mch + device pci_domain 0 on + chip southbridge/intel/esb6300 # esb6300 + register "pirq_a_d" = "0x0b0a0a05" + register "pirq_e_h" = "0x0a0b0c80" + + device pci 1c.0 on end + + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.4 on end + device pci 1d.5 on end + device pci 1d.7 on end + + device pci 1e.0 on end + + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.1 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + device pnp 2e.f off end + device pnp 2e.10 off end + device pnp 2e.14 off end + end + end + device pci 1f.1 on end + device pci 1f.2 on end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 on end + end + device pci 00.0 on end + device pci 00.1 on end + device pci 00.2 on end + device pci 02.0 on end + device pci 03.0 on end + device pci 04.0 on end + device pci 08.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # cpu0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # cpu1 + device apic 6 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,86 @@ +chip northbridge/intel/e7520 # MCH + chip drivers/generic/debug # DEBUGGING + device pnp 00.0 on end + device pnp 00.1 off end + device pnp 00.2 off end + device pnp 00.3 off end + end + device pci_domain 0 on + chip southbridge/intel/esb6300 # ESB6300 + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + + device pci 1c.0 on + chip drivers/generic/generic + device pci 01.0 on end # onboard gige1 + device pci 02.0 on end # onboard gige2 + end + end + + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.4 on end # Southbridge Watchdog timer + device pci 1d.5 on end # Southbridge I/O apic1 + device pci 1d.7 on end + + # VGA / PCI 32-bit + device pci 1e.0 on + chip drivers/generic/generic + device pci 01.0 on end + end + end + + + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + device pci 1f.1 on end + device pci 1f.2 off end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end + device pci 1f.6 off end + end + + device pci 00.0 on end # Northbridge + device pci 00.1 on end # Northbridge Error reporting + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge + device pci 00.1 on end # I/O apic + device pci 00.2 on end # bridge + device pci 00.3 on end # I/O apic + end + end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end + end + + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # CPU 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # CPU 1 + device apic 6 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,86 @@ +chip northbridge/intel/e7520 # MCH + chip drivers/generic/debug # DEBUGGING + device pnp 00.0 off end + device pnp 00.1 off end + device pnp 00.2 off end + device pnp 00.3 off end + end + device pci_domain 0 on + chip southbridge/intel/i82801er # ICH5R + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + + device pci 1c.0 on + chip drivers/generic/generic + device pci 01.0 on end # onboard gige1 + device pci 02.0 on end # onboard gige2 + end + end + + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.4 on end # Southbridge Watchdog timer + device pci 1d.5 on end # Southbridge I/O apic1 + device pci 1d.7 on end + + # VGA / PCI 32-bit + device pci 1e.0 on + chip drivers/generic/generic + device pci 01.0 on end + end + end + + + device pci 1f.0 on # ISA bridge + chip superio/nsc/pc87427 + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + device pci 1f.1 on end + device pci 1f.2 on end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end + device pci 1f.6 off end + end + + device pci 00.0 on end # Northbridge + device pci 00.1 on end # Northbridge Error reporting + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge + device pci 00.1 on end # I/O apic + device pci 00.2 on end # bridge + device pci 00.3 on end # I/O apic + end + end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end + end + + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # CPU 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # CPU 1 + device apic 6 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,84 @@ +chip northbridge/intel/e7520 # mch + device pci_domain 0 on + chip southbridge/intel/i82801er # i82801er + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + + # -> VGA + device pci 1e.0 on end + + # -> IDE + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + device pci 1f.1 on end + device pci 1f.2 on end + device pci 1f.3 on end + + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + end + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on end + device pci 03.0 on + chip southbridge/intel/pxhd # pxhd1 + # Bus bridges and ioapics usually bus 2 + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on + # On board gig e1000 + chip drivers/generic/generic + device pci 02.0 on end + device pci 02.1 on end + end + end + device pci 0.3 on end + end + end + device pci 04.0 on + chip southbridge/intel/pxhd # pxhd2 + # Bus bridges and ioapics usually bus 5 + device pci 0.0 on end + # Slot 6 is usually 6:2.0 + device pci 0.1 on end + device pci 0.2 on end + # Slot 7 is usually 7:2.0 + device pci 0.3 on end + end + end + device pci 06.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # cpu 1 + device apic 6 on end + end + end + register "intrline" = "0x00070105" +end + Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,75 @@ +chip northbridge/intel/e7520 # mch + device pci_domain 0 on + chip southbridge/intel/i82801er # i82801er + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + + # -> Bridge + device pci 1e.0 on end + + # -> ISA + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + # -> IDE + device pci 1f.1 on end + # -> SATA + device pci 1f.2 on end + device pci 1f.3 on end + + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + end + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + # Bus bridges and ioapics usually bus 1 + device pci 0.0 on + # On board gig e1000 + chip drivers/generic/generic + device pci 03.0 on end + device pci 03.1 on end + end + end + device pci 0.1 on end + device pci 0.2 on end + device pci 0.3 on end + end + end + device pci 04.0 on end + device pci 06.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # cpu 1 + device apic 6 on end + end + end + register "intrline" = "0x00070105" +end + Added: trunk/coreboot-v2/src/mainboard/technexion/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,117 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_S1G1 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff80000" + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff80000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex + Added: trunk/coreboot-v2/src/mainboard/technologic/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/technologic/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,16 @@ +chip cpu/amd/sc520 + device pci_domain 0 on + device pci 0.0 on end + +# chip drivers/pci/onboard +# device pci 12.0 on end # enet +# end +# chip drivers/pci/onboard +# device pci 14.0 on end # 69000 +# register "rom_address" = "0x2000000" +# end +# register "com1" = "{1}" +# register "com1" = "{1, 0, 0x3f8, 4}" + end + +end Added: trunk/coreboot-v2/src/mainboard/televideo/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,57 @@ +chip northbridge/amd/gx1 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 12.0 on # ISA bridge + chip superio/nsc/pc97317 # Super I/O + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC, Advanced power control (APC) + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy (N/A on this board) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe8 + end + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA (onboard) + device pci 13.0 on end # USB + device pci 14.0 on end # MiniPCI slot + device pci 15.0 on end # Ethernet (onboard) + register "ide0_enable" = "1" + register "ide1_enable" = "0" # Not available/needed on this board + end + end + chip cpu/amd/model_gx1 # CPU + end +end Added: trunk/coreboot-v2/src/mainboard/thomson/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/thomson/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/thomson/ip1000/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,73 @@ +chip northbridge/intel/i82830 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip drivers/pci/onboard # Onboard VGA + device pci 2.0 on end # VGA (Intel 82830 CGC) + register "rom_address" = "0xfff00000" + end + chip southbridge/intel/i82801xx # Southbridge + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x06" + register "pirqc_routing" = "0x07" + register "pirqd_routing" = "0x09" + register "pirqe_routing" = "0x0a" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + + register "ide0_enable" = "1" + register "ide1_enable" = "1" + + device pci 1d.0 on end # USB UHCI Controller #1 + device pci 1d.1 on end # USB UHCI Controller #2 + device pci 1d.2 on end # USB UHCI Controller #3 + device pci 1d.7 on end # USB2 EHCI Controller + device pci 1e.0 on # PCI bridge + device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet + end + device pci 1f.0 on # ISA/LPC bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # Com2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.9 off end # Game port + device pnp 2e.a on # PME + io 0x60 = 0x800 + end + device pnp 2e.b off end # MPU-401 + end + end + device pci 1f.1 on end # IDE + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC'97 audio + device pci 1f.6 off end # AC'97 modem + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479 + device apic 0 on end # APIC + end + end +end + Added: trunk/coreboot-v2/src/mainboard/totalimpact/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/totalimpact/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/totalimpact/briq/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/briq/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +chip northbridge/ibm/cpc710 + device pci_domain 0 on # 32bit pci bridge + device pci 0.0 on + chip southbridge/winbond/w83c553 + # FIXME The function numbers are ok but the device id is wrong here! + device pci 0.0 on end # pci to isa bridge + device pci 0.1 on end # pci ide controller + end + end + end + device cpu_bus 0 on + # chip cpu/ppc/ppc7xx + # device cpu 0 on end + # end + end +end + +## +## Build the objects we have code for in this directory. +## + +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" Added: trunk/coreboot-v2/src/mainboard/tyan/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +# Added: trunk/coreboot-v2/src/mainboard/tyan/s1846/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,55 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/nsc/pc87309 # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Power management + end + device pnp 2e.5 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/tyan/s2735/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,91 @@ +chip northbridge/intel/e7501 + device pci_domain 0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 2.0 on + chip southbridge/intel/i82870 + device pci 1c.0 on end + device pci 1d.0 on + chip drivers/pci/onboard + device pci 1.0 on end # intel lan + device pci 1.1 on end + end + end + device pci 1e.0 on end + device pci 1f.0 on end + end + end + device pci 6.0 on end + chip southbridge/intel/i82801er + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + device pci 1e.0 on + chip drivers/pci/onboard + device pci 1.0 on end # intel lan 10/100 + end + chip drivers/pci/onboard + device pci 2.0 on end # ati + end + end + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1f.1 off end + device pci 1f.2 on end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 off end + end # SB + end # PCI_DOMAIN + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 + device apic 6 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s2850/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,98 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # LDT0 + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + #chip drivers/ati/ragexl + chip drivers/pci/onboard + device pci b.0 on end + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device pci 1.5 on end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end + device pci 18.0 on end + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s2875/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,90 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + chip drivers/pci/onboard + device pci 5.0 on end + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 on end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s2880/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,105 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on + chip drivers/pci/onboard + device pci 9.0 on end #broadcom + device pci 9.1 on end + end +# chip drivers/lsi/53c1030 +# device pci a.0 on end +# device pci a.1 on end +# register "fw_address" = "0xfff8c000" +# end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + chip drivers/pci/onboard + device pci 5.0 on end #some sata + end + chip drivers/pci/onboard + device pci 6.0 on end #adti + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s2881/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,140 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # LDT0 + device pci 18.0 on end # LDT1 + device pci 18.0 on # northbridge + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on + chip drivers/pci/onboard + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + end + chip drivers/pci/onboard + device pci a.0 on end # Adaptic + device pci a.1 on end + end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + chip drivers/pci/onboard + device pci 5.0 on end # SiI + end + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + chip drivers/i2c/adm1027 # ADT7463A CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3 + device i2c 2d on end + end + chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN + device i2c 2a on end + end + chip drivers/generic/generic # Winbond HWM 0x92 + device i2c 49 on end + end + chip drivers/generic/generic # Winbond HWM 0x94 + device i2c 4a on end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s2882/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,135 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on + chip drivers/pci/onboard + device pci 6.0 on end # adaptec + device pci 6.1 on end + end + chip drivers/pci/onboard + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end + end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + chip drivers/pci/onboard + device pci 5.0 on end + end + # chip drivers/ati/ragexl + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff00000" + end + chip drivers/pci/onboard + device pci 8.0 on end #intel 10/100 + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.3 on +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 54 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 55 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 56 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 57 on end +# end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # NB + end #pci_domain +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s2885/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,135 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # LDT0 + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end + device pci 18.0 on end # LDT1 + device pci 18.0 on # northbridge + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on + chip drivers/pci/onboard + device pci 9.0 on end # broadcom 5703 + end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + chip drivers/pci/onboard + device pci b.0 on end # SiI 3114 + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # acpi + device pci 1.5 on end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + + end #pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end +# device pnp 0.1 off end +# device pnp 0.2 off end +# device pnp 0.3 off end +# device pnp 0.4 off end +# device pnp 0.5 on end +# end +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s2891/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,158 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 54 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 55 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 56 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 57 on end +# end + end # SM +# device pci 1.1 on # SM 1 +# chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 +# device i2c 2d on end +# end +# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 +# device i2c 2e on end +# end +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN +# device i2c 2a on end +# end +# chip drivers/generic/generic # Winbond HWM 0x92 +# device i2c 49 on end +# end +# chip drivers/generic/generic # Winbond HWM 0x94 +# device i2c 4a on end +# end +# end #SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + chip drivers/pci/onboard + device pci 7.0 on end + #register "rom_address" = "0xfff80000" #for 512K + register "rom_address" = "0xfff00000" #for 1M + end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + chip drivers/pci/onboard + device pci 9.0 on end + device pci 9.1 on end + end + end + device pci 1.1 on end + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #mc0 + + end # pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 off end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 on end # hard_reset +# end +end # root_complex Added: trunk/coreboot-v2/src/mainboard/tyan/s2892/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,158 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 + chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + device i2c 2d on end + end + chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + device i2c 2e on end + end + chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + device i2c 2a on end + end + chip drivers/generic/generic # Winbond HWM 0x92 + device i2c 49 on end + end + chip drivers/generic/generic # Winbond HWM 0x94 + device i2c 4a on end + end + end #SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff80000" + end + chip drivers/pci/onboard + device pci 8.0 on end + end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + chip drivers/pci/onboard + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end + end + end + device pci 1.1 on end + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #mc0 + + end # pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end +# device pnp 0.1 off end +# device pnp 0.2 off end +# device pnp 0.3 off end +# device pnp 0.4 off end +# device pnp 0.5 on end +# end +end # root_complex Added: trunk/coreboot-v2/src/mainboard/tyan/s2895/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,173 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/lpc47b397 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.8 on # HW Monitor + io 0x60 = 0x480 + chip drivers/generic/generic # LM95221 CPU temp + device i2c 2b on end + end + chip drivers/generic/generic # EMCT03 + device i2c 54 on end + end + end + device pnp 2e.a on # RT + io 0x60 = 0x400 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" +# register "nic_rom_address" = "0xfff80000" # 64k +# register "raid_rom_address" = "0xfff90000" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + chip drivers/pci/onboard + device pci 6.0 on end # lsi scsi + device pci 6.1 on end + end + end + device pci 1.1 on end + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #mc0 + + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 off end # SM + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 off end # IDE + device pci 7.0 off end # SATA 1 + device pci 8.0 off end # SATA 0 + device pci 9.0 off end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 +# register "nic_rom_address" = "0xfff80000" # 64k + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 off end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end +end # root_complex Added: trunk/coreboot-v2/src/mainboard/tyan/s2912/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,150 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,156 @@ +chip northbridge/amd/amdfam10/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F_1207 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 #mc0 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + # SB on link 2.0. + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 1.1 on # SM 1 +#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? +# chip drivers/generic/generic #PCIXA Slot1 +# device i2c 50 on end +# end +# chip drivers/generic/generic #PCIXB Slot1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #PCIXB Slot2 +# device i2c 52 on end +# end +# chip drivers/generic/generic #PCI Slot1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #Master MCP55 PCI-E +# device i2c 54 on end +# end +# chip drivers/generic/generic #Slave MCP55 PCI-E +# device i2c 55 on end +# end + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on + chip drivers/pci/onboard + device pci 4.0 on end + register "rom_address" = "0xfff00000" + end + end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_addr" = "0x51" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # mc0 + + end # PCI domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end +end #root_complex Added: trunk/coreboot-v2/src/mainboard/tyan/s4880/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,103 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # LDT0 + device pci 18.0 on end # LDT1 + device pci 18.0 on # northbridge + # devices on link 2, link 2 == LDT 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on +# chip drivers/lsi/53c1030 +# device pci 4.0 on end +# device pci 4.1 on end +# register "fw_address" = "0xfff8c000" +# end + chip drivers/pci/onboard + device pci 9.0 on end + device pci 9.1 on end + end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff80000" + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + + end #pci_domain +end + Added: trunk/coreboot-v2/src/mainboard/tyan/s4882/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,211 @@ +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on end # LDT0 + device pci 18.0 on # northbridge + # devices on link 1, link 1 == LDT 1 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on +# chip drivers/lsi/53c1030 +# device pci 4.0 on end +# device pci 4.1 on end +# register "fw_address" = "0xfff8c000" +# end + chip drivers/pci/onboard + device pci 9.0 on end #Broadcom + device pci 9.1 on end + end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + #chip drivers/ati/ragexl + chip drivers/pci/onboard + device pci 6.0 on end + register "rom_address" = "0xfff80000" + end + chip drivers/pci/onboard + device pci 5.0 on end #SiI + end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on +# chip drivers/i2c/i2cmux # pca9556 smbus mux +# device i2c 18 on #0 pca9516 2, 1 +# chip drivers/i2c/lm63 #cpu0 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #1 pca9516 1, 1 +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #2 pca9516 1, 2 +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #3 pca9516 1, 3 +# chip drivers/generic/generic #dimm 3-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 3-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 3-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 3-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #4 pca9516 1, 4 +# chip drivers/generic/generic #dimm 2-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 2-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 2-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 2-1-1 +# device i2c 53 on end +# end +# end +# device i2c 18 on #5 pca9516 2, 2 +# chip drivers/i2c/lm63 #cpu1 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #6 pca9516 2, 3 +# chip drivers/i2c/lm63 #cpu2 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #7 pca9516 2, 4 +# chip drivers/i2c/lm63 #cpu3 temp +# device i2c 4c on end +# end +# end +# end # i2cmux +# chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... +# device i2c 2e on end +# end +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid +# device i2c 2a on end +# end +# chip drivers/generic/generic # Winbond HWM 0x92 +# device i2c 49 on end +# end +# chip drivers/generic/generic # Winbond HWM 0x94 +# device i2c 4a on end +# end +# chip drivers/generic/generic # ?? +# device i2c 69 on end +# end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + + end +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 off end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 on end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 on end # dual core msr +# device pnp 0.6 on end # cache size +# device pnp 0.7 on end # tsc +# end +end + Added: trunk/coreboot-v2/src/mainboard/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,37 @@ +choice + prompt "Mainboard model" + depends on VENDOR_VIA + +config BOARD_VIA_VT8454C + bool "vt8454c" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CX700 +# select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_VIA_VT1211 + select PIRQ_TABLE +# select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + help + Kontron 986LCD-M Series mainboards +endchoice + +config MAINBOARD_DIR + string + default via/vt8454c + depends on BOARD_VIA_VT8454C + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + depends on BOARD_VIA_VT8454C + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_VIA_VT8454C + +config MAINBOARD_PART_NUMBER + string + default "VT8454C" + depends on BOARD_VIA_VT8454C Added: trunk/coreboot-v2/src/mainboard/via/epia/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,65 @@ +chip northbridge/via/vt8601 + device pci_domain 0 on + device pci 0.0 on end # Northbridge +# device pci 0.1 on # AGP bridge + # chip drivers/pci/onboard # Integrated VGA + # device pci 0.0 on end + # register "rom_adress" = "0xfff80000" + # end +# end + chip southbridge/via/vt8231 + register "enable_native_ide" = "0" + register "enable_com_ports" = "1" + register "enable_keyboard" = "0" + device pci 11.0 on # Southbrdge + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + register "com1" = "{CONFIG_TTYS0_BAUD}" + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + end + device pci 11.1 on end # Ide + device pci 11.2 off end # Usb port 0-1 + device pci 11.3 off end # Usb port 2-3 + device pci 11.4 off end # ACPI + device pci 11.5 off end # AC97 Audio + device pci 11.6 on end # AC97 Modem + device pci 12.0 on end # Ethernet + end + end + + device apic_cluster 0 on + chip cpu/via/model_c3 + device apic 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,61 @@ +chip northbridge/via/cn700 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + device pci f.0 on end # IDE + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci 10.0 on end # OHCI + device pci 10.1 on end # OHCI + device pci 10.2 on end # OHCI + device pci 10.3 on end # OHCI + device pci 10.4 on end # EHCI + device pci 10.5 on end # UDCI + device pci 11.0 on # Southbridge LPC + chip superio/via/vt1211 # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end + end + device pci 11.5 on end # AC'97 audio + # device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end # Ethernet + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end Added: trunk/coreboot-v2/src/mainboard/via/epia-m/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,57 @@ +chip northbridge/via/vt8623 + + device apic_cluster 0 on + chip cpu/via/model_c3 + device apic 0 on end + end + end + + device pci_domain 0 on + chip southbridge/via/vt8235 + + device pci 10.0 on end # USB 1.1 + device pci 10.1 on end # USB 1.1 + device pci 10.2 on end # USB 1.1 + device pci 10.3 on end # USB 2 + + device pci 11.0 on # Southbridge + chip superio/via/vt1211 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + + end + end + + device pci 11.1 on end # IDE + # 2-4 non existant? + device pci 11.5 on end # AC97 Audio + device pci 11.6 off end # AC97 Modem + device pci 12.0 on end # Ethernet + end +# This is on the EPIA MII, not the M. + chip southbridge/ricoh/rl5c476 + register "enable_cf" = "1" + device pci 0a.0 on end + device pci 0a.1 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,24 @@ +chip northbridge/via/vx800 # Northbridge + device pci_domain 0 on + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + # device pci f.0 on end # IDE/SATA + # device pci f.1 on end # IDE + # device pci 10.0 on end # USB 1.1 + # device pci 10.1 on end # USB 1.1 + # device pci 10.2 on end # USB 1.1 + # device pci 10.4 on end # USB 2.0 + # device pci 11.0 on # Southbridge LPC + # end + end + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end Added: trunk/coreboot-v2/src/mainboard/via/pc2500e/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,88 @@ +chip northbridge/via/cn700 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + device pci f.0 on end # SATA + device pci f.1 on end # IDE + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci 10.0 on end # UHCI + device pci 10.1 on end # UHCI + device pci 10.2 on end # UHCI + device pci 10.3 on end # UHCI + device pci 10.4 on end # EHCI + device pci 10.5 on end # UDCI + device pci 11.0 on # Southbridge LPC + chip superio/ite/it8716f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # COM2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x0000 + irq 0x70 = 9 + end + device pnp 2e.5 off # PS/2 keyboard (not used) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # PS/2 mouse (not used) + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0000 + io 0x62 = 0x0800 + io 0x64 = 0x0000 + end + device pnp 2e.8 off # MIDI port (N/A) + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # Game port (N/A) + io 0x60 = 0x201 + end + device pnp 2e.a on # Consumer IR + io 0x60 = 0x310 + irq 0x70 = 11 + end + end + end + device pci 11.5 on end # AC'97 audio + # device pci 11.6 off end # AC'97 modem (N/A) + device pci 12.0 on end # Ethernet + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end Added: trunk/coreboot-v2/src/mainboard/via/vt8454c/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +driver-y += mainboard.o + +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/via/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/via/vt8454c/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/devicetree.cb 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,59 @@ +chip northbridge/via/cx700 + device apic_cluster 0 on + chip cpu/via/model_c7 + device apic 0 on end + end + end + device pci_domain 0 on + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on # PCI Bridge + chip drivers/pci/onboard + device pci 0.0 on end + #register "rom_address" = "0xfffc0000" #256k image + register "rom_address" = "0xfff80000" #512k image + #register "rom_address" = "0xfff00000" #1024k image + end # Onboard Video + end # PCI Bridge + device pci f.0 on end # IDE/SATA + #device pci f.1 on end # IDE + device pci 10.0 on end # USB 1.1 + device pci 10.1 on end # USB 1.1 + device pci 10.2 on end # USB 1.1 + device pci 10.4 on end # USB 2.0 + device pci 11.0 on # Southbridge LPC + chip superio/via/vt1211 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end # superio + end # pci 11.0 + # 1-4 non existant + #device pci 11.5 on end # AC97 Audio + #device pci 11.6 off end # AC97 Modem + #device pci 12.0 on end # Ethernet + end # pci domain 0 +end # cx700 + Added: trunk/coreboot-v2/src/northbridge/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,5 @@ +#source src/northbridge/amd/Kconfig +#source src/northbridge/ibm/Kconfig +source src/northbridge/intel/Kconfig +#source src/northbridge/motorola/Kconfig +source src/northbridge/via/Kconfig Added: trunk/coreboot-v2/src/northbridge/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,5 @@ +#subdirs-y += amd +#subdirs-y += ibm +subdirs-y += intel +#subdirs-y += motorola +subdirs-y += via Added: trunk/coreboot-v2/src/northbridge/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,7 @@ +#source src/northbridge/amd/amdfam10/Kconfig +#source src/northbridge/amd/amdht/Kconfig +source src/northbridge/amd/amdk8/Kconfig +#source src/northbridge/amd/amdmct/Kconfig +#source src/northbridge/amd/gx1/Kconfig +#source src/northbridge/amd/gx2/Kconfig +#source src/northbridge/amd/lx/Kconfig Added: trunk/coreboot-v2/src/northbridge/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,8 @@ +subdirs-$(CPU_AMD_K10) += amdfam10 +subdirs-$(CPU_AMD_HT) += amdht +subdirs-$(CPU_AMD_K8) += amdk8 +subdirs-$(CPU_AMD_MCT) += amdmct +subdirs-$(CPU_AMD_GX1) += gx1 +subdirs-$(CPU_AMD_GX2) += gx2 +subdirs-$(CPU_AMD_LX) += lx + Added: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_AMDK8 + bool + default n Added: trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + bool + default n Added: trunk/coreboot-v2/src/northbridge/ibm/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/ibm/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/ibm/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#source src/northbridge/ibm/cpc710/Kconfig +#source src/northbridge/ibm/cpc925/Kconfig Added: trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +subdirs-y += cpc710 +subdirs-y += cpc925 Added: trunk/coreboot-v2/src/northbridge/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,10 @@ +#source src/northbridge/intel/e7501/Kconfig +#source src/northbridge/intel/e7520/Kconfig +#source src/northbridge/intel/e7525/Kconfig +#source src/northbridge/intel/i3100/Kconfig +#source src/northbridge/intel/i440bx/Kconfig +source src/northbridge/intel/i82810/Kconfig +#source src/northbridge/intel/i82830/Kconfig +#source src/northbridge/intel/i855gme/Kconfig +#source src/northbridge/intel/i855pm/Kconfig +source src/northbridge/intel/i945/Kconfig Added: trunk/coreboot-v2/src/northbridge/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,10 @@ +#subdirs-y += e7501 +#subdirs-y += e7520 +#subdirs-y += e7525 +#subdirs-y += i3100 +#subdirs-y += i440bx +subdirs-y += i82810 +#subdirs-y += i82830 +#subdirs-y += i855gme +#subdirs-y += i855pm +subdirs-y += i945 Added: trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config HAVE_HIGH_TABLES + bool "Do we have high tables" + default y + +config NORTHBRIDGE_INTEL_I82810 + bool + default n + Added: trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += northbridge.o + Added: trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_INTEL_I945 + bool + default n Added: trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += northbridge.o +driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += gma.o +ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) + obj-$(CONFIG_NORTHBRIDGE_INTEL_I945) += acpi.o +endif Added: trunk/coreboot-v2/src/northbridge/motorola/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/motorola/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/motorola/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +#source src/northbridge/motorola/mpc107/Kconfig Added: trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += mpc107 Added: trunk/coreboot-v2/src/northbridge/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,5 @@ +#source src/northbridge/via/cn700/Kconfig +source src/northbridge/via/cx700/Kconfig +#source src/northbridge/via/vt8601/Kconfig +#source src/northbridge/via/vt8623/Kconfig +#source src/northbridge/via/vx800/Kconfig Added: trunk/coreboot-v2/src/northbridge/via/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/via/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,6 @@ +#subdirs-y += vt8601 +#subdirs-y += vt8623 +#subdirs-y += cn700 +subdirs-y += cx700 +#subdirs-y += vx800 + Added: trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,3 @@ +config NORTHBRIDGE_VIA_CX700 + bool + default n Added: trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,25 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_reset.o +obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += northbridge.o +obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += vgabios.o + +driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_agp.o +driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_lpc.o +driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_sata.o +driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_vga.o Added: trunk/coreboot-v2/src/pc80/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/pc80/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/pc80/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,9 @@ +obj-y += mc146818rtc.o +obj-y += isa-dma.o +obj-y += i8259.o +#obj-y += udelay_timer2.o CONFIG_UDELAY_TIMER2 +obj-$(CONFIG_UDELAY_IO) += udelay_io.o +obj-y += keyboard.o + +#initobj-y += serial.o + Modified: trunk/coreboot-v2/src/pc80/serial.c =================================================================== --- trunk/coreboot-v2/src/pc80/serial.c 2009-08-12 05:49:48 UTC (rev 4533) +++ trunk/coreboot-v2/src/pc80/serial.c 2009-08-12 15:00:51 UTC (rev 4534) @@ -71,7 +71,7 @@ uart_wait_until_sent(); } -static void uart_init(void) +void uart_init(void) { /* disable interrupts */ outb(0x0, CONFIG_TTYS0_BASE + UART_IER); Added: trunk/coreboot-v2/src/southbridge/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,8 @@ +#source src/southbridge/amd/Kconfig +#source src/southbridge/broadcom/Kconfig +source src/southbridge/intel/Kconfig +#source src/southbridge/nvidia/Kconfig +#source src/southbridge/ricoh/Kconfig +#source src/southbridge/sis/Kconfig +#source src/southbridge/via/Kconfig +#source src/southbridge/winbond/Kconfig Added: trunk/coreboot-v2/src/southbridge/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,8 @@ +#subdirs-y += amd +#subdirs-y += broadcom +subdirs-y += intel +#subdirs-y += nvidia +#subdirs-y += ricoh +#subdirs-y += sis +#subdirs-y += via +#subdirs-y += winbond Added: trunk/coreboot-v2/src/southbridge/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,10 @@ +source src/southbridge/amd/amd8111/Kconfig +source src/southbridge/amd/amd8131/Kconfig +source src/southbridge/amd/amd8131-disable/Kconfig +source src/southbridge/amd/amd8132/Kconfig +source src/southbridge/amd/amd8151/Kconfig +source src/southbridge/amd/cs5530/Kconfig +source src/southbridge/amd/cs5535/Kconfig +source src/southbridge/amd/cs5536/Kconfig +source src/southbridge/amd/rs690/Kconfig +source src/southbridge/amd/sb600/Kconfig Added: trunk/coreboot-v2/src/southbridge/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,11 @@ +subdirs-$(SOUTHBRIDGE_AMD_AMD8111) += amd8111 +subdirs-$(SOUTHBRIDGE_AMD_AMD8131) += amd8131 +subdirs-$(SOUTHBRIDGE_AMD_AMD8112) += amd8132 +subdirs-$(SOUTHBRIDGE_AMD_AMD8151) += amd8151 +subdirs-$(SOUTHBRIDGE_AMD_RS690) += rs690 +subdirs-$(SOUTHBRIDGE_AMD_SB600) += sb600 + +subdirs-$(SOUTHBRIDGE_AMD_CS5530) += cs5530 +subdirs-$(SOUTHBRIDGE_AMD_CS5535) += cs5535 +subdirs-$(SOUTHBRIDGE_AMD_CS5536) += cs5536 + Added: trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_AMD_AMD8111 + bool + default n + Added: trunk/coreboot-v2/src/southbridge/broadcom/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,3 @@ +source src/southbridge/broadcom/bcm21000/Kconfig +source src/southbridge/broadcom/bcm5780/Kconfig +source src/southbridge/broadcom/bcm5785/Kconfig Added: trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,4 @@ +subdirs-y += bcm21000 +subdirs-y += bcm5780 +subdirs-y += bcm5785 + Added: trunk/coreboot-v2/src/southbridge/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,10 @@ +#source src/southbridge/intel/esb6300/Kconfig +#source src/southbridge/intel/i3100/Kconfig +source src/southbridge/intel/i82371eb/Kconfig +#source src/southbridge/intel/i82801ca/Kconfig +#source src/southbridge/intel/i82801dbm/Kconfig +#source src/southbridge/intel/i82801er/Kconfig +source src/southbridge/intel/i82801gx/Kconfig +source src/southbridge/intel/i82801xx/Kconfig +#source src/southbridge/intel/i82870/Kconfig +#source src/southbridge/intel/pxhd/Kconfig Added: trunk/coreboot-v2/src/southbridge/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,11 @@ +#subdirs-y += esb6300 +#subdirs-y += i3100 +subdirs-y += i82371eb +#subdirs-y += i82801ca +#subdirs-y += i82801dbm +#subdirs-y += i82801er +subdirs-y += i82801gx +subdirs-y += i82801xx +#subdirs-y += i82870 +#subdirs-y += pxhd + Added: trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,3 @@ +config SOUTHBRIDGE_INTEL_I82371EB + boolean + Added: trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_isa.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_ide.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_usb.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_smbus.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_reset.o + +#initobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_early_rom.o Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_INTEL_I82801GX + bool + default n + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_ac97.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_azalia.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_ide.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_lpc.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_nic.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_pci.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_pcie.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_sata.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smbus.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_usb.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_usb_ehci.o + +object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_reset.o +object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_watchdog.o + +# arg. How does the linux kconfig handle compound conditionals? +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) + object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smi.o + smmobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smihandler.o +endif Added: trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_INTEL_I82801XX + bool + default n + Added: trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_ac97.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_ide.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_lpc.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_nic.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_pci.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_sata.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_smbus.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb.o +driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb_ehci.o + +object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_reset.o +object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_watchdog.o + +# TODO: What about cmos_failover.c? + Added: trunk/coreboot-v2/src/southbridge/nvidia/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/nvidia/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +source src/southbridge/nvidia/ck804/Kconfig +source src/southbridge/nvidia/mcp55/Kconfig Added: trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,3 @@ +subdirs-y += ck804 +subdirs-y += mcp55 + Added: trunk/coreboot-v2/src/southbridge/ricoh/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/ricoh/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +source src/southbridge/ricoh/rl5c476/Kconfig Added: trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += rl5c476 Added: trunk/coreboot-v2/src/southbridge/sis/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/sis/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +source src/southbridge/sis/sis966/Kconfig Added: trunk/coreboot-v2/src/southbridge/sis/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/sis/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +subdirs-y += sis966 + Added: trunk/coreboot-v2/src/southbridge/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,5 @@ +source src/southbridge/via/k8t890/Kconfig +source src/southbridge/via/vt8231/Kconfig +source src/southbridge/via/vt8235/Kconfig +source src/southbridge/via/vt8237r/Kconfig +source src/southbridge/via/vt82c686/Kconfig Added: trunk/coreboot-v2/src/southbridge/via/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/via/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,5 @@ +subdirs-y += k8t890 +subdirs-y += vt8231 +subdirs-y += vt8235 +subdirs-y += vt8237r +subdirs-y += vt82c686 Added: trunk/coreboot-v2/src/southbridge/winbond/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/winbond/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/winbond/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +source src/southbridge/winbond/w83c553/Kconfig Added: trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += w83c553 Added: trunk/coreboot-v2/src/superio/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,8 @@ +source src/superio/fintek/Kconfig +source src/superio/intel/Kconfig +source src/superio/ite/Kconfig +source src/superio/nsc/Kconfig +source src/superio/serverengines/Kconfig +source src/superio/smsc/Kconfig +source src/superio/via/Kconfig +source src/superio/winbond/Kconfig Added: trunk/coreboot-v2/src/superio/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,10 @@ + +subdirs-y += fintek +subdirs-y += intel +subdirs-y += ite +subdirs-y += nsc +#subdirs-y += serverengine +subdirs-y += smsc +subdirs-y += via +subdirs-y += winbond + Added: trunk/coreboot-v2/src/superio/fintek/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/fintek/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/fintek/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +config SUPERIO_FINTEK_F71805F + bool Added: trunk/coreboot-v2/src/superio/fintek/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/fintek/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/fintek/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += f71805f Added: trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.o + Added: trunk/coreboot-v2/src/superio/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/intel/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/intel/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +config SUPERIO_FINTEK_I3100 + bool Added: trunk/coreboot-v2/src/superio/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/intel/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/intel/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += i3100 Added: trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Arastra, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_INTEL_I3100) += superio.o + Added: trunk/coreboot-v2/src/superio/ite/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/ite/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/ite/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,14 @@ +config SUPERIO_ITE_IT8661F + bool +config SUPERIO_ITE_IT8671F + bool +config SUPERIO_ITE_IT8673F + bool +config SUPERIO_ITE_IT8705F + bool +config SUPERIO_ITE_IT8712F + bool +config SUPERIO_ITE_IT8716F + bool +config SUPERIO_ITE_IT8718F + bool Added: trunk/coreboot-v2/src/superio/ite/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,7 @@ +subdirs-y += it8661f +subdirs-y += it8671f +subdirs-y += it8673f +subdirs-y += it8705f +subdirs-y += it8712f +subdirs-y += it8716f +subdirs-y += it8718f Added: trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.o + Added: trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.o + Added: trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_ITE_IT8673F) += superio.o + Added: trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.o + Added: trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.o + Added: trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.o + Added: trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.o + Added: trunk/coreboot-v2/src/superio/nsc/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/nsc/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,18 @@ +config SUPERIO_NSC_PC8374 + bool +config SUPERIO_NSC_PC87309 + bool +config SUPERIO_NSC_PC87351 + bool +config SUPERIO_NSC_PC87360 + bool +config SUPERIO_NSC_PC87366 + bool +config SUPERIO_NSC_PC87417 + bool +config SUPERIO_NSC_PC87427 + bool +config SUPERIO_NSC_PC97307 + bool +config SUPERIO_NSC_PC97317 + bool Added: trunk/coreboot-v2/src/superio/nsc/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,9 @@ +subdirs-y += pc8374 +subdirs-y += pc87309 +subdirs-y += pc87351 +subdirs-y += pc87360 +subdirs-y += pc87366 +subdirs-y += pc87417 +subdirs-y += pc87427 +subdirs-y += pc97307 +subdirs-y += pc97317 Added: trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC8374) += superio.o Added: trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC87309) += superio.o + Added: trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC87351) += superio.o Added: trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC87360) += superio.o Added: trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC87366) += superio.o Added: trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC87417) += superio.o Added: trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC87427) += superio.o Added: trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC97307) += superio.o Added: trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_NSC_PC97317) += superio.o Added: trunk/coreboot-v2/src/superio/serverengines/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/serverengines/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +config SERVERENGINES_ITE_PILOT + bool Added: trunk/coreboot-v2/src/superio/smsc/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/smsc/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,12 @@ +config SUPERIO_SMCSC_FDC37M60X + bool +config SUPERIO_SMCSC_LPC47B272 + bool +config SUPERIO_SMCSC_LPC47B397 + bool +config SUPERIO_SMCSC_LPC47M10X + bool +config SUPERIO_SMCSC_LPC47N217 + bool +config SUPERIO_SMCSC_SMSCSUPERIO + bool Added: trunk/coreboot-v2/src/superio/smsc/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/smsc/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,6 @@ +subdirs-y += fdc37m60x +subdirs-y += lpc47b272 +subdirs-y += lpc47b397 +subdirs-y += lpc47m10x +subdirs-y += lpc47n217 +subdirs-y += smscsuperio Added: trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_SMSC_FDC37M60X) += superio.o + Added: trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2005 Digital Design Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_SMSC_DEVICE) += superio.o + Added: trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.o Added: trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.o Added: trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2005 Digital Design Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.o Added: trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.o + Added: trunk/coreboot-v2/src/superio/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/via/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/via/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +config SUPERIO_VIA_VT1211 + bool Added: trunk/coreboot-v2/src/superio/via/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/via/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/via/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1 @@ +subdirs-y += vt1211 Added: trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_VIA_VT1211) += vt1211.o Added: trunk/coreboot-v2/src/superio/winbond/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/winbond/Kconfig (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/Kconfig 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,18 @@ +config SUPERIO_WINBOND_W83627DHG + boolean +config SUPERIO_WINBOND_W83627EHG + boolean +config SUPERIO_WINBOND_W83627HF + boolean +config SUPERIO_WINBOND_W83627THF + boolean +config SUPERIO_WINBOND_W83627THG + boolean +config SUPERIO_WINBOND_W83627UHG + boolean +config SUPERIO_WINBOND_W83697HF + boolean +config SUPERIO_WINBOND_W83977F + boolean +config SUPERIO_WINBOND_W83977TF + boolean Added: trunk/coreboot-v2/src/superio/winbond/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,9 @@ +subdirs-y += w83627dhg +subdirs-y += w83627ehg +subdirs-y += w83627hf +subdirs-y += w83627thf +subdirs-y += w83627thg +subdirs-y += w83627uhg +subdirs-y += w83697hf +subdirs-y += w83977f +subdirs-y += w83977tf Added: trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.o + Added: trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.o + Added: trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83627THF) += superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83627THG) += superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Dynon Avionics +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $ +## + +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Sean Nelson +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Nikolay Petukhov +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83977F) += superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc 2009-08-12 15:00:51 UTC (rev 4534) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_WINBOND_W83977TF) += superio.o Modified: trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb 2009-08-12 05:49:48 UTC (rev 4533) +++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb 2009-08-12 15:00:51 UTC (rev 4534) @@ -5,9 +5,14 @@ ## (normal AND fallback images and payloads). option CONFIG_ROM_SIZE = 1024 * 1024 +option CONFIG_CBFS=1 +option HAVE_HIGH_TABLES=1 +option MAXIMUM_CONSOLE_LOGLEVEL=9 +option DEFAULT_CONSOLE_LOGLEVEL=9 + romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE = 1 - payload ../payload.elf + payload /tmp/bios.bin.elf end buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" Modified: trunk/coreboot-v2/util/abuild/abuild =================================================================== --- trunk/coreboot-v2/util/abuild/abuild 2009-08-12 05:49:48 UTC (rev 4533) +++ trunk/coreboot-v2/util/abuild/abuild 2009-08-12 15:00:51 UTC (rev 4534) @@ -103,7 +103,7 @@ { # make this a f