[coreboot] [v2] r4569 - trunk/coreboot-v2/src/northbridge/amd/amdmct/mct

[svn at coreboot.org]

Author: zbao
Date: 2009-08-25 06:12:55 +0200 (Tue, 25 Aug 2009)
New Revision: 4569

Modified:
   trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
Log:
Without this patch, if we only got a DIMM in Channel B, memory can not be
set up correctly. Now it can. Please test it.

Moving "mct_AfterGetCLT(pMCTstat, pDCTstat, dct);" out of the "if" is the
key point.
Changing the Get_DIMMAddress_D(pDCTstat, i) to Get_DIMMAddress_D(pDCTstat, dct + i)
doesnt seem to take any effect. But I believe this is what it should be.

And a duplicated semicolon is removed.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c	2009-08-25 01:06:39 UTC (rev 4568)
+++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c	2009-08-25 04:12:55 UTC (rev 4569)
@@ -352,7 +352,7 @@
 	nv_DQSTrainCTL = 1;
 
 	print_t("DQSTiming_D: mct_BeforeDQSTrain_D:\n");
-	mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);;
+	mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
 	phyAssistedMemFnceTraining(pMCTstat, pDCTstatA);
 
 	if (nv_DQSTrainCTL) {
@@ -982,8 +982,8 @@
 		if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
 			pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1;
 
-		mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
 	}
+	mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
 
 	/* Gather all DIMM mini-max values for cycle timing data */
 	Rows = 0;
@@ -1001,7 +1001,7 @@
 	for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
 		LDIMM = i >> 1;
 		if (pDCTstat->DIMMValid & (1 << i)) {
-			smbaddr = Get_DIMMAddress_D(pDCTstat, i);
+			smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i);
 			byte = mctRead_SPD(smbaddr, SPD_ROWSZ);
 			if (Rows < byte)
 				Rows = byte;	/* keep track of largest row sz */