[coreboot] [PATCH] amd/pistachio and technexion/tim8960 devicetree.cb comments

[Carl-Daniel Hailfinger]

r4534 introduced devicetree.cb in every mainboard directory, but didn't
copy any comment lines before the start of the device tree.
Fix up amd/pistachio and technexion/tim8960.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb
===================================================================
--- LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb	(Revision 4614)
+++ LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb	(Arbeitskopie)
@@ -1,3 +1,14 @@
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff0000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#Define gfx_dual_slot, 0: single slot, 1: dual slot
+#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
+#Define gfx_tmds, 0: didn't support TMDS, 1: support
+#Define gfx_compliance, 0: didn't support compliance, 1: support
+#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
+#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on
 		chip cpu/amd/socket_AM2
Index: LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb
===================================================================
--- LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb	(Revision 4614)
+++ LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb	(Arbeitskopie)
@@ -1,3 +1,14 @@
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define vga_rom_address = 0xfff80000
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#Define gfx_dual_slot, 0: single slot, 1: dual slot
+#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
+#Define gfx_tmds, 0: didn't support TMDS, 1: support
+#Define gfx_compliance, 0: didn't support compliance, 1: support
+#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
+#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on
 		chip cpu/amd/socket_S1G1


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