[coreboot] GeodeLX RAM initialisation issue

ron minnich rminnich at gmail.com
Fri Dec 4 18:16:37 CET 2009

On Fri, Dec 4, 2009 at 9:12 AM, Daniel Mack <daniel at caiaq.de> wrote:

> Help me understanding how the DRAM can be programmed correctly. Is it
> about timing constraints?

it's how you set the timing in the dram controller and how it matches
the DRAM, but it's also about the order in which you program things
and the timing of how you issue the commands. If you're doing v3 this
should all "just work", it certainly used to for me. But I have not
touched this code in 9 months or more.

> That could well be an explanation for what I'm seeing, however, I wonder
> why all boards work totally stable once they booted. Wouldn't wrong DRAM
> settings result in unpredictable behaviour such as sporadic fails? I
> don't see anything like that.

I wish I knew.

> I was unplugging the DC jack from the board. There is some blocking
> capacitors on it, but I doubt they will cause any part of the system to
> survive much longer than a couple of seconds. But even something like
> 10s doesn't solve it. Only sometimes though, and I haven't found a
> reliable pattern yet. Damn, I really wish I could provide more specific
> input :-/

This points more to what Myles was saying -- you might want to zero
all of memory and see if that helps. Are you using crosstool to build?
If not, you should.


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