[coreboot] VIA EDEN ESP (C3) + Apollo CLE266(VT8623) + VT8237R + W83627HG

Andrej Skirn andrejskirn at celestials.net
Thu Dec 10 04:26:20 CET 2009

Stefan Reinauer wrote:
> Are you configuring your Super IO correctly? Did you call your Super IO
> init function in auto.c? Compare your settings with the output of
> superiotool -d
I'm using the EPIA-N as basis, as shown earlier. This uses the same 
super-IO, so the super-IO config is presumably correct. I don't seem to 
be getting the serial port IO-cycles on the LPC bus though, which is not 
such a surprise because I can't find out where the chipset is supposed 
to be set to redirect it to LPC. The CN400 versions have:

   /* Enable multifunction for northbridge. */
    pci_write_config8(ctrl.d0f0, 0x4f, 0x01);


   w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);


I'm assuming the "multifunction" may have somethng to do with the LPC, 
although I thought LPC controller is always in southbridge. I didn't 
seem to find any VT8237R + W83627HG setup code, but I'm still surprised 
not to find any apparent serial IO to LPC setting anywhere. It might be 
the default, but then I don't understand why I'm not seeing the IO 
cycles on the bus. I guess I'll have to try out different IO port ranges 
and chipset registers.

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