[coreboot] More SeaBIOS timings

Tom Sylla tsylla at gmail.com
Mon Dec 21 16:29:54 CET 2009

This looks like it was an interesting task. I had some questions and
comments from previous fast-POST exercises:

On Mon, Dec 21, 2009 at 12:44 AM, Kevin O'Connor <kevin at koconnor.net> wrote:
> * cpu appears to start running around 350ms

Do you have a scope at all?. The only way to know this number for sure
would be to put a scope on the reset wire and the rs-232 to see how
long the power sequence takes.

> * smbus power stabilizes around 400ms

I don't understand this. SMBus power is 3.3V, and I don't know why a
platform would be executing code before 3.3V is stable. The ATX is
turning on 3.3, 5, and 12 *first*, then the various regulators,
including the core regulator, come on after that. There should be
various hardware voltage monitors keeping things in reset until all
the voltages are up. Am I not understanding something? What exactly do
you mean by "smbus power stabilizes"?

> * I've commented out the calls to wbinvd() in coreboot's mtrr
>  cache_disable logic - those calls are expensive and the code seems
>  to work without it.

You removed *all* of them? You might just be getting lucky, that is a
bit dangerous.

Just a note: PCI has a specified time called Trhfa which is the time
from reset going high to the first allowable configuration access. It
is specified as 2^25 clocks, which is 1 second for 33MHz PCI and 500ms
for 66MHz PCI. You have to heed that if you want to generically
support random PCI plugin cards. If you are making fixed-configuration
concessions, then you can do it as fast as your particular hardware

More information about the coreboot mailing list