[coreboot] flashrom SB600 LPC vs SPI, ROM straps

Bao, Zheng Zheng.Bao at amd.com
Wed Feb 4 04:59:11 CET 2009

About 2, we don't have to know where the board boots. If we assume the
cross-burning is not allowed, the flashrom can not detect the existence
of a SPI chip. Then it will not do any SPI action. Right?


-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Peter Stuge
Sent: Wednesday, February 04, 2009 11:40 AM
To: coreboot at coreboot.org
Subject: Re: [coreboot] flashrom SB600 LPC vs SPI, ROM straps


Bao, Zheng wrote:
> This patch is about flashrom running on dbm690t.
> It was sent several months ago and hasn't got any response yet.

Thanks for sending it, and thank you very much for the reminder!
I sometimes forget about patches on the mailing list. Sorry for
the delay.

> Now it deals with 3 problems.
> 1. Fix the bug that the flashrom would hang if there is not SPI
>    chip. A timeout detection was added.

Carl-Daniel confirmed that flashrom hangs while trying to probe for
SPI flash chips, if the system is not using SPI.

> 2. We only access LPC ROM if we boot via LPC ROM. And only SPI ROM
>    if we boot via SPI ROM. Doing crossly is not allowed. Anybody
>    has better idea?

This is a good idea, but at the moment enable_flash_sb600() in
chipset_enable.c assumes that SB600 is always using SPI.

The best fix for 2. (and I believe it will also fix 1. without the
need for a timeout, but the timeout can be a good idea anyway) is to
make sure that enable_flash_sb600() sets

flashbus = BUS_TYPE_SB600_SPI;

only when SPI is actually used. In that case flashrom will not call
any SB600 SPI functions.

If the enable functions do not set flashbus then flashrom falls back
to assume direct CPU access, which will work correctly.

The SB600 RRG says that the BypassRom bits in FakeAsrEn (0xcd6 0x8f)
will only _override_ the strap setting, so I think that they can not
be used by software to read the ROM straps.

We need another method to find out what was used to boot the system.
The only way to more information that I can find is to read the LPC
ROM Address Range registers in the LPC/ISA bridge, register 0x68 and
test for the special value meaning that the LPC strap is disabled.
RRG page 256.

However: LPC being disabled does not mean that SPI is enabled. The
straps can also be FWH and PCI. How can we read the ROM straps?

> 3. When we read/write SPI, we use memory read/write instead of
>    sending SPI command.

Yes, this is a really nice feature of the SB600! :)


coreboot mailing list: coreboot at coreboot.org

More information about the coreboot mailing list