[coreboot] [v3][patch] Add early MTRR setup

Marc Jones marcj303 at gmail.com
Fri Feb 6 23:37:28 CET 2009

Setup the MTRRs in stage1 so that memory and cache are available throughout
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.

Signed-off-by: Marc Jones <marcj303 at gmail.com>
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