[coreboot] cached SMI handler
kevin at koconnor.net
Sat Feb 7 17:40:29 CET 2009
On Sat, Feb 07, 2009 at 05:31:37PM +0100, Carl-Daniel Hailfinger wrote:
> > If the SMI handler is set to run code at 0xa0000 (ie, it has an SMBASE
> > of 0x98000), then it would see the 'jmp' insn and start running OS
> > code at 0x10000.
> This needs a unified cache, though.
If you get the jmp insn into the L2 cache, the icache should pull from
L2. It will be a little tricky to get the insn into L2 (and not just
L1 dcache), but I can think of several ways to try.
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