[coreboot] [v3][patch] Add early MTRR setup

Marc Jones marcj303 at gmail.com
Sat Feb 7 18:28:58 CET 2009

On Sat, Feb 7, 2009 at 4:05 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 06.02.2009 23:37, Marc Jones wrote:
>> Setup the MTRRs in stage1 so that memory and cache are available throughout
>> stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
>> It also sets all system memory to WriteBack cached and sets the ROM
>> area to cached.
>> Signed-off-by: Marc Jones <marcj303 at gmail.com>
> The code looks scary, especially the part where you disable cache
> although memory may not be set up completely yet. Can you explain why
> that is not a problem? Thanks.
> My general principle is "don't fiddle with cache settings until you know
> RAM is fine".

I guess that comment could use more clarification. The RAM that is
available will be cached but not all the memory in the system may be
setup when set_mtrr_ram_access is called. It is the job of the
memory/cpu init code to call it again as memory is added. Note the the
cache is being set based on TOM and TOM2.


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