[coreboot] [PATCH] cs5536/nand: Allow setting of NAND timing values in the dts.

Mart Raudsepp mart.raudsepp at artecdesign.ee
Mon Feb 9 16:15:49 CET 2009


cs5536/nand: Allow setting of NAND timing values in the dts.

The reset value for NAND timings is the slowest possible for Flash interface.
Implement optionally setting it to a different value inside the NAND device.
Set it to appropriate values for Artec Group DBE61 and DBE62.
This results in a roughly two times quicker read time as measured by hdparm
for these boards.

Signed-off-by: Mart Raudsepp <mart.raudsepp at artecdesign.ee>
---
 mainboard/artecgroup/dbe61/dts  |    5 ++++-
 mainboard/artecgroup/dbe62/dts  |    5 ++++-
 southbridge/amd/cs5536/cs5536.c |   18 ++++++++++++++++++
 southbridge/amd/cs5536/nand     |    4 ++++
 4 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts
index a6995ce..cb46292 100644
--- a/mainboard/artecgroup/dbe61/dts
+++ b/mainboard/artecgroup/dbe61/dts
@@ -109,8 +109,11 @@ end
 			/* USB Port Power Handling setting. */
 			pph = "0xf5";
 		};
-		pci at f,1 {
+		pci at f,1 { /* NAND Flash */
 			/config/("southbridge/amd/cs5536/nand");
+			/* Timings */
+			nandf_data = "0x01200120";
+			nandf_ctl = "0x00000120";
 		};
 	};
 };
diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts
index 8089e79..73dc5a7 100644
--- a/mainboard/artecgroup/dbe62/dts
+++ b/mainboard/artecgroup/dbe62/dts
@@ -63,8 +63,11 @@
 			/* USB Port Power Handling setting. */
 			pph = "0xf5";
 		};
-		pci at f,1 {
+		pci at f,1 { /* NAND Flash */
 			/config/("southbridge/amd/cs5536/nand");
+			/* Timings */
+			nandf_data = "0x01200120";
+			nandf_ctl = "0x00000120";
 		};
 	};
 };
diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c
index 5437937..ea90fd4 100644
--- a/southbridge/amd/cs5536/cs5536.c
+++ b/southbridge/amd/cs5536/cs5536.c
@@ -109,6 +109,24 @@ static void hide_vpci(u32 vpci_devid)
 static void nand_phase2(struct device *dev)
 {
 	if (dev->enabled) {
+		struct southbridge_amd_cs5536_nand_config *nand;
+		struct msr msr;
+
+		/* Set up timings */
+		nand = (struct southbridge_amd_cs5536_nand_config *)dev->device_configuration;
+		msr.hi = 0x0;
+
+		if (nand->nandf_data) {
+			msr.lo = nand->nandf_data;
+			wrmsr(MDD_NANDF_DATA, msr);
+			printk(BIOS_DEBUG, "NANDF_DATA set to 0x%08x\n", msr.lo);
+		}
+		if (nand->nandf_ctl) {
+			msr.lo = nand->nandf_ctl;
+			wrmsr(MDD_NANDF_CTL, msr);
+			printk(BIOS_DEBUG, "NANDF_CTL set to 0x%08x\n", msr.lo);
+		}
+
 		/* Tell VSA to use FLASH PCI header. Not IDE header. */
 		hide_vpci(0x800079C4);
 	}
diff --git a/southbridge/amd/cs5536/nand b/southbridge/amd/cs5536/nand
index 69f4fa4..62c28b0 100644
--- a/southbridge/amd/cs5536/nand
+++ b/southbridge/amd/cs5536/nand
@@ -20,4 +20,8 @@
 
 {
 	device_operations = "cs5536_nand";
+
+	/* NAND timings per data book and NAND chip on board. 0x0 leaves to reset value. */
+	nandf_data = "0x0";
+	nandf_ctl = "0x0";
 };
-- 
1.6.1.1





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