[coreboot] Coreboot patches for v2 with SeaBIOS

Myles Watson mylesgw at gmail.com
Wed Feb 11 17:38:44 CET 2009

On Tue, Jan 20, 2009 at 4:08 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
> Here's my latest patch. It contains generic parts, northbridge specific
> parts and board specific parts.
> Please let me know what you think.

Sorry it has taken so long, I have been working on implementing ACPI
for my board so that I could try it out.

Your patch works fine for me.  Seabios gets the tables, Linux finds
them from there.

I'm having trouble with my fadt (FACP) and DSDT (the only ones I
really have to do :) since coreboot has support for SRAT, RSDT, RSDP,
and APIC ).  I'm attaching the current patches that I'm using.  They
apply on top of the patch you sent.

- I can't figure out the correspondence between pnp devices in
/proc/ioports and coreboot.  The ACPI device is missing, and I'm not
sure how to add it.  That causes problems when it tries to read the
timer specified in fadt.c.  If I remove the timer reference Linux
complains but continues until it breaks based on interrupt routing.

- The disassembled dsdt from the board doesn't match the way coreboot
configures the board, so I was trying to add my own based on another

- I don't see the relationship between /proc/interrupts and how to
generate the _PRT in the dsdt

- I've looked for a tutorial or Mindshare book on ACPI tables, but
can't find a decent one.  Can anyone recommend one?  The spec's
examples don't have enough information for me.

- I just want the bare minimum for now.  If there's something I should
disable to make it simpler, I'm happy to do that.


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