[coreboot] Coreboot patches for v2 with SeaBIOS

Rudolf Marek r.marek at assembler.cz
Wed Feb 11 18:01:30 CET 2009


Hi,
http://www.coreboot.org/ACPI_in_coreboot


Did you checked link above?

> - I can't figure out the correspondence between pnp devices in
> /proc/ioports and coreboot.  The ACPI device is missing, and I'm not
> sure how to add it.  That causes problems when it tries to read the
> timer specified in fadt.c.  If I remove the timer reference Linux
> complains but continues until it breaks based on interrupt routing.

You dont need ACPI device...

> - The disassembled dsdt from the board doesn't match the way coreboot
> configures the board, so I was trying to add my own based on another
> board...
> 
> - I don't see the relationship between /proc/interrupts and how to
> generate the _PRT in the dsdt

You need to check the MPTable/PIRQ the _PRT is just another way how to express 
the tables. Check the link above.

> - I just want the bare minimum for now.  If there's something I should
> disable to make it simpler, I'm happy to do that.

Well, for Linux you can remove:


+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate ()
+				{
+				IO (Decode16,
+				0x0CF8,	// Address Range Minimum
+				0x0CF8,	// Address Range Maximum
+				0x01,	// Address Alignment
+				0x08,	// Address Length
+				)
+				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000,	// Address Space Granularity
+				0x0000,	// Address Range Minimum
+				0x0CF7,	// Address Range Maximum
+				0x0000,	// Address Translation Offset
+				0x0CF8,	// Address Length
+				,, , TypeStatic)
+				})
+				/* Methods bellow use SSDT to get actual MMIO regs
+				 * The IO ports are from 0xd00, optionally an VGA,
+				 * otherwise the info from MMIO is used.
+				 */
+				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+				Return (Local3)
+			}

As well the  Include ("amdk8_util.asl")



 From mptable:

165	// Onboard ck804 SATA 0
166	        smp_write_intsrc(mc, mp_INT, 
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, 
apicid_ck804, 0x17); // 23
167	
168	// Onboard ck804 SATA 1
169	        smp_write_intsrc(mc, mp_INT, 
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, 
apicid_ck804, 0x16); // 22
170	


The sbdn is static? Lets assume SBDN is 0 for now.

for SATA 0 the _PR looks like this:

  Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, //sata at 7.0 goes to IRQ 23

Similar for other devices. Hope it helps.

Rudolf






More information about the coreboot mailing list