[coreboot] [PATCH 2/2] AMD boards to use new Power Now infrastructure

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Thu Feb 19 04:25:57 CET 2009


On 14.02.2009 14:18, Rudolf Marek wrote:
> Hello,
>
> This patch is for AMD boards which can do the P state generation. This
> just
> removes the ugly binary DSDT patching and all other related stuff.
> Stick to
> infrastructure in previous patch.
>
> This was just compile tested. I think it should work. Please test.
>
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
>
> Rudolf

The following differences exist (shortened):
--- old
+++ ruik
-    Scope (_PR)
+    Scope (\_PR)
     {
-        Processor (CPU0, 0x00, 0x00000808, 0x06)
+        Processor (\_PR.CPU0, 0x00, 0x00000808, 0x06)
         {
             Name (_PCT, Package (0x02)
             {

And your code shows one processor, the original code shows four
processors (I have one single-core CPU).

It seems that your code also fixes the message "powernow-k8: ph2 null
fid transition 0xa", but I am not sure whether this is an artifact of my
testing setup.

I tested switching from maximum powersave to maximum performance in a
tight loop (0.1 seconds delay between state changes) and it survived 262
changes in each direction. After that, I stopped the test because it
seemed to work.

If you are sure that your code can handle multicore/multiprocessor
constellations and if you can explain that additional backslash before
_PR, the patch is

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Attached are acpidumps and bootlogs without and with your patch.

Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/

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