[coreboot] slow load times
mylesgw at gmail.com
Mon Feb 23 22:00:32 CET 2009
On Thu, Feb 19, 2009 at 9:02 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> -----Original Message-----
>> From: Kevin O'Connor [mailto:kevin at koconnor.net]
>> Sent: Thursday, February 19, 2009 6:36 AM
>> To: Myles Watson
>> Cc: coreboot at coreboot.org
>> Subject: Re: [coreboot] slow load times
>> On Wed, Feb 18, 2009 at 09:47:29PM -0700, Myles Watson wrote:
>> > > Finally, I suppose SeaBIOS could just scan all 256 buses. (Does
>> > > anyone know if a bus is guaranteed to have a device 0? If so, that
>> > > would speed the scan significantly.)
>> > The AMD Serengeti board doesn't. The 8111 has a base device number of
>> <grasp straw>
>> Any idea if "root buses" will always have a device 0?
>> (That is, if SeaBIOS did its normal bridge/cardbus detection, could it
>> find all the remaining root buses by just scanning for device 0s?)
> No. In this case, the 8111 is the first device on bus 0, bus 0x40, or
> whatever bus it's on. The Opteron provides the root bus, and it is always
> reachable, but besides reading from the Opteron's registers...
For the benefit of searchers, this patch is for SeaBIOS for multiple
root PCI buses.
Until there's a better solution, this one works for me. My SATA card
The patch makes pci_next jump to the next root when it would have been
done scanning if there are more roots defined. If you set them to 0,
there is no change in functionality.
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