[coreboot] Plugin support

Myles Watson mylesgw at gmail.com
Wed Feb 25 17:38:03 CET 2009


On Mon, Feb 23, 2009 at 11:10 AM, Myles Watson <mylesgw at gmail.com> wrote:
> On Mon, Feb 23, 2009 at 10:43 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> On Mon, Feb 23, 2009 at 10:22 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
>>> On 23.02.2009 18:04 Uhr, Myles Watson wrote:
>>>> I implemented the *_PLUGIN_SUPPORT config options for v3.  I thought
>>>> it was simple since I was just enabling the defines already in the
>>>> code.  In retrospect I may have implemented them backward.
>>>>
>>>> The space in the ROM consumed by PLUGIN_SUPPORT is very small if you
>>>> already have support for that bus.  If you don't have support for the
>>>> bus it could be significant.  I wanted to make it so that e.g.
>>>> HYPERTRANSPORT_PLUGIN_SUPPORT was the default if you had
>>>> HYPERTRANSPORT_SUPPORT.  I'd also like people to be able to select
>>>> CARDBUS_PLUGIN_SUPPORT or NO_CARDBUS_PLUGIN_SUPPORT.
>>>>
>>> How much code do all those "plugins" together consume, given you have a
>>> system with none of that buses in the dts?
>>
>> Coreboot ROM Image (QEMU) with no plugin support:
>>  normal/option_table (932 bytes @0x50);loadaddress 0x0 entry 0x0
>>  normal/initram/segment0 (440 bytes @0x450);loadaddress 0x0 entry 0x0x20
>>  normal/stage2/segment0 (194780 bytes, zeroes compressed to 1 bytes
>> @0x660);loadaddress 0x0xd130 entry 0x0x2000
>>  normal/stage2/segment1 (35188 bytes, lzma compressed to 18410 bytes
>> @0x6c0);loadaddress 0x0x2000 entry 0x0x2000
>>  normal/stage2/segment2 (6076 bytes, lzma compressed to 360 bytes
>> @0x4f00);loadaddress 0x0xb974 entry 0x0x2000
>>  bootblock (20480 bytes @0x3b000)
>> Total size = 41071B 40KB (0xa06f)
>>
>> Coreboot ROM Image with all plugins:
>>  normal/option_table (932 bytes @0x50);loadaddress 0x0 entry 0x0
>>  normal/initram/segment0 (440 bytes @0x450);loadaddress 0x0 entry 0x0x20
>>  normal/stage2/segment0 (194784 bytes, zeroes compressed to 1 bytes
>> @0x660);loadaddress 0x0xe1c0 entry 0x0x2000
>>  normal/stage2/segment1 (39340 bytes, lzma compressed to 20416 bytes
>> @0x6c0);loadaddress 0x0x2000 entry 0x0x2000
>>  normal/stage2/segment2 (6164 bytes, lzma compressed to 376 bytes
>> @0x56d0);loadaddress 0x0xc9ac entry 0x0x2000
>>  bootblock (20480 bytes @0x3b000)
>> Total size = 43093B 42KB (0xa855)
>>
>> It looks like about 2K.  In order for it to build I had to define a
>> few HT-specific things and put in  an empty mainboard.h, but it won't
>> be hard if we want to make it the default to always include all buses.
>
> Coreboot ROM Image with everything but HyperTransport:
>  normal/option_table (932 bytes @0x50);loadaddress 0x0 entry 0x0
>  normal/initram/segment0 (440 bytes @0x450);loadaddress 0x0 entry 0x0x20
>  normal/stage2/segment0 (194784 bytes, zeroes compressed to 1 bytes
> @0x660);loadaddress 0x0xda70 entry 0x0x2000
>  normal/stage2/segment1 (37468 bytes, lzma compressed to 19388 bytes
> @0x6c0);loadaddress 0x0x2000 entry 0x0x2000
>  normal/stage2/segment2 (6164 bytes, lzma compressed to 379 bytes
> @0x52d0);loadaddress 0x0xc25c entry 0x0x2000
>  bootblock (20480 bytes @0x3b000)
> Total size = 42068B 41KB (0xa454)
>
> Maybe this is a good middle ground.  I haven't seen a PCI->HT bridge yet :)

This patch removes all *_PLUGIN_SUPPORT options and replaces most
*_SUPPORT options with NO_*_SUPPORT options.  This means that you have
to specify that you want a smaller BIOS, otherwise you get full
functionality.

HyperTransport is the only exception for a couple of reasons.  HT
requires a mainboard.h file which not all mainboards have, and it's
less likely to be "plugged in" to a board that doesn't have some
onboard HT.

It also fixes a trivial typo in Kconfig (paylaod -> payload)

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Build tested on Serengeti and qemu.

Thanks,
Myles
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