[coreboot] Coreboot patches for v2 with SeaBIOS

Myles Watson mylesgw at gmail.com
Fri Feb 27 22:10:52 CET 2009


On Fri, Feb 27, 2009 at 1:10 PM, Marc Jones <marcj303 at gmail.com> wrote:
> On Fri, Feb 27, 2009 at 12:40 PM, Myles Watson <mylesgw at gmail.com> wrote:
>>
>>
>>> -----Original Message-----
>>> From: Marc Jones [mailto:marcj303 at gmail.com]
>>> Sent: Friday, February 27, 2009 10:51 AM
>>> To: Myles Watson
>>> Cc: Stefan Reinauer; Coreboot
>>> Subject: Re: [coreboot] Coreboot patches for v2 with SeaBIOS
>>>
>>> On Fri, Feb 27, 2009 at 10:42 AM, Myles Watson <mylesgw at gmail.com> wrote:
>>>
>>> > Does this work for you with 4G of RAM?  I don't have a Kontron board,
>>> > but I copied the implementation to the amdk8 northbridge code.  It
>>> > works for me when I have the RAM "boosted" and it works when I boot
>>> > with less than 4G, but if I boot with 4G it tries to put the high
>>> > tables in the PCI decode space since they overlap.
>>> >
>>> > Besides that the patch is working well for me, and I'd like to see it
>>> merged.
>>> >
>>> > If it works in the 4G case and I just didn't implement it right for K8:
>>> >
>>> > Acked-by: Myles Watson <mylesgw at gmail.com>
>>> >
>>>
>>> Do you have an off by 1 problem? That would cause the problem @ 4GB as
>>> you described.
>>
>> I'm confused ( again :) )
>>
>> I'm not sure where the off by one problem would be.
>>
>> I thought the problem was that when you have the top of RAM at 0x100000000
>> and then subtract some small number from it you end up at 0xffff0000, which
>> isn't where you should be accessing normal RAM, or reserving it for ACPI.
>
> I guess I didn't understand what you were saying. I assumed it was a
> problem with a size calculation at 4GB. If you have 4GB of memory it
> should hoist (boost) some portion of it. 512MB or 1GB typically. Is
> there a bug in the memory hoist code? Can you check what the tomk is
> with 4GB

Sorry that took a while.  Here are snippets of the output (full output attached)

//4 GB getting cleared:
Setting up local apic... apic_id: 0x00 done.
Clearing memory 2048K - 4194304K:
--------------------------------------------------------------- done
CPU #0 initialized
...
//This is from northbridge.c where I grabbed the space for the high tables:
0: mmio_basek=003e0000, basek=003e0000, limitk=00400000
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran
0x0c io <node 0 link 0>
PCI: 00:18.0 1b8 <- [0x00fd400000 - 0x00fd3fffff] size 0x00000000 gran
0x14 prefmem <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00fc000000 - 0x00fd1fffff] size 0x01200000 gran
0x14 mem <node 0 link 0>
PCI: 00:18.0 1da <- [0x0000004000 - 0x0000003fff] size 0x00000000 gran
0x0c io <node 0 link 2>
PCI: 00:18.0 1aa <- [0x00fd400000 - 0x00fd3fffff] size 0x00000000 gran
0x14 prefmem <node 0 link 2>
PCI: 00:18.0 1a2 <- [0x00fd200000 - 0x00fd3fffff] size 0x00200000 gran
0x14 mem <node 0 link 2>
PCI: 00:01.0 10 <- [0x0000002c00 - 0x0000002c7f] size 0x00000080 gran 0x07 io
...
//This is the code trying to write the high tables into the ROM :)
Devices initialized
High Tables Base is ffff0000.
Writing IRQ routing tables to 0xffff0000...done.
ACPI: Writing ACPI tables at ffff0400.
ACPI:    * FACS ffff04c0
ACPI:    * DSDT ffff0500
ACPI:    * DSDT @ ffff0500 Length b7000f6d
ACPI:    * FACP (FADT) @ ffff0ef0
pm_base: 0x2000
ACPI: could not add ACPI table to RSDT. failed.
ACPI:    * HPET @ ffff0ff0
ACPI: could not add ACPI table to RSDT. failed.
ACPI:    * APIC/MADT @ ffff1030
ACPI: could not add ACPI table to RSDT. failed.
ACPI:    * SRAT @ c0aa8290
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000,
sizek=00000280
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300,
sizek=003dfd00
ACPI: could not add ACPI table to RSDT. failed.
ACPI:    * SLIT @ c0aa8320
ACPI: could not add ACPI table to RSDT. failed.
ACPI:    * SSDT @ c0aa8350
processor_brand=AMD Opteron(tm) Processor 248
Pstates Algorithm ...

Thanks,
Myles
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