[coreboot] [PATCH 1/2] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
mart.raudsepp at artecdesign.ee
Fri Jan 9 18:13:37 CET 2009
Ühel kenal päeval, R, 2009-01-09 kell 15:29, kirjutas Peter Stuge:
> Mart Raudsepp wrote:
> > cs5536: Add a NAND device and do the IDE PCI header disabling on time.
> > This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better.
> > It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late
> > before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2
> > before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it
> > enabled in VSA2.
> > It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch,
> > but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the
> > VSA2 bug suggests something further will still need fixing. There are also more potential opportunities
> > to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup
> > actually works right in the current form.
> > Also corrected the documentation of ide_init() to match current reality.
> > Signed-off-by: Mart Raudsepp <mart.raudsepp at artecdesign.ee>
> Acked-by: Peter Stuge <peter at stuge.se>
Here's a new patch for the same thing.
It adds a dev->enabled check to nand_phase2 hide_vpci call compared to
the previous, so that it won't switch to NAND if some mainboard dts
decides to add a nand device that is spedified to be "disabled;".
More information about the coreboot