[coreboot] r1115 - in coreboot-v3/mainboard/artecgroup: dbe61 dbe62

[svn at coreboot.org]

Author: mraudsepp
Date: 2009-01-14 12:22:32 +0100 (Wed, 14 Jan 2009)
New Revision: 1115

Modified:
   coreboot-v3/mainboard/artecgroup/dbe61/initram.c
   coreboot-v3/mainboard/artecgroup/dbe62/initram.c
Log:
Remove redundant unused tRCD entries from dbe61/dbe62 SPD value list.

SPD_MIN_RAS_TO_CAS_DELAY is already set earlier in the list, so the alternative
constant tRCD in the end has no effect in the memory algorithm - remove them.

Signed-off-by: Mart Raudsepp <mart.raudsepp at artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/initram.c	2009-01-09 18:12:08 UTC (rev 1114)
+++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c	2009-01-14 11:22:32 UTC (rev 1115)
@@ -66,7 +66,6 @@
 	{SPD_REFRESH, 0x82},
 	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
 	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
-	{SPD_tRCD, 15},
 };
 
 /* Fake SPD for DBE61A - 128MB */
@@ -89,7 +88,6 @@
 	{SPD_REFRESH, 0x82},
 	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
 	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
-	{SPD_tRCD, 15},
 };
 
 /**

Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2009-01-09 18:12:08 UTC (rev 1114)
+++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2009-01-14 11:22:32 UTC (rev 1115)
@@ -70,7 +70,6 @@
 	{SPD_REFRESH, 0x82},
 	{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
 	{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
-	{SPD_tRCD, 15},
 };
 
 /**