[coreboot] #120: flashrom failure to read

[coreboot]

#120: flashrom failure to read
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   Reporter:  toc@…               |          Owner:  stuge   
       Type:  defect              |         Status:  assigned
   Priority:  major               |      Milestone:          
  Component:  flashrom            |        Version:          
   Keywords:  ich9                |   Dependencies:          
Patchstatus:  patch needs review  |  
----------------------------------+-----------------------------------------

Comment(by toc@…):

 Replying to [comment:3 stuge]:
 > Ok, the patch worked, but there is some other problem. I just committed
 a small change that adds useful debugging in r3862. Please update and
 resend output from running with -V.

 {{{
 Calibrating delay loop... 663M loops per second, 100 myus = 200 us. OK.
 No coreboot table found.
 Found chipset "Intel ICH9R", enabling flash write...
 BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
 tried to set 0xdc to 0x3 on Intel ICH9R failed (WARNING ONLY)

 Root Complex Register Block address = 0xfeda8000
 GCS = 0x410460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1
 (SPI)
 Top Swap : not enabled
 SPIBAR = 0xfeda8000 + 0x3800
 0x00: 0x1fff (HSFS)
 FLOCKDN 0, FDV 0, FDOPSS 0, SCIP 1, BERASE 3, AEL 1, FCERR 1, FDONE 1
 0x50: 0x0000ffff (FRAP)
 BMWAG 0, BMRAG 0, BRWA 255, BRRA 255
 0x54: 0x00001fff (FREG0)
 0x58: 0x00001fff (FREG1)
 0x5C: 0x00001fff (FREG2)
 0x60: 0x00001fff (FREG3)
 0x64: 0x00001fff (FREG4)
 0x74: 0x00000000 (PR0)
 0x78: 0x00000000 (PR1)
 0x7C: 0x00000000 (PR2)
 0x80: 0x00000000 (PR3)
 0x84: 0x00000000 (PR4)
 0xB0: 0x00000000 (FDOC)
 Programming OPCODES...
 program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f01ab
 done
 SPI Read Configuration: prefetching disabled, caching enabled, FAILED!
 <<<snip>>>>
 probe_spi_rdid_generic: id1 0xc2, id2 0x2014
 Chip status register is 00
 Chip status register: Status Register Write Disable (SRWD) is not set
 Chip status register: Bit 6 is not set
 Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
 Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
 Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
 Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
 Chip status register: Write Enable Latch (WEL) is not set
 Chip status register: Write In Progress (WIP/BUSY) is not set
 Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000.
 <<<<snip>>>>>
 Reading flash... ich_spi_read_page: offset=0, number=256, buf=0xb7cdd008
 Opcode 3 not found.
 run OPCODE 0x03 failed
 Error readingdone.
 }}}}

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Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/120#comment:5>
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