From wallbraker at gmail.com  Wed Jul  1 01:11:06 2009
From: wallbraker at gmail.com (Jakob Bornecrantz)
Date: Wed, 1 Jul 2009 01:11:06 +0200
Subject: [coreboot] [PATCH] Changes for DLP 1232H external programer to
	Flashrom
In-Reply-To: <4A48B146.2020700@gmx.net>
References: <427ca1a20906270443j5fea2019j5a32c781758a41f5@mail.gmail.com>
	<4A48B146.2020700@gmx.net>
Message-ID: <427ca1a20906301611r5bba8bceu714909d665d675a9@mail.gmail.com>

On Mon, Jun 29, 2009 at 2:19 PM, Carl-Daniel
Hailfinger<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 27.06.2009 13:43, Jakob Bornecrantz wrote:
>> These are the changes I had to do the flashrom to get my in circuit
>> programer working. Not much as you can see.
>
> Alternative patch which allows runtime selection of FT2232H/FT4232H and
> interface A/B.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

[SNIP]

Tested it works well.

Acked-by: Jakob Bornecrantz <wallbraker at gmail.com>
Tested-by: Jakob Bornecrantz <wallbraker at gmail.com>

Cheers Jakob.



From kevin at koconnor.net  Wed Jul  1 01:40:08 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 30 Jun 2009 19:40:08 -0400
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906231327u7d36e1f7t840fc5cdde67dfba@mail.gmail.com>
	<23a460760906231418l596e2a3cm3d61953c2b12db6b@mail.gmail.com>
	<8B53F3255BEE44A896F998A7405BA0E6@chimp>
	<23a460760906240534s2b6b20f3w58b2bcdc7bdd1019@mail.gmail.com>
	<20090626182130.GA30895@morn.localdomain>
	<23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
Message-ID: <20090630234008.GA22496@morn.localdomain>

On Tue, Jun 30, 2009 at 09:10:46AM +0200, Thomas JOURDAN wrote:
> My mistake ! Seabios run the VGA bios of the matrox graphics card
> flawless. When I tried seabios, the coreboot Options.lb file of my
> mainboard wasn't correct. I set :
> default CONFIG_VGA_ROM_RUN=0
> default CONFIG_PCI_ROM_RUN=0
> but also (and that was my mistake)
> default CONFIG_CONSOLE_VGA=0

That's odd - I didn't think these coreboot options had any impact to
SeaBIOS either.  As a guess, coreboot is initializing some hardware
only when the CONFIG_CONSOLE_VGA option is set.

-Kevin



From c-d.hailfinger.devel.2006 at gmx.net  Wed Jul  1 02:03:32 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 01 Jul 2009 02:03:32 +0200
Subject: [coreboot] [PATCH] Changes for DLP 1232H external programer to
 Flashrom
In-Reply-To: <427ca1a20906301611r5bba8bceu714909d665d675a9@mail.gmail.com>
References: <427ca1a20906270443j5fea2019j5a32c781758a41f5@mail.gmail.com>	<4A48B146.2020700@gmx.net>
	<427ca1a20906301611r5bba8bceu714909d665d675a9@mail.gmail.com>
Message-ID: <4A4AA7D4.7050709@gmx.net>

On 01.07.2009 01:11, Jakob Bornecrantz wrote:
> On Mon, Jun 29, 2009 at 2:19 PM, Carl-Daniel
> Hailfinger<c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> allows runtime selection of FT2232H/FT4232H and
>> interface A/B.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> Acked-by: Jakob Bornecrantz <wallbraker at gmail.com>
> Tested-by: Jakob Bornecrantz <wallbraker at gmail.com>
>   

Thanks, committed in r638.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Wed Jul  1 02:28:53 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 01 Jul 2009 02:28:53 +0200
Subject: [coreboot] [ANNOUNCE] Upcoming Flashrom Mailing List and IRC
	splitoff
In-Reply-To: <4A4204D9.6040302@gmx.net>
References: <4A4204D9.6040302@gmx.net>
Message-ID: <4A4AADC5.8000904@gmx.net>

Dear list participants,

flashrom has grown up to a point where it is large and vital enough to
live in its own home. To accommodate flashrom's new independence, the
#coreboot IRC channel on irc.freenode.net and the coreboot at coreboot.org
mailing list will be split in two.

New mailing list structure:
flashrom at flashrom.org is where flashrom development and usage will be
discussed.
coreboot at coreboot.org will carry all traffic not related to flashrom.
coreboot at coreboot.org list members will be subscribed automatically to
flashrom at flashrom.org over the next few days. If you are only interested
in either coreboot or flashrom, feel free to unsubscribe from either
list once the split is done.

New IRC structure:
#flashrom on irc.freenode.net is the new channel for flashrom
development and usage discussions. #flashrom is already active, please
join us.
#coreboot on irc.freenode.net will remain the place to discuss all
coreboot and non-flashrom matters.

You will get another mail once the new mailing list is active.


Thanks go to Stefan Reinauer and his company coresystems GmbH for
providing all the infrastructure for flashrom and coreboot.

Regards,
Carl-Daniel



From mylesgw at gmail.com  Wed Jul  1 04:09:05 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 30 Jun 2009 20:09:05 -0600
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <20090630234008.GA22496@morn.localdomain>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906231327u7d36e1f7t840fc5cdde67dfba@mail.gmail.com>
	<23a460760906231418l596e2a3cm3d61953c2b12db6b@mail.gmail.com>
	<8B53F3255BEE44A896F998A7405BA0E6@chimp>
	<23a460760906240534s2b6b20f3w58b2bcdc7bdd1019@mail.gmail.com>
	<20090626182130.GA30895@morn.localdomain>
	<23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
	<20090630234008.GA22496@morn.localdomain>
Message-ID: <03E0EFDE09E54A48882815F04D43D762@chimp>


> On Tue, Jun 30, 2009 at 09:10:46AM +0200, Thomas JOURDAN wrote:
> > My mistake ! Seabios run the VGA bios of the matrox graphics card
> > flawless. When I tried seabios, the coreboot Options.lb file of my
> > mainboard wasn't correct. I set :
> > default CONFIG_VGA_ROM_RUN=0
> > default CONFIG_PCI_ROM_RUN=0
> > but also (and that was my mistake)
> > default CONFIG_CONSOLE_VGA=0
> 
> That's odd - I didn't think these coreboot options had any impact to
> SeaBIOS either.  As a guess, coreboot is initializing some hardware
> only when the CONFIG_CONSOLE_VGA option is set.

Yes.  If you don't have CONSOLE_VGA set then the PCI bridge bits don't get
set to allow the legacy I/O and memory ranges to be mapped.

Thanks,
Myles




From kevin at koconnor.net  Wed Jul  1 04:40:44 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 30 Jun 2009 22:40:44 -0400
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <03E0EFDE09E54A48882815F04D43D762@chimp>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906231327u7d36e1f7t840fc5cdde67dfba@mail.gmail.com>
	<23a460760906231418l596e2a3cm3d61953c2b12db6b@mail.gmail.com>
	<8B53F3255BEE44A896F998A7405BA0E6@chimp>
	<23a460760906240534s2b6b20f3w58b2bcdc7bdd1019@mail.gmail.com>
	<20090626182130.GA30895@morn.localdomain>
	<23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
	<20090630234008.GA22496@morn.localdomain>
	<03E0EFDE09E54A48882815F04D43D762@chimp>
Message-ID: <20090701024044.GA25070@morn.localdomain>

On Tue, Jun 30, 2009 at 08:09:05PM -0600, Myles Watson wrote:
> > That's odd - I didn't think these coreboot options had any impact to
> > SeaBIOS either.  As a guess, coreboot is initializing some hardware
> > only when the CONFIG_CONSOLE_VGA option is set.
> 
> Yes.  If you don't have CONSOLE_VGA set then the PCI bridge bits don't get
> set to allow the legacy I/O and memory ranges to be mapped.

That's unfortunate - setting CONSOLE_VGA also causes coreboot to try
and write to the vga screen.

I would think coreboot should always configure the legacy PCI bridge
bits and CONSOLE_VGA should just control whether or not coreboot tries
to write to the screen.  (Or, if there is a reason to not configure
the pci ranges, then make it a separate config item.)

-Kevin



From rick_077 at yahoo.com  Wed Jul  1 08:58:16 2009
From: rick_077 at yahoo.com (Rick Ant)
Date: Tue, 30 Jun 2009 23:58:16 -0700 (PDT)
Subject: [coreboot] Boot from IDE..
Message-ID: <729484.19824.qm@web110812.mail.gq1.yahoo.com>

Guys,

How can I put the Linux kernel in the Compact Flash on IDE?
Coreboot is in BIOS chip then calling the Linux Compact Flash on IDE,
I see it on FILO but I still don't understand, since the tutorial is for Qemu only..

Any help/ info will be so usefull for me

Thanks



      
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From svn at coreboot.org  Wed Jul  1 09:01:32 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 09:01:32 +0200
Subject: [coreboot] [v2] r4385 - in trunk/coreboot-v2/src: cpu/amd
	cpu/amd/socket_AM2r2 northbridge/amd/amdfam10
	northbridge/amd/amdmct/mct northbridge/amd/amdmct/wrappers
Message-ID: <mailman.3502.1355071588.16123.coreboot@coreboot.org>

Author: zbao
Date: 2009-07-01 09:01:32 +0200 (Wed, 01 Jul 2009)
New Revision: 4385

Added:
   trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/
   trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h
   trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c
Modified:
   trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c
   trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c
   trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
Log:
Add AMD family 10 AM2r2 support.

Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is.

This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE.
It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c


Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb	2009-07-01 07:01:32 UTC (rev 4385)
@@ -0,0 +1,54 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+uses CONFIG_PCI_IO_CFG_EXT
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_HT3_SUPPORT
+uses CONFIG_EXT_RT_TBL_SUPPORT
+uses CONFIG_EXT_CONF_SUPPORT
+uses CONFIG_DIMM_SUPPORT
+uses CONFIG_CPU_SOCKET_TYPE
+uses CONFIG_CBB
+uses CONFIG_CDB
+uses CONFIG_PCI_BUS_SEGN_BITS
+uses CONFIG_CAR_FAM10
+
+config chip.h
+
+default CONFIG_PCI_IO_CFG_EXT=1
+
+default CONFIG_HT3_SUPPORT=1
+default CONFIG_EXT_RT_TBL_SUPPORT=0
+default CONFIG_EXT_CONF_SUPPORT=0
+default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
+default CONFIG_CPU_SOCKET_TYPE=0x11
+
+default CONFIG_CAR_FAM10=1
+
+if CONFIG_EXT_RT_TBL_SUPPORT
+	default CONFIG_CBB=0xff
+	default CONFIG_CDB=0
+end
+
+#default CONFIG_MMCONF_SUPPORT=1
+#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
+
+object socket_AM2r2.o
+
+dir /cpu/amd/model_10xxx

Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h	2009-07-01 07:01:32 UTC (rev 4385)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_amd_socket_AM2r2_ops;
+
+struct cpu_amd_socket_AM2r2_config {
+};

Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c	2009-07-01 07:01:32 UTC (rev 4385)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_amd_socket_AM2r2_ops = {
+	CHIP_NAME("socket AM2r2")
+};

Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c	2009-06-30 17:13:58 UTC (rev 4384)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c	2009-07-01 07:01:32 UTC (rev 4385)
@@ -63,10 +63,10 @@
 #include "../amdmct/mct/mctndi_d.c"
 #include "../amdmct/mct/mctchi_d.c"
 
-#if SYSTEM_TYPE == SERVER
+#if CONFIG_CPU_SOCKET_TYPE == 0x10
 //L1
 #include "../amdmct/mct/mctardk3.c"
-#elif SYSTEM_TYPE == DESKTOP
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11
 //AM2
 #include "../amdmct/mct/mctardk4.c"
 //#elif SYSTEM_TYPE == MOBILE

Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c	2009-06-30 17:13:58 UTC (rev 4384)
+++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c	2009-07-01 07:01:32 UTC (rev 4385)
@@ -25,7 +25,7 @@
 
 void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
 			 struct DCTStatStruc *pDCTstat, u32 dct)
-
+{
 	print_tx("dct: ", dct);
 	print_tx("Speed: ", pDCTstat->Speed);
 
@@ -66,42 +66,43 @@
  */
 
 static const u8 Table_ATC_ODC_D_Bx[] = {
-	1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0
-	4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0
-	5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0
-	0FFh
+	1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0,
+	4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0,
+	5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0,
+	0xFF
+};
 
 static const u8 Table_ATC_ODC_D_Ax[] = {
-	1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0
-	2,   32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0
-	3,   32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0
-	4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0
-	5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0
+	1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0,
+	2,   32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0,
+	3,   32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0,
+	4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0,
+	5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0,
 	0xFF
 };
 
 
 static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
 				u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
-				u32 *CMDmode);
+				u32 *CMDmode)
 {
 	u8 *p;
 
@@ -168,5 +169,5 @@
 		}
 		p+=10;
 	} while (0xFF == *p);
-
+	}
 }

Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c	2009-06-30 17:13:58 UTC (rev 4384)
+++ trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c	2009-07-01 07:01:32 UTC (rev 4385)
@@ -25,9 +25,9 @@
 
 	switch (index) {
 	case NV_PACK_TYPE:
-#if SYSTEM_TYPE == SERVER
+#if CONFIG_CPU_SOCKET_TYPE == 0x10	/* Socket F */
 		val = 0;
-#elif SYSTEM_TYPE == DESKTOP
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11   /* AM2r2 */
 		val = 1;
 //#elif SYSTEM_TYPE == MOBILE
 //		val = 2;




From Zheng.Bao at amd.com  Wed Jul  1 09:06:04 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Wed, 1 Jul 2009 15:06:04 +0800
Subject: [coreboot] [PATCH]:AMD family 10 AM2r2 support
In-Reply-To: <534e5dc20906300822w71c11311ubc7491a1bbd397d3@mail.gmail.com>
References: <DD1CC71B621B004FA76856E5129D6B1702D2AD89@sbjgexmb1.amd.com>
	<534e5dc20906300822w71c11311ubc7491a1bbd397d3@mail.gmail.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B1702D2B108@sbjgexmb1.amd.com>

"CONFIG_" is added.

Committed, r4385.

-----Original Message-----
From: Marc Jones [mailto:marcj303 at gmail.com] 
Sent: Tuesday, June 30, 2009 11:23 PM
To: Bao, Zheng
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH]:AMD family 10 AM2r2 support

On Mon, Jun 29, 2009 at 11:46 PM, Bao, Zheng<Zheng.Bao at amd.com> wrote:
> Add AMD family 10 AM2r2 support.
> Coreboot used to take SYSTEM_TYPE as a label to tell what the socket is.
> The patch replaces (some of, not all) SYSTEM_TYPE with ?CPU_SOCKET_TYPE.
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>

T

> +default CPU_SOCKET_TYPE=0x11

Please add an equate for the socket names.

Acked-by: Marc Jones <marcj3030 at gmail.com>

-- 
http://marcjonesconsulting.com





From info at coresystems.de  Wed Jul  1 09:23:47 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 09:23:47 +0200
Subject: [coreboot] build service results for r4385
Message-ID: <E1MLuAV-00022e-R0@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "zbao" checked in revision 4385 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add AMD family 10 AM2r2 support.

Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is.

This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE.
It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c


Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>



Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in zbao's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From jon.harrison at selexgalileo.com  Wed Jul  1 12:42:44 2009
From: jon.harrison at selexgalileo.com (Harrison, Jon (SELEX GALILEO, UK))
Date: Wed, 1 Jul 2009 11:42:44 +0100
Subject: [coreboot] C3/CN400 Support - coreboot_tables
In-Reply-To: <13426df10906300844u17000333k4159b3f9d0ce011@mail.gmail.com>
References: <mailman.62.1246371138.8743.coreboot@coreboot.org>
	<8E520A5E7FB8D647BFDA039F6031C1C6057276DD@desmdswms201.des.grplnk.net>
	<13426df10906300844u17000333k4159b3f9d0ce011@mail.gmail.com>
Message-ID: <8E520A5E7FB8D647BFDA039F6031C1C605727AE9@desmdswms201.des.grplnk.net>

Ron,

Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.

Patch should work against r4381 (or later ?)

This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)

The coreboot_table issue seems to have been automagically resolved by
the latest core files.

It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.

Signed-off-by: Jon Harrison <bothlyn at blueyonder.co.uk>




-----Original Message-----
From: ron minnich [mailto:rminnich at gmail.com] 
Sent: 30 June 2009 16:44
To: Harrison, Jon (SELEX GALILEO, UK)
Subject: Re: [coreboot] C3/CN400 Support - coreboot_tables

                    *** WARNING ***

 This message has originated outside your organisation,
  either from an external partner or the Global Internet. 
      Keep this in mind if you answer this message.


is your port visible anywhere?

[snip]

ron

SELEX Sensors and Airborne Systems Limited
Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL
A company registered in England & Wales.  Company no. 02426132
********************************************************************
This email and any attachments are confidential to the intended
recipient and may also be privileged. If you are not the intended
recipient please delete it from your system and notify the sender.
You should not copy it or use it for any purpose nor disclose or
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********************************************************************
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From svn at coreboot.org  Wed Jul  1 12:57:25 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 12:57:25 +0200
Subject: [coreboot] [v2] r4386 - in trunk/coreboot-v2: src/config
	src/mainboard/via src/mainboard/via/epia-n
	src/northbridge/via src/northbridge/via/cn400 targets/via
	targets/via/epia-n
Message-ID: <mailman.3503.1355071588.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-07-01 12:57:25 +0200 (Wed, 01 Jul 2009)
New Revision: 4386

Added:
   trunk/coreboot-v2/src/mainboard/via/epia-n/
   trunk/coreboot-v2/src/mainboard/via/epia-n/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-n/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/chip.h
   trunk/coreboot-v2/src/mainboard/via/epia-n/cmos.layout
   trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.asl
   trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/fadt.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/failover.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/irq_tables.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/mainboard.c
   trunk/coreboot-v2/src/northbridge/via/cn400/
   trunk/coreboot-v2/src/northbridge/via/cn400/Config.lb
   trunk/coreboot-v2/src/northbridge/via/cn400/agp.c
   trunk/coreboot-v2/src/northbridge/via/cn400/chip.h
   trunk/coreboot-v2/src/northbridge/via/cn400/cn400.h
   trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.h
   trunk/coreboot-v2/src/northbridge/via/cn400/raminit.c
   trunk/coreboot-v2/src/northbridge/via/cn400/raminit.h
   trunk/coreboot-v2/src/northbridge/via/cn400/vga.c
   trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/cn400/vgachip.h
   trunk/coreboot-v2/targets/via/epia-n/
   trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb
   trunk/coreboot-v2/targets/via/epia-n/Config.lb
Modified:
   trunk/coreboot-v2/src/config/Options.lb
Log:

Ron,

Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.

Patch should work against r4381 (or later ?)

This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)

The coreboot_table issue seems to have been automagically resolved by
the latest core files.

It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.

Signed-off-by: Jon Harrison <bothlyn at blueyonder.co.uk>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2009-07-01 07:01:32 UTC (rev 4385)
+++ trunk/coreboot-v2/src/config/Options.lb	2009-07-01 10:57:25 UTC (rev 4386)
@@ -568,6 +568,11 @@
 	export always
 	comment "Maximum number of PCI buses to search for devices"
 end
+define CONFIG_EPIA_VT8237R_INIT
+	default none
+	export used
+	comment "Enable EPIA Specific Initialisation of VT8237R SB" 
+end
 ###############################################
 # SMP options
 ###############################################

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/Config.lb	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,197 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+
+include /config/nofailovercalculation.lb
+
+##
+## Set all of the defaults for an x86 architecture
+##
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+
+#object vgabios.o
+
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+
+if CONFIG_HAVE_ACPI_TABLES
+#acpi_create_fadt is located in VT8237R code
+	object dsdt.o
+	object acpi_tables.o
+end
+makerule ./failover.E
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of coreboot startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/via/cn400			# Northbridge
+
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/via/model_c3			# VIA C3
+      device apic 0 on end			# APIC
+    end
+  end
+
+  device pci_domain 0 on			# PCI domain
+    device pci 0.0 on end			# AGP Bridge
+    device pci 0.1 on end			# Error Reporting
+    device pci 0.2 on end			# Host Bus Control
+    device pci 0.3 on end			# Memory Controller
+    device pci 0.4 on end			# Power Management
+    device pci 0.7 on end			# V-Link Controller
+    device pci 1.0 on end			# PCI Bridge
+    chip southbridge/via/vt8237r		# Southbridge
+      # Enable both IDE channels.
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      # Both cables are 40pin.
+      register "ide0_80pin_cable" = "0"
+      register "ide1_80pin_cable" = "0"
+      device pci f.0 on end			# IDE/SATA
+	  device pci f.1 on end			# IDE
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci 10.0 on end			# OHCI
+      device pci 10.1 on end			# OHCI
+      device pci 10.2 on end			# OHCI
+      device pci 10.3 on end			# OHCI
+      device pci 10.4 on end			# EHCI
+      device pci 11.0 on			# Southbridge LPC
+        chip superio/winbond/w83697hf		# Super I/O
+          device pnp 2e.0 off			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 off			# Parallel Port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.2 on			# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 off			# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 off			# IR Port
+            io 0x60 = 0x000
+          end
+          device pnp 2e.7 off			# GPIO 1
+            io 0x60 = 0x201			# 0x201
+          end
+          device pnp 2e.8 off			# GPIO 5
+            io 0x60 = 0x330			# 0x330
+          end
+          device pnp 2e.9 off			# GPIO 2, 3,and 4
+            io 0x60 = 0x000			#
+          end
+          device pnp 2e.a off			# ACPI
+            io 0x60 = 0x000			#
+          end
+          device pnp 2e.b on			# HWM
+            io 0x60 = 0x290
+			irq 0x70 = 0
+          end
+        end
+      end
+      device pci 11.5 off end			# AC'97 audio
+      # device pci 11.6 off end			# AC'97 Modem
+      device pci 12.0 on end			# Ethernet
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,127 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CBFS
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_ARCH
+uses CONFIG_LB_MEM_TOPK
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_CROSS_COMPILE
+uses CC
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_MAX_PCI_BUSES
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_VIDEO_MB
+uses CONFIG_IOAPIC
+uses CONFIG_COMPRESS
+uses CONFIG_EPIA_VT8237R_INIT
+
+default CONFIG_EPIA_VT8237R_INIT = 1
+#default CONFIG_LB_MEM_TOPK = 4 * 1024
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_COMPRESS = 1
+default CONFIG_IOAPIC = 0
+default CONFIG_VIDEO_MB = 64
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default CONFIG_PCI_ROM_RUN = 0
+default CONFIG_CONSOLE_VGA = 0
+default CONFIG_HAVE_FAILOVER_BOOT = 0
+default CONFIG_USE_FAILOVER_IMAGE = 0
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 9
+default CONFIG_HAVE_ACPI_TABLES = 0
+default CONFIG_HAVE_OPTION_TABLE = 1
+#default CONFIG_ROM_IMAGE_SIZE = 67 * 1024
+#default CONFIG_PAYLOAD_SIZE = 125 * 1024
+default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_PAYLOAD_SIZE = 256 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE + CONFIG_PAYLOAD_SIZE
+default CONFIG_USE_FALLBACK_IMAGE = 1
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
+default CONFIG_ROM_PAYLOAD = 1
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
+default CONFIG_HOSTCC = "gcc"
+#default CONFIG_MAINBOARD = "EPIA-N"
+
+##
+## Set this to the max PCI bus number you would ever use for PCI config I/O.
+## Setting this number very high will make pci_locate_device() take a long
+## time when it can't find a device.
+##
+default CONFIG_MAX_PCI_BUSES = 3
+
+
+#
+# CBFS
+#
+#
+default CONFIG_CBFS=0
+end

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/acpi_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/acpi_tables.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,94 @@
+/*
+ * coreboot ACPI Table support
+ * written by Stefan Reinauer <stepan at openbios.org>
+ * ACPI FADT, FACS, and DSDT table support added by 
+ * Nick Barker <nick.barker9 at btinternet.com>, and those portions
+ * (C) Copyright 2004 Nick Barker
+ * (C) Copyright 2005 Stefan Reinauer
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Nothing to do */
+	return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Nothing to do */
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	
+	/* Align ACPI tables to 16byte */
+	start   = ( start + 0x0f ) & -0x10;
+	current = start;
+	
+	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+	
+	acpi_write_rsdp(rsdp, rsdt);
+	acpi_write_rsdt(rsdt);
+	
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk_debug("ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *)current;
+	current += ((acpi_header_t *)AmlCode)->length;
+	memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
+	dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
+	dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
+	printk_debug("ACPI:     * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+	printk_debug("ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt,facs,dsdt);
+	acpi_add_table(rsdt,fadt);
+
+	printk_info("ACPI: done.\n");
+	return current;
+}
+

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "northbridge/via/cn400/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+
+/*
+ * NOOB ::			
+ * d0f0 - Device 0 Function 0 etc. 
+ */
+static const struct mem_controller ctrl = {
+	.d0f0 = 0x0000,
+	.d0f2 = 0x2000,
+	.d0f3 = 0x3000,
+	.d0f4 = 0x4000,
+	.d0f7 = 0x7000,
+	.d1f0 = 0x8000,
+	.channel0 = { 0x50 },
+};
+
+
+static void memreset_setup(void)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/via/cn400/raminit.c"
+
+static void enable_mainboard_devices(void)
+{
+	device_t dev;
+	u8 reg;
+ 
+ 	dev = pci_locate_device(PCI_ID(0x1106, 0x7259), 0);
+	if (dev == PCI_DEV_INVALID)
+		die("Northbridge V-Link not found!!!\n");
+	pci_write_config8(dev, 0x4F, 0x01);
+	pci_write_config8(dev, 0x48, 0x13);
+	
+	
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+	if (dev == PCI_DEV_INVALID)
+		die("Southbridge not found!!!\n");
+
+	/* bit=0 means enable function (per VT8237R datasheet)
+	 *   7 17.6 MC97
+	 *   6 17.5 AC97
+	 *   5 16.1 USB 2
+	 *   4 16.0 USB 1
+	 *   3 15.0 SATA and PATA
+	 *   2 16.2 USB 3
+	 *   1 16.4 USB EHCI
+	 */
+	pci_write_config8(dev, 0x50, 0x80);
+
+	/*bit=0 means enable internal function (per VT8237R datasheet)
+	 *   7 USB Device Mode
+	 *bit=1 means enable internal function (per VT8237R datasheet)
+	 *   6 Reserved
+	 *   5 LAN Controller Clock Gating
+	 *   4 LAN Controller
+	 *   3 Internal RTC
+	 *   2 Internal PS2 Mouse
+	 *   1 Internal KBC Configuration
+	 *   0 Internal Keyboard Controller
+	 */
+	pci_write_config8(dev, 0x51, 0x1d);
+}
+
+static void enable_shadow_ram(void) 
+{
+	unsigned char shadowreg;
+	
+	shadowreg = pci_read_config8(ctrl.d0f3, 0x82);
+	/* 0xf0000-0xfffff Read/Write*/
+	shadowreg |= 0x30;
+	pci_write_config8(ctrl.d0f3, 0x82, shadowreg);
+}
+
+static void main(unsigned long bist)
+{
+	unsigned long x;
+	device_t dev;
+
+	/* Enable multifunction for northbridge. */
+	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
+
+	w83697hf_set_clksel_48(SERIAL_DEV);
+
+	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	uart_init();
+	console_init();
+
+	print_spew("In auto.c:main()\r\n");
+
+	enable_smbus();
+	smbus_fixup(&ctrl);
+
+	/* Halt if there was a built-in self test failure. */
+	report_bist_failure(bist);
+
+	print_debug("Enabling mainboard devices\r\n");
+	enable_mainboard_devices();
+
+	print_debug("Enable F-ROM Shadow RAM\r\n");
+	enable_shadow_ram();
+	
+	/* setup cpu */
+	print_debug("Setup CPU Interface\r\n");
+	c3_cpu_setup(ctrl.d0f2);	
+
+
+	ddr_ram_setup();
+
+	if (bist == 0) {
+		print_debug("doing early_mtrr\r\n");
+		early_mtrr_init();
+	}
+	
+	//ram_check(0, 640 * 1024);
+
+	print_spew("Leaving auto.c:main()\r\n");
+}

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/chip.h	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+	int nothing;
+};

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/cmos.layout	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/cmos.layout	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.asl	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,257 @@
+/*
+ * Minimalist ACPI DSDT table for EPIA-M / MII
+ * (C) Copyright 2004 Nick Barker <Nick.Barker9 at btinternet.com>
+ *
+ * 
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+	/*  
+	 * Define the main processor
+	 */
+	Scope (\_PR)
+	{
+		Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
+	}
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 * any others would involve declaring the wake up methods
+	 */
+	Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
+
+	/* Root of the bus hierarchy */
+	Scope (\_SB)
+    	{
+		/* Define how interrupt Link A is plumbed in */ 
+		Device (LNKA)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x01)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {5}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+ 			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKA 
+
+		/* Define how interrupt Link B is plumbed in */ 
+		Device (LNKB)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x02)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {9}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKB
+
+		/* Define how interrupt Link C is plumbed in */ 
+		Device (LNKC)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x03)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {9}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKC
+
+		/* Define how interrupt Link D is plumbed in */ 
+		Device (LNKD)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x04)
+			/* Status - always return ready */
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0B)
+ 			}
+			/* Current Resources - return irq set up in BIOS */  
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+				{
+					IRQ (Level, ActiveLow, Shared) {5}
+				})
+				Return (BUFF)
+                	}
+			/* Possible Resources - return the range of irqs
+			 * we are using for PCI - only here to keep Linux ACPI
+			 * happy 
+			 */
+			Method (_PRS, 0, NotSerialized)
+			{
+				Name (BUFF, ResourceTemplate ()
+                    		{
+					IRQ (Level, ActiveLow, Shared) {5,9,10}
+                    		})
+                    		Return (BUFF)
+                	}
+			/* Set Resources - dummy function to keep Linux ACPI happy
+                         * Linux is more than happy not to tinker with irq
+			 * assignments as long as the CRS and STA functions 
+			 * return good values
+			 */
+			Method (_SRS, 1, NotSerialized ) {}
+			/* Disable - dummy function to keep Linux ACPI happy */
+			Method (_DIS, 0, NotSerialized ) {}
+ 
+		} // End of LNKD 
+
+ 
+		/* top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+
+			/* PCI Routing Table */
+			Name (_PRT, Package () {
+				/* Epia-MII 6000e cardbus: */
+				Package () {0x000AFFFF, 0x00, LNKA, 0x00}, // Cardbus Link A
+				Package () {0x000AFFFF, 0x01, LNKB, 0x00}, // Cardbus Link B
+				Package () {0x000AFFFF, 0x02, LNKC, 0x00}, // Cardbus Link C
+				Package () {0x000AFFFF, 0x03, LNKD, 0x00}, // Cardbus Link D
+
+				Package () {0x000DFFFF, 0x00, LNKB, 0x00}, // Firewire Link B
+				Package () {0x000DFFFF, 0x01, LNKC, 0x00}, // Firewire Link C
+				Package () {0x000DFFFF, 0x02, LNKD, 0x00}, // Firewire Linc D
+				Package () {0x000DFFFF, 0x03, LNKA, 0x00}, // Firewire Link A
+
+				Package () {0x0010FFFF, 0x00, LNKA, 0x00}, // USB Link A
+				Package () {0x0010FFFF, 0x01, LNKB, 0x00}, // USB Link B
+				Package () {0x0010FFFF, 0x02, LNKC, 0x00}, // USB Link C
+				Package () {0x0010FFFF, 0x03, LNKD, 0x00}, // USB Link D
+
+				Package () {0x0011FFFF, 0x00, LNKA, 0x00}, // vt8623 Link A
+				Package () {0x0011FFFF, 0x01, LNKB, 0x00}, // vt8623 Link B
+				Package () {0x0011FFFF, 0x02, LNKC, 0x00}, // vt8623 Link C
+				Package () {0x0011FFFF, 0x03, LNKD, 0x00}, // vt8623 Link D
+
+				Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A 
+				Package () {0x0012FFFF, 0x01, LNKB, 0x00}, // LAN Link B
+				Package () {0x0012FFFF, 0x02, LNKC, 0x00}, // LAN Link C
+				Package () {0x0012FFFF, 0x03, LNKD, 0x00}, // LAN Link D
+
+				Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA 
+				Package () {0x0013FFFF, 0x01, LNKB, 0x00}, // Riser slot LinkB
+				Package () {0x0013FFFF, 0x02, LNKC, 0x00}, // Riser slot LinkC
+				Package () {0x0013FFFF, 0x03, LNKD, 0x00}, // Riser slot LinkD
+
+				Package () {0x0014FFFF, 0x00, LNKB, 0x00}, // Slot 1, Link B
+				Package () {0x0014FFFF, 0x01, LNKC, 0x00}, // Slot 1, Link C
+				Package () {0x0014FFFF, 0x02, LNKD, 0x00}, // Slot 1, Link D
+				Package () {0x0014FFFF, 0x03, LNKA, 0x00}, // Slot 1, Link A
+                
+				Package () {0x0001FFFF, 0x00, LNKA, 0x00}, // VGA Link A
+				Package () {0x0001FFFF, 0x01, LNKB, 0x00}, // VGA Link B
+				Package () {0x0001FFFF, 0x02, LNKC, 0x00}, // VGA Link C
+				Package () {0x0001FFFF, 0x03, LNKD, 0x00} // VGA Link D
+
+            		})
+
+
+		} // End of PCI0
+
+	} // End of _SB
+
+} // End of Definition Block
+

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,142 @@
+/*
+ * 
+ * Intel ACPI Component Architecture
+ * ASL Optimizing Compiler version 20060127 [Apr 23 2006]
+ * Copyright (C) 2000 - 2006 Intel Corporation
+ * Supports ACPI Specification Revision 3.0a
+ * 
+ * Compilation of "dsdt.asl" - Wed Sep  6 11:36:08 2006
+ * 
+ * C source code output
+ *
+ */
+unsigned char AmlCode[] =
+{
+    0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00,  /* 00000000    "DSDT...." */
+    0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53,  /* 00000008    "..LXBIOS" */
+    0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54,  /* 00000010    "LXB-DSDT" */
+    0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C,  /* 00000018    "....INTL" */
+    0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50,  /* 00000020    "'.. .._P" */
+    0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55,  /* 00000028    "R_[..CPU" */
+    0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08,  /* 00000030    "0......." */
+    0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00,  /* 00000038    "_S0_...." */
+    0x00,0x00,0x00,0x08,0x5F,0x53,0x35,0x5F,  /* 00000040    "...._S5_" */
+    0x12,0x08,0x04,0x0A,0x02,0x0A,0x02,0x00,  /* 00000048    "........" */
+    0x00,0x10,0x4E,0x39,0x5F,0x53,0x42,0x5F,  /* 00000050    "..N9_SB_" */
+    0x5B,0x82,0x44,0x06,0x4C,0x4E,0x4B,0x41,  /* 00000058    "[.D.LNKA" */
+    0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,  /* 00000060    "._HID.A." */
+    0x0C,0x0F,0x08,0x5F,0x55,0x49,0x44,0x01,  /* 00000068    "..._UID." */
+    0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,  /* 00000070    ".._STA.." */
+    0x0A,0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53,  /* 00000078    "...._CRS" */
+    0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09,  /* 00000080    "..BUFF.." */
+    0x0A,0x06,0x23,0x20,0x00,0x18,0x79,0x00,  /* 00000088    "..# ..y." */
+    0xA4,0x42,0x55,0x46,0x46,0x14,0x1A,0x5F,  /* 00000090    ".BUFF.._" */
+    0x50,0x52,0x53,0x00,0x08,0x42,0x55,0x46,  /* 00000098    "PRS..BUF" */
+    0x46,0x11,0x09,0x0A,0x06,0x23,0x20,0x06,  /* 000000A0    "F....# ." */
+    0x18,0x79,0x00,0xA4,0x42,0x55,0x46,0x46,  /* 000000A8    ".y..BUFF" */
+    0x14,0x06,0x5F,0x53,0x52,0x53,0x01,0x14,  /* 000000B0    ".._SRS.." */
+    0x06,0x5F,0x44,0x49,0x53,0x00,0x5B,0x82,  /* 000000B8    "._DIS.[." */
+    0x45,0x06,0x4C,0x4E,0x4B,0x42,0x08,0x5F,  /* 000000C0    "E.LNKB._" */
+    0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,  /* 000000C8    "HID.A..." */
+    0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,0x14,  /* 000000D0    "._UID..." */
+    0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,  /* 000000D8    "._STA..." */
+    0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53,0x00,  /* 000000E0    "..._CRS." */
+    0x08,0x42,0x55,0x46,0x46,0x11,0x09,0x0A,  /* 000000E8    ".BUFF..." */
+    0x06,0x23,0x00,0x02,0x18,0x79,0x00,0xA4,  /* 000000F0    ".#...y.." */
+    0x42,0x55,0x46,0x46,0x14,0x1A,0x5F,0x50,  /* 000000F8    "BUFF.._P" */
+    0x52,0x53,0x00,0x08,0x42,0x55,0x46,0x46,  /* 00000100    "RS..BUFF" */
+    0x11,0x09,0x0A,0x06,0x23,0x20,0x06,0x18,  /* 00000108    "....# .." */
+    0x79,0x00,0xA4,0x42,0x55,0x46,0x46,0x14,  /* 00000110    "y..BUFF." */
+    0x06,0x5F,0x53,0x52,0x53,0x01,0x14,0x06,  /* 00000118    "._SRS..." */
+    0x5F,0x44,0x49,0x53,0x00,0x5B,0x82,0x45,  /* 00000120    "_DIS.[.E" */
+    0x06,0x4C,0x4E,0x4B,0x43,0x08,0x5F,0x48,  /* 00000128    ".LNKC._H" */
+    0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,  /* 00000130    "ID.A...." */
+    0x5F,0x55,0x49,0x44,0x0A,0x03,0x14,0x09,  /* 00000138    "_UID...." */
+    0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B,  /* 00000140    "_STA...." */
+    0x14,0x1A,0x5F,0x43,0x52,0x53,0x00,0x08,  /* 00000148    ".._CRS.." */
+    0x42,0x55,0x46,0x46,0x11,0x09,0x0A,0x06,  /* 00000150    "BUFF...." */
+    0x23,0x00,0x02,0x18,0x79,0x00,0xA4,0x42,  /* 00000158    "#...y..B" */
+    0x55,0x46,0x46,0x14,0x1A,0x5F,0x50,0x52,  /* 00000160    "UFF.._PR" */
+    0x53,0x00,0x08,0x42,0x55,0x46,0x46,0x11,  /* 00000168    "S..BUFF." */
+    0x09,0x0A,0x06,0x23,0x20,0x06,0x18,0x79,  /* 00000170    "...# ..y" */
+    0x00,0xA4,0x42,0x55,0x46,0x46,0x14,0x06,  /* 00000178    "..BUFF.." */
+    0x5F,0x53,0x52,0x53,0x01,0x14,0x06,0x5F,  /* 00000180    "_SRS..._" */
+    0x44,0x49,0x53,0x00,0x5B,0x82,0x45,0x06,  /* 00000188    "DIS.[.E." */
+    0x4C,0x4E,0x4B,0x44,0x08,0x5F,0x48,0x49,  /* 00000190    "LNKD._HI" */
+    0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,  /* 00000198    "D.A...._" */
+    0x55,0x49,0x44,0x0A,0x04,0x14,0x09,0x5F,  /* 000001A0    "UID...._" */
+    0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B,0x14,  /* 000001A8    "STA....." */
+    0x1A,0x5F,0x43,0x52,0x53,0x00,0x08,0x42,  /* 000001B0    "._CRS..B" */
+    0x55,0x46,0x46,0x11,0x09,0x0A,0x06,0x23,  /* 000001B8    "UFF....#" */
+    0x20,0x00,0x18,0x79,0x00,0xA4,0x42,0x55,  /* 000001C0    " ..y..BU" */
+    0x46,0x46,0x14,0x1A,0x5F,0x50,0x52,0x53,  /* 000001C8    "FF.._PRS" */
+    0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09,  /* 000001D0    "..BUFF.." */
+    0x0A,0x06,0x23,0x20,0x06,0x18,0x79,0x00,  /* 000001D8    "..# ..y." */
+    0xA4,0x42,0x55,0x46,0x46,0x14,0x06,0x5F,  /* 000001E0    ".BUFF.._" */
+    0x53,0x52,0x53,0x01,0x14,0x06,0x5F,0x44,  /* 000001E8    "SRS..._D" */
+    0x49,0x53,0x00,0x5B,0x82,0x4B,0x1F,0x50,  /* 000001F0    "IS.[.K.P" */
+    0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44,  /* 000001F8    "CI0._HID" */
+    0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41,  /* 00000200    ".A...._A" */
+    0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44,  /* 00000208    "DR.._UID" */
+    0x00,0x08,0x5F,0x42,0x42,0x4E,0x00,0x08,  /* 00000210    ".._BBN.." */
+    0x5F,0x50,0x52,0x54,0x12,0x43,0x1D,0x20,  /* 00000218    "_PRT.C. " */
+    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0A,0x00,  /* 00000220    "........" */
+    0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,  /* 00000228    ".LNKA..." */
+    0x04,0x0C,0xFF,0xFF,0x0A,0x00,0x01,0x4C,  /* 00000230    ".......L" */
+    0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,  /* 00000238    "NKB....." */
+    0xFF,0xFF,0x0A,0x00,0x0A,0x02,0x4C,0x4E,  /* 00000240    "......LN" */
+    0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,  /* 00000248    "KC......" */
+    0xFF,0x0A,0x00,0x0A,0x03,0x4C,0x4E,0x4B,  /* 00000250    ".....LNK" */
+    0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 00000258    "D......." */
+    0x0D,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00,  /* 00000260    "...LNKB." */
+    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0D,0x00,  /* 00000268    "........" */
+    0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,  /* 00000270    ".LNKC..." */
+    0x04,0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x02,  /* 00000278    "........" */
+    0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0E,0x04,  /* 00000280    "LNKD...." */
+    0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x03,0x4C,  /* 00000288    ".......L" */
+    0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,  /* 00000290    "NKA....." */
+    0xFF,0xFF,0x10,0x00,0x00,0x4C,0x4E,0x4B,  /* 00000298    ".....LNK" */
+    0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 000002A0    "A......." */
+    0x10,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00,  /* 000002A8    "...LNKB." */
+    0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00,  /* 000002B0    "........" */
+    0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12,  /* 000002B8    "..LNKC.." */
+    0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00,0x0A,  /* 000002C0    "........" */
+    0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D,  /* 000002C8    ".LNKD..." */
+    0x04,0x0C,0xFF,0xFF,0x11,0x00,0x00,0x4C,  /* 000002D0    ".......L" */
+    0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,  /* 000002D8    "NKA....." */
+    0xFF,0xFF,0x11,0x00,0x01,0x4C,0x4E,0x4B,  /* 000002E0    ".....LNK" */
+    0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,  /* 000002E8    "B......." */
+    0x11,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43,  /* 000002F0    "....LNKC" */
+    0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x11,  /* 000002F8    "........" */
+    0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00,  /* 00000300    "...LNKD." */
+    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x12,0x00,  /* 00000308    "........" */
+    0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,  /* 00000310    ".LNKA..." */
+    0x04,0x0C,0xFF,0xFF,0x12,0x00,0x01,0x4C,  /* 00000318    ".......L" */
+    0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,  /* 00000320    "NKB....." */
+    0xFF,0xFF,0x12,0x00,0x0A,0x02,0x4C,0x4E,  /* 00000328    "......LN" */
+    0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,  /* 00000330    "KC......" */
+    0xFF,0x12,0x00,0x0A,0x03,0x4C,0x4E,0x4B,  /* 00000338    ".....LNK" */
+    0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 00000340    "D......." */
+    0x13,0x00,0x00,0x4C,0x4E,0x4B,0x41,0x00,  /* 00000348    "...LNKA." */
+    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x13,0x00,  /* 00000350    "........" */
+    0x01,0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E,  /* 00000358    ".LNKB..." */
+    0x04,0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x02,  /* 00000360    "........" */
+    0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04,  /* 00000368    "LNKC...." */
+    0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x03,0x4C,  /* 00000370    ".......L" */
+    0x4E,0x4B,0x44,0x00,0x12,0x0D,0x04,0x0C,  /* 00000378    "NKD....." */
+    0xFF,0xFF,0x14,0x00,0x00,0x4C,0x4E,0x4B,  /* 00000380    ".....LNK" */
+    0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 00000388    "B......." */
+    0x14,0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00,  /* 00000390    "...LNKC." */
+    0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00,  /* 00000398    "........" */
+    0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12,  /* 000003A0    "..LNKD.." */
+    0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00,0x0A,  /* 000003A8    "........" */
+    0x03,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,  /* 000003B0    ".LNKA..." */
+    0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C,  /* 000003B8    ".......L" */
+    0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,  /* 000003C0    "NKA....." */
+    0xFF,0xFF,0x01,0x00,0x01,0x4C,0x4E,0x4B,  /* 000003C8    ".....LNK" */
+    0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,  /* 000003D0    "B......." */
+    0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43,  /* 000003D8    "....LNKC" */
+    0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,  /* 000003E0    "........" */
+    0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00,  /* 000003E8    "...LNKD." */
+
+};

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/fadt.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/fadt.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/fadt.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,155 @@
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ * (C) Copyright 2004 Nick Barker <nick.barker9 at btinternet.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <string.h>
+#include <arch/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
+	acpi_header_t *header=&(fadt->header);
+
+	memset((void *)fadt,0,sizeof(acpi_fadt_t));
+	memcpy(header->signature,"FACP",4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id,OEM_ID,6);
+	memcpy(header->oem_table_id,"COREBOOT",8);
+	memcpy(header->asl_compiler_id,ASLC,4);
+	header->asl_compiler_revision=0;
+
+	fadt->firmware_ctrl=facs;
+	fadt->dsdt= dsdt;
+	fadt->preferred_pm_profile=0;
+	fadt->sci_int=5;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = 0x400;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = 0x404;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = 0x408;
+	fadt->gpe0_blk = 0x420;
+	fadt->gpe1_blk = 0x0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 4;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 90;
+	fadt->p_lvl3_lat = 900;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 0;
+	fadt->duty_width = 1;
+	fadt->day_alrm = 125;
+	fadt->mon_alrm = 126;
+	fadt->century = 50;
+	fadt->iapc_boot_arch = 0x1;
+	fadt->flags = 0x4a5;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 4;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = 0x400;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 2;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = 0x404;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = 0x0;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 4;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = 0x408;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 0;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = 0x420;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+
+}

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/failover.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/failover.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,34 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+
+static unsigned long main(unsigned long bist)
+{
+#if 0
+	/* This is the primary cpu how should I boot? */
+	if (do_normal_boot()) {
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
+	}
+ normal_image:
+	asm volatile ("jmp __normal_image" 
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm volatile ("jmp __cpu_reset"
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+#endif
+	return bist;
+}

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/irq_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/irq_tables.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Jon Harrison <bothlyn at blueyonder.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 7,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x11 << 3) | 0x0,	/* Interrupt router dev */
+	0x1c00,			/* IRQs devoted exclusively to PCI usage */
+	0x1106,			/* Vendor */
+	0x596,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xf,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x14 << 3) | 0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x1, 0x0},
+		{0x00, (0x13 << 3) | 0x0, {{0x05, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x01, 0xdeb8}}, 0x2, 0x0},
+		{0x00, (0x11 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x0f << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x12 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

Added: trunk/coreboot-v2/src/mainboard/via/epia-n/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/mainboard.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/mainboard.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("VIA EPIA-N Mainboard")
+};

Added: trunk/coreboot-v2/src/northbridge/via/cn400/Config.lb
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/Config.lb	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses CONFIG_HAVE_HIGH_TABLES
+
+config chip.h
+
+object vgabios.o
+
+driver northbridge.o
+driver agp.o
+driver vga.o
+
+default CONFIG_HAVE_HIGH_TABLES=1

Added: trunk/coreboot-v2/src/northbridge/via/cn400/agp.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/agp.c	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/agp.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "cn400.h"
+
+/* This is the main AGP device, and only one used when configured for AGP 2.0 */
+static void agp_init(device_t dev)
+{
+	u32 reg32;
+
+	/* Some of this may not be necessary (should be handled by the OS). */
+	printk_debug("Enabling AGP.\n");
+
+	/* Allow R/W access to AGP registers. */
+	pci_write_config8(dev, 0x4d, 0x15);
+
+	/* Setup PCI latency timer. */
+	pci_write_config8(dev, 0xd, 0x8);
+
+	/*
+	 * Set to AGP 3.0 Mode, which should theoretically render the rest of
+	 * the registers set here pointless.
+	 */
+	pci_write_config8(dev, 0x84, 0xb);
+
+	/* AGP Request Queue Size */
+	pci_write_config8(dev, 0x4a, 0x1f);
+
+	/*
+	 * AGP Hardware Support (default 0xc4)
+	 * 7: AGP SBA Enable (1 to Enable)
+	 * 6: AGP Enable
+	 * 5: Reserved
+	 * 4: Fast Write Enable
+	 * 3: AGP8X Mode Enable
+	 * 2: AGP4X Mode Enable
+	 * 1: AGP2X Mode Enable
+	 * 0: AGP1X Mode Enable
+	 */
+	pci_write_config8(dev, 0x4b, 0xc4);
+
+	/* Enable AGP Backdoor */
+	pci_write_config8(dev, 0xb5, 0x03);
+
+	/* Set aperture to 32 MB. */
+	/* TODO: Use config option, explain how it works. */
+	pci_write_config32(dev, 0x94, 0x00010f38);
+	/* Set GART Table Base Address (31:12). */
+	pci_write_config32(dev, 0x98, (0x1558 << 12));
+	/* Set AGP Aperture Base. */
+	pci_write_config32(dev, 0x10, 0xf8000008);
+
+	/* Enable CPU/PMSTR GART Access. */
+	reg32 = pci_read_config8(dev, 0xbf);
+	reg32 |= 0x80;
+	pci_write_config8(dev, 0xbf, reg32);
+
+	/* Enable AGP Aperture. */
+	reg32 = pci_read_config32(dev, 0x94);
+	reg32 |= (3 << 7);
+	pci_write_config32(dev, 0x90, reg32);
+
+	/* AGP Control */
+	pci_write_config8(dev, 0xbc, 0x21);
+	pci_write_config8(dev, 0xbd, 0xd2);
+
+	/*
+	 * AGP Pad, driving strength, and delay control. All this should be
+	 * constant, seeing as the VGA controller is onboard.
+	 */
+	pci_write_config8(dev, 0x40, 0xc7);
+	pci_write_config8(dev, 0x41, 0xdb);
+	pci_write_config8(dev, 0x42, 0x10);
+	pci_write_config8(dev, 0x43, 0xdb);
+	pci_write_config8(dev, 0x44, 0x24);
+
+	/* AGPC CKG Control */
+	pci_write_config8(dev, 0xc0, 0x02);
+	pci_write_config8(dev, 0xc1, 0x02);
+}
+
+static const struct device_operations agp_operations = {
+	.read_resources   = cn400_noop,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = agp_init,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver agp_driver __pci_driver = {
+	.ops    = &agp_operations,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = PCI_DEVICE_ID_VIA_CN400_AGP,
+};
+
+/*
+ * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
+ * config in this device takes presidence. We configure both just to be safe.
+ */
+static void agp_bridge_init(device_t dev)
+{
+	printk_debug("Setting up AGP bridge device\n");
+
+	pci_write_config16(dev, 0x4, 0x0007);
+
+	/* Secondary Bus Number */
+	pci_write_config8(dev, 0x19, 0x01);
+	/* Subordinate Bus Number */
+	pci_write_config8(dev, 0x1a, 0x01);
+	/* I/O Base */
+	pci_write_config8(dev, 0x1c, 0xd0);
+	/* I/O Limit */
+	pci_write_config8(dev, 0x1d, 0xd0);
+
+	/* Memory Base */
+	pci_write_config16(dev, 0x20, 0xfb00);
+	/* Memory Limit */
+	pci_write_config16(dev, 0x22, 0xfcf0);
+	/* Prefetchable Memory Base */
+	pci_write_config16(dev, 0x24, 0xf400);
+	/* Prefetchable Memory Limit */
+	pci_write_config16(dev, 0x26, 0xf7f0);
+	/* Enable VGA Compatible Memory/IO Range */
+	pci_write_config8(dev, 0x3e, 0x08);
+
+	/* Second PCI Bus Control (see datasheet) */
+	pci_write_config8(dev, 0x40, 0x83);
+	pci_write_config8(dev, 0x41, 0x43);
+	pci_write_config8(dev, 0x42, 0xe2);
+	pci_write_config8(dev, 0x43, 0x44);
+	pci_write_config8(dev, 0x44, 0x34);
+	pci_write_config8(dev, 0x45, 0x72);
+}
+
+static const struct device_operations agp_bridge_operations = {
+	.read_resources   = cn400_noop,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = agp_bridge_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver agp_bridge_driver __pci_driver = {
+	.ops    = &agp_bridge_operations,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = PCI_DEVICE_ID_VIA_CN400_BRIDGE,
+};

Added: trunk/coreboot-v2/src/northbridge/via/cn400/chip.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/chip.h	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_via_cn400_config {
+};
+
+extern struct chip_operations northbridge_via_cn400_ops;

Added: trunk/coreboot-v2/src/northbridge/via/cn400/cn400.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/cn400.h	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/cn400.h	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __ROMCC__
+static void cn400_noop()
+{
+}
+#endif
+
+/* VGA stuff */
+#define SR_INDEX		0x3c4
+#define SR_DATA			0x3c5
+#define CRTM_INDEX		0x3b4
+#define CRTM_DATA		0x3b5
+#define CRTC_INDEX		0x3d4
+#define CRTC_DATA		0x3d5
+
+/* Memory controller registers */
+#define RANK0_END		0x40
+#define RANK1_END		0x41
+#define RANK2_END		0x42
+#define RANK3_END		0x43
+
+#define DDR_PAGE_CTL			0x69
+#define DRAM_REFRESH_COUNTER	0x6a
+#define DRAM_MISC_CTL			0x6b
+#define CH_A_DQS_OUTPUT_DELAY	0x70
+#define CH_A_MD_OUTPUT_DELAY	0x71
+
+/* RAM init commands */
+#define RAM_COMMAND_NORMAL		(const char) 0x00
+#define RAM_COMMAND_NOP			(const char) 0x01
+#define RAM_COMMAND_PRECHARGE	(const char) 0x02
+#define RAM_COMMAND_MSR_LOW		(const char) 0x03
+#define RAM_COMMAND_CBR			(const char) 0x04
+#define RAM_COMMAND_MSR_HIGH	(const char) 0x05

Added: trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,281 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "cn400.h"
+
+static void memctrl_init(device_t dev)
+{
+	device_t vlink_dev;
+	u16 reg16;
+	u8 ranks, pagec, paged, pagee, pagef, shadowreg;
+
+	printk_spew("Entering cn400 memctrl_init.\n");
+	
+	/* Set up the VGA framebuffer size. */
+	reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
+	pci_write_config16(dev, 0xa0, reg16);
+
+	/* Set up VGA timers. */
+	pci_write_config8(dev, 0xa2, 0x44);
+
+	for (ranks = 0x4b; ranks >= 0x48; ranks--) {
+		if (pci_read_config8(dev, ranks)) {
+			ranks -= 0x48;
+			break;
+		}
+	}
+	if (ranks == 0x47)
+		ranks = 0x00;
+	reg16 = 0xaaf0;
+	reg16 |= ranks;
+	/* GMINT Misc. FrameBuffer rank */
+	pci_write_config16(dev, 0xb0, reg16);
+	/* AGPCINT Misc. */
+	pci_write_config8(dev, 0xb8, 0x08);
+
+	/* Shadow RAM */
+	pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
+	/* PAGE C, D, E are all read write enable */
+	pci_write_config8(dev, 0x80, pagec);
+	pci_write_config8(dev, 0x81, paged);
+	pci_write_config8(dev, 0x83, pagee);
+	/* PAGE F are read/writable */
+	shadowreg = pci_read_config8(dev, 0x82);
+	shadowreg |= pagef;
+	pci_write_config8(dev, 0x82, shadowreg);
+	/* vlink mirror */
+	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+				    PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
+	if (vlink_dev) {
+		pci_write_config8(vlink_dev, 0x61, pagec);
+		pci_write_config8(vlink_dev, 0x62, paged);
+		pci_write_config8(vlink_dev, 0x64, pagee);
+
+		shadowreg = pci_read_config8(vlink_dev, 0x63);
+		shadowreg |= pagef;
+		pci_write_config8(vlink_dev, 0x63, shadowreg);
+	}
+	
+	printk_spew("Leaving cn400 memctrl_init.\n");
+}
+
+static const struct device_operations memctrl_operations = {
+	.read_resources = cn400_noop,
+	.init           = memctrl_init,
+};
+
+static const struct pci_driver memctrl_driver __pci_driver = {
+	.ops    = &memctrl_operations,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL,
+};
+
+static void pci_domain_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	printk_spew("Entering cn400 pci_domain_read_resources.\n");
+
+	/* Initialize the system wide I/O space constraints. */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	resource->limit = 0xffffUL;
+	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+	    IORESOURCE_ASSIGNED;
+
+	/* Initialize the system wide memory resources constraints. */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	resource->limit = 0xffffffffULL;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+	    IORESOURCE_ASSIGNED;
+
+	printk_spew("Leaving cn400 pci_domain_read_resources.\n");
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+			 unsigned long basek, unsigned long sizek)
+{
+	struct resource *resource;
+
+	if (!sizek)
+		return;
+
+	resource = new_resource(dev, index);
+	resource->base = ((resource_t) basek) << 10;
+	resource->size = ((resource_t) sizek) << 10;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+	struct resource **best_p = gp;
+	struct resource *best;
+
+	best = *best_p;
+	if (!best || (best->base > new->base))
+		best = new;
+	*best_p = best;
+}
+
+static u32 find_pci_tolm(struct bus *bus)
+{
+	struct resource *min;
+	u32 tolm;
+
+	print_debug("Entering CN400 find_pci_tolm\n");
+
+	min = 0;
+	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
+			     tolm_test, &min);
+	tolm = 0xffffffffUL;
+	if (min && tolm > min->base)
+		tolm = min->base;
+
+	print_debug("Leaving find_pci_tolm\n");
+
+	return tolm;
+}
+
+#if HAVE_HIGH_TABLES==1
+/* maximum size of high tables in KB */
+#define HIGH_TABLES_SIZE 64
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	/* The order is important to find the correct RAM size. */
+	static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
+	device_t mc_dev;
+	u32 pci_tolm;
+
+	printk_spew("Entering cn400 pci_domain_set_resources.\n");
+
+	pci_tolm = find_pci_tolm(&dev->link[0]);
+	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+				 PCI_DEVICE_ID_VIA_CN400_MEMCTRL, 0);
+
+	if (mc_dev) {
+		unsigned long tomk, tolmk;
+		unsigned char rambits;
+		int i, idx;
+
+		/*
+		 * Once the register value is not zero, the RAM size is
+		 * this register's value multiply 64 * 1024 * 1024.
+		 */
+		for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+			rambits = pci_read_config8(mc_dev, ramregs[i]);
+			if (rambits != 0)
+				break;
+		}
+
+		tomk = rambits * 64 * 1024;
+		printk_spew("tomk is 0x%x\n", tomk);
+		/* Compute the Top Of Low Memory (TOLM), in Kb. */
+		tolmk = pci_tolm >> 10;
+		if (tolmk >= tomk) {
+			/* The PCI hole does does not overlap the memory. */
+			tolmk = tomk;
+		}
+
+#if HAVE_HIGH_TABLES == 1
+		high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+		high_tables_size = HIGH_TABLES_SIZE* 1024;
+		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+#endif
+
+		/* Report the memory regions. */
+		idx = 10;
+		/* TODO: Hole needed? */
+		ram_resource(dev, idx++, 0, 640);	/* First 640k */
+		/* Leave a hole for VGA, 0xa0000 - 0xc0000 */
+		ram_resource(dev, idx++, 768,
+			     (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
+	}
+	assign_resources(&dev->link[0]);
+	
+	printk_spew("Leaving cn400 pci_domain_set_resources.\n");
+}
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+	printk_debug("Entering cn400 pci_domain_scan_bus.\n");
+
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
+}
+
+static const struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = enable_childrens_resources,
+	.init             = 0,
+	.scan_bus         = pci_domain_scan_bus,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static const struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+	printk_spew("In cn400 enable_dev for device %s.\n", dev_path(dev));
+
+	/* Set the operations if it is a special bus type. */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+		pci_set_method(dev);
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_via_cn400_ops = {
+	CHIP_NAME("VIA CN400 Northbridge")
+	.enable_dev = enable_dev,
+};

Added: trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.h	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.h	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_VIA_CN400_H
+#define NORTHBRIDGE_VIA_CN400_H
+
+extern unsigned int cn400_scan_root_bus(device_t root, unsigned int max);
+
+#endif /* NORTHBRIDGE_VIA_CN400_H */

Added: trunk/coreboot-v2/src/northbridge/via/cn400/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/raminit.c	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/raminit.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,809 @@
+/*
+ * (C) Copyright 2005 Nick Barker <nick.barker9 at btinternet.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* 
+  Automatically detect and set up ddr dram on the CLE266 chipset.
+  Assumes DDR memory, though chipset also supports SDRAM
+  Assumes at least 266Mhz memory as no attempt is made to clock
+  the chipset down if slower memory is installed.
+  So far tested on:
+	256 Mb 266Mhz 1 Bank (i.e. single sided)
+	256 Mb 266Mhz 2 Bank (i.e. double sided)
+	512 Mb 266Mhz 2 Bank (i.e. double sided)
+*/
+/* ported and enhanced from assembler level code in coreboot v1 */
+
+#include <spd.h>
+#include <sdram_mode.h>
+#include <delay.h>
+#include <cpu/x86/mtrr.h>
+#include "cn400.h"
+
+static void dimm_read(unsigned long bank,unsigned long x) 
+{
+	//unsigned long eax; 
+	volatile unsigned long y;
+	//eax =  x;
+	y = * (volatile unsigned long *) (x+ bank) ;
+
+}
+
+
+static void print_val(char *str, int val)
+{
+	print_debug(str);
+	print_debug_hex8(val);
+}
+
+/**
+ * Configure the bus between the CPU and the northbridge. This might be able to 
+ * be moved to post-ram code in the future. For the most part, these registers
+ * should not be messed around with. These are too complex to explain short of
+ * copying the datasheets into the comments, but most of these values are from
+ * the BIOS Porting Guide, so they should work on any board. If they don't,
+ * try the values from your factory BIOS.
+ *
+ * TODO: Changing the DRAM frequency doesn't work (hard lockup).
+ *
+ * @param dev The northbridge's CPU Host Interface (D0F2).
+ */
+static void c3_cpu_setup(device_t dev)
+{
+	/* Host bus interface registers (D0F2 0x50-0x67) */
+	/* Taken from CN700 and updated from running CN400 */
+	
+	/* Host Bus I/O Circuit (see datasheet) */
+	/* Host Address Pullup/down Driving */
+	pci_write_config8(dev, 0x70, 0x33);
+	pci_write_config8(dev, 0x71, 0x44);
+	pci_write_config8(dev, 0x72, 0x33);
+	pci_write_config8(dev, 0x73, 0x44);
+	
+	/* Output Delay Stagger Control */
+	pci_write_config8(dev, 0x74, 0x70);
+	
+	/* AGTL+ I/O Circuit */
+	pci_write_config8(dev, 0x75, 0x08);
+	
+	/* AGTL+ Compensation Status */
+	pci_write_config8(dev, 0x76, 0x74);
+	
+	/* AGTL+ Auto Compensation Offest */
+	pci_write_config8(dev, 0x77, 0x00);
+	
+	/* Request phase control */
+	pci_write_config8(dev, 0x50, 0xA8);
+
+	/* Line DRDY# Timing Control */
+	pci_write_config8(dev, 0x60, 0x00);
+	pci_write_config8(dev, 0x61, 0x00);
+	pci_write_config8(dev, 0x62, 0x00);
+	
+	/* QW DRDY# Timing Control */
+	pci_write_config8(dev, 0x63, 0x00);
+	pci_write_config8(dev, 0x64, 0x00);
+	pci_write_config8(dev, 0x65, 0x00);
+	
+	/* Read Line Burst DRDY# Timing Control */
+	pci_write_config8(dev, 0x66, 0x00);
+	pci_write_config8(dev, 0x67, 0x00);
+	
+	/* CPU Interface Control */
+	pci_write_config8(dev, 0x51, 0xFE);
+	pci_write_config8(dev, 0x52, 0xEF);
+	
+	/* Arbitration */
+	pci_write_config8(dev, 0x53, 0x88);
+		
+	/* Write Policy & Reorder Latecy */
+	pci_write_config8(dev, 0x56, 0x00);
+	
+	/* Delivery-Trigger Control */
+	pci_write_config8(dev, 0x58, 0x00);
+		
+	/* IPI Control */
+	pci_write_config8(dev, 0x59, 0x30);
+	
+	/* CPU Misc Control */
+	pci_write_config8(dev, 0x5C, 0x00);
+	
+	/* Write Policy */
+	pci_write_config8(dev, 0x5d, 0xb2);
+	
+	/* Bandwidth Timer */
+	pci_write_config8(dev, 0x5e, 0x88);
+	
+	/* CPU Miscellaneous Control */
+	pci_write_config8(dev, 0x5f, 0xc7);
+	
+	/* CPU Miscellaneous Control */
+	pci_write_config8(dev, 0x55, 0x28);
+	
+}
+ 
+static void ddr_ram_setup(void) 
+{
+	uint8_t b, c, bank, ma;
+	uint16_t i;
+	unsigned long bank_address;
+	
+	
+	print_debug("CN400 RAM init starting\r\n");	
+
+	pci_write_config8(ctrl.d0f7, 0x75, 0x08);
+	
+		
+	/* No  Interleaving or Multi Page */
+	pci_write_config8(ctrl.d0f3, 0x69, 0x00);
+	pci_write_config8(ctrl.d0f3, 0x6b, 0x10);	
+	
+/*
+    DRAM MA Map Type  Device 0  Fn3 Offset 50-51
+
+    Determine memory addressing based on the module's memory technology and
+    arrangement.  See Table 4-9 of Intel's 82443GX datasheet for details.
+
+    Bank 1/0 MA map type   50[7-5]
+    Bank 1/0 command rate  50[4]
+    Bank 3/2 MA map type   50[3-1]
+    Bank 3/2 command rate  50[0]
+
+
+    Read SPD byte 17, Number of banks on SDRAM device.
+*/
+	c = 0;
+	b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
+	//print_val("Detecting Memory\r\nNumber of Banks ",b);
+
+	// Only supporting 4 bank chips just now
+	if( b == 4 ){
+		/*
+    		Read SPD byte 3, Number of row addresses.
+		*/
+		c = 0;
+		bank = 0x40;
+		b = smbus_read_byte(0x50, SPD_NUM_ROWS);
+		//print_val("\r\nNumber of Rows ", b);
+		
+		if( b >= 0x0d ){	// 256/512Mb
+		
+			if (b == 0x0e)
+				bank = 0x48;
+			else
+				bank = 0x44;
+			 
+			/*
+    			Read SPD byte 13, Primary DRAM width.
+			*/
+			b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
+			//print_val("\r\nPrimary DRAM width", b);
+			if( b != 4 )   // not 64/128Mb (x4)
+				c = 0x80;  // 256Mb
+		}
+
+		/*
+    		Read SPD byte 4, Number of column addresses.
+		*/		
+		b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
+		//print_val("\r\nNo Columns ",b);
+		if( b == 10 || b == 11 || b == 12) c |= 0x60;   // 10/11 bit col addr
+		if( b == 9 ) c |= 0x40;           // 9 bit col addr
+		if( b == 8 ) c |= 0x20;           // 8 bit col addr
+
+		//print_val("\r\nMA type ", c);
+		pci_write_config8(ctrl.d0f3, 0x50, c);
+
+	}
+/*	else
+	{
+		die("DRAM module size is not supported by CN400\r\n");
+	}
+*/
+
+/*
+    DRAM bank size.  See 4.3.1 pg 35
+
+    5a->5d  set to end address for each bank.  1 bit == 32MB
+    5a = bank 0
+    5b = bank 0 + b1
+    5c = bank 0 + b1 + b2
+    5d = bank 0 + b1 + b2 + b3
+*/
+
+	// Read SPD byte 31 Module bank density
+	//c = 0;
+	b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+	if( b & 0x02 )
+	{ 
+		c = 0x40;         				// 2GB
+		bank |= 0x02;
+	}
+	else if( b & 0x01) 
+	{
+		c = 0x20;    					// 1GB
+		if (bank == 0x48) bank |= 0x01;
+		else bank |= 0x03;
+	}
+	else if( b & 0x80)
+	{
+		c = 0x10;    					// 512MB
+		if (bank == 0x44) bank |= 0x02;
+	}
+	else if( b & 0x40) 
+	{	
+		c = 0x08;    					// 256MB
+		if (bank == 0x44) bank |= 0x01;
+		else bank |= 0x03;
+	} 
+	else if( b & 0x20)
+	{
+		c = 0x04;    					// 128MB
+		if (bank == 0x40) bank |= 0x02;
+	}
+	else if( b & 0x10)
+	{
+		c = 0x02;    					// 64MB
+		bank |= 0x01;
+	}
+	else if( b & 0x08) c = 0x01;    	// 32MB
+	else c = 0x01;                  	// Error, use default
+
+	//print_val("\r\nBank 0 (*32 Mb) ",c);
+
+	// set bank zero size
+	pci_write_config8(ctrl.d0f3, 0x40, c);
+	
+	// SPD byte 5  # of physical banks
+	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
+
+	//print_val("\r\nNo Physical Banks ",b);
+	if( b == 2)
+	{
+		c <<=1;
+		bank |= 0x80;
+		//print_val("\r\nTotal Memory (*32 Mb) ",c);
+	}
+/*	else
+	{
+		die("Only a single DIMM is supported by EPIA-N(L)\r\n");	
+	}
+*/
+	// set banks 1,2,3...
+	pci_write_config8(ctrl.d0f3, 0x41,c);
+	pci_write_config8(ctrl.d0f3, 0x42,c);
+	pci_write_config8(ctrl.d0f3, 0x43,c);
+	pci_write_config8(ctrl.d0f3, 0x44,c);
+	pci_write_config8(ctrl.d0f3, 0x45,c);
+	pci_write_config8(ctrl.d0f3, 0x46,c);
+	pci_write_config8(ctrl.d0f3, 0x47,c);
+	
+	ma = bank;
+		
+	/* Read SPD byte 18 CAS Latency */
+	b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
+/*	print_debug("\r\nCAS Supported ");
+	if(b & 0x04)
+		print_debug("2 ");
+	if(b & 0x08)
+		print_debug("2.5 ");
+	if(b & 0x10)
+		print_debug("3");
+
+	c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+	print_val("\r\nCycle time at CL X     (nS)", c);
+	c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
+	print_val("\r\nCycle time at CL X-0.5 (nS)", c);
+	c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
+	print_val("\r\nCycle time at CL X-1   (nS)", c);
+*/	
+	bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+
+	/* Setup DRAM Cycle Time */
+	if ( bank <= 0x50 ) bank = 0x14;
+	else if (bank <= 0x60) bank = 0x18;
+	else bank = 0x1E;
+		
+	if( b & 0x10 ){             // DDR offering optional CAS 3
+		//print_debug("\r\nStarting at CAS 3");
+		c = 0x30;
+		/* see if we can better it */
+		if( b & 0x08 ){     // DDR mandatory CAS 2.5
+			if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
+				//print_debug("\r\nWe can do CAS 2.5");
+				c = 0x20;
+			}
+		}
+		if( b & 0x04 ){     // DDR mandatory CAS 2
+			if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
+				//print_debug("\r\nWe can do CAS 2");
+				c = 0x10;
+			}
+		}
+	}else{                     // no optional CAS values just 2 & 2.5
+		//print_debug("\r\nStarting at CAS 2.5");
+		c = 0x20;          // assume CAS 2.5
+		if( b & 0x04){      // Should always happen
+			if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
+				//print_debug("\r\nWe can do CAS 2");
+				c = 0x10;
+			}
+		}
+	}	
+
+/*
+    DRAM Timing  Device 0  Fn 3 Offset 56
+
+    RAS Pulse width 56[7,6]
+    CAS Latency     56[5,4]
+    Row pre-charge  56[1,0]
+
+         SDR  DDR
+      00  1T   -
+      01  2T   2T
+      10  3T   2.5T
+      11  -    3T
+
+    RAS/CAS delay   56[3,2]
+
+    Determine row pre-charge time (tRP)
+
+
+    Read SPD byte 27, min row pre-charge time.
+*/
+
+	b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
+	
+	//print_val("\r\ntRP ",b);
+	if ( b >= (5 * bank)) {
+		c |= 0x03;		// set tRP = 5T
+	}
+	else if ( b >= (4 * bank)) {
+		c |= 0x02;		// set tRP = 4T
+	}
+	else if ( b >= (3 * bank)) {
+		c |= 0x01;		// set tRP = 3T
+	}
+
+/*
+    Determine RAS to CAS delay (tRCD)
+
+    Read SPD byte 29, min row pre-charge time.
+*/
+
+	b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
+	//print_val("\r\ntRCD ",b);
+
+	if ( b >= (5 * bank)) c |= 0x0C;		// set tRCD = 5T
+	else if ( b >= (4 * bank)) c |= 0x08;	// set tRCD = 4T
+	else if ( b >= (3 * bank)) c |= 0x04;	// set tRCD = 3T
+
+/*
+    Determine RAS pulse width (tRAS)
+
+
+    Read SPD byte 30, device min active to pre-charge time.
+*/
+
+	b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+	//print_val("\r\ntRAS ",b);
+	if ( b >= (9 * bank)) c |= 0xC0;		// set tRAS = 9T
+	else if ( b >= (8 * bank)) c |= 0x80;	// set tRAS = 8T
+	else if ( b >= (7 * bank)) c |= 0x40;	// set tRAS = 7T
+	
+	/* Write DRAM Timing All Banks I */
+	pci_write_config8(ctrl.d0f3, 0x56, c);
+	
+	/* TWrite DRAM Timing All Banks II */
+	pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
+	
+	/* DRAM arbitration timer */
+	pci_write_config8(ctrl.d0f3, 0x65, 0x99);
+		
+/*
+    DRAM Clock  Device 0 Fn 3 Offset 68
+*/
+	bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+
+	/* Setup DRAM Cycle Time */
+	if ( bank <= 0x50 )
+	{
+		/* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
+		/* This sets to 133MHz FSB / DDR400. */
+		pci_write_config8(ctrl.d0f3, 0x68, 0x85);
+	}
+	else if (bank <= 0x60)
+	{
+		/* DRAM DDR Control Alert! Alert! This hardwires to */
+		/* 133MHz FSB / DDR333.  See also c3_cpu_setup */
+		pci_write_config8(ctrl.d0f3, 0x68, 0x81);
+	}
+	else 
+	{
+		/* DRAM DDR Control Alert! Alert! This hardwires to */
+		/* 133MHz FSB / DDR266.  See also c3_cpu_setup */
+		pci_write_config8(ctrl.d0f3, 0x68, 0x80);
+	}
+
+	/* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
+	udelay(200);
+
+/*
+    Determine bank interleave
+
+    Read SPD byte 17, Number of banks on SDRAM device.
+*/
+	c = 0x0F;
+	b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
+	if( b == 4) c |= 0x80;
+	else if (b == 2) c |= 0x40;
+
+	/* 4-Way Interleave With Multi-Paging (From Running System)*/
+	pci_write_config8(ctrl.d0f3, 0x69, c);
+	
+	/* DRAM Arbitration Control */
+	pci_write_config8(ctrl.d0f3, 0x66, 0x82);
+
+	/* DRAM Control */
+	pci_write_config8(ctrl.d0f3, 0x6e, 0x00);
+	
+	/* Disable refresh for now */
+	pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
+
+
+
+	/* DRAM Clock Control */
+	pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
+
+	/* DRAM Bus Turn-Around Setting */
+	pci_write_config8(ctrl.d0f3, 0x60, 0x01);
+	
+	/* Disable DRAM refresh */
+	pci_write_config8(ctrl.d0f3,0x6a,0x0);
+
+
+	/* Memory Pads Driving and Range Select */
+	pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
+	pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
+	pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
+
+	/* DRAM signal timing control */
+	pci_write_config8(ctrl.d0f3, 0x74, 0x99);	
+	pci_write_config8(ctrl.d0f3, 0x76, 0x09);
+
+	pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
+	pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
+	pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
+	pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
+	pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
+
+
+	/* SPD byte 5  # of physical banks */
+	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
+	c = b | 0x40;
+
+	pci_write_config8(ctrl.d0f3, 0xb0, c);
+	
+	/* Enable DIMM Ranks */
+	pci_write_config8(ctrl.d0f3, 0x48, ma);
+	udelay(200);
+
+	c = smbus_read_byte(0x50, SPD_SUPPORTED_BURST_LENGTHS);
+	c &= 0x08;
+	if ( c == 0x08 )
+	{
+		print_debug("Setting Burst Length 8\r\n");
+		/*
+    		CPU Frequency  Device 0 Function 2 Offset 54
+
+			CPU FSB Operating Frequency (bits 7:5)
+	    	  	000 : 100MHz    001 : 133MHz
+	    	  	010 : 200MHz    
+			  	011->111 : Reserved
+		  
+			SDRAM BL8 (4)
+			
+			Don't change Frequency from power up defaults
+			This seems to lockup the RAM interface
+		*/	
+		c = pci_read_config8(ctrl.d0f2, 0x54);
+		c |= 0x10;
+		pci_write_config8(ctrl.d0f2, 0x54, c);
+		i = 0x008; 		// Used later to set SDRAM MSR
+	}
+
+		
+	for( bank = 0 , bank_address=0; bank <= b ; bank++) {
+/*
+    DDR init described in Via VT8623 BIOS Porting Guide.  Pg 28 (4.2.3.1)
+*/
+
+		/* NOP command enable */
+		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
+		c &= 0xf8;		/* Clear bits 2-0. */
+		c |= RAM_COMMAND_NOP;
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+
+		/* read a double word from any address of the dimm */
+		dimm_read(bank_address,0x1f000);
+		//udelay(200);
+
+		/* All bank precharge Command Enable */
+		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
+		c &= 0xf8;		/* Clear bits 2-0. */
+		c |= RAM_COMMAND_PRECHARGE;
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+		dimm_read(bank_address,0x1f000);
+
+
+		/* MSR Enable Low DIMM*/
+		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
+		c &= 0xf8;		/* Clear bits 2-0. */
+		c |= RAM_COMMAND_MSR_LOW;
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);	
+		/* TODO: Bank Addressing for Different Numbers of Row Addresses */	
+		dimm_read(bank_address,0x2000);
+		udelay(1);
+		dimm_read(bank_address,0x800);
+		udelay(1);
+
+		/* All banks precharge Command Enable */
+		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
+		c &= 0xf8;		/* Clear bits 2-0. */
+		c |= RAM_COMMAND_PRECHARGE;
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+		dimm_read(bank_address,0x1f200);
+
+		/* CBR Cycle Enable */
+		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
+		c &= 0xf8;		/* Clear bits 2-0. */
+		c |= RAM_COMMAND_CBR;
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+
+		/* Read 8 times */
+		for (c=0;c<8;c++) {
+			dimm_read(bank_address,0x1f300);
+			udelay(100);
+		}
+
+		/* MSR Enable */
+		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
+		c &= 0xf8;		/* Clear bits 2-0. */
+		c |= RAM_COMMAND_MSR_LOW;
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);		
+
+
+/* 
+    Mode Register Definition
+    with adjustement so that address calculation is correct - 64 bit technology, therefore
+    a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
+    to DIMM as a row or column address.
+
+    MR[9-7]   CAS Latency
+    MR[6]     Burst Type 0 = sequential, 1 = interleaved
+    MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
+    MR[0-2]   dont care 
+
+    CAS Latency 
+    000       reserved
+    001       reserved
+    010       2
+    011       3
+    100       reserved
+    101       1.5
+    110       2.5
+    111       reserved
+
+    CAS 2     0101011000 = 0x158
+    CAS 2.5   1101011000 = 0x358
+    CAS 3     0111011000 = 0x1d8
+
+*/
+		c = pci_read_config8(ctrl.d0f3, 0x56);
+		if( (c & 0x30) == 0x10 )
+			dimm_read(bank_address,(0x150 + i));
+		else if((c & 0x30) == 0x20 )
+			dimm_read(bank_address,(0x350 + i));
+		else
+			dimm_read(bank_address,(0x1d0 + i));
+
+
+		/* Normal SDRAM Mode */
+		c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
+		c &= 0xf8;		/* Clear bits 2-0. */
+		c |= RAM_COMMAND_NORMAL;
+		pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
+				
+		bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
+	} // end of for each bank
+
+	
+	/* Set DRAM DQS Output Control */
+	pci_write_config8(ctrl.d0f3, 0x79, 0x11);
+	
+	/* Set DQS A/B Input delay to defaults */
+	pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
+	pci_write_config8(ctrl.d0f3, 0x7B, 0x62);	
+
+	/* SPD byte 5  # of physical banks */
+	b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
+	
+	/* determine low bond */
+	if( b == 2)
+		bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
+	else
+		bank_address = 0;
+
+	for(i = 0x40 ; i < 0x0ff; i++){
+		pci_write_config8(ctrl.d0f3,0x70,i);
+		// clear
+		*(volatile unsigned long*)(0x4000) = 0;
+		*(volatile unsigned long*)(0x4100+bank_address) = 0;
+		*(volatile unsigned long*)(0x4200) = 0;
+		*(volatile unsigned long*)(0x4300+bank_address) = 0;
+		*(volatile unsigned long*)(0x4400) = 0;
+		*(volatile unsigned long*)(0x4500+bank_address) = 0;
+
+		// fill
+		*(volatile unsigned long*)(0x4000) = 0x12345678;
+		*(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
+		*(volatile unsigned long*)(0x4200) = 0x78123456;
+		*(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
+		*(volatile unsigned long*)(0x4400) = 0x56781234;
+		*(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
+
+			// verify
+		if( *(volatile unsigned long*)(0x4000) != 0x12345678)
+			continue;
+
+		if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
+			continue;
+
+		if( *(volatile unsigned long*)(0x4200) != 0x78123456)
+			continue;
+
+		if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
+			continue;
+
+		if( *(volatile unsigned long*)(0x4400) != 0x56781234)
+			continue;
+
+		if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
+			continue;
+
+		// if everything verified then found low bond
+		break;
+		
+	}
+	print_val("\r\nLow Bond ",i);	
+	if( i < 0xff ){ 
+		c = i++;
+		for(  ; i <0xff ; i++){
+			pci_write_config8(ctrl.d0f3,0x70, i);
+			// clear
+			*(volatile unsigned long*)(0x8000) = 0;
+			*(volatile unsigned long*)(0x8100+bank_address) = 0;
+			*(volatile unsigned long*)(0x8200) = 0x0;
+			*(volatile unsigned long*)(0x8300+bank_address) = 0;
+			*(volatile unsigned long*)(0x8400) = 0x0;
+			*(volatile unsigned long*)(0x8500+bank_address) = 0;
+
+			// fill
+			*(volatile unsigned long*)(0x8000) = 0x12345678;
+			*(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
+			*(volatile unsigned long*)(0x8200) = 0x78123456;
+			*(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
+			*(volatile unsigned long*)(0x8400) = 0x56781234;
+			*(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
+
+			// verify
+			if( *(volatile unsigned long*)(0x8000) != 0x12345678)
+				break;
+
+			if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
+				break;
+
+			if( *(volatile unsigned long*)(0x8200) != 0x78123456)
+				break;
+
+			if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
+				break;
+
+			if( *(volatile unsigned long*)(0x8400) != 0x56781234)
+				break;
+
+			if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
+				break;
+
+		}
+		print_val("  High Bond ",i);
+		c = ((i - c)<<1)/3 + c;
+		print_val("  Setting DQS delay",c);
+		print_debug("\r\n");
+		pci_write_config8(ctrl.d0f3,0x70,c);
+	}else{
+		pci_write_config8(ctrl.d0f3,0x70,0x67);
+	}
+
+	/* Set DQS ChB Output to the default */
+	pci_write_config8(ctrl.d0f3, 0x71, 0x6c);
+	
+	/* Set DQS Input Delays */
+	pci_write_config8(ctrl.d0f3, 0x72, 0x29);
+	pci_write_config8(ctrl.d0f3, 0x73, 0x99);	
+	
+	/* Mystery Value */
+	pci_write_config8(ctrl.d0f3, 0x67, 0x50);
+	
+	/* Enable Toggle Limiting */
+	pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
+	
+/*
+    DRAM refresh rate  Device 0 F3 Offset 6a
+	TODO :: Fix for different DRAM technologies 
+	other than 512Mb and DRAM Freq 
+    Units of 16 DRAM clock cycles - 1. 
+*/
+	//c = pci_read_config8(ctrl.d0f3, 0x68);
+	//c &= 0x07;
+	//b = smbus_read_byte(0x50, SPD_REFRESH);
+	//print_val("SPD_REFRESH = ", b);
+
+	pci_write_config8(ctrl.d0f3,0x6a,0x6C);
+	
+	
+	/* Enable TLB Auto refresh */
+	b = pci_read_config8(ctrl.d0f3, 0x69);
+	b |= 0x10;
+	pci_write_config8(ctrl.d0f3, 0x69, b);
+
+	/* Open Up the Rest of the Shadow RAM */
+	pci_write_config8(ctrl.d0f3,0x80,0xff);
+	pci_write_config8(ctrl.d0f3,0x81,0xff);
+
+	/* pci */
+	pci_write_config8(ctrl.d0f7,0x70,0x82);
+	pci_write_config8(ctrl.d0f7,0x73,0x01);
+	pci_write_config8(ctrl.d0f7,0x76,0x50);
+
+	pci_write_config8(ctrl.d0f7,0x71,0xc8);
+	
+    print_debug("CN400 Init done\r\n");
+
+	/* VGA device. */
+	pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
+	pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
+	
+	/* Graphics Control Basic Init. */
+	//pci_write_config8(ctrl.d0f3, 0xb0, 0xFf);
+	//pci_write_config8(ctrl.d0f3, 0xb1, 0xAA);
+	//pci_write_config8(ctrl.d0f3, 0xb2, 0xAA);
+	//pci_write_config8(ctrl.d0f3, 0xb3, 0x5A);
+	//pci_write_config8(ctrl.d0f3, 0xb4, 0x0f);
+	
+	/* AGP Controller Interface Basic Init */
+	//pci_write_config8(ctrl.d0f3, 0xc0, 0x3b);
+	
+	/* VGA device, Basic frame Buffer Init. */
+	//pci_write_config8(ctrl.d0f3, 0xa0, 0x01);
+	/* Bit 7 = Enable VGA When Set to 1 */
+	//pci_write_config8(ctrl.d0f3, 0xa1, 0xef);
+	//pci_write_config8(ctrl.d0f3, 0xa4, 0x00);
+
+}	

Added: trunk/coreboot-v2/src/northbridge/via/cn400/raminit.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/raminit.h	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/raminit.h	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood at verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#define DIMM_SOCKETS 1		/* Only one works, for now. */
+
+struct mem_controller {
+	device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0;
+	u8 channel0[DIMM_SOCKETS];
+};
+
+#endif

Added: trunk/coreboot-v2/src/northbridge/via/cn400/vga.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/vga.c	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/vga.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Note: Some of the VGA control registers are located on the memory
+ * controller. Registers are set both in raminit.c and northbridge.c.
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "cn400.h"
+#include "vgachip.h"
+
+void write_protect_vgabios(void)
+{
+	/* Don't bother for now. */
+}
+
+static void vga_init(device_t dev)
+{
+	u8 reg8;
+	u32 temp;
+
+	temp = (0xffffffff - CONFIG_FALLBACK_SIZE - 0xffff);
+	printk_debug("Copying BOCHS BIOS from 0x%08X	to 0xf000\n", temp);
+	/*
+	 * Copy BOCHS BIOS from 4G-CONFIG_FALLBACK_SIZE-64k (in flash) to 0xf0000 (in RAM)
+	 * This is for compatibility with the VGA ROM's BIOS callbacks.
+	 */
+	//memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
+	memcpy(0xf0000, temp, 0x10000);
+	printk_debug("Initializing VGA\n");
+
+	/* Set memory rate to 200 MHz. */
+	outb(0x3d, CRTM_INDEX);
+	reg8 = inb(CRTM_DATA);
+	reg8 &= 0x0f;
+	reg8 |= (0x1 << 4);
+	outb(0x3d, CRTM_INDEX);
+	outb(reg8, CRTM_DATA);
+
+	/* Set framebuffer size. */
+	reg8 = (CONFIG_VIDEO_MB / 4);
+	outb(0x39, SR_INDEX);
+	outb(reg8, SR_DATA);
+
+	pci_write_config8(dev, 0x04, 0x07);
+	pci_write_config8(dev, 0x0d, 0x20);
+	pci_write_config32(dev, 0x10, 0xf4000008);
+	pci_write_config32(dev, 0x14, 0xfb000000);
+
+	printk_debug("INSTALL REAL-MODE IDT\n");
+	setup_realmode_idt();
+	printk_debug("DO THE VGA BIOS\n");
+	do_vgabios();
+	/* VGA seems to work without this, but crash & burn with it. */
+	// printk_debug("Enable VGA console\n");
+	// vga_enable_console();
+
+	/* It's not clear if these need to be programmed before or after
+	 * the VGA BIOS runs. Try both, clean up later. */
+	/* Set memory rate to 200 MHz (again). */
+	outb(0x3d, CRTM_INDEX);
+	reg8 = inb(CRTM_DATA);
+	reg8 &= 0x0f;
+	reg8 |= (0x1 << 4);
+	outb(0x3d, CRTM_INDEX);
+	outb(reg8, CRTM_DATA);
+
+	/* Set framebuffer size (again). */
+	reg8 = (CONFIG_VIDEO_MB / 4);
+	outb(0x39, SR_INDEX);
+	outb(reg8, SR_DATA);
+
+	/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
+	memset(0xf0000, 0, 0x10000);
+}
+
+static void vga_read_resources(device_t dev)
+{
+	dev->rom_address = 0xfff80000;
+	dev->on_mainboard = 1;
+	pci_dev_read_resources(dev);
+}
+
+static const struct device_operations vga_operations = {
+	.read_resources   = vga_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = vga_init,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+	.ops    = &vga_operations,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = PCI_DEVICE_ID_VIA_CN400_VGA,
+};

Added: trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,839 @@
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#undef __KERNEL__
+#include <arch/io.h>
+//#include <printk.h>
+#include <string.h>
+#include "vgachip.h"
+
+/* vgabios.c. Derived from: */
+
+/*------------------------------------------------------------ -*- C -*-
+ *  2 Kernel Monte a.k.a. Linux loading Linux on x86
+ *
+ *  Erik Arjan Hendriks <hendriks at lanl.gov>
+ *
+ *  This version is a derivative of the original two kernel monte
+ *  which is (C) 2000 Scyld.
+ *
+ *  Copyright (C) 2000 Scyld Computing Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Portions related to the alpha architecture are:
+ *
+ *  Copyright(C) 2001 University of California.  LA-CC Number 01-67.
+ *  This software has been authored by an employee or employees of the
+ *  University of California, operator of the Los Alamos National
+ *  Laboratory under Contract No.  W-7405-ENG-36 with the U.S.
+ *  Department of Energy.  The U.S. Government has rights to use,
+ *  reproduce, and distribute this software. If the software is
+ *  modified to produce derivative works, such modified software should
+ *  be clearly marked, so as not to confuse it with the version
+ *  available from LANL.
+ *
+ *  This software may be used and distributed according to the terms
+ *  of the GNU General Public License, incorporated herein by
+ *  reference to http://www.gnu.org/licenses/gpl.html.
+ *
+ *  This software is provided by the author(s) "as is" and any express
+ *  or implied warranties, including, but not limited to, the implied
+ *  warranties of merchantability and fitness for a particular purpose
+ *  are disclaimed.  In no event shall the author(s) be liable for any
+ *  direct, indirect, incidental, special, exemplary, or consequential
+ *  damages (including, but not limited to, procurement of substitute
+ *  goods or services; loss of use, data, or profits; or business
+ *  interruption) however caused and on any theory of liability,
+ *  whether in contract, strict liability, or tort (including
+ *  negligence or otherwise) arising in any way out of the use of this
+ *  software, even if advised of the possibility of such damage.
+ *
+ *  $Id: vgabios.c,v 1.5 2004/10/06 17:33:52 rminnich Exp $
+ *--------------------------------------------------------------------*/
+
+/* Modified to be a self sufficient plug in so that it can be used 
+   without reliance on other parts of coreboot's core
+   (C) 2005 Nick.Barker9 at btinternet.com
+
+  Used initially for epia-m where there are problems getting the bios
+  emulator to successfully run this bios.
+*/
+
+/* Declare a temporary global descriptor table - necessary because the
+   Core part of the bios no longer sets up any 16 bit segments */
+__asm__ (
+	/* pointer to original gdt */
+	"gdtarg:			\n"
+	"	.word	gdt_limit	\n"
+	"	.long	gdt	       	\n"		
+
+	/* compute the table limit */
+	"__mygdt_limit = __mygdt_end - __mygdt - 1	\n"
+
+	"__mygdtaddr:			\n"
+	"	.word	__mygdt_limit  	\n"
+	"	.long	__mygdt	       	\n"
+
+	"__mygdt: 		       	\n"
+	/* selgdt 0, unused */
+	"	.word	0x0000, 0x0000	\n"
+	"	.byte	0x00, 0x00, 0x00, 0x00	\n"
+
+	/* selgdt 8, unused */
+	"	.word	0x0000, 0x0000	       	\n"
+	"	.byte	0x00, 0x00, 0x00, 0x00	\n"
+
+	/* selgdt 0x10, flat code segment */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0x00, 0x9b, 0xcf, 0x00	\n"	
+
+	/* selgdt 0x18, flat data segment */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0x00, 0x93, 0xcf, 0x00	\n"
+
+	/* selgdt 0x20, unused */
+	"	.word	0x0000, 0x0000	       	\n"
+	"	.byte	0x00, 0x00, 0x00, 0x00	\n"
+
+        /* selgdt 0x28 16-bit 64k code at 0x00000000 */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0, 0x9a, 0, 0	       	\n"
+
+	/* selgdt 0x30 16-bit 64k data at 0x00000000 */
+	"	.word	0xffff, 0x0000	       	\n"
+	"	.byte	0, 0x92, 0, 0	       	\n"
+
+	"__mygdt_end:				\n"
+);
+
+/* Declare a pointer to where our idt is going to be i.e. at mem zero */
+__asm__ ("__myidt:		\n"
+	 /* 16-bit limit */
+	 "	.word 1023	\n"
+	 /* 24-bit base */
+	 "	.long 0		\n"
+	 "	.word 0		\n"
+);
+
+/* The address arguments to this function are PHYSICAL ADDRESSES */ 
+static void real_mode_switch_call_vga(unsigned long devfn)
+{
+	__asm__ __volatile__ (
+		// paranoia -- does ecx get saved? not sure. This is 
+		// the easiest safe thing to do.
+		"	pushal			\n"
+		/* save the stack */
+		"	mov 	%esp, __stack	\n"
+		"	jmp 	1f		\n"
+		"__stack: .long 0		\n"
+		"1:\n"
+		/* get devfn into %ecx */
+		"	movl    %esp, %ebp	\n"
+		"	movl    8(%ebp), %ecx	\n"
+		/* load 'our' gdt */
+		"	lgdt	%cs:__mygdtaddr	\n"
+
+		/*  This configures CS properly for real mode. */
+		"	ljmp	$0x28, $__rms_16bit\n"
+		"__rms_16bit:		  	\n"
+		"	.code16			\n"
+		/* 16 bit code from here on... */
+
+		/* Load the segment registers w/ properly configured segment
+		 * descriptors.  They will retain these configurations (limits,
+		 * writability, etc.) once protected mode is turned off. */
+		"	mov	$0x30, %ax	\n"
+		"	mov	%ax, %ds       	\n"
+		"	mov	%ax, %es       	\n"
+		"	mov	%ax, %fs       	\n"
+		"	mov	%ax, %gs       	\n"
+		"	mov	%ax, %ss       	\n"
+
+		/* Turn off protection (bit 0 in CR0) */
+		"	movl	%cr0, %eax	\n"
+		"	andl	$0xFFFFFFFE, %eax \n"
+		"	movl	%eax, %cr0	\n"
+
+		/* Now really going into real mode */
+		"	ljmp	$0,  $__rms_real\n"
+		"__rms_real:			\n"
+
+		/* put the stack at the end of page zero. 
+		 * that way we can easily share it between real and protected, 
+		 * since the 16-bit ESP at segment 0 will work for any case. 
+		/* Setup a stack */
+		"	mov	$0x0, %ax	\n"
+		"	mov	%ax, %ss	\n"
+		"	movl	$0x1000, %eax	\n"
+		"	movl	%eax, %esp	\n"
+
+		/* Load our 16 it idt */
+		"	xor	%ax, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	lidt	__myidt		\n"
+
+		/* Dump zeros in the other segregs */
+		"	mov	%ax, %es       	\n"
+		"	mov	%ax, %fs       	\n"
+		"	mov	%ax, %gs       	\n"
+		"	mov	$0x40, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	mov	%cx, %ax	\n"
+
+		/* run VGA BIOS at 0xc000:0003 */
+		"	lcall	$0xc000, $0x0003\n"
+
+		/* if we got here, just about done. 
+		 * Need to get back to protected mode */
+		"	movl	%cr0, %eax	\n"
+		"	orl	$0x0000001, %eax\n" /* PE = 1 */
+		"	movl	%eax, %cr0	\n"
+
+		/* Now that we are in protected mode jump to a 32 bit code segment. */
+		"	data32	ljmp	$0x10, $vgarestart\n"
+		"vgarestart:\n"
+		"	.code32\n"
+		"	movw	$0x18, %ax     	\n"
+		"	mov	%ax, %ds       	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	%ax, %ss	\n"
+
+		/* restore proper gdt and idt */
+		"	lgdt	%cs:gdtarg	\n"
+		"	lidt	idtarg		\n"
+
+		".globl vga_exit		\n"
+		"vga_exit:			\n"
+		"	mov	__stack, %esp	\n"
+		"	popal			\n"
+		);
+}
+
+__asm__ (".text\n""real_mode_switch_end:\n");
+extern char real_mode_switch_end[];
+
+/* call vga bios int 10 function 0x4f14 to enable main console 
+   epia-m does not always autosence the main console so forcing it on is good !! */ 
+void vga_enable_console()
+{
+	__asm__ __volatile__ (
+		/* paranoia -- does ecx get saved? not sure. This is 
+		 * the easiest safe thing to do. */
+		"	pushal			\n"
+		/* save the stack */
+		"	mov	%esp, __stack	\n"
+
+		/* load 'our' gdt */
+		"	lgdt 	%cs:__mygdtaddr	\n"
+
+		/*  This configures CS properly for real mode. */
+		"	ljmp 	$0x28, $__vga_ec_16bit\n"
+		"__vga_ec_16bit:		\n"
+		"	.code16			\n"
+		/* 16 bit code from here on... */
+
+		/* Load the segment registers w/ properly configured segment
+		 * descriptors.  They will retain these configurations (limits,
+		 * writability, etc.) once protected mode is turned off. */
+		"	mov	$0x30, %ax     	\n"
+		"	mov	%ax, %ds       	\n"
+		"	mov	%ax, %es       	\n"
+		"	mov	%ax, %fs       	\n"
+		"	mov	%ax, %gs       	\n"
+		"	mov	%ax, %ss       	\n"
+
+		/* Turn off protection (bit 0 in CR0) */
+		"	movl	%cr0, %eax     	\n"
+		"	andl	$0xFFFFFFFE, %eax\n"
+		"	movl	%eax, %cr0     	\n"
+
+		/* Now really going into real mode */
+		"	ljmp	$0, $__vga_ec_real \n"
+		"__vga_ec_real:                  \n"
+
+		/* put the stack at the end of page zero. 
+		 * that way we can easily share it between real and protected, 
+		 * since the 16-bit ESP at segment 0 will work for any case. 
+		/* Setup a stack */
+		"	mov	$0x0, %ax	\n"
+		"	mov	%ax, %ss	\n"
+		"	movl	$0x1000, %eax	\n"
+		"	movl	%eax, %esp	\n"
+
+		/* debugging for RGM */
+		"	mov	$0x11, %al	\n"
+		"	outb	%al, $0x80	\n"
+
+		/* Load our 16 it idt */
+		"	xor	%ax, %ax       	\n"
+		"	mov	%ax, %ds	\n"
+		"	lidt	__myidt		\n"
+
+		/* Dump zeros in the other segregs */
+		"	mov	%ax, %ds	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+
+		/* ask bios to enable main console */
+		/* set up for int 10 call - values found from X server
+		 * bios call routines */
+		"	movw	$0x4f14,%ax	\n"
+		"	movw	$0x8003,%bx	\n"
+		"	movw	$1, %cx		\n"
+		"	movw	$0, %dx		\n"
+		"	movw	$0, %di		\n"
+		"	int	$0x10		\n"
+
+		"	movb	$0x55, %al	\n"
+		"	outb	%al, $0x80	\n"
+
+		/* if we got here, just about done. 
+		 * Need to get back to protected mode */
+		"	movl	%cr0, %eax	\n"
+		"	orl	$0x0000001, %eax\n" /* PE = 1 */
+		"	movl	%eax, %cr0	\n"
+
+		/* Now that we are in protected mode jump to a 32 bit code segment. */
+		"	data32	ljmp	$0x10, $vga_ec_restart\n"
+		"vga_ec_restart:\n"
+		"	.code32\n"
+		"	movw	$0x18, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	%ax, %ss	\n"
+
+		/* restore proper gdt and idt */
+		"	lgdt	%cs:gdtarg 	\n"
+		"	lidt	idtarg		\n"
+		"	.globl	vga__ec_exit	\n"
+		"vga_ec_exit:\n"
+		"	mov	__stack, %esp	\n"
+		"	popal\n"
+		);
+}
+
+void do_vgabios(void)
+{
+	device_t dev;
+	unsigned long busdevfn;
+	unsigned int rom = 0;
+	unsigned char *buf;
+	unsigned int size = 64*1024;
+	int i;
+	
+	/* clear vga bios data area */
+	for (i = 0x400; i < 0x500; i++) {
+		*(unsigned char *) i = 0;
+	}
+
+	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
+
+	if (!dev) {
+		printk_debug("NO VGA FOUND\n");
+		return;
+	}
+	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+
+	/* declare rom address here - keep any config data out of the way
+	 * of core LXB stuff */
+
+	rom = 0xfff80000;
+	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
+	printk_debug("VGA BIOS ROM base address: %x\n", rom);
+
+	buf = (unsigned char *) rom;
+	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
+		memcpy((void *) 0xc0000, buf, size);
+
+		write_protect_vgabios();  // in northbridge
+
+	  	// check signature again
+		buf = (unsigned char *) 0xc0000;
+		if (buf[0]==0x55 && buf[1]==0xAA) {
+			busdevfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
+			printk_debug("bus/devfn = %#x\n", busdevfn);
+
+		    	real_mode_switch_call_vga(busdevfn);
+		} else
+			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+	} else 
+		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+
+	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
+}
+
+
+// we had hoped to avoid this. 
+// this is a stub IDT only. It's main purpose is to ignore calls 
+// to the BIOS. 
+// no longer. Dammit. We have to respond to these.
+struct realidt {
+	unsigned short offset, cs;
+}; 
+
+// from a handy writeup that andrey found.
+
+// handler. 
+// There are some assumptions we can make here. 
+// First, the Top Of Stack (TOS) is located on the top of page zero. 
+// we can share this stack between real and protected mode. 
+// that simplifies a lot of things ...
+// we'll just push all the registers on the stack as longwords, 
+// and pop to protected mode. 
+// second, since this only ever runs as part of coreboot, 
+// we know all the segment register values -- so we don't save any.
+// keep the handler that calls things small. It can do a call to 
+// more complex code in coreboot itself. This helps a lot as we don't
+// have to do address fixup in this little stub, and calls are absolute
+// so the handler is relocatable.
+void handler(void)
+{
+	__asm__ __volatile__ ( 
+		"	.code16		\n"
+		"idthandle:		\n"
+		"	pushal		\n"
+		"	movb 	$0, %al	\n"
+		"	ljmp 	$0, $callbiosint16\n"
+		"end_idthandle:		\n"
+		"	.code32		\n"
+		);
+}
+
+void debughandler(void)
+{
+	__asm__ __volatile__ ( 
+		"	.code16		\n"
+		"debughandle:		\n"
+		"	pushw	%cx	\n"
+		"	movw	$250, %cx \n"
+		"dbh1:			\n"
+		"	loop	dbh1	\n"
+		"	popw	%cx	\n"
+		"	iret		\n"
+		"end_debughandle:	\n"
+		".code32		\n"
+		);
+}
+
+// Calling conventions. The first C function is called with this stuff
+// on the stack. They look like value parameters, but note that if you
+// modify them they will go back to the INTx function modified. 
+// the C function will call the biosint function with these as
+// REFERENCE parameters. In this way, we can easily get 
+// returns back to the INTx caller (i.e. vgabios)
+void callbiosint(void)
+{
+	__asm__ __volatile__ (
+		"	.code16		\n"
+		"callbiosint16:		\n"
+		"	push	%ds	\n"
+		"	push	%es	\n"
+		"	push	%fs	\n"
+		"	push	%gs	\n"
+		// clean up the int #. To save space we put it in the lower
+		// byte. But the top 24 bits are junk. 
+		"	andl	$0xff, %eax\n"
+		// this push does two things:
+		// - put the INT # on the stack as a parameter
+		// - provides us with a temp for the %cr0 mods.
+		"	pushl	%eax	\n"
+		"	movl    %cr0, %eax\n"
+		"	orl	$0x00000001, %eax\n" /* PE = 1 */
+		"	movl	%eax, %cr0\n"
+		/* Now that we are in protected mode jump to a 32 bit code segment. */
+		"	data32  ljmp    $0x10, $biosprotect\n"
+		"biosprotect:		\n"
+		"	.code32		\n"
+		"	movw	$0x18, %ax          \n"
+		"	mov	%ax, %ds          \n"
+		"	mov	%ax, %es          \n"
+		"	mov	%ax, %fs          \n"
+		"	mov	%ax, %gs          \n"
+		"	mov	%ax, %ss          \n"
+		"	lidt	idtarg         \n"
+		"	call	biosint	\n"
+		// back to real mode ...
+		"	ljmp	$0x28, $__rms_16bit2\n"
+		"__rms_16bit2:			\n"
+		"	.code16			\n"
+		/* 16 bit code from here on... */
+		/* Load the segment registers w/ properly configured segment
+		 * descriptors.  They will retain these configurations (limits,
+		 * writability, etc.) once protected mode is turned off. */
+		"	mov	$0x30, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	%ax, %ss	\n"
+		
+		/* Turn off protection (bit 0 in CR0) */
+		"	movl	%cr0, %eax		\n"
+		"	andl	$0xFFFFFFFE, %eax	\n"
+		"	movl	%eax, %cr0		\n"
+
+		/* Now really going into real mode */
+		"	ljmp $0,  $__rms_real2	\n"
+		"__rms_real2:			\n"
+
+		/* Setup a stack
+		 * FixME: where is esp? */
+		"	mov	$0x0, %ax       \n"
+		"	mov	%ax, %ss	\n"
+
+		/* ebugging for RGM */
+		"	mov	$0x11, %al	\n"
+		"	outb	%al, $0x80	\n"
+
+		/* Load our 16 it idt */
+		"	xor	%ax, %ax	\n"
+		"	mov	%ax, %ds	\n"
+		"	lidt	__myidt		\n"
+
+		/* Dump zeros in the other segregs */
+		"	mov	%ax, %es	\n"
+		"	mov	%ax, %fs	\n"
+		"	mov	%ax, %gs	\n"
+		"	mov	$0x40, %ax	\n"
+		"	mov	%ax, %ds	\n"
+
+		/* pop the INT # that you pushed earlier */
+		"	popl	%eax		\n"
+		"	pop	%gs		\n"
+		"	pop	%fs		\n"
+		"	pop	%es		\n"
+		"	pop	%ds		\n"
+		"	popal			\n"
+		"	iret			\n"
+		"	.code32			\n"
+		);
+}
+
+enum {
+	PCIBIOS = 0x1a, 
+	MEMSIZE = 0x12
+};
+
+int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+	    unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+	    unsigned long *pecx, unsigned long *peax, unsigned long *pflags);
+
+int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
+		unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
+		unsigned long *pecx, unsigned long *peax, unsigned long *pflags
+        );
+
+extern void vga_exit(void);
+
+int biosint(unsigned long intnumber,
+	    unsigned long gsfs, unsigned long dses,
+	    unsigned long edi, unsigned long esi,
+	    unsigned long ebp, unsigned long esp, 
+	    unsigned long ebx, unsigned long edx, 
+	    unsigned long ecx, unsigned long eax, 
+	    unsigned long cs_ip, unsigned short stackflags)
+{
+	unsigned long ip; 
+	unsigned long cs; 
+	unsigned long flags;
+	int ret = -1;
+	
+	ip = cs_ip & 0xffff;
+	cs = cs_ip >> 16;
+	flags = stackflags;
+	
+	printk_debug("biosint: INT# 0x%lx\n", intnumber);
+	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+		      eax, ebx, ecx, edx);
+	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+		     ebp, esp, edi, esi);
+	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+		     ip, cs, flags);
+
+	// cases in a good compiler are just as good as your own tables. 
+	switch (intnumber) {
+	case 0 ... 15:
+		// These are not BIOS service, but the CPU-generated exceptions
+		printk_info("biosint: Oops, exception %u\n", intnumber);
+		if (esp < 0x1000) {
+			printk_debug("Stack contents: ");
+			while (esp < 0x1000) {
+				printk_debug("0x%04x ", *(unsigned short *) esp);
+				esp += 2;
+			}
+			printk_debug("\n");
+		}
+		printk_debug("biosint: Bailing out\n");
+		// "longjmp"
+		vga_exit();
+		break;
+		
+	case PCIBIOS:
+		ret = pcibios( &edi, &esi, &ebp, &esp, 
+			       &ebx, &edx, &ecx, &eax, &flags);
+		break;
+	case MEMSIZE: 
+		// who cares. 
+		eax = 64 * 1024;
+		ret = 0;
+		break;
+	case 0x15:
+		ret=handleint21( &edi, &esi, &ebp, &esp, 
+				&ebx, &edx, &ecx, &eax, &flags);
+		break;
+	default:
+		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+			    intnumber);
+		break;
+	}
+	if (ret)
+		flags |= 1; // carry flags
+	else
+		flags &= ~1;
+	stackflags = flags;
+	return ret;
+} 
+
+
+void setup_realmode_idt(void) 
+{
+	extern unsigned char idthandle, end_idthandle;
+	extern unsigned char debughandle, end_debughandle;
+
+	int i;
+	struct realidt *idts = (struct realidt *) 0;
+	int codesize = &end_idthandle - &idthandle;
+	unsigned char *intbyte, *codeptr;
+	
+	// for each int, we create a customized little handler
+	// that just pushes %ax, puts the int # in %al, 
+	// then calls the common interrupt handler. 
+	// this necessitated because intel didn't know much about 
+	// architecture when they did the 8086 (it shows)
+	// (hmm do they know anymore even now :-)
+	// obviously you can see I don't really care about memory 
+	// efficiency. If I did I would probe back through the stack
+	// and get it that way. But that's really disgusting.
+	for (i = 0; i < 256; i++) {
+		idts[i].cs = 0;
+		codeptr = (char*) 4096 + i * codesize;
+		idts[i].offset = (unsigned) codeptr;
+		memcpy(codeptr, &idthandle, codesize);
+		intbyte = codeptr + 3;
+		*intbyte = i;
+	}
+	
+	// fixed entry points
+	
+	// VGA BIOSes tend to hardcode f000:f065 as the previous handler of
+	// int10. 
+	// calling convention here is the same as INTs, we can reuse
+	// the int entry code.
+	codeptr = (char*) 0xff065;
+	memcpy(codeptr, &idthandle, codesize);
+	intbyte = codeptr + 3;
+	*intbyte = 0x42; /* int42 is the relocated int10 */
+
+	/* debug handler - useful to set a programmable delay between instructions if the
+	   TF bit is set upon call to real mode */
+	idts[1].cs = 0;
+	idts[1].offset = 16384;
+	memcpy(16384, &debughandle, &end_debughandle - &debughandle);
+
+	
+}
+
+
+
+enum {
+	CHECK = 0xb001,
+	FINDDEV = 0xb102,
+	READCONFBYTE = 0xb108,
+	READCONFWORD = 0xb109,
+	READCONFDWORD = 0xb10a,
+	WRITECONFBYTE = 0xb10b,
+	WRITECONFWORD = 0xb10c,
+	WRITECONFDWORD = 0xb10d
+};
+
+// errors go in AH. Just set these up so that word assigns
+// will work. KISS. 
+enum {
+	PCIBIOS_NODEV = 0x8600,
+	PCIBIOS_BADREG = 0x8700
+};
+
+int
+pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, 
+	unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, 
+	unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
+{
+	unsigned long edi = *pedi;
+	unsigned long esi = *pesi;
+	unsigned long ebp = *pebp;
+	unsigned long esp = *pesp;
+	unsigned long ebx = *pebx;
+	unsigned long edx = *pedx;
+	unsigned long ecx = *pecx;
+	unsigned long eax = *peax;
+	unsigned long flags = *pflags;
+	unsigned short func = (unsigned short) eax;
+	int retval = 0;
+	unsigned short devid, vendorid, devfn;
+	short devindex; /* Use short to get rid of garbage in upper half of 32-bit register */
+	unsigned char bus;
+	device_t dev;
+	
+	switch(func) {
+	case  CHECK:
+		*pedx = 0x4350;
+		*pecx = 0x2049;
+		retval = 0;
+		break;
+	case FINDDEV:
+	{
+		devid = *pecx;
+		vendorid = *pedx;
+		devindex = *pesi;
+		dev = 0;
+		while ((dev = dev_find_device(vendorid, devid, dev))) {
+			if (devindex <= 0)
+				break;
+			devindex--;
+		}
+		if (dev) {
+			unsigned short busdevfn;
+			*peax = 0;
+			// busnum is an unsigned char;
+			// devfn is an int, so we mask it off. 
+			busdevfn = (dev->bus->secondary << 8)
+				| (dev->path.pci.devfn & 0xff);
+			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			*pebx = busdevfn;
+			retval = 0;
+		} else {
+			*peax = PCIBIOS_NODEV;
+			retval = -1;
+		}
+	}
+	break;
+	case READCONFDWORD:
+	case READCONFWORD:
+	case READCONFBYTE:
+	case WRITECONFDWORD:
+	case WRITECONFWORD:
+	case WRITECONFBYTE:
+	{
+		unsigned long dword;
+		unsigned short word;
+		unsigned char byte;
+		unsigned char reg;
+		
+		devfn = *pebx & 0xff;
+		bus = *pebx >> 8;
+		reg = *pedi;
+		dev = dev_find_slot(bus, devfn);
+		if (! dev) {
+			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
+			*peax = PCIBIOS_BADREG;
+			retval = -1;
+		}
+		switch(func) {
+		case READCONFBYTE:
+			byte = pci_read_config8(dev, reg);
+			*pecx = byte;
+			break;
+		case READCONFWORD:
+			word = pci_read_config16(dev, reg);
+			*pecx = word;
+			break;
+		case READCONFDWORD:
+			dword = pci_read_config32(dev, reg);
+			*pecx = dword;
+			break;
+		case WRITECONFBYTE:
+			byte = *pecx;
+			pci_write_config8(dev, reg, byte);
+			break;
+		case WRITECONFWORD:
+			word = *pecx;
+			pci_write_config16(dev, reg, word);
+			break;
+		case WRITECONFDWORD:
+			dword = *pecx;
+			pci_write_config32(dev, reg, dword);
+			break;
+		}
+		
+		if (retval) 
+			retval = PCIBIOS_BADREG;
+		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+			     func, bus, devfn, reg, *pecx);
+		*peax = 0;
+		retval = 0;
+	}
+	break;
+	default:
+		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		break;
+	}
+	
+	return retval;
+} 
+
+int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
+		unsigned long *esp, unsigned long *ebx, unsigned long *edx,
+		unsigned long *ecx, unsigned long *eax, unsigned long *flags)
+{
+	int res=-1;
+	switch(*eax&0xffff)
+	{
+	case 0x5f19:
+		break;
+	case 0x5f18:
+		*eax=0x5f;
+		*ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
+		*ecx=0x060;
+		res=0;
+		break;
+	case 0x5f00:
+		*eax = 0x8600;
+		break;
+	case 0x5f01:
+		*eax = 0x5f;
+		*ecx = (*ecx & 0xffffff00 ) | 2; // panel type =  2 = 1024 * 768
+		res = 0;
+		break;
+	case 0x5f02:
+		*eax=0x5f;
+		*ebx= (*ebx & 0xffff0000) | 2;
+		*ecx= (*ecx & 0xffff0000) | 0x401;  // PAL + crt only 
+		*edx= (*edx & 0xffff0000) | 0;  // TV Layout - default
+		res=0;
+		break;
+	case 0x5f0f:
+		*eax=0x860f;
+		break;
+	}
+	return res;
+}

Added: trunk/coreboot-v2/src/northbridge/via/cn400/vgachip.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/vgachip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/vgachip.h	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PC80_VGABIOS
+#define _PC80_VGABIOS
+
+extern struct chip_control pc80_vgabios_control;
+
+struct pc80_vgabios_config {
+	int nothing;
+};
+
+void vga_enable_console(void);
+void do_vgabios(void);
+void setup_realmode_idt(void);
+void write_protect_vgabios(void);
+
+#endif /* _PC80_VGABIOS */

Added: trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb
===================================================================
--- trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb	                        (rev 0)
+++ trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,21 @@
+# This will make a target directory of ./VENDOR_MAINBOARD
+
+target VENDOR_MAINBOARD
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option CONFIG_HOSTCC="CROSS_HOSTCC"
+
+__COMPRESSION__
+__LOGLEVEL__
+
+option CONFIG_ROM_SIZE=512*1024
+
+romimage "fallback" 
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option COREBOOT_EXTRA_VERSION=".0-fallback"
+	payload __PAYLOAD__
+end
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

Added: trunk/coreboot-v2/targets/via/epia-n/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/via/epia-n/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/targets/via/epia-n/Config.lb	2009-07-01 10:57:25 UTC (rev 4386)
@@ -0,0 +1,50 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target via_epia_n
+mainboard via/epia-n
+
+option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=10
+option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=10
+option CONFIG_CONSOLE_SERIAL8250=1
+
+# coreboot C code runs at this location in RAM
+option CONFIG_RAMBASE=0x00004000
+
+#
+# Generate the final ROM like this:
+# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
+#
+#option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
+
+romimage "image"
+	option COREBOOT_EXTRA_VERSION = "-epia_n"
+	payload ../../../../../payloads/filo/build/filo.elf
+end
+
+romimage "fallback"
+	option COREBOOT_EXTRA_VERSION = "-epia_n-fallback"
+	payload ../../../../../payloads/filo/build/filo.elf
+end
+
+#buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" "fallback"
+#buildrom ./coreboot.rom CONFIG_FALLBACK_SIZE "image" "fallback"
+buildrom ./coreboot.rom CONFIG_FALLBACK_SIZE "fallback"




From info at coresystems.de  Wed Jul  1 13:18:41 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 13:18:41 +0200
Subject: [coreboot] build service results for r4386
Message-ID: <E1MLxpp-0002Gc-1c@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4386 to
the coreboot repository. This caused the following 
changes:

Change Log:

Ron,

Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.

Patch should work against r4381 (or later ?)

This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)

The coreboot_table issue seems to have been automagically resolved by
the latest core files.

It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.

Signed-off-by: Jon Harrison <bothlyn at blueyonder.co.uk>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4386&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4386&device=epia-m700&vendor=via&num=2
Configuration of via:epia-n is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4386&device=epia-n&vendor=via&num=1


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Jul  1 14:22:26 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 14:22:26 +0200
Subject: [coreboot] [v2] r4387 -
	trunk/coreboot-v2/src/mainboard/via/epia-m700
Message-ID: <mailman.3504.1355071589.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-07-01 14:22:26 +0200 (Wed, 01 Jul 2009)
New Revision: 4387

Modified:
   trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb
Log:
the file was not really different, so use the default file (trivial, since it
didn't build before, and it still doesn't)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb	2009-07-01 10:57:25 UTC (rev 4386)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb	2009-07-01 12:22:26 UTC (rev 4387)
@@ -57,7 +57,7 @@
     end
   end
 end
-mainboardinit cpu/via/16bit/entry16.inc
+mainboardinit cpu/x86/16bit/entry16.inc
 ldscript /cpu/via/16bit/entry16.lds
 
 mainboardinit northbridge/via/vx800/romstrap.inc




From svn at coreboot.org  Wed Jul  1 14:26:12 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 14:26:12 +0200
Subject: [coreboot] [v2] r4388 - trunk/coreboot-v2/util/abuild
Message-ID: <mailman.3505.1355071589.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-07-01 14:26:11 +0200 (Wed, 01 Jul 2009)
New Revision: 4388

Modified:
   trunk/coreboot-v2/util/abuild/abuild
Log:
let abuild autodetect the coreboot path a bit better. So in the top level of
coreboot you can now do:
  $ util/abuild/abuild -t foo/bar
instead of
  $ util/abuild/abuild -t foo/bar $PWD

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/util/abuild/abuild
===================================================================
--- trunk/coreboot-v2/util/abuild/abuild	2009-07-01 12:22:26 UTC (rev 4387)
+++ trunk/coreboot-v2/util/abuild/abuild	2009-07-01 12:26:11 UTC (rev 4388)
@@ -603,9 +603,12 @@
 # default options
 target=""
 buildall=false
-LBROOT=$( cd ../..; pwd )
 verbose=false
 
+test -f util/newconfig/config.g && LBROOT=$( pwd )
+test -f ../util/newconfig/config.g && LBROOT=$( cd ..; pwd )
+test "$LBROOT" = "" && LBROOT=$( cd ../..; pwd )
+
 # parse parameters.. try to find out whether we're running GNU getopt
 getoptbrand="`getopt -V`"
 if [ "${getoptbrand:0:6}" == "getopt" ]; then




From info at coresystems.de  Wed Jul  1 14:42:59 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 14:42:59 +0200
Subject: [coreboot] build service results for r4387
Message-ID: <E1MLz9P-0007Hw-4K@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4387 to
the coreboot repository. This caused the following 
changes:

Change Log:
the file was not really different, so use the default file (trivial, since it
didn't build before, and it still doesn't)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4387&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4387&device=epia-m700&vendor=via&num=2
Configuration of via:epia-n is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4387&device=epia-n&vendor=via&num=1


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Wed Jul  1 15:07:12 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 15:07:12 +0200
Subject: [coreboot] build service results for r4388
Message-ID: <E1MLzWq-0007Tz-Ue@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4388 to
the coreboot repository. This caused the following 
changes:

Change Log:
let abuild autodetect the coreboot path a bit better. So in the top level of
coreboot you can now do:
  $ util/abuild/abuild -t foo/bar
instead of
  $ util/abuild/abuild -t foo/bar $PWD

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4388&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4388&device=epia-m700&vendor=via&num=2
Configuration of via:epia-n is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4388&device=epia-n&vendor=via&num=1


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Jul  1 15:19:26 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 15:19:26 +0200
Subject: [coreboot] [v2] r4389 - in trunk/coreboot-v2/src: include/device
	mainboard/via/epia-n southbridge/via/vt8237r
Message-ID: <mailman.3506.1355071589.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-07-01 15:19:25 +0200 (Wed, 01 Jul 2009)
New Revision: 4389

Modified:
   trunk/coreboot-v2/src/include/device/pci_ids.h
   trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
Log:
I missed three files. 
Signed-off-by: Jon Harrison <bothlyn at blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/coreboot-v2/src/include/device/pci_ids.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-01 12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-01 13:19:25 UTC (rev 4389)
@@ -1198,6 +1198,14 @@
 #define PCI_DEVICE_ID_VIA_CN700_VLINK	0x7314
 #define PCI_DEVICE_ID_VIA_CN700_BRIDGE	0xB198
 #define PCI_DEVICE_ID_VIA_CN700_VGA	0x3344
+#define PCI_DEVICE_ID_VIA_CN400_AGP	0x0259
+#define PCI_DEVICE_ID_VIA_CN400_ERR	0x1259
+#define PCI_DEVICE_ID_VIA_CN400_HOST	0x2259
+#define PCI_DEVICE_ID_VIA_CN400_MEMCTRL	0x3259
+#define PCI_DEVICE_ID_VIA_CN400_PM	0x4259
+#define PCI_DEVICE_ID_VIA_CN400_VLINK	0x7259
+#define PCI_DEVICE_ID_VIA_CN400_BRIDGE	0xB198
+#define PCI_DEVICE_ID_VIA_CN400_VGA	0x3118
 
 #define PCI_VENDOR_ID_SIEMENS           0x110A
 #define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102

Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	2009-07-01 12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	2009-07-01 13:19:25 UTC (rev 4389)
@@ -58,7 +58,7 @@
 uses CONFIG_HAVE_ACPI_RESUME
 uses CONFIG_CROSS_COMPILE
 uses CC
-uses CONFIG_HOSTCC
+uses HOSTCC
 uses CONFIG_OBJCOPY
 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
@@ -108,7 +108,7 @@
 default CONFIG_ROM_PAYLOAD = 1
 default CONFIG_CROSS_COMPILE = ""
 default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default CONFIG_HOSTCC = "gcc"
+default HOSTCC = "gcc"
 #default CONFIG_MAINBOARD = "EPIA-N"
 
 ##

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2009-07-01 12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2009-07-01 13:19:25 UTC (rev 4389)
@@ -91,7 +91,7 @@
 
 	/* All delivered to CPU0. */
 	ioapic_table[0].value_high = (lapicid()) << (56 - 32);
-	l = (unsigned long *)ioapic_base;
+	l = (u32 *)ioapic_base;
 
 	/* Set APIC to FSB message bus. */
 	l[0] = 0x3;
@@ -243,26 +243,56 @@
 {
 	u8 enables;
 
+	printk_spew("Entering vt8237r_init.\n");
+	
+#ifdef CONFIG_EPIA_VT8237R_INIT
+	printk_spew("vt8237r_init SATA LED.\n");
 	/*
+	 * TODO: Looks like stock BIOS can do this but causes a hang
 	 * Enable SATA LED, disable special CPU Frequency Change -
 	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 * Setup to match EPIA default
+	 * PCS0# on Pin U1
 	 */
-	pci_write_config8(dev, 0xe5, 0x9);
+	enables = pci_read_config8(dev, 0xe5);
+	enables |= 0x02;
+	pci_write_config8(dev, 0xe5, enables);
+	
+	printk_spew("vt8237r_init PCI Req.\n");
+	/* 
+	 * Enable Flash Write Access. 
+	 * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
+	 */
+	enables = pci_read_config8(dev, 0xe4);
+	enables |= 0x2B;
+	pci_write_config8(dev, 0xe4, enables);
 
+#else 
+	/*
+	 * Enable SATA LED, disable special CPU Frequency Change -
+	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 */
+	pci_write_config8(dev, 0xe5, 0x09);
+	
 	/* REQ5 as PCI request input - should be together with INTE-INTH. */
 	pci_write_config8(dev, 0xe4, 0x4);
+#endif
 
+
+	printk_spew("vt8237r_init CPU Rst.\n");
 	/* Set bit 3 of 0x4f (use INIT# as CPU reset). */
 	enables = pci_read_config8(dev, 0x4f);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4f, enables);
 
+	printk_spew("vt8237r_init Read Pass Write Ctrl.\n");
 	/*
 	 * Set Read Pass Write Control Enable
 	 * (force A2 from APIC FSB to low).
 	 */
 	pci_write_config8(dev, 0x48, 0x8c);
 
+	printk_spew("vt8237r_init calling southbridge_init_common.\n");
 	southbridge_init_common(dev);
 
 	/* FIXME: Intel needs more bit set for C2/C3. */
@@ -272,6 +302,8 @@
 	 * Will work for C3 and for FID/VID change.
 	 */
 	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+	
+	printk_spew("Leaving vt8237r_init.\n");
 }
 
 static void vt8237s_init(struct device *dev)




From rminnich at gmail.com  Wed Jul  1 15:20:47 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Jul 2009 06:20:47 -0700
Subject: [coreboot] C3/CN400 Support - coreboot_tables
In-Reply-To: <8E520A5E7FB8D647BFDA039F6031C1C6057276DD@desmdswms201.des.grplnk.net>
References: <mailman.62.1246371138.8743.coreboot@coreboot.org>
	<8E520A5E7FB8D647BFDA039F6031C1C6057276DD@desmdswms201.des.grplnk.net>
Message-ID: <13426df10907010620p594535s442bfccb5edf6fea@mail.gmail.com>

Jon's support code is now in the upstream.

Thanks Jon!

ron



From rminnich at gmail.com  Wed Jul  1 15:22:05 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 1 Jul 2009 06:22:05 -0700
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <20090701024044.GA25070@morn.localdomain>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906231327u7d36e1f7t840fc5cdde67dfba@mail.gmail.com>
	<23a460760906231418l596e2a3cm3d61953c2b12db6b@mail.gmail.com>
	<8B53F3255BEE44A896F998A7405BA0E6@chimp>
	<23a460760906240534s2b6b20f3w58b2bcdc7bdd1019@mail.gmail.com>
	<20090626182130.GA30895@morn.localdomain>
	<23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
	<20090630234008.GA22496@morn.localdomain>
	<03E0EFDE09E54A48882815F04D43D762@chimp>
	<20090701024044.GA25070@morn.localdomain>
Message-ID: <13426df10907010622v5ed50edbi24a1116e82de0d7e@mail.gmail.com>

On Tue, Jun 30, 2009 at 7:40 PM, Kevin O'Connor<kevin at koconnor.net> wrote:

> I would think coreboot should always configure the legacy PCI bridge
> bits and CONSOLE_VGA should just control whether or not coreboot tries
> to write to the screen. ?(Or, if there is a reason to not configure
> the pci ranges, then make it a separate config item.)

It probably needs to be a config item then.

ron



From thomas.jourdan at gmail.com  Wed Jul  1 15:31:14 2009
From: thomas.jourdan at gmail.com (Thomas JOURDAN)
Date: Wed, 1 Jul 2009 15:31:14 +0200
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <D6079DC63DA74FBBBDD0FA295B0AB877@chimp>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906291447w375f39e9gdffde44ef8b0b769@mail.gmail.com>
	<23a460760906300006s6a2ee8caqfbb54c0c5fec5a14@mail.gmail.com>
	<D6079DC63DA74FBBBDD0FA295B0AB877@chimp>
Message-ID: <23a460760907010631k729aed59ya169a786706fd3ff@mail.gmail.com>

Hi Myles, all

> ?Could you send me the corrected Config.lb now that you removed the disabled devices?

Here it is. As I said the audio and modem devices are disabled early
so they won't be present and won't be enumerated despite the function
exists in the i3100. Anyway, no internal connectors are present on the
board for audio or modem.

Thomas
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From info at coresystems.de  Wed Jul  1 15:40:16 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 15:40:16 +0200
Subject: [coreboot] build service results for r4389
Message-ID: <E1MM02q-0000KX-27@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4389 to
the coreboot repository. This caused the following 
changes:

Change Log:
I missed three files.
Signed-off-by: Jon Harrison <bothlyn at blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4389&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4389&device=epia-m700&vendor=via&num=2
Configuration of via:epia-n is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4389&device=epia-n&vendor=via&num=1


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From thomas.jourdan at gmail.com  Wed Jul  1 16:02:20 2009
From: thomas.jourdan at gmail.com (Thomas JOURDAN)
Date: Wed, 1 Jul 2009 16:02:20 +0200
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <A1C2FDA80DF24CFAB3F9AB449D8F26D1@chimp>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906291447w375f39e9gdffde44ef8b0b769@mail.gmail.com>
	<23a460760906300006s6a2ee8caqfbb54c0c5fec5a14@mail.gmail.com>
	<A1C2FDA80DF24CFAB3F9AB449D8F26D1@chimp>
Message-ID: <23a460760907010702v4e3f8bsb8df9ac717db50e5@mail.gmail.com>

Hi Myles, guys

> Could you send the copyright line for your work? ?You made several
> non-trivial additions. ?I'll add it to the files for you.
Is it mandatory ? A coreboot copyright is fine to me. If you need one,
we can put :

Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>

Regards,
Thomas



From mylesgw at gmail.com  Wed Jul  1 16:22:35 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 1 Jul 2009 08:22:35 -0600
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <13426df10907010622v5ed50edbi24a1116e82de0d7e@mail.gmail.com>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906231327u7d36e1f7t840fc5cdde67dfba@mail.gmail.com>
	<23a460760906231418l596e2a3cm3d61953c2b12db6b@mail.gmail.com>
	<8B53F3255BEE44A896F998A7405BA0E6@chimp>
	<23a460760906240534s2b6b20f3w58b2bcdc7bdd1019@mail.gmail.com>
	<20090626182130.GA30895@morn.localdomain>
	<23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
	<20090630234008.GA22496@morn.localdomain>
	<03E0EFDE09E54A48882815F04D43D762@chimp>
	<20090701024044.GA25070@morn.localdomain>
	<13426df10907010622v5ed50edbi24a1116e82de0d7e@mail.gmail.com>
Message-ID: <53E9375E372D4F318F740294EBA8F512@chimp>



> -----Original Message-----
> From: ron minnich [mailto:rminnich at gmail.com]
> On Tue, Jun 30, 2009 at 7:40 PM, Kevin O'Connor<kevin at koconnor.net> wrote:
> > I would think coreboot should always configure the legacy PCI bridge
> > bits and CONSOLE_VGA should just control whether or not coreboot tries
> > to write to the screen. ?(Or, if there is a reason to not configure
> > the pci ranges, then make it a separate config item.)
> 
> It probably needs to be a config item then.

If Coreboot never writes to the console, that fixes it too.  I think that
was Stefan's preferred solution.  I think he's right that most of the time
the VGA console is useless for debugging.  All the tricky things happen
before that's available.

Thanks,
Myles




From jon.harrison at selexgalileo.com  Wed Jul  1 16:24:45 2009
From: jon.harrison at selexgalileo.com (Harrison, Jon (SELEX GALILEO, UK))
Date: Wed, 1 Jul 2009 15:24:45 +0100
Subject: [coreboot] R4389 Adds EPIA-N(L) C3/CN400 Support - Developer Notes
Message-ID: <8E520A5E7FB8D647BFDA039F6031C1C60578A20D@desmdswms201.des.grplnk.net>

Dear Corebooters !

R4389 has added initial support for Via C3/CN400/VT8237R based EPIA
boards.

This should cover EPIA-N, EPIA-NL and also some of the low end EPIA-SP
boards.

The build has been tested on a Via EPIA-NL 8000 fitted with 1GB DDR400
SDRAM.

Current notes for the build for anyone seeking to develop further are as
follows::

1/ You need the VGA BIOS from factory BIOS and BOCHS to support the VGA
init, as described in the EPIA-M/II HOWTO.

2/ ACPI is completely untested

3/ At this point the build does not actually get through the payload
launch stage (may be a coreboot tables issue)

The spew level output is attached, for reference for what to expect if
you're working with epia-n.

I'm working now to get FILO launching and then get ACPI working.

Thanks,
Jon




SELEX Sensors and Airborne Systems Limited
Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL
A company registered in England & Wales.  Company no. 02426132
********************************************************************
This email and any attachments are confidential to the intended
recipient and may also be privileged. If you are not the intended
recipient please delete it from your system and notify the sender.
You should not copy it or use it for any purpose nor disclose or
distribute its contents to any other person.
********************************************************************
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From svn at coreboot.org  Wed Jul  1 17:08:19 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 17:08:19 +0200
Subject: [coreboot] [v2] r4390 - trunk/coreboot-v2/targets/via/epia-n
Message-ID: <mailman.3507.1355071589.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-07-01 17:08:19 +0200 (Wed, 01 Jul 2009)
New Revision: 4390

Modified:
   trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb
Log:
Fix abuild for via/epia-n.  Trivial.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb
===================================================================
--- trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb	2009-07-01 13:19:25 UTC (rev 4389)
+++ trunk/coreboot-v2/targets/via/epia-n/Config-abuild.lb	2009-07-01 15:08:19 UTC (rev 4390)
@@ -5,7 +5,7 @@
 
 option CC="CROSSCC"
 option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option CONFIG_HOSTCC="CROSS_HOSTCC"
+option HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 __LOGLEVEL__




From info at coresystems.de  Wed Jul  1 17:29:35 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 17:29:35 +0200
Subject: [coreboot] build service results for r4390
Message-ID: <E1MM1kd-0006YM-SU@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4390 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix abuild for via/epia-n.  Trivial.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4390&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4390&device=epia-m700&vendor=via&num=2
Configuration of via:epia-n has been fixed


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Jul  1 18:34:03 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 18:34:03 +0200
Subject: [coreboot] [v2] r4391 - trunk/coreboot-v2/src/cpu/intel/model_6fx
Message-ID: <mailman.3508.1355071589.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-07-01 18:34:03 +0200 (Wed, 01 Jul 2009)
New Revision: 4391

Modified:
   trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c
Log:
Fix typo and only output post code if the work was done.

Thanks to Thomas Jourdan <thomas.jourdan at gmail.com> for reporting it.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c	2009-07-01 15:08:19 UTC (rev 4390)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c	2009-07-01 16:34:03 UTC (rev 4391)
@@ -50,9 +50,9 @@
 	"wrmsr\n"
 	"movl	$MTRRphysMask_MSR(1), %ecx\n"
 	"wrmsr\n"
-#endif
 
 	"movb	$0x33, %al\noutb %al, $0x80\n"
+#endif
 #ifdef CLEAR_FIRST_1M_RAM
 	"movb	$0x34, %al\noutb %al, $0x80\n"
 	/* Enable Write Combining and Speculative Reads for the first 1MB */
@@ -120,7 +120,7 @@
 	"movb	$0x3b, %al\noutb %al, $0x80\n"
 
 	/* Enable prefetchers */
-	"movl	$0x01a0, %eax\n"
+	"movl	$0x01a0, %ecx\n"
 	"rdmsr\n"
 	"andl	$~((1 << 9) | (1 << 19)), %eax\n"
 	"andl	$~((1 << 5) | (1 << 7)), %edx\n"




From mylesgw at gmail.com  Wed Jul  1 18:34:56 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 1 Jul 2009 10:34:56 -0600
Subject: [coreboot] Bug in cache_as_ram.inc and cache_as_ram_post.c
In-Reply-To: <1227903381.7278.12.camel@desktop.maison.net>
References: <1227903381.7278.12.camel@desktop.maison.net>
Message-ID: <2831fecf0907010934m36acfbe5rac73d07814e50eb3@mail.gmail.com>

On Fri, Nov 28, 2008 at 2:16 PM, Thomas Jourdan <tjourdan at neuf.fr> wrote:

> Hi guys
>
> I don't know how usefull is it but there is a bug in cache_as_ram.inc
> and cache_as_ram_post.c for the 6fx intel processors. The code disable /
> enable the prefetcher in IA32_MISC_ENABLES MSR register.


Rev 4391.  Sorry it took so long.

Thanks,
Myles
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From info at coresystems.de  Wed Jul  1 18:56:58 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 18:56:58 +0200
Subject: [coreboot] build service results for r4391
Message-ID: <E1MM37C-0004kF-R6@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4391 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix typo and only output post code if the work was done.

Thanks to Thomas Jourdan <thomas.jourdan at gmail.com> for reporting it.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4391&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4391&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Jul  1 19:01:17 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  1 Jul 2009 19:01:17 +0200
Subject: [coreboot] [v2] r4392 - in trunk/coreboot-v2: src/cpu/intel
	src/cpu/intel/bga956 src/cpu/intel/model_1067x
	src/include/device src/mainboard/intel
	src/mainboard/intel/eagleheights src/northbridge/intel/i3100
	src/southbridge/intel/i3100 src/superio/smsc/smscsuperio
	targets/intel targets/intel/eagleheights
Message-ID: <mailman.3509.1355071589.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-07-01 19:01:17 +0200 (Wed, 01 Jul 2009)
New Revision: 4392

Added:
   trunk/coreboot-v2/src/cpu/intel/bga956/
   trunk/coreboot-v2/src/cpu/intel/bga956/Config.lb
   trunk/coreboot-v2/src/cpu/intel/bga956/bga956.c
   trunk/coreboot-v2/src/cpu/intel/bga956/chip.h
   trunk/coreboot-v2/src/cpu/intel/model_1067x/
   trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb
   trunk/coreboot-v2/src/cpu/intel/model_1067x/model_1067x_init.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/chip.h
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/cmos.layout
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/debug.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/dsdt.dsl
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/fadt.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/ioapic.h
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/irq_tables.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/mainboard.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/mptable.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/power_reset_check.c
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/reset.c
   trunk/coreboot-v2/src/northbridge/intel/i3100/reset_test.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/cmos_failover.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_pciexp_portb.c
   trunk/coreboot-v2/targets/intel/eagleheights/
   trunk/coreboot-v2/targets/intel/eagleheights/Config.lb
Modified:
   trunk/coreboot-v2/src/include/device/pci_ids.h
   trunk/coreboot-v2/src/northbridge/intel/i3100/i3100.h
   trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/Config.lb
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c
   trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c
Log:
Add support for the Intel Eagle Heights development board.

Signed-off-by: Thomas Jourdan <thomas.jourdan at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Added: trunk/coreboot-v2/src/cpu/intel/bga956/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/bga956/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/bga956/Config.lb	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,3 @@
+config chip.h
+object bga956.o
+dir /cpu/intel/model_1067x

Added: trunk/coreboot-v2/src/cpu/intel/bga956/bga956.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/bga956/bga956.c	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/bga956/bga956.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_bga956_ops = {
+	CHIP_NAME("BGA956 CPU")
+};

Added: trunk/coreboot-v2/src/cpu/intel/bga956/chip.h
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/bga956/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/bga956/chip.h	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_bga956_ops;
+
+struct cpu_intel_bga956_config {
+};

Copied: trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb (from rev 4389, trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb)
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,14 @@
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
+
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/x86/smm
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+driver model_1067x_init.o


Property changes on: trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/cpu/intel/model_1067x/model_1067x_init.c (from rev 4379, trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c)
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_1067x/model_1067x_init.c	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_1067x/model_1067x_init.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,265 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static const uint32_t microcode_updates[] = {
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+static inline void strcpy(char *dst, char *src) 
+{
+	while (*src) *dst++ = *src++;
+}
+
+static void init_timer(void)
+{
+	/* Set the apic timer to no interrupts and periodic mode */
+	lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
+
+	/* Set the divider to 1, no divider */
+	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
+
+	/* Set the initial counter to 0xffffffff */
+	lapic_write(LAPIC_TMICT, 0xffffffff);
+}
+
+static void fill_processor_name(char *processor_name)
+{
+	struct cpuid_result regs;
+	char temp_processor_name[49];
+	char *processor_name_start;
+	unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+	int i;
+
+	for (i=0; i<3; i++) {
+		regs = cpuid(0x80000002 + i);
+		name_as_ints[i*4 + 0] = regs.eax;
+		name_as_ints[i*4 + 1] = regs.ebx;
+		name_as_ints[i*4 + 2] = regs.ecx;
+		name_as_ints[i*4 + 3] = regs.edx;
+	}
+
+	temp_processor_name[48] = 0;
+
+	/* Skip leading spaces */
+	processor_name_start = temp_processor_name;
+	while (*processor_name_start == ' ') 
+		processor_name_start++;
+
+	memset(processor_name, 0, 49);
+	strcpy(processor_name, processor_name_start);
+}
+
+#define IA32_FEATURE_CONTROL 0x003a
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+static void enable_vmx(void)
+{
+	struct cpuid_result regs;
+	msr_t msr;
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		/* VMX locked. If we set it again we get an illegal
+		 * instruction
+		 */
+		return;
+	}
+
+	regs = cpuid(1);
+	if (regs.ecx & CPUID_VMX) {
+		msr.lo |= (1 << 2);
+		if (regs.ecx & CPUID_SMX)
+			msr.lo |= (1 << 1);
+	}
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+
+	msr.lo |= (1 << 0); /* Set lock bit */
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+#define PMG_CST_CONFIG_CONTROL	0xe2
+#define PMG_IO_BASE_ADDR	0xe3
+#define PMG_IO_CAPTURE_ADDR	0xe4
+
+#define PMB0_BASE		0x580
+#define PMB1_BASE		0x800
+#define CST_RANGE		2
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+
+	msr.lo |= (1 << 15); // config lock until next reset
+	msr.lo |= (1 << 14); // Deeper Sleep
+	msr.lo |= (1 << 10); // Enable IO MWAIT redirection
+	msr.lo &= ~(1 << 9); // Issue a  single stop grant cycle upon stpclk
+	msr.lo |= (1 << 3); // Dynamic L2
+
+	wrmsr(PMG_CST_CONFIG_CONTROL, msr);
+
+	/* Set Processor MWAIT IO BASE */
+	msr.hi = 0;
+	msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
+	wrmsr(PMG_IO_BASE_ADDR, msr);
+
+	/* Set IO Capture Address */
+	msr.hi = 0;
+	msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16);
+	wrmsr(PMG_IO_CAPTURE_ADDR, msr);
+}
+
+#define IA32_MISC_ENABLE	0x1a0
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 3); 	/* TM1 enable */
+	msr.lo |= (1 << 13);	/* TM2 enable */
+	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
+
+	msr.lo |= (1 << 10);	/* FERR# multiplexing */
+
+	// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
+	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+
+	/* Enable C2E */
+	msr.lo |= (1 << 26);
+
+	/* Enable C4E */
+	/* TODO This should only be done on mobile CPUs, see cpuid 5 */
+	msr.hi |= (1 << (32 - 32)); // C4E
+	msr.hi |= (1 << (33 - 32)); // Hard C4E
+
+	/* Enable EMTTM. */
+	/* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */
+	msr.hi |= (1 << (36 - 32));
+
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+#define PIC_SENS_CFG	0x1aa
+static void configure_pic_thermal_sensors(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(PIC_SENS_CFG);
+
+	msr.lo |= (1 << 21); // inter-core lock TM1
+	msr.lo |= (1 << 4); // Enable bypass filter
+
+	wrmsr(PIC_SENS_CFG, msr);
+}
+
+#if CONFIG_USBDEBUG_DIRECT
+static unsigned ehci_debug_addr;
+#endif
+		
+static void model_1067x_init(device_t cpu)
+{
+	char processor_name[49];
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk_info("CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG_DIRECT
+	// Is this caution really needed?
+	if(!ehci_debug_addr) 
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs */
+	x86_setup_mtrrs(36);
+	x86_mtrr_check();
+
+#if CONFIG_USBDEBUG_DIRECT
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+	/* Initialize the APIC timer */
+	init_timer();
+
+	/* Enable virtualization */
+	enable_vmx();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* PIC thermal sensor control */
+	configure_pic_thermal_sensors();
+
+	/* Start up my cpu siblings */
+	intel_sibling_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_1067x_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
+


Property changes on: trunk/coreboot-v2/src/cpu/intel/model_1067x/model_1067x_init.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Modified: trunk/coreboot-v2/src/include/device/pci_ids.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-01 16:34:03 UTC (rev 4391)
+++ trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-01 17:01:17 UTC (rev 4392)
@@ -2395,6 +2395,10 @@
 #define PCI_DEVICE_ID_INTEL_3100_MC     0x35b0
 #define PCI_DEVICE_ID_INTEL_3100_PCIE_PA0 0x35b6
 #define PCI_DEVICE_ID_INTEL_3100_PCIE_PA1 0x35b7
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB0 0x2690
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB1 0x2692
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB2 0x2694
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB3 0x2696
 
 /* Intel EP80579 */
 #define PCI_DEVICE_ID_INTEL_EP80579_LPC    0x5031

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,211 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+##
+## Only use the option table in a normal image
+##
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+
+if CONFIG_HAVE_ACPI_TABLES
+	object fadt.o
+	object acpi_tables.o
+	makerule dsdt.c
+		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
+		action  "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
+		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
+	end
+	object ./dsdt.o
+end
+
+object reset.o
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+
+else
+
+makerule ./auto.inc
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
+	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+end
+
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+if CONFIG_USE_INIT
+	ldscript /cpu/x86/32bit/entry32.lds
+	ldscript /cpu/x86/car/cache_as_ram.lds
+end
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/reset16.inc
+        ldscript /cpu/x86/16bit/reset16.lds
+else
+        mainboardinit cpu/x86/32bit/reset32.inc
+        ldscript /cpu/x86/32bit/reset32.lds
+end
+
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/intel/model_6fx/cache_as_ram.inc
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i3100
+        device pci_domain 0 on
+                device pci 00.0 on end # IMCH
+                device pci 00.1 on end # IMCH error status
+                device pci 01.0 on end # IMCH EDMA engine
+                device pci 02.0 on end # PCIe port A/A0
+                device pci 03.0 on end # PCIe port A1
+                chip southbridge/intel/i3100
+                        # PIRQ line -> legacy IRQ mappings
+			register "pirq_a_d" = "0x8b808a8a"
+                        register "pirq_e_h" = "0x85808080"
+
+                        device pci 1c.0 on end # PCIe port B0
+                        device pci 1c.1 off end # PCIe port B1
+                        device pci 1c.2 off end # PCIe port B2
+                        device pci 1c.3 off end # PCIe port B3
+                        device pci 1d.0 on end # USB (UHCI) 1
+                        device pci 1d.1 on end # USB (UHCI) 2
+                        device pci 1d.7 on end # USB (EHCI)
+                        device pci 1e.0 on end # PCI bridge
+                        device pci 1f.0 on     # LPC bridge
+                                chip superio/intel/i3100
+                                        device pnp 4e.4 on # Com1
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 4e.5 on # Com2
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+                                        end
+                                end
+				chip superio/smsc/smscsuperio
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.2 off	# Serial Port 4
+						io 0x60 = 0x2e8
+						irq 0x70 = 3
+					end
+					device pnp 2e.3 on	# Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 2
+					end
+					device pnp 2e.4 off	# Serial Port 3
+						io 0x60 = 0x3e8
+						irq 0x70 = 4
+					end
+					device pnp 2e.7 on	# PS/2 Keyboard / Mouse
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1    # PS/2 keyboard interrupt
+						irq 0x72 = 12   # PS/2 mouse interrupt
+					end
+					device pnp 2e.a off     # Runtime registers
+					       io 0x60 = 0x600
+					end
+				end
+                        end
+                        device pci 1f.2 on end # SATA
+                        device pci 1f.3 on end # SMBus
+			device pci 1f.4 on end # Performance counters
+                end
+        end
+        device apic_cluster 0 on
+                chip cpu/intel/bga956
+                        device apic 0 on end
+                end
+        end
+end
+


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,331 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+# Tables
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
+# SMP
+uses CONFIG_SMP
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_AP_IN_SIPI_WAIT
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+# Image Size
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+# Payload
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+uses CONFIG_PAYLOAD_SIZE
+# Build Internals
+uses CONFIG_RAMBASE
+uses CONFIG_ROMBASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_SMI_HANDLER
+uses CONFIG_PCIE_CONFIGSPACE_HOLE
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_MMCONF_BASE_ADDRESS
+uses CONFIG_CBFS
+#
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+# Timers
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+# Console
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_VGA_ROM_RUN
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_DEBUG
+uses CONFIG_VGA
+uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
+# Toolchain
+uses CC
+uses HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
+# Tweaks
+uses CONFIG_GDB_STUB
+uses CONFIG_MAX_REBOOT_CNT
+uses CONFIG_USE_WATCHDOG_ON_BOOT
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+
+###
+### Build options
+###
+
+##
+##
+default CONFIG_MAX_REBOOT_CNT=3
+
+##
+## Use the watchdog to break out of a lockup condition
+##
+default CONFIG_USE_WATCHDOG_ON_BOOT=0
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default CONFIG_ROM_SIZE=1024*1024
+
+
+##
+## Build code for the fallback boot
+##
+default CONFIG_HAVE_FALLBACK_BOOT=1
+
+##
+## Delay timer options
+## Use timer2
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to reset the motherboard from coreboot
+##
+default CONFIG_HAVE_HARD_RESET=1
+
+##
+## Build SMI handler
+##
+default CONFIG_HAVE_SMI_HANDLER=0
+
+##
+## Leave a hole for mmapped PCIe config space
+##
+default CONFIG_PCIE_CONFIGSPACE_HOLE=1
+default CONFIG_MMCONF_SUPPORT=1
+default CONFIG_MMCONF_BASE_ADDRESS=0xE0000000
+
+##
+## Build code to export a programmable irq routing table
+##
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=18
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default CONFIG_HAVE_MP_TABLE=1
+
+##
+## Build code to provide ACPI support
+##
+default CONFIG_HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
+
+##
+## Build code to export a CMOS option table
+##
+default CONFIG_HAVE_OPTION_TABLE=1
+
+##
+## Move the default coreboot cmos range off of AMD RTC registers
+##
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=0
+# There are some network option roms that don't work with
+# coreboot's x86emu. Thus, we only execute the VGA option rom
+# for now:
+default CONFIG_VGA_ROM_RUN=0
+default CONFIG_PCI_ROM_RUN=0
+default CONFIG_DEBUG=0
+
+#default CONFIG_VGA=0
+#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+default CONFIG_AP_IN_SIPI_WAIT=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default CONFIG_MAINBOARD_PART_NUMBER="EagleHeights"
+default CONFIG_MAINBOARD_VENDOR=     "Intel"
+
+###
+### coreboot layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default CONFIG_STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default CONFIG_HEAP_SIZE=0x8000
+
+
+###
+### Compute the location and size of where this firmware image
+### (coreboot plus bootloader) will live in the boot rom chip.
+###
+default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+
+##
+## coreboot C code runs at this location in RAM
+##
+default CONFIG_RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD=1
+default CONFIG_PRECOMPRESSED_PAYLOAD=1
+default CONFIG_COMPRESSED_PAYLOAD_LZMA=1
+#default CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
+
+# Select the serial console base port
+default CONFIG_TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default CONFIG_TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
+
+## Request this level of debugging output
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
+## At a maximum only compile in this level of debugging
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
+
+##
+## Select power on after power fail setting
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+#
+# CBFS
+#
+default CONFIG_CBFS=1
+
+### End Options.lb
+end


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/acpi_tables.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/acpi_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/acpi_tables.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,227 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "ioapic.h"
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	u64 mmcfg;
+
+	dev = dev_find_device(0x8086, 0x35B0, 0);	// 0:0x13.0
+	if (!dev)
+		return current;
+
+	// MMCFG not supported or not enabled.
+	mmcfg = ((u64) pci_read_config16(dev, 0xce)) << 16;
+	if (!mmcfg)
+		return current;
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+			mmcfg, 0x0, 0x0, 0xff);
+
+	return current;
+}
+
+void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header = &(hpet->header);
+	acpi_addr_t *addr = &(hpet->addr);
+
+	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, HPET_NAME, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "IC      ", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	// XXX factory bios just puts an address here -- who's right?
+	addr->space_id = 0;	/* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = HPET_ADDR & 0xffffffff;
+	addr->addrh = HPET_ADDR >> 32;
+
+	hpet->id = 0x80861234;
+	hpet->number = 0x00;
+	hpet->min_tick = 0x0090;
+
+	header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+#define IO_APIC0 2
+#define IO_APIC1 3
+#define IO_APIC0_ADDR	0xfec00000UL
+#define IO_APIC1_ADDR	0xfec10000UL
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	unsigned int irq_start = 0;
+	device_t dev = 0;
+	struct resource* res = NULL;
+	unsigned char bus_isa;
+
+	/* Local Apic */
+	current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0);
+	// This one is for the second core... Will it hurt?
+	current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC0_ADDR, irq_start);
+	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC1_ADDR, irq_start);
+	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+	dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
+
+	if (dev) {
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+	} else {
+		printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+		bus_isa = 7;
+	}
+
+	/* Map ISA IRQ 0 to IRQ 2 */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, bus_isa, 0, 2, 0);
+
+	/* IRQ9 differs from ISA standard - ours is active high, level-triggered */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d);
+
+	return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk_info("ACPI: Writing ACPI tables at %lx.\n", current);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk_debug("ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdt, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk_debug("ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdt, madt);
+
+	printk_debug("ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdt, mcfg);
+
+	printk_debug("ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	current += ((acpi_header_t *) AmlCode)->length;
+	ALIGN_CURRENT;
+	memcpy((void *) dsdt, (void *) AmlCode,
+	       ((acpi_header_t *) AmlCode)->length);
+
+	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+	printk_debug("ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdt, fadt);
+
+	printk_info("ACPI: done.\n");
+	return current;
+}


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/acpi_tables.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define __ROMCC__
+
+#include <delay.h>
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include <cpu/x86/bist.h>
+
+#include "ram/ramtest.c"
+#include "southbridge/intel/i3100/i3100_early_smbus.c"
+#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "reset.c"
+#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#define SIO_GPIO_BASE 0x680
+#define SIO_XBUS_BASE 0x4880
+
+#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
+#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
+
+#define IA32_PERF_STS     0x198
+#define IA32_PERF_CTL     0x199
+#define MSR_THERM2_CTL    0x19D
+#define IA32_MISC_ENABLES 0x1A0
+
+/* SATA */
+#define SATA_MAP 0x90
+
+#define SATA_MODE_IDE  0x00
+#define SATA_MODE_AHCI 0x01
+
+/* RCBA registers */
+#define RCBA 0xF0
+#define DEFAULT_RCBA 0xFEA00000
+
+#define RCBA_RPC   0x0224 /* 32 bit */
+
+#define RCBA_TCTL  0x3000 /*  8 bit */
+
+#define RCBA_D31IP 0x3100 /* 32 bit */
+#define RCBA_D30IP 0x3104 /* 32 bit */
+#define RCBA_D29IP 0x3108 /* 32 bit */
+#define RCBA_D28IP 0x310C /* 32 bit */
+#define RCBA_D31IR 0x3140 /* 16 bit */
+#define RCBA_D30IR 0x3142 /* 16 bit */
+#define RCBA_D29IR 0x3144 /* 16 bit */
+#define RCBA_D28IR 0x3146 /* 16 bit */
+
+#define RCBA_RTC   0x3400 /* 32 bit */
+#define RCBA_HPTC  0x3404 /* 32 bit */
+#define RCBA_GCS   0x3410 /* 32 bit */
+#define RCBA_BUC   0x3414 /*  8 bit */
+#define RCBA_FD    0x3418 /* 32 bit */
+#define RCBA_PRC   0x341C /* 32 bit */
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+static inline int spd_read_byte(u16 device, u8 address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i3100/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/intel/i3100/memory_initialized.c"
+#include "northbridge/intel/i3100/raminit.c"
+#include "sdram/generic_sdram.c"
+#include "northbridge/intel/i3100/reset_test.c"
+#include "debug.c"
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+#include "southbridge/intel/i3100/cmos_failover.c"
+#endif
+
+void early_config(void) {
+	device_t dev;
+	u32 gcs, rpc, fd;
+
+	/* Enable RCBA */
+	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+
+	/* Disable watchdog */
+	gcs = readl(DEFAULT_RCBA + RCBA_GCS);
+	gcs |= (1 << 5); /* No reset */
+	writel(gcs, DEFAULT_RCBA + RCBA_GCS);
+
+	/* Configure PCIe port B as 4x */
+	rpc = readl(DEFAULT_RCBA + RCBA_RPC);
+	rpc |= (3 << 0);
+	writel(rpc, DEFAULT_RCBA + RCBA_RPC);
+
+	/* Disable Modem, Audio, PCIe ports 2/3/4 */
+	fd = readl(DEFAULT_RCBA + RCBA_FD);
+	fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
+	writel(fd, DEFAULT_RCBA + RCBA_FD);
+
+	/* Enable HPET */
+	writel((1 << 7), DEFAULT_RCBA + RCBA_HPTC);
+
+	/* Improve interrupt routing
+	 * D31:F2 SATA        INTB# -> PIRQD
+	 * D31:F3 SMBUS       INTB# -> PIRQD
+	 * D31:F4 CHAP        INTD# -> PIRQA
+	 * D29:F0 USB1#1      INTA# -> PIRQH
+	 * D29:F1 USB1#2      INTB# -> PIRQD
+	 * D29:F7 USB2        INTA# -> PIRQH
+	 * D28:F0 PCIe Port 1 INTA# -> PIRQE
+	 */
+
+	writew(0x0230, DEFAULT_RCBA + RCBA_D31IR);
+	writew(0x3210, DEFAULT_RCBA + RCBA_D30IR);
+	writew(0x3237, DEFAULT_RCBA + RCBA_D29IR);
+	writew(0x3214, DEFAULT_RCBA + RCBA_D28IR);
+
+	/* Setup sata mode */
+	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
+}
+
+void real_main(unsigned long bist)
+{
+	/* int boot_mode = 0; */
+
+	static const struct mem_controller mch[] = {
+		{
+			.node_id = 0,
+			.f0 = PCI_DEV(0, 0x00, 0),
+			.f1 = PCI_DEV(0, 0x00, 1),
+			.f2 = PCI_DEV(0, 0x00, 2),
+			.f3 = PCI_DEV(0, 0x00, 3),
+			.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
+			.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+		}
+	};
+
+	if (bist == 0) {
+		enable_lapic();
+	}
+
+	/* Setup the console */
+	i3100_enable_superio();
+	i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	/* Perform early board specific init */
+	early_config();
+
+	/* Prevent the TCO timer from rebooting us */
+	i3100_halt_tco_timer();
+
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+
+	/* Enable SpeedStep and automatic thermal throttling */
+	{
+		msr_t msr;
+		u16 perf;
+
+		msr = rdmsr(IA32_MISC_ENABLES);
+		msr.lo |= (1 << 3) | (1 << 16);
+		wrmsr(IA32_MISC_ENABLES, msr);
+
+		/* Set CPU frequency/voltage to maximum */
+
+		/* Read performance status register and keep
+		 * bits 47:32, where BUS_RATIO_MAX and VID_MAX
+		 * are encoded
+		 */
+		msr = rdmsr(IA32_PERF_STS);
+		perf = msr.hi & 0x0000ffff;
+
+		/* Write VID_MAX & BUS_RATIO_MAX to
+		 * performance control register
+		 */
+		msr = rdmsr(IA32_PERF_CTL);
+		msr.lo &= 0xffff0000;
+		msr.lo |= perf;
+		wrmsr(IA32_PERF_CTL, msr);
+	}
+
+	/* Initialize memory */
+	sdram_initialize(ARRAY_SIZE(mch), mch);
+}
+
+#include "cpu/intel/model_6fx/cache_as_ram_disable.c"


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/chip.h (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/chip.h)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/chip.h	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+	int nothing;
+};


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/chip.h
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/cmos.layout (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/cmos.layout	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/cmos.layout	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,134 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          1       e       1        power_on_after_fail
+#410          6       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+#928         80       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/cmos.layout
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/debug.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/debug.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/debug.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/debug.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,350 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define SMBUS_MEM_DEVICE_START 0x50
+#define SMBUS_MEM_DEVICE_END 0x57
+#define SMBUS_MEM_DEVICE_INC 1
+
+static void print_reg(unsigned char index)
+{
+        unsigned char data;
+
+        outb(index, 0x2e);
+        data = inb(0x2f);
+	print_debug("0x");
+	print_debug_hex8(index);
+	print_debug(": 0x");
+	print_debug_hex8(data);
+	print_debug("\r\n");
+        return;
+}
+
+static void xbus_en(void)
+{
+        /* select the XBUS function in the SIO */
+        outb(0x07, 0x2e);
+        outb(0x0f, 0x2f);
+        outb(0x30, 0x2e);
+        outb(0x01, 0x2f);
+	return;
+}
+
+static void setup_func(unsigned char func)
+{
+        /* select the function in the SIO */
+        outb(0x07, 0x2e);
+        outb(func, 0x2f);
+        /* print out the regs */
+        print_reg(0x30);
+        print_reg(0x60);
+        print_reg(0x61);
+        print_reg(0x62);
+        print_reg(0x63);
+        print_reg(0x70);
+        print_reg(0x71);
+        print_reg(0x74);
+        print_reg(0x75);
+        return;
+}
+
+static void siodump(void)
+{
+        int i;
+        unsigned char data;
+
+	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+        for (i=0x10; i<=0x2d; i++) {
+                print_reg((unsigned char)i);
+        }
+#if 0
+        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        setup_func(0x0f);
+        for (i=0xf0; i<=0xff; i++) {
+                print_reg((unsigned char)i);
+        }
+
+        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        setup_func(0x03);
+        print_reg(0xf0);
+
+        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        setup_func(0x02);
+        print_reg(0xf0);
+
+#endif
+        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        setup_func(0x07);
+        for (i=0xf0; i<=0xf8; i++) {
+                print_reg((unsigned char)i);
+        }
+        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        data = inb(0x68a);
+	print_debug("\r\nGPDO 4: 0x");
+	print_debug_hex8(data);
+        data = inb(0x68b);
+	print_debug("\r\nGPDI 4: 0x");
+	print_debug_hex8(data);
+	print_debug("\r\n");
+
+#if 0
+
+        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        setup_func(0x0a);
+        print_reg(0xf0);
+
+        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        setup_func(0x09);
+        print_reg(0xf0);
+        print_reg(0xf1);
+
+        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        setup_func(0x10);
+        print_reg(0xf0);
+        print_reg(0xf1);
+        print_reg(0xf3);
+        print_reg(0xf6);
+        print_reg(0xf7);
+        print_reg(0xfe);
+        print_reg(0xff);
+
+        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        setup_func(0x14);
+        print_reg(0xf0);
+#endif
+        return;
+}
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
+	}
+}
+
+static void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
+
+	for(i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_bar14(unsigned dev)
+{
+	int i;
+	unsigned long bar;
+
+	print_debug("BAR 14 Dump\r\n");
+
+	bar = pci_read_config32(dev, 0x14);
+	for(i = 0; i <= 0x300; i+=4) {
+#if 0
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+#endif
+		if((i%4)==0) {
+		print_debug("\r\n");
+		print_debug_hex16(i);
+		print_debug_char(' ');
+		}
+		print_debug_hex32(read32(bar + i));
+		print_debug_char(' ');
+	}
+	print_debug("\r\n");
+}
+
+static void dump_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
+	}
+}
+
+#if 0
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+	int i;
+	print_debug("\r\n");
+	for(i = 0; i < 4; i++) {
+		unsigned device;
+		device = ctrl->channel0[i];
+		if (device) {
+			int j;
+			print_debug("dimm: ");
+			print_debug_hex8(i);
+			print_debug(".0: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = smbus_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+		device = ctrl->channel1[i];
+		if (device) {
+			int j;
+			print_debug("dimm: ");
+			print_debug_hex8(i);
+			print_debug(".1: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = smbus_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+	}
+}
+#endif
+
+void dump_spd_registers(void)
+{
+        unsigned device;
+        device = SMBUS_MEM_DEVICE_START;
+        while(device <= SMBUS_MEM_DEVICE_END) {
+                int status = 0;
+                int i;
+        	print_debug("\r\n");
+                print_debug("dimm ");
+		print_debug_hex8(device);
+
+                for(i = 0; (i < 256) ; i++) {
+                        if ((i % 16) == 0) {
+				print_debug("\r\n");
+				print_debug_hex8(i);
+				print_debug(": ");
+                        }
+			status = smbus_read_byte(device, i);
+                        if (status < 0) {
+			         print_debug("bad device: ");
+				 print_debug_hex8(-status);
+				 print_debug("\r\n");
+			         break;
+			}
+			print_debug_hex8(status);
+			print_debug_char(' ');
+		}
+		device += SMBUS_MEM_DEVICE_INC;
+		print_debug("\n");
+	}
+}
+
+void dump_ipmi_registers(void)
+{
+        unsigned device;
+        device = 0x42;
+        while(device <= 0x42) {
+                int status = 0;
+                int i;
+        	print_debug("\r\n");
+                print_debug("ipmi ");
+		print_debug_hex8(device);
+
+                for(i = 0; (i < 8) ; i++) {
+			status = smbus_read_byte(device, 2);
+                        if (status < 0) {
+			         print_debug("bad device: ");
+				 print_debug_hex8(-status);
+				 print_debug("\r\n");
+			         break;
+			}
+			print_debug_hex8(status);
+			print_debug_char(' ');
+		}
+		device += SMBUS_MEM_DEVICE_INC;
+		print_debug("\n");
+	}
+}


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/debug.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Added: trunk/coreboot-v2/src/mainboard/intel/eagleheights/dsdt.dsl
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/dsdt.dsl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/dsdt.dsl	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,1079 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001)
+{
+	Scope (\_PR)
+	{
+		Processor (CPU1, 0x01, 0x00000810, 0x06)
+		{
+			OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+			Name (NCPU, 0x80)
+			Name (TYPE, 0x80000000)
+			Name (HNDL, 0x80000000)
+			Name (CFGD, 0x80000000)
+			Name (TBLD, 0x80)
+			Method (_PDC, 1, NotSerialized)
+			{
+			}
+		}
+	}
+
+	Scope (\_PR)
+	{
+		Processor (CPU2, 0x02, 0x00000000, 0x00)
+		{
+			OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+			Name (NCPU, 0x80)
+			Name (TYPE, 0x80000000)
+			Name (HNDL, 0x80000000)
+			Name (CFGD, 0x80000000)
+			Name (TBLD, 0x80)
+			Method (_PDC, 1, NotSerialized)
+			{
+			}
+		}
+	}
+
+	/* For now only define 2 power states:
+	*  - S0 which is fully on
+	*  - S5 which is soft off
+	* Any others would involve declaring the wake up methods.
+	*/
+	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+	Name (PICM, 0x00)
+	Method (_PIC, 1, NotSerialized)
+	{
+		Store (Arg0, PICM)
+	}
+
+	/* System bus */
+	Scope (\_SB)
+	{
+		/* Routing PCI0 */
+		Name (PR00, Package (0x0E)
+		{
+		Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */
+		Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */
+		Package (0x04){0x0002FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0002FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0002FFFF,0x03,LNKD,0x00},
+		Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */
+		Package (0x04){0x0003FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0003FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0003FFFF,0x03,LNKD,0x00},
+		Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */
+			Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */
+			Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */
+		Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */
+			Package (0x04){0x001FFFFF,0x03,LNKA,0x00}  /* CHAP INTD# */
+		})
+		Name (AR00, Package (0x0E)
+		{
+		Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */
+		Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */
+		Package (0x04){0x0002FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0002FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0002FFFF,0x03,0x00,0x13},
+		Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */
+		Package (0x04){0x0003FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0003FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0003FFFF,0x03,0x00,0x13},
+		Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */
+			Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */
+			Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */
+		Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */
+			Package (0x04){0x001FFFFF,0x0D,0x00,0x10}  /* CHAP INTD# */
+		})
+	/* Routing PCIe Port A */
+		Name (PR0A, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,LNKA,0x00},
+			Package (0x04){0xFFFF,0x01,LNKB,0x00},
+			Package (0x04){0xFFFF,0x02,LNKC,0x00},
+			Package (0x04){0xFFFF,0x03,LNKD,0x00}
+		})
+		Name (AR0A, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,0x00,0x10},
+			Package (0x04){0xFFFF,0x01,0x00,0x11},
+			Package (0x04){0xFFFF,0x02,0x00,0x12},
+			Package (0x04){0xFFFF,0x03,0x00,0x13}
+		})
+	/* Routing PCIe Port B */
+		Name (PR0B, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,LNKA,0x00},
+			Package (0x04){0xFFFF,0x01,LNKB,0x00},
+			Package (0x04){0xFFFF,0x02,LNKC,0x00},
+			Package (0x04){0xFFFF,0x03,LNKD,0x00}
+		})
+		Name (AR0B, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,0x00,0x10},
+			Package (0x04){0xFFFF,0x01,0x00,0x11},
+			Package (0x04){0xFFFF,0x02,0x00,0x12},
+			Package (0x04){0xFFFF,0x03,0x00,0x13}
+		})
+	/* Routing Bus PCI */
+	Name (PR01, Package (0x04)
+		{
+		Package (0x04){0x0000FFFF,0x00,LNKA,0x00},
+		Package (0x04){0x0000FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0000FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0000FFFF,0x03,LNKD,0x00},
+	})
+	Name (AR01, Package (0x04)
+		{
+		Package (0x04){0x0000FFFF,0x00,0x00,0x10},
+		Package (0x04){0x0000FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0000FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0000FFFF,0x03,0x00,0x13},
+	})
+
+		Name (PRSA, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared, )
+				{3,4,5,6,7,10,11,12,14,15}
+		})
+		Alias (PRSA, PRSB)
+		Alias (PRSA, PRSC)
+		Alias (PRSA, PRSD)
+		Alias (PRSA, PRSE)
+		Alias (PRSA, PRSF)
+		Alias (PRSA, PRSG)
+		Alias (PRSA, PRSH)
+
+	Device (PCI0)
+	{
+		Name (_HID, EisaId ("PNP0A08"))
+		Name (_CID, EisaId ("PNP0A03"))
+		Name (_ADR, 0x00)
+		Name (_SEG, 0x00)
+		Name (_UID, 0x00)
+		Name (_BBN, 0x00)
+
+		Name (SUPP, 0) /* PCI _OSC Support Field Value */
+		Name (CTRL, 0) /* PCI _OSC Control Field Value */
+
+		Method (_OSC, 4)
+		{
+			/* Check for proper GUID */
+		If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+		{
+			/* Create DWORD-adressable field from the Capabilities Buffer */
+			CreateDWordField (Arg3, 0, CDW1)
+			CreateDWordField (Arg3, 4, CDW2)
+			CreateDWordField (Arg3, 8, CDW3)
+
+			/* Save Capabilities DWord 2 & 3 */
+			Store (CDW2, SUPP)
+			Store (CDW3, CTRL)
+
+			/* Don't care of OS capabilites */
+			/* We support nothing (maybe we should add PCIe Capability Structure Control) */
+			And (CTRL, 0x00, CTRL)
+
+			/* Query flag clear ? */
+			If (Not (And (CDW1, 1)))
+			{
+				/* Nothing to do */
+			}
+
+			/* Unknown revision ? */
+			If (LNotEqual (Arg1, One))
+			{
+				Or (CDW1, 0x08, CDW1)
+			}
+
+			/* Capabilities bits masked ? */
+			If (LNotEqual (CDW3, CTRL))
+			{
+				Or (CDW1, 0x10, CDW1)
+			}
+
+			/* Update DWORD3 in the buffer */
+			Store (CTRL, CDW3)
+
+			Return (Arg3)
+		}
+		Else
+		{
+			/* Unrecognized UUID */
+			Or (CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+		} /* End _OSC */
+
+			Method (_PRT, 0, NotSerialized)
+			{
+				If (PICM)
+				{
+					Return (AR00)
+				}
+
+				Return (PR00)
+			}
+
+		/* PCI Express Port A */
+		Device (EPA0)
+			{
+				Name (_ADR, 0x00020000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0A)
+					}
+
+					Return (PR0A)
+				}
+			}
+
+		/* PCI Express Port A1 */
+			Device (EPA1)
+			{
+				Name (_ADR, 0x00030000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0A)
+					}
+
+					Return (PR0A)
+				}
+			}
+
+		/* PCI Express Port B0 */
+			Device (EPB0)
+			{
+				Name (_ADR, 0x001C0000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0B)
+					}
+
+					Return (PR0B)
+				}
+			}
+
+		/* PCI Bridge */
+			Device (P0P1)
+			{
+				Name (_ADR, 0x001E0000)
+
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR01)
+					}
+
+					Return (PR01)
+				}
+			}
+
+		/* LPC I/F Bridge */
+		Device (ISA) {
+			Name (_ADR, 0x001F0000)
+
+				/* MMCONF */
+				Device (^PCIE)
+				{
+					Name (_HID, EisaId ("PNP0C02"))
+					Name (_UID, 0x11)
+					Name (CRS, ResourceTemplate ()
+					{
+						Memory32Fixed (ReadOnly,
+							0xE0000000,         // Address Base
+							0x10000000,         // Address Length
+							_Y10)
+					})
+					Method (_CRS, 0, NotSerialized)
+					{
+						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)
+						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)
+						Store (0xE0000000, BAS1)
+						Store (0x10000000, LEN1)
+						Return (CRS)
+					}
+				}
+
+		/* PIC */
+				Device (PIC)
+				{
+			Name (_HID, EisaId ("PNP0000"))
+			Name (_CRS, ResourceTemplate()
+			{
+				IO (Decode16,
+				0x0020,
+				0x0020,
+				0x00,
+				0x02,
+				)
+			IO (Decode16,
+				0x00A0,
+				0x00A0,
+				0x00,
+				0x02,
+				)
+			IRQNoFlags ()
+				{2}
+			})
+				}
+
+		/* Real time clock */
+				Device (RTC0)
+				{
+					Name (_HID, EisaId ("PNP0B00"))
+					Name (_CRS, ResourceTemplate ()
+					{
+						IO (Decode16,
+				0x0070,
+				0x0070,
+				0x00,
+				0x02)
+						IRQNoFlags ()
+				{8}
+					})
+				}
+
+				Device (UAR1)
+				{
+					Name (_UID, 0x01)
+					Name (_HID, EisaId ("PNP0501"))
+
+					Method (_PRS, 0, NotSerialized)
+					{
+						Return (CMPR)
+					}
+
+					Name (CMPR, ResourceTemplate ()
+					{
+						StartDependentFn (0x00, 0x00)
+						{
+							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+							IRQNoFlags () {4}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x02F8,0x02F8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+				DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x03E8,0x03E8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+				DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x02E8,0x02E8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						EndDependentFn ()
+					})
+				}
+
+		/* PS/2 keyboard (seems to be important for WinXP install) */
+		Device (KBD)
+		{
+			Name (_HID, EisaId ("PNP0303"))
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0f)
+			}
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+				IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+				IRQNoFlags () {1}
+			})
+			Return (TMP)
+			}
+		}
+
+		/* PS/2 mouse */
+		Device (MOU)
+		{
+			Name (_HID, EisaId ("PNP0F13"))
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0f)
+			}
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (TMP, ResourceTemplate () {
+				IRQNoFlags () {12}
+			})
+			Return (TMP)
+			}
+		}
+
+		/* COM ports of SIO */
+		Device(SIO) {
+				OperationRegion (PT4E, SystemIO, 0x4E, 0x02)
+				Field (PT4E, ByteAcc, NoLock, Preserve)
+				{
+					PO4E,   8,
+					PO4F,   8
+				}
+
+				IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)
+				{
+							Offset (0x07),
+					ILDN,   8,
+							Offset (0x28),
+					SIUI,   8,
+					SIUC,   8,
+							Offset (0x30),
+					IACT,   8,
+							Offset (0x60),
+					IIOH,   8,
+					IIOL,   8,
+							Offset (0x70),
+					IINT,   8
+				}
+
+				Method (IENF, 0, NotSerialized)
+				{
+					Store (0x80, PO4E)
+					Store (0x86, PO4E)
+				}
+
+				Method (IEXF, 0, NotSerialized)
+				{
+					Store (0x68, PO4E)
+					Store (0x08, PO4E)
+				}
+
+				Device (COM1)
+				{
+					Name (_UID, 0x03)
+					Name (_HID, EisaId ("PNP0501"))
+					Method (_STA, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x04, ILDN)
+						Store (IACT, Local0)
+						IEXF ()
+						If (LEqual (Local0, 0xFF))
+						{
+							Return (0x00)
+						}
+
+						If (LEqual (Local0, One))
+						{
+							Return (0x0F)
+						}
+						Else
+						{
+							Return (0x0D)
+						}
+					}
+
+					Method (_DIS, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x04, ILDN)
+						Store (Zero, IACT)
+						IEXF ()
+					}
+
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BFU1, ResourceTemplate ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								_Y03)
+							IRQNoFlags (_Y04)
+								{5}
+						})
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)
+						IENF ()
+						Store (0x04, ILDN)
+						Store (IIOH, Local0)
+						ShiftLeft (Local0, 0x08, Local1)
+						Store (IIOL, Local0)
+						Add (Local1, Local0, Local0)
+						Store (Local0, IMIN)
+						Store (Local0, IMAX)
+						Store (IINT, Local0)
+						IEXF ()
+						Store (0x01, Local1)
+						ShiftLeft (Local1, Local0, IRQ0)
+						Return (BFU1)
+					}
+
+					Name (_PRS, ResourceTemplate ()
+					{
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{5}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x02F8,             // Range Minimum
+								0x02F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{9}
+						}
+				EndDependentFn ()
+					})
+					Method (_SRS, 1, NotSerialized)
+					{
+						CreateByteField (Arg0, 0x02, IOLO)
+						CreateByteField (Arg0, 0x03, IOHI)
+						CreateWordField (Arg0, 0x09, IRQ0)
+						IENF ()
+						Store (0x04, ILDN)
+						Store (Zero, IACT)
+						Store (IOLO, IIOL)
+						Store (IOHI, IIOH)
+						FindSetRightBit (IRQ0, Local0)
+						If (LGreater (Local0, 0x00))
+						{
+							Decrement (Local0)
+						}
+
+						Store (Local0, IINT)
+						Store (One, IACT)
+						IEXF ()
+					}
+				} /* COM1 */
+
+				Device (COM2)
+				{
+					Name (_UID, 0x04)
+					Name (_HID, EisaId ("PNP0501"))
+					Method (_STA, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x05, ILDN)
+						Store (IACT, Local0)
+						IEXF ()
+						If (LEqual (Local0, 0xFF))
+						{
+							Return (0x00)
+						}
+
+						If (LEqual (Local0, One))
+						{
+							Return (0x0F)
+						}
+						Else
+						{
+							Return (0x0D)
+						}
+					}
+
+					Method (_DIS, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x05, ILDN)
+						Store (Zero, IACT)
+						IEXF ()
+					}
+
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BFU1, ResourceTemplate ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								_Y05)
+							IRQNoFlags (_Y06)
+								{9}
+						})
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)
+						IENF ()
+						Store (0x05, ILDN)
+						Store (IIOH, Local0)
+						ShiftLeft (Local0, 0x08, Local1)
+						Store (IIOL, Local0)
+						Add (Local1, Local0, Local0)
+						Store (Local0, IMIN)
+						Store (Local0, IMAX)
+						Store (IINT, Local0)
+						IEXF ()
+						Store (0x01, Local1)
+						ShiftLeft (Local1, Local0, IRQ0)
+						Return (BFU1)
+					}
+
+					Name (_PRS, ResourceTemplate ()
+					{
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{5}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x02F8,             // Range Minimum
+								0x02F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{9}
+						}
+						EndDependentFn ()
+					})
+					Method (_SRS, 1, NotSerialized)
+					{
+						CreateByteField (Arg0, 0x02, IOLO)
+						CreateByteField (Arg0, 0x03, IOHI)
+						CreateWordField (Arg0, 0x09, IRQ0)
+						IENF ()
+						Store (0x05, ILDN)
+						Store (Zero, IACT)
+						Store (IOLO, IIOL)
+						Store (IOHI, IIOH)
+						FindSetRightBit (IRQ0, Local0)
+						If (LGreater (Local0, 0x00))
+						{
+							Decrement (Local0)
+						}
+
+						Store (Local0, IINT)
+						Store (One, IACT)
+						IEXF ()
+					}
+				} /* COM2 */
+		} /* Device SIO */
+		} /* Device ISA */
+	} /* Device PCI 0*/
+	} /* Scope SB */
+
+	OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)
+	Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)
+	{
+		PIRA,   8,
+		PIRB,   8,
+		PIRC,   8,
+		PIRD,   8,
+				Offset (0x08),
+		PIRE,   8,
+		PIRF,   8,
+		PIRG,   8,
+		PIRH,   8
+	}
+
+	Scope (_SB)
+	{
+		Name (BUFA, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared, _Y1C)
+				{15}
+		})
+		CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)
+		Device (LNKA)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x01)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRA, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSA)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRA, 0x80, PIRA)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRA, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRA)
+			}
+		}
+
+		Device (LNKB)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x02)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRB, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSB)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRB, 0x80, PIRB)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRB, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRB)
+			}
+		}
+
+		Device (LNKC)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x03)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRC, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSC)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRC, 0x80, PIRC)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRC, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRC)
+			}
+		}
+
+		Device (LNKD)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x04)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRD, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSD)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRD, 0x80, PIRD)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRD, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRD)
+			}
+		}
+
+		Device (LNKE)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x05)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRE, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSE)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRE, 0x80, PIRE)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRE, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRE)
+			}
+		}
+
+		Device (LNKF)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x06)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRF, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSF)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRF, 0x80, PIRF)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRF, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRF)
+			}
+		}
+
+		Device (LNKG)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x07)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRG, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSG)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRG, 0x80, PIRG)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRG, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRG)
+			}
+		}
+
+		Device (LNKH)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x08)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRH, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSH)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRH, 0x80, PIRH)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRH, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRH)
+			}
+		}
+	}
+}
+
+

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/fadt.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/fadt.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/fadt.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+#define ACPI_PM1_STS        (pmbase + 0x00)
+#define ACPI_PM1_EN         (pmbase + 0x02)
+#define ACPI_PM1_CNT        (pmbase + 0x04)
+#define ACPI_PM1_TMR        (pmbase + 0x08)
+#define ACPI_PROC_CNT       (pmbase + 0x10)
+#define ACPI_LV2            (pmbase + 0x14)
+#define ACPI_GPE0_STS       (pmbase + 0x28)
+#define ACPI_GPE0_EN        (pmbase + 0x2C)
+#define ACPI_SMI_EN         (pmbase + 0x30)
+#define ACPI_SMI_STS        (pmbase + 0x34)
+#define ACPI_ALT_GP_SMI_EN  (pmbase + 0x38)
+#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A)
+#define ACPI_MON_SMI        (pmbase + 0x40)
+#define ACPI_DEVACT_STS     (pmbase + 0x44)
+#define ACPI_DEVTRAP_EN     (pmbase + 0x48)
+#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C)
+#define ACPI_BUS_CYC_TRACK  (pmbase + 0x4E)
+
+#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS
+#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT
+#define ACPI_PM_TMR_BLK   ACPI_PM1_TMR
+#define ACPI_P_BLK        ACPI_PROC_CNT
+#define ACPI_GPE0_BLK     ACPI_GPE0_STS
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->preferred_pm_profile = 7; /* Performance Server */
+	fadt->sci_int = 0x9;
+#if HAVE_SMI_HANDLER == 1
+	fadt->smi_cmd = 0xb2;
+#else
+	fadt->smi_cmd = 0x00;
+#endif
+	fadt->acpi_enable = 0xe1;
+	fadt->acpi_disable = 0x1e;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0x0;
+
+	fadt->pm1_evt_len = 0x4;
+	fadt->pm1_cnt_len = 0x2;
+	fadt->pm2_cnt_len = 0x0;
+	fadt->pm_tmr_len = 0x4;
+	fadt->gpe0_blk_len = 0x8;
+	fadt->gpe1_blk_len = 0x0;
+	fadt->gpe1_base = 0x0;
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 0x65;
+	fadt->p_lvl3_lat = 0x3e9;
+	fadt->flush_size = 0x400;
+	fadt->flush_stride = 0x10;
+	fadt->duty_offset = 0x1;
+	fadt->duty_width = 0x3;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = 0x03;
+	fadt->flags = 0xa5;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = 6;
+	fadt->res3 = 0;
+	fadt->res4 = 0;
+	fadt->res5 = 0;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 32;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = 0x0;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 32;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/fadt.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Added: trunk/coreboot-v2/src/mainboard/intel/eagleheights/ioapic.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/ioapic.h	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/ioapic.h	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,2 @@
+#define IOAPIC_I3100 2
+#define INTEL_IOAPIC_NUM_INTERRUPTS 24

Added: trunk/coreboot-v2/src/mainboard/intel/eagleheights/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/irq_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/irq_tables.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 9,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x2670,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x4b,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x1, 0x0},
+		{0x01, (0x01 << 3) | 0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/mainboard.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/mainboard.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/mainboard.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include "chip.h"
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Intel Eagle Heights Mainboard")
+};
+


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/mainboard.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/mptable.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mptable.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/mptable.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/mptable.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,323 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+// Generate MP-table IRQ numbers for PCI devices.
+#define IO_APIC0 2
+
+#define INT_A	0
+#define INT_B	1
+#define INT_C	2
+#define INT_D	3
+#define PCI_IRQ(dev, intLine)	(((dev)<<2) | intLine)
+
+#define PIRQ_A 16
+#define PIRQ_B 17
+#define PIRQ_C 18
+#define PIRQ_D 19
+#define PIRQ_E 20
+#define PIRQ_F 21
+#define PIRQ_G 22
+#define PIRQ_H 23
+
+// RCBA
+#define RCBA 0xF0
+
+#define RCBA_D31IP 0x3100
+#define RCBA_D30IP 0x3104
+#define RCBA_D29IP 0x3108
+#define RCBA_D28IP 0x310C
+#define RCBA_D31IR 0x3140
+#define RCBA_D30IR 0x3142
+#define RCBA_D29IR 0x3144
+#define RCBA_D28IR 0x3146
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "Intel   ";
+        static const char productid[12] = "EagleHeights";
+        struct mp_config_table *mc;
+	unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
+	unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
+	int i;
+	uint32_t pin, route;
+	device_t dev;
+	struct resource *res;
+	unsigned long rcba;
+
+	dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
+	res = find_resource(dev, RCBA);
+	if (!res) {
+	  return;
+	}
+	rcba = res->base;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+	/* Get bus numbers */
+	bus_chipset = 0;
+
+	/* PCI */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
+	if (dev) {
+	  bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	  bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+	  bus_isa++;
+	} else {
+	  printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+	  bus_pci = 6;
+	  bus_isa = 7;
+	}
+
+	dev = dev_find_slot(0, PCI_DEVFN(2,0));
+	if(dev) {
+	  bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	} else {
+	  printk_debug("ERROR - could not find PCIe Port A  0:2.0, using defaults\n");
+	  bus_pcie_a = 1;
+	}
+
+	dev = dev_find_slot(0, PCI_DEVFN(3,0));
+	if(dev) {
+	  bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	} else {
+	  printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+	  bus_pcie_a1 = 2;
+	}
+
+	dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));
+	if(dev) {
+	  bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	} else {
+	  printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+	  bus_pcie_b = 3;
+	}
+
+	/*Bus: Bus ID Type*/
+	for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+	  smp_write_bus(mc, bus_num, "PCI   ");
+	}
+	smp_write_bus(mc, bus_isa, "ISA   ");
+
+	/*I/O APICs: APIC ID Version State Address*/
+	smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+	/*
+	{
+		device_t dev;
+		struct resource *res;
+		dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
+		if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 3, 0x20, res->base);
+			}
+		}
+		dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
+		if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 4, 0x20, res->base);
+			}
+		}
+                dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 5, 0x20, res->base);
+			}
+                }
+                dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 8, 0x20, res->base);
+			}
+                }
+	}
+	*/
+	/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	/* IRQ0 8254 Counter 0, MNT0 */
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  0);
+	/* IRQ1 Keyboard */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  1, IO_APIC0,  1);
+	/* IRQ2 8259 cascade only */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  2);
+	/* IRQ3 COM2, Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  3, IO_APIC0,  3);
+	/* IRQ4 COM1, Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  4, IO_APIC0,  4);
+	/* IRQ5 Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  5, IO_APIC0,  5);
+	/* IRQ6 Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  6, IO_APIC0,  6);
+	/* IRQ7 OPtion for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  7, IO_APIC0,  7);
+	/* IRQ8# RTC, MNT1 */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_EDGE   |MP_IRQ_POLARITY_HIGH,    bus_isa,  8, IO_APIC0,  8);
+	/* IRQ9 Option for PIRQx, SCI, TCO */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  9, IO_APIC0,  9);
+	/* IRQ10 Option for PIRQx, SCI, TCO */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 10);
+	/* IRQ11 Option for PIRQx, SCI, TCO, MMT2 */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 11);
+	/* IRQ12 Mouse, Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 12);
+	/* IRQ13 Floating point interrupt generated off of the processor assertion of FERR# */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 13, IO_APIC0, 13);
+	/* IRQ14 PIRQx Sata primary (legacy mode) */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 14, IO_APIC0, 14);
+	/* IRQ15 PIRQx Sata secondary (legacy mode) */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 15, IO_APIC0, 15);
+
+	/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
+	smp_write_intsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
+
+	/* Internal PCI device for i3100 */
+
+	/* EDMA
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A);
+
+	/* PCIe Port A
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A);
+
+	/* PCIe Port A1
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A);
+
+	/* PCIe Port B
+	 */
+	for(i = 0; i < 4; i++) {
+	  pin = (readl(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+	  if(pin > 0) {
+	    pin -= 1;
+	    route = PIRQ_A + ((readw(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
+	  }
+	}
+
+	/* USB 1.1 : device 29, function 0, 1
+	 */
+	for(i = 0; i < 2; i++) {
+	  pin = (readl(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+	  if(pin > 0) {
+	    pin -= 1;
+	    route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+	  }
+	}
+
+	/* USB 2.0 : device 29, function 7
+	*/
+	pin = (readl(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
+	if(pin > 0) {
+	  pin -= 1;
+	  route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+	  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+	}
+
+	/* SATA : device 31 function 2
+	   SMBus : device 31 function 3
+	   Performance counters : device 31 function 4
+	 */
+	for(i = 2; i < 5; i++) {
+	  pin = (readl(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+	  if(pin > 0) {
+	    pin -= 1;
+	    route = PIRQ_A + ((readw(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
+	  }
+	}
+
+	/* SLOTS */
+
+	/* PCIe 4x slot A
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+	/* PCIe 4x slot A1
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+	/* PCIe 4x slot B
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+	/* PCI slot
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/mptable.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/power_reset_check.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/power_reset_check.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/power_reset_check.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/power_reset_check.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+static void power_down_reset_check(void)
+{
+	uint8_t cmos;
+
+	cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
+	printk_debug("Boot byte = %x\r\n", cmos);
+
+	if((cmos>2)&&(cmos&1))  full_reset();
+}


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/power_reset_check.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Copied: trunk/coreboot-v2/src/mainboard/intel/eagleheights/reset.c (from rev 4379, trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/reset.c)
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/reset.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/reset.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#ifndef __ROMCC__
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+#define PCI_DEV_INVALID 0
+
+static inline device_t pci_locate_device(unsigned pci_id, device_t from)
+{
+	return dev_find_device(pci_id >> 16, pci_id & 0xffff, from);
+}
+#endif
+
+void soft_reset(void)
+{
+	outb(0x04, 0xcf9);
+}
+
+void hard_reset(void)
+{
+	outb(0x06, 0xcf9);
+}
+
+void full_reset(void)
+{
+	device_t dev;
+	/* Enable power on after power fail... */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_LPC), 0);
+	if (dev != PCI_DEV_INVALID) {
+		unsigned byte;
+		byte = pci_read_config8(dev, 0xa4);
+		byte &= 0xfe;
+		pci_write_config8(dev, 0xa4, byte);
+	}
+	outb(0x0e, 0xcf9);
+}
+


Property changes on: trunk/coreboot-v2/src/mainboard/intel/eagleheights/reset.c
___________________________________________________________________
Added: svn:mergeinfo
   + 

Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/i3100.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i3100/i3100.h	2009-07-01 16:34:03 UTC (rev 4391)
+++ trunk/coreboot-v2/src/northbridge/intel/i3100/i3100.h	2009-07-01 17:01:17 UTC (rev 4392)
@@ -57,3 +57,7 @@
 #define  DEVPRES1_D0F1 (1 << 5)
 #define  DEVPRES1_D8F0 (1 << 1)
 #define MSCFG	0XF6
+
+/* DRC */
+#define DRC_NOECC_MODE        (0 << 20)
+#define DRC_72BIT_ECC         (1 << 20)

Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c	2009-07-01 16:34:03 UTC (rev 4391)
+++ trunk/coreboot-v2/src/northbridge/intel/i3100/raminit.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -963,8 +963,8 @@
 	{{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
 		/* FSB 167 */
 	{{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
-		/* N/A */
-	{{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}},
+		/* FSB 200 DIMM 400 */
+	{{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
 	};
 
 	static const u32 dqs_data[] = {
@@ -1220,5 +1220,7 @@
 	pci_write_config16(ctrl->f0, MCHSCRB, data16);
 
 	/* The memory is now setup, use it */
+#if CONFIG_USE_DCACHE_RAM == 0
 	cache_lbmem(MTRR_TYPE_WRBACK);
+#endif
 }

Added: trunk/coreboot-v2/src/northbridge/intel/i3100/reset_test.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i3100/reset_test.c	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/i3100/reset_test.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,20 @@
+/* Convert to C by yhlu */
+#define MCH_DRC 0x7c
+#define DRC_DONE (1 << 29)
+
+/* If I have already booted once skip a bunch of initialization */
+/* To see if I have already booted I check to see if memory
+ * has been enabled.
+ */
+static int bios_reset_detected(void)
+{
+	uint32_t dword;
+
+	dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
+
+	if( (dword & DRC_DONE) != 0 ) {
+		return 1;
+	}
+
+	return 0;
+}

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/Config.lb	2009-07-01 16:34:03 UTC (rev 4391)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/Config.lb	2009-07-01 17:01:17 UTC (rev 4392)
@@ -26,3 +26,4 @@
 driver i3100_smbus.o
 driver i3100_pci.o
 object i3100_reset.o
+object i3100_pciexp_portb.o

Added: trunk/coreboot-v2/src/southbridge/intel/i3100/cmos_failover.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/cmos_failover.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/cmos_failover.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "i3100.h"
+
+#define RTC_FAILED    (1 <<2)
+#define GEN_PMCON_3     0xa4
+
+static void check_cmos_failed(void)
+{
+	u8 byte;
+	byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+	if (byte & RTC_FAILED) {
+		// clear bit 1 and bit 2
+		byte = cmos_read(RTC_BOOT_BYTE);
+		byte &= 0x0c;
+		byte |= CONFIG_MAX_REBOOT_CNT << 4;
+		cmos_write(byte, RTC_BOOT_BYTE);
+	}
+}

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c	2009-07-01 16:34:03 UTC (rev 4391)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -35,12 +35,18 @@
 #define GPIO_BAR 0x48
 #define RCBA 0xf0
 
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xA0
+#define GEN_PMCON_2 0xA2
+#define GEN_PMCON_3 0xA4
+
 #define NMI_OFF 0
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON  1
 
-#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
 #define ALL		(0xff << 24)
@@ -93,11 +99,10 @@
 	}
 
 	/* Put the APIC in virtual wire mode */
-	l[0] = 0x10;
+	l[0] = 0x12;
 	l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
 }
 
-#define SERIRQ_CNTL 0x64
 static void i3100_enable_serial_irqs(device_t dev)
 {
 	/* set packet length and toggle silent mode bit */
@@ -257,7 +262,69 @@
 	}
 }
 
+static void i3100_power_options(device_t dev) {
+  u8 reg8;
+  u16 reg16;
+  int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+  int nmi_option;
 
+  /* Which state do we want to goto after g3 (power restored)?
+   * 0 == S0 Full On
+   * 1 == S5 Soft Off
+   */
+  get_option(&pwr_on, "power_on_after_fail");
+  reg8 = pci_read_config8(dev, GEN_PMCON_3);
+  reg8 &= 0xfe;
+  if (pwr_on) {
+    reg8 &= ~1;
+  } else {
+    reg8 |= 1;
+  }
+  /* avoid #S4 assertions */
+  reg8 |= (3 << 4);
+  /* minimum asssertion is 1 to 2 RTCCLK */
+  reg8 &= ~(1 << 3);	
+  pci_write_config8(dev, GEN_PMCON_3, reg8);
+  printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");  
+
+  /* Set up NMI on errors. */
+  reg8 = inb(0x61);
+  /* Higher Nibble must be 0 */
+  reg8 &= 0x0f;
+  /* IOCHK# NMI Enable */
+  reg8 &= ~(1 << 3);
+  /* PCI SERR# Enable */
+  // reg8 &= ~(1 << 2);
+  /* PCI SERR# Disable for now */
+  reg8 |= (1 << 2);
+  outb(reg8, 0x61);
+  
+  reg8 = inb(0x70);
+  nmi_option = NMI_OFF;
+  get_option(&nmi_option, "nmi");
+  if (nmi_option) {
+    /* Set NMI. */
+    printk_info ("NMI sources enabled.\n");
+    reg8 &= ~(1 << 7);	
+  } else {
+    /* Can't mask NMI from PCI-E and NMI_NOW */
+    printk_info ("NMI sources disabled.\n");
+    reg8 |= ( 1 << 7);
+  }
+  outb(reg8, 0x70);
+
+  // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
+  reg16 = pci_read_config16(dev, GEN_PMCON_1);
+  reg16 &= ~((3 << 0) | (1 << 10));
+  reg16 |= (1 << 3) | (1 << 5);
+  /* CLKRUN_EN */
+  // reg16 |= (1 << 2);
+  pci_write_config16(dev, GEN_PMCON_1, reg16);
+  
+  // Set the board's GPI routing.
+  // i82801gx_gpi_routing(dev);
+}
+
 static void i3100_gpio_init(device_t dev)
 {
 	struct resource *res;
@@ -296,9 +363,6 @@
 
 static void lpc_init(struct device *dev)
 {
-	u8 byte;
-	int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
-
 	setup_ioapic(dev);
 
 	/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
@@ -306,18 +370,12 @@
 
 	i3100_enable_serial_irqs(dev);
 
-	get_option(&pwr_on, "power_on_after_fail");
-	byte = pci_read_config8(dev, 0xa4);
-	byte &= 0xfe;
-	if (!pwr_on) {
-		byte |= 1;
-	}
-	pci_write_config8(dev, 0xa4, byte);
-	printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
-
 	/* Set up the PIRQ */
 	i3100_pirq_init(dev);
 
+	/* Setup power options */
+	i3100_power_options(dev);
+
 	/* Set the state of the gpio lines */
 	i3100_gpio_init(dev);
 

Added: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_pciexp_portb.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_pciexp_portb.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_pciexp_portb.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pciexp.h>
+#include <arch/io.h>
+#include "chip.h"
+#include <part/hard_reset.h>
+
+#define PCIE_LCTL 0x50
+#define PCIE_LSTS 0x52
+
+typedef struct northbridge_intel_i3100_config config_t;
+
+static void pcie_init(struct device *dev)
+{
+}
+
+static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
+{
+	u16 val;
+	u16 ctl;
+	int flag = 0;
+	do {
+		val = pci_read_config16(dev, PCIE_LSTS);
+		printk_debug("pcie portb link status: %02x\n", val);
+		if ((val & (1<<10)) && (!flag)) { /* training error */
+			ctl = pci_read_config16(dev, PCIE_LCTL);
+			pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
+			val = pci_read_config16(dev, PCIE_LSTS);
+			printk_debug("pcie portb reset link status: %02x\n", val);
+			flag=1;
+			hard_reset();
+		}
+	} while	(val & (3<<10));
+	return pciexp_scan_bridge(dev, max);
+}
+
+static struct device_operations pcie_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pcie_init,
+	.scan_bus         = pcie_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = 0,
+};
+
+static struct pci_driver pci_driver_0 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,
+};
+
+static struct pci_driver pci_driver_1 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,
+};
+
+static struct pci_driver pci_driver_2 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,
+};
+
+static struct pci_driver pci_driver_3 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,
+};

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c	2009-07-01 16:34:03 UTC (rev 4391)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -27,32 +27,76 @@
 #include <device/pci_ops.h>
 #include "i3100.h"
 
+#define SATA_CMD     0x04
+#define SATA_PI      0x09
+#define SATA_PTIM    0x40
+#define SATA_STIM    0x42
+#define SATA_D1TIM   0x44
+#define SATA_SYNCC   0x48
+#define SATA_SYNCTIM 0x4A
+#define SATA_IIOC    0x54
+#define SATA_MAP     0x90
+#define SATA_PCS     0x91
+#define SATA_ACR0    0xA8
+#define SATA_ACR1    0xAC
+#define SATA_ATC     0xC0
+#define SATA_ATS     0xC4
+#define SATA_SP      0xD0
+
+typedef struct southbridge_intel_i3100_config config_t;
+
 static void sata_init(struct device *dev)
 {
-	/* Enable SATA devices */
+        u8 ahci;
 
-	printk_debug("SATA init\n");
-	/* SATA configuration */
-	pci_write_config8(dev, 0x04, 0x07);
-	pci_write_config8(dev, 0x09, 0x8f);
+	/* Get the chip configuration */
+	ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
 
-	/* Set timings */
-	pci_write_config16(dev, 0x40, 0x0a307);
-	pci_write_config16(dev, 0x42, 0x0a307);
+	/* Enable SATA devices */
+	printk_info("SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
 
-	/* Sync DMA */
-	pci_write_config16(dev, 0x48, 0x000f);
-	pci_write_config16(dev, 0x4a, 0x1111);
+	if(ahci) {
+	  /* AHCI mode */
+	  pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
 
-	/* Fast ATA */
-	pci_write_config16(dev, 0x54, 0x1000);
+	  /* Enable ports */
+	  pci_write_config8(dev, SATA_PCS, 0x03);
+	  pci_write_config8(dev, SATA_PCS + 1, 0x0F);
 
-	/* Select IDE mode */
-	pci_write_config8(dev, 0x90, 0x00);
+	  /* Setup timings */
+	  pci_write_config16(dev, SATA_PTIM, 0x8000);
+	  pci_write_config16(dev, SATA_STIM, 0x8000);
 
-	/* Enable ports 0-3 */
-	pci_write_config8(dev, 0x92, 0x0f);
+	  /* Synchronous DMA */
+	  pci_write_config8(dev, SATA_SYNCC, 0);
+	  pci_write_config16(dev, SATA_SYNCTIM, 0);
 
+	  /* IDE I/O configuration */
+	  pci_write_config32(dev, SATA_IIOC, 0);
+	  
+	} else {
+	  /* SATA configuration */
+	  pci_write_config8(dev, SATA_CMD, 0x07);
+	  pci_write_config8(dev, SATA_PI, 0x8f);
+	  
+	  /* Set timings */
+	  pci_write_config16(dev, SATA_PTIM, 0x0a307);
+	  pci_write_config16(dev, SATA_STIM, 0x0a307);
+	  
+	  /* Sync DMA */
+	  pci_write_config8(dev, SATA_SYNCC, 0x0f);
+	  pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
+	  
+	  /* Fast ATA */
+	  pci_write_config16(dev, SATA_IIOC, 0x1000);
+	  
+	  /* Select IDE mode */
+	  pci_write_config8(dev, SATA_MAP, 0x00);
+	  
+	  /* Enable ports 0-3 */
+	  pci_write_config8(dev, SATA_PCS + 1, 0x0f);
+	  
+	}
 	printk_debug("SATA Enabled\n");
 }
 

Modified: trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c	2009-07-01 16:34:03 UTC (rev 4391)
+++ trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c	2009-07-01 17:01:17 UTC (rev 4392)
@@ -44,6 +44,7 @@
 #include "chip.h"
 
 /* The following Super I/O chips are currently supported by this driver: */
+#define LPC47M172	0x14
 #define FDC37B80X	0x42	/* Same ID: FDC37M70X (a.k.a. FDC37M707) */
 #define FDC37B78X	0x44
 #define FDC37B72X	0x4c
@@ -62,6 +63,7 @@
 /* Register defines */
 #define DEVICE_ID_REG	0x20	/* Device ID register */
 #define DEVICE_REV_REG	0x21	/* Device revision register */
+#define DEVICE_TEST7_REG 0x29   /* Device test 7 register */
 
 /* Static variables for the Super I/O device ID and revision. */
 static int first_time = 1;
@@ -116,6 +118,7 @@
 	int devs[MAX_LOGICAL_DEVICES];
 } logical_device_table[] = {
 	// Chip   FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB
+	{LPC47M172,{0, 3, 4,  2, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 	{FDC37B80X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, -1, -1}},
 	{FDC37B78X,{0, 3, 4,  5,  6,  7,  8,  -1, -1,  -1, -1, -1, -1, 10, -1}},
 	{FDC37B72X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, 10, -1}},
@@ -284,6 +287,7 @@
 {
 	int i, j, fn;
 	int tmp[MAX_LOGICAL_DEVICES];
+	uint8_t test7;
 
 	if (first_time) {
 		/* Read the device ID and revision of the Super I/O chip. */
@@ -297,6 +301,19 @@
 		printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
 			    superio_id, superio_rev);
 		first_time = 0;
+
+		if(superio_id == LPC47M172) {
+		  /* Do not use the default logical device number
+		   * but instead the standard smsc registers set
+		   */
+
+		  /* TEST7 configuration register (0x29)
+		   * bit 0 : LD_NUM (0 = new, 1 = std smsc)
+		   */
+		  test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
+		  test7 |= 1;
+		  pnp_write_config(dev, DEVICE_TEST7_REG, test7);
+		}
 	}
 
 	/* Find the correct Super I/O. */

Copied: trunk/coreboot-v2/targets/intel/eagleheights/Config.lb (from rev 4379, trunk/coreboot-v2/targets/intel/mtarvon/Config.lb)
===================================================================
--- trunk/coreboot-v2/targets/intel/eagleheights/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/targets/intel/eagleheights/Config.lb	2009-07-01 17:01:17 UTC (rev 4392)
@@ -0,0 +1,32 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 as
+## published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target eagleheights
+mainboard intel/eagleheights
+
+## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
+## (normal AND fallback images and payloads).
+option CONFIG_ROM_SIZE = 1024 * 1024
+
+romimage "fallback"
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	payload ../payload.elf
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"


Property changes on: trunk/coreboot-v2/targets/intel/eagleheights/Config.lb
___________________________________________________________________
Added: svn:mergeinfo
   + 




From mylesgw at gmail.com  Wed Jul  1 19:02:46 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 1 Jul 2009 11:02:46 -0600
Subject: [coreboot] Intel Eagle Height evaluation board support
In-Reply-To: <23a460760906231404h1bc683e4p20d730232588a39e@mail.gmail.com>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<23a460760906231404h1bc683e4p20d730232588a39e@mail.gmail.com>
Message-ID: <2831fecf0907011002n442a3ad7h727dea912a69e154@mail.gmail.com>

On Tue, Jun 23, 2009 at 3:04 PM, Thomas JOURDAN <thomas.jourdan at gmail.com>wrote:

> Signed-off-by: Thomas Jourdan <thomas.jourdan at gmail.com>

Rev 4392.

I used common code where I could to get the same end result.

Thanks,
Myles
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From info at coresystems.de  Wed Jul  1 19:22:29 2009
From: info at coresystems.de (coreboot information)
Date: Wed, 01 Jul 2009 19:22:29 +0200
Subject: [coreboot] build service results for r4392
Message-ID: <E1MM3Vt-0005fC-OD@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4392 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add support for the Intel Eagle Heights development board.

Signed-off-by: Thomas Jourdan <thomas.jourdan at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4392&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4392&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From ward at gnu.org  Wed Jul  1 23:25:19 2009
From: ward at gnu.org (Ward Vandewege)
Date: Wed, 1 Jul 2009 17:25:19 -0400
Subject: [coreboot] [PATCH] convert h8dmr to CBFS
Message-ID: <20090701212519.GA28645@countzero.vandewege.net>

The patch comment says it all...

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator
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From mylesgw at gmail.com  Wed Jul  1 23:53:27 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 1 Jul 2009 15:53:27 -0600
Subject: [coreboot] [PATCH] convert h8dmr to CBFS
In-Reply-To: <20090701212519.GA28645@countzero.vandewege.net>
References: <20090701212519.GA28645@countzero.vandewege.net>
Message-ID: <2CDA449536684FCAA0905CD7B64B7B0C@chimp>


Signed-off-by: Ward Vandewege <ward at gnu.org>

If you put
default CONFIG_USE_FAILOVER_IMAGE=0
default CONFIG_USE_FALLBACK_IMAGE=0
default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE

In Options.lb it would clean up your Config.lb files a little more.

Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles





From peter at stuge.se  Thu Jul  2 00:04:47 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 00:04:47 +0200
Subject: [coreboot] Copyright [was: Intel Eagle Height evaluation
	board	support]
In-Reply-To: <23a460760907010702v4e3f8bsb8df9ac717db50e5@mail.gmail.com>
References: <23a460760906231142q5eeec4e6h77a8fe07007bc017@mail.gmail.com>
	<2831fecf0906291447w375f39e9gdffde44ef8b0b769@mail.gmail.com>
	<23a460760906300006s6a2ee8caqfbb54c0c5fec5a14@mail.gmail.com>
	<A1C2FDA80DF24CFAB3F9AB449D8F26D1@chimp>
	<23a460760907010702v4e3f8bsb8df9ac717db50e5@mail.gmail.com>
Message-ID: <20090701220447.5155.qmail@stuge.se>

Hello Thomas,

Thanks a lot for your contributions to coreboot!


Thomas JOURDAN wrote:
> Is it mandatory ?

Yes.


> A coreboot copyright is fine to me.

Please note that there is no "coreboot" legal entity.

Unfortunately the name of Stefan Reinauer's company, coresystems GmbH,
is quite similar to the name of this project and the two could easily
be confused - but please keep in mind that coresystems GmbH is only
one part of the greater coreboot community. While Stefan and Patrick
do some amazing work with coreboot, I am sure that it is not the
intention of coresystems GmbH to own copyright for all coreboot code.


> Copyright (C) 2009 Thomas Jourdan <thomas.jourdan at gmail.com>

Great! Thanks.


//Peter



From peter at stuge.se  Thu Jul  2 00:07:30 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 00:07:30 +0200
Subject: [coreboot] coreboot VGA init vs. writes [was: Intel
	Eagle	Height evaluation board support]
In-Reply-To: <53E9375E372D4F318F740294EBA8F512@chimp>
References: <23a460760906231418l596e2a3cm3d61953c2b12db6b@mail.gmail.com>
	<8B53F3255BEE44A896F998A7405BA0E6@chimp>
	<23a460760906240534s2b6b20f3w58b2bcdc7bdd1019@mail.gmail.com>
	<20090626182130.GA30895@morn.localdomain>
	<23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
	<20090630234008.GA22496@morn.localdomain>
	<03E0EFDE09E54A48882815F04D43D762@chimp>
	<20090701024044.GA25070@morn.localdomain>
	<13426df10907010622v5ed50edbi24a1116e82de0d7e@mail.gmail.com>
	<53E9375E372D4F318F740294EBA8F512@chimp>
Message-ID: <20090701220730.5722.qmail@stuge.se>

Myles Watson wrote:
> If Coreboot never writes to the console, that fixes it too.  I
> think that was Stefan's preferred solution.

I like that too! Where does coreboot write to VGA now?


> I think he's right that most of the time the VGA console is useless
> for debugging. All the tricky things happen before that's
> available.

Agree.


//Peter



From wallbraker at gmail.com  Thu Jul  2 00:07:33 2009
From: wallbraker at gmail.com (Jakob Bornecrantz)
Date: Thu, 2 Jul 2009 00:07:33 +0200
Subject: [coreboot] Info for EPIA m700 and EPIA n700
Message-ID: <427ca1a20907011507g1eb14864od3dfa27e26c2180d@mail.gmail.com>

Hi all

Here is some info on two Via EPIA boards, you can find them here:
http://irc.walkyrie.se/coreboot/EPIA_m700/
http://irc.walkyrie.se/coreboot/EPIA_n700/
and some pictures of the boards, which I release to public domain:
http://irc.walkyrie.se/coreboot/pictures/

Cheers Jakob.



From mylesgw at gmail.com  Thu Jul  2 00:15:25 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 1 Jul 2009 16:15:25 -0600
Subject: [coreboot] coreboot VGA init vs. writes [was: Intel Eagle
	Height evaluation board support]
In-Reply-To: <20090701220730.5722.qmail@stuge.se>
References: <23a460760906231418l596e2a3cm3d61953c2b12db6b@mail.gmail.com>
	<23a460760906240534s2b6b20f3w58b2bcdc7bdd1019@mail.gmail.com>
	<20090626182130.GA30895@morn.localdomain>
	<23a460760906300010o70e7183fyb2cf07af6af0af67@mail.gmail.com>
	<20090630234008.GA22496@morn.localdomain>
	<03E0EFDE09E54A48882815F04D43D762@chimp>
	<20090701024044.GA25070@morn.localdomain>
	<13426df10907010622v5ed50edbi24a1116e82de0d7e@mail.gmail.com>
	<53E9375E372D4F318F740294EBA8F512@chimp>
	<20090701220730.5722.qmail@stuge.se>
Message-ID: <2831fecf0907011515x6cc8628cq45f32e032a4a4ae7@mail.gmail.com>

On Wed, Jul 1, 2009 at 4:07 PM, Peter Stuge <peter at stuge.se> wrote:

> Myles Watson wrote:
> > If Coreboot never writes to the console, that fixes it too.  I
> > think that was Stefan's preferred solution.
>
> I like that too! Where does coreboot write to VGA now?


from printk as soon as it thinks the console is initialized when CONSOLE_VGA
is set.

Thanks,
Myles
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From peter at stuge.se  Thu Jul  2 00:28:23 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 00:28:23 +0200
Subject: [coreboot] Boot from IDE..
In-Reply-To: <729484.19824.qm@web110812.mail.gq1.yahoo.com>
References: <729484.19824.qm@web110812.mail.gq1.yahoo.com>
Message-ID: <20090701222823.10316.qmail@stuge.se>

Hi Rick,

Rick Ant wrote:
> How can I put the Linux kernel in the Compact Flash on IDE?

Putting it there is easy on another system with a CF reader. To boot
it in a system which uses coreboot, you must use a payload which has
drivers for IDE and the filesystem which is used on the CF card.
FILO, Linux and maybe GRUB 2 should be good choices.


> Coreboot is in BIOS chip then calling the Linux Compact Flash on
> IDE,

No! coreboot does not call anything on IDE. coreboot starts the
payload, FILO, and then coreboot is out of the picture. FILO has
drivers for IDE and several filesystems, and can be used to load
the Linux kernel.


> I see it on FILO

What exactly do you see on FILO? Please be careful to include more
detail when you ask for help. It is impossible to help you when you
are so brief.


> but I still don't understand, since the tutorial is for Qemu only..

That does not matter in this case. Qemu also has IDE devices.

If FILO does not detect your CF card, one suggestion you can try is
to build FILO with more debugging. Enable the relevant debug options
for your configuration.

It is also helpful if you send debugging output.

If you do not send that output, you are MUCH less likely to get any
response at all, as you may have noticed, simply because it is
impossible to help you without more information than you provide.


Thanks

//Peter



From peter at stuge.se  Thu Jul  2 00:30:43 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 00:30:43 +0200
Subject: [coreboot] [PATCH]:AMD family 10 AM2r2 support
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1702D2B108@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1702D2AD89@sbjgexmb1.amd.com>
	<534e5dc20906300822w71c11311ubc7491a1bbd397d3@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702D2B108@sbjgexmb1.amd.com>
Message-ID: <20090701223043.11094.qmail@stuge.se>

Bao, Zheng wrote:
> > > +default CPU_SOCKET_TYPE=0x11
> > 
> > Please add an equate for the socket names.
> 
> "CONFIG_" is added.

I think what Marc meant is to add a #define with a sensible name, for
each socket type, instead of using 0x11 directly.


//Peter



From peter at stuge.se  Thu Jul  2 00:39:04 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 00:39:04 +0200
Subject: [coreboot] C3/CN400 Support - coreboot_tables
In-Reply-To: <8E520A5E7FB8D647BFDA039F6031C1C605727AE9@desmdswms201.des.grplnk.net>
References: <mailman.62.1246371138.8743.coreboot@coreboot.org>
	<8E520A5E7FB8D647BFDA039F6031C1C6057276DD@desmdswms201.des.grplnk.net>
	<13426df10906300844u17000333k4159b3f9d0ce011@mail.gmail.com>
	<8E520A5E7FB8D647BFDA039F6031C1C605727AE9@desmdswms201.des.grplnk.net>
Message-ID: <20090701223905.12463.qmail@stuge.se>

Harrison, Jon (SELEX GALILEO, UK) wrote:
> This version now boots all of the way through to attempting to
> launch a payload (I'm trying FILO right now), where it falls over
> with exception 6 (invalid opcode)

Please start with memtest86 or memtest86+ as payload, and let it run
a few days.


//Peter



From peter at stuge.se  Thu Jul  2 00:41:34 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 00:41:34 +0200
Subject: [coreboot] [v2] r4389 - in
	trunk/coreboot-v2/src:	include/device mainboard/via/epia-n
	southbridge/via/vt8237r
Message-ID: <20090701224134.13011.qmail@stuge.se>

svn at coreboot.org wrote:
> +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2009-07-01 13:19:25 UTC (rev 4389)
..
> +	
> +#ifdef CONFIG_EPIA_VT8237R_INIT

Is this absolutely neccessary? We really want any board specific code
only in the src/mainboard directory.

> +	 * Setup to match EPIA default
> +	 * PCS0# on Pin U1

Yeah, again, I would like this to be improved, so that the
southbridge code is general.

Some pin muxing would have to become structured information so
southbridge code can do the right thing at runtime, I guess..


//Peter



From wallbraker at gmail.com  Thu Jul  2 00:50:03 2009
From: wallbraker at gmail.com (Jakob Bornecrantz)
Date: Thu, 2 Jul 2009 00:50:03 +0200
Subject: [coreboot] Info for EPIA m700 and EPIA n700
In-Reply-To: <427ca1a20907011507g1eb14864od3dfa27e26c2180d@mail.gmail.com>
References: <427ca1a20907011507g1eb14864od3dfa27e26c2180d@mail.gmail.com>
Message-ID: <427ca1a20907011550s709e9dd0n627ef163a52530b3@mail.gmail.com>

On Thu, Jul 2, 2009 at 12:07 AM, Jakob Bornecrantz<wallbraker at gmail.com> wrote:
> Hi all
>
> Here is some info on two Via EPIA boards, you can find them here:
> http://irc.walkyrie.se/coreboot/EPIA_m700/
> http://irc.walkyrie.se/coreboot/EPIA_n700/
> and some pictures of the boards, which I release to public domain:
> http://irc.walkyrie.se/coreboot/pictures/

Here are the files attached as per requested on IRC.

Also I have tested read/write/erase on the m700 board but only read on
the n700, not that write/erase failed I just don't have a way to
recover bad write on the n700 yet.

Cheers Jakob.
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From peter at stuge.se  Thu Jul  2 01:05:20 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 01:05:20 +0200
Subject: [coreboot] Patches long forgotten
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1702CD889E@sbjgexmb1.amd.com>
References: <534e5dc20906170834v585f5c42l2d47265ea5762167@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702C62234@sbjgexmb1.amd.com>
	<534e5dc20906180915w193897a3p22e25641aa12c292@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702C624CE@sbjgexmb1.amd.com>
	<534e5dc20906182116n35897747nc0593ae87dc660d2@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702CD84A0@sbjgexmb1.amd.com>
	<534e5dc20906251451h7e896324haf3185e07dc5fbb8@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702CD85F0@sbjgexmb1.amd.com>
	<534e5dc20906260758q13219bf1n342194d13b6465a9@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702CD889E@sbjgexmb1.amd.com>
Message-ID: <20090701230520.17840.qmail@stuge.se>

Bao, Zheng wrote:
> Can you tell me which is the patch or send it to me?

This is why we need patchwork. Patrick, do you think you'll have a
chance to set it up or should I have a go?


//Peter



From joe at settoplinux.org  Thu Jul  2 01:13:06 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 01 Jul 2009 19:13:06 -0400
Subject: [coreboot] Patches long forgotten
In-Reply-To: <20090701230520.17840.qmail@stuge.se>
References: <534e5dc20906170834v585f5c42l2d47265ea5762167@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702C62234@sbjgexmb1.amd.com>
	<534e5dc20906180915w193897a3p22e25641aa12c292@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702C624CE@sbjgexmb1.amd.com>
	<534e5dc20906182116n35897747nc0593ae87dc660d2@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702CD84A0@sbjgexmb1.amd.com>
	<534e5dc20906251451h7e896324haf3185e07dc5fbb8@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702CD85F0@sbjgexmb1.amd.com>
	<534e5dc20906260758q13219bf1n342194d13b6465a9@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702CD889E@sbjgexmb1.amd.com>
	<20090701230520.17840.qmail@stuge.se>
Message-ID: <5932fac1578aa26e2d29ec0d2cdc8dc3@imap.1and1.com>




On Thu, 2 Jul 2009 01:05:20 +0200, Peter Stuge <peter at stuge.se> wrote:
> Bao, Zheng wrote:
>> Can you tell me which is the patch or send it to me?
> 
> This is why we need patchwork. Patrick, do you think you'll have a
> chance to set it up or should I have a go?
> 
> 
YES, much agreed!

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Thu Jul  2 01:22:52 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 02 Jul 2009 01:22:52 +0200
Subject: [coreboot] Info for EPIA m700 and EPIA n700
In-Reply-To: <427ca1a20907011550s709e9dd0n627ef163a52530b3@mail.gmail.com>
References: <427ca1a20907011507g1eb14864od3dfa27e26c2180d@mail.gmail.com>
	<427ca1a20907011550s709e9dd0n627ef163a52530b3@mail.gmail.com>
Message-ID: <4A4BEFCC.70706@gmx.net>

Hi Jakob,

no offense intended, but getpir recently got an update which caused it
to print incorrect file headers. The irq_table.c snippet below looks
like you used that getpir version and followed the instructions, so I
won't blame you.
I didn't yet have time (and energy) to revert that change to getpir.

If you got irq_table.c by running getpir, it is most likely not under
the GPL and also not your copyright. It might be possible that the
results of getpir can be classified as non-copyrightable data, but even
then applying the GPL to data someone else created feels wrong. For now,
I have to ask you to rerun getpir from revision 4295 which has somewhat
different output without bogus license information. Thanks.

If you created irq_table.c from scratch or based your own routing layout
on getpir results, please accept my apologies.

Regards,
Carl-Daniel

On 02.07.2009 00:50, Jakob Bornecrantz wrote:
> /*
>  * This file is part of the coreboot project.
>  *
>  * Copyright (C) 2009 Jakob Bornecrantz <wallbraker at gmail.com>
>
>  * This program is free software; you can redistribute it and/or modify
>  * it under the terms of the GNU General Public License as published by
>  * the Free Software Foundation; either version 2 of the License, or
>  * (at your option) any later version.
> [...]
>  */
>
> #ifdef GETPIR			/* TODO: Drop this when copying to coreboot. */
> #include "pirq_routing.h"	/* TODO: Drop this when copying to coreboot. */
> #else				/* TODO: Drop this when copying to coreboot. */
> #include <arch/pirq_routing.h>
> #endif				/* TODO: Drop this when copying to coreboot. */
>
>   
-- 
http://www.hailfinger.org/




From wallbraker at gmail.com  Thu Jul  2 01:58:37 2009
From: wallbraker at gmail.com (Jakob Bornecrantz)
Date: Thu, 2 Jul 2009 01:58:37 +0200
Subject: [coreboot] Info for EPIA m700 and EPIA n700
In-Reply-To: <4A4BEFCC.70706@gmx.net>
References: <427ca1a20907011507g1eb14864od3dfa27e26c2180d@mail.gmail.com>
	<427ca1a20907011550s709e9dd0n627ef163a52530b3@mail.gmail.com>
	<4A4BEFCC.70706@gmx.net>
Message-ID: <427ca1a20907011658j23eac839xa0deb775ccfa5d07@mail.gmail.com>

On Thu, Jul 2, 2009 at 1:22 AM, Carl-Daniel
Hailfinger<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi Jakob,
>
> no offense intended, but getpir recently got an update which caused it
> to print incorrect file headers. The irq_table.c snippet below looks
> like you used that getpir version and followed the instructions, so I
> won't blame you.
> I didn't yet have time (and energy) to revert that change to getpir.
>
> If you got irq_table.c by running getpir, it is most likely not under
> the GPL and also not your copyright. It might be possible that the
> results of getpir can be classified as non-copyrightable data, but even
> then applying the GPL to data someone else created feels wrong. For now,
> I have to ask you to rerun getpir from revision 4295 which has somewhat
> different output without bogus license information. Thanks.

Yes it was a broken version I will re run.

>
> If you created irq_table.c from scratch or based your own routing layout
> on getpir results, please accept my apologies.

No i did not write them myself, I assumed it was okay to add it since
mptable adds a copyright automatically, I'm sorry.

Cheers Jakob.



From wallbraker at gmail.com  Thu Jul  2 02:36:14 2009
From: wallbraker at gmail.com (Jakob Bornecrantz)
Date: Thu, 2 Jul 2009 02:36:14 +0200
Subject: [coreboot] Info for EPIA m700 and EPIA n700
In-Reply-To: <4A4BEFCC.70706@gmx.net>
References: <427ca1a20907011507g1eb14864od3dfa27e26c2180d@mail.gmail.com>
	<427ca1a20907011550s709e9dd0n627ef163a52530b3@mail.gmail.com>
	<4A4BEFCC.70706@gmx.net>
Message-ID: <427ca1a20907011736u5f9fe5a5ia7da980da841431@mail.gmail.com>

On Thu, Jul 2, 2009 at 1:22 AM, Carl-Daniel
Hailfinger<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi Jakob,
>
> no offense intended, but getpir recently got an update which caused it
> to print incorrect file headers. The irq_table.c snippet below looks
> like you used that getpir version and followed the instructions, so I
> won't blame you.
> I didn't yet have time (and energy) to revert that change to getpir.
>
> If you got irq_table.c by running getpir, it is most likely not under
> the GPL and also not your copyright. It might be possible that the
> results of getpir can be classified as non-copyrightable data, but even
> then applying the GPL to data someone else created feels wrong. For now,
> I have to ask you to rerun getpir from revision 4295 which has somewhat
> different output without bogus license information. Thanks.

Here are the new results from getpir.

Cheers Jakob.
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From peter at stuge.se  Thu Jul  2 03:02:12 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 03:02:12 +0200
Subject: [coreboot] libpayload question
In-Reply-To: <e37d376a0906280039g42efaf40m2ce12a68d1526249@mail.gmail.com>
References: <e37d376a0906280037p3e7a3cd6k168e00ef406e297e@mail.gmail.com>
	<e37d376a0906280039g42efaf40m2ce12a68d1526249@mail.gmail.com>
Message-ID: <20090702010212.6241.qmail@stuge.se>

Warren Turkal wrote:
> Actually, I just found coreinfo. Can it be launched by grub?

Don't know. Try it.

Etherboot and FILO can both start payloads as were they kernels.


//Peter



From peter at stuge.se  Thu Jul  2 03:16:49 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 03:16:49 +0200
Subject: [coreboot] [flashrom] [PATCH] external serial flasher
	protocol	support
In-Reply-To: <460f92b70906231458m234f68d4k95f6cfb2c241cb77@mail.gmail.com>
References: <460f92b70906091511l65fecbb2nc2914398562492bb@mail.gmail.com>
	<4A2F8C37.6030801@web.de>
	<460f92b70906101100k6a080023tb25f618e3f453858@mail.gmail.com>
	<e37d376a0906101320h2adc9cffob602ea4271a6d98c@mail.gmail.com>
	<460f92b70906140321g5cb6c080wbb79e7a7ece37da8@mail.gmail.com>
	<460f92b70906141123u3d74d3ascceb181faea3d44d@mail.gmail.com>
	<4A40CF8D.5030303@gmx.net>
	<460f92b70906231458m234f68d4k95f6cfb2c241cb77@mail.gmail.com>
Message-ID: <20090702011649.9175.qmail@stuge.se>

Urja Rannikko wrote:
> > You may want to add the following commands for handling of CE#, OE#, WE#.
> > .. GPIO ..
> 
> one would need to define the GPIO's too.

Keep them out of the protocol. These signals must not be messed with
at this high level, they are all in the programmer domain.


//Peter



From peter at stuge.se  Thu Jul  2 04:25:40 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 04:25:40 +0200
Subject: [coreboot] [PATCH] flashrom: Add support for Hyundai HY29F002T
In-Reply-To: <4A42F27A.3060106@ziltro.com>
References: <4A42D46E.2020001@ziltro.com> <20090625030639.18209.qmail@stuge.se>
	<4A42F27A.3060106@ziltro.com>
Message-ID: <20090702022540.22457.qmail@stuge.se>

Andrew Morgan wrote:
>>> Gigabyte GA-7ZXR has two of them for its DualBIOS?. Switching between 
>>> chips seems to be done in software... Very useful.
>>
>> Gigabyte owns a patent involving a timer and a software handshake.
>
> Interesting... That software has to be stored somewhere though, right?
> Unless there is a third ROM, it'll have to be within both BIOSes...

The handshake only needs to be in one BIOS. If the handshake is not
performed within some time period, the board is reset, the other
flash chip activated, and then the CPU is taken out of reset. The
second BIOS image needs no handshake.


//Peter



From peter at stuge.se  Thu Jul  2 12:51:09 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 12:51:09 +0200
Subject: [coreboot] Simple Firmware Interface?
In-Reply-To: <4A43F3CC.5070508@georgi-clan.de>
References: <a698c16a0906251356q29f9ddbei9cafb22a975a0c84@mail.gmail.com>
	<4A43F3CC.5070508@georgi-clan.de>
Message-ID: <20090702105109.5857.qmail@stuge.se>

Patrick Georgi wrote:
> It's a subset of ACPI, looks quite Intel specific, and the FAQ (and
> the draft standard, I think) state that if both, ACPI and SFI are
> available, ACPI should be used.
>
> So, nothing to worry about.

I don't know. I think SFI seems to be a good thing. I believe we will
want to support it.


//Peter



From andi.mundt at web.de  Wed Jul  1 16:21:39 2009
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Wed, 1 Jul 2009 16:21:39 +0200
Subject: [coreboot] ACPI on m57sli v1.0
Message-ID: <20090701142139.GA7679@flashgordon>

Hi everybody,

with the help of Harald's seaBIOS-payload I managed to run the latest
coreboot (revision 4387) on my v1.0 m57sli-board. From a first look
everything seems to work: kvm, sound, power-now frequency scaling. 
dmesg is attached for proprietary and free bios.

Minor issues: 

coreboot ACPI:
 hda: host side 80-wire cable detection failed, limiting max speed to UDMA33
 hda: UDMA/33 mode selected
 [...]
 powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ processors (2 cpu cores) (version 2.20.00)
 powernow-k8:    0 : fid 0x11 (2500 MHz), vid 0x9
 powernow-k8:    1 : fid 0x10 (2400 MHz), vid 0xa
 powernow-k8:    2 : fid 0xe (2200 MHz), vid 0xc
 powernow-k8:    3 : fid 0xc (2000 MHz), vid 0xe
 powernow-k8:    4 : fid 0x2 (1000 MHz), vid 0x12
 powernow-k8: ph2 null fid transition 0x11

proprietary:
 hda: UDMA/66 mode selected
 [...]
 powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ processors (2 cpu cores) (version 2.20.00)
 powernow-k8:    0 : fid 0x11 (2500 MHz), vid 0x9
 powernow-k8:    1 : fid 0x10 (2400 MHz), vid 0xa
 powernow-k8:    2 : fid 0xe (2200 MHz), vid 0xc
 powernow-k8:    3 : fid 0xc (2000 MHz), vid 0xe
 powernow-k8:    4 : fid 0xa (1800 MHz), vid 0x10
 powernow-k8:    5 : fid 0x2 (1000 MHz), vid 0x12

Many thanks to everybody involved! I'll run my board now fulltime coreboot!

     Regards Andi


-------------- next part --------------
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 2.6.26-2-amd64 (Debian 2.6.26-17) (dannf at debian.org) (gcc version 4.1.3 20080704 (prerelease) (Debian 4.1.2-25)) #1 SMP Sun Jun 21 04:47:08 UTC 2009
[    0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-2.6.26-2-amd64 root=UUID=3f46729c-a47e-4b29-a5a6-6bbe2e6cc7a4 ro vga=791
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
[    0.000000]  BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 00000000bfff0000 (usable)
[    0.000000]  BIOS-e820: 00000000bfff0000 - 00000000c0000000 (reserved)
[    0.000000]  BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
[    0.000000] Entering add_active_range(0, 0, 159) 0 entries of 3200 used
[    0.000000] Entering add_active_range(0, 256, 786416) 1 entries of 3200 used
[    0.000000] Entering add_active_range(0, 1048576, 1310720) 2 entries of 3200 used
[    0.000000] max_pfn_mapped = 1310720
[    0.000000] init_memory_mapping
[    0.000000] DMI 2.4 present.
[    0.000000] ACPI: RSDP 000FD5F0, 0024 (r2 CORE  )
[    0.000000] ACPI: RSDT BFFF0424, 0040 (r1 CORE   RSDT            0 CORE        0)
[    0.000000] ACPI: FACP BFFF0F10, 00F4 (r1    GBT COREBOOT        0 CORE       2A)
[    0.000000] ACPI: DSDT BFFF04C0, 0A50 (r1 LXBIOS LXB-DSDT        1 INTL 20061109)
[    0.000000] ACPI: FACS BFFF0480, 0040
[    0.000000] ACPI: HPET BFFF1004, 0038 (r1 CORE   AMD64           0 CORE        0)
[    0.000000] ACPI: APIC BFFF103C, 0068 (r1 CORE   MADT            0 CORE        0)
[    0.000000] ACPI: MCFG BFFF10A4, 002C (r1 CORE   MCFG            0 CORE        0)
[    0.000000] ACPI: SRAT BFFF10D0, 00C8 (r1 CORE   SRAT            0 CORE        0)
[    0.000000] ACPI: SLIT BFFF1198, 002D (r1 CORE   SLIT            0 CORE        0)
[    0.000000] ACPI: SSDT BFFF11C5, 037A (r2 CORE   DYNADATA       2A GENA       2A)
[    0.000000] SRAT: PXM 0 -> APIC 0 -> Node 0
[    0.000000] SRAT: PXM 0 -> APIC 1 -> Node 0
[    0.000000] SRAT: Node 0 PXM 0 0-a0000
[    0.000000] Entering add_active_range(0, 0, 159) 0 entries of 3200 used
[    0.000000] SRAT: Node 0 PXM 0 100000-c0000000
[    0.000000] Entering add_active_range(0, 256, 786416) 1 entries of 3200 used
[    0.000000] SRAT: Node 0 PXM 0 100000000-140000000
[    0.000000] Entering add_active_range(0, 1048576, 1310720) 2 entries of 3200 used
[    0.000000] NUMA: Allocated memnodemap from d000 - f880
[    0.000000] NUMA: Using 20 for the hash shift.
[    0.000000] Bootmem setup node 0 0000000000000000-0000000140000000
[    0.000000]   NODE_DATA [000000000000f880 - 000000000001487f]
[    0.000000]   bootmap [0000000000015000 -  000000000003cfff] pages 28
[    0.000000]   early res: 0 [0-fff] BIOS data page
[    0.000000]   early res: 1 [6000-7fff] TRAMPOLINE
[    0.000000]   early res: 2 [200000-673397] TEXT DATA BSS
[    0.000000]   early res: 3 [3773a000-37fefd6d] RAMDISK
[    0.000000]   early res: 4 [9fc00-fffff] BIOS reserved
[    0.000000]   early res: 5 [8000-cfff] PGTABLE
[    0.000000]   early res: 6 [d000-f87f] MEMNODEMAP
[    0.000000]  [ffffe20000000000-ffffe20003bfffff] PMD -> [ffff810001200000-ffff810003ffffff] on node 0
[    0.000000]  [ffffe20003c00000-ffffe200045fffff] PMD -> [ffff81000c000000-ffff81000c9fffff] on node 0
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA             0 ->     4096
[    0.000000]   DMA32        4096 ->  1048576
[    0.000000]   Normal    1048576 ->  1310720
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[3] active PFN ranges
[    0.000000]     0:        0 ->      159
[    0.000000]     0:      256 ->   786416
[    0.000000]     0:  1048576 ->  1310720
[    0.000000] On node 0 totalpages: 1048463
[    0.000000]   DMA zone: 56 pages used for memmap
[    0.000000]   DMA zone: 1247 pages reserved
[    0.000000]   DMA zone: 2696 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 14280 pages used for memmap
[    0.000000]   DMA32 zone: 768040 pages, LIFO batch:31
[    0.000000]   Normal zone: 3584 pages used for memmap
[    0.000000]   Normal zone: 258560 pages, LIFO batch:31
[    0.000000]   Movable zone: 0 pages used for memmap
[    0.000000] ACPI: PM-Timer IO Port: 0x2008
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xf6244000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, version 0, address 0xf6244000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ2 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] Setting APIC routing to flat
[    0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000
[    0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000
[    0.000000] PM: Registered nosave memory: 00000000bfff0000 - 00000000c0000000
[    0.000000] PM: Registered nosave memory: 00000000c0000000 - 0000000100000000
[    0.000000] Allocating PCI resources starting at c4000000 (gap: c0000000:40000000)
[    0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs
[    0.000000] PERCPU: Allocating 37168 bytes of per cpu data
[    0.000000] NR_CPUS: 32, nr_cpu_ids: 2
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 1029296
[    0.000000] Policy zone: Normal
[    0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-2.6.26-2-amd64 root=UUID=3f46729c-a47e-4b29-a5a6-6bbe2e6cc7a4 ro vga=791
[    0.000000] Initializing CPU#0
[    0.000000] PID hash table entries: 4096 (order: 12, 32768 bytes)
[    0.000000] TSC calibrated against PM_TIMER
[    0.000000] Marking TSC unstable due to TSCs unsynchronized
[    0.000000] time.c: Detected 2500.009 MHz processor.
[    0.004000] Console: colour dummy device 80x25
[    0.004000] console [tty0] enabled
[    0.004000] Checking aperture...
[    0.004000] Node 0: aperture @ f0000000 size 64 MB
[    0.004000] Memory: 4122664k/5242880k available (2225k kernel code, 71188k reserved, 1080k data, 392k init)
[    0.004000] CPA: page pool initialized 1 of 1 pages preallocated
[    0.004000] hpet clockevent registered
[    0.083880] Calibrating delay using timer specific routine.. 5003.94 BogoMIPS (lpj=10007888)
[    0.083932] Security Framework initialized
[    0.083940] SELinux:  Disabled at boot.
[    0.083945] Capability LSM initialized
[    0.084005] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.084005] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.084005] Mount-cache hash table entries: 256
[    0.084005] Initializing cgroup subsys ns
[    0.084005] Initializing cgroup subsys cpuacct
[    0.084005] Initializing cgroup subsys devices
[    0.084005] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.084005] CPU: L2 Cache: 512K (64 bytes/line)
[    0.084005] CPU 0/0 -> Node 0
[    0.084005] CPU: Physical Processor ID: 0
[    0.084005] CPU: Processor Core ID: 0
[    0.084636] ACPI: Core revision 20080321
[    0.125980] CPU0: AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ stepping 01
[    0.125988] Using local APIC timer interrupts.
[    0.132008] APIC timer calibration result 12500062
[    0.132008] Detected 12.500 MHz APIC timer.
[    0.132008] Booting processor 1/1 ip 6000
[    0.140008] Initializing CPU#1
[    0.140008] Calibrating delay using timer specific routine.. 5000.12 BogoMIPS (lpj=10000242)
[    0.140008] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.140008] CPU: L2 Cache: 512K (64 bytes/line)
[    0.140008] CPU 1/1 -> Node 0
[    0.140008] CPU: Physical Processor ID: 0
[    0.140008] CPU: Processor Core ID: 1
[    0.219907] CPU1: AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ stepping 01
[    0.219945] Brought up 2 CPUs
[    0.219950] Total of 2 processors activated (10004.06 BogoMIPS).
[    0.220013] CPU0 attaching sched-domain:
[    0.220013]  domain 0: span 0-1
[    0.220013]   groups: 0 1
[    0.220013]   domain 1: span 0-1
[    0.220013]    groups: 0-1
[    0.220013] CPU1 attaching sched-domain:
[    0.220013]  domain 0: span 0-1
[    0.220013]   groups: 1 0
[    0.220013]   domain 1: span 0-1
[    0.220013]    groups: 0-1
[    0.220013] net_namespace: 1224 bytes
[    0.220013] Booting paravirtualized kernel on bare hardware
[    0.220013] NET: Registered protocol family 16
[    0.220013] node 0 link 0: io port [1000, 3fff]
[    0.220013] TOM: 00000000c0000000 aka 3072M
[    0.220013] node 0 link 0: mmio [a0000, bffff]
[    0.220013] node 0 link 0: mmio [f4000000, f62fffff]
[    0.220013] node 0 link 0: mmio [e0000000, efffffff]
[    0.220013] TOM2: 0000000140000000 aka 5120M
[    0.220013] bus: [00,07] on node 0 link 0
[    0.220013] bus: 00 index 0 io port: [0, ffff]
[    0.220013] bus: 00 index 1 mmio: [a0000, bffff]
[    0.220013] bus: 00 index 2 mmio: [f0000000, ffffffff]
[    0.220013] bus: 00 index 3 mmio: [c0000000, efffffff]
[    0.220013] bus: 00 index 4 mmio: [140000000, fcffffffff]
[    0.220013] ACPI: bus type pci registered
[    0.220013] ACPI: MMCONFIG has no entries
[    0.220013] PCI: Using configuration type 1 for base access
[    0.220013] ACPI: EC: Look up EC in DSDT
[    0.220013] ACPI: Interpreter enabled
[    0.220013] ACPI: (supports S0 S5)
[    0.220013] ACPI: Using IOAPIC for interrupt routing
[    0.220013] ACPI: MMCONFIG has no entries
[    0.220013] ACPI: PCI Root Bridge [PCI0] (0000:00)
[    0.220679] PCI: Transparent bridge - 0000:00:06.0
[    0.220877] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[    0.220916] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBF._PRT]
[    0.220934] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBE._PRT]
[    0.220953] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBD._PRT]
[    0.220971] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBC._PRT]
[    0.220989] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBB._PRT]
[    0.221008] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBA._PRT]
[    0.221026] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCID._PRT]
[    0.224014] Linux Plug and Play Support v0.97 (c) Adam Belay
[    0.224014] pnp: PnP ACPI init
[    0.224014] ACPI: bus type pnp registered
[    0.224014] pnp 00:00: parse allocated resources
[    0.225638] pnp 00:00:   add io  0xcf8-0xcff flags 0x1
[    0.225797] pnp 00:00: Plug and Play ACPI device, IDs PNP0a03 (active)
[    0.225826] pnp 00:01: parse allocated resources
[    0.225845] pnp 00:01:   add io  0x60-0x60 flags 0x1
[    0.225847] pnp 00:01:   add io  0x64-0x64 flags 0x1
[    0.225854] pnp 00:01:   add irq 1 flags 0x1
[    0.226010] pnp 00:01: Plug and Play ACPI device, IDs PNP0303 (active)
[    0.226030] pnp 00:02: parse allocated resources
[    0.226048] pnp 00:02:   add io  0x60-0x60 flags 0x1
[    0.226050] pnp 00:02:   add io  0x64-0x64 flags 0x1
[    0.226053] pnp 00:02:   add irq 12 flags 0x1
[    0.226210] pnp 00:02: Plug and Play ACPI device, IDs PNP0f13 (active)
[    0.226228] pnp 00:03: parse allocated resources
[    0.226247] pnp 00:03:   add io  0x3f0-0x3f5 flags 0x1
[    0.226249] pnp 00:03:   add io  0x3f7-0x3f7 flags 0x1
[    0.226252] pnp 00:03:   add irq 6 flags 0x1
[    0.226254] pnp 00:03:   add dma 2 flags 0x0
[    0.226411] pnp 00:03: Plug and Play ACPI device, IDs PNP0700 (active)
[    0.226414] pnp: PnP ACPI: found 4 devices
[    0.226419] ACPI: ACPI bus type pnp unregistered
[    0.227474] usbcore: registered new interface driver usbfs
[    0.227776] usbcore: registered new interface driver hub
[    0.228014] usbcore: registered new device driver usb
[    0.228014] PCI: Using ACPI for IRQ routing
[    0.244015] PCI-DMA: Disabling AGP.
[    0.244015] PCI-DMA: aperture base @ f0000000 size 65536 KB
[    0.244015] PCI-DMA: using GART IOMMU.
[    0.244015] PCI-DMA: Reserving 64MB of IOMMU area in the AGP aperture
[    0.244015] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 31
[    0.244015] hpet0: 3 32-bit timers, 25000000 Hz
[    0.245964] Switched to high resolution mode on CPU 0
[    0.248545] Switched to high resolution mode on CPU 1
[    0.257940] pnp: the driver 'system' has been registered
[    0.260005] PCI: Bridge: 0000:00:06.0
[    0.260005]   IO window: disabled.
[    0.260005]   MEM window: 0xf6100000-0xf61fffff
[    0.260005]   PREFETCH window: disabled.
[    0.260005] PCI: Bridge: 0000:00:0a.0
[    0.260005]   IO window: disabled.
[    0.260005]   MEM window: disabled.
[    0.260005]   PREFETCH window: disabled.
[    0.260005] PCI: Bridge: 0000:00:0b.0
[    0.260005]   IO window: disabled.
[    0.260005]   MEM window: disabled.
[    0.260005]   PREFETCH window: disabled.
[    0.260005] PCI: Bridge: 0000:00:0c.0
[    0.260005]   IO window: disabled.
[    0.260005]   MEM window: disabled.
[    0.260005]   PREFETCH window: disabled.
[    0.260005] PCI: Bridge: 0000:00:0d.0
[    0.260005]   IO window: disabled.
[    0.260005]   MEM window: disabled.
[    0.260005]   PREFETCH window: disabled.
[    0.260005] PCI: Bridge: 0000:00:0e.0
[    0.260005]   IO window: disabled.
[    0.260005]   MEM window: disabled.
[    0.260005]   PREFETCH window: disabled.
[    0.260005] PCI: Bridge: 0000:00:0f.0
[    0.260005]   IO window: 1000-1fff
[    0.260005]   MEM window: 0xf4000000-0xf60fffff
[    0.260005]   PREFETCH window: 0x00000000e0000000-0x00000000efffffff
[    0.260005] PCI: Setting latency timer of device 0000:00:06.0 to 64
[    0.260005] PCI: Setting latency timer of device 0000:00:0a.0 to 64
[    0.260005] PCI: Setting latency timer of device 0000:00:0b.0 to 64
[    0.260005] PCI: Setting latency timer of device 0000:00:0c.0 to 64
[    0.260005] PCI: Setting latency timer of device 0000:00:0d.0 to 64
[    0.260005] PCI: Setting latency timer of device 0000:00:0e.0 to 64
[    0.260005] PCI: Setting latency timer of device 0000:00:0f.0 to 64
[    0.260005] NET: Registered protocol family 2
[    0.293154] IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.297007] TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
[    0.301012] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    0.301012] TCP: Hash tables configured (established 524288 bind 65536)
[    0.301012] TCP reno registered
[    0.309109] NET: Registered protocol family 1
[    0.309215] checking if image is initramfs... it is
[    0.833007] Freeing initrd memory: 8919k freed
[    0.837012] platform rtc_cmos: registered platform RTC device (no PNP device found)
[    0.841008] audit: initializing netlink socket (disabled)
[    0.841008] type=2000 audit(1246450262.833:1): initialized
[    0.841008] Total HugeTLB memory allocated, 0
[    0.841045] VFS: Disk quotas dquot_6.5.1
[    0.841045] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.841045] msgmni has been set to 8069
[    0.841045] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[    0.841045] io scheduler noop registered
[    0.841045] io scheduler anticipatory registered
[    0.841045] io scheduler deadline registered
[    0.841045] io scheduler cfq registered (default)
[    0.841045] pci 0000:00:05.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:05.1: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:05.2: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:06.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:06.1: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:08.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:0a.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:0b.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:0c.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:0d.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:0e.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:00:0f.0: Enabling HT MSI Mapping
[    0.841045] pci 0000:07:00.0: Boot video device
[    0.841045] PCI: Setting latency timer of device 0000:00:0a.0 to 64
[    0.841045] assign_interrupt_mode Found MSI capability
[    0.841045] Allocate Port Service[0000:00:0a.0:pcie00]
[    0.841045] PCI: Setting latency timer of device 0000:00:0b.0 to 64
[    0.841045] assign_interrupt_mode Found MSI capability
[    0.841045] Allocate Port Service[0000:00:0b.0:pcie00]
[    0.841045] PCI: Setting latency timer of device 0000:00:0c.0 to 64
[    0.841045] assign_interrupt_mode Found MSI capability
[    0.841045] Allocate Port Service[0000:00:0c.0:pcie00]
[    0.841045] PCI: Setting latency timer of device 0000:00:0d.0 to 64
[    0.841045] assign_interrupt_mode Found MSI capability
[    0.841045] Allocate Port Service[0000:00:0d.0:pcie00]
[    0.841045] PCI: Setting latency timer of device 0000:00:0e.0 to 64
[    0.841045] assign_interrupt_mode Found MSI capability
[    0.841045] Allocate Port Service[0000:00:0e.0:pcie00]
[    0.841045] PCI: Setting latency timer of device 0000:00:0f.0 to 64
[    0.841045] assign_interrupt_mode Found MSI capability
[    0.841045] Allocate Port Service[0000:00:0f.0:pcie00]
[    0.841045] vesafb: framebuffer at 0xe0000000, mapped to 0xffffc20001080000, using 3072k, total 262144k
[    0.841045] vesafb: mode is 1024x768x16, linelength=2048, pages=1
[    0.841045] vesafb: scrolling: redraw
[    0.841045] vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0
[    0.851328] Console: switching to colour frame buffer device 128x48
[    0.863267] fb0: VESA VGA frame buffer device
[    0.867267] Linux agpgart interface v0.103
[    0.867267] Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
[    0.867267] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    0.867267] pnp: the driver 'serial' has been registered
[    0.867267] brd: module loaded
[    0.867267] input: Macintosh mouse button emulation as /class/input/input0
[    0.867267] pnp: the driver 'i8042 kbd' has been registered
[    0.867267] i8042 kbd 00:01: driver attached
[    0.867267] pnp: the driver 'i8042 aux' has been registered
[    0.867267] i8042 aux 00:02: driver attached
[    0.867267] PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
[    0.867267] serio: i8042 KBD port at 0x60,0x64 irq 1
[    0.867267] serio: i8042 AUX port at 0x60,0x64 irq 12
[    0.891268] mice: PS/2 mouse device common for all mice
[    0.891268] pnp: the driver 'rtc_cmos' has been registered
[    0.891268] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
[    0.891268] rtc0: alarms up to one day
[    0.908400] input: AT Translated Set 2 keyboard as /class/input/input1
[    0.923269] cpuidle: using governor ladder
[    0.923269] cpuidle: using governor menu
[    0.923269] No iBFT detected.
[    0.923269] TCP cubic registered
[    0.923269] NET: Registered protocol family 17
[    0.923269] registered taskstats version 1
[    0.923269] rtc_cmos rtc_cmos: setting system clock to 2009-07-01 12:11:03 UTC (1246450263)
[    0.923269] Freeing unused kernel memory: 392k freed
[    1.020457] device-mapper: uevent: version 1.0.3
[    1.022791] device-mapper: ioctl: 4.13.0-ioctl (2007-10-18) initialised: dm-devel at redhat.com
[    1.048484] ACPI: ACPI0007:00 is registered as cooling_device0
[    1.051630] ACPI: ACPI0007:01 is registered as cooling_device1
[    1.193359] Uniform Multi-Platform E-IDE driver
[    1.195997] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
[    1.200983] No dock devices found.
[    1.209017] SCSI subsystem initialized
[    1.216592] forcedeth: Reverse Engineered nForce ethernet driver. Version 0.61.
[    1.219592] ACPI: PCI Interrupt 0000:00:08.0[A] -> GSI 20 (level, low) -> IRQ 20
[    1.221027] PCI: Setting latency timer of device 0000:00:08.0 to 64
[    1.226436] libata version 3.00 loaded.
[    1.782453] forcedeth 0000:00:08.0: ifname eth0, PHY OUI 0x5043 @ 1, addr 00:e0:81:54:32:66
[    1.785997] forcedeth 0000:00:08.0: highdma csum vlan pwrctl mgmt timirq gbit lnktim msi desc-v3
[    1.793997] ACPI: PCI Interrupt 0000:00:02.1[B] -> GSI 23 (level, low) -> IRQ 23
[    1.797427] PCI: Setting latency timer of device 0000:00:02.1 to 64
[    1.797430] ehci_hcd 0000:00:02.1: EHCI Host Controller
[    1.801029] ehci_hcd 0000:00:02.1: new USB bus registered, assigned bus number 1
[    1.804621] ehci_hcd 0000:00:02.1: debug port 1
[    1.808187] PCI: cache line size of 64 is not supported by device 0000:00:02.1
[    1.808199] ehci_hcd 0000:00:02.1: irq 23, io mem 0xf624a000
[    1.824769] ehci_hcd 0000:00:02.1: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004
[    1.828493] usb usb1: configuration #1 chosen from 1 choice
[    1.830032] hub 1-0:1.0: USB hub found
[    1.833860] hub 1-0:1.0: 10 ports detected
[    1.942125] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    1.946141] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.954141] usb usb1: Product: EHCI Host Controller
[    1.958215] usb usb1: Manufacturer: Linux 2.6.26-2-amd64 ehci_hcd
[    1.962244] usb usb1: SerialNumber: 0000:00:02.1
[    1.966294] NFORCE-MCP55: 0000:00:04.0 (rev a1) UDMA133 controller
[    1.970299] NFORCE-MCP55: IDE controller (0x10de:0x036e rev 0xa1) at  PCI slot 0000:00:04.0
[    1.974378] NFORCE-MCP55: not 100% native mode: will probe irqs later
[    1.974541] NFORCE-MCP55: IDE port disabled
[    1.978550] PCI: Setting latency timer of device 0000:00:04.0 to 64
[    1.978553]     ide0: BM-DMA at 0x2cc0-0x2cc7
[    1.984961] Probing IDE interface ide0...
[    2.722262] hda: Optiarc DVD RW AD-7173A, ATAPI CD/DVD-ROM drive
[    3.398395] hda: host max PIO5 wanted PIO255(auto-tune) selected PIO4
[    3.398495] hda: host side 80-wire cable detection failed, limiting max speed to UDMA33
[    3.402615] hda: UDMA/33 mode selected
[    3.410689] ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
[    3.414908] sata_nv 0000:00:05.0: version 3.5
[    3.414908] ACPI: PCI Interrupt 0000:00:05.0[A] -> GSI 20 (level, low) -> IRQ 20
[    3.418912] sata_nv 0000:00:05.0: Using SWNCQ mode
[    3.423213] PCI: Setting latency timer of device 0000:00:05.0 to 64
[    3.423265] scsi0 : sata_nv
[    3.427489] scsi1 : sata_nv
[    3.431518] ata1: SATA max UDMA/133 cmd 0x3000 ctl 0x3070 bmdma 0x2cd0 irq 20
[    3.435622] ata2: SATA max UDMA/133 cmd 0x3010 ctl 0x3080 bmdma 0x2cd8 irq 20
[    3.931722] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[    3.943720] ata1.00: HPA detected: current 488395055, native 488397168
[    3.947146] ata1.00: ATA-7: SAMSUNG SP2504C, VT100-50, max UDMA7
[    3.951307] ata1.00: 488395055 sectors, multi 0: LBA48 NCQ (depth 31/32)
[    3.986921] ata1.00: configured for UDMA/133
[    4.355604] ata2: SATA link down (SStatus 0 SControl 300)
[    4.391484] scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG SP2504C  VT10 PQ: 0 ANSI: 5
[    4.397093] ACPI: PCI Interrupt 0000:00:05.1[B] -> GSI 21 (level, low) -> IRQ 21
[    4.401097] sata_nv 0000:00:05.1: Using SWNCQ mode
[    4.405100] PCI: Setting latency timer of device 0000:00:05.1 to 64
[    4.405250] scsi2 : sata_nv
[    4.409279] scsi3 : sata_nv
[    4.409306] ata3: SATA max UDMA/133 cmd 0x3020 ctl 0x3090 bmdma 0x2ce0 irq 21
[    4.413283] ata4: SATA max UDMA/133 cmd 0x3030 ctl 0x30a0 bmdma 0x2ce8 irq 21
[    4.793082] ata3: SATA link down (SStatus 0 SControl 300)
[    5.172991] ata4: SATA link down (SStatus 0 SControl 300)
[    5.212984] ACPI: PCI Interrupt 0000:00:05.2[C] -> GSI 22 (level, low) -> IRQ 22
[    5.213712] sata_nv 0000:00:05.2: Using SWNCQ mode
[    5.217753] PCI: Setting latency timer of device 0000:00:05.2 to 64
[    5.220555] scsi4 : sata_nv
[    5.225047] scsi5 : sata_nv
[    5.225047] ata5: SATA max UDMA/133 cmd 0x3040 ctl 0x30b0 bmdma 0x2cf0 irq 22
[    5.229052] ata6: SATA max UDMA/133 cmd 0x3050 ctl 0x30c0 bmdma 0x2cf8 irq 22
[    5.604877] ata5: SATA link down (SStatus 0 SControl 300)
[    5.995696] ata6: SATA link down (SStatus 0 SControl 300)
[    6.027615] ohci_hcd: 2006 August 04 USB 1.1 'Open' Host Controller (OHCI) Driver
[    6.027615] ACPI: PCI Interrupt 0000:01:08.0[A] -> GSI 16 (level, low) -> IRQ 16
[    6.028439] udev: renamed network interface eth0 to eth2
[    6.037027] ACPI: PCI Interrupt 0000:00:02.0[A] -> GSI 22 (level, low) -> IRQ 22
[    6.037044] PCI: Setting latency timer of device 0000:00:02.0 to 64
[    6.037047] ohci_hcd 0000:00:02.0: OHCI Host Controller
[    6.039718] ohci_hcd 0000:00:02.0: new USB bus registered, assigned bus number 2
[    6.043526] ohci_hcd 0000:00:02.0: irq 22, io mem 0xf6245000
[    6.088993] ssb: Sonics Silicon Backplane found on PCI device 0000:01:08.0
[    6.092470] ACPI: PCI Interrupt 0000:01:0a.0[A] -> GSI 18 (level, low) -> IRQ 18
[    6.106023] usb usb2: configuration #1 chosen from 1 choice
[    6.109643] hub 2-0:1.0: USB hub found
[    6.113623] hub 2-0:1.0: 10 ports detected
[    6.150023] ohci1394: fw-host0: OHCI-1394 1.1 (PCI): IRQ=[18]  MMIO=[f6106000-f61067ff]  Max Packet=[2048]  IR/IT contexts=[4/8]
[    6.219059] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
[    6.222797] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    6.226797] usb usb2: Product: OHCI Host Controller
[    6.230860] usb usb2: Manufacturer: Linux 2.6.26-2-amd64 ohci_hcd
[    6.235268] usb usb2: SerialNumber: 0000:00:02.0
[    6.249613] hda: ATAPI 48X DVD-ROM DVD-R-RAM CD-R/RW drive, 2048kB Cache
[    6.251326] Uniform CD-ROM driver Revision: 3.20
[    6.349122] Driver 'sd' needs updating - please use bus_type methods
[    6.353455] sd 0:0:0:0: [sda] 488395055 512-byte hardware sectors (250058 MB)
[    6.355350] sd 0:0:0:0: [sda] Write Protect is off
[    6.359281] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    6.359306] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    6.363239] sd 0:0:0:0: [sda] 488395055 512-byte hardware sectors (250058 MB)
[    6.367104] sd 0:0:0:0: [sda] Write Protect is off
[    6.370902] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    6.370923] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    6.374811]  sda: sda1 sda2 sda3 sda4 < sda5 sda6 >
[    6.429595] sd 0:0:0:0: [sda] Attached SCSI disk
[    6.535934] usb 2-9: new low speed USB device using ohci_hcd and address 2
[    6.774592] usb 2-9: configuration #1 chosen from 1 choice
[    6.783452] usb 2-9: New USB device found, idVendor=1241, idProduct=1166
[    6.787522] usb 2-9: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    6.805297] usbcore: registered new interface driver hiddev
[    6.818292] input: HID 1241:1166 as /class/input/input2
[    6.845781] input,hidraw0: USB HID v1.00 Mouse [HID 1241:1166] on usb-0000:00:02.0-9
[    6.850106] usbcore: registered new interface driver usbhid
[    6.853939] usbhid: v2.6:USB HID core driver
[    6.919130] PM: Starting manual resume from disk
[    7.002252] kjournald starting.  Commit interval 5 seconds
[    7.006271] EXT3-fs: mounted filesystem with ordered data mode.
[    7.477903] ieee1394: Host added: ID:BUS[0-00:1023]  GUID[0016e65600b7173c]
[    8.536191] udev: starting version 141
[    8.542707] udev: deprecated sysfs layout; update the kernel or disable CONFIG_SYSFS_DEPRECATED; some udev features will not work correctly
[    9.273694] input: Power Button (FF) as /class/input/input3
[    9.327263] ACPI: Power Button (FF) [PWRF]
[    9.365918] input: PC Speaker as /class/input/input4
[    9.687281] i2c-adapter i2c-0: nForce2 SMBus adapter at 0x2c40
[    9.692002] i2c-adapter i2c-1: nForce2 SMBus adapter at 0x2c80
[   10.159747] b43-phy0: Broadcom 4318 WLAN found
[   10.233475] phy0: Selected rate control algorithm 'pid'
[   10.241476] ACPI: PCI Interrupt 0000:00:06.1[B] -> GSI 23 (level, low) -> IRQ 23
[   10.246020] PCI: Setting latency timer of device 0000:00:06.1 to 64
[   10.283438] hda_codec: Unknown model for ALC883, trying auto-probe from BIOS...
[   10.291827] Broadcom 43xx driver loaded [ Features: PMLR, Firmware-ID: FW13 ]
[   11.677423] Adding 7815580k swap on /dev/sda1.  Priority:-1 extents:1 across:7815580k
[   12.392475] EXT3 FS on sda2, internal journal
[   12.725728] loop: module loaded
[   12.833626] powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ processors (2 cpu cores) (version 2.20.00)
[   12.855000] powernow-k8:    0 : fid 0x11 (2500 MHz), vid 0x9
[   12.865352] powernow-k8:    1 : fid 0x10 (2400 MHz), vid 0xa
[   12.869671] powernow-k8:    2 : fid 0xe (2200 MHz), vid 0xc
[   12.873918] powernow-k8:    3 : fid 0xc (2000 MHz), vid 0xe
[   12.878094] powernow-k8:    4 : fid 0x2 (1000 MHz), vid 0x12
[   12.882240] powernow-k8: ph2 null fid transition 0x11
[   12.945434] it87: Found IT8716F chip at 0x290, revision 0
[   12.949446] it87: in3 is VCC (+5V)
[   12.953424] it87: in7 is VCCH (+5V Stand-By)
[   14.656024] kjournald starting.  Commit interval 5 seconds
[   14.700658] EXT3 FS on sda3, internal journal
[   14.704649] EXT3-fs: mounted filesystem with ordered data mode.
[   14.732146] kjournald starting.  Commit interval 5 seconds
[   14.738243] EXT3 FS on sda5, internal journal
[   14.742088] EXT3-fs: mounted filesystem with ordered data mode.
[   16.053423] ip_tables: (C) 2000-2006 Netfilter Core Team
[   16.098329] nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
[   16.295387] eth2: no link during initialization.
[   16.713875] input: b43-phy0 as /class/input/input5
[   16.829132] firmware: requesting b43/ucode5.fw
[   16.917097] firmware: requesting b43/pcm5.fw
[   16.956739] firmware: requesting b43/b0g0initvals5.fw
[   16.997853] firmware: requesting b43/b0g0bsinitvals5.fw
[   17.092117] b43-phy0: Loading firmware version 410.2160 (2015-15-255 15:32:10)
[   17.642544] NET: Registered protocol family 10
[   18.146380] Registered led device: b43-phy0::tx
[   18.152926] Registered led device: b43-phy0::rx
[   18.156572] Registered led device: b43-phy0::radio
[   18.235895] lo: Disabled Privacy Extensions
[   18.240148] ADDRCONF(NETDEV_UP): eth2: link is not ready
[   18.244367] ADDRCONF(NETDEV_UP): wlan0: link is not ready
[   19.390047] wlan0: Initial auth_alg=0
[   19.390051] wlan0: authenticate with AP 00:13:49:b1:2e:1c
[   19.391422] wlan0: RX authentication from 00:13:49:b1:2e:1c (alg=0 transaction=2 status=0)
[   19.391422] wlan0: authenticated
[   19.391422] wlan0: associate with AP 00:13:49:b1:2e:1c
[   19.391422] wlan0: RX AssocResp from 00:13:49:b1:2e:1c (capab=0x411 status=0 aid=1)
[   19.391422] wlan0: associated
[   19.391422] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
[   19.446094] wlan0: CTS protection enabled (BSSID=00:13:49:b1:2e:1c)
[   19.446094] wlan0: switched to short barker preamble (BSSID=00:13:49:b1:2e:1c)
[   34.998896] wlan0: no IPv6 routers present
[   35.249519] RPC: Registered udp transport module.
[   35.250607] RPC: Registered tcp transport module.
[   35.381043] Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
[   41.517954] Clocksource tsc unstable (delta = -298205271 ns)
[   46.091705] NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
[   46.109336] NFSD: starting 90-second grace period
[   54.387273] pnp: the driver 'parport_pc' has been registered
[   54.388956] lp: driver loaded but no devices found
[   54.409159] ppdev: user-space parallel port driver
[   56.902065] mtrr: type mismatch for e0000000,10000000 old: write-back new: write-combining
[   74.702276] CPU0 attaching NULL sched-domain.
[   74.702284] CPU1 attaching NULL sched-domain.
[   74.721068] CPU0 attaching sched-domain:
[   74.721072]  domain 0: span 0-1
[   74.721074]   groups: 0 1
[   74.721076]   domain 1: span 0-1
[   74.721078]    groups: 0-1
[   74.721080] CPU1 attaching sched-domain:
[   74.721082]  domain 0: span 0-1
[   74.721083]   groups: 1 0
[   74.721086]   domain 1: span 0-1
[   74.721087]    groups: 0-1
-------------- next part --------------
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 2.6.26-2-amd64 (Debian 2.6.26-17) (dannf at debian.org) (gcc version 4.1.3 20080704 (prerelease) (Debian 4.1.2-25)) #1 SMP Sun Jun 21 04:47:08 UTC 2009
[    0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-2.6.26-2-amd64 root=UUID=3f46729c-a47e-4b29-a5a6-6bbe2e6cc7a4 ro vga=791
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f800 (usable)
[    0.000000]  BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 00000000cfff0000 (usable)
[    0.000000]  BIOS-e820: 00000000cfff0000 - 00000000cfff3000 (ACPI NVS)
[    0.000000]  BIOS-e820: 00000000cfff3000 - 00000000d0000000 (ACPI data)
[    0.000000]  BIOS-e820: 00000000d0000000 - 00000000e0000000 (reserved)
[    0.000000]  BIOS-e820: 00000000f0000000 - 00000000f8000000 (reserved)
[    0.000000]  BIOS-e820: 00000000fec00000 - 0000000100000000 (reserved)
[    0.000000]  BIOS-e820: 0000000100000000 - 0000000130000000 (usable)
[    0.000000] Entering add_active_range(0, 0, 159) 0 entries of 3200 used
[    0.000000] Entering add_active_range(0, 256, 851952) 1 entries of 3200 used
[    0.000000] Entering add_active_range(0, 1048576, 1245184) 2 entries of 3200 used
[    0.000000] max_pfn_mapped = 1245184
[    0.000000] init_memory_mapping
[    0.000000] DMI 2.3 present.
[    0.000000] ACPI: RSDP 000F6640, 0014 (r0 GBT   )
[    0.000000] ACPI: RSDT CFFF3000, 0038 (r1 GBT    NVDAACPI 42302E31 NVDA  1010101)
[    0.000000] ACPI: FACP CFFF3040, 0074 (r1 GBT    NVDAACPI 42302E31 NVDA  1010101)
[    0.000000] ACPI: DSDT CFFF30C0, 4C8E (r1 GBT    NVDAACPI     1000 MSFT  100000C)
[    0.000000] ACPI: FACS CFFF0000, 0040
[    0.000000] ACPI: SSDT CFFF7E40, 028A (r1 PTLTD  POWERNOW        1  LTP        1)
[    0.000000] ACPI: HPET CFFF8100, 0038 (r1 GBT    NVDAACPI 42302E31 NVDA       98)
[    0.000000] ACPI: MCFG CFFF8140, 003C (r1 GBT    NVDAACPI 42302E31 NVDA  1010101)
[    0.000000] ACPI: APIC CFFF7D80, 0098 (r1 GBT    NVDAACPI 42302E31 NVDA  1010101)
[    0.000000] Scanning NUMA topology in Northbridge 24
[    0.000000] No NUMA configuration found
[    0.000000] Faking a node at 0000000000000000-0000000130000000
[    0.000000] Entering add_active_range(0, 0, 159) 0 entries of 3200 used
[    0.000000] Entering add_active_range(0, 256, 851952) 1 entries of 3200 used
[    0.000000] Entering add_active_range(0, 1048576, 1245184) 2 entries of 3200 used
[    0.000000] Bootmem setup node 0 0000000000000000-0000000130000000
[    0.000000]   NODE_DATA [000000000000e000 - 0000000000012fff]
[    0.000000]   bootmap [0000000000013000 -  0000000000038fff] pages 26
[    0.000000]   early res: 0 [0-fff] BIOS data page
[    0.000000]   early res: 1 [6000-7fff] TRAMPOLINE
[    0.000000]   early res: 2 [200000-673397] TEXT DATA BSS
[    0.000000]   early res: 3 [3773a000-37fefd6d] RAMDISK
[    0.000000]   early res: 4 [9f800-fffff] BIOS reserved
[    0.000000]   early res: 5 [8000-dfff] PGTABLE
[    0.000000]  [ffffe20000000000-ffffe20002dfffff] PMD -> [ffff810001200000-ffff810003ffffff] on node 0
[    0.000000]  [ffffe20003800000-ffffe200043fffff] PMD -> [ffff81000c000000-ffff81000cbfffff] on node 0
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA             0 ->     4096
[    0.000000]   DMA32        4096 ->  1048576
[    0.000000]   Normal    1048576 ->  1245184
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[3] active PFN ranges
[    0.000000]     0:        0 ->      159
[    0.000000]     0:      256 ->   851952
[    0.000000]     0:  1048576 ->  1245184
[    0.000000] On node 0 totalpages: 1048463
[    0.000000]   DMA zone: 56 pages used for memmap
[    0.000000]   DMA zone: 1246 pages reserved
[    0.000000]   DMA zone: 2697 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 14280 pages used for memmap
[    0.000000]   DMA32 zone: 833576 pages, LIFO batch:31
[    0.000000]   Normal zone: 2688 pages used for memmap
[    0.000000]   Normal zone: 193920 pages, LIFO batch:31
[    0.000000]   Movable zone: 0 pages used for memmap
[    0.000000] Detected use of extended apic ids on hypertransport bus
[    0.000000] ACPI: PM-Timer IO Port: 0x1008
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled)
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] dfl dfl lint[0x1])
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] dfl dfl lint[0x1])
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] dfl dfl lint[0x1])
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] dfl dfl lint[0x1])
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, version 0, address 0xfec00000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 14 global_irq 14 high edge)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 15 global_irq 15 high edge)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ2 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] ACPI: IRQ14 used by override.
[    0.000000] ACPI: IRQ15 used by override.
[    0.000000] Setting APIC routing to flat
[    0.000000] ACPI: HPET id: 0x10b9a201 base: 0xfefffc00
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000
[    0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000
[    0.000000] PM: Registered nosave memory: 00000000cfff0000 - 00000000cfff3000
[    0.000000] PM: Registered nosave memory: 00000000cfff3000 - 00000000d0000000
[    0.000000] PM: Registered nosave memory: 00000000d0000000 - 00000000e0000000
[    0.000000] PM: Registered nosave memory: 00000000e0000000 - 00000000f0000000
[    0.000000] PM: Registered nosave memory: 00000000f0000000 - 00000000f8000000
[    0.000000] PM: Registered nosave memory: 00000000f8000000 - 00000000fec00000
[    0.000000] PM: Registered nosave memory: 00000000fec00000 - 0000000100000000
[    0.000000] Allocating PCI resources starting at e1000000 (gap: e0000000:10000000)
[    0.000000] SMP: Allowing 4 CPUs, 2 hotplug CPUs
[    0.000000] PERCPU: Allocating 37168 bytes of per cpu data
[    0.000000] NR_CPUS: 32, nr_cpu_ids: 4
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 1030193
[    0.000000] Policy zone: Normal
[    0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-2.6.26-2-amd64 root=UUID=3f46729c-a47e-4b29-a5a6-6bbe2e6cc7a4 ro vga=791
[    0.000000] Initializing CPU#0
[    0.000000] PID hash table entries: 4096 (order: 12, 32768 bytes)
[    0.000000] TSC calibrated against PM_TIMER
[    0.000000] Marking TSC unstable due to TSCs unsynchronized
[    0.000000] time.c: Detected 2512.872 MHz processor.
[    0.004000] spurious 8259A interrupt: IRQ7.
[    0.004000] Console: colour dummy device 80x25
[    0.004000] console [tty0] enabled
[    0.004000] Checking aperture...
[    0.004000] Node 0: aperture @ 1c46000000 size 32 MB
[    0.004000] Aperture beyond 4GB. Ignoring.
[    0.004000] No AGP bridge found
[    0.004000] Your BIOS doesn't leave a aperture memory hole
[    0.004000] Please enable the IOMMU option in the BIOS setup
[    0.004000] This costs you 64 MB of RAM
[    0.004000] Mapping aperture over 65536 KB of RAM @ 4000000
[    0.004000] PM: Registered nosave memory: 0000000004000000 - 0000000008000000
[    0.004000] Memory: 4055004k/4980736k available (2225k kernel code, 138848k reserved, 1080k data, 392k init)
[    0.004000] CPA: page pool initialized 1 of 1 pages preallocated
[    0.004000] hpet clockevent registered
[    0.083900] Calibrating delay using timer specific routine.. 5029.71 BogoMIPS (lpj=10059431)
[    0.083951] Security Framework initialized
[    0.083958] SELinux:  Disabled at boot.
[    0.083964] Capability LSM initialized
[    0.084005] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.084005] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.084005] Mount-cache hash table entries: 256
[    0.084005] Initializing cgroup subsys ns
[    0.084005] Initializing cgroup subsys cpuacct
[    0.084005] Initializing cgroup subsys devices
[    0.084005] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.084005] CPU: L2 Cache: 512K (64 bytes/line)
[    0.084005] CPU 0/0 -> Node 0
[    0.084005] CPU: Physical Processor ID: 0
[    0.084005] CPU: Processor Core ID: 0
[    0.084623] ACPI: Core revision 20080321
[    0.133120] CPU0: AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ stepping 01
[    0.133129] Using local APIC timer interrupts.
[    0.140008] APIC timer calibration result 12564374
[    0.140008] Detected 12.564 MHz APIC timer.
[    0.140008] Booting processor 1/1 ip 6000
[    0.148009] Initializing CPU#1
[    0.148009] Calibrating delay using timer specific routine.. 5025.82 BogoMIPS (lpj=10051645)
[    0.148009] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
[    0.148009] CPU: L2 Cache: 512K (64 bytes/line)
[    0.148009] CPU 1/1 -> Node 0
[    0.148009] CPU: Physical Processor ID: 0
[    0.148009] CPU: Processor Core ID: 1
[    0.227936] CPU1: AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ stepping 01
[    0.227974] Brought up 2 CPUs
[    0.227979] Total of 2 processors activated (10055.53 BogoMIPS).
[    0.228014] CPU0 attaching sched-domain:
[    0.228014]  domain 0: span 0-1
[    0.228014]   groups: 0 1
[    0.228014]   domain 1: span 0-1
[    0.228014]    groups: 0-1
[    0.228014] CPU1 attaching sched-domain:
[    0.228014]  domain 0: span 0-1
[    0.228014]   groups: 1 0
[    0.228014]   domain 1: span 0-1
[    0.228014]    groups: 0-1
[    0.228014] net_namespace: 1224 bytes
[    0.228014] Booting paravirtualized kernel on bare hardware
[    0.228014] NET: Registered protocol family 16
[    0.228014] node 0 link 0: io port [1000, fffff]
[    0.228014] TOM: 00000000d0000000 aka 3328M
[    0.228014] node 0 link 0: mmio [f0000000, f7ffffff]
[    0.228014] node 0 link 0: mmio [a0000, bffff]
[    0.228014] node 0 link 0: mmio [d0000000, ffb7ffff]
[    0.228014] TOM2: 0000000130000000 aka 4864M
[    0.228014] bus: [00,ff] on node 0 link 0
[    0.228014] bus: 00 index 0 io port: [0, ffff]
[    0.228014] bus: 00 index 1 mmio: [d0000000, ffffffff]
[    0.228014] bus: 00 index 2 mmio: [a0000, bffff]
[    0.228014] bus: 00 index 3 mmio: [130000000, fcffffffff]
[    0.228014] ACPI: bus type pci registered
[    0.228014] PCI: MCFG configuration 0: base f0000000 segment 0 buses 0 - 127
[    0.228014] PCI: MCFG area at f0000000 reserved in E820
[    0.235014] PCI: Using MMCONFIG at f0000000 - f7ffffff
[    0.235021] PCI: Using configuration type 1 for base access
[    0.236014] ACPI: EC: Look up EC in DSDT
[    0.246218] ACPI: Interpreter enabled
[    0.246226] ACPI: (supports S0 S1 S4 S5)
[    0.246244] ACPI: Using IOAPIC for interrupt routing
[    0.254983] ACPI: PCI Root Bridge [PCI0] (0000:00)
[    0.254983] PCI: Transparent bridge - 0000:00:06.0
[    0.254983] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[    0.254983] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.HUB0._PRT]
[    0.302877] ACPI: PCI Interrupt Link [LNK1] (IRQs 5 7 9 10 11 14 *15)
[    0.302986] ACPI: PCI Interrupt Link [LNK2] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.302986] ACPI: PCI Interrupt Link [LNK3] (IRQs *5 7 9 10 11 14 15)
[    0.302986] ACPI: PCI Interrupt Link [LNK4] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.302986] ACPI: PCI Interrupt Link [LNK5] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.302986] ACPI: PCI Interrupt Link [LNK6] (IRQs 5 7 9 10 *11 14 15)
[    0.302986] ACPI: PCI Interrupt Link [LNK7] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.302986] ACPI: PCI Interrupt Link [LNK8] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.302986] ACPI: PCI Interrupt Link [LP2P] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.302986] ACPI: PCI Interrupt Link [LUBA] (IRQs 5 7 9 10 *11 14 15)
[    0.302986] ACPI: PCI Interrupt Link [LMAC] (IRQs *5 7 9 10 11 14 15)
[    0.302986] ACPI: PCI Interrupt Link [LAZA] (IRQs 5 7 9 *10 11 14 15)
[    0.302986] ACPI: PCI Interrupt Link [LPMU] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.303146] ACPI: PCI Interrupt Link [LSMB] (IRQs 5 7 9 *10 11 14 15)
[    0.305425] ACPI: PCI Interrupt Link [LUB2] (IRQs 5 7 9 10 11 14 *15)
[    0.305578] ACPI: PCI Interrupt Link [LIDE] (IRQs 5 7 9 10 11 14 15) *0, disabled.
[    0.305735] ACPI: PCI Interrupt Link [LSID] (IRQs 5 7 9 10 *11 14 15)
[    0.305889] ACPI: PCI Interrupt Link [LFID] (IRQs 5 7 9 10 11 14 *15)
[    0.306044] ACPI: PCI Interrupt Link [LSA2] (IRQs 5 7 9 *10 11 14 15)
[    0.306242] ACPI: PCI Interrupt Link [APC1] (IRQs 16) *0
[    0.306434] ACPI: PCI Interrupt Link [APC2] (IRQs 17) *0, disabled.
[    0.306626] ACPI: PCI Interrupt Link [APC3] (IRQs 18) *0
[    0.306817] ACPI: PCI Interrupt Link [APC4] (IRQs 19) *0, disabled.
[    0.307008] ACPI: PCI Interrupt Link [APC5] (IRQs 16) *0, disabled.
[    0.307199] ACPI: PCI Interrupt Link [APC6] (IRQs 16) *0
[    0.307390] ACPI: PCI Interrupt Link [APC7] (IRQs 16) *0, disabled.
[    0.307582] ACPI: PCI Interrupt Link [APC8] (IRQs 16) *0, disabled.
[    0.307774] ACPI: PCI Interrupt Link [APCF] (IRQs 20 21 22 23) *0
[    0.307966] ACPI: PCI Interrupt Link [APCH] (IRQs 20 21 22 23) *0
[    0.308157] ACPI: PCI Interrupt Link [APMU] (IRQs 20 21 22 23) *0, disabled.
[    0.308350] ACPI: PCI Interrupt Link [AAZA] (IRQs 20 21 22 23) *0
[    0.308542] ACPI: PCI Interrupt Link [APCS] (IRQs 20 21 22 23) *0
[    0.308736] ACPI: PCI Interrupt Link [APCL] (IRQs 20 21 22 23) *0
[    0.308928] ACPI: PCI Interrupt Link [APCM] (IRQs 20 21 22 23) *0, disabled.
[    0.309110] ACPI: PCI Interrupt Link [APCZ] (IRQs 20 21 22 23) *0, disabled.
[    0.309419] ACPI: PCI Interrupt Link [APSI] (IRQs 20 21 22 23) *0
[    0.309612] ACPI: PCI Interrupt Link [APSJ] (IRQs 20 21 22 23) *0
[    0.309804] ACPI: PCI Interrupt Link [ASA2] (IRQs 20 21 22 23) *0
[    0.310205] Linux Plug and Play Support v0.97 (c) Adam Belay
[    0.310354] pnp: PnP ACPI init
[    0.310365] ACPI: bus type pnp registered
[    0.310443] pnp 00:00: parse allocated resources
[    0.310527] pnp 00:00:   add io  0xcf8-0xcff flags 0x1
[    0.310699] pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
[    0.310712] pnp 00:01: parse allocated resources
[    0.310807] pnp 00:01:   add io  0x1000-0x107f flags 0x1
[    0.310809] pnp 00:01:   add io  0x1080-0x10ff flags 0x1
[    0.310811] pnp 00:01:   add io  0x1400-0x147f flags 0x1
[    0.310813] pnp 00:01:   add io  0x1480-0x14ff flags 0x1
[    0.310815] pnp 00:01:   add io  0x1800-0x187f flags 0x1
[    0.310816] pnp 00:01:   add io  0x1880-0x18ff flags 0x1
[    0.310819] pnp 00:01:   add mem 0xd0000000-0xdfffffff flags 0x1
[    0.310821] pnp 00:01: PNP0c02: calling quirk_system_pci_resources+0x0/0x15c
[    0.310997] pnp 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.312633] pnp 00:02: parse allocated resources
[    0.312639] pnp 00:02:   add io  0x10-0x1f flags 0x1
[    0.312641] pnp 00:02:   add io  0x22-0x3f flags 0x1
[    0.312643] pnp 00:02:   add io  0x44-0x5f flags 0x1
[    0.312645] pnp 00:02:   add io  0x62-0x63 flags 0x1
[    0.312647] pnp 00:02:   add io  0x65-0x6f flags 0x1
[    0.312649] pnp 00:02:   add io  0x74-0x7f flags 0x1
[    0.312650] pnp 00:02:   add io  0x91-0x93 flags 0x1
[    0.312652] pnp 00:02:   add io  0xa2-0xbf flags 0x1
[    0.312654] pnp 00:02:   add io  0xe0-0xef flags 0x1
[    0.312656] pnp 00:02:   add io  0x4d0-0x4d1 flags 0x1
[    0.312658] pnp 00:02:   add io  0x800-0x87f flags 0x1
[    0.312659] pnp 00:02:   add io  0x295-0x314 flags 0x1
[    0.312661] pnp 00:02:   add io  0x290-0x294 flags 0x1
[    0.312664] pnp 00:02: PNP0c02: calling quirk_system_pci_resources+0x0/0x15c
[    0.312844] pnp 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.312857] pnp 00:03: parse allocated resources
[    0.312862] pnp 00:03:   add dma 4 flags 0x4
[    0.312864] pnp 00:03:   add io  0x0-0xf flags 0x1
[    0.312866] pnp 00:03:   add io  0x80-0x90 flags 0x1
[    0.312868] pnp 00:03:   add io  0x94-0x9f flags 0x1
[    0.312869] pnp 00:03:   add io  0xc0-0xdf flags 0x1
[    0.313031] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active)
[    0.313092] pnp 00:04: parse allocated resources
[    0.313149] pnp 00:04:   add irq 8 flags 0x1
[    0.313151] pnp 00:04:   add mem 0xfefffc00-0xfeffffff flags 0x1
[    0.313223] pnp 00:04: Plug and Play ACPI device, IDs PNP0103 (active)
[    0.313223] pnp 00:05: parse allocated resources
[    0.313223] pnp 00:05:   add io  0x70-0x73 flags 0x1
[    0.313223] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.313223] pnp 00:06: parse allocated resources
[    0.313223] pnp 00:06:   add io  0x61-0x61 flags 0x1
[    0.313223] pnp 00:06: Plug and Play ACPI device, IDs PNP0800 (active)
[    0.313223] pnp 00:07: parse allocated resources
[    0.313223] pnp 00:07:   add io  0xf0-0xff flags 0x1
[    0.313223] pnp 00:07:   add irq 13 flags 0x1
[    0.313223] pnp 00:07: Plug and Play ACPI device, IDs PNP0c04 (active)
[    0.313223] pnp 00:08: parse allocated resources
[    0.313223] pnp 00:08:   add io  0x3f8-0x3ff flags 0x1
[    0.313223] pnp 00:08:   add irq 4 flags 0x1
[    0.313223] pnp 00:08: parse resource options
[    0.313223] pnp 00:08: new independent option
[    0.313223] pnp 00:08: new dependent option (priority 0x1)
[    0.313223] pnp 00:08:   io  min 0x3f8 max 0x3f8 align 1 size 8 flags 0x1
[    0.313223] pnp 00:08:   irq bitmask 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00001eb8 flags 0x1
[    0.313223] pnp 00:08: new dependent option (priority 0x1)
[    0.313223] pnp 00:08:   io  min 0x2f8 max 0x2f8 align 1 size 8 flags 0x1
[    0.313223] pnp 00:08:   irq bitmask 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00001eb8 flags 0x1
[    0.313223] pnp 00:08: new dependent option (priority 0x1)
[    0.313223] pnp 00:08:   io  min 0x3e8 max 0x3e8 align 1 size 8 flags 0x1
[    0.313223] pnp 00:08:   irq bitmask 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00001eb8 flags 0x1
[    0.313223] pnp 00:08: new dependent option (priority 0x1)
[    0.313223] pnp 00:08:   io  min 0x2e8 max 0x2e8 align 1 size 8 flags 0x1
[    0.313223] pnp 00:08:   irq bitmask 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00001eb8 flags 0x1
[    0.313223] pnp 00:08: end dependent options
[    0.317224] pnp 00:08: Plug and Play ACPI device, IDs PNP0501 (active)
[    0.317224] pnp 00:09: parse allocated resources
[    0.317224] pnp 00:09:   add io  0x378-0x37f flags 0x1
[    0.317224] pnp 00:09:   add irq 7 flags 0x1
[    0.317224] pnp 00:09: parse resource options
[    0.317224] pnp 00:09: new independent option
[    0.317224] pnp 00:09: new dependent option (priority 0x1)
[    0.317224] pnp 00:09:   io  min 0x378 max 0x378 align 1 size 8 flags 0x1
[    0.317224] pnp 00:09:   irq bitmask 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00001eb8 flags 0x1
[    0.317224] pnp 00:09: new dependent option (priority 0x1)
[    0.317224] pnp 00:09:   io  min 0x278 max 0x278 align 1 size 8 flags 0x1
[    0.317224] pnp 00:09:   irq bitmask 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00001eb8 flags 0x1
[    0.317224] pnp 00:09: new dependent option (priority 0x1)
[    0.317224] pnp 00:09:   io  min 0x3bc max 0x3bc align 1 size 4 flags 0x1
[    0.317224] pnp 00:09:   irq bitmask 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00001eb8 flags 0x1
[    0.317224] pnp 00:09: end dependent options
[    0.317224] pnp 00:09: Plug and Play ACPI device, IDs PNP0400 (active)
[    0.317224] pnp 00:0a: parse allocated resources
[    0.317224] pnp 00:0a:   add io  0x60-0x60 flags 0x1
[    0.317224] pnp 00:0a:   add io  0x64-0x64 flags 0x1
[    0.317224] pnp 00:0a:   add irq 1 flags 0x1
[    0.317224] pnp 00:0a: Plug and Play ACPI device, IDs PNP0303 (active)
[    0.317224] pnp 00:0b: parse allocated resources
[    0.317224] pnp 00:0b:   add mem 0xf0000000-0xf7ffffff flags 0x1
[    0.317224] pnp 00:0b: PNP0c02: calling quirk_system_pci_resources+0x0/0x15c
[    0.317224] pnp 00:0b: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.317224] pnp 00:0c: parse allocated resources
[    0.317224] pnp 00:0c:   add mem 0xd0000-0xd3fff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0xf0000-0xf7fff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0xf8000-0xfbfff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0xfc000-0xfffff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0xcfff0000-0xcfffffff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0xffff0000-0xffffffff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0x0-0x9ffff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0x100000-0xcffeffff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0xfec00000-0xfec00fff flags 0x1
[    0.317224] pnp 00:0c:   add mem 0xfee00000-0xfee00fff flags 0x1
[    0.317224] pnp 00:0c: PNP0c01: calling quirk_system_pci_resources+0x0/0x15c
[    0.317224] pnp 00:0c: Plug and Play ACPI device, IDs PNP0c01 (active)
[    0.317224] pnp: PnP ACPI: found 13 devices
[    0.317224] ACPI: ACPI bus type pnp unregistered
[    0.317224] usbcore: registered new interface driver usbfs
[    0.317224] usbcore: registered new interface driver hub
[    0.317224] usbcore: registered new device driver usb
[    0.317224] PCI: Using ACPI for IRQ routing
[    0.337374] PCI-DMA: Disabling AGP.
[    0.337374] PCI-DMA: aperture base @ 4000000 size 65536 KB
[    0.337374] PCI-DMA: using GART IOMMU.
[    0.337374] PCI-DMA: Reserving 64MB of IOMMU area in the AGP aperture
[    0.337374] hpet0: at MMIO 0xfefffc00, IRQs 2, 8, 31
[    0.337374] hpet0: 3 32-bit timers, 25000000 Hz
[    0.337374] ACPI: RTC can wake from S4
[    0.339147] Switched to high resolution mode on CPU 0
[    0.341882] Switched to high resolution mode on CPU 1
[    0.347125] pnp: the driver 'system' has been registered
[    0.347143] system 00:01: ioport range 0x1000-0x107f has been reserved
[    0.347150] system 00:01: ioport range 0x1080-0x10ff has been reserved
[    0.347156] system 00:01: ioport range 0x1400-0x147f has been reserved
[    0.347162] system 00:01: ioport range 0x1480-0x14ff has been reserved
[    0.347168] system 00:01: ioport range 0x1800-0x187f has been reserved
[    0.347174] system 00:01: ioport range 0x1880-0x18ff has been reserved
[    0.347181] system 00:01: iomem range 0xd0000000-0xdfffffff could not be reserved
[    0.347189] system 00:01: driver attached
[    0.347196] system 00:02: ioport range 0x4d0-0x4d1 has been reserved
[    0.347202] system 00:02: ioport range 0x800-0x87f has been reserved
[    0.347210] system 00:02: ioport range 0x295-0x314 has been reserved
[    0.347216] system 00:02: ioport range 0x290-0x294 has been reserved
[    0.347222] system 00:02: driver attached
[    0.347233] system 00:0b: iomem range 0xf0000000-0xf7ffffff could not be reserved
[    0.347241] system 00:0b: driver attached
[    0.347248] system 00:0c: iomem range 0xd0000-0xd3fff has been reserved
[    0.347254] system 00:0c: iomem range 0xf0000-0xf7fff could not be reserved
[    0.347260] system 00:0c: iomem range 0xf8000-0xfbfff could not be reserved
[    0.347266] system 00:0c: iomem range 0xfc000-0xfffff could not be reserved
[    0.347272] system 00:0c: iomem range 0xcfff0000-0xcfffffff could not be reserved
[    0.347280] system 00:0c: iomem range 0xffff0000-0xffffffff could not be reserved
[    0.347288] system 00:0c: iomem range 0x0-0x9ffff could not be reserved
[    0.347294] system 00:0c: iomem range 0x100000-0xcffeffff could not be reserved
[    0.347302] system 00:0c: iomem range 0xfec00000-0xfec00fff could not be reserved
[    0.347310] system 00:0c: iomem range 0xfee00000-0xfee00fff could not be reserved
[    0.347318] system 00:0c: driver attached
[    0.349859] PCI: Bridge: 0000:00:06.0
[    0.349859]   IO window: disabled.
[    0.349859]   MEM window: 0xfb000000-0xfb0fffff
[    0.349859]   PREFETCH window: disabled.
[    0.349859] PCI: Bridge: 0000:00:0f.0
[    0.349859]   IO window: 9000-9fff
[    0.349859]   MEM window: 0xf8000000-0xfaffffff
[    0.349859]   PREFETCH window: 0x00000000e0000000-0x00000000efffffff
[    0.349859] PCI: Setting latency timer of device 0000:00:06.0 to 64
[    0.349859] PCI: Setting latency timer of device 0000:00:0f.0 to 64
[    0.349859] NET: Registered protocol family 2
[    0.385763] IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.389607] TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
[    0.393611] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    0.393611] TCP: Hash tables configured (established 524288 bind 65536)
[    0.393611] TCP reno registered
[    0.401735] NET: Registered protocol family 1
[    0.401832] checking if image is initramfs... it is
[    0.922087] Freeing initrd memory: 8919k freed
[    0.929610] audit: initializing netlink socket (disabled)
[    0.929610] type=2000 audit(1246451137.916:1): initialized
[    0.929610] Total HugeTLB memory allocated, 0
[    0.929610] VFS: Disk quotas dquot_6.5.1
[    0.929610] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.929610] msgmni has been set to 7937
[    0.929610] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[    0.929610] io scheduler noop registered
[    0.929610] io scheduler anticipatory registered
[    0.929610] io scheduler deadline registered
[    0.929610] io scheduler cfq registered (default)
[    0.954088] pci 0000:00:05.0: Enabling HT MSI Mapping
[    0.954105] pci 0000:00:05.1: Enabling HT MSI Mapping
[    0.954122] pci 0000:00:05.2: Enabling HT MSI Mapping
[    0.954137] pci 0000:00:06.0: Enabling HT MSI Mapping
[    0.954154] pci 0000:00:06.1: Enabling HT MSI Mapping
[    0.954172] pci 0000:00:08.0: Enabling HT MSI Mapping
[    0.954188] pci 0000:00:0f.0: Enabling HT MSI Mapping
[    0.954214] pci 0000:02:00.0: Boot video device
[    0.954321] PCI: Setting latency timer of device 0000:00:0f.0 to 64
[    0.954338] assign_interrupt_mode Found MSI capability
[    0.954359] Allocate Port Service[0000:00:0f.0:pcie00]
[    0.954409] Allocate Port Service[0000:00:0f.0:pcie03]
[    0.954857] vesafb: framebuffer at 0xe0000000, mapped to 0xffffc20009100000, using 3072k, total 262144k
[    0.954867] vesafb: mode is 1024x768x16, linelength=2048, pages=1
[    0.954873] vesafb: scrolling: redraw
[    0.954878] vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0
[    0.966967] Console: switching to colour frame buffer device 128x48
[    0.974967] fb0: VESA VGA frame buffer device
[    0.978969] hpet_resources: 0xfefffc00 is busy
[    0.978969] Linux agpgart interface v0.103
[    0.978969] Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
[    0.978969] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    0.978969] pnp: the driver 'serial' has been registered
[    0.978969] 00:08: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    0.978969] serial 00:08: driver attached
[    0.978969] brd: module loaded
[    0.978969] input: Macintosh mouse button emulation as /class/input/input0
[    0.978969] pnp: the driver 'i8042 kbd' has been registered
[    0.978969] i8042 kbd 00:0a: driver attached
[    0.978969] pnp: the driver 'i8042 aux' has been registered
[    0.978969] PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
[    0.978969] PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
[    0.982972] serio: i8042 KBD port at 0x60,0x64 irq 1
[    1.006968] mice: PS/2 mouse device common for all mice
[    1.006968] pnp: the driver 'rtc_cmos' has been registered
[    1.006968] rtc_cmos 00:05: rtc core: registered rtc_cmos as rtc0
[    1.006968] rtc0: alarms up to one year, y3k
[    1.006968] rtc_cmos 00:05: driver attached
[    1.006968] cpuidle: using governor ladder
[    1.006968] cpuidle: using governor menu
[    1.006968] No iBFT detected.
[    1.006968] TCP cubic registered
[    1.006968] NET: Registered protocol family 17
[    1.006968] registered taskstats version 1
[    1.006968] rtc_cmos 00:05: setting system clock to 2009-07-01 12:25:38 UTC (1246451138)
[    1.006968] Freeing unused kernel memory: 392k freed
[    1.026971] input: AT Translated Set 2 keyboard as /class/input/input1
[    1.098975] device-mapper: uevent: version 1.0.3
[    1.098975] device-mapper: ioctl: 4.13.0-ioctl (2007-10-18) initialised: dm-devel at redhat.com
[    1.126974] ACPI: ACPI0007:00 is registered as cooling_device0
[    1.126974] ACPI: ACPI0007:01 is registered as cooling_device1
[    1.286975] ACPI: PCI Interrupt Link [APCL] enabled at IRQ 23
[    1.289587] ACPI: PCI Interrupt 0000:00:02.1[B] -> Link [APCL] -> GSI 23 (level, low) -> IRQ 23
[    1.293275] PCI: Setting latency timer of device 0000:00:02.1 to 64
[    1.293278] ehci_hcd 0000:00:02.1: EHCI Host Controller
[    1.295965] ehci_hcd 0000:00:02.1: new USB bus registered, assigned bus number 1
[    1.297838] ehci_hcd 0000:00:02.1: debug port 1
[    1.301801] PCI: cache line size of 64 is not supported by device 0000:00:02.1
[    1.301813] ehci_hcd 0000:00:02.1: irq 23, io mem 0xfb106000
[    1.304736] ohci_hcd: 2006 August 04 USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.310977] Uniform Multi-Platform E-IDE driver
[    1.313466] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
[    1.316701] ehci_hcd 0000:00:02.1: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004
[    1.319832] usb usb1: configuration #1 chosen from 1 choice
[    1.320180] No dock devices found.
[    1.327139] hub 1-0:1.0: USB hub found
[    1.330516] hub 1-0:1.0: 10 ports detected
[    1.334006] SCSI subsystem initialized
[    1.348491] libata version 3.00 loaded.
[    1.436622] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    1.440211] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.443871] usb usb1: Product: EHCI Host Controller
[    1.447870] usb usb1: Manufacturer: Linux 2.6.26-2-amd64 ehci_hcd
[    1.451644] usb usb1: SerialNumber: 0000:00:02.1
[    1.456621] ACPI: PCI Interrupt Link [APCF] enabled at IRQ 22
[    1.460390] ACPI: PCI Interrupt 0000:00:02.0[A] -> Link [APCF] -> GSI 22 (level, low) -> IRQ 22
[    1.464230] PCI: Setting latency timer of device 0000:00:02.0 to 64
[    1.464233] ohci_hcd 0000:00:02.0: OHCI Host Controller
[    1.470706] ohci_hcd 0000:00:02.0: new USB bus registered, assigned bus number 2
[    1.470733] ohci_hcd 0000:00:02.0: irq 22, io mem 0xfb105000
[    1.530958] usb usb2: configuration #1 chosen from 1 choice
[    1.534767] hub 2-0:1.0: USB hub found
[    1.538751] hub 2-0:1.0: 10 ports detected
[    1.645635] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
[    1.648886] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.656517] usb usb2: Product: OHCI Host Controller
[    1.682937] usb usb2: Manufacturer: Linux 2.6.26-2-amd64 ohci_hcd
[    1.686938] usb usb2: SerialNumber: 0000:00:02.0
[    1.694937] NFORCE-MCP55: 0000:00:04.0 (rev a1) UDMA133 controller
[    1.698622] NFORCE-MCP55: IDE controller (0x10de:0x036e rev 0xa1) at  PCI slot 0000:00:04.0
[    1.702420] NFORCE-MCP55: not 100% native mode: will probe irqs later
[    1.706227] NFORCE-MCP55: BIOS didn't set cable bits correctly. Enabling workaround.
[    1.710102] NFORCE-MCP55: IDE port disabled
[    1.713959]     ide0: BM-DMA at 0xf000-0xf007
[    1.717829] Probing IDE interface ide0...
[    2.004629] usb 2-9: new low speed USB device using ohci_hcd and address 2
[    2.234279] usb 2-9: configuration #1 chosen from 1 choice
[    2.238976] usb 2-9: New USB device found, idVendor=1241, idProduct=1166
[    2.245806] usb 2-9: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.478753] hda: Optiarc DVD RW AD-7173A, ATAPI CD/DVD-ROM drive
[    3.202712] hda: host max PIO5 wanted PIO255(auto-tune) selected PIO4
[    3.202850] hda: UDMA/66 mode selected
[    3.210671] ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
[    3.214672] sata_nv 0000:00:05.0: version 3.5
[    3.214672] ACPI: PCI Interrupt Link [APSI] enabled at IRQ 21
[    3.218287] ACPI: PCI Interrupt 0000:00:05.0[A] -> Link [APSI] -> GSI 21 (level, low) -> IRQ 21
[    3.218965] sata_nv 0000:00:05.0: Using SWNCQ mode
[    3.222710] PCI: Setting latency timer of device 0000:00:05.0 to 64
[    3.226277] scsi0 : sata_nv
[    3.229970] scsi1 : sata_nv
[    3.233476] ata1: SATA max UDMA/133 cmd 0xa800 ctl 0xac00 bmdma 0xb800 irq 21
[    3.237476] ata2: SATA max UDMA/133 cmd 0xb000 ctl 0xb400 bmdma 0xb808 irq 21
[    3.774682] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[    3.785877] ata1.00: HPA detected: current 488395055, native 488397168
[    3.786162] ata1.00: ATA-7: SAMSUNG SP2504C, VT100-50, max UDMA7
[    3.789996] ata1.00: 488395055 sectors, multi 16: LBA48 NCQ (depth 31/32)
[    3.826473] ata1.00: configured for UDMA/133
[    4.167658] ata2: SATA link down (SStatus 0 SControl 300)
[    4.173349] scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG SP2504C  VT10 PQ: 0 ANSI: 5
[    4.179208] ACPI: PCI Interrupt Link [APSJ] enabled at IRQ 20
[    4.182749] ACPI: PCI Interrupt 0000:00:05.1[B] -> Link [APSJ] -> GSI 20 (level, low) -> IRQ 20
[    4.186375] sata_nv 0000:00:05.1: Using SWNCQ mode
[    4.189989] PCI: Setting latency timer of device 0000:00:05.1 to 64
[    4.190411] scsi2 : sata_nv
[    4.193980] scsi3 : sata_nv
[    4.194264] ata3: SATA max UDMA/133 cmd 0xbc00 ctl 0xc000 bmdma 0xcc00 irq 20
[    4.197809] ata4: SATA max UDMA/133 cmd 0xc400 ctl 0xc800 bmdma 0xcc08 irq 20
[    4.556843] ata3: SATA link down (SStatus 0 SControl 300)
[    4.904526] ata4: SATA link down (SStatus 0 SControl 300)
[    4.912521] ACPI: PCI Interrupt Link [ASA2] enabled at IRQ 23
[    4.915917] ACPI: PCI Interrupt 0000:00:05.2[C] -> Link [ASA2] -> GSI 23 (level, low) -> IRQ 23
[    4.919369] sata_nv 0000:00:05.2: Using SWNCQ mode
[    4.922840] PCI: Setting latency timer of device 0000:00:05.2 to 64
[    4.923270] scsi4 : sata_nv
[    4.925333] scsi5 : sata_nv
[    4.928637] ata5: SATA max UDMA/133 cmd 0xd000 ctl 0xd400 bmdma 0xe000 irq 23
[    4.932090] ata6: SATA max UDMA/133 cmd 0xd800 ctl 0xdc00 bmdma 0xe008 irq 23
[    5.267723] ata5: SATA link down (SStatus 0 SControl 300)
[    5.602694] ata6: SATA link down (SStatus 0 SControl 300)
[    5.612204] forcedeth: Reverse Engineered nForce ethernet driver. Version 0.61.
[    5.615663] ACPI: PCI Interrupt Link [APCH] enabled at IRQ 22
[    5.619024] ACPI: PCI Interrupt 0000:00:08.0[A] -> Link [APCH] -> GSI 22 (level, low) -> IRQ 22
[    5.619662] PCI: Setting latency timer of device 0000:00:08.0 to 64
[    6.160096] forcedeth 0000:00:08.0: ifname eth0, PHY OUI 0x5043 @ 1, addr 00:16:e6:45:d2:18
[    6.163166] forcedeth 0000:00:08.0: highdma csum vlan pwrctl mgmt timirq gbit lnktim msi desc-v3
[    6.174596] ACPI: PCI Interrupt Link [APC1] enabled at IRQ 16
[    6.175085] ACPI: PCI Interrupt 0000:01:08.0[A] -> Link [APC1] -> GSI 16 (level, low) -> IRQ 16
[    6.186890] udev: renamed network interface eth0 to eth2
[    6.194889] usbcore: registered new interface driver hiddev
[    6.206886] input: HID 1241:1166 as /class/input/input2
[    6.229215] input,hidraw0: USB HID v1.00 Mouse [HID 1241:1166] on usb-0000:00:02.0-9
[    6.230886] usbcore: registered new interface driver usbhid
[    6.234415] usbhid: v2.6:USB HID core driver
[    6.242954] ssb: Sonics Silicon Backplane found on PCI device 0000:01:08.0
[    6.247190] ACPI: PCI Interrupt Link [APC3] enabled at IRQ 18
[    6.250887] ACPI: PCI Interrupt 0000:01:0a.0[A] -> Link [APC3] -> GSI 18 (level, low) -> IRQ 18
[    6.306884] ohci1394: fw-host0: OHCI-1394 1.1 (PCI): IRQ=[18]  MMIO=[fb006000-fb0067ff]  Max Packet=[2048]  IR/IT contexts=[4/8]
[    6.325497] hda: ATAPI 48X DVD-ROM DVD-R-RAM CD-R/RW drive, 2048kB Cache
[    6.329505] Uniform CD-ROM driver Revision: 3.20
[    6.338909] Driver 'sd' needs updating - please use bus_type methods
[    6.343022] sd 0:0:0:0: [sda] 488395055 512-byte hardware sectors (250058 MB)
[    6.343060] sd 0:0:0:0: [sda] Write Protect is off
[    6.347065] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    6.347108] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    6.350970] sd 0:0:0:0: [sda] 488395055 512-byte hardware sectors (250058 MB)
[    6.354909] sd 0:0:0:0: [sda] Write Protect is off
[    6.358871] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    6.358901] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    6.362832]  sda: sda1 sda2 sda3 sda4 < sda5 sda6 >
[    6.410386] sd 0:0:0:0: [sda] Attached SCSI disk
[    6.787453] PM: Starting manual resume from disk
[    6.866449] kjournald starting.  Commit interval 5 seconds
[    6.867905] EXT3-fs: mounted filesystem with ordered data mode.
[    7.623122] ieee1394: Host added: ID:BUS[0-00:1023]  GUID[0016e65600b7173c]
[    8.536578] udev: starting version 141
[    8.540732] udev: deprecated sysfs layout; update the kernel or disable CONFIG_SYSFS_DEPRECATED; some udev features will not work correctly
[    9.331186] input: Power Button (FF) as /class/input/input3
[    9.377911] input: PC Speaker as /class/input/input4
[    9.382351] ACPI: Power Button (FF) [PWRF]
[    9.388047] input: Power Button (CM) as /class/input/input5
[    9.429554] ACPI: Power Button (CM) [PWRB]
[    9.794479] pnp: the driver 'parport_pc' has been registered
[    9.794479] parport_pc 00:09: reported by Plug and Play ACPI
[    9.809907] parport0: PC-style at 0x378, irq 7 [PCSPP,TRISTATE]
[    9.912619] parport_pc 00:09: driver attached
[   10.001375] i2c-adapter i2c-0: nForce2 SMBus adapter at 0x1c00
[   10.004465] i2c-adapter i2c-1: nForce2 SMBus adapter at 0x1c80
[   10.219914] b43-phy0: Broadcom 4318 WLAN found
[   10.296220] ACPI: PCI Interrupt Link [AAZA] enabled at IRQ 21
[   10.300367] ACPI: PCI Interrupt 0000:00:06.1[B] -> Link [AAZA] -> GSI 21 (level, low) -> IRQ 21
[   10.304572] PCI: Setting latency timer of device 0000:00:06.1 to 64
[   10.308555] phy0: Selected rate control algorithm 'pid'
[   10.360936] Broadcom 43xx driver loaded [ Features: PMLR, Firmware-ID: FW13 ]
[   11.744833] Adding 7815580k swap on /dev/sda1.  Priority:-1 extents:1 across:7815580k
[   12.425397] EXT3 FS on sda2, internal journal
[   12.964700] loop: module loaded
[   13.066632] powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ processors (2 cpu cores) (version 2.20.00)
[   13.096557] powernow-k8:    0 : fid 0x11 (2500 MHz), vid 0x9
[   13.099925] powernow-k8:    1 : fid 0x10 (2400 MHz), vid 0xa
[   13.103926] powernow-k8:    2 : fid 0xe (2200 MHz), vid 0xc
[   13.107901] powernow-k8:    3 : fid 0xc (2000 MHz), vid 0xe
[   13.111846] powernow-k8:    4 : fid 0xa (1800 MHz), vid 0x10
[   13.115705] powernow-k8:    5 : fid 0x2 (1000 MHz), vid 0x12
[   13.171029] it87: Found IT8716F chip at 0x290, revision 0
[   13.174733] it87: in3 is VCC (+5V)
[   13.178338] it87: in7 is VCCH (+5V Stand-By)
[  123.043285] kjournald starting.  Commit interval 5 seconds
[  123.044774] EXT3 FS on sda3, internal journal
[  123.044774] EXT3-fs: mounted filesystem with ordered data mode.
[  123.080056] kjournald starting.  Commit interval 5 seconds
[  123.080056] EXT3 FS on sda5, internal journal
[  123.080056] EXT3-fs: mounted filesystem with ordered data mode.
[  124.382923] ip_tables: (C) 2000-2006 Netfilter Core Team
[  124.432831] nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
[  124.535669] eth2: no link during initialization.
[  125.286936] input: b43-phy0 as /class/input/input6
[  125.399616] firmware: requesting b43/ucode5.fw
[  125.509424] firmware: requesting b43/pcm5.fw
[  125.547154] firmware: requesting b43/b0g0initvals5.fw
[  125.603501] firmware: requesting b43/b0g0bsinitvals5.fw
[  125.707016] b43-phy0: Loading firmware version 410.2160 (2015-15-255 15:32:10)
[  126.278542] NET: Registered protocol family 10
[  126.735315] Registered led device: b43-phy0::tx
[  126.742165] Registered led device: b43-phy0::rx
[  126.745787] Registered led device: b43-phy0::radio
[  126.826162] lo: Disabled Privacy Extensions
[  126.830363] ADDRCONF(NETDEV_UP): eth2: link is not ready
[  126.834564] ADDRCONF(NETDEV_UP): wlan0: link is not ready
[  127.737317] wlan0: Initial auth_alg=0
[  127.737321] wlan0: authenticate with AP 00:13:49:b1:2e:1c
[  127.737286] wlan0: RX authentication from 00:13:49:b1:2e:1c (alg=0 transaction=2 status=0)
[  127.737286] wlan0: authenticated
[  127.737286] wlan0: associate with AP 00:13:49:b1:2e:1c
[  127.737286] wlan0: RX AssocResp from 00:13:49:b1:2e:1c (capab=0x411 status=0 aid=1)
[  127.737286] wlan0: associated
[  127.737286] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
[  127.971869] wlan0: CTS protection enabled (BSSID=00:13:49:b1:2e:1c)
[  127.971869] wlan0: switched to short barker preamble (BSSID=00:13:49:b1:2e:1c)
[  143.593856] wlan0: no IPv6 routers present
[  159.293959] RPC: Registered udp transport module.
[  159.296563] RPC: Registered tcp transport module.
[  159.423412] Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
[  165.671496] Clocksource tsc unstable (delta = -300035282 ns)
[  170.255429] NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
[  170.277218] NFSD: starting 90-second grace period
[  179.494713] lp0: using parport0 (interrupt-driven).
[  179.516281] ppdev: user-space parallel port driver
[  206.405264] CPU0 attaching NULL sched-domain.
[  206.405272] CPU1 attaching NULL sched-domain.
[  206.424691] CPU0 attaching sched-domain:
[  206.424697]  domain 0: span 0-1
[  206.424700]   groups: 0 1
[  206.424707]   domain 1: span 0-1
[  206.424711]    groups: 0-1
[  206.424716] CPU1 attaching sched-domain:
[  206.424719]  domain 0: span 0-1
[  206.424723]   groups: 1 0
[  206.424730]   domain 1: span 0-1
[  206.424734]    groups: 0-1

From andi.mundt at web.de  Thu Jul  2 17:56:30 2009
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Thu, 2 Jul 2009 17:56:30 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090701142139.GA7679@flashgordon>
References: <20090701142139.GA7679@flashgordon>
Message-ID: <20090702155630.GA10928@flashgordon>

Hi everybody,

just noticed that my parallel port printer unfortunately only works
with the prop. BIOS:


From andi.mundt at web.de  Thu Jul  2 18:00:44 2009
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Thu, 2 Jul 2009 18:00:44 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090701142139.GA7679@flashgordon>
References: <20090701142139.GA7679@flashgordon>
Message-ID: <20090702160043.GB10928@flashgordon>

Hi everybody,

the last message did not get throug completely :-(
Here is the missing part:

From joe at settoplinux.org  Thu Jul  2 18:49:37 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 02 Jul 2009 12:49:37 -0400
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702155630.GA10928@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
Message-ID: <a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>




On Thu, 2 Jul 2009 17:56:30 +0200, "Andreas B. Mundt" <andi.mundt at web.de>
wrote:
> Hi everybody,
> 
> just noticed that my parallel port printer unfortunately only works
> with the prop. BIOS:
> 
> From dmesg:
> 
> coreboot:
> [   54.388956] lp: driver loaded but no devices found
> [   54.409159] ppdev: user-space parallel port driver
> 
> prop. BIOS:
> [  179.494713] lp0: using parport0 (interrupt-driven).
> [  179.516281] ppdev: user-space parallel port driver
> 
Hmm is it enabled in by the SuperIO in coreboot? Perhaps it is related to a
IRQ conflict?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From andi.mundt at web.de  Thu Jul  2 19:16:05 2009
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Thu, 2 Jul 2009 19:16:05 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
Message-ID: <20090702171605.GA5514@flashgordon>

Hi,

find attached the output of superiotool -dV.

The parallel port part:

coreboot:
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 00 03 78 07 78 07 04 03
def 00 03 78 07 78 07 03 03

prop. BIOS:
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 01 03 78 00 00 07 04 08
def 00 03 78 07 78 07 03 03

Any hints are appreciated.

Regards 

	Andi


On Thu, Jul 02, 2009 at 12:49:37PM -0400, Joseph Smith wrote:
> 
> 
> 
> On Thu, 2 Jul 2009 17:56:30 +0200, "Andreas B. Mundt" <andi.mundt at web.de>
> wrote:
> > Hi everybody,
> > 
> > just noticed that my parallel port printer unfortunately only works
> > with the prop. BIOS:
> > 
> > From dmesg:
> > 
> > coreboot:
> > [   54.388956] lp: driver loaded but no devices found
> > [   54.409159] ppdev: user-space parallel port driver
> > 
> > prop. BIOS:
> > [  179.494713] lp0: using parport0 (interrupt-driven).
> > [  179.516281] ppdev: user-space parallel port driver
> > 
> Hmm is it enabled in by the SuperIO in coreboot? Perhaps it is related to a
> IRQ conflict?
> 
> -- 
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
> 
-------------- next part --------------
superiotool r3194
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e...
Found ITE IT8716F (id=0x8716, rev=0x0) at 0x2e
Register dump:
idx 07 20 21 22 23 24 2b
val 07 87 16 00 11 00 00
def NA 87 16 01 00 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1
val 00 03 f0 06 02 00 00
def 00 03 f0 06 02 00 00
LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1 f2 f3
val 01 03 f8 04 00 50 00 7f
def 00 03 f8 04 00 50 00 7f
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1 f2 f3
val 00 02 f8 03 00 50 00 7f
def 00 02 f8 03 00 50 00 7f
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 00 03 78 07 78 07 04 03
def 00 03 78 07 78 07 03 03
LDN 0x04 (Environment controller)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6
val 01 02 90 02 30 09 80 00  0a 00 80 00 ff
def 00 02 90 02 30 09 00 00  00 00 00 NA NA
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 71 f0
val 01 00 60 00 64 01 02 48
def 01 00 60 00 64 01 02 00
LDN 0x06 (Mouse)
idx 30 70 71 f0
val 01 0c 02 00
def 00 0c 02 00
LDN 0x07 (GPIO)
idx 25 26 27 28 29 2a 2c 60  61 62 63 64 65 70 71 72  73 74 b0 b1 b2 b3 b4 b5  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c8 c9 ca cb cc  e0 e1 e2 e3 e4 f0 f1 f2  f3 f4 f5 f6 f7 f8 f9 fa  fb fc fd
val 00 43 20 00 81 00 1f 00  00 08 00 08 20 00 01 00  38 00 00 00 00 00 00 00  00 00 00 00 01 00 00 43  20 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 28 00 00 00 00  00 32 00
def 01 00 00 40 00 00 00 00  00 00 00 00 00 00 00 20  38 00 00 00 00 00 00 00  00 00 00 00 00 00 01 00  00 40 00 01 00 00 40 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 NA 00
LDN 0x08 (MIDI port)
idx 30 60 61 70 f0
val 00 03 00 0a 00
def 00 03 00 0a 00
LDN 0x09 (Game port)
idx 30 60 61
val 00 02 01
def 00 02 01
LDN 0x0a (Consumer IR)
idx 30 60 61 70 f0
val 00 03 10 0b 06
def 00 03 10 0b 00
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
Found SMSC FDC37C669FR (id=0x04, rev=0x04) at 0x162e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
Found SMSC FDC37C669FR (id=0x04, rev=0x04) at 0x162e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
Found SMSC FDC37C669FR (id=0x04, rev=0x04) at 0x164e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
Found SMSC FDC37C669FR (id=0x04, rev=0x04) at 0x164e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
-------------- next part --------------
superiotool r3194
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e...
Found ITE IT8716F (id=0x8716, rev=0x0) at 0x2e
Register dump:
idx 07 20 21 22 23 24 2b
val 07 87 16 00 11 00 00
def NA 87 16 01 00 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1
val 00 00 00 00 04 00 80
def 00 03 f0 06 02 00 00
LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1 f2 f3
val 01 03 f8 04 00 50 00 7f
def 00 03 f8 04 00 50 00 7f
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1 f2 f3
val 00 00 00 00 00 50 00 7f
def 00 02 f8 03 00 50 00 7f
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 01 03 78 00 00 07 04 08
def 00 03 78 07 78 07 03 03
LDN 0x04 (Environment controller)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6
val 01 02 90 00 00 00 80 00  0a 00 80 00 ff
def 00 02 90 02 30 09 00 00  00 00 00 NA NA
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 71 f0
val 01 00 60 00 64 01 02 68
def 01 00 60 00 64 01 02 00
LDN 0x06 (Mouse)
idx 30 70 71 f0
val 01 0c 02 00
def 00 0c 02 00
LDN 0x07 (GPIO)
idx 25 26 27 28 29 2a 2c 60  61 62 63 64 65 70 71 72  73 74 b0 b1 b2 b3 b4 b5  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c8 c9 ca cb cc  e0 e1 e2 e3 e4 f0 f1 f2  f3 f4 f5 f6 f7 f8 f9 fa  fb fc fd
val 00 43 20 00 81 00 1f 00  00 08 00 00 00 00 00 00  38 00 00 00 00 00 00 00  00 00 00 00 01 00 00 43  20 00 00 00 40 00 00 00  00 00 00 00 00 10 40 00  00 00 00 28 00 00 00 00  00 32 00
def 01 00 00 40 00 00 00 00  00 00 00 00 00 00 00 20  38 00 00 00 00 00 00 00  00 00 00 00 00 00 01 00  00 40 00 01 00 00 40 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 NA 00
LDN 0x08 (MIDI port)
idx 30 60 61 70 f0
val 00 03 00 0a 00
def 00 03 00 0a 00
LDN 0x09 (Game port)
idx 30 60 61
val 00 02 01
def 00 02 01
LDN 0x0a (Consumer IR)
idx 30 60 61 70 f0
val 00 03 10 0b 06
def 00 03 10 0b 00
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff

From harald.gutmann at gmx.net  Thu Jul  2 19:58:43 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Jul 2009 19:58:43 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090701142139.GA7679@flashgordon>
References: <20090701142139.GA7679@flashgordon>
Message-ID: <200907021958.47574.harald.gutmann@gmx.net>

On Wednesday 01 July 2009 16:21:39 Andreas B. Mundt wrote:
> Hi everybody,
>
> with the help of Harald's seaBIOS-payload I managed to run the latest
> coreboot (revision 4387) on my v1.0 m57sli-board. From a first look
> everything seems to work: kvm, sound, power-now frequency scaling.
> dmesg is attached for proprietary and free bios.
Nice that you could test it.
The payload wasn't from me, just the link to it. (It's directly on the seabios 
homepage, kevin built it some time ago.)

>
> Minor issues:
>
> coreboot ACPI:
>  hda: host side 80-wire cable detection failed, limiting max speed to
> UDMA33 hda: UDMA/33 mode selected
>  [...]
>  powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+
> processors (2 cpu cores) (version 2.20.00) powernow-k8:    0 : fid 0x11
> (2500 MHz), vid 0x9
>  powernow-k8:    1 : fid 0x10 (2400 MHz), vid 0xa
>  powernow-k8:    2 : fid 0xe (2200 MHz), vid 0xc
>  powernow-k8:    3 : fid 0xc (2000 MHz), vid 0xe
>  powernow-k8:    4 : fid 0x2 (1000 MHz), vid 0x12
>  powernow-k8: ph2 null fid transition 0x11
>
> proprietary:
>  hda: UDMA/66 mode selected
>  [...]
>  powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+
> processors (2 cpu cores) (version 2.20.00) powernow-k8:    0 : fid 0x11
> (2500 MHz), vid 0x9
>  powernow-k8:    1 : fid 0x10 (2400 MHz), vid 0xa
>  powernow-k8:    2 : fid 0xe (2200 MHz), vid 0xc
>  powernow-k8:    3 : fid 0xc (2000 MHz), vid 0xe
>  powernow-k8:    4 : fid 0xa (1800 MHz), vid 0x10
>  powernow-k8:    5 : fid 0x2 (1000 MHz), vid 0x12
Interesting, and good that you mention that!

When I tested the PowerNow! stuff, I also recognized that, but it seems that I 
flipped the results. My point of view was that coreboot offers one more stepping 
mode, and therefore didn't care about it.
Maybe Rudolf Marek can us help here, because he wrote the automatic generation 
for that ACPI table (SSDT).




> Many thanks to everybody involved! I'll run my board now fulltime coreboot!
>
>      Regards Andi
Regards,
Harald
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From harald.gutmann at gmx.net  Thu Jul  2 20:00:21 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Jul 2009 20:00:21 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702155630.GA10928@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
Message-ID: <200907022000.21736.harald.gutmann@gmx.net>

On Thursday 02 July 2009 17:56:30 Andreas B. Mundt wrote:
> Hi everybody,
>
> just noticed that my parallel port printer unfortunately only works
I've no parallel port hardware and therefore not cared about this, but I think 
we can fix this.
The floppy issue is hopefully the same way to fix than parport. (I think that 
floppy is also SIO related.)

> with the prop. BIOS:
> >From dmesg:
>
> coreboot:
> [   54.388956] lp: driver loaded but no devices found
> [   54.409159] ppdev: user-space parallel port driver
>
> prop. BIOS:
> [  179.494713] lp0: using parport0 (interrupt-driven).
> [  179.516281] ppdev: user-space parallel port driver
>
> Regards,
>
> 	Andi
Will try to find out something more on that topic.

Kind regards,
Harald
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From peter at stuge.se  Thu Jul  2 20:08:00 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 20:08:00 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <200907022000.21736.harald.gutmann@gmx.net>
	<20090702171605.GA5514@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<200907022000.21736.harald.gutmann@gmx.net>
	<20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
	<20090702171605.GA5514@flashgordon>
Message-ID: <20090702180800.19058.qmail@stuge.se>

Andreas B. Mundt wrote:
> coreboot:
> LDN 0x03 (Parallel port)
> idx 30 60 61 62 63 70 74 f0
> val 00 03 78 07 78 07 04 03

> prop. BIOS:
> LDN 0x03 (Parallel port)
> idx 30 60 61 62 63 70 74 f0
> val 01 03 78 00 00 07 04 08

LDN 30 bit 1 is almost always enable. So coreboot simply does not
enable the parallel port.


Harald Gutmann wrote:
> I've no parallel port hardware and therefore not cared about this,
> but I think we can fix this.
> The floppy issue is hopefully the same way to fix than parport. (I
> think that floppy is also SIO related.)
..

> Will try to find out something more on that topic.

Maybe it's as simple as a missing "on" in Config.lb ?


//Peter



From harald.gutmann at gmx.net  Thu Jul  2 20:12:33 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Jul 2009 20:12:33 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702180800.19058.qmail@stuge.se>
References: <20090701142139.GA7679@flashgordon>
	<20090702171605.GA5514@flashgordon>
	<20090702180800.19058.qmail@stuge.se>
Message-ID: <200907022012.33859.harald.gutmann@gmx.net>

On Thursday 02 July 2009 20:08:00 Peter Stuge wrote:
> Andreas B. Mundt wrote:
> > coreboot:
> > LDN 0x03 (Parallel port)
> > idx 30 60 61 62 63 70 74 f0
> > val 00 03 78 07 78 07 04 03
> >
> > prop. BIOS:
> > LDN 0x03 (Parallel port)
> > idx 30 60 61 62 63 70 74 f0
> > val 01 03 78 00 00 07 04 08
>
> LDN 30 bit 1 is almost always enable. So coreboot simply does not
> enable the parallel port.
>
> Harald Gutmann wrote:
> > I've no parallel port hardware and therefore not cared about this,
> > but I think we can fix this.
> > The floppy issue is hopefully the same way to fix than parport. (I
> > think that floppy is also SIO related.)
>
> ..
>
> > Will try to find out something more on that topic.
>
> Maybe it's as simple as a missing "on" in Config.lb ?
Seems that it is that simple.
I'll test it, and check if it works.

>
>
> //Peter
Regards,
Harald

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From harald.gutmann at gmx.net  Thu Jul  2 20:22:50 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Jul 2009 20:22:50 +0200
Subject: [coreboot] ACPI on m57sli v1.0 - Parport & Floppy Patch
In-Reply-To: <20090702155630.GA10928@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
Message-ID: <200907022022.55815.harald.gutmann@gmx.net>

On Thursday 02 July 2009 17:56:30 Andreas B. Mundt wrote:
> Hi everybody,
>
> just noticed that my parallel port printer unfortunately only works
>
> with the prop. BIOS:
> >From dmesg:
>
> coreboot:
> [   54.388956] lp: driver loaded but no devices found
> [   54.409159] ppdev: user-space parallel port driver
>
> prop. BIOS:
> [  179.494713] lp0: using parport0 (interrupt-driven).
> [  179.516281] ppdev: user-space parallel port driver
>
>
With the attached patch I get the following output on modprobe parport:
[   28.848297] lp0: using parport0 (polling).
[   28.858860] ppdev: user-space parallel port driver

The patch also turns on the floppy device, but I've none here to verify if it 
will work. It would be great if you can test if floppy works, so that we could 
mark the last two "not-working" parts as OK in the wiki, if it the floppy does 
its job


Regards,
Harald
> Regards,
>
> 	Andi
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From svn at coreboot.org  Thu Jul  2 20:27:02 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Jul 2009 20:27:02 +0200
Subject: [coreboot] [v2] r4393 - in trunk/coreboot-v2:
	src/mainboard/supermicro/h8dmr targets/supermicro/h8dmr
Message-ID: <mailman.3512.1355071590.16123.coreboot@coreboot.org>

Author: ward
Date: 2009-07-02 20:27:02 +0200 (Thu, 02 Jul 2009)
New Revision: 4393

Modified:
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
   trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb
   trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb
Log:

Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in
targets/supermicro/h8dmr/Config.lb and Config-abuild.lb.

Importantly, this also sets

  default CONFIG_AP_CODE_IN_CAR=0

in

  src/mainboard/supermicro/h8dmr/Options.lb

which is required to make this box boot since the changes that went in in
r4315.

At Myles' suggestion, this patch also sets

  default CONFIG_USE_FAILOVER_IMAGE=0
  default CONFIG_USE_FALLBACK_IMAGE=0
  default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE

in src/mainboard/supermicro/h8dmr/Options.lb to simplify
targets/supermicro/h8dmr/Config.lb a bit further.

Build tested with abuild, boot tested on physical hardware.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Myles Watson <mylesgw at gmail.com>



Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb	2009-07-01 17:01:17 UTC (rev 4392)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb	2009-07-02 18:27:02 UTC (rev 4393)
@@ -58,7 +58,6 @@
                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
         end
-        ldscript /arch/i386/init/ldscript_apc.lb
     end
 end
 

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb	2009-07-01 17:01:17 UTC (rev 4392)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb	2009-07-02 18:27:02 UTC (rev 4393)
@@ -126,13 +126,9 @@
 default CONFIG_ROM_SIZE=0x100000
 
 ##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use
 ##
-#default CONFIG_FALLBACK_SIZE=131072
-#default CONFIG_FALLBACK_SIZE=0x40000
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE=0x3f000
+default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -234,7 +230,7 @@
 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
-default CONFIG_AP_CODE_IN_CAR=1
+default CONFIG_AP_CODE_IN_CAR=0
 default CONFIG_MEM_TRAIN_SEQ=1
 default CONFIG_WAIT_BEFORE_CPUS_INIT=1
 
@@ -256,8 +252,9 @@
 ###
 
 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_ROM_IMAGE_SIZE = 0xf000
 
+
 ##
 ## Use a small 8K stack
 ##
@@ -347,10 +344,15 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-### End Options.lb
+default CONFIG_USE_FAILOVER_IMAGE=0
+default CONFIG_USE_FALLBACK_IMAGE=0
+default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
+
 #
 # CBFS
 #
 #
-default CONFIG_CBFS=0
+default CONFIG_CBFS=1
+
+### End Options.lb
 end

Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb
===================================================================
--- trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb	2009-07-01 17:01:17 UTC (rev 4392)
+++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb	2009-07-02 18:27:02 UTC (rev 4393)
@@ -11,27 +11,20 @@
 __LOGLEVEL__
 
 romimage "normal"
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
-        option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
 
 romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION=".0-failover"
+  option CONFIG_USE_FAILOVER_IMAGE=1
+  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+  option COREBOOT_EXTRA_VERSION=".0-failover"
 end
 
 buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb	2009-07-01 17:01:17 UTC (rev 4392)
+++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb	2009-07-02 18:27:02 UTC (rev 4393)
@@ -23,44 +23,20 @@
 mainboard supermicro/h8dmr
 
 romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 475136
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 425984 
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 458752 
-#       44k for atixx.rom
-#        option CONFIG_ROM_SIZE = 479232
-        option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	payload ../payload.elf
+  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+  payload ../payload.elf
 end
 
 romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	payload ../payload.elf
+  option CONFIG_USE_FALLBACK_IMAGE=1
+  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+  payload ../payload.elf
 end
 
 romimage "failover"
-        option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+  option CONFIG_USE_FAILOVER_IMAGE=1
+  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
 buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"




From ward at gnu.org  Thu Jul  2 20:27:36 2009
From: ward at gnu.org (Ward Vandewege)
Date: Thu, 2 Jul 2009 14:27:36 -0400
Subject: [coreboot] [PATCH] convert h8dmr to CBFS
In-Reply-To: <2CDA449536684FCAA0905CD7B64B7B0C@chimp>
References: <20090701212519.GA28645@countzero.vandewege.net>
	<2CDA449536684FCAA0905CD7B64B7B0C@chimp>
Message-ID: <20090702182736.GA26849@countzero.vandewege.net>

On Wed, Jul 01, 2009 at 03:53:27PM -0600, Myles Watson wrote:
> 
> Signed-off-by: Ward Vandewege <ward at gnu.org>
> 
> If you put
> default CONFIG_USE_FAILOVER_IMAGE=0
> default CONFIG_USE_FALLBACK_IMAGE=0
> default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
> 
> In Options.lb it would clean up your Config.lb files a little more.
> 
> Acked-by: Myles Watson <mylesgw at gmail.com>

Excellent idea, I've made that change.

r4393

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From info at Ivn.cl  Thu Jul  2 20:27:29 2009
From: info at Ivn.cl (Ivan Barrera A.)
Date: Thu, 02 Jul 2009 14:27:29 -0400
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
Message-ID: <4A4CFC11.4070609@Ivn.cl>

Hi !
Ive just joined the mailing list, to see if it is possible to get an
Asus G1 (laptop) use coreboot.

I recently killed my bios doing some experiments, so i desoldered the
chip, and put a nice socket. (it is a PLCC32). Also i have the equipment
needed to program this chip, so no worries there.

Details :

- Laptop : Asus G1 , first revisions. IMPORTANT NOTE: Video card is a
Geforce Go 7700 512MB, and video bios is integrated as a module in bios
rom (amibios)
- Attached lspci outpu
- No super io chip (it seems)
- PLCC32 SST49LF004B (49LF004B-33-4C-NH Rev CA, according to specs it is
lpc/fwh)
- Host bridge: Intel Corporation Mobile 945GM/PM/GMS
- South Bridge : ICH7 Family

- Bios : http://ivn.cl/software/asus_g1.rom (read with flasrom)


Actually, running linux 64bits, with no problems. (i just want a fater
startup, and see if there is any way to break the memory remapping
function non existant in asus rom... 4GB ram installed, only 2.9 Usable
, and... try some other OS)

Thanks :)


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From harald.gutmann at gmx.net  Thu Jul  2 20:31:50 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Jul 2009 20:31:50 +0200
Subject: [coreboot] ACPI on m57sli v1.0 - Parport & Floppy Patch
In-Reply-To: <200907022022.55815.harald.gutmann@gmx.net>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<200907022022.55815.harald.gutmann@gmx.net>
Message-ID: <200907022031.50628.harald.gutmann@gmx.net>

On Thursday 02 July 2009 20:22:50 Harald Gutmann wrote:
> On Thursday 02 July 2009 17:56:30 Andreas B. Mundt wrote:
> > Hi everybody,
> >
> > just noticed that my parallel port printer unfortunately only works
> >
> > with the prop. BIOS:
> > >From dmesg:
> >
> > coreboot:
> > [   54.388956] lp: driver loaded but no devices found
> > [   54.409159] ppdev: user-space parallel port driver
> >
> > prop. BIOS:
> > [  179.494713] lp0: using parport0 (interrupt-driven).
> > [  179.516281] ppdev: user-space parallel port driver
>
> With the attached patch I get the following output on modprobe parport:
> [   28.848297] lp0: using parport0 (polling).
> [   28.858860] ppdev: user-space parallel port driver
>
> The patch also turns on the floppy device, but I've none here to verify if
> it will work. It would be great if you can test if floppy works, so that we
> could mark the last two "not-working" parts as OK in the wiki, if it the
> floppy does its job
Sry, I forgot to sign it off:
Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>

>
> Regards,
> Harald
>
> > Regards,
> >
> > 	Andi

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From peter at stuge.se  Thu Jul  2 20:45:31 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 20:45:31 +0200
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
In-Reply-To: <4A4CFC11.4070609@Ivn.cl>
References: <4A4CFC11.4070609@Ivn.cl>
Message-ID: <20090702184531.27293.qmail@stuge.se>

Ivan Barrera A. wrote:
> Ive just joined the mailing list, to see if it is possible to get
> an Asus G1 (laptop) use coreboot.

Maybe. You could try a coreboot image for kontron/986lcd-m and see if
you get any serial output. But please check where the serial port is
on the kontron board, it may be on a superio, which may not be
available on the G1 - in that case you need another debug output
method..


//Peter



From info at coresystems.de  Thu Jul  2 20:48:58 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Jul 2009 20:48:58 +0200
Subject: [coreboot] build service results for r4393
Message-ID: <E1MMRL8-0007Ig-IE@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "ward" checked in revision 4393 to
the coreboot repository. This caused the following 
changes:

Change Log:

Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in
targets/supermicro/h8dmr/Config.lb and Config-abuild.lb.

Importantly, this also sets

  default CONFIG_AP_CODE_IN_CAR=0

in

  src/mainboard/supermicro/h8dmr/Options.lb

which is required to make this box boot since the changes that went in in
r4315.

At Myles' suggestion, this patch also sets

  default CONFIG_USE_FAILOVER_IMAGE=0
  default CONFIG_USE_FALLBACK_IMAGE=0
  default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE

in src/mainboard/supermicro/h8dmr/Options.lb to simplify
targets/supermicro/h8dmr/Config.lb a bit further.

Build tested with abuild, boot tested on physical hardware.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Myles Watson <mylesgw at gmail.com>



Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4393&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4393&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in ward's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at Ivn.cl  Thu Jul  2 20:47:52 2009
From: info at Ivn.cl (Ivan Barrera A.)
Date: Thu, 02 Jul 2009 14:47:52 -0400
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
In-Reply-To: <20090702184531.27293.qmail@stuge.se>
References: <4A4CFC11.4070609@Ivn.cl> <20090702184531.27293.qmail@stuge.se>
Message-ID: <4A4D00D8.2020503@Ivn.cl>

Peter Stuge escribi?:
> Ivan Barrera A. wrote:
>> Ive just joined the mailing list, to see if it is possible to get
>> an Asus G1 (laptop) use coreboot.
> 
> Maybe. You could try a coreboot image for kontron/986lcd-m and see if
> you get any serial output. But please check where the serial port is
> on the kontron board, it may be on a superio, which may not be
> available on the G1 - in that case you need another debug output
> method..

The G1 does not have any serial port :/
(and havent find any on the mainboard).

I guess the screen output will have problems due to the integrated video 
rom...
Is there any way to initialize video in this cases ?


> 
> 
> //Peter
> 




From svn at coreboot.org  Thu Jul  2 20:56:24 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Jul 2009 20:56:24 +0200
Subject: [coreboot] [v2] r4394 - in trunk/coreboot-v2/src: cpu/amd/sc520
	cpu/emulation/qemu-x86 cpu/ppc/ppc4xx devices include/device
	northbridge/amd/amdfam10 northbridge/amd/amdk8
	northbridge/amd/gx1 northbridge/amd/gx2 northbridge/amd/lx
	northbridge/ibm/cpc710 northbridge/ibm/cpc925
	northbridge/intel/e7501 northbridge/intel/e7520
	northbridge/intel/e7525 northbridge/intel/i3100
	northbridge/intel/i440bx northbridge/intel/i82810
	northbridge/intel/i82830 northbridge/intel/i855gme
	northbridge/intel/i855pm northbridge/intel/i945
	northbridge/motorola/mpc107 northbridge/via/cn400
	northbridge/via/cn700 northbridge/via/cx700
	northbridge/via/vt8601 northbridge/via/vt8623
	northbridge/via/vx800 southbridge/amd/amd8111
	southbridge/amd/amd8131 southbridge/amd/amd8132
	southbridge/amd/cs5530 southbridge/amd/cs5535
	southbridge/amd/cs5536 southbridge/amd/sb600
	southbridge/broadcom/bcm5785 southbridge/intel/esb6300
	southbridge/intel/i3100 southbridge/intel/i82371eb
	southbridge/intel/i82801ca southbridge/intel/i82801dbm
	southbridge/intel/i82801er southbridge/intel/i82801gx
	southbridge/intel/i82801xx southbridge/nvidia/ck804
	southbridge/nvidia/mcp55 southbridge/ricoh/rl5c476
	southbridge/sis/sis966 southbridge/via/vt8231
	southbridge/via/vt8235 southbridge/winbond/w83c553
Message-ID: <mailman.3513.1355071590.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-07-02 20:56:24 +0200 (Thu, 02 Jul 2009)
New Revision: 4394

Modified:
   trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c
   trunk/coreboot-v2/src/devices/cardbus_device.c
   trunk/coreboot-v2/src/devices/device.c
   trunk/coreboot-v2/src/devices/device_util.c
   trunk/coreboot-v2/src/devices/pci_device.c
   trunk/coreboot-v2/src/devices/root_device.c
   trunk/coreboot-v2/src/include/device/device.h
   trunk/coreboot-v2/src/include/device/resource.h
   trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c
   trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c
   trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
   trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c
   trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
   trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
   trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c
   trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c
   trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c
   trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c
   trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
   trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
   trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
   trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
   trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c
   trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
   trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c
   trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c
   trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
Log:
Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below) 
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -62,9 +62,27 @@
 
 }
 
+static void sc520_read_resources(device_t dev)
+{
+	struct resource* res;
 
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+
 static struct device_operations cpu_operations = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources   = sc520_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = sc520_enable_resources,
 	.init             = cpu_init,
@@ -78,25 +96,6 @@
 	.device = 0x3000
 };
 
-
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-  printk_spew("%s\n", __func__);
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -184,14 +183,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-  printk_spew("%s\n", __func__);
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
-
 #if 0
 void sc520_enable_resources(device_t dev) {
 
@@ -219,7 +210,7 @@
 	 * If enable_resources is set to the generic enable_resources
 	 * function the whole thing will hang in an endless loop on
 	 * the ts5300. If this is really needed on another platform,
-	 * something is conceptionally wrong.
+	 * something is conceptually wrong.
 	 */
         .enable_resources = 0, //enable_resources,
         .init             = 0,

Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include "chip.h"
 #include "northbridge.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -70,7 +53,7 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void cpu_pci_domain_set_resources(device_t dev)
 {
 	static const uint8_t ramregs[] = {
 		0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
@@ -127,15 +110,34 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static void cpu_pci_domain_read_resources(struct device *dev)
 {
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
+	struct resource *res;
+
+	pci_domain_read_resources(dev);
+
+	/* Reserve space for the IOAPIC.  This should be in the Southbridge,
+	 * but I couldn't tell which device to put it in. */
+	res = new_resource(dev, 2);
+	res->base = 0xfec00000UL;
+	res->size = 0x100000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
+
+	/* Reserve space for the LAPIC.  There's one in every processor, but
+	 * the space only needs to be reserved once, so we do it here. */
+	res = new_resource(dev, 3);
+	res->base = 0xfee00000UL;
+	res->size = 0x10000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources		= pci_domain_read_resources,
-	.set_resources		= pci_domain_set_resources,
+	.read_resources		= cpu_pci_domain_read_resources,
+	.set_resources		= cpu_pci_domain_set_resources,
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -7,27 +7,6 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {

Modified: trunk/coreboot-v2/src/devices/cardbus_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/cardbus_device.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/devices/cardbus_device.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -77,8 +77,6 @@
 	resource = find_resource(dev, index);
 	if (resource) {
 		min_size = resource->size;
-		compute_allocate_resource(&dev->link[0], resource, 
-			resource->flags, resource->flags);
 		/* Allways allocate at least the miniumum size to a
 		 * cardbus bridge in case a new card is plugged in.
 		 */

Modified: trunk/coreboot-v2/src/devices/device.c
===================================================================
--- trunk/coreboot-v2/src/devices/device.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/devices/device.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -12,6 +12,7 @@
  * Copyright (C) 2005-2006 Tyan
  * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
  * Copyright (C) 2005-2006 Stefan Reinauer <stepan at openbios.org>
+ * Copyright (C) 2009 Myles Watson <mylesgw at gmail.com>
  */
 
 /*
@@ -43,12 +44,6 @@
 /** Pointer to the last device */
 extern struct device **last_dev_p;
 
-/** The upper limit of MEM resource of the devices.
- * Reserve 20M for the system */
-#define DEVICE_MEM_HIGH 0xFEBFFFFFUL
-/** The lower limit of IO resource of the devices.
- * Reserve 4k for ISA/Legacy devices */
-#define DEVICE_IO_START 0x1000
 
 /**
  * @brief Allocate a new device structure.
@@ -71,25 +66,25 @@
 
 	spin_lock(&dev_lock);
 
-	/* Find the last child of our parent */
-	for(child = parent->children; child && child->sibling; ) {
+	/* Find the last child of our parent. */
+	for (child = parent->children; child && child->sibling; /* */ ) {
 		child = child->sibling;
 	}
 
 	dev = malloc(sizeof(*dev));
-	if (dev == 0) {
+	if (dev == 0)
 		die("DEV: out of memory.\n");
-	}
+
 	memset(dev, 0, sizeof(*dev));
 	memcpy(&dev->path, path, sizeof(*path));
 
-	/* Initialize the back pointers in the link fields */
-	for(link = 0; link < MAX_LINKS; link++) {
-		dev->link[link].dev  = dev;
+	/* Initialize the back pointers in the link fields. */
+	for (link = 0; link < MAX_LINKS; link++) {
+		dev->link[link].dev = dev;
 		dev->link[link].link = link;
 	}
 
-	/* By default devices are enabled */
+	/* By default devices are enabled. */
 	dev->enabled = 1;
 
 	/* Add the new device to the list of children of the bus. */
@@ -132,64 +127,46 @@
 {
 	struct device *curdev;
 
-	printk_spew("%s read_resources bus %d link: %d\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+	printk_spew("%s %s bus %x link: %d\n", dev_path(bus->dev), __func__,
+		    bus->secondary, bus->link);
 
-	/* Walk through all of the devices and find which resources they need. */
-	for(curdev = bus->children; curdev; curdev = curdev->sibling) {
-		unsigned links;
+	/* Walk through all devices and find which resources they need. */
+	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
 		int i;
-		if (curdev->have_resources) {
-			continue;
-		}
 		if (!curdev->enabled) {
 			continue;
 		}
 		if (!curdev->ops || !curdev->ops->read_resources) {
 			printk_err("%s missing read_resources\n",
-				dev_path(curdev));
+				   dev_path(curdev));
 			continue;
 		}
 		curdev->ops->read_resources(curdev);
-		curdev->have_resources = 1;
-		/* Read in subtractive resources behind the current device */
-		links = 0;
-		for(i = 0; i < curdev->resources; i++) {
-			struct resource *resource;
-			unsigned link;
-			resource = &curdev->resource[i];
-			if (!(resource->flags & IORESOURCE_SUBTRACTIVE))
-				continue;
-			link = IOINDEX_SUBTRACTIVE_LINK(resource->index);
-			if (link > MAX_LINKS) {
-				printk_err("%s subtractive index on link: %d\n",
-					dev_path(curdev), link);
-				continue;
-			}
-			if (!(links & (1 << link))) {
-				links |= (1 << link);
-				read_resources(&curdev->link[link]);
-			}
-		}
+
+		/* Read in the resources behind the current device's links. */
+		for (i = 0; i < curdev->links; i++)
+			read_resources(&curdev->link[i]);
 	}
 	printk_spew("%s read_resources bus %d link: %d done\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+		    dev_path(bus->dev), bus->secondary, bus->link);
 }
 
 struct pick_largest_state {
 	struct resource *last;
-	struct device   *result_dev;
+	struct device *result_dev;
 	struct resource *result;
 	int seen_last;
 };
 
-static void pick_largest_resource(void *gp,
-	struct device *dev, struct resource *resource)
+static void pick_largest_resource(void *gp, struct device *dev,
+				  struct resource *resource)
 {
 	struct pick_largest_state *state = gp;
 	struct resource *last;
+
 	last = state->last;
-	/* Be certain to pick the successor to last */
+
+	/* Be certain to pick the successor to last. */
 	if (resource == last) {
 		state->seen_last = 1;
 		return;
@@ -206,21 +183,22 @@
 	if (!state->result ||
 	    (state->result->align < resource->align) ||
 	    ((state->result->align == resource->align) &&
-	     (state->result->size < resource->size)))
-	{
+	     (state->result->size < resource->size))) {
 		state->result_dev = dev;
 		state->result = resource;
 	}
 }
 
-static struct device *largest_resource(struct bus *bus, struct resource **result_res,
-	unsigned long type_mask, unsigned long type)
+static struct device *largest_resource(struct bus *bus,
+				       struct resource **result_res,
+				       unsigned long type_mask,
+				       unsigned long type)
 {
 	struct pick_largest_state state;
 
 	state.last = *result_res;
-	state.result_dev = 0;
-	state.result = 0;
+	state.result_dev = NULL;
+	state.result = NULL;
 	state.seen_last = 0;
 
 	search_bus_resources(bus, type_mask, type, pick_largest_resource,
@@ -233,144 +211,136 @@
 /* Compute allocate resources is the guts of the resource allocator.
  *
  * The problem.
- *  - Allocate resources locations for every device.
+ *  - Allocate resource locations for every device.
  *  - Don't overlap, and follow the rules of bridges.
  *  - Don't overlap with resources in fixed locations.
  *  - Be efficient so we don't have ugly strategies.
  *
  * The strategy.
  * - Devices that have fixed addresses are the minority so don't
- *   worry about them too much.  Instead only use part of the address
- *   space for devices with programmable addresses.  This easily handles
+ *   worry about them too much. Instead only use part of the address
+ *   space for devices with programmable addresses. This easily handles
  *   everything except bridges.
  *
- * - PCI devices are required to have thier sizes and their alignments
- *   equal.  In this case an optimal solution to the packing problem
- *   exists.  Allocate all devices from highest alignment to least
- *   alignment or vice versa.  Use this.
+ * - PCI devices are required to have their sizes and their alignments
+ *   equal. In this case an optimal solution to the packing problem
+ *   exists. Allocate all devices from highest alignment to least
+ *   alignment or vice versa. Use this.
  *
- * - So we can handle more than PCI run two allocation passes on
- *   bridges.  The first to see how large the resources are behind
- *   the bridge, and what their alignment requirements are.  The
- *   second to assign a safe address to the devices behind the
- *   bridge.  This allows me to treat a bridge as just a device with
- *   a couple of resources, and not need to special case it in the
- *   allocator.  Also this allows handling of other types of bridges.
+ * - So we can handle more than PCI run two allocation passes on bridges. The
+ *   first to see how large the resources are behind the bridge, and what
+ *   their alignment requirements are. The second to assign a safe address to
+ *   the devices behind the bridge. This allows us to treat a bridge as just
+ *   a device with a couple of resources, and not need to special case it in
+ *   the allocator. Also this allows handling of other types of bridges.
  *
  */
-
-void compute_allocate_resource(
-	struct bus *bus,
-	struct resource *bridge,
-	unsigned long type_mask,
-	unsigned long type)
+void compute_resources(struct bus *bus, struct resource *bridge,
+		       unsigned long type_mask, unsigned long type)
 {
 	struct device *dev;
 	struct resource *resource;
 	resource_t base;
-	unsigned long align, min_align;
-	min_align = 0;
-	base = bridge->base;
+	base = round(bridge->base, bridge->align);
 
-	printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d\n",
-		dev_path(bus->dev),
-		(bridge->flags & IORESOURCE_IO)? "io":
-		(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
-		base, bridge->size, bridge->align, bridge->gran);
+	printk_spew( "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx\n",
+	       dev_path(bus->dev), __func__,
+	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
+	       "prefmem" : "mem",
+	       base, bridge->size, bridge->align, bridge->gran, bridge->limit);
 
-	/* We want different minimum alignments for different kinds of
-	 * resources.  These minimums are not device type specific
-	 * but resource type specific.
-	 */
-	if (bridge->flags & IORESOURCE_IO) {
-		min_align = log2(DEVICE_IO_ALIGN);
-	}
-	if (bridge->flags & IORESOURCE_MEM) {
-		min_align = log2(DEVICE_MEM_ALIGN);
-	}
+	/* For each child which is a bridge, compute_resource_needs. */
+	for (dev = bus->children; dev; dev = dev->sibling) {
+		unsigned i;
+		struct resource *child_bridge;
 
-	/* Make certain I have read in all of the resources */
-	read_resources(bus);
+		if (!dev->links)
+			continue;
 
-	/* Remember I haven't found anything yet. */
-	resource = 0;
+		/* Find the resources with matching type flags. */
+		for (i = 0; i < dev->resources; i++) {
+			unsigned link;
+			child_bridge = &dev->resource[i];
 
-	/* Walk through all the devices on the current bus and
-	 * compute the addresses.
-	 */
-	while((dev = largest_resource(bus, &resource, type_mask, type))) {
-		resource_t size;
-		/* Do NOT I repeat do not ignore resources which have zero size.
-		 * If they need to be ignored dev->read_resources should not even
-		 * return them.   Some resources must be set even when they have
-		 * no size.  PCI bridge resources are a good example of this.
-		 */
-		/* Make certain we are dealing with a good minimum size */
-		size = resource->size;
-		align = resource->align;
-		if (align < min_align) {
-			align = min_align;
-		}
+			if (!(child_bridge->flags & IORESOURCE_BRIDGE) ||
+			    (child_bridge->flags & type_mask) != type)
+				continue;
 
-		/* Propagate the resource alignment to the bridge register  */
-		if (align > bridge->align) {
-			bridge->align = align;
+			/* Split prefetchable memory if combined.  Many domains
+			 * use the same address space for prefetchable memory
+			 * and non-prefetchable memory.  Bridges below them
+			 * need it separated.  Add the PREFETCH flag to the
+			 * type_mask and type.
+			 */
+			link = IOINDEX_LINK(child_bridge->index);
+			compute_resources(&dev->link[link], child_bridge,
+					  type_mask | IORESOURCE_PREFETCH,
+					  type | (child_bridge->flags &
+						  IORESOURCE_PREFETCH));
 		}
+	}
 
-		if (resource->flags & IORESOURCE_FIXED) {
+	/* Remember we haven't found anything yet. */
+	resource = NULL;
+
+	/* Walk through all the resources on the current bus and compute the
+	 * amount of address space taken by them.  Take granularity and
+	 * alignment into account.
+	 */
+	while ((dev = largest_resource(bus, &resource, type_mask, type))) {
+
+		/* Size 0 resources can be skipped. */
+		if (!resource->size) {
 			continue;
 		}
 
-		/* Propogate the resource limit to the bridge register */
+		/* Propagate the resource alignment to the bridge resource. */
+		if (resource->align > bridge->align) {
+			bridge->align = resource->align;
+		}
+
+		/* Propagate the resource limit to the bridge register. */
 		if (bridge->limit > resource->limit) {
 			bridge->limit = resource->limit;
 		}
-#warning This heuristic should be replaced by real devices with fixed resources.
-		/* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */
-		if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) {
-			bridge->limit = DEVICE_MEM_HIGH;
+
+		/* Warn if it looks like APICs aren't declared. */
+		if ((resource->limit == 0xffffffff) &&
+		    (resource->flags & IORESOURCE_ASSIGNED)) {
+			printk_err("Resource limit looks wrong! (no APIC?)\n");
+			printk_err("%s %02lx limit %08Lx\n", dev_path(dev),
+			           resource->index, resource->limit);
 		}
 
 		if (resource->flags & IORESOURCE_IO) {
-			/* Don't allow potential aliases over the
-			 * legacy pci expansion card addresses.
-			 * The legacy pci decodes only 10 bits,
-			 * uses 100h - 3ffh. Therefor, only 0 - ff
-			 * can be used out of each 400h block of io
-			 * space.
+			/* Don't allow potential aliases over the legacy PCI
+			 * expansion card addresses. The legacy PCI decodes
+			 * only 10 bits, uses 0x100 - 0x3ff. Therefore, only
+			 * 0x00 - 0xff can be used out of each 0x400 block of
+			 * I/O space.
 			 */
 			if ((base & 0x300) != 0) {
 				base = (base & ~0x3ff) + 0x400;
 			}
-			/* Don't allow allocations in the VGA IO range.
+			/* Don't allow allocations in the VGA I/O range.
 			 * PCI has special cases for that.
 			 */
 			else if ((base >= 0x3b0) && (base <= 0x3df)) {
 				base = 0x3e0;
 			}
 		}
-		if (((round(base, align) + size) -1) <= resource->limit) {
-			/* base must be aligned to size */
-			base = round(base, align);
-			resource->base = base;
-			resource->flags |= IORESOURCE_ASSIGNED;
-			resource->flags &= ~IORESOURCE_STORED;
-			base += size;
+		/* Base must be aligned. */
+		base = round(base, resource->align);
+		resource->base = base;
+		base += resource->size;
 
-			printk_spew("%s %02lx *  [0x%08Lx - 0x%08Lx] %s\n",
-				dev_path(dev),
-				resource->index,
-				resource->base,
-				resource->base + resource->size - 1,
-				(resource->flags & IORESOURCE_IO)? "io":
-				(resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
-		}
-#if CONFIG_PCIE_CONFIGSPACE_HOLE
-#warning Handle PCIe hole differently...
-		if (base >= 0xf0000000 && base < 0xf4000000) {
-			base = 0xf4000000;
-		}
-#endif
+		printk_spew("%s %02lx *  [0x%llx - 0x%llx] %s\n",
+			    dev_path(dev), resource->index,
+			    resource->base,
+			    resource->base + resource->size - 1,
+			    (resource->flags & IORESOURCE_IO) ? "io" :
+			    (resource->flags & IORESOURCE_PREFETCH) ?
+			     "prefmem" : "mem");
 	}
 	/* A pci bridge resource does not need to be a power
 	 * of two size, but it does have a minimum granularity.
@@ -378,23 +348,327 @@
 	 * know not to place something else at an address postitively
 	 * decoded by the bridge.
 	 */
-	bridge->size = round(base, bridge->gran) - bridge->base;
+	bridge->size = round(base, bridge->gran) -
+		       round(bridge->base, bridge->align);
 
-	printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d done\n",
-		    dev_path(bus->dev),
-		    (bridge->flags & IORESOURCE_IO)? "io":
-		     (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
-		    base, bridge->size, bridge->align, bridge->gran);
+	printk_spew("%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n",
+		    dev_path(bus->dev), __func__,
+		    (bridge->flags & IORESOURCE_IO) ? "io" :
+		     (bridge->flags & IORESOURCE_PREFETCH) ?  "prefmem" : "mem",
+		    base, bridge->size, bridge->align, bridge->gran, bridge->limit);
 }
 
+/**
+ * This function is the second part of the resource allocator.
+ *
+ * The problem.
+ *  - Allocate resource locations for every device.
+ *  - Don't overlap, and follow the rules of bridges.
+ *  - Don't overlap with resources in fixed locations.
+ *  - Be efficient so we don't have ugly strategies.
+ *
+ * The strategy.
+ * - Devices that have fixed addresses are the minority so don't
+ *   worry about them too much. Instead only use part of the address
+ *   space for devices with programmable addresses. This easily handles
+ *   everything except bridges.
+ *
+ * - PCI devices are required to have their sizes and their alignments
+ *   equal. In this case an optimal solution to the packing problem
+ *   exists. Allocate all devices from highest alignment to least
+ *   alignment or vice versa. Use this.
+ *
+ * - So we can handle more than PCI run two allocation passes on bridges. The
+ *   first to see how large the resources are behind the bridge, and what
+ *   their alignment requirements are. The second to assign a safe address to
+ *   the devices behind the bridge. This allows us to treat a bridge as just
+ *   a device with a couple of resources, and not need to special case it in
+ *   the allocator. Also this allows handling of other types of bridges.
+ *
+ * - This function assigns the resources a value.
+ *
+ * @param bus The bus we are traversing.
+ * @param bridge The bridge resource which must contain the bus' resources.
+ * @param type_mask This value gets anded with the resource type.
+ * @param type This value must match the result of the and.
+ */
+void allocate_resources(struct bus *bus, struct resource *bridge,
+			unsigned long type_mask, unsigned long type)
+{
+	struct device *dev;
+	struct resource *resource;
+	resource_t base;
+	base = bridge->base;
+
+	printk_spew("%s %s_%s: base:%llx size:%llx align:%d gran:%d limit:%llx\n",
+	       dev_path(bus->dev), __func__,
+	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
+	       "prefmem" : "mem",
+	       base, bridge->size, bridge->align, bridge->gran, bridge->limit);
+
+	/* Remember we haven't found anything yet. */
+	resource = NULL;
+
+	/* Walk through all the resources on the current bus and allocate them
+	 * address space.
+	 */
+	while ((dev = largest_resource(bus, &resource, type_mask, type))) {
+
+		/* Propagate the bridge limit to the resource register. */
+		if (resource->limit > bridge->limit) {
+			resource->limit = bridge->limit;
+		}
+
+		/* Size 0 resources can be skipped. */
+		if (!resource->size) {
+			/* Set the base to limit so it doesn't confuse tolm. */
+			resource->base = resource->limit;
+			resource->flags |= IORESOURCE_ASSIGNED;
+			continue;
+		}
+
+		if (resource->flags & IORESOURCE_IO) {
+			/* Don't allow potential aliases over the legacy PCI
+			 * expansion card addresses. The legacy PCI decodes
+			 * only 10 bits, uses 0x100 - 0x3ff. Therefore, only
+			 * 0x00 - 0xff can be used out of each 0x400 block of
+			 * I/O space.
+			 */
+			if ((base & 0x300) != 0) {
+				base = (base & ~0x3ff) + 0x400;
+			}
+			/* Don't allow allocations in the VGA I/O range.
+			 * PCI has special cases for that.
+			 */
+			else if ((base >= 0x3b0) && (base <= 0x3df)) {
+				base = 0x3e0;
+			}
+		}
+
+		if ((round(base, resource->align) + resource->size - 1) <=
+		    resource->limit) {
+			/* Base must be aligned. */
+			base = round(base, resource->align);
+			resource->base = base;
+			resource->flags |= IORESOURCE_ASSIGNED;
+			resource->flags &= ~IORESOURCE_STORED;
+			base += resource->size;
+		} else {
+			printk_err("!! Resource didn't fit !!\n");
+			printk_err("   aligned base %llx size %llx limit %llx\n",
+			       round(base, resource->align), resource->size,
+			       resource->limit);
+			printk_err("   %llx needs to be <= %llx (limit)\n",
+			       (round(base, resource->align) +
+				resource->size) - 1, resource->limit);
+			printk_err("   %s%s %02lx *  [0x%llx - 0x%llx] %s\n",
+			       (resource->
+				flags & IORESOURCE_ASSIGNED) ? "Assigned: " :
+			       "", dev_path(dev), resource->index,
+			       resource->base,
+			       resource->base + resource->size - 1,
+			       (resource->
+				flags & IORESOURCE_IO) ? "io" : (resource->
+								 flags &
+								 IORESOURCE_PREFETCH)
+			       ? "prefmem" : "mem");
+		}
+
+		printk_spew("%s%s %02lx *  [0x%llx - 0x%llx] %s\n",
+		       (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: "
+		       : "",
+		       dev_path(dev), resource->index, resource->base,
+		       resource->size ? resource->base + resource->size - 1 :
+		       resource->base,
+		       (resource->flags & IORESOURCE_IO) ? "io" :
+		       (resource->flags & IORESOURCE_PREFETCH) ? "prefmem" :
+		       "mem");
+	}
+	/* A PCI bridge resource does not need to be a power of two size, but
+	 * it does have a minimum granularity. Round the size up to that
+	 * minimum granularity so we know not to place something else at an
+	 * address positively decoded by the bridge.
+	 */
+
+	bridge->flags |= IORESOURCE_ASSIGNED;
+
+	printk_spew("%s %s_%s: next_base: %llx size: %llx align: %d gran: %d done\n",
+	       dev_path(bus->dev), __func__,
+	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
+	       "prefmem" : "mem",
+	       base, bridge->size, bridge->align, bridge->gran);
+
+	/* For each child which is a bridge, allocate_resources. */
+	for (dev = bus->children; dev; dev = dev->sibling) {
+		unsigned i;
+		struct resource *child_bridge;
+
+		if (!dev->links)
+			continue;
+
+		/* Find the resources with matching type flags. */
+		for (i = 0; i < dev->resources; i++) {
+			unsigned link;
+			child_bridge = &dev->resource[i];
+
+			if (!(child_bridge->flags & IORESOURCE_BRIDGE) ||
+			    (child_bridge->flags & type_mask) != type)
+				continue;
+
+			/* Split prefetchable memory if combined.  Many domains
+			 * use the same address space for prefetchable memory
+			 * and non-prefetchable memory.  Bridges below them
+			 * need it separated.  Add the PREFETCH flag to the
+			 * type_mask and type.
+			 */
+			link = IOINDEX_LINK(child_bridge->index);
+			allocate_resources(&dev->link[link], child_bridge,
+					   type_mask | IORESOURCE_PREFETCH,
+					   type | (child_bridge->flags &
+						   IORESOURCE_PREFETCH));
+		}
+	}
+}
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+	#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
+#else
+	#define MEM_MASK (IORESOURCE_MEM)
+#endif
+#define IO_MASK (IORESOURCE_IO)
+#define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM)
+#define MEM_TYPE (IORESOURCE_MEM)
+#define IO_TYPE (IORESOURCE_IO)
+
+struct constraints {
+	struct resource pref, io, mem;
+};
+
+static void constrain_resources(struct device *dev, struct constraints* limits)
+{
+	struct device *child;
+	struct resource *res;
+	struct resource *lim;
+	int i;
+
+	printk_spew("%s: %s\n", __func__, dev_path(dev));
+
+	/* Constrain limits based on the fixed resources of this device. */
+	for (i = 0; i < dev->resources; i++) {
+		res = &dev->resource[i];
+		if (!(res->flags & IORESOURCE_FIXED))
+			continue;
+
+		/* PREFETCH, MEM, or I/O - skip any others. */
+		if ((res->flags & MEM_MASK) == PREF_TYPE)
+			lim = &limits->pref;
+		else if ((res->flags & MEM_MASK) == MEM_TYPE)
+			lim = &limits->mem;
+		else if ((res->flags & IO_MASK) == IO_TYPE)
+			lim = &limits->io;
+		else
+			continue;
+
+		/* Is it already outside the limits? */
+		if (res->size && (((res->base + res->size -1) < lim->base) ||
+				  (res->base > lim->limit)))
+			continue;
+
+		/* Choose to be above or below fixed resources.  This
+		 * check is signed so that "negative" amounts of space
+		 * are handled correctly.
+		 */
+		if ((signed long long)(lim->limit - (res->base + res->size -1)) >
+		    (signed long long)(res->base - lim->base))
+			lim->base = res->base + res->size;
+		else
+			lim->limit = res->base -1;
+	}
+
+	/* Descend into every enabled child and look for fixed resources. */
+	for (i = 0; i < dev->links; i++)
+		for (child = dev->link[i].children; child;
+		     child = child->sibling)
+			if (child->enabled)
+				constrain_resources(child, limits);
+}
+
+static void avoid_fixed_resources(struct device *dev)
+{
+	struct constraints limits;
+	struct resource *res;
+	int i;
+
+	printk_spew("%s: %s\n", __func__, dev_path(dev));
+	/* Initialize constraints to maximum size. */
+
+	limits.pref.base = 0;
+	limits.pref.limit = 0xffffffffffffffffULL;
+	limits.io.base = 0;
+	limits.io.limit = 0xffffffffffffffffULL;
+	limits.mem.base = 0;
+	limits.mem.limit = 0xffffffffffffffffULL;
+
+	/* Constrain the limits to dev's initial resources. */
+	for (i = 0; i < dev->resources; i++) {
+		res = &dev->resource[i];
+		if ((res->flags & IORESOURCE_FIXED))
+			continue;
+		printk_spew("%s:@%s %02lx limit %08Lx\n", __func__,
+			     dev_path(dev), res->index, res->limit);
+		if ((res->flags & MEM_MASK) == PREF_TYPE &&
+		    (res->limit < limits.pref.limit))
+			limits.pref.limit = res->limit;
+		if ((res->flags & MEM_MASK) == MEM_TYPE &&
+		    (res->limit < limits.mem.limit))
+			limits.mem.limit = res->limit;
+		if ((res->flags & IO_MASK) == IO_TYPE &&
+		    (res->limit < limits.io.limit))
+			limits.io.limit = res->limit;
+	}
+
+	/* Look through the tree for fixed resources and update the limits. */
+	constrain_resources(dev, &limits);
+
+	/* Update dev's resources with new limits. */
+	for (i = 0; i < dev->resources; i++) {
+		struct resource *lim;
+		res = &dev->resource[i];
+
+		if ((res->flags & IORESOURCE_FIXED))
+			continue;
+
+		/* PREFETCH, MEM, or I/O - skip any others. */
+		if ((res->flags & MEM_MASK) == PREF_TYPE)
+			lim = &limits.pref;
+		else if ((res->flags & MEM_MASK) == MEM_TYPE)
+			lim = &limits.mem;
+		else if ((res->flags & IO_MASK) == IO_TYPE)
+			lim = &limits.io;
+		else
+			continue;
+
+		printk_spew("%s2: %s@%02lx limit %08Lx\n", __func__,
+			     dev_path(dev), res->index, res->limit);
+		printk_spew("\tlim->base %08Lx lim->limit %08Lx\n",
+			     lim->base, lim->limit);
+
+		/* Is the resource outside the limits? */
+		if (lim->base > res->base)
+			res->base = lim->base;
+		if (res->limit > lim->limit)
+			res->limit = lim->limit;
+	}
+}
+
 #if CONFIG_CONSOLE_VGA == 1
 device_t vga_pri = 0;
 static void allocate_vga_resource(void)
 {
 #warning "FIXME modify allocate_vga_resource so it is less pci centric!"
-#warning "This function knows to much about PCI stuff, it should be just a ietrator/visitor."
+#warning "This function knows too much about PCI stuff, it should be just a iterator/visitor."
 
-	/* FIXME handle the VGA pallette snooping */
+	/* FIXME: Handle the VGA palette snooping. */
 	struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last;
 	struct bus *bus;
 	bus = 0;
@@ -402,66 +676,63 @@
 	vga_onboard = 0;
 	vga_first = 0;
 	vga_last = 0;
-	for(dev = all_devices; dev; dev = dev->next) {
-		if (!dev->enabled) continue;
+	for (dev = all_devices; dev; dev = dev->next) {
+		if (!dev->enabled)
+			continue;
 		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
-			((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER))
-		{
-                        if (!vga_first) {
-                                if (dev->on_mainboard) {
-                                        vga_onboard = dev;
-                                } else {
-                                        vga_first = dev;
-                                }
-                        } else {
-                                if (dev->on_mainboard) {
-                                        vga_onboard = dev;
-                                } else {
-                                        vga_last = dev;
-                                }
-                        }
+		    ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
+			if (!vga_first) {
+				if (dev->on_mainboard) {
+					vga_onboard = dev;
+				} else {
+					vga_first = dev;
+				}
+			} else {
+				if (dev->on_mainboard) {
+					vga_onboard = dev;
+				} else {
+					vga_last = dev;
+				}
+			}
 
-			/* It isn't safe to enable other VGA cards */
+			/* It isn't safe to enable other VGA cards. */
 			dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		}
 	}
 
-        vga = vga_last;
+	vga = vga_last;
 
-        if(!vga) {
-                vga = vga_first;
-        }
-
+	if (!vga) {
+		vga = vga_first;
+	}
 #if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1
-        if (vga_onboard) // will use on board vga as pri
+	if (vga_onboard)	// Will use on board VGA as pri.
 #else
-        if (!vga) // will use last add on adapter as pri
+	if (!vga)		// Will use last add on adapter as pri.
 #endif
-        {
-                vga = vga_onboard;
-        }
+	{
+		vga = vga_onboard;
+	}
 
-
 	if (vga) {
-		/* vga is first add on card or the only onboard vga */
+		/* VGA is first add on card or the only onboard VGA. */
 		printk_debug("Allocating VGA resource %s\n", dev_path(vga));
-		/* All legacy VGA cards have MEM & I/O space registers */
+		/* All legacy VGA cards have MEM & I/O space registers. */
 		vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		vga_pri = vga;
 		bus = vga->bus;
 	}
-	/* Now walk up the bridges setting the VGA enable */
-	while(bus) {
+	/* Now walk up the bridges setting the VGA enable. */
+	while (bus) {
 		printk_debug("Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
 			     dev_path(bus->dev));
 		bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
-		bus = (bus == bus->dev->bus)? 0 : bus->dev->bus;
+		bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
 	}
 }
 
 #endif
 
-
 /**
  * @brief  Assign the computed resources to the devices on the bus.
  *
@@ -480,21 +751,21 @@
 	struct device *curdev;
 
 	printk_spew("%s assign_resources, bus %d link: %d\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+		    dev_path(bus->dev), bus->secondary, bus->link);
 
-	for(curdev = bus->children; curdev; curdev = curdev->sibling) {
+	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
 		if (!curdev->enabled || !curdev->resources) {
 			continue;
 		}
 		if (!curdev->ops || !curdev->ops->set_resources) {
 			printk_err("%s missing set_resources\n",
-				dev_path(curdev));
+				   dev_path(curdev));
 			continue;
 		}
 		curdev->ops->set_resources(curdev);
 	}
 	printk_spew("%s assign_resources, bus %d link: %d\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+		    dev_path(bus->dev), bus->secondary, bus->link);
 }
 
 /**
@@ -539,8 +810,7 @@
  */
 int reset_bus(struct bus *bus)
 {
-	if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus)
-	{
+	if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus) {
 		bus->dev->ops->reset_bus(bus);
 		bus->reset_needed = 0;
 		return 1;
@@ -551,37 +821,34 @@
 /**
  * @brief Scan for devices on a bus.
  *
- * If there are bridges on the bus, recursively scan the buses behind the bridges.
- * If the setting up and tuning of the bus causes a reset to be required,
- * reset the bus and scan it again.
+ * If there are bridges on the bus, recursively scan the buses behind the
+ * bridges. If the setting up and tuning of the bus causes a reset to be
+ * required, reset the bus and scan it again.
  *
- * @param bus pointer to the bus device
- * @param max current bus number
- *
- * @return The maximum bus number found, after scanning all subordinate busses
+ * @param busdev Pointer to the bus device.
+ * @param max Current bus number.
+ * @return The maximum bus number found, after scanning all subordinate buses.
  */
-unsigned int scan_bus(device_t bus, unsigned int max)
+unsigned int scan_bus(struct device *busdev, unsigned int max)
 {
 	unsigned int new_max;
 	int do_scan_bus;
-	if (	!bus ||
-		!bus->enabled ||
-		!bus->ops ||
-		!bus->ops->scan_bus)
-	{
+	if (!busdev || !busdev->enabled || !busdev->ops ||
+	    !busdev->ops->scan_bus) {
 		return max;
 	}
+
 	do_scan_bus = 1;
-	while(do_scan_bus) {
+	while (do_scan_bus) {
 		int link;
-		new_max = bus->ops->scan_bus(bus, max);
+		new_max = busdev->ops->scan_bus(busdev, max);
 		do_scan_bus = 0;
-		for(link = 0; link < bus->links; link++) {
-			if (bus->link[link].reset_needed) {
-				if (reset_bus(&bus->link[link])) {
+		for (link = 0; link < busdev->links; link++) {
+			if (busdev->link[link].reset_needed) {
+				if (reset_bus(&busdev->link[link])) {
 					do_scan_bus = 1;
 				} else {
-					bus->bus->reset_needed = 1;
+					busdev->bus->reset_needed = 1;
 				}
 			}
 		}
@@ -589,7 +856,6 @@
 	return new_max;
 }
 
-
 /**
  * @brief Determine the existence of devices and extend the device tree.
  *
@@ -619,7 +885,7 @@
 	printk_info("Enumerating buses...\n");
 	root = &dev_root;
 
-	show_all_devs(BIOS_DEBUG, "Before Phase 3.");
+	show_all_devs(BIOS_DEBUG, "Before Device Enumeration.");
 	printk_debug("Compare with tree...\n");
 
 	show_devs_tree(root, BIOS_DEBUG, 0, 0);
@@ -643,66 +909,115 @@
  * requried by each device. In the second pass, the resources ranges are
  * relocated to their final position and stored to the hardware.
  *
- * I/O resources start at DEVICE_IO_START and grow upward. MEM resources start
- * at DEVICE_MEM_HIGH and grow downward.
+ * I/O resources grow upward. MEM resources grow downward.
  *
  * Since the assignment is hierarchical we set the values into the dev_root
  * struct.
  */
 void dev_configure(void)
 {
-	struct resource *io, *mem;
+	struct resource *res;
 	struct device *root;
+	struct device *child;
+	int i;
 
 	printk_info("Allocating resources...\n");
 
 	root = &dev_root;
 
-	print_resource_tree(root, BIOS_DEBUG, "Original.");
+	/* Each domain should create resources which contain the entire address
+	 * space for IO, MEM, and PREFMEM resources in the domain. The
+	 * allocation of device resources will be done from this address space.
+	 */
 
-	if (!root->ops || !root->ops->read_resources) {
-		printk_err("dev_root missing read_resources\n");
-		return;
-	}
-	if (!root->ops || !root->ops->set_resources) {
-		printk_err("dev_root missing set_resources\n");
-		return;
-	}
+	/* Read the resources for the entire tree. */
 
 	printk_info("Reading resources...\n");
-	root->ops->read_resources(root);
+	read_resources(&root->link[0]);
 	printk_info("Done reading resources.\n");
 
 	print_resource_tree(root, BIOS_DEBUG, "After reading.");
 
-	/* Get the resources */
-	io  = &root->resource[0];
-	mem = &root->resource[1];
-	/* Make certain the io devices are allocated somewhere safe. */
-	io->base = DEVICE_IO_START;
-	io->flags |= IORESOURCE_ASSIGNED;
-	io->flags &= ~IORESOURCE_STORED;
-	/* Now reallocate the pci resources memory with the
-	 * highest addresses I can manage.
+	/* Compute resources for all domains. */
+	for (child = root->link[0].children; child; child = child->sibling) {
+		if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
+			continue;
+		for (i = 0; i < child->resources; i++) {
+			res = &child->resource[i];
+			if (res->flags & IORESOURCE_FIXED)
+				continue;
+			if (res->flags & IORESOURCE_PREFETCH) {
+				compute_resources(&child->link[0],
+					       res, MEM_MASK, PREF_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_MEM) {
+				compute_resources(&child->link[0],
+					       res, MEM_MASK, MEM_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_IO) {
+				compute_resources(&child->link[0],
+					       res, IO_MASK, IO_TYPE);
+				continue;
+			}
+		}
+	}
+
+	/* For all domains. */
+	for (child = root->link[0].children; child; child=child->sibling)
+		if (child->path.type == DEVICE_PATH_PCI_DOMAIN)
+			avoid_fixed_resources(child);
+
+	/* Now we need to adjust the resources. MEM resources need to start at
+	 * the highest address managable.
 	 */
-	mem->base = resource_max(&root->resource[1]);
-	mem->flags |= IORESOURCE_ASSIGNED;
-	mem->flags &= ~IORESOURCE_STORED;
+	for (child = root->link[0].children; child; child = child->sibling) {
+		if (child->path.type != DEVICE_PATH_PCI_DOMAIN)
+			continue;
+		for (i = 0; i < child->resources; i++) {
+			res = &child->resource[i];
+			if (!(res->flags & IORESOURCE_MEM) ||
+			    res->flags & IORESOURCE_FIXED)
+				continue;
+			res->base = resource_max(res);
+		}
+	}
 
 #if CONFIG_CONSOLE_VGA == 1
-	/* Allocate the VGA I/O resource.. */
+	/* Allocate the VGA I/O resource. */
 	allocate_vga_resource();
 	print_resource_tree(root, BIOS_DEBUG, "After VGA.");
 #endif
 
 	/* Store the computed resource allocations into device registers ... */
 	printk_info("Setting resources...\n");
-	root->ops->set_resources(root);
+	for (child = root->link[0].children; child; child = child->sibling) {
+		if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
+			continue;
+		for (i = 0; i < child->resources; i++) {
+			res = &child->resource[i];
+			if (res->flags & IORESOURCE_FIXED)
+				continue;
+			if (res->flags & IORESOURCE_PREFETCH) {
+				allocate_resources(&child->link[0],
+					       res, MEM_MASK, PREF_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_MEM) {
+				allocate_resources(&child->link[0],
+					       res, MEM_MASK, MEM_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_IO) {
+				allocate_resources(&child->link[0],
+					       res, IO_MASK, IO_TYPE);
+				continue;
+			}
+		}
+	}
+	assign_resources(&root->link[0]);
 	printk_info("Done setting resources.\n");
-#if 0
-	mem->flags |= IORESOURCE_STORED;
-	report_resource_stored(root, mem, "");
-#endif
 	print_resource_tree(root, BIOS_DEBUG, "After assigning values.");
 
 	printk_info("Done allocating resources.\n");
@@ -736,13 +1051,13 @@
 	struct device *dev;
 
 	printk_info("Initializing devices...\n");
-	for(dev = all_devices; dev; dev = dev->next) {
+	for (dev = all_devices; dev; dev = dev->next) {
 		if (dev->enabled && !dev->initialized &&
-			dev->ops && dev->ops->init)
-		{
+		    dev->ops && dev->ops->init) {
 			if (dev->path.type == DEVICE_PATH_I2C) {
- 				printk_debug("smbus: %s[%d]->",
-					dev_path(dev->bus->dev), dev->bus->link);
+				printk_debug("smbus: %s[%d]->",
+					     dev_path(dev->bus->dev),
+					     dev->bus->link);
 			}
 			printk_debug("%s init\n", dev_path(dev));
 			dev->initialized = 1;
@@ -752,4 +1067,3 @@
 	printk_info("Devices initialized\n");
 	show_all_devs(BIOS_DEBUG, "After init.");
 }
-

Modified: trunk/coreboot-v2/src/devices/device_util.c
===================================================================
--- trunk/coreboot-v2/src/devices/device_util.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/devices/device_util.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -487,7 +487,7 @@
 	for(curdev = bus->children; curdev; curdev = curdev->sibling) {
 		int i;
 		/* Ignore disabled devices */
-		if (!curdev->have_resources) continue;
+		if (!curdev->enabled) continue;
 		for(i = 0; i < curdev->resources; i++) {
 			struct resource *resource = &curdev->resource[i];
 			/* If it isn't the right kind of resource ignore it */
@@ -514,7 +514,7 @@
 	for(curdev = all_devices; curdev; curdev = curdev->next) {
 		int i;
 		/* Ignore disabled devices */
-		if (!curdev->have_resources) continue;
+		if (!curdev->enabled) continue;
 		for(i = 0; i < curdev->resources; i++) {
 			struct resource *resource = &curdev->resource[i];
 			/* If it isn't the right kind of resource ignore it */

Modified: trunk/coreboot-v2/src/devices/pci_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_device.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/devices/pci_device.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -15,12 +15,12 @@
  */
 
 /*
- *      PCI Bus Services, see include/linux/pci.h for further explanation.
+ * PCI Bus Services, see include/linux/pci.h for further explanation.
  *
- *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
- *      David Mosberger-Tang
+ * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
+ * David Mosberger-Tang
  *
- *      Copyright 1997 -- 1999 Martin Mares <mj at atrey.karlin.mff.cuni.cz>
+ * Copyright 1997 -- 1999 Martin Mares <mj at atrey.karlin.mff.cuni.cz>
  */
 
 #include <console/console.h>
@@ -51,9 +51,9 @@
 #include <device/cardbus.h>
 #endif
 
-uint8_t pci_moving_config8(struct device *dev, unsigned reg)
+u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
-	uint8_t value, ones, zeroes;
+	u8 value, ones, zeroes;
 	value = pci_read_config8(dev, reg);
 
 	pci_write_config8(dev, reg, 0xff);
@@ -67,9 +67,9 @@
 	return ones ^ zeroes;
 }
 
-uint16_t pci_moving_config16(struct device *dev, unsigned reg)
+u16 pci_moving_config16(struct device * dev, unsigned int reg)
 {
-	uint16_t value, ones, zeroes;
+	u16 value, ones, zeroes;
 	value = pci_read_config16(dev, reg);
 
 	pci_write_config16(dev, reg, 0xffff);
@@ -83,9 +83,9 @@
 	return ones ^ zeroes;
 }
 
-uint32_t pci_moving_config32(struct device *dev, unsigned reg)
+u32 pci_moving_config32(struct device * dev, unsigned int reg)
 {
-	uint32_t value, ones, zeroes;
+	u32 value, ones, zeroes;
 	value = pci_read_config32(dev, reg);
 
 	pci_write_config32(dev, reg, 0xffffffff);
@@ -99,7 +99,16 @@
 	return ones ^ zeroes;
 }
 
-unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last)
+/**
+ * Given a device, a capability type, and a last position, return the next
+ * matching capability. Always start at the head of the list.
+ *
+ * @param dev Pointer to the device structure.
+ * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
+ * @param last Location of the PCI capability register to start from.
+ */
+unsigned pci_find_next_capability(struct device *dev, unsigned cap,
+				  unsigned last)
 {
 	unsigned pos;
 	unsigned status;
@@ -109,7 +118,7 @@
 	if (!(status & PCI_STATUS_CAP_LIST)) {
 		return 0;
 	}
-	switch(dev->hdr_type & 0x7f) {
+	switch (dev->hdr_type & 0x7f) {
 	case PCI_HEADER_TYPE_NORMAL:
 	case PCI_HEADER_TYPE_BRIDGE:
 		pos = PCI_CAPABILITY_LIST;
@@ -121,11 +130,12 @@
 		return 0;
 	}
 	pos = pci_read_config8(dev, pos);
-	while(reps-- && (pos >= 0x40)) {   /* loop through the linked list */
+	while (reps-- && (pos >= 0x40)) {	/* Loop through the linked list. */
 		int this_cap;
 		pos &= ~3;
 		this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
-		printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
+		printk_spew("Capability: type 0x%02x @ 0x%02x\n", this_cap,
+			    pos);
 		if (this_cap == 0xff) {
 			break;
 		}
@@ -140,64 +150,71 @@
 	return 0;
 }
 
+/**
+ * Given a device, and a capability type, return the next matching
+ * capability. Always start at the head of the list.
+ *
+ * @param dev Pointer to the device structure.
+ * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
+ */
 unsigned pci_find_capability(device_t dev, unsigned cap)
 {
 	return pci_find_next_capability(dev, cap, 0);
-
 }
 
-/** Given a device and register, read the size of the BAR for that register.
- * @param dev       Pointer to the device structure
- * @param resource  Pointer to the resource structure
- * @param index     Address of the pci configuration register
+/**
+ * Given a device and register, read the size of the BAR for that register.
+ *
+ * @param dev Pointer to the device structure.
+ * @param index Address of the PCI configuration register.
  */
 struct resource *pci_get_resource(struct device *dev, unsigned long index)
 {
 	struct resource *resource;
 	unsigned long value, attr;
-	resource_t  moving, limit;
+	resource_t moving, limit;
 
-	/* Initialize the resources to nothing */
+	/* Initialize the resources to nothing. */
 	resource = new_resource(dev, index);
 
-	/* Get the initial value */
+	/* Get the initial value. */
 	value = pci_read_config32(dev, index);
 
-	/* See which bits move */
+	/* See which bits move. */
 	moving = pci_moving_config32(dev, index);
 
-	/* Initialize attr to the bits that do not move */
+	/* Initialize attr to the bits that do not move. */
 	attr = value & ~moving;
 
-	/* If it is a 64bit resource look at the high half as well */
+	/* If it is a 64bit resource look at the high half as well. */
 	if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
-		((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
-	{
-		/* Find the high bits that move */
-		moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
+	    ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
+	     PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
+		/* Find the high bits that move. */
+		moving |=
+		    ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
 	}
 	/* Find the resource constraints.
-	 *
 	 * Start by finding the bits that move. From there:
 	 * - Size is the least significant bit of the bits that move.
 	 * - Limit is all of the bits that move plus all of the lower bits.
-	 * See PCI Spec 6.2.5.1 ...
+	 * See PCI Spec 6.2.5.1.
 	 */
 	limit = 0;
 	if (moving) {
 		resource->size = 1;
 		resource->align = resource->gran = 0;
-		while(!(moving & resource->size)) {
+		while (!(moving & resource->size)) {
 			resource->size <<= 1;
 			resource->align += 1;
-			resource->gran  += 1;
+			resource->gran += 1;
 		}
 		resource->limit = limit = moving | (resource->size - 1);
 	}
-	/*
-	 * some broken hardware has read-only registers that do not
+
+	/* Some broken hardware has read-only registers that do not
 	 * really size correctly.
-	 * Example: the acer m7229 has BARs 1-4 normally read-only.
+	 * Example: the Acer M7229 has BARs 1-4 normally read-only.
 	 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
 	 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
 	 * violation of the spec.
@@ -207,21 +224,19 @@
 	 */
 	if (moving == 0) {
 		if (value != 0) {
-			printk_debug(
-				"%s register %02lx(%08lx), read-only ignoring it\n",
-				dev_path(dev), index, value);
+			printk_debug
+			    ("%s register %02lx(%08lx), read-only ignoring it\n",
+			     dev_path(dev), index, value);
 		}
 		resource->flags = 0;
-	}
-	else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
-		/* An I/O mapped base address */
+	} else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
+		/* An I/O mapped base address. */
 		attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
 		resource->flags |= IORESOURCE_IO;
-		/* I don't want to deal with 32bit I/O resources */
+		/* I don't want to deal with 32bit I/O resources. */
 		resource->limit = 0xffff;
-	}
-	else {
-		/* A Memory mapped base address */
+	} else {
+		/* A Memory mapped base address. */
 		attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 		resource->flags |= IORESOURCE_MEM;
 		if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
@@ -229,73 +244,65 @@
 		}
 		attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
 		if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
-			/* 32bit limit */
+			/* 32bit limit. */
 			resource->limit = 0xffffffffUL;
-		}
-		else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
-			/* 1MB limit */
+		} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
+			/* 1MB limit. */
 			resource->limit = 0x000fffffUL;
-		}
-		else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
-			/* 64bit limit */
+		} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
+			/* 64bit limit. */
 			resource->limit = 0xffffffffffffffffULL;
 			resource->flags |= IORESOURCE_PCI64;
-		}
-		else {
-			/* Invalid value */
+		} else {
+			/* Invalid value. */
+			printk_err("Broken BAR with value %lx\n", attr);
+			printk_err(" on dev %s at index %02lx\n",
+			       dev_path(dev), index);
 			resource->flags = 0;
 		}
 	}
-	/* Don't let the limit exceed which bits can move */
+	/* Don't let the limit exceed which bits can move. */
 	if (resource->limit > limit) {
 		resource->limit = limit;
 	}
-#if 0
-	if (resource->flags) {
-		printk_debug("%s %02x ->",
-			dev_path(dev), resource->index);
-		printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
-			value, zeroes, ones, attr);
-		printk_debug(
-			"%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ",
-			dev_path(dev),
-			resource->index,
-			resource->size,	resource->limit,
-			resource_type(resource));
-	}
-#endif
 
 	return resource;
 }
 
+/**
+ * Given a device and an index, read the size of the BAR for that register.
+ *
+ * @param dev Pointer to the device structure.
+ * @param index Address of the PCI configuration register.
+ */
 static void pci_get_rom_resource(struct device *dev, unsigned long index)
 {
 	struct resource *resource;
 	unsigned long value;
-	resource_t  moving;
+	resource_t moving;
 
-        if ((dev->on_mainboard) && (dev->rom_address == 0)) {
-		//skip it if rom_address is not set in MB Config.lb
-                return;
-        }
+	if ((dev->on_mainboard) && (dev->rom_address == 0)) {
+		/* Skip it if rom_address is not set in the MB Config.lb. */
+		return;
+	}
 
-	/* Initialize the resources to nothing */
+	/* Initialize the resources to nothing. */
 	resource = new_resource(dev, index);
 
-	/* Get the initial value */
+	/* Get the initial value. */
 	value = pci_read_config32(dev, index);
 
-	/* See which bits move */
+	/* See which bits move. */
 	moving = pci_moving_config32(dev, index);
-	/* clear the Enable bit */
+
+	/* Clear the Enable bit. */
 	moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
 
 	/* Find the resource constraints.
-	 *
 	 * Start by finding the bits that move. From there:
 	 * - Size is the least significant bit of the bits that move.
 	 * - Limit is all of the bits that move plus all of the lower bits.
-	 * See PCI Spec 6.2.5.1 ...
+	 * See PCI Spec 6.2.5.1.
 	 */
 	if (moving) {
 		resource->size = 1;
@@ -303,59 +310,57 @@
 		while (!(moving & resource->size)) {
 			resource->size <<= 1;
 			resource->align += 1;
-			resource->gran  += 1;
+			resource->gran += 1;
 		}
 		resource->limit = moving | (resource->size - 1);
-	}
-
-	if (moving == 0) {
+		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
+	} else {
 		if (value != 0) {
-			printk_debug("%s register %02lx(%08lx), read-only ignoring it\n",
-				     dev_path(dev), index, value);
+			printk_debug
+			    ("%s register %02lx(%08lx), read-only ignoring it\n",
+			     dev_path(dev), index, value);
 		}
 		resource->flags = 0;
-	} else {
-		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
 	}
 
-	/* for on board device with embedded ROM image, the ROM image is at
+	/* For on board device with embedded ROM image, the ROM image is at
 	 * fixed address specified in the Config.lb, the dev->rom_address is
 	 * inited by driver_pci_onboard_ops::enable_dev() */
 	if ((dev->on_mainboard) && (dev->rom_address != 0)) {
-		resource->base   = dev->rom_address;
+		resource->base = dev->rom_address;
 		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
-			IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+		    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 	}
 
 	compact_resources(dev);
 }
 
-/** Read the base address registers for a given device.
- * @param dev Pointer to the dev structure
- * @param howmany How many registers to read (6 for device, 2 for bridge)
+/**
+ * Read the base address registers for a given device.
+ *
+ * @param dev Pointer to the dev structure.
+ * @param howmany How many registers to read (6 for device, 2 for bridge).
  */
 static void pci_read_bases(struct device *dev, unsigned int howmany)
 {
 	unsigned long index;
 
-	for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
+	for (index = PCI_BASE_ADDRESS_0;
+	     (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
 		struct resource *resource;
 		resource = pci_get_resource(dev, index);
-		index += (resource->flags & IORESOURCE_PCI64)?8:4;
+		index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
 	}
 
 	compact_resources(dev);
 }
 
-static void pci_set_resource(struct device *dev, struct resource *resource);
-
-static void pci_record_bridge_resource(
-	struct device *dev, resource_t moving,
-	unsigned index, unsigned long mask, unsigned long type)
+static void pci_record_bridge_resource(struct device *dev, resource_t moving,
+				       unsigned index, unsigned long type)
 {
-	/* Initiliaze the constraints on the current bus */
+	/* Initialize the constraints on the current bus. */
 	struct resource *resource;
-	resource = 0;
+	resource = NULL;
 	if (moving) {
 		unsigned long gran;
 		resource_t step;
@@ -363,29 +368,15 @@
 		resource->size = 0;
 		gran = 0;
 		step = 1;
-		while((moving & step) == 0) {
+		while ((moving & step) == 0) {
 			gran += 1;
 			step <<= 1;
 		}
 		resource->gran = gran;
 		resource->align = gran;
 		resource->limit = moving | (step - 1);
-		resource->flags = type | IORESOURCE_PCI_BRIDGE;
-		compute_allocate_resource(&dev->link[0], resource, mask, type);
-		/* If there is nothing behind the resource,
-		 * clear it and forget it.
-		 */
-		if (resource->size == 0) {
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
-			resource->base = moving;
-#else
-			resource->base = moving & 0xffffffff;
-#endif
-			resource->flags |= IORESOURCE_ASSIGNED;
-			resource->flags &= ~IORESOURCE_STORED;
-			pci_set_resource(dev, resource);
-			resource->flags = 0;
-		}
+		resource->flags = type | IORESOURCE_PCI_BRIDGE |
+				  IORESOURCE_BRIDGE;
 	}
 	return;
 }
@@ -394,47 +385,48 @@
 {
 	resource_t moving_base, moving_limit, moving;
 
-	/* See if the bridge I/O resources are implemented */
-	moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
-	moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
+	/* See if the bridge I/O resources are implemented. */
+	moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
+	moving_base |=
+	    ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
 
-	moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
-	moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
+	moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
+	moving_limit |=
+	    ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
 
 	moving = moving_base & moving_limit;
 
-	/* Initialize the io space constraints on the current bus */
-	pci_record_bridge_resource(
-		dev, moving, PCI_IO_BASE,
-		IORESOURCE_IO, IORESOURCE_IO);
+	/* Initialize the I/O space constraints on the current bus. */
+	pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
 
+	/* See if the bridge prefmem resources are implemented. */
+	moving_base =
+	    ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
+	moving_base |=
+	    ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) <<
+	    32;
 
-	/* See if the bridge prefmem resources are implemented */
-	moving_base =  ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
-	moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
+	moving_limit =
+	    ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) <<
+	    16;
+	moving_limit |=
+	    ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) <<
+	    32;
 
-	moving_limit =  ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
-	moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
-
 	moving = moving_base & moving_limit;
-	/* Initiliaze the prefetchable memory constraints on the current bus */
-	pci_record_bridge_resource(
-		dev, moving, PCI_PREF_MEMORY_BASE,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH);
+	/* Initialize the prefetchable memory constraints on the current bus. */
+	pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
+				   IORESOURCE_MEM | IORESOURCE_PREFETCH);
 
+	/* See if the bridge mem resources are implemented. */
+	moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
+	moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
 
-	/* See if the bridge mem resources are implemented */
-	moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
-	moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
-
 	moving = moving_base & moving_limit;
 
-	/* Initialize the memory resources on the current bus */
-	pci_record_bridge_resource(
-		dev, moving, PCI_MEMORY_BASE,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM);
+	/* Initialize the memory resources on the current bus. */
+	pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
+				   IORESOURCE_MEM);
 
 	compact_resources(dev);
 }
@@ -452,34 +444,50 @@
 	pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
 }
 
+void pci_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Initialize the system-wide I/O space constraints. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED;
+
+	/* Initialize the system-wide memory resources constraints. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED;
+}
+
 static void pci_set_resource(struct device *dev, struct resource *resource)
 {
 	resource_t base, end;
 
-	/* Make certain the resource has actually been set */
+	/* Make certain the resource has actually been assigned a value. */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n",
-			dev_path(dev), resource->index,
-			resource_type(resource),
-			resource->size);
+		printk_err("ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
+			   dev_path(dev), resource->index,
+			   resource_type(resource), resource->size);
 		return;
 	}
 
-	/* If I have already stored this resource don't worry about it */
+	/* If I have already stored this resource don't worry about it. */
 	if (resource->flags & IORESOURCE_STORED) {
 		return;
 	}
 
-	/* If the resources is substractive don't worry about it */
+	/* If the resource is subtractive don't worry about it. */
 	if (resource->flags & IORESOURCE_SUBTRACTIVE) {
 		return;
 	}
 
-	/* Only handle PCI memory and IO resources for now */
-	if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
+	/* Only handle PCI memory and I/O resources for now. */
+	if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 		return;
 
-	/* Enable the resources in the command register */
+	/* Enable the resources in the command register. */
 	if (resource->size) {
 		if (resource->flags & IORESOURCE_MEM) {
 			dev->command |= PCI_COMMAND_MEMORY;
@@ -491,19 +499,29 @@
 			dev->command |= PCI_COMMAND_MASTER;
 		}
 	}
-	/* Get the base address */
+	/* Get the base address. */
 	base = resource->base;
 
-	/* Get the end */
+	/* Get the end. */
 	end = resource_end(resource);
 
-	/* Now store the resource */
+	/* Now store the resource. */
 	resource->flags |= IORESOURCE_STORED;
+
+	/* PCI Bridges have no enable bit.  They are disabled if the base of
+	 * the range is greater than the limit.  If the size is zero, disable
+	 * by setting the base = limit and end = limit - 2^gran.
+	 */
+	if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
+		base = resource->limit;
+		end = resource->limit - (1 << resource->gran);
+		resource->base = base;
+	}
+
 	if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 		unsigned long base_lo, base_hi;
-		/*
-		 * some chipsets allow us to set/clear the IO bit.
-		 * (e.g. VIA 82c686a.) So set it to be safe)
+		/* Some chipsets allow us to set/clear the I/O bit
+		 * (e.g. VIA 82c686a). So set it to be safe.
 		 */
 		base_lo = base & 0xffffffff;
 		base_hi = (base >> 32) & 0xffffffff;
@@ -514,39 +532,27 @@
 		if (resource->flags & IORESOURCE_PCI64) {
 			pci_write_config32(dev, resource->index + 4, base_hi);
 		}
-	}
-	else if (resource->index == PCI_IO_BASE) {
-		/* set the IO ranges */
-		compute_allocate_resource(&dev->link[0], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
-		pci_write_config8(dev,  PCI_IO_BASE, base >> 8);
+	} else if (resource->index == PCI_IO_BASE) {
+		/* Set the I/O ranges. */
+		pci_write_config8(dev, PCI_IO_BASE, base >> 8);
 		pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
-		pci_write_config8(dev,  PCI_IO_LIMIT, end >> 8);
+		pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
 		pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
-	}
-	else if (resource->index == PCI_MEMORY_BASE) {
-		/* set the memory range	 */
-		compute_allocate_resource(&dev->link[0], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
+	} else if (resource->index == PCI_MEMORY_BASE) {
+		/* Set the memory range. */
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
 		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
-	}
-	else if (resource->index == PCI_PREF_MEMORY_BASE) {
-		/* set the prefetchable memory range */
-		compute_allocate_resource(&dev->link[0], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
+	} else if (resource->index == PCI_PREF_MEMORY_BASE) {
+		/* Set the prefetchable memory range. */
 		pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
 		pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
 		pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
 		pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
-	}
-	else {
-		/* Don't let me think I stored the resource */
+	} else {
+		/* Don't let me think I stored the resource. */
 		resource->flags &= ~IORESOURCE_STORED;
 		printk_err("ERROR: invalid resource->index %lx\n",
-			resource->index);
+			   resource->index);
 	}
 	report_resource_stored(dev, resource, "");
 	return;
@@ -556,14 +562,14 @@
 {
 	struct resource *resource, *last;
 	unsigned link;
-	uint8_t line;
+	u8 line;
 
 	last = &dev->resource[dev->resources];
 
-	for(resource = &dev->resource[0]; resource < last; resource++) {
+	for (resource = &dev->resource[0]; resource < last; resource++) {
 		pci_set_resource(dev, resource);
 	}
-	for(link = 0; link < dev->links; link++) {
+	for (link = 0; link < dev->links; link++) {
 		struct bus *bus;
 		bus = &dev->link[link];
 		if (bus->children) {
@@ -571,60 +577,64 @@
 		}
 	}
 
-	/* set a default latency timer */
+	/* Set a default latency timer. */
 	pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 
-	/* set a default secondary latency timer */
+	/* Set a default secondary latency timer. */
 	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
 		pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
 	}
 
-	/* zero the irq settings */
+	/* Zero the IRQ settings. */
 	line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
 	if (line) {
 		pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 	}
-	/* set the cache line size, so far 64 bytes is good for everyone */
+	/* Set the cache line size, so far 64 bytes is good for everyone. */
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
 
 void pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
-	uint16_t command;
+	u16 command;
 
-	/* Set the subsystem vendor and device id for mainboard devices */
+	/* Set the subsystem vendor and device id for mainboard devices. */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk_debug("%s subsystem <- %02x/%02x\n",
-			dev_path(dev),
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			     dev_path(dev),
+			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 		ops->set_subsystem(dev,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+				   CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+				   CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
+	/* v3 has
+	 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR);	// Error check.
+	 */
 	printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
 }
 
 void pci_bus_enable_resources(struct device *dev)
 {
-	uint16_t ctrl;
-	/* enable IO in command register if there is VGA card
-	 * connected with (even it does not claim IO resource) */
+	u16 ctrl;
+
+	/* Enable I/O in command register if there is VGA card
+	 * connected with (even it does not claim I/O resource).
+	 */
 	if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
 		dev->command |= PCI_COMMAND_IO;
 	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 	ctrl |= dev->link[0].bridge_ctrl;
-	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
+	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR);	/* Error check. */
 	printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
 	pci_dev_enable_resources(dev);
-
 	enable_childrens_resources(dev);
 }
 
@@ -640,17 +650,17 @@
 	delay(1);
 }
 
-void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 /** default handler: only runs the relevant pci bios. */
 void pci_dev_init(struct device *dev)
 {
 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
-	void run_bios(struct device * dev, unsigned long addr);
+	void run_bios(struct device *dev, unsigned long addr);
 	struct rom_header *rom, *ram;
 
 #if CONFIG_PCI_ROM_RUN != 1
@@ -658,7 +668,7 @@
 	 * is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
 	 * all other option ROM types.
 	 */
-	if ((dev->class>>8)!=PCI_CLASS_DISPLAY_VGA)
+	if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
 		return;
 #endif
 
@@ -685,13 +695,13 @@
 };
 
 struct device_operations default_pci_ops_dev = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init		  = pci_dev_init,
-	.scan_bus	  = 0,
-	.enable           = 0,
-	.ops_pci          = &pci_dev_ops_pci,
+	.init = pci_dev_init,
+	.scan_bus = 0,
+	.enable = 0,
+	.ops_pci = &pci_dev_ops_pci,
 };
 
 /** Default device operations for PCI bridges */
@@ -700,32 +710,29 @@
 };
 
 struct device_operations default_pci_ops_bus = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
-	.init		  = 0,
-	.scan_bus	  = pci_scan_bridge,
-	.enable           = 0,
-	.reset_bus        = pci_bus_reset,
-	.ops_pci          = &pci_bus_ops_pci,
+	.init = 0,
+	.scan_bus = pci_scan_bridge,
+	.enable = 0,
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &pci_bus_ops_pci,
 };
 
 /**
  * @brief Detect the type of downstream bridge
  *
- * This function is a heuristic to detect which type
- * of bus is downstream of a pci to pci bridge.  This
- * functions by looking for various capability blocks
- * to figure out the type of downstream bridge.  PCI-X
- * PCI-E, and Hypertransport all seem to have appropriate
- * capabilities.
+ * This function is a heuristic to detect which type of bus is downstream
+ * of a PCI-to-PCI bridge. This functions by looking for various capability
+ * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
+ * Hypertransport all seem to have appropriate capabilities.
  *
  * When only a PCI-Express capability is found the type
  * is examined to see which type of bridge we have.
  *
- * @param dev
- *
- * @return appropriate bridge operations
+ * @param dev Pointer to the device structure of the bridge.
+ * @return Appropriate bridge operations.
  */
 static struct device_operations *get_pci_bridge_ops(device_t dev)
 {
@@ -743,13 +750,13 @@
 #endif
 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
 	pos = 0;
-	while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
+	while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
 		unsigned flags;
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 		if ((flags >> 13) == 1) {
 			/* Host or Secondary Interface */
 			printk_debug("%s subbordinate bus Hypertransport\n",
-				dev_path(dev));
+				     dev_path(dev));
 			return &default_ht_ops_bus;
 		}
 	}
@@ -759,16 +766,15 @@
 	if (pos) {
 		unsigned flags;
 		flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
-		switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
+		switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
 		case PCI_EXP_TYPE_ROOT_PORT:
 		case PCI_EXP_TYPE_UPSTREAM:
 		case PCI_EXP_TYPE_DOWNSTREAM:
 			printk_debug("%s subbordinate bus PCI Express\n",
-				dev_path(dev));
+				     dev_path(dev));
 			return &default_pciexp_ops_bus;
 		case PCI_EXP_TYPE_PCI_BRIDGE:
-			printk_debug("%s subbordinate PCI\n",
-				dev_path(dev));
+			printk_debug("%s subbordinate PCI\n", dev_path(dev));
 			return &default_pci_ops_bus;
 		default:
 			break;
@@ -779,11 +785,10 @@
 }
 
 /**
- * @brief Set up PCI device operation
+ * Set up PCI device operation.  Check if it already has a driver.  If not, use
+ * find_device_operations, or set to a default based on type.
  *
- *
- * @param dev
- *
+ * @param dev Pointer to the device whose pci_ops you want to set.
  * @see pci_drivers
  */
 static void set_pci_ops(struct device *dev)
@@ -794,23 +799,22 @@
 	}
 
 	/* Look through the list of setup drivers and find one for
-	 * this pci device
+	 * this PCI device.
 	 */
-	for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
+	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
 		if ((driver->vendor == dev->vendor) &&
-			(driver->device == dev->device))
-		{
+		    (driver->device == dev->device)) {
 			dev->ops = driver->ops;
 			printk_spew("%s [%04x/%04x] %sops\n",
-				dev_path(dev),
-				driver->vendor, driver->device,
-				(driver->ops->scan_bus?"bus ":""));
+				    dev_path(dev),
+				    driver->vendor, driver->device,
+				    (driver->ops->scan_bus ? "bus " : ""));
 			return;
 		}
 	}
 
 	/* If I don't have a specific driver use the default operations */
-	switch(dev->hdr_type & 0x7f) {	/* header type */
+	switch (dev->hdr_type & 0x7f) {	/* header type */
 	case PCI_HEADER_TYPE_NORMAL:	/* standard header */
 		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 			goto bad;
@@ -827,20 +831,18 @@
 		break;
 #endif
 	default:
-	bad:
+	      bad:
 		if (dev->enabled) {
 			printk_err("%s [%04x/%04x/%06x] has unknown header "
-				"type %02x, ignoring.\n",
-				dev_path(dev),
-				dev->vendor, dev->device,
-				dev->class >> 8, dev->hdr_type);
+				   "type %02x, ignoring.\n",
+				   dev_path(dev),
+				   dev->vendor, dev->device,
+				   dev->class >> 8, dev->hdr_type);
 		}
 	}
 	return;
 }
 
-
-
 /**
  * @brief See if we have already allocated a device structure for a given devfn.
  *
@@ -848,42 +850,43 @@
  * device structure correspond to the devfn, if present. This function also
  * removes the device structure from the linked list.
  *
- * @param list the device structure list
- * @param devfn a device/function number
+ * @param list The device structure list.
+ * @param devfn A device/function number.
  *
- * @return pointer to the device structure found or null of we have not
+ * @return Pointer to the device structure found or NULL if we have not
  *	   allocated a device for this devfn yet.
  */
 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
 {
 	struct device *dev;
 	dev = 0;
-	for(; *list; list = &(*list)->sibling) {
+	for (; *list; list = &(*list)->sibling) {
 		if ((*list)->path.type != DEVICE_PATH_PCI) {
 			printk_err("child %s not a pci device\n",
-				dev_path(*list));
+				   dev_path(*list));
 			continue;
 		}
 		if ((*list)->path.pci.devfn == devfn) {
-			/* Unlink from the list */
+			/* Unlink from the list. */
 			dev = *list;
 			*list = (*list)->sibling;
-			dev->sibling = 0;
+			dev->sibling = NULL;
 			break;
 		}
 	}
-	/* Just like alloc_dev add the device to the  list of device on the bus.
-	 * When the list of devices was formed we removed all of the parents
-	 * children, and now we are interleaving static and dynamic devices in
-	 * order on the bus.
+
+	/* Just like alloc_dev() add the device to the list of devices on the
+	 * bus. When the list of devices was formed we removed all of the
+	 * parents children, and now we are interleaving static and dynamic
+	 * devices in order on the bus.
 	 */
 	if (dev) {
-		device_t child;
-		/* Find the last child of our parent */
-		for(child = dev->bus->children; child && child->sibling; ) {
+		struct device *child;
+		/* Find the last child of our parent. */
+		for (child = dev->bus->children; child && child->sibling;) {
 			child = child->sibling;
 		}
-		/* Place the device on the list of children of it's parent. */
+		/* Place the device on the list of children of its parent. */
 		if (child) {
 			child->sibling = dev;
 		} else {
@@ -897,7 +900,8 @@
 /**
  * @brief Scan a PCI bus.
  *
- * Determine the existence of a given PCI device.
+ * Determine the existence of a given PCI device. Allocate a new struct device
+ * if dev==NULL was passed in and the device exists in hardware.
  *
  * @param bus pointer to the bus structure
  * @param devfn to look at
@@ -905,107 +909,94 @@
  * @return The device structure for hte device (if found)
  *         or the NULL if no device is found.
  */
-device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
+device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
 {
-	uint32_t id, class;
-	uint8_t hdr_type;
+	u32 id, class;
+	u8 hdr_type;
 
-	/* Detect if a device is present */
+	/* Detect if a device is present. */
 	if (!dev) {
 		struct device dummy;
-		dummy.bus              = bus;
-		dummy.path.type        = DEVICE_PATH_PCI;
+		dummy.bus = bus;
+		dummy.path.type = DEVICE_PATH_PCI;
 		dummy.path.pci.devfn = devfn;
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
-		/* Have we found somthing?
+		/* Have we found something?
 		 * Some broken boards return 0 if a slot is empty.
 		 */
-		if (	(id == 0xffffffff) || (id == 0x00000000) ||
-			(id == 0x0000ffff) || (id == 0xffff0000))
-		{
+		if ((id == 0xffffffff) || (id == 0x00000000) ||
+		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
 			return NULL;
 		}
 		dev = alloc_dev(bus, &dummy.path);
-	}
-	else {
-		/* Enable/disable the device.  Once we have
-		 * found the device specific operations this
-		 * operations we will disable the device with
-		 * those as well.
+	} else {
+		/* Enable/disable the device. Once we have found the device-
+		 * specific operations this operations we will disable the
+		 * device with those as well.
 		 *
 		 * This is geared toward devices that have subfunctions
 		 * that do not show up by default.
 		 *
 		 * If a device is a stuff option on the motherboard
-		 * it may be absent and enable_dev must cope.
-		 *
+		 * it may be absent and enable_dev() must cope.
 		 */
-		/* Run the magice enable sequence for the device */
+		/* Run the magic enable sequence for the device. */
 		if (dev->chip_ops && dev->chip_ops->enable_dev) {
 			dev->chip_ops->enable_dev(dev);
 		}
-		/* Now read the vendor and device id */
+		/* Now read the vendor and device ID. */
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 
-
-		/* If the device does not have a pci id disable it.
-		 * Possibly this is because we have already disabled
-		 * the device.  But this also handles optional devices
-		 * that may not always show up.
+		/* If the device does not have a PCI ID disable it. Possibly
+		 * this is because we have already disabled the device. But
+		 * this also handles optional devices that may not always
+		 * show up.
 		 */
 		/* If the chain is fully enumerated quit */
-		if (	(id == 0xffffffff) || (id == 0x00000000) ||
-			(id == 0x0000ffff) || (id == 0xffff0000))
-		{
+		if ((id == 0xffffffff) || (id == 0x00000000) ||
+		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			if (dev->enabled) {
 				printk_info("Disabling static device: %s\n",
-					dev_path(dev));
+					    dev_path(dev));
 				dev->enabled = 0;
 			}
 			return dev;
 		}
 	}
-	/* Read the rest of the pci configuration information */
+	/* Read the rest of the PCI configuration information. */
 	hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 	class = pci_read_config32(dev, PCI_CLASS_REVISION);
 
-	/* Store the interesting information in the device structure */
+	/* Store the interesting information in the device structure. */
 	dev->vendor = id & 0xffff;
 	dev->device = (id >> 16) & 0xffff;
 	dev->hdr_type = hdr_type;
-	/* class code, the upper 3 bytes of PCI_CLASS_REVISION */
+
+	/* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
 	dev->class = class >> 8;
 
-
-	/* Architectural/System devices always need to
-	 * be bus masters.
-	 */
+	/* Architectural/System devices always need to be bus masters. */
 	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
 		dev->command |= PCI_COMMAND_MASTER;
 	}
-	/* Look at the vendor and device id, or at least the
-	 * header type and class and figure out which set of
-	 * configuration methods to use.  Unless we already
-	 * have some pci ops.
+	/* Look at the vendor and device ID, or at least the header type and
+	 * class and figure out which set of configuration methods to use.
+	 * Unless we already have some PCI ops.
 	 */
 	set_pci_ops(dev);
 
-	/* Now run the magic enable/disable sequence for the device */
+	/* Now run the magic enable/disable sequence for the device. */
 	if (dev->ops && dev->ops->enable) {
 		dev->ops->enable(dev);
 	}
 
-
-	/* Display the device and error if we don't have some pci operations
-	 * for it.
-	 */
+	/* Display the device. */
 	printk_debug("%s [%04x/%04x] %s%s\n",
-		dev_path(dev),
-		dev->vendor, dev->device,
-		dev->enabled?"enabled": "disabled",
-		dev->ops?"" : " No operations"
-		);
+		     dev_path(dev),
+		     dev->vendor, dev->device,
+		     dev->enabled ? "enabled" : "disabled",
+		     dev->ops ? "" : " No operations");
 
 	return dev;
 }
@@ -1027,73 +1018,69 @@
  * @return The maximum bus number found, after scanning all subordinate busses
  */
 unsigned int pci_scan_bus(struct bus *bus,
-	unsigned min_devfn, unsigned max_devfn,
-	unsigned int max)
+			  unsigned min_devfn, unsigned max_devfn,
+			  unsigned int max)
 {
 	unsigned int devfn;
-	device_t old_devices;
-	device_t child;
+	struct device *old_devices;
+	struct device *child;
 
 #if CONFIG_PCI_BUS_SEGN_BITS
-	printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
+	printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
+		     bus->secondary >> 8, bus->secondary & 0xff);
 #else
 	printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
 #endif
 
 	old_devices = bus->children;
-	bus->children = 0;
+	bus->children = NULL;
 
 	post_code(0x24);
-	/* probe all devices/functions on this bus with some optimization for
-	 * non-existence and single funcion devices
+	/* Probe all devices/functions on this bus with some optimization for
+	 * non-existence and single function devices.
 	 */
 	for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
-		device_t dev;
+		struct device *dev;
 
 		/* First thing setup the device structure */
 		dev = pci_scan_get_dev(&old_devices, devfn);
 
-		/* See if a device is present and setup the device
-		 * structure.
-		 */
+		/* See if a device is present and setup the device structure. */
 		dev = pci_probe_dev(dev, bus, devfn);
 
-		/* if this is not a multi function device,
-		 * or the device is not present don't waste
-		 * time probing another function.
+		/* If this is not a multi function device, or the device is
+		 * not present don't waste time probing another function.
 		 * Skip to next device.
 		 */
 		if ((PCI_FUNC(devfn) == 0x00) &&
-			(!dev || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80))))
-		{
+		    (!dev
+		     || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
 			devfn += 0x07;
 		}
 	}
 	post_code(0x25);
 
-	/* Die if any left over static devices are are found.
+	/* Warn if any leftover static devices are are found.
 	 * There's probably a problem in the Config.lb.
-	*/
-	if(old_devices) {
+	 */
+	if (old_devices) {
 		device_t left;
-		for(left = old_devices; left; left = left->sibling) {
-			printk_err("%s\n", dev_path(left));
+		printk_warning("PCI: Left over static devices:\n");
+		for (left = old_devices; left; left = left->sibling) {
+			printk_warning("%s\n", dev_path(left));
 		}
-		printk_warning("PCI: Left over static devices.  Check your mainboard Config.lb\n");
+		printk_warning("PCI: Check your mainboard Config.lb.\n");
 	}
 
-	/* For all children that implement scan_bus (i.e. bridges)
+	/* For all children that implement scan_bus() (i.e. bridges)
 	 * scan the bus behind that child.
 	 */
-	for(child = bus->children; child; child = child->sibling) {
+	for (child = bus->children; child; child = child->sibling) {
 		max = scan_bus(child, max);
 	}
 
-	/*
-	 * We've scanned the bus and so we know all about what's on
-	 * the other side of any bridges that may be on this bus plus
-	 * any devices.
-	 *
+	/* We've scanned the bus and so we know all about what's on the other
+	 * side of any bridges that may be on this bus plus any devices.
 	 * Return how far we've got finding sub-buses.
 	 */
 	printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
@@ -1101,7 +1088,6 @@
 	return max;
 }
 
-
 /**
  * @brief Scan a PCI bridge and the buses behind the bridge.
  *
@@ -1110,18 +1096,19 @@
  *
  * This function is the default scan_bus() method for PCI bridge devices.
  *
- * @param dev pointer to the bridge device
- * @param max the highest bus number assgined up to now
- *
- * @return The maximum bus number found, after scanning all subordinate busses
+ * @param dev Pointer to the bridge device.
+ * @param max The highest bus number assigned up to now.
+ * @return The maximum bus number found, after scanning all subordinate buses.
  */
 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
-	unsigned int (*do_scan_bus)(struct bus *bus,
-		unsigned min_devfn, unsigned max_devfn, unsigned int max))
+				unsigned int (*do_scan_bus) (struct bus * bus,
+							     unsigned min_devfn,
+							     unsigned max_devfn,
+							     unsigned int max))
 {
 	struct bus *bus;
-	uint32_t buses;
-	uint16_t cr;
+	u32 buses;
+	u16 cr;
 
 	printk_spew("%s for %s\n", __func__, dev_path(dev));
 
@@ -1141,8 +1128,7 @@
 	pci_write_config16(dev, PCI_COMMAND, 0x0000);
 	pci_write_config16(dev, PCI_STATUS, 0xffff);
 
-	/*
-	 * Read the existing primary/secondary/subordinate bus
+	/* Read the existing primary/secondary/subordinate bus
 	 * number configuration.
 	 */
 	buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
@@ -1152,9 +1138,9 @@
 	 * correctly configured.
 	 */
 	buses &= 0xff000000;
-	buses |= (((unsigned int) (dev->bus->secondary) << 0) |
-		((unsigned int) (bus->secondary) << 8) |
-		((unsigned int) (bus->subordinate) << 16));
+	buses |= (((unsigned int)(dev->bus->secondary) << 0) |
+		  ((unsigned int)(bus->secondary) << 8) |
+		  ((unsigned int)(bus->subordinate) << 16));
 	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 
 	/* Now we can scan all subordinate buses
@@ -1166,8 +1152,7 @@
 	 * bus number to its real value.
 	 */
 	bus->subordinate = max;
-	buses = (buses & 0xff00ffff) |
-		((unsigned int) (bus->subordinate) << 16);
+	buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
 	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 	pci_write_config16(dev, PCI_COMMAND, cr);
 
@@ -1183,90 +1168,109 @@
  *
  * This function is the default scan_bus() method for PCI bridge devices.
  *
- * @param dev pointer to the bridge device
+ * @param dev Pointer to the bridge device.
+ * @param max The highest bus number assigned up to now.
+ * @return The maximum bus number found, after scanning all subordinate buses.
+ */
+unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
+{
+	return do_pci_scan_bridge(dev, max, pci_scan_bus);
+}
+
+/**
+ * @brief Scan a PCI domain.
+ *
+ * This function is the default scan_bus() method for PCI domains.
+ *
+ * @param dev pointer to the domain
  * @param max the highest bus number assgined up to now
  *
  * @return The maximum bus number found, after scanning all subordinate busses
  */
-unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
+unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 {
-	return do_pci_scan_bridge(dev, max, pci_scan_bus);
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
 }
 
-/*
-    Tell the EISA int controller this int must be level triggered
-    THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
-*/
+/**
+ * Tell the EISA int controller this int must be level triggered.
+ *
+ * THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
+ */
 void pci_level_irq(unsigned char intNum)
 {
-	unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
+	unsigned short intBits = inb(0x4d0) | (((unsigned)inb(0x4d1)) << 8);
 
 	printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
 	intBits |= (1 << intNum);
 
 	printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
 
-	// Write new values
-	outb((unsigned char) intBits, 0x4d0);
-	outb((unsigned char) (intBits >> 8), 0x4d1);
+	/* Write new values. */
+	outb((unsigned char)intBits, 0x4d0);
+	outb((unsigned char)(intBits >> 8), 0x4d1);
 
-	/* this seems like an error but is not ... */
-#if 1
+	/* This seems like an error but is not. */
 	if (inb(0x4d0) != (intBits & 0xff)) {
-	  printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
-		     __func__, intBits &0xff, inb(0x4d0));
+		printk_err(
+			   "%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
+			   __func__, intBits & 0xff, inb(0x4d0));
 	}
 	if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
-	  printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
-		     __func__, (intBits>>8) &0xff, inb(0x4d1));
+		printk_err(
+			   "%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
+			   __func__, (intBits >> 8) & 0xff, inb(0x4d1));
 	}
-#endif
 }
 
-/*
-    This function assigns IRQs for all functions contained within
-    the indicated device address.  If the device does not exist or does
-    not require interrupts then this function has no effect.
-
-    This function should be called for each PCI slot in your system.
-
-    pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
-    this slot.
-    The particular irq #s that are passed in depend on the routing inside
-    your southbridge and on your motherboard.
-
-    -kevinh at ispiri.com
+/**
+ * This function assigns IRQs for all functions contained within the
+ * indicated device address. If the device does not exist or does not
+ * require interrupts then this function has no effect.
+ *
+ * This function should be called for each PCI slot in your system.
+ *
+ * pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
+ * this slot.
+ *
+ * The particular irq #s that are passed in depend on the routing inside
+ * your southbridge and on your motherboard.
+ *
+ * -kevinh at ispiri.com
+ *
 */
 void pci_assign_irqs(unsigned bus, unsigned slot,
-	const unsigned char pIntAtoD[4])
+		     const unsigned char pIntAtoD[4])
 {
 	unsigned functNum;
-	device_t pdev;
+	struct device *pdev;
 	unsigned char line;
 	unsigned char irq;
 	unsigned char readback;
 
-	/* Each slot may contain up to eight functions */
+	/* Each slot may contain up to eight functions. */
 	for (functNum = 0; functNum < 8; functNum++) {
 		pdev = dev_find_slot(bus, (slot << 3) + functNum);
 
 		if (pdev) {
-		  line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
+			line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
 
-			// PCI spec says all other values are reserved
+			/* PCI spec says all other values are reserved. */
 			if ((line >= 1) && (line <= 4)) {
 				irq = pIntAtoD[line - 1];
 
-				printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
-					irq, bus, slot, functNum);
+				printk_debug("Assigning IRQ %d to %d:%x.%d\n",
+					     irq, bus, slot, functNum);
 
-				pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
-					pIntAtoD[line - 1]);
+				pci_write_config8(pdev, PCI_INTERRUPT_LINE,
+						  pIntAtoD[line - 1]);
 
-				readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
+				readback =
+				    pci_read_config8(pdev, PCI_INTERRUPT_LINE);
 				printk_debug("  Readback = %d\n", readback);
 
-				// Change to level triggered
+				// Change to level triggered.
 				pci_level_irq(pIntAtoD[line - 1]);
 			}
 		}

Modified: trunk/coreboot-v2/src/devices/root_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/root_device.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/devices/root_device.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -34,29 +34,7 @@
  */
 void root_dev_read_resources(device_t root)
 {
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(root, 0);
-	resource->base  = 0x400;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO;
-	compute_allocate_resource(&root->link[0], resource, 
-		IORESOURCE_IO, IORESOURCE_IO);
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(root, 1);
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM;
-	compute_allocate_resource(&root->link[0], resource,
-		IORESOURCE_MEM, IORESOURCE_MEM);
+	printk_err("%s should never be called.\n", __func__);
 }
 
 /**
@@ -68,14 +46,7 @@
  */
 void root_dev_set_resources(device_t root)
 {
-	struct bus *bus;
-
-	bus = &root->link[0];
-	compute_allocate_resource(bus,
-		&root->resource[0], IORESOURCE_IO, IORESOURCE_IO);
-	compute_allocate_resource(bus, 
-		&root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
-	assign_resources(bus);
+	printk_err("%s should never be called.\n", __func__);
 }
 
 /**

Modified: trunk/coreboot-v2/src/include/device/device.h
===================================================================
--- trunk/coreboot-v2/src/include/device/device.h	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/include/device/device.h	2009-07-02 18:56:24 UTC (rev 4394)
@@ -69,17 +69,16 @@
 	unsigned int	hdr_type;	/* PCI header type */
 	unsigned int    enabled : 1;	/* set if we should enable the device */
 	unsigned int    initialized : 1; /* set if we have initialized the device */
-	unsigned int    have_resources : 1; /* Set if we have read the devices resources */
 	unsigned int    on_mainboard : 1;
 	unsigned long   rom_address;
 
-	uint8_t command;
+	u8 command;
 
 	/* Base registers for this device. I/O, MEM and Expansion ROM */
 	struct resource resource[MAX_RESOURCES];
 	unsigned int resources;
 
-	/* link are (down stream) buses attached to the device, usually a leaf
+	/* links are (downstream) buses attached to the device, usually a leaf
 	 * device with no children have 0 buses attached and a bridge has 1 bus 
 	 */
 	struct bus link[MAX_LINKS];
@@ -106,8 +105,6 @@
 /* Generic device helper functions */
 int reset_bus(struct bus *bus);
 unsigned int scan_bus(struct device *bus, unsigned int max);
-void compute_allocate_resource(struct bus *bus, struct resource *bridge,
-	unsigned long type_mask, unsigned long type);
 void assign_resources(struct bus *bus);
 void enable_resources(struct device *dev);
 void enumerate_static_device(void);
@@ -142,6 +139,8 @@
 #define DEVICE_MEM_ALIGN 4096
 
 extern struct device_operations default_dev_ops_root;
+void pci_domain_read_resources(struct device *dev);
+unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
 void root_dev_read_resources(device_t dev);
 void root_dev_set_resources(device_t dev);
 unsigned int scan_static_bus(device_t bus, unsigned int max);

Modified: trunk/coreboot-v2/src/include/device/resource.h
===================================================================
--- trunk/coreboot-v2/src/include/device/resource.h	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/include/device/resource.h	2009-07-02 18:56:24 UTC (rev 4394)
@@ -1,5 +1,5 @@
-#ifndef RESOURCE_H
-#define RESOURCE_H
+#ifndef DEVICE_RESOURCE_H
+#define DEVICE_RESOURCE_H
 
 #include <stdint.h>
 
@@ -19,6 +19,7 @@
 #define IORESOURCE_SUBTRACTIVE  0x00040000	/* This resource filters all of the unclaimed transactions
 						 * to the bus below.
 						 */
+#define IORESOURCE_BRIDGE	0x00080000	/* The IO resource has a bus below it. */
 #define IORESOURCE_STORED	0x20000000	/* The IO resource assignment has been stored in the device */
 #define IORESOURCE_ASSIGNED	0x40000000	/* An IO resource that has been assigned a value */
 #define IORESOURCE_FIXED	0x80000000	/* An IO resource the allocator must not change */
@@ -62,7 +63,7 @@
 #define IORESOURCE_MEM_EXPANSIONROM	(1<<6)
 
 
-typedef uint64_t resource_t;
+typedef u64 resource_t;
 struct resource {
 	resource_t base;	/* Base address of the resource */
 	resource_t size;	/* Size of the resource */
@@ -74,10 +75,14 @@
 	/* Alignment must be >= the granularity of the resource */
 };
 
-/* Macros to generate index values for subtractive resources */
+/* Macros to generate index values for resources */
 #define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) + LINK)
 #define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff)
 
+#define IOINDEX(IDX,LINK) (((LINK) << 16) + IDX)
+#define IOINDEX_LINK(IDX) (( IDX & 0xf0000) >> 16)
+#define IOINDEX_IDX(IDX) (IDX & 0xffff)
+
 /* Generic resource helper functions */
 struct device;
 struct bus;
@@ -101,4 +106,4 @@
 #define RESOURCE_TYPE_MAX 20
 extern const char *resource_type(struct resource *resource);
 
-#endif /* RESOURCE_H */
+#endif /* DEVICE_RESOURCE_H */

Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -341,7 +341,7 @@
 		if (!dev)
 			continue;
 		for(link = 0; !res && (link < 8); link++) {
-			res = probe_resource(dev, 0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1,
+			res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
 		}
 	}
 	result = 2;
@@ -385,7 +385,7 @@
 		reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
 	}
 
-	resource = new_resource(dev, 0x1000 + reg + (link<<16));
+		resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
 
 	return resource;
 }
@@ -421,7 +421,7 @@
 		reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
 
 	}
-	resource = new_resource(dev, 0x1000 + reg + (link<<16));
+	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
 	return resource;
 }
 
@@ -447,8 +447,6 @@
 		resource->gran	= align;
 		resource->limit = 0xffffUL;
 		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource,
-					IORESOURCE_IO, IORESOURCE_IO);
 	}
 
 	/* Initialize the prefetchable memory constraints on the current bus */
@@ -460,9 +458,6 @@
 		resource->gran	= log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
 
 #if CONFIG_EXT_CONF_SUPPORT == 1
 		if((resource->index & 0x1fff) == 0x1110) { // ext
@@ -481,9 +476,6 @@
 		resource->gran	= log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 
 #if CONFIG_EXT_CONF_SUPPORT == 1
 		if((resource->index & 0x1fff) == 0x1110) { // ext
@@ -541,19 +533,14 @@
 
 	/* Get the register and link */
 	reg  = resource->index & 0xfff; // 4k
-	link = ( resource->index>> 16)& 0x7; // 8 links
+	link = IOINDEX_LINK(resource->index);
 
 	if (resource->flags & IORESOURCE_IO) {
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 
 		set_io_addr_reg(dev, nodeid, link, reg, rbase>>8, rend>>8);
 		store_conf_io_addr(nodeid, link, reg, (resource->index >> 24), rbase>>8, rend>>8);
 	}
 	else if (resource->flags & IORESOURCE_MEM) {
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
 		set_mmio_addr_reg(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
 		store_conf_mmio_addr(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8);
 	}
@@ -657,7 +644,7 @@
 	.enable_dev = 0,
 };
 
-static void pci_domain_read_resources(device_t dev)
+static void amdfam10_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 	unsigned reg;
@@ -672,20 +659,20 @@
 		/* Is this register allocated? */
 		if ((base & 3) != 0) {
 			unsigned nodeid, link;
-			device_t dev;
+			device_t reg_dev;
 			if(reg<0xc0) { // mmio
 				nodeid = (limit & 0xf) + (base&0x30);
 			} else { // io
 				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
 			}
 			link   = (limit >> 4) & 7;
-			dev = __f0_dev[nodeid];
-			if (dev) {
-				/* Reserve the resource	 */
-				struct resource *resource;
-				resource = new_resource(dev, 0x1000 + reg + (link<<16));
-				if (resource) {
-					resource->flags = 1;
+			reg_dev = __f0_dev[nodeid];
+			if (reg_dev) {
+				/* Reserve the resource  */
+				struct resource *reg_resource;
+				reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, link));
+				if (reg_resource) {
+					reg_resource->flags = 1;
 				}
 			}
 		}
@@ -711,24 +698,16 @@
 		resource->base	= 0x400;
 		resource->limit = 0xffffUL;
 		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 
 		/* Initialize the system wide prefetchable memory resources constraints */
 		resource = new_resource(dev, 1|(link<<2));
 		resource->limit = 0xfcffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
 
 		/* Initialize the system wide memory resources constraints */
 		resource = new_resource(dev, 2|(link<<2));
 		resource->limit = 0xfcffffffffULL;
 		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 	}
 #endif
 }
@@ -770,10 +749,6 @@
 	return tolm;
 }
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
-#endif
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 
 struct hw_mem_hole_info {
@@ -980,9 +955,6 @@
 		resource->flags |= IORESOURCE_ASSIGNED;
 		resource->flags &= ~IORESOURCE_STORED;
 		link = (resource>>2) & 3;
-		compute_allocate_resource(&dev->link[link], resource,
-			BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
-
 		resource->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, resource, "");
 
@@ -1142,7 +1114,7 @@
 	}
 }
 
-static u32 pci_domain_scan_bus(device_t dev, u32 max)
+static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
 {
 	u32 reg;
 	int i;
@@ -1192,11 +1164,11 @@
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources	  = pci_domain_read_resources,
+	.read_resources	  = amdfam10_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init		  = 0,
-	.scan_bus	  = pci_domain_scan_bus,
+	.scan_bus	  = amdfam10_domain_scan_bus,
 #if CONFIG_MMCONF_SUPPORT_DEFAULT
 	.ops_pci_bus	  = &pci_ops_mmconf,
 #else

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -53,7 +53,7 @@
 	if (iommu) {
 		/* Add a Gart apeture resource */
 		resource = new_resource(dev, 0x94);
-		resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1;
+		resource->size = CONFIG_AGP_APERTURE_SIZE;
 		resource->align = log2(resource->size);
 		resource->gran  = log2(resource->size);
 		resource->limit = 0xffffffff; /* 4G */

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -297,7 +297,7 @@
 		if (!dev)
 			continue;
 		for(link = 0; !res && (link < 3); link++) {
-			res = probe_resource(dev, 0x100 + (reg | link));
+			res = probe_resource(dev, IOINDEX(0x100 + reg, link));
 		}
 	}
 	result = 2;
@@ -335,7 +335,7 @@
 		reg = free_reg;
 	}
 	if (reg > 0) {
-		resource = new_resource(dev, 0x100 + (reg | link));
+		resource = new_resource(dev, IOINDEX(0x100 + reg, link));
 	}
 	return resource;
 }
@@ -362,7 +362,7 @@
 		reg = free_reg;
 	}
 	if (reg > 0) {
-		resource = new_resource(dev, 0x100 + (reg | link));
+		resource = new_resource(dev, IOINDEX(0x100 + reg, link));
 	}
 	return resource;
 }
@@ -379,9 +379,7 @@
 		resource->align = log2(HT_IO_HOST_ALIGN);
 		resource->gran  = log2(HT_IO_HOST_ALIGN);
 		resource->limit = 0xffffUL;
-		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
+		resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
 	}
 
 	/* Initialize the prefetchable memory constraints on the current bus */
@@ -393,9 +391,9 @@
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
+#ifdef CONFIG_PCI_64BIT_PREF_MEM
+		resource->flags |= IORESOURCE_BRIDGE;
+#endif
 	}
 
 	/* Initialize the memory constraints on the current bus */
@@ -405,11 +403,8 @@
 		resource->size  = 0;
 		resource->align = log2(HT_MEM_HOST_ALIGN);
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
-		resource->limit = 0xffffffffffULL;
-		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
+		resource->limit = 0xffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
 	}
 }
 
@@ -432,11 +427,15 @@
 
 	/* Make certain the resource has actually been set */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		printk_err("%s: can't set unassigned resource @%lx %lx\n",
+			   __func__, resource->index, resource->flags);
 		return;
 	}
 
 	/* If I have already stored this resource don't worry about it */
 	if (resource->flags & IORESOURCE_STORED) {
+		printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
+			   resource->index, resource->flags);
 		return;
 	}
 
@@ -448,6 +447,10 @@
 	if (resource->index < 0x100) {
 		return;
 	}
+
+	if (resource->size == 0)
+		return;
+
 	/* Get the base address */
 	rbase = resource->base;
 
@@ -456,12 +459,10 @@
 
 	/* Get the register and link */
 	reg  = resource->index & 0xfc;
-	link = resource->index & 3;
+	link = IOINDEX_LINK(resource->index);
 
 	if (resource->flags & IORESOURCE_IO) {
 		uint32_t base, limit;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0xfe000fcc;
@@ -486,9 +487,6 @@
 	}
 	else if (resource->flags & IORESOURCE_MEM) {
 		uint32_t base, limit;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0x000000f0;
@@ -634,7 +632,7 @@
 	.enable_dev = 0,
 };
 
-static void pci_domain_read_resources(device_t dev)
+static void amdk8_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 	unsigned reg;
@@ -655,48 +653,21 @@
 			if (reg_dev) {
 				/* Reserve the resource  */
 				struct resource *reg_resource;
-				reg_resource = new_resource(reg_dev, 0x100 + (reg | link));
+				reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
 				if (reg_resource) {
 					reg_resource->flags = 1;
 				}
 			}
 		}
 	}
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base  = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-#else
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, 0);
-	resource->base  = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_IO, IORESOURCE_IO);
+	pci_domain_read_resources(dev);
 
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	/* Initialize the system wide prefetchable memory resources constraints */
-	resource = new_resource(dev, 1);
-	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH);
-
-	/* Initialize the system wide memory resources constraints */
 	resource = new_resource(dev, 2);
 	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM);
+	resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 #endif
 }
 
@@ -739,10 +710,6 @@
 	return tolm;
 }
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
-#endif
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 
 struct hw_mem_hole_info {
@@ -898,7 +865,7 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void amdk8_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	struct resource *io, *mem1, *mem2;
@@ -964,13 +931,7 @@
 	last = &dev->resource[dev->resources];
 	for(resource = &dev->resource[0]; resource < last; resource++)
 	{
-#if 1
 		resource->flags |= IORESOURCE_ASSIGNED;
-		resource->flags &= ~IORESOURCE_STORED;
-#endif
-		compute_allocate_resource(&dev->link[0], resource,
-			BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
-
 		resource->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, resource, "");
 
@@ -1125,7 +1086,7 @@
 
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
 {
 	unsigned reg;
 	int i;
@@ -1160,11 +1121,11 @@
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
+	.read_resources   = amdk8_domain_read_resources,
+	.set_resources    = amdk8_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = amdk8_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1,
 };
 

Modified: trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -66,27 +66,6 @@
 	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, 
 };
 
-
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -187,12 +166,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -356,25 +356,6 @@
 	.device = PCI_DEVICE_ID_NS_GX2,
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -468,12 +449,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -74,8 +74,6 @@
 #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
 #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
 extern void graphics_init(void);
 extern void cpubug(void);
 extern void chipsetinit(void);
@@ -382,24 +380,6 @@
 	.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
 };
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -470,14 +450,6 @@
 	pci_set_method(dev);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
-
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources = pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base	= 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->base	= 0x80000000ULL;
-	resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -53,13 +36,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = pci_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base	= 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->base	= 0x80000000ULL;
-	resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -53,13 +36,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = pci_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include <bitops.h>
 #include "chip.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-        unsigned reg;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base = 0x400; //yhlu
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -155,12 +138,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -28,30 +28,6 @@
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
 	struct resource **best_p = gp;
@@ -90,7 +66,7 @@
 
 #if 1
 	printk_debug("PCI mem marker = %x\n", pci_tolm);
-#endif	
+#endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
 		pci_tolm = 0xe0000000;
@@ -122,7 +98,7 @@
 			remapbasek   = 0x3ff << 16;
 			remaplimitk  = 0 << 16;
 			remapoffsetk = 0 << 16;
-		} 
+		}
 		else {
 			/* The PCI memory hole overlaps memory
 			 * setup the remap window.
@@ -165,7 +141,7 @@
 			ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 		}
 		if (remaplimitk >= remapbasek) {
-			ram_resource(dev, 6, remapbasek, 
+			ram_resource(dev, 6, remapbasek,
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
@@ -178,13 +154,10 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static u32 e7520_domain_scan_bus(device_t dev, u32 max)
 {
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
-	if (max > max_bus) {
-		max_bus = max;
-	}
-	return max;
+	max_bus = pci_domain_scan_bus(dev, max);
+	return max_bus;
 }
 
 static struct device_operations pci_domain_ops = {
@@ -192,7 +165,7 @@
 	.set_resources    = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = e7520_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 };
 

Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -28,30 +28,6 @@
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
 	struct resource **best_p = gp;
@@ -90,7 +66,7 @@
 
 #if 1
 	printk_debug("PCI mem marker = %x\n", pci_tolm);
-#endif	
+#endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
 		pci_tolm = 0xe0000000;
@@ -122,7 +98,7 @@
 			remapbasek   = 0x3ff << 16;
 			remaplimitk  = 0 << 16;
 			remapoffsetk = 0 << 16;
-		} 
+		}
 		else {
 			/* The PCI memory hole overlaps memory
 			 * setup the remap window.
@@ -160,12 +136,12 @@
 
 		/* Report the memory regions */
     		ram_resource(dev, 3,   0, 640);
-		ram_resource(dev, 4, 768, tolmk - 768);
+		ram_resource(dev, 4, 768, (tolmk - 768));
 		if (tomk > 4*1024*1024) {
 			ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 		}
 		if (remaplimitk >= remapbasek) {
-			ram_resource(dev, 6, remapbasek, 
+			ram_resource(dev, 6, remapbasek,
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
@@ -178,13 +154,10 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static u32 e7525_domain_scan_bus(device_t dev, u32 max)
 {
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
-	if (max > max_bus) {
-		max_bus = max;
-	}
-	return max;
+	max_bus = pci_domain_scan_bus(dev, max);
+	return max_bus;
 }
 
 static struct device_operations pci_domain_ops = {
@@ -192,7 +165,7 @@
 	.set_resources    = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = e7525_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 };
 

Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -49,30 +49,6 @@
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
 	struct resource **best_p = gp;
@@ -199,13 +175,10 @@
 	assign_resources(&dev->link[0]);
 }
 
-static u32 pci_domain_scan_bus(device_t dev, u32 max)
+static u32 i3100_domain_scan_bus(device_t dev, u32 max)
 {
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
-	if (max > max_bus) {
-		max_bus = max;
-	}
-	return max;
+	max_bus = pci_domain_scan_bus(dev, max);
+	return max_bus;
 }
 
 static struct device_operations pci_domain_ops = {
@@ -213,7 +186,7 @@
 	.set_resources    = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = i3100_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 };
 

Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -33,24 +33,6 @@
 	.device = 0x7190,
 };
 
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -95,7 +77,7 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void i440bx_domain_set_resources(device_t dev)
 {
 	device_t mc_dev;
 	uint32_t pci_tolm;
@@ -140,15 +122,9 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources		= pci_domain_read_resources,
-	.set_resources		= pci_domain_set_resources,
+	.set_resources		= i440bx_domain_set_resources,
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,

Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -52,27 +52,6 @@
 	.device	= 0x7120,
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-	unsigned reg;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -181,12 +160,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources		= pci_domain_read_resources,
 	.set_resources		= pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -51,25 +51,6 @@
 	.device = 0x3575,
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide I/O space constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -158,12 +139,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources		= pci_domain_read_resources,
 	.set_resources		= pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -31,24 +31,6 @@
 #include <cpu/x86/cache.h>
 #include "chip.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-        unsigned reg;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -156,12 +138,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -10,23 +10,6 @@
 #include <bitops.h>
 #include "chip.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -123,12 +106,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -43,31 +43,6 @@
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base = 0;
-	resource->size = 0;
-	resource->align = 0;
-	resource->gran = 0;
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->base = 0;
-	resource->size = 0;
-	resource->align = 0;
-	resource->gran = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
 	struct resource **best_p = gp;
@@ -184,15 +159,10 @@
 #endif
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
 	/* TODO We could determine how many PCIe busses we need in
 	 * the bar. For now that number is hardcoded to a max of 64.
+	 * See e7525/northbridge.c for an example.
 	 */
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources   = pci_domain_read_resources,
 	.set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -16,7 +16,7 @@
  * be large enough to hold all expected resources for all PCI
  * devices.
  */
-static void pci_domain_read_resources(device_t dev)
+static void mpc107_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 
@@ -101,15 +101,8 @@
 	assign_resources(&dev->link[0]);
 }
 
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
-	.read_resources	  = pci_domain_read_resources,
+	.read_resources	  = mpc107_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init		  = 0,

Modified: trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -101,11 +101,11 @@
 	.device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL,
 };
 
-static void pci_domain_read_resources(device_t dev)
+static void cn400_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 
-	printk_spew("Entering cn400 pci_domain_read_resources.\n");
+	printk_spew("Entering %s.\n", __func__);
 
 	/* Initialize the system wide I/O space constraints. */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
@@ -119,7 +119,7 @@
 	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 	    IORESOURCE_ASSIGNED;
 
-	printk_spew("Leaving cn400 pci_domain_read_resources.\n");
+	printk_spew("Leaving %s.\n", __func__);
 }
 
 static void ram_resource(device_t dev, unsigned long index,
@@ -173,14 +173,14 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void cn400_domain_set_resources(device_t dev)
 {
 	/* The order is important to find the correct RAM size. */
 	static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
 	device_t mc_dev;
 	u32 pci_tolm;
 
-	printk_spew("Entering cn400 pci_domain_set_resources.\n");
+	printk_spew("Entering %s.\n", __func__);
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -226,23 +226,23 @@
 	}
 	assign_resources(&dev->link[0]);
 	
-	printk_spew("Leaving cn400 pci_domain_set_resources.\n");
+	printk_spew("Leaving %s.\n", __func__);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
 {
-	printk_debug("Entering cn400 pci_domain_scan_bus.\n");
+	printk_debug("Entering %s.\n", __func__);
 
 	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 	return max;
 }
 
 static const struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
+	.read_resources   = cn400_domain_read_resources,
+	.set_resources    = cn400_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = cn400_domain_scan_bus,
 };
 
 static void cpu_bus_init(device_t dev)

Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -97,27 +97,6 @@
 	.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
 };
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	printk_spew("Entering cn700 pci_domain_read_resources.\n");
-
-	/* Initialize the system wide I/O space constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	printk_spew("Leaving cn700 pci_domain_read_resources.\n");
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -223,14 +202,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_debug("Entering cn700 pci_domain_scan_bus.\n");
-
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static const struct device_operations pci_domain_ops = {
 	.read_resources   = pci_domain_read_resources,
 	.set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -329,7 +329,7 @@
 
 void cx700_read_resources(device_t dev)
 {
-	struct resource *resource;
+	struct resource *res;
 
 	/* Make sure we call our childrens set/enable functions - these
 	 * are not called unless this device has a resource to set.
@@ -337,11 +337,16 @@
 
 	pci_dev_read_resources(dev);
 
-	resource = new_resource(dev, 1);
-	resource->flags |=
-	    IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED;
-	resource->size = 2;
-	resource->base = 0x2e;
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 void cx700_set_resources(device_t dev)

Modified: trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -32,21 +32,6 @@
 #include "chip.h"
 #include "northbridge.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -146,12 +131,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = pci_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -45,23 +45,6 @@
 	.device = 0x0601, /* 0x8601 is the AGP bridge? */
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -160,12 +143,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -190,30 +190,6 @@
 	.device = 0x3122,
 };
 
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-	printk_spew("Entering vt8623 pci_domain_read_resources.\n");
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		IORESOURCE_ASSIGNED;
-
-	printk_spew("Leaving vt8623 pci_domain_read_resources.\n");
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -313,14 +289,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_spew("Entering vt8623 pci_domain_scan_bus.\n");
-
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -69,27 +69,6 @@
 	.device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL,
 };
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	printk_spew("Entering vx800 pci_domain_read_resources.\n");
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	printk_spew("Leaving vx800 pci_domain_read_resources.\n");
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -195,14 +174,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_debug("Entering vx800 pci_domain_scan_bus.\n");
-
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static const struct device_operations pci_domain_ops = {
 	.read_resources = pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -162,15 +162,26 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-	
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void amd8111_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -364,9 +364,6 @@
 		/* set the memory range */
 		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		res->flags |= IORESOURCE_STORED;
-		compute_allocate_resource(&dev->link[0], res,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 		base = res->base;
 		end  = resource_end(res);
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);

Modified: trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -350,9 +350,6 @@
 		/* set the memory range */
 		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		res->flags |= IORESOURCE_STORED;
-		compute_allocate_resource(&dev->link[0], res,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 		base = res->base;
 		end  = resource_end(res);
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -25,6 +25,24 @@
 #include <device/pci_ids.h>
 #include "cs5530.h"
 
+static void cs5530_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static void isa_init(struct device *dev)
 {
 	uint8_t reg8;
@@ -45,7 +63,7 @@
 }
 
 static struct device_operations isa_ops = {
-	.read_resources		= pci_dev_read_resources,
+	.read_resources		= cs5530_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= cs5530_pci_dev_enable_resources,
 	.init			= isa_init,

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -69,6 +69,24 @@
 	printk_spew("%s: dev is %p\n", __func__, dev);
 }
 
+static void cs5535_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static void cs5535_pci_dev_enable_resources(device_t dev)
 {
 	printk_spew("cs5535.c: %s()\n", __func__);
@@ -77,7 +95,7 @@
 }
 
 static struct device_operations southbridge_ops = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources   = cs5535_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = cs5535_pci_dev_enable_resources,
 	.init             = southbridge_init,

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -607,6 +607,25 @@
 	}
 }
 
+static void cs5536_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static void southbridge_enable(struct device *dev)
 {
 	printk_err("cs5536: %s: dev is %p\n", __func__, dev);
@@ -621,7 +640,7 @@
 }
 
 static struct device_operations southbridge_ops = {
-	.read_resources = pci_dev_read_resources,
+	.read_resources = cs5536_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = cs5536_pci_dev_enable_resources,
 	.init = southbridge_init,

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -70,15 +70,24 @@
 
 	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
 	compact_resources(dev);
 }
 
@@ -111,7 +120,7 @@
 		for (child = dev->link[link].children; child;
 		     child = child->sibling) {
 			enable_resources(child);
-			if (child->have_resources
+			if (child->enabled
 			    && (child->path.type == DEVICE_PATH_PNP)) {
 				for (i = 0; i < child->resources; i++) {
 					struct resource *res;

Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -29,18 +29,27 @@
 static void bcm5785_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
-	unsigned long index;
 
 	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev); 
-	
-        /* Add an extra subtractive resource for both memory and I/O */
-        res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-        res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-        
-        res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	pci_dev_read_resources(dev);
 
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 /**     
@@ -69,7 +78,7 @@
                 device_t child;
                 for (child = dev->link[link].children; child; child = child->sibling) {
                         enable_resources(child);
-			if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 				for(i=0;i<child->resources;i++) {
 					struct resource *res;
 			                unsigned long base, end; // don't need long long

Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -51,7 +51,6 @@
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); 		
-	
 	/* Get Resource for SMBUS */	
 	pci_get_resource(dev, 0x90);	
 

Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -361,12 +361,23 @@
 	/* Add the GPIO BAR */
 	res = pci_get_resource(dev, GPIO_BAR);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void esb6300_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -399,13 +399,24 @@
 	/* Add the GPIO BAR */
 	res = pci_get_resource(dev, GPIO_BAR);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
 	/* Add resource for RCBA */
 	res = new_resource(dev, RCBA);
 	res->size = 0x4000;

Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -55,8 +55,31 @@
 	isa_dma_init();
 }
 
-static const struct device_operations isa_ops = {
-	.read_resources		= pci_dev_read_resources,
+static void sb_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 2);
+	res->base = 0xff800000UL;
+	res->size = 0x00800000UL; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+const struct device_operations isa_ops = {
+	.read_resources		= sb_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= isa_init,

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -207,15 +207,26 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void i82801ca_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -182,15 +182,26 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void i82801dbm_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -334,7 +334,7 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
 	/* Add the ACPI BAR */
@@ -343,12 +343,23 @@
 	/* Add the GPIO BAR */
 	res = pci_get_resource(dev, GPIO_BAR);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void i82801er_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -419,12 +419,21 @@
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void i82801gx_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -340,12 +340,21 @@
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void i82801xx_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -275,12 +275,21 @@
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 /**
@@ -308,7 +317,7 @@
 		device_t child;
 		for (child = dev->link[link].children; child; child = child->sibling) {
 			enable_resources(child);
-			if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+			if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 				for (i = 0; i < child->resources; i++) {
 					struct resource *res;
 					unsigned long base, end;	// don't need long long

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -5,6 +5,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/resource.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -13,10 +14,8 @@
 static void pci_init(struct device *dev)
 {
 	uint32_t dword;
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
-	struct resource *mem1, *mem2;
-#endif
+	struct resource *mem, *pref;
 
 	dword = pci_read_config32(dev, 0x04);
 	dword |= (1 << 8);	/* System error enable */
@@ -36,7 +35,6 @@
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
 	while (pci_domain_dev) {
 		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
@@ -47,21 +45,19 @@
 	if (!pci_domain_dev)
 		return;		/* Impossible */
 
-	mem1 = find_resource(pci_domain_dev, 1);	// prefmem, it could be 64bit
-	mem2 = find_resource(pci_domain_dev, 2);	// mem
-	if (mem1->base > mem2->base) {
-		dword = mem2->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
+	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
+	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
+
+	if (!mem)
+		return;		/* Impossible */
+
+	if (!pref || pref->base > mem->base) {
+		dword = mem->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
 	} else {
-		dword = mem1->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n",
-			     mem1->base);
+		dword = pref->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
 	}
-#else
-	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n",
-		     dev_root.resource[1].base);
-#endif
 
 	printk_debug("[0x50] <-- 0x%08x\n", dword);
 	pci_write_config32(dev, 0x50, dword);	/* TOM */

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -248,16 +248,27 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
+	/* Get the normal PCI resources of this device. */
+	/* We got one for APIC, or one more for TRAP. */
+	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 /**
@@ -265,7 +276,7 @@
  *
  * @param dev the device whos children's resources are to be enabled
  *
- * This function is call by the global enable_resources() indirectly via the
+ * This function is called by the global enable_resources() indirectly via the
  * device_operation::enable_resources() method of devices.
  *
  * Indirect mutual recursion:
@@ -286,7 +297,7 @@
 		device_t child;
 		for (child = dev->link[link].children; child; child = child->sibling) {
 			enable_resources(child);
-			if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 				for(i=0;i<child->resources;i++) {
 					struct resource *res;
 					unsigned long base, end; // don't need long long

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -23,6 +23,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/resource.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -33,10 +34,8 @@
 
 	uint32_t dword;
 	uint16_t word;
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
-	struct resource *mem1, *mem2;
-#endif
+	struct resource *mem, *pref;
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
@@ -58,30 +57,32 @@
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
-	while(pci_domain_dev) {
-		if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;
+	while (pci_domain_dev) {
+		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
+			break;
 		pci_domain_dev = pci_domain_dev->bus->dev;
 	}
 
-	if(!pci_domain_dev) return; // impossiable
-	mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
-	mem2 = find_resource(pci_domain_dev, 2); // mem
-	if(mem1->base > mem2->base) {
-		dword = mem2->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
+	if (!pci_domain_dev)
+		return;		/* Impossible */
+
+	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
+	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
+
+	if (!mem)
+		return;		/* Impossible */
+
+	if (!pref || pref->base > mem->base) {
+		dword = mem->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
 	} else {
-		dword = mem1->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
+		dword = pref->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
 	}
-#else
-	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
-#endif
+
 	printk_debug("[0x50] <-- 0x%08x\n", dword);
-	pci_write_config32(dev, 0x50, dword); //TOM
-
+	pci_write_config32(dev, 0x50, dword);	/* TOM */
 }
 
 static struct pci_operations lops_pci = {

Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -172,7 +172,6 @@
 		resource = find_resource(dev,1);
 		if( !(resource->flags & IORESOURCE_STORED) ){
 			resource->flags |= IORESOURCE_STORED ;
-			compute_allocate_resource(&dev->link[0],resource,resource->flags,resource->flags);
 			printk_debug("%s 1 ==> %x\n",dev_path(dev),resource->base); 
 			cf_base = resource->base;
 		}

Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -239,13 +239,23 @@
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 /**
@@ -274,7 +284,7 @@
 		device_t child;
 		for (child = dev->link[link].children; child; child = child->sibling) {
 			enable_resources(child);
-			if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 				for(i=0;i<child->resources;i++) {
 					struct resource *res;
 					unsigned long base, end; // don't need long long

Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -131,6 +131,24 @@
 	rtc_init(0);
 }
 
+void vt8231_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static void southbridge_init(struct device *dev)
 {
 	vt8231_init(dev);
@@ -138,7 +156,7 @@
 }
 
 static struct device_operations vt8231_lpc_ops = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources   = vt8231_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init		  = &southbridge_init,

Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -219,15 +219,22 @@
    device has a resource to set - so set a dummy one */
 void vt8235_read_resources(device_t dev)
 {
+	struct resource *res;
 
-	struct resource *resource;
 	pci_dev_read_resources(dev);
-	resource = new_resource(dev, 1);
-	resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED;
-	resource->size = 2;
-	resource->base = 0x2e;
 
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
+
 void vt8235_set_resources(device_t dev)
 {
 	struct resource *resource;

Modified: trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c	2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c	2009-07-02 18:56:24 UTC (rev 4394)
@@ -188,8 +188,26 @@
 	enable_childrens_resources(dev);
 }
 
+static void w83c553_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static struct device_operations w83c553_ops  = {
-        .read_resources   = pci_dev_read_resources,
+        .read_resources   = w83c553_read_resources,
         .set_resources    = pci_dev_set_resources,
         .enable_resources = w83c553_enable_resources,
         .init             = w83c553_init,




From andi.mundt at web.de  Thu Jul  2 20:58:42 2009
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Thu, 2 Jul 2009 20:58:42 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702171605.GA5514@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
	<20090702171605.GA5514@flashgordon>
Message-ID: <20090702185842.GA5338@flashgordon>

On Thursday 02 July 2009 20:22:50 Harald Gutmann wrote:
> On Thursday 02 July 2009 17:56:30 Andreas B. Mundt wrote:
> > Hi everybody,
> >
> > just noticed that my parallel port printer unfortunately only works
> >
> > with the prop. BIOS:
> > >From dmesg:
> >
> > coreboot:
> > [   54.388956] lp: driver loaded but no devices found
> > [   54.409159] ppdev: user-space parallel port driver
> >
> > prop. BIOS:
> > [  179.494713] lp0: using parport0 (interrupt-driven).
> > [  179.516281] ppdev: user-space parallel port driver
>
> With the attached patch I get the following output on modprobe parport:
> [   28.848297] lp0: using parport0 (polling).
> [   28.858860] ppdev: user-space parallel port driver
>
> The patch also turns on the floppy device, but I've none here to verify if
> it will work. It would be great if you can test if floppy works, so that we
> could mark the last two "not-working" parts as OK in the wiki, if it the
> floppy does its job
Sry, I forgot to sign it off:
Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>

Patch tested succesfully with parallel-port printer.

Acked-by: Andreas B. Mundt


Thanks,

	Andi



From mylesgw at gmail.com  Thu Jul  2 20:58:57 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Jul 2009 12:58:57 -0600
Subject: [coreboot] [PATCH] v3 Resource allocator to v2
In-Reply-To: <13426df10905271801k60c6c1c8l71ea74a846d91a20@mail.gmail.com>
References: <C9163063016E42B78E446D11A3429A0E@chimp>
	<2831fecf0905271525mb32bef9s7ded9f8d813f22e@mail.gmail.com>
	<13426df10905271801k60c6c1c8l71ea74a846d91a20@mail.gmail.com>
Message-ID: <2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>

On Wed, May 27, 2009 at 7:01 PM, ron minnich <rminnich at gmail.com> wrote:

>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>

Rev 4394.

Thanks,
Myles
-------------- next part --------------
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From svn at coreboot.org  Thu Jul  2 21:02:34 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Jul 2009 21:02:34 +0200
Subject: [coreboot] [v2] r4395 - in trunk/coreboot-v2/src: devices
	northbridge/amd/amdk8
Message-ID: <mailman.3514.1355071590.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-07-02 21:02:33 +0200 (Thu, 02 Jul 2009)
New Revision: 4395

Modified:
   trunk/coreboot-v2/src/devices/device.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
Log:
Update the k8 code for the v3 resource allocator.
The major change is that the K8 registers don't get touched until the end of
resource allocation.

Fam10 code could be updated the same way.

Move VGA code before resource allocation but after device enumeration.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/coreboot-v2/src/devices/device.c
===================================================================
--- trunk/coreboot-v2/src/devices/device.c	2009-07-02 18:56:24 UTC (rev 4394)
+++ trunk/coreboot-v2/src/devices/device.c	2009-07-02 19:02:33 UTC (rev 4395)
@@ -663,9 +663,9 @@
 
 #if CONFIG_CONSOLE_VGA == 1
 device_t vga_pri = 0;
-static void allocate_vga_resource(void)
+static void set_vga_bridge_bits(void)
 {
-#warning "FIXME modify allocate_vga_resource so it is less pci centric!"
+#warning "FIXME modify set_vga_bridge so it is less pci centric!"
 #warning "This function knows too much about PCI stuff, it should be just a iterator/visitor."
 
 	/* FIXME: Handle the VGA palette snooping. */
@@ -716,7 +716,7 @@
 
 	if (vga) {
 		/* VGA is first add on card or the only onboard VGA. */
-		printk_debug("Allocating VGA resource %s\n", dev_path(vga));
+		printk_debug("Setting up VGA for %s\n", dev_path(vga));
 		/* All legacy VGA cards have MEM & I/O space registers. */
 		vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		vga_pri = vga;
@@ -921,6 +921,10 @@
 	struct device *child;
 	int i;
 
+#if CONFIG_CONSOLE_VGA == 1
+	set_vga_bridge_bits();
+#endif
+
 	printk_info("Allocating resources...\n");
 
 	root = &dev_root;
@@ -984,12 +988,6 @@
 		}
 	}
 
-#if CONFIG_CONSOLE_VGA == 1
-	/* Allocate the VGA I/O resource. */
-	allocate_vga_resource();
-	print_resource_tree(root, BIOS_DEBUG, "After VGA.");
-#endif
-
 	/* Store the computed resource allocations into device registers ... */
 	printk_info("Setting resources...\n");
 	for (child = root->link[0].children; child; child = child->sibling) {

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-07-02 18:56:24 UTC (rev 4394)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-07-02 19:02:33 UTC (rev 4395)
@@ -36,56 +36,38 @@
 
 struct amdk8_sysconf_t sysconf;
 
-#define FX_DEVS 8
-static device_t __f0_dev[FX_DEVS];
-static device_t __f1_dev[FX_DEVS];
+#define MAX_FX_DEVS 8
+static device_t __f0_dev[MAX_FX_DEVS];
+static device_t __f1_dev[MAX_FX_DEVS];
+static unsigned fx_devs=0;
 
-#if 0
-static void debug_fx_devs(void)
-{
-	int i;
-	for(i = 0; i < FX_DEVS; i++) {
-		device_t dev;
-		dev = __f0_dev[i];
-		if (dev) {
-			printk_debug("__f0_dev[%d]: %s bus: %p\n",
-				i, dev_path(dev), dev->bus);
-		}
-		dev = __f1_dev[i];
-		if (dev) {
-			printk_debug("__f1_dev[%d]: %s bus: %p\n",
-				i, dev_path(dev), dev->bus);
-		}
-	}
-}
-#endif
-
 static void get_fx_devs(void)
 {
 	int i;
-	if (__f1_dev[0]) {
-		return;
-	}
-	for(i = 0; i < FX_DEVS; i++) {
+	for(i = 0; i < MAX_FX_DEVS; i++) {
 		__f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
 		__f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
+		if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+			fx_devs = i+1;
 	}
-	if (!__f1_dev[0]) {
-		die("Cannot find 0:0x18.1\n");
+	if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+		die("Cannot find 0:0x18.[0|1]\n");
 	}
 }
 
 static uint32_t f1_read_config32(unsigned reg)
 {
-	get_fx_devs();
+	if ( fx_devs == 0)
+		get_fx_devs();
 	return pci_read_config32(__f1_dev[0], reg);
 }
 
 static void f1_write_config32(unsigned reg, uint32_t value)
 {
 	int i;
-	get_fx_devs();
-	for(i = 0; i < FX_DEVS; i++) {
+	if ( fx_devs == 0)
+		get_fx_devs();
+	for(i = 0; i < fx_devs; i++) {
 		device_t dev;
 		dev = __f1_dev[i];
 		if (dev && dev->enabled) {
@@ -291,7 +273,7 @@
 	unsigned nodeid, link=0;
 	int result;
 	res = 0;
-	for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
+	for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
 		device_t dev;
 		dev = __f0_dev[nodeid];
 		if (!dev)
@@ -313,13 +295,14 @@
 	return result;
 }
 
-static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
+			       unsigned min, unsigned max)
 {
-	struct resource *resource;
+	unsigned resource;
 	unsigned free_reg, reg;
 	resource = 0;
 	free_reg = 0;
-	for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+	for(reg = min; reg <= max; reg += 0x8) {
 		int result;
 		result = reg_useable(reg, dev, nodeid, link);
 		if (result == 1) {
@@ -331,48 +314,31 @@
 			free_reg = reg;
 		}
 	}
-	if (reg > 0xd8) {
+	if (reg > max) {
 		reg = free_reg;
 	}
 	if (reg > 0) {
-		resource = new_resource(dev, IOINDEX(0x100 + reg, link));
+		resource = IOINDEX(0x100 + reg, link);
 	}
 	return resource;
 }
 
-static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
+static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
 {
-	struct resource *resource;
-	unsigned free_reg, reg;
-	resource = 0;
-	free_reg = 0;
-	for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
-		int result;
-		result = reg_useable(reg, dev, nodeid, link);
-		if (result == 1) {
-			/* I have been allocated this one */
-			break;
-		}
-		else if (result > 1) {
-			/* I have a free register pair */
-			free_reg = reg;
-		}
-	}
-	if (reg > 0xb8) {
-		reg = free_reg;
-	}
-	if (reg > 0) {
-		resource = new_resource(dev, IOINDEX(0x100 + reg, link));
-	}
-	return resource;
+	return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
 }
 
+static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
+{
+	return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
+}
+
 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
 {
 	struct resource *resource;
 
 	/* Initialize the io space constraints on the current bus */
-	resource =  amdk8_find_iopair(dev, nodeid, link);
+	resource = new_resource(dev, IOINDEX(0, link));
 	if (resource) {
 		resource->base  = 0;
 		resource->size  = 0;
@@ -383,7 +349,7 @@
 	}
 
 	/* Initialize the prefetchable memory constraints on the current bus */
-	resource = amdk8_find_mempair(dev, nodeid, link);
+	resource = new_resource(dev, IOINDEX(2, link));
 	if (resource) {
 		resource->base  = 0;
 		resource->size  = 0;
@@ -397,7 +363,7 @@
 	}
 
 	/* Initialize the memory constraints on the current bus */
-	resource = amdk8_find_mempair(dev, nodeid, link);
+	resource = new_resource(dev, IOINDEX(1, link));
 	if (resource) {
 		resource->base  = 0;
 		resource->size  = 0;
@@ -408,6 +374,8 @@
 	}
 }
 
+static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
+
 static void amdk8_read_resources(device_t dev)
 {
 	unsigned nodeid, link;
@@ -417,6 +385,8 @@
 			amdk8_link_read_bases(dev, nodeid, link);
 		}
 	}
+
+	amdk8_create_vga_resource(dev, nodeid);
 }
 
 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
@@ -518,8 +488,6 @@
 {
 	struct resource *resource;
 	unsigned link;
-	uint32_t base, limit;
-	unsigned reg;
 
 	/* find out which link the VGA card is connected,
 	 * we only deal with the 'first' vga card */
@@ -543,31 +511,17 @@
 
 	printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 
-	/* allocate a temp resrouce for legacy VGA buffer */
-	resource = amdk8_find_mempair(dev, nodeid, link);
+	/* allocate a temp resource for the legacy VGA buffer */
+	resource = new_resource(dev, IOINDEX(4, link));
 	if(!resource){
-		printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
+		printk_debug("VGA: %s out of resources.\n", dev_path(dev));
 		return;
 	}
 	resource->base = 0xa0000;
 	resource->size = 0x20000;
-
-	/* write the resource to the hardware */
-	reg  = resource->index & 0xfc;
-	base  = f1_read_config32(reg);
-	limit = f1_read_config32(reg + 0x4);
-	base  &= 0x000000f0;
-	base  |= (resource->base >> 8) & 0xffffff00;
-	base  |= 3;
-	limit &= 0x00000048;
-	limit |= (resource_end(resource) >> 8) & 0xffffff00;
-	limit |= (resource->index & 3) << 4;
-	limit |= (nodeid & 7);
-	f1_write_config32(reg + 0x4, limit);
-	f1_write_config32(reg, base);
-
-	/* release the temp resource */
-	resource->flags = 0;
+	resource->limit = 0xffffffff;
+	resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
+			  IORESOURCE_ASSIGNED;
 }
 
 static void amdk8_set_resources(device_t dev)
@@ -578,13 +532,36 @@
 	/* Find the nodeid */
 	nodeid = amdk8_nodeid(dev);
 
-	amdk8_create_vga_resource(dev, nodeid);
-
 	/* Set each resource we have found */
 	for(i = 0; i < dev->resources; i++) {
-		amdk8_set_resource(dev, &dev->resource[i], nodeid);
+		struct resource *res = &dev->resource[i];
+		struct resource *old = NULL;
+		unsigned index;
+
+		if (res->size == 0) /* No need to allocate registers. */
+			continue;
+
+		if (res->flags & IORESOURCE_IO)
+			index = amdk8_find_iopair(dev, nodeid,
+						  IOINDEX_LINK(res->index));
+		else
+			index = amdk8_find_mempair(dev, nodeid,
+						   IOINDEX_LINK(res->index));
+
+		old = probe_resource(dev, index);
+		if (old) {
+			res->index = old->index;
+			old->index = 0;
+			old->flags = 0;
+		}
+		else
+			res->index = index;
+
+		amdk8_set_resource(dev, res, nodeid);
 	}
 
+	compact_resources(dev);
+
 	for(link = 0; link < dev->links; link++) {
 		struct bus *bus;
 		bus = &dev->link[link];
@@ -634,7 +611,6 @@
 
 static void amdk8_domain_read_resources(device_t dev)
 {
-	struct resource *resource;
 	unsigned reg;
 
 	/* Find the already assigned resource pairs */
@@ -652,10 +628,12 @@
 			reg_dev = __f0_dev[nodeid];
 			if (reg_dev) {
 				/* Reserve the resource  */
-				struct resource *reg_resource;
-				reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
-				if (reg_resource) {
-					reg_resource->flags = 1;
+				struct resource *res;
+				res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
+				if (res) {
+					res->base = base;
+					res->limit = limit;
+					res->flags = 1;
 				}
 			}
 		}
@@ -691,7 +669,8 @@
 	struct resource **best_p = gp;
 	struct resource *best;
 	best = *best_p;
-	if (!best || (best->base > new->base)) {
+	/* Skip VGA. */
+	if (!best || (best->base > new->base && new->base > 0xa0000)) {
 		best = new;
 	}
 	*best_p = best;
@@ -725,15 +704,14 @@
 		mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
 		mem_hole.node_id = -1;
 
-		for (i = 0; i < FX_DEVS; i++) {
+		for (i = 0; i < fx_devs; i++) {
 			uint32_t base;
 			uint32_t hole;
 			base  = f1_read_config32(0x40 + (i << 3));
 			if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 				continue;
 			}
-			if (!__f1_dev[i])
-				continue;
+
 			hole = pci_read_config32(__f1_dev[i], 0xf0);
 			if(hole & 1) { // we find the hole
 				mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
@@ -769,9 +747,10 @@
 		return mem_hole;
 
 }
-static void disable_hoist_memory(unsigned long hole_startk, int i)
+
+static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 {
-	int ii;
+	int i;
 	device_t dev;
 	uint32_t base, limit;
 	uint32_t hoist;
@@ -787,33 +766,35 @@
 
 	hole_sizek = (4*1024*1024) - hole_startk;
 
-	for(ii=7;ii>i;ii--) {
+	for(i=7;i>node_id;i--) {
 
-		base  = f1_read_config32(0x40 + (ii << 3));
+		base  = f1_read_config32(0x40 + (i << 3));
 		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 			continue;
 		}
-		limit = f1_read_config32(0x44 + (ii << 3));
-		f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
-		f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
+		limit = f1_read_config32(0x44 + (i << 3));
+		f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
+		f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 	}
-	limit = f1_read_config32(0x44 + (i << 3));
-	f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
-	dev = __f1_dev[i];
-	if (dev) {
-		hoist = pci_read_config32(dev, 0xf0);
-		if(hoist & 1) {
-			pci_write_config32(dev, 0xf0, 0);
-		} else {
-			base = pci_read_config32(dev, 0x40 + (i << 3));
-			f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
-		}
+	limit = f1_read_config32(0x44 + (node_id << 3));
+	f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
+	dev = __f1_dev[node_id];
+	if (dev == NULL) {
+		printk_err("%s: node %x is NULL!\n", __func__, node_id);
+		return;
 	}
+	hoist = pci_read_config32(dev, 0xf0);
+	if(hoist & 1)
+		pci_write_config32(dev, 0xf0, 0);
+	else {
+		base = pci_read_config32(dev, 0x40 + (node_id << 3));
+		f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
+	}
 }
 
-static uint32_t hoist_memory(unsigned long hole_startk, int i)
+static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
 {
-	int ii;
+	int i;
 	uint32_t carry_over;
 	device_t dev;
 	uint32_t base, limit;
@@ -822,27 +803,27 @@
 
 	carry_over = (4*1024*1024) - hole_startk;
 
-	for(ii=7;ii>i;ii--) {
+	for(i=7;i>node_id;i--) {
 
-		base  = f1_read_config32(0x40 + (ii << 3));
+		base  = f1_read_config32(0x40 + (i << 3));
 		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 			continue;
 		}
-		limit = f1_read_config32(0x44 + (ii << 3));
-		f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
-		f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
+		limit = f1_read_config32(0x44 + (i << 3));
+		f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
+		f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
 	}
-	limit = f1_read_config32(0x44 + (i << 3));
-	f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
-	dev = __f1_dev[i];
-	base  = pci_read_config32(dev, 0x40 + (i << 3));
+	limit = f1_read_config32(0x44 + (node_id << 3));
+	f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
+	dev = __f1_dev[node_id];
+	base  = pci_read_config32(dev, 0x40 + (node_id << 3));
 	basek  = (base & 0xffff0000) >> 2;
 	if(basek == hole_startk) {
 		//don't need set memhole here, because hole off set will be 0, overflow
 		//so need to change base reg instead, new basek will be 4*1024*1024
 		base &= 0x0000ffff;
 		base |= (4*1024*1024)<<2;
-		f1_write_config32(0x40 + (i<<3), base);
+		f1_write_config32(0x40 + (node_id<<3), base);
 	}
 	else if (dev)
 	{
@@ -980,7 +961,7 @@
 		#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 			//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
 			uint32_t basek_pri;
-			for (i = 0; i < FX_DEVS; i++) {
+			for (i = 0; i < fx_devs; i++) {
 				uint32_t base;
 				uint32_t basek;
 				base  = f1_read_config32(0x40 + (i << 3));
@@ -1005,7 +986,7 @@
 #endif
 
 	idx = 0x10;
-	for(i = 0; i < FX_DEVS; i++) {
+	for(i = 0; i < fx_devs; i++) {
 		uint32_t base, limit;
 		unsigned basek, limitk, sizek;
 		base  = f1_read_config32(0x40 + (i << 3));
@@ -1043,7 +1024,7 @@
 					/* Leave some space for ACPI, PIRQ and MP tables */
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk_debug(" split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1100,7 +1081,7 @@
 	 * Including enabling relaxed ordering if it is safe.
 	 */
 	get_fx_devs();
-	for(i = 0; i < FX_DEVS; i++) {
+	for(i = 0; i < fx_devs; i++) {
 		device_t f0_dev;
 		f0_dev = __f0_dev[i];
 		if (f0_dev && f0_dev->enabled) {




From mylesgw at gmail.com  Thu Jul  2 21:03:19 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Jul 2009 13:03:19 -0600
Subject: [coreboot] K8 resource allocation cleanup
In-Reply-To: <13426df10906190817md416ecerd7f1ae70dbf737f5@mail.gmail.com>
References: <2831fecf0906182048n4d864ad3q3e154e68435c52ac@mail.gmail.com>
	<13426df10906190817md416ecerd7f1ae70dbf737f5@mail.gmail.com>
Message-ID: <2831fecf0907021203t2302d3e8lc98d74bce7b643fa@mail.gmail.com>

On Fri, Jun 19, 2009 at 9:17 AM, ron minnich <rminnich at gmail.com> wrote:

> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
Rev 4395.

Thanks,
Myles
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From svn at coreboot.org  Thu Jul  2 21:06:01 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Jul 2009 21:06:01 +0200
Subject: [coreboot] [v2] r4396 -
	trunk/coreboot-v2/src/mainboard/gigabyte/m57sli
Message-ID: <mailman.3515.1355071590.16123.coreboot@coreboot.org>

Author: hargut
Date: 2009-07-02 21:06:01 +0200 (Thu, 02 Jul 2009)
New Revision: 4396

Modified:
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
Log:
ChangeLog:

Turn on Parallel Port and Floppy in Config.lb

Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt at web.de>


Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-07-02 19:02:33 UTC (rev 4395)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-07-02 19:06:01 UTC (rev 4396)
@@ -196,7 +196,7 @@
                 			device pci 1.0 on # LPC
 						chip superio/ite/it8716f
 							# Floppy and any LDN
-							device pnp 2e.0 off
+							device pnp 2e.0 on
                 	               			# Watchdog from CLKIN, CLKIN = 24 MHz
                 	                 			irq 0x23 = 0x11 
 							# Serial Flash (SPI only)
@@ -213,7 +213,7 @@
                 	                 			io 0x60 = 0x2f8
                 	                			irq 0x70 = 3
 							end
-                	        			device pnp 2e.3 off #  Parallel Port
+                	        			device pnp 2e.3 on #  Parallel Port
                 	                 			io 0x60 = 0x378
                 	                			irq 0x70 = 7
 							end




From harald.gutmann at gmx.net  Thu Jul  2 21:07:12 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Jul 2009 21:07:12 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702185842.GA5338@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702171605.GA5514@flashgordon>
	<20090702185842.GA5338@flashgordon>
Message-ID: <200907022107.16977.harald.gutmann@gmx.net>

On Thursday 02 July 2009 20:58:42 Andreas B. Mundt wrote:
> On Thursday 02 July 2009 20:22:50 Harald Gutmann wrote:
> > On Thursday 02 July 2009 17:56:30 Andreas B. Mundt wrote:
> > > Hi everybody,
> > >
> > > just noticed that my parallel port printer unfortunately only works
> > >
> > > with the prop. BIOS:
> > > >From dmesg:
> > >
> > > coreboot:
> > > [   54.388956] lp: driver loaded but no devices found
> > > [   54.409159] ppdev: user-space parallel port driver
> > >
> > > prop. BIOS:
> > > [  179.494713] lp0: using parport0 (interrupt-driven).
> > > [  179.516281] ppdev: user-space parallel port driver
> >
> > With the attached patch I get the following output on modprobe parport:
> > [   28.848297] lp0: using parport0 (polling).
> > [   28.858860] ppdev: user-space parallel port driver
> >
> > The patch also turns on the floppy device, but I've none here to verify
> > if it will work. It would be great if you can test if floppy works, so
> > that we could mark the last two "not-working" parts as OK in the wiki, if
> > it the floppy does its job
>
> Sry, I forgot to sign it off:
> Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>
>
> Patch tested succesfully with parallel-port printer.
>
> Acked-by: Andreas B. Mundt
Thanks, r4396.

>
> Thanks,
>
> 	Andi
Regards,
Harald

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From info at coresystems.de  Thu Jul  2 21:19:41 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Jul 2009 21:19:41 +0200
Subject: [coreboot] build service results for r4394
Message-ID: <E1MMRor-0000xa-0P@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4394 to
the coreboot repository. This caused the following 
changes:

Change Log:
Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below)
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4394&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4394&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Thu Jul  2 21:38:38 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 21:38:38 +0200
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
In-Reply-To: <4A4D00D8.2020503@Ivn.cl>
References: <4A4CFC11.4070609@Ivn.cl> <20090702184531.27293.qmail@stuge.se>
	<4A4D00D8.2020503@Ivn.cl>
Message-ID: <20090702193838.7170.qmail@stuge.se>

Ivan Barrera A. wrote:
>> you need another debug output method..
>
> The G1 does not have any serial port :/
> (and havent find any on the mainboard).
>
> I guess the screen output will have problems due to the integrated
> video rom...
> Is there any way to initialize video in this cases ?

I'm afraid video is useless for debugging. It is enabled as the very
last thing coreboot does. You need to be able to follow every step of
coreboot as it runs.

Are there any other usable signals on the board? One bit is enough.

If you have budget for a PromICE it can interpret sequences of reads
from the (emulated) flash chip as a debug write.

Or if you have VHDL skills and a bit of free time, you can add that
functionality to the Artec LPC dongle or your favorite FPGA devkit.


//Peter



From peter at stuge.se  Thu Jul  2 21:40:52 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 21:40:52 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702185842.GA5338@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
	<20090702171605.GA5514@flashgordon>
	<20090702185842.GA5338@flashgordon>
Message-ID: <20090702194053.7744.qmail@stuge.se>

Andreas B. Mundt wrote:
> > With the attached patch I get the following output on modprobe parport:
> > [   28.848297] lp0: using parport0 (polling).

> Patch tested succesfully with parallel-port printer.

Is the port interrupt-driven, or polling, on your system, Andreas?


//Peter



From info at coresystems.de  Thu Jul  2 21:43:38 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Jul 2009 21:43:38 +0200
Subject: [coreboot] build service results for r4395
Message-ID: <E1MMSC2-0001Xr-Ss@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4395 to
the coreboot repository. This caused the following 
changes:

Change Log:
Update the k8 code for the v3 resource allocator.
The major change is that the K8 registers don't get touched until the end of
resource allocation.

Fam10 code could be updated the same way.

Move VGA code before resource allocation but after device enumeration.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4395&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4395&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From andi.mundt at web.de  Thu Jul  2 21:52:31 2009
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Thu, 2 Jul 2009 21:52:31 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
Message-ID: <20090702195231.GA5717@flashgordon>

Hi,

>Is the port interrupt-driven, or polling, on your system, Andreas?
>
>
>//Peter


dmesg:

[   63.699013] pnp: the driver 'parport_pc' has been registered          
[   63.699116] parport0: PC-style at 0x378 (0x778) [PCSPP,TRISTATE]      
[   63.828395] parport0: irq 7 detected                                  
[   63.853986] parport0: Printer, Hewlett-Packard HP LaserJet 5L         
[   63.857440] lp0: using parport0 (polling).                            
[   63.878908] ppdev: user-space parallel port driver                




From harald.gutmann at gmx.net  Thu Jul  2 22:02:03 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 2 Jul 2009 22:02:03 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702194053.7744.qmail@stuge.se>
References: <20090701142139.GA7679@flashgordon>
	<20090702185842.GA5338@flashgordon>
	<20090702194053.7744.qmail@stuge.se>
Message-ID: <200907022202.08049.harald.gutmann@gmx.net>

On Thursday 02 July 2009 21:40:52 Peter Stuge wrote:
> Andreas B. Mundt wrote:
> > > With the attached patch I get the following output on modprobe parport:
> > > [   28.848297] lp0: using parport0 (polling).
> >
> > Patch tested succesfully with parallel-port printer.
>
> Is the port interrupt-driven, or polling, on your system, Andreas?
Here on my system it says also polling, like on Andreas system.
What is the difference between interrupt driven and polling?

On vendor bios it is interrupt-driven.
Is an ACPI part missing to get it interrupt driven?

>
> //Peter
Regards,
Harald
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From info at Ivn.cl  Thu Jul  2 22:03:34 2009
From: info at Ivn.cl (Ivan Barrera A.)
Date: Thu, 02 Jul 2009 16:03:34 -0400
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
In-Reply-To: <20090702193838.7170.qmail@stuge.se>
References: <4A4CFC11.4070609@Ivn.cl>
	<20090702184531.27293.qmail@stuge.se>	<4A4D00D8.2020503@Ivn.cl>
	<20090702193838.7170.qmail@stuge.se>
Message-ID: <4A4D1296.1020604@Ivn.cl>

Peter Stuge escribi?:
> Ivan Barrera A. wrote:
>>> you need another debug output method..
>> The G1 does not have any serial port :/
>> (and havent find any on the mainboard).
>>
>> I guess the screen output will have problems due to the integrated
>> video rom...
>> Is there any way to initialize video in this cases ?
> 
> I'm afraid video is useless for debugging. It is enabled as the very
> last thing coreboot does. You need to be able to follow every step of
> coreboot as it runs.
> 
> Are there any other usable signals on the board? One bit is enough.

MMMh.... Need to check that.
What kind of signals can be of use ? leds ? or more low-level



> If you have budget for a PromICE it can interpret sequences of reads
> from the (emulated) flash chip as a debug write.

Tried to find pricing on that... havent found one.
Do you happen to know how much it costs ?


> Or if you have VHDL skills and a bit of free time, you can add that
> functionality to the Artec LPC dongle or your favorite FPGA devkit.

Interesting. However, that would require even more time xD
I think i'll try the image you suggested soon, and see what it does.
First i need to install another laptop to be the "programming station"
in case everything goes wrong.



> 
> 
> //Peter
> 





From info at coresystems.de  Thu Jul  2 22:09:29 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Jul 2009 22:09:29 +0200
Subject: [coreboot] build service results for r4396
Message-ID: <E1MMSb3-0003QL-BP@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "hargut" checked in revision 4396 to
the coreboot repository. This caused the following 
changes:

Change Log:
ChangeLog:

Turn on Parallel Port and Floppy in Config.lb

Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt at web.de>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4396&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4396&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in hargut's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Thu Jul  2 23:19:34 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  2 Jul 2009 23:19:34 +0200
Subject: [coreboot] [v2] r4397 - in trunk/coreboot-v2/src: include/device
	mainboard/via/epia-m700 northbridge/via/vx800
	northbridge/via/vx800/examples
Message-ID: <mailman.3516.1355071590.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-07-02 23:19:33 +0200 (Thu, 02 Jul 2009)
New Revision: 4397

Modified:
   trunk/coreboot-v2/src/include/device/pci_ids.h
   trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c
   trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c
   trunk/coreboot-v2/src/northbridge/via/vx800/dev_init.c
   trunk/coreboot-v2/src/northbridge/via/vx800/dram_util.c
   trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c
   trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vx800/raminit.c
   trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c
   trunk/coreboot-v2/src/northbridge/via/vx800/vga.c
   trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/vx800/vx800.h
   trunk/coreboot-v2/src/northbridge/via/vx800/vx800_early_smbus.c
Log:
Fix many things for via/epia-m700 to build.

Unfortunately it still doesn't.  I think it's close, though.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/coreboot-v2/src/include/device/pci_ids.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-02 21:19:33 UTC (rev 4397)
@@ -1190,6 +1190,11 @@
 #define PCI_DEVICE_ID_VIA_VT8237S_LPC	0x3372
 #define PCI_DEVICE_ID_VIA_VT8237_SATA	0x5372
 #define PCI_DEVICE_ID_VIA_VT8237_VLINK	0x287e
+#define PCI_DEVICE_ID_VIA_VX855_LPC	0x8353
+#define PCI_DEVICE_ID_VIA_VX855_IDE	0x5324
+#define PCI_DEVICE_ID_VIA_VX855_VGA	0x5122
+#define PCI_DEVICE_ID_VIA_VX855_VLINK	0x7409
+#define PCI_DEVICE_ID_VIA_VX855_MEMCTRL	0x3409
 #define PCI_DEVICE_ID_VIA_CN700_AGP	0x0314
 #define PCI_DEVICE_ID_VIA_CN700_ERR	0x1314
 #define PCI_DEVICE_ID_VIA_CN700_HOST	0x2314

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb	2009-07-02 21:19:33 UTC (rev 4397)
@@ -58,7 +58,7 @@
   end
 end
 mainboardinit cpu/x86/16bit/entry16.inc
-ldscript /cpu/via/16bit/entry16.lds
+ldscript /cpu/x86/16bit/entry16.lds
 
 mainboardinit northbridge/via/vx800/romstrap.inc
 ldscript /northbridge/via/vx800/romstrap.lds

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -59,25 +59,6 @@
 	return current;
 }
 
-unsigned long acpi_create_madt_lapics(unsigned long current)
-{
-	device_t cpu;
-	int cpu_index = 0;
-
-	for (cpu = all_devices; cpu; cpu = cpu->next) {
-		if ((cpu->path.type != DEVICE_PATH_APIC) ||
-		    (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
-			continue;
-		}
-		if (!cpu->enabled)
-			continue;
-		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
-					   cpu_index, cpu->path.apic.apic_id);
-		cpu_index++;
-	}
-	return current;
-}
-
 unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags,
 					  u8 lint)
 {

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -208,6 +208,21 @@
 #endif
 }
 
+/* !!FIXME!!
+ * This is a bogus definition to get it to compile.
+ */
+
+struct VIA_PCI_REG_INIT_TABLE {
+	u8 and_val;
+	u8 or_val;
+	u8 bus;
+	u8 dev;
+	u8 func;
+	u8 reg;
+	u8 v1;
+	u8 v2;
+};
+
 /*
  * Added this table 2008-11-28.
  * This table contains the value needed to be set before begin to init DRAM.

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -204,7 +204,7 @@
 #endif
 
 /* vt6413D */
-static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
+static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
 	//    (And NOT) DDR800 DDR667 DDR533 DDR400
 	//Reg  Mask  Value Value Value Value
 	{0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01},	// 1Rank

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -131,9 +131,9 @@
 	memcpy((void *)(WAKE_THUNK16_ADDR - 100), jump_to_wakeup,
 	       sizeof(jump_to_wakeup));
 
-	jason_tsc_count();
+	//jason_tsc_count();
 	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
-	jason_tsc_count_end();
+	//jason_tsc_count_end();
 
 	unsigned long long *real_mode_gdt_entries_at_eseg;
 	real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT;		/* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/dev_init.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/dev_init.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/dev_init.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -298,7 +298,7 @@
 Purpose   : Set ending address of virtual rank specified by VirRank 
 ===================================================================*/
 
-void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank,	/* ending address
+void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address
 		   register number indicator (INDEX */, INT8 Value /* (value)
 		   add or subtract value to this and after banks */) {
 	u8 Data;

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/dram_util.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/dram_util.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/dram_util.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -56,11 +56,8 @@
 
 u32 via_read_phys(volatile u32 addr)
 {
-	volatile u32 *ptr;
 	volatile u32 y;
-//    ptr = (volatile u32 *)addr;
 	y = *(volatile u32 *)addr;
-//    return *ptr;
 	return y;
 }
 

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -24,7 +24,7 @@
 #include <../northbridge/via/vx800/vx800.h>
 
 #include <arch/io.h>
-#include <arch/pci_rawops.h>
+#include "pci_rawops.h"
 
 static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = {
 	// Combine Stage1 registers
@@ -249,7 +249,7 @@
 {
 	device_t_raw rawdevice = 0;
 	u8 sbchiprev;
-	rawdevice = PCI_RAWDEV(0, 0x11, 0);
+	rawdevice = PCI_DEV(0, 0x11, 0);
 	// Set the PMIO base io address 
 	pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE,
 			       0xff80);
@@ -277,13 +277,13 @@
 	device_t_raw rawdevice = 0;
 	u8 nbchiprev;
 	u32 subid = 0;
-	rawdevice = PCI_RAWDEV(0, 0, 4);
+	rawdevice = PCI_DEV(0, 0, 4);
 	nbchiprev = pci_rawread_config8(rawdevice, 0xf6);
 	printk_debug("NB chip revision =%x\n", nbchiprev);
 
 	via_pci_inittable(nbchiprev, mNbStage2InitTable);
 
-	rawdevice = PCI_RAWDEV(0, 0, 0);
+	rawdevice = PCI_DEV(0, 0, 0);
 
 	subid = PCI_DEVICE_ID_VIA_VX855_D0F0 << 16 + PCI_VENDOR_ID_VIA;
 	pci_rawwrite_config32(rawdevice, 0x2C, subid);
@@ -295,15 +295,15 @@
 
 void IDECSupportOption(u8 sbchiprev)
 {
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0, 0x08);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0, 0x08);
 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x00, 0x80);
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x0A, 0x01, 0xFF);
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x80, 0x00);
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x45, 0x00, 0x80);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x0A, 0x01, 0xFF);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x45, 0x80, 0x00);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x40, 0x02, 0x00);
 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05);	//COMPATIBLE MODE 
-//      pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE 
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x09, 0x00, 0x05);	//COMPATIBLE MODE 
+//      pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE 
 
 	via_pci_inittable(sbchiprev, IDEC_INIT);
 }
@@ -350,23 +350,23 @@
 		Mask = 0x0;
 		Value = 0x1 << BitShift;
 	}
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, Value, Mask);
 
 
 	if (bEnable) {
 		D16 = 0;
-		pci_rawwrite_config16(PCI_RAWDEV(0, 0x10, BaseAddress),
+		pci_rawwrite_config16(PCI_DEV(0, 0x10, BaseAddress),
 				      0x20, D16);
 
 		// Config some Control Register
 		Mask = 0x00;
 		Value = 0x12;
 
-		pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress),
+		pci_rawmodify_config8(PCI_DEV(0, 0x10, BaseAddress),
 				      0x41, Value, Mask);
 		Mask = 0x00;
 		Value = 0xEB;
-		pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress),
+		pci_rawmodify_config8(PCI_DEV(0, 0x10, BaseAddress),
 				      0x4B, Value, Mask);
 	}
 	return;
@@ -407,13 +407,13 @@
 		Mask = 0x0;
 		Value = 0x1 << 1;
 	}
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, Value, Mask);
 
 
 	if (bEnable) {
 		// Get Chipset Revision
 		EHCIRevision =
-		    pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6);
+		    pci_rawread_config8(PCI_DEV(0, 0x10, 4), 0xF6);
 		printk_debug("EHCI Revision =%x\n", EHCIRevision);
 		via_pci_inittable(EHCIRevision, mEHCIInitTable);
 	}
@@ -475,9 +475,9 @@
 {
 	u8 HpetEnable = HPET_ENABLE_BIT;
 	u16 HpetBase = HPET_BASE_ADDRESS;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_CONTROL,
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), R_SB_HPET_CONTROL,
 			     HpetEnable);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0),
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0),
 			      R_SB_HPET_ADDRESS + 1, HpetBase);
 }
 
@@ -512,7 +512,7 @@
 	// Set SCI IRQ and its level trigger
 	Mask = 0x0F;
 	Value = 0x09;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x82, Value, Mask);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x82, Value, Mask);
 
 	Mask = 0x02;
 	Value = 0x02;
@@ -533,7 +533,7 @@
 	// Now it is C2 & C4 Up Down Mode
 	Mask = 0xFF;
 	Value = 0x30;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask);	//SB_LPC_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask);	//SB_LPC_REG
 
 	Mask = 0xFF;
 	Value = 0x1F;
@@ -542,15 +542,15 @@
 
 	Mask = 0x00;
 	Value = 0x80;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask);	//SB_VLINK_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask);	//SB_VLINK_REG
 
 	Mask = 0xFF;
 	Value = 0x00;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask);	//SB_VLINK_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask);	//SB_VLINK_REG
 
 	Mask = 0xFF;
 	Value = 0x1F;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask);	//SB_VLINK_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask);	//SB_VLINK_REG
 }
 
 void InitSBPM(u8 sbchiprev)
@@ -565,7 +565,7 @@
 	device_t_raw rawdevice = 0;
 	u8 sbchiprev;
 
-	rawdevice = PCI_RAWDEV(0, 11, 0);
+	rawdevice = PCI_DEV(0, 11, 0);
 	sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
 	printk_debug("SB chip revision =%x\n", sbchiprev);
 
@@ -585,7 +585,7 @@
 
 	HpetInit();
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG
 
 }
 
@@ -603,7 +603,7 @@
 	Stage2SbInit();
 
 	//5.open hdac
-	pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04);
+	pci_rawmodify_config32(PCI_DEV(0, 0x11, 7), 0xd1, 0, 0x04);
 	printk_debug("End: init_VIA_chipset\n");
 }
 
@@ -634,27 +634,27 @@
 
 #if 0
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5,
-			     pci_rawread_config8(PCI_RAWDEV(0, 3, 0),
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xa3, 0x80);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 7), 0x60, 0x20);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 7), 0xE5,
+			     pci_rawread_config8(PCI_DEV(0, 3, 0),
 						 0x88));
 #endif
 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x51, 0x40, 0x40);	//close CE-ATA (Consumer Electronics-ATA) and NFC
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x51, 0x40, 0x40);	//close CE-ATA (Consumer Electronics-ATA) and NFC
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x40, 0x40);	//close USB Device Mode
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable 
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x40, 0x40);	//close USB Device Mode
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci
 
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
 
 	printk_info("=================SB 50h=%02x \n",
-		    pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
+		    pci_rawread_config8(PCI_DEV(0, 0x11, 0), 0x50));
 
 
 	/* FIXME: Is there a better way to handle this? */
@@ -671,7 +671,7 @@
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -690,7 +690,7 @@
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -710,7 +710,7 @@
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -723,7 +723,7 @@
 	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
 
 
-//          pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
+//          pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBA, 0x0571);
 
 #if 0
 	x = y = 0;
@@ -732,7 +732,7 @@
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -743,10 +743,10 @@
 
 #if 0
 
-	y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d);
+	y = pci_rawread_config8(PCI_DEV(0, 0xf, 0), 0x0d);
 	y &= 0x0f;
 	y |= 0x40;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d, y);
+	pci_rawwrite_config8(PCI_DEV(0, 0xf, 0), 0x0d, y);
 #endif
 
 #if 0
@@ -948,7 +948,7 @@
 	u8 i;
 /* error form ---- but add the chance to resume
 for(i=0;i<5;i++){
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]);
+		pci_rawwrite_config8(PCI_DEV(0, 0, 0), i, d0f0pcitable[i+0xcb]);
 	}
 
 	
@@ -956,7 +956,7 @@
 
 /* RO reg
 for(i=0;i<5;i++){
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]);
+		pci_rawwrite_config8(PCI_DEV(0, 0, 0), i+0xcb, d0f0pcitable[i]);
 	}
 */
 
@@ -964,25 +964,25 @@
 //boot ok, resume still err in linux    
 #if 1
 	for (i = 0; i < 9; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50,
 				     d0f2pcitable[i]);
 	}
 	//9 is warm reset reg,   // boot err in coreboot
 	for (i = 10; i < 64; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50,
 				     d0f2pcitable[i]);
 	}
 	//0x90 look d0f2 appendixA1 ,   if set this to 09 or 0b, then some ddr2 will crash.
 	for (i = 65; i < 113; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50,
 				     d0f2pcitable[i]);
 	}
 #endif
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x66, 0x09);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x70, 0xdd);
-	//  pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x90, 0x09);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x92, 0x40);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x66, 0x09);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x70, 0xdd);
+	//  pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x90, 0x09);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x92, 0x40);
 
 #endif
 
@@ -993,61 +993,61 @@
 
 //d0f3 
 /*		*/
-	//      pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b);  setting, my lspci is 0x29
+	//      pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x3b);  setting, my lspci is 0x29
 	//set bit4 cause the ide not be found
-//              pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b);
+//              pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x2b);
 	//set bit1 cause the ide not be found
 
-//              pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x95, 0x05);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x99, 0x12);
+//              pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x29);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x95, 0x05);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x99, 0x12);
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xde, 0x00);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0xde, 0x00);
 #endif
 
 //boot ok,  resume err in coreboot 
 #if 1
 	for (i = 0; i < 99; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 4), i + 0x8d,
 				     d0f4pcitable[i]);
 	}
 #endif
 
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xe9, 0x90);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xec, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xed, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xee, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xe9, 0x90);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xec, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xed, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xee, 0x0);
 #endif
 
 
 #if 1
 //boot ok, resume still err in linux    
 	for (i = 0; i < 160; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 5), i + 0x60,
 				     d0f5pcitable[i]);
 	}
 	for (i = 0; i < 144; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), i + 0x60,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 7), i + 0x60,
 				     d0f7pcitable[i]);
 	}
 	for (i = 0; i < 3; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 1, 0), i + 0xb0,
+		pci_rawwrite_config8(PCI_DEV(0, 1, 0), i + 0xb0,
 				     d1f0pcitable[i]);
 	}
 	for (i = 0; i < 96; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), i + 0x40,
 				     dcf0pcitable[i]);
 	}
 #endif
 
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x61, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x63, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x76, 0xd0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x88, 0x81);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x89, 0x01);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x8A, 0x60);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x61, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x63, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x76, 0xd0);
+	pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x88, 0x81);
+	pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x89, 0x01);
+	pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x8A, 0x60);
 #endif
 
 //d15f0
@@ -1057,24 +1057,24 @@
 
 #if 1
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2);	// no affect.
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 0), 0x4a, 0xa2);	// no affect.
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 1), 0x4a, 0xa2);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 2), 0x4a, 0xa2);
 
 //boot ok, resume still err in linux,  and if disable USB, then all ok
 //      for(i=0;i<48;i++){
 	for (i = 0; i < 44; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), i + 0x40,
 				     d10f4pcitable[i]);
 	}
 #endif
 
 //#ifdef NOOPTION_1
 #if 0
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6b, 0x01);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6d, 0x00);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6e, 0x08);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6b, 0x01);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6d, 0x00);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6e, 0x08);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6f, 0x80);
 #endif
 
 
@@ -1083,171 +1083,171 @@
 //before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok
 //      for(i=0;i<192;i++){
 	for (i = 0; i < 6; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//6 is uart and dvp vcp,   will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
 
 	//7-18 is my familar part
 	for (i = 7; i < 18; i++) {	//sleep ok ,resume sleep err 2 
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 
 	for (i = 18; i < 21; i++) {	//sleep ok ,   sleep err 1, resume 
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//0x55 56 57 irq intA#B#C# linkA#linkB#linkC#
 	for (i = 24; i < 27; i++) {	//sleep ok , resume sleep err 1  resume  1
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//5b port 80h
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x5b, 0x0, 0x08);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x5b, 0x0, 0x08);
 	//          i++;
-	//      pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]);
+	//      pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]);
 
 	for (i = 28; i < 72; i++) {	//sleep ok , resume  sleep err 1 , resume 1ci
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//7273ACPI BASE
 
 	for (i = 74; i < 112; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 	//B0B4B5 dvp vcp,  if copy this ,then no uart, no gui(of unbuntu)
-	// pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]);
-	i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0);
+	// pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]);
+	i = pci_rawread_config8(PCI_DEV(0, 17, 0), 0xB0);
 	//multiplex with VCP
 	//    i = i | 0x30;
 	i = i & 0xf7;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 0), 0xB0, i);
 
 
 
 	for (i = 113; i < 114; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 	for (i = 115; i < 116; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 
 	for (i = 118; i < 192; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 #endif
 #ifdef NOOPTION_1
 //      for(i=0;i<192;i++){
 	for (i = 0; i < 6; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 	//6 is uart and dvp vcp,   will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
 
 	//7-18 is my familar part
 	for (i = 7; i < 18; i++) {	//   sleep err 2
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	for (i = 18; i < 21; i++) {	//sleep ok , resume ???
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//0x55 56 57 irq intA#B#C# linkA#linkB#linkC#
 	for (i = 24; i < 27; i++) {	//sleep ok , resume ???
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//5b port 80h
 	i++;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 			     OPTION_1_d11f0pcitable[i]);
 
 	for (i = 28; i < 72; i++) {	//sleep ok , resume???
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 	//7273ACPI BASE
 
 	for (i = 74; i < 112; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	//B0B4B5 dvp vcp,  if copy this ,then no uart, no gui(of unbuntu)
-	// pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]);
-	i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0);
+	// pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]);
+	i = pci_rawread_config8(PCI_DEV(0, 17, 0), 0xB0);
 	//multiplex with VCP
 	//    i = i | 0x30;
 	i = i & 0xf7;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 0), 0xB0, i);
 
 
 
 	for (i = 113; i < 114; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	for (i = 115; i < 116; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	for (i = 118; i < 192; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 #endif
 
 #if 1
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE);	//5324
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBE,
+	pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE);	//5324
+	pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBE,
 			      PCI_DEVICE_ID_VIA_VX855_IDE);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA0,
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0xA0,
 			      PCI_VENDOR_ID_VIA);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC);	//8353
-	i = pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x79);
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC);	//8353
+	i = pci_rawread_config8(PCI_DEV(0, 0x11, 0), 0x79);
 	i &= ~0x40;
 	i |= 0x40;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0x79, i);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72,
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0x79, i);
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0x72,
 			      PCI_DEVICE_ID_VIA_VX855_LPC);
 
 
 //boot ok, resume still err in linux
 	for (i = 0; i < 192; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), i + 0x40,
 				     d11f7pcitable[i]);
 	}
 #endif
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x61, 0x2a);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x63, 0xa0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x64, 0xaa);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x84, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x61, 0x2a);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x63, 0xa0);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x64, 0xaa);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x84, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x88, 0x02);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0xe6, 0x3f);
 #endif
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31);
+	pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x40, 0x20);
+	pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x41, 0x31);
 
 
 
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00);
+	pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x40, 0x00);
 #endif
 
 
@@ -1256,11 +1256,11 @@
 	u8 i911;
 	//disable CHB L.L
 	//set VGA memory selection
-	i911 = pci_rawread_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0);
+	i911 = pci_rawread_config8(PCI_DEV(0, 0x1, 0), 0xb0);
 	i911 &= 0xF8;
 	//ByteVal |= 0x03;
 	i911 |= 0x01;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911);
+	pci_rawwrite_config8(PCI_DEV(0, 0x1, 0), 0xb0, i911);
 
 
 #if 1
@@ -1290,8 +1290,8 @@
 
 
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);//
-//      pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
+	//pci_rawmodify_config8(PCI_DEV(0, 0x10, 4), 0x04, 0x17, 0x17);//
+//      pci_rawmodify_config8(PCI_DEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
 
 
 

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -35,6 +35,11 @@
 #include "northbridge.h"
 #include "vx800.h"
 
+/* !!FIXME!!  This was meant to be a CONFIG option */
+#define VIACONFIG_TOP_SM_SIZE_MB 32	// Set frame buffer 32M for default
+/* !!FIXME!!  I declared this to fix the build. */
+u8 acpi_sleep_type = 0;
+
 static void memctrl_init(device_t dev)
 {
 /*

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/raminit.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/raminit.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -20,7 +20,6 @@
 #include <spd.h>
 #include <sdram_mode.h>
 #include <delay.h>
-#include <arch/pci_rawops.h>
 
 #define DEBUG_RAM_SETUP 1
 

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include "pci_rawops.h"
+
 typedef struct __UMA_RAM_tag {
 	u16 DramSize;
 	u8 D0F3Val;
@@ -48,6 +50,9 @@
 #define VGA_PORT_32M	0xF0
 #define VGA_PORT_16M	0xF8
 
+#define VIACONFIG_VGA_PCI_10 0xf8000008
+#define VIACONFIG_VGA_PCI_14 0xfc000000
+
 static const UMARAM UMARamArr[] = {
 	{0, UMARAM_0M, FB_4M, 0xFE},
 	{8, UMARAM_8M, FB_8M, 0xFC},
@@ -168,10 +173,10 @@
 	pci_write_config32(vga_dev, 0x14, Tmp);
 
 //enable direct cpu frame buffer access
-	i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1);
+	i = pci_conf1_read8(PCI_DEV(0, 0, 3), 0xa1);
 	i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01);
+	pci_conf1_write8(PCI_DEV(0, 0, 3), 0xa1, i);
+	pci_conf1_write8(PCI_DEV(0, 0, 3), 0xa0, 0x01);
 
 	//enable GFx memory space access control for S.L and mmio
 	ByteVal = pci_read_config8(d0f0_dev, 0xD4);

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/vga.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/vga.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/vga.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -45,19 +45,22 @@
 #define CRTC_INDEX	0x3d4
 #define CRTC_DATA	0x3d5
 
+/* !!FIXME!! These were CONFIG_ options.  Fix it in uma_ram_setting.c too. */
+#define VIACONFIG_VGA_PCI_10 0xf8000008
+#define VIACONFIG_VGA_PCI_14 0xfc000000
+
 void write_protect_vgabios(void)
 {
 	device_t dev;
 
 	printk_info("write_protect_vgabios\n");
 	/* there are two possible devices. Just do both. */
-	dev =
-	    dev_find_device(PCI_VENDOR_ID_VIA,
-			    PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_VIA,
+			      PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
 	if (dev)
 		pci_write_config8(dev, 0x80, 0xff);
 	/*vx855 no th 0x61 reg */
-	/*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_NB_VLINK, 0);
+	/*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0);
 	   //if(dev)
 	   //   pci_write_config8(dev, 0x61, 0xff); */
 }
@@ -90,7 +93,7 @@
 	printk_debug("DO THE VGA BIOS\n");
 
 	do_vgabios();
-	if ((acpi_sleep_type == 3) || (PAYLOAD_IS_SEABIOS == 0)) {
+	if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
 		printk_debug("Enable VGA console\n");
 		// remove this function since in cn700 it is said "VGA seems to work without this, but crash & burn with it"
 		//but the existense of  vga_enable_console()  seems do not hurt my coreboot. XP+ubuntu s3 can resume with and without this function.
@@ -103,7 +106,7 @@
 	pci_rom_load(dev, 0xfff80000);
 	run_bios(dev, 0xc0000);
 #endif
-	if ((acpi_sleep_type == 3) || (PAYLOAD_IS_SEABIOS == 0)) {
+	if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
 		/* It's not clear if these need to be programmed before or after
 		 * the VGA bios runs. Try both, clean up later */
 		/* Set memory rate to 200MHz */
@@ -125,7 +128,7 @@
 
 static void vga_read_resources(device_t dev)
 {
-	dev->rom_address = (void *)(0xffffffff - FULL_ROM_SIZE + 1);
+	dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1);
 	dev->on_mainboard = 1;
 	pci_dev_read_resources(dev);
 }

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -118,7 +118,7 @@
 
 static void real_mode_switch_call_vga(unsigned long devfn)
 {
-	if ((acpi_sleep_type == 0) && (PAYLOAD_IS_SEABIOS == 1))
+	if ((acpi_sleep_type == 0)/* && (PAYLOAD_IS_SEABIOS == 1)*/)
 		return;
 	__asm__ __volatile__(
 				    // paranoia -- does ecx get saved? not sure. This is 
@@ -205,7 +205,7 @@
    epia-m does not always autosence the main console so forcing it on is good !! */
 void vga_enable_console()
 {
-	if ((acpi_sleep_type == 0) && (PAYLOAD_IS_SEABIOS == 1))
+	if ((acpi_sleep_type == 0)/* && (PAYLOAD_IS_SEABIOS == 1)*/)
 		return;
 	__asm__ __volatile__(
 				    /* paranoia -- does ecx get saved? not sure. This is 
@@ -319,7 +319,7 @@
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = 0xffffffff - FULL_ROM_SIZE + 1;
+	rom = 0xffffffff - CONFIG_ROM_SIZE + 1;
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
 	printk_debug("rom base: %x\n", rom);
 	buf = (unsigned char *)rom;
@@ -522,7 +522,9 @@
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
-	case 0...15:
+	case 0: case 1: case 2: case 3: case 4: case 5:
+	case 6: case 7: case 8: case 9: case 10:
+	case 11: case 12: case 13: case 14: case 15:
 		// These are not BIOS service, but the CPU-generated exceptions
 		printk_info("biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
@@ -535,7 +537,7 @@
 		}
 		printk_debug("biosint: Bailing out\n");
 		// "longjmp"
-		if ((acpi_sleep_type == 3) || (PAYLOAD_IS_SEABIOS == 0))	// add this to keep same with kevin's seabios patch in 2008-9-8
+		if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/)	// add this to keep same with kevin's seabios patch in 2008-9-8
 			vga_exit();
 		break;
 

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/vx800.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/vx800.h	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/vx800.h	2009-07-02 21:19:33 UTC (rev 4397)
@@ -25,12 +25,12 @@
 {
 }
 #endif
-#define REV_B0  0x10
+//#define REV_B0 0x10
 #define REV_B1 0x11
-#define REV_B2 0x12
+//#define REV_B2 0x12
 #define REV_B3 0x13
 #define REV_B4 0x14
-#define REV_B2 0xB4
+//#define REV_B2 0xB4
 #define REV_B0 0x00
 #define REV_B2 0x01
 

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/vx800_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/vx800_early_smbus.c	2009-07-02 19:06:01 UTC (rev 4396)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/vx800_early_smbus.c	2009-07-02 21:19:33 UTC (rev 4397)
@@ -114,7 +114,6 @@
 /* Public functions */
 static unsigned int set_ics_data(unsigned char dev, int data, char len)
 {
-	int i;
 	smbus_reset();
 	/* clear host data port */
 	outb(0x00, SMBHSTDAT0);
@@ -125,7 +124,7 @@
 	inb(SMBHSTCTL);
 
 	/* fill blocktransfer array */
-	if (dev = 0xd2) {
+	if (dev == 0xd2) {
 		//char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
 		outb(0x0d, SMBBLKDAT);
 		outb(0x00, SMBBLKDAT);




From peter at stuge.se  Thu Jul  2 23:26:34 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 23:26:34 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <200907022202.08049.harald.gutmann@gmx.net>
References: <20090701142139.GA7679@flashgordon>
	<20090702185842.GA5338@flashgordon>
	<20090702194053.7744.qmail@stuge.se>
	<200907022202.08049.harald.gutmann@gmx.net>
Message-ID: <20090702212634.3905.qmail@stuge.se>

Harald Gutmann wrote:
> > Is the port interrupt-driven, or polling, on your system, Andreas?
> 
> Here on my system it says also polling, like on Andreas system.
> What is the difference between interrupt driven and polling?

Interrupt driven means the port has an interrupt assigned to it, and
that communication over the port is event based.

Polling means there is a timer running in the kernel which will check
the port for activity every few milliseconds or something.


> On vendor bios it is interrupt-driven.
> Is an ACPI part missing to get it interrupt driven?

I think so, yes.


//Peter
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From stepan at coresystems.de  Thu Jul  2 23:28:42 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 2 Jul 2009 23:28:42 +0200
Subject: [coreboot] Simple Firmware Interface?
In-Reply-To: <20090702105109.5857.qmail@stuge.se>
References: <a698c16a0906251356q29f9ddbei9cafb22a975a0c84@mail.gmail.com>
	<4A43F3CC.5070508@georgi-clan.de>
	<20090702105109.5857.qmail@stuge.se>
Message-ID: <A21DEE10-7D66-4C55-B6AA-3C0413100F9F@coresystems.de>



On 02.07.2009, at 12:51, Peter Stuge <peter at stuge.se> wrote:

> Patrick Georgi wrote:
>> It's a subset of ACPI, looks quite Intel specific, and the FAQ (and
>> the draft standard, I think) state that if both, ACPI and SFI are
>> available, ACPI should be used.
>>
>> So, nothing to worry about.
>
> I don't know. I think SFI seems to be a good thing. I believe we will
> want to support it.
>
>
> //Peter
>


Sure,.. I guess if you are interested in SFI you should send a patch;  
it won't be denied.

Are there any OSes that support SFI? Maybe it could even be  
incorporated into the coreboot table?

Stefan


> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From peter at stuge.se  Thu Jul  2 23:37:44 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2009 23:37:44 +0200
Subject: [coreboot] Simple Firmware Interface?
In-Reply-To: <A21DEE10-7D66-4C55-B6AA-3C0413100F9F@coresystems.de>
References: <a698c16a0906251356q29f9ddbei9cafb22a975a0c84@mail.gmail.com>
	<4A43F3CC.5070508@georgi-clan.de>
	<20090702105109.5857.qmail@stuge.se>
	<A21DEE10-7D66-4C55-B6AA-3C0413100F9F@coresystems.de>
Message-ID: <20090702213744.5807.qmail@stuge.se>

Stefan Reinauer wrote:
>>> So, nothing to worry about.
>>
>> I don't know. I think SFI seems to be a good thing. I believe we
>> will want to support it.
> 
> Sure,.. I guess if you are interested in SFI you should send a
> patch; it won't be denied.

Yep.


> Are there any OSes that support SFI? Maybe it could even be
> incorporated into the coreboot table?

There's a Linux git tree on simplefirmware.org.


//Peter



From info at coresystems.de  Thu Jul  2 23:42:23 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 02 Jul 2009 23:42:23 +0200
Subject: [coreboot] build service results for r4397
Message-ID: <E1MMU2x-00055E-KR@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4397 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix many things for via/epia-m700 to build.

Unfortunately it still doesn't.  I think it's close, though.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4397&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4397&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From russ at ashlandhome.net  Fri Jul  3 00:08:48 2009
From: russ at ashlandhome.net (Russell Whitaker)
Date: Thu, 2 Jul 2009 15:08:48 -0700 (PDT)
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <200907022202.08049.harald.gutmann@gmx.net>
References: <20090701142139.GA7679@flashgordon>
	<20090702185842.GA5338@flashgordon>
	<20090702194053.7744.qmail@stuge.se>
	<200907022202.08049.harald.gutmann@gmx.net>
Message-ID: <alpine.LNX.2.00.0907021457220.1449@bigred.russwhit.org>



On Thu, 2 Jul 2009, Harald Gutmann wrote:

> On Thursday 02 July 2009 21:40:52 Peter Stuge wrote:
>> Andreas B. Mundt wrote:
[..]
> What is the difference between interrupt driven and polling?

Polling means the printer driver checks the printer at regular intervals
to see if the printer is ready for another character.

Interrupt driven the printer tells the driver it's ready.

Thus a high speed printer will run a little slower with polling.

   Russ



From r.marek at assembler.cz  Fri Jul  3 00:15:33 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 03 Jul 2009 00:15:33 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <200907021958.47574.harald.gutmann@gmx.net>
References: <20090701142139.GA7679@flashgordon>
	<200907021958.47574.harald.gutmann@gmx.net>
Message-ID: <4A4D3185.9070001@assembler.cz>

> Maybe Rudolf Marek can us help here, because he wrote the automatic generation 
> for that ACPI table (SSDT).

Hi,

If I understand correctly, the 1800MHz is missing? If so, please check what is 
the portal frequency for this CPU. Maybe it is 2000 and not 1800 (so prop bios 
is wrong). Check the BKDG. I'm very busy so I think better would be if someone 
else could check.

The interupt driven parport works now?

Rudolf



From bari at onelabs.com  Fri Jul  3 00:52:38 2009
From: bari at onelabs.com (bari)
Date: Thu, 02 Jul 2009 17:52:38 -0500
Subject: [coreboot] pci_rawops.h from vx800 tree
Message-ID: <4A4D3A36.4000102@onelabs.com>

This file has been sanitized for your safety.

-Bari
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From Cristi.Magherusan at net.utcluj.ro  Fri Jul  3 02:23:55 2009
From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Fri, 03 Jul 2009 03:23:55 +0300
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
In-Reply-To: <4A4D1296.1020604@Ivn.cl>
References: <4A4CFC11.4070609@Ivn.cl> <20090702184531.27293.qmail@stuge.se>
	<4A4D00D8.2020503@Ivn.cl> <20090702193838.7170.qmail@stuge.se>
	<4A4D1296.1020604@Ivn.cl>
Message-ID: <1246580635.30256.30.camel@localhost.localdomain>

On Thu, 2009-07-02 at 16:03 -0400, Ivan Barrera A. wrote:
> Peter Stuge escribi?:
> > Ivan Barrera A. wrote:
> >>> you need another debug output method..
> >> The G1 does not have any serial port :/
> >> (and havent find any on the mainboard).
> >>
> >> I guess the screen output will have problems due to the integrated
> >> video rom...
> >> Is there any way to initialize video in this cases ?
> > 
> > I'm afraid video is useless for debugging. It is enabled as the very
> > last thing coreboot does. You need to be able to follow every step of
> > coreboot as it runs.
> > 
> > Are there any other usable signals on the board? One bit is enough.
> 
> MMMh.... Need to check that.
> What kind of signals can be of use ? leds ? or more low-level
> 
> 
> 
> > If you have budget for a PromICE it can interpret sequences of reads
> > from the (emulated) flash chip as a debug write.
> 
> Tried to find pricing on that... havent found one.
> Do you happen to know how much it costs ?
> 
> 
> > Or if you have VHDL skills and a bit of free time, you can add that
> > functionality to the Artec LPC dongle or your favorite FPGA devkit.
> 
> Interesting. However, that would require even more time xD
> I think i'll try the image you suggested soon, and see what it does.
> First i need to install another laptop to be the "programming station"
> in case everything goes wrong.
> 
Hi,

I think this could be a good testcase for SerialICE
http://www.coreboot.org/pipermail/coreboot-announce/2009-June/000002.html

What do you think?

Cristi

-- 
Ing. Cristi M?gheru?an, System/Network Engineer
Technical University of Cluj-Napoca, Romania
http://cc.utcluj.ro  +40264 401247
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From peter at stuge.se  Fri Jul  3 03:32:57 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Jul 2009 03:32:57 +0200
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
In-Reply-To: <1246580635.30256.30.camel@localhost.localdomain>
References: <4A4CFC11.4070609@Ivn.cl> <20090702184531.27293.qmail@stuge.se>
	<4A4D00D8.2020503@Ivn.cl> <20090702193838.7170.qmail@stuge.se>
	<4A4D1296.1020604@Ivn.cl>
	<1246580635.30256.30.camel@localhost.localdomain>
Message-ID: <20090703013257.20601.qmail@stuge.se>

Cristi Magherusan wrote:
> I think this could be a good testcase for SerialICE
> What do you think?

I think it's difficult to use SerialICE without a serial port. :\


//Peter
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From Zheng.Bao at amd.com  Fri Jul  3 04:06:36 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Fri, 3 Jul 2009 10:06:36 +0800
Subject: [coreboot] [PATCH] v3 Resource allocator to v2
In-Reply-To: <2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>
References: <C9163063016E42B78E446D11A3429A0E@chimp><2831fecf0905271525mb32bef9s7ded9f8d813f22e@mail.gmail.com><13426df10905271801k60c6c1c8l71ea74a846d91a20@mail.gmail.com>
	<2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B1702D2B52F@sbjgexmb1.amd.com>

In SB600, the IOAPIC is allocated in sb600_sm.c. Is there any conflict
with sb600_lpc.c?

Zheng

________________________________________
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Myles Watson
Sent: Friday, July 03, 2009 2:59 AM
To: ron minnich
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] v3 Resource allocator to v2


On Wed, May 27, 2009 at 7:01 PM, ron minnich <rminnich at gmail.com> wrote:

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Rev 4394.

Thanks,
Myles




From goboster at yahoo.com  Fri Jul  3 04:08:08 2009
From: goboster at yahoo.com (Goboster)
Date: Fri, 3 Jul 2009 02:08:08 +0000 (UTC)
Subject: [coreboot] Support for Asus A8M2N-LA ?
Message-ID: <loom.20090703T011652-263@post.gmane.org>

I've got a HP Pavilion desktop that has an ASUS OEM motherboard model A8M2N-LA.
Manufacturer details are here (there is a nice schematic):
http://tr.im/qHw7

It appears to have an MCP51 southbridge, ASUS A8000 SuperIO, a "GeForce 6150 LE"
northbridge, Pm49FL004 flash, and also has a Nvidia C51PVG chip on it. I have no
idea what that last chip is, but I saw some references to it in an earlier
thread here http://tr.im/qHvZ .

I don't see the MCP51 listed in the supported southbridges, but then I saw some
reference to mcp51_early_setup_car.c in this thread http://tr.im/qHr8 so maybe
some headway has been made?

I'm really interested in getting the memory hole enabled so I can actually use
all my memory... Would that be possible with coreboot?

Here's outputs as requested in the faq:
 lspci -tvnn
-[0000:00]-+-00.0  nVidia Corporation C51 Host Bridge [10de:02f0]
           +-00.1  nVidia Corporation C51 Memory Controller 0 [10de:02fa]
           +-00.2  nVidia Corporation C51 Memory Controller 1 [10de:02fe]
           +-00.3  nVidia Corporation C51 Memory Controller 5 [10de:02f8]
           +-00.4  nVidia Corporation C51 Memory Controller 4 [10de:02f9]
           +-00.5  nVidia Corporation C51 Host Bridge [10de:02ff]
           +-00.6  nVidia Corporation C51 Memory Controller 3 [10de:027f]
           +-00.7  nVidia Corporation C51 Memory Controller 2 [10de:027e]
           +-02.0-[0000:01]--
           +-04.0-[0000:02]--
           +-05.0  nVidia Corporation C51 [GeForce 6150 LE] [10de:0241]
           +-09.0  nVidia Corporation MCP51 Host Bridge [10de:0270]
           +-0a.0  nVidia Corporation MCP51 LPC Bridge [10de:0260]
           +-0a.1  nVidia Corporation MCP51 SMBus [10de:0264]
           +-0a.2  nVidia Corporation MCP51 Memory Controller 0 [10de:0272]
           +-0b.0  nVidia Corporation MCP51 USB Controller [10de:026d]
           +-0b.1  nVidia Corporation MCP51 USB Controller [10de:026e]
           +-0d.0  nVidia Corporation MCP51 IDE [10de:0265]
           +-0e.0  nVidia Corporation MCP51 Serial ATA Controller [10de:0266]
           +-0f.0  nVidia Corporation MCP51 Serial ATA Controller [10de:0267]
           +-10.0-[0000:03]--+-05.0  Agere Systems FW323 [11c1:5811]
           |                 +-09.0  Conexant HSF 56k Data/Fax Modem [14f1:2f20]
           |                 \-0a.0  RaLink RT2500 802.11g Cardbus/mini-PCI
[1814:0201]
           +-10.1  nVidia Corporation MCP51 High Definition Audio [10de:026c]
           +-14.0  nVidia Corporation MCP51 Ethernet Controller [10de:0269]
           +-18.0  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
HyperTransport Technology Configuration [1022:1100]
           +-18.1  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address
Map [1022:1101]
           +-18.2  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM
Controller [1022:1102]
           \-18.3  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
Miscellaneous Control [1022:1103]

superiotool -dV
(all other probes not listed failed)
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
Found ASUS A8000 (id=0x77, rev=0x03) at 0x2e
Register dump:
idx 03 07 20 21 22 23 24 26  27 28 2a 2b 2c 2d 2e 2f
val 00 0a 77 03 00 00 44 2e  00 00 00 00 00 00 00 00
def RR 00 77 NA 00 RR 44 MM  MM RR NA NA NA NA NA NA
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 00 00 00 00 04 0e 00 ff  00 00
def 00 03 f0 06 02 0e 00 ff  00 00
LDN 0x03 (Parallel port)
idx 30 60 61 70 74 f0 f1
val 00 00 00 00 04 3c 00
def 00 00 00 00 04 3c 00
LDN 0x04 (COM1)
idx 30 60 61 70 f0
val 00 00 00 00 00
def 00 00 00 00 00
LDN 0x05 (COM2)
idx 30 60 61 70 f0 f1 f2
val 00 00 00 00 00 02 03
def 00 00 00 00 00 02 03
LDN 0x07 (Keyboard)
idx 30 70 72 f0
val 01 01 0c 00
def 00 00 00 00
LDN 0x0a (Runtime registers)
idx 30 60 61 62 63 f0 f1 f2
val 01 08 00 00 00 00 00 04
def 00 00 00 00 00 NA RR 04
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0x00, rev=0x00

flashrom -V
Calibrating delay loop... 353M loops per second. OK.
No coreboot table found.
Found chipset "NVidia MCP51", enabling flash write... OK.
Probing for Am29F040B, 512 KB
probe_29f040b: id1 0x23, id2 0x3d
Probing for Am29LV040B, 512 KB
probe_29f040b: id1 0x23, id2 0x3d
Probing for Am29F016D, 2048 KB
probe_29f040b: id1 0xff, id2 0xff
Probing for AE49F2008, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for At29C040A, 512 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for At29C020, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for At49F002(N), 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for At49F002(N)T, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for EN29F002(A)(N)T, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for EN29F002(A)(N)B, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for MBM29F400TC, 512 KB
probe_m29f400bt: id1 0x23, id2 0x2d
Probing for MX29F002, 256 KB
probe_29f002: id1 0x9d, id2 0x6e
Probing for MX25L4005, 512 KB
generic_spi_command called, but no SPI chipset detected
Probing for MX25L8005, 1024 KB
generic_spi_command called, but no SPI chipset detected
Probing for MX25L3205, 4096 KB
generic_spi_command called, but no SPI chipset detected
Probing for S25FL016A, 2048 KB
generic_spi_command called, but no SPI chipset detected
Probing for SST25VF040B, 512 KB
generic_spi_command called, but no SPI chipset detected
Probing for SST25VF016B, 2048 KB
generic_spi_command called, but no SPI chipset detected
Probing for SST29EE020A, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST28SF040A, 512 KB
probe_28sf040: id1 0x23, id2 0x3d
Probing for SST39SF010A, 128 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST39SF020A, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST39SF040, 512 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST39VF020, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST49LF040B, 512 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST49LF040, 512 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST49LF020A, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST49LF080A, 1024 KB
probe_jedec: id1 0xff, id2 0xff
Probing for SST49LF002A/B, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST49LF003A/B, 384 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST49LF004A/B, 512 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for SST49LF008A, 1024 KB
probe_jedec: id1 0xff, id2 0xff
Probing for SST49LF004C, 512 KB
probe_49lfxxxc: id1 0x23, id2 0x3d
Probing for SST49LF008C, 1024 KB
probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST49LF016C, 2048 KB
probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST49LF160C, 2048 KB
probe_49lfxxxc: id1 0xff, id2 0xff
Probing for Pm49FL002, 256 KB
probe_jedec: id1 0x9d, id2 0x6e
Probing for Pm49FL004, 512 KB
probe_jedec: id1 0x9d, id2 0x6e
Pm49FL004 found at physical address 0xfff80000.
Flash part is Pm49FL004 (512 KB).
No operations were specified.

Thanks!






From Zheng.Bao at amd.com  Fri Jul  3 05:43:37 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Fri, 3 Jul 2009 11:43:37 +0800
Subject: [coreboot] [v2] r4394 - in trunk/coreboot-v2/src:
	cpu/amd/sc520cpu/emulation/qemu-x86 cpu/ppc/ppc4xx devices
	include/devicenorthbridge/amd/amdfam10
	northbridge/amd/amdk8northbridge/amd/gx1 northbridge/amd/gx2
	northbridge/amd/lxnorthbridge/ibm/cpc710 n
In-Reply-To: <20090702185642.082A845005B@mail154-va3.bigfish.com>
References: <20090702185642.082A845005B@mail154-va3.bigfish.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B1702D2B5A7@sbjgexmb1.amd.com>

This patch makes my AMD fam10 board not work (K8 works). The resource
can not be allocated correctly.


Zheng

-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of svn at coreboot.org
Sent: Friday, July 03, 2009 2:56 AM
To: coreboot at coreboot.org
Subject: [coreboot] [v2] r4394 - in trunk/coreboot-v2/src:
cpu/amd/sc520cpu/emulation/qemu-x86 cpu/ppc/ppc4xx devices
include/devicenorthbridge/amd/amdfam10
northbridge/amd/amdk8northbridge/amd/gx1 northbridge/amd/gx2
northbridge/amd/lxnorthbridge/ibm/cpc710 north

Author: myles
Date: 2009-07-02 20:56:24 +0200 (Thu, 02 Jul 2009)
New Revision: 4394

Modified:
   trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c
   trunk/coreboot-v2/src/devices/cardbus_device.c
   trunk/coreboot-v2/src/devices/device.c
   trunk/coreboot-v2/src/devices/device_util.c
   trunk/coreboot-v2/src/devices/pci_device.c
   trunk/coreboot-v2/src/devices/root_device.c
   trunk/coreboot-v2/src/include/device/device.h
   trunk/coreboot-v2/src/include/device/resource.h
   trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c
   trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c
   trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
 
trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c
   trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
   trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
   trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c
   trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c
   trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c
   trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c
   trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
   trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
 
trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
   trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
   trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c
   trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
   trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c
   trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c
   trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
Log:
Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the
placement
of other resources.  All fixed resources will end up outside (above or
below) 
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of
0xfec00000 is
still there for resources.  Some platforms may want to change that, but
I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for
I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c	2009-07-02 18:27:02 UTC
(rev 4393)
+++ trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c	2009-07-02 18:56:24 UTC
(rev 4394)
@@ -62,9 +62,27 @@
 
 }
 
+static void sc520_read_resources(device_t dev)
+{
+	struct resource* res;
 
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+}
+
+
 static struct device_operations cpu_operations = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources   = sc520_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = sc520_enable_resources,
 	.init             = cpu_init,
@@ -78,25 +96,6 @@
 	.device = 0x3000
 };
 
-
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-  printk_spew("%s\n", __func__);
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -184,14 +183,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-  printk_spew("%s\n", __func__);
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
-
 #if 0
 void sc520_enable_resources(device_t dev) {
 
@@ -219,7 +210,7 @@
 	 * If enable_resources is set to the generic enable_resources
 	 * function the whole thing will hang in an endless loop on
 	 * the ts5300. If this is really needed on another platform,
-	 * something is conceptionally wrong.
+	 * something is conceptually wrong.
 	 */
         .enable_resources = 0, //enable_resources,
         .init             = 0,

Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include "chip.h"
 #include "northbridge.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -70,7 +53,7 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void cpu_pci_domain_set_resources(device_t dev)
 {
 	static const uint8_t ramregs[] = {
 		0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
@@ -127,15 +110,34 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static void cpu_pci_domain_read_resources(struct device *dev)
 {
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
+	struct resource *res;
+
+	pci_domain_read_resources(dev);
+
+	/* Reserve space for the IOAPIC.  This should be in the
Southbridge,
+	 * but I couldn't tell which device to put it in. */
+	res = new_resource(dev, 2);
+	res->base = 0xfec00000UL;
+	res->size = 0x100000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
+
+	/* Reserve space for the LAPIC.  There's one in every processor,
but
+	 * the space only needs to be reserved once, so we do it here.
*/
+	res = new_resource(dev, 3);
+	res->base = 0xfee00000UL;
+	res->size = 0x10000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources		= pci_domain_read_resources,
-	.set_resources		= pci_domain_set_resources,
+	.read_resources		= cpu_pci_domain_read_resources,
+	.set_resources		= cpu_pci_domain_set_resources,
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c	2009-07-02
18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c	2009-07-02
18:56:24 UTC (rev 4394)
@@ -7,27 +7,6 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {

Modified: trunk/coreboot-v2/src/devices/cardbus_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/cardbus_device.c	2009-07-02
18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/devices/cardbus_device.c	2009-07-02
18:56:24 UTC (rev 4394)
@@ -77,8 +77,6 @@
 	resource = find_resource(dev, index);
 	if (resource) {
 		min_size = resource->size;
-		compute_allocate_resource(&dev->link[0], resource, 
-			resource->flags, resource->flags);
 		/* Allways allocate at least the miniumum size to a
 		 * cardbus bridge in case a new card is plugged in.
 		 */

Modified: trunk/coreboot-v2/src/devices/device.c
===================================================================
--- trunk/coreboot-v2/src/devices/device.c	2009-07-02 18:27:02 UTC
(rev 4393)
+++ trunk/coreboot-v2/src/devices/device.c	2009-07-02 18:56:24 UTC
(rev 4394)
@@ -12,6 +12,7 @@
  * Copyright (C) 2005-2006 Tyan
  * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
  * Copyright (C) 2005-2006 Stefan Reinauer <stepan at openbios.org>
+ * Copyright (C) 2009 Myles Watson <mylesgw at gmail.com>
  */
 
 /*
@@ -43,12 +44,6 @@
 /** Pointer to the last device */
 extern struct device **last_dev_p;
 
-/** The upper limit of MEM resource of the devices.
- * Reserve 20M for the system */
-#define DEVICE_MEM_HIGH 0xFEBFFFFFUL
-/** The lower limit of IO resource of the devices.
- * Reserve 4k for ISA/Legacy devices */
-#define DEVICE_IO_START 0x1000
 
 /**
  * @brief Allocate a new device structure.
@@ -71,25 +66,25 @@
 
 	spin_lock(&dev_lock);
 
-	/* Find the last child of our parent */
-	for(child = parent->children; child && child->sibling; ) {
+	/* Find the last child of our parent. */
+	for (child = parent->children; child && child->sibling; /* */ )
{
 		child = child->sibling;
 	}
 
 	dev = malloc(sizeof(*dev));
-	if (dev == 0) {
+	if (dev == 0)
 		die("DEV: out of memory.\n");
-	}
+
 	memset(dev, 0, sizeof(*dev));
 	memcpy(&dev->path, path, sizeof(*path));
 
-	/* Initialize the back pointers in the link fields */
-	for(link = 0; link < MAX_LINKS; link++) {
-		dev->link[link].dev  = dev;
+	/* Initialize the back pointers in the link fields. */
+	for (link = 0; link < MAX_LINKS; link++) {
+		dev->link[link].dev = dev;
 		dev->link[link].link = link;
 	}
 
-	/* By default devices are enabled */
+	/* By default devices are enabled. */
 	dev->enabled = 1;
 
 	/* Add the new device to the list of children of the bus. */
@@ -132,64 +127,46 @@
 {
 	struct device *curdev;
 
-	printk_spew("%s read_resources bus %d link: %d\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+	printk_spew("%s %s bus %x link: %d\n", dev_path(bus->dev),
__func__,
+		    bus->secondary, bus->link);
 
-	/* Walk through all of the devices and find which resources they
need. */
-	for(curdev = bus->children; curdev; curdev = curdev->sibling) {
-		unsigned links;
+	/* Walk through all devices and find which resources they need.
*/
+	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
 		int i;
-		if (curdev->have_resources) {
-			continue;
-		}
 		if (!curdev->enabled) {
 			continue;
 		}
 		if (!curdev->ops || !curdev->ops->read_resources) {
 			printk_err("%s missing read_resources\n",
-				dev_path(curdev));
+				   dev_path(curdev));
 			continue;
 		}
 		curdev->ops->read_resources(curdev);
-		curdev->have_resources = 1;
-		/* Read in subtractive resources behind the current
device */
-		links = 0;
-		for(i = 0; i < curdev->resources; i++) {
-			struct resource *resource;
-			unsigned link;
-			resource = &curdev->resource[i];
-			if (!(resource->flags & IORESOURCE_SUBTRACTIVE))
-				continue;
-			link =
IOINDEX_SUBTRACTIVE_LINK(resource->index);
-			if (link > MAX_LINKS) {
-				printk_err("%s subtractive index on
link: %d\n",
-					dev_path(curdev), link);
-				continue;
-			}
-			if (!(links & (1 << link))) {
-				links |= (1 << link);
-				read_resources(&curdev->link[link]);
-			}
-		}
+
+		/* Read in the resources behind the current device's
links. */
+		for (i = 0; i < curdev->links; i++)
+			read_resources(&curdev->link[i]);
 	}
 	printk_spew("%s read_resources bus %d link: %d done\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+		    dev_path(bus->dev), bus->secondary, bus->link);
 }
 
 struct pick_largest_state {
 	struct resource *last;
-	struct device   *result_dev;
+	struct device *result_dev;
 	struct resource *result;
 	int seen_last;
 };
 
-static void pick_largest_resource(void *gp,
-	struct device *dev, struct resource *resource)
+static void pick_largest_resource(void *gp, struct device *dev,
+				  struct resource *resource)
 {
 	struct pick_largest_state *state = gp;
 	struct resource *last;
+
 	last = state->last;
-	/* Be certain to pick the successor to last */
+
+	/* Be certain to pick the successor to last. */
 	if (resource == last) {
 		state->seen_last = 1;
 		return;
@@ -206,21 +183,22 @@
 	if (!state->result ||
 	    (state->result->align < resource->align) ||
 	    ((state->result->align == resource->align) &&
-	     (state->result->size < resource->size)))
-	{
+	     (state->result->size < resource->size))) {
 		state->result_dev = dev;
 		state->result = resource;
 	}
 }
 
-static struct device *largest_resource(struct bus *bus, struct resource
**result_res,
-	unsigned long type_mask, unsigned long type)
+static struct device *largest_resource(struct bus *bus,
+				       struct resource **result_res,
+				       unsigned long type_mask,
+				       unsigned long type)
 {
 	struct pick_largest_state state;
 
 	state.last = *result_res;
-	state.result_dev = 0;
-	state.result = 0;
+	state.result_dev = NULL;
+	state.result = NULL;
 	state.seen_last = 0;
 
 	search_bus_resources(bus, type_mask, type,
pick_largest_resource,
@@ -233,144 +211,136 @@
 /* Compute allocate resources is the guts of the resource allocator.
  *
  * The problem.
- *  - Allocate resources locations for every device.
+ *  - Allocate resource locations for every device.
  *  - Don't overlap, and follow the rules of bridges.
  *  - Don't overlap with resources in fixed locations.
  *  - Be efficient so we don't have ugly strategies.
  *
  * The strategy.
  * - Devices that have fixed addresses are the minority so don't
- *   worry about them too much.  Instead only use part of the address
- *   space for devices with programmable addresses.  This easily
handles
+ *   worry about them too much. Instead only use part of the address
+ *   space for devices with programmable addresses. This easily handles
  *   everything except bridges.
  *
- * - PCI devices are required to have thier sizes and their alignments
- *   equal.  In this case an optimal solution to the packing problem
- *   exists.  Allocate all devices from highest alignment to least
- *   alignment or vice versa.  Use this.
+ * - PCI devices are required to have their sizes and their alignments
+ *   equal. In this case an optimal solution to the packing problem
+ *   exists. Allocate all devices from highest alignment to least
+ *   alignment or vice versa. Use this.
  *
- * - So we can handle more than PCI run two allocation passes on
- *   bridges.  The first to see how large the resources are behind
- *   the bridge, and what their alignment requirements are.  The
- *   second to assign a safe address to the devices behind the
- *   bridge.  This allows me to treat a bridge as just a device with
- *   a couple of resources, and not need to special case it in the
- *   allocator.  Also this allows handling of other types of bridges.
+ * - So we can handle more than PCI run two allocation passes on
bridges. The
+ *   first to see how large the resources are behind the bridge, and
what
+ *   their alignment requirements are. The second to assign a safe
address to
+ *   the devices behind the bridge. This allows us to treat a bridge as
just
+ *   a device with a couple of resources, and not need to special case
it in
+ *   the allocator. Also this allows handling of other types of
bridges.
  *
  */
-
-void compute_allocate_resource(
-	struct bus *bus,
-	struct resource *bridge,
-	unsigned long type_mask,
-	unsigned long type)
+void compute_resources(struct bus *bus, struct resource *bridge,
+		       unsigned long type_mask, unsigned long type)
 {
 	struct device *dev;
 	struct resource *resource;
 	resource_t base;
-	unsigned long align, min_align;
-	min_align = 0;
-	base = bridge->base;
+	base = round(bridge->base, bridge->align);
 
-	printk_spew("%s compute_allocate_resource %s: base: %08Lx size:
%08Lx align: %d gran: %d\n",
-		dev_path(bus->dev),
-		(bridge->flags & IORESOURCE_IO)? "io":
-		(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" :
"mem",
-		base, bridge->size, bridge->align, bridge->gran);
+	printk_spew( "%s %s_%s: base: %llx size: %llx align: %d gran: %d
limit: %llx\n",
+	       dev_path(bus->dev), __func__,
+	       (type & IORESOURCE_IO) ? "io" : (type &
IORESOURCE_PREFETCH) ?
+	       "prefmem" : "mem",
+	       base, bridge->size, bridge->align, bridge->gran,
bridge->limit);
 
-	/* We want different minimum alignments for different kinds of
-	 * resources.  These minimums are not device type specific
-	 * but resource type specific.
-	 */
-	if (bridge->flags & IORESOURCE_IO) {
-		min_align = log2(DEVICE_IO_ALIGN);
-	}
-	if (bridge->flags & IORESOURCE_MEM) {
-		min_align = log2(DEVICE_MEM_ALIGN);
-	}
+	/* For each child which is a bridge, compute_resource_needs. */
+	for (dev = bus->children; dev; dev = dev->sibling) {
+		unsigned i;
+		struct resource *child_bridge;
 
-	/* Make certain I have read in all of the resources */
-	read_resources(bus);
+		if (!dev->links)
+			continue;
 
-	/* Remember I haven't found anything yet. */
-	resource = 0;
+		/* Find the resources with matching type flags. */
+		for (i = 0; i < dev->resources; i++) {
+			unsigned link;
+			child_bridge = &dev->resource[i];
 
-	/* Walk through all the devices on the current bus and
-	 * compute the addresses.
-	 */
-	while((dev = largest_resource(bus, &resource, type_mask, type)))
{
-		resource_t size;
-		/* Do NOT I repeat do not ignore resources which have
zero size.
-		 * If they need to be ignored dev->read_resources should
not even
-		 * return them.   Some resources must be set even when
they have
-		 * no size.  PCI bridge resources are a good example of
this.
-		 */
-		/* Make certain we are dealing with a good minimum size
*/
-		size = resource->size;
-		align = resource->align;
-		if (align < min_align) {
-			align = min_align;
-		}
+			if (!(child_bridge->flags & IORESOURCE_BRIDGE)
||
+			    (child_bridge->flags & type_mask) != type)
+				continue;
 
-		/* Propagate the resource alignment to the bridge
register  */
-		if (align > bridge->align) {
-			bridge->align = align;
+			/* Split prefetchable memory if combined.  Many
domains
+			 * use the same address space for prefetchable
memory
+			 * and non-prefetchable memory.  Bridges below
them
+			 * need it separated.  Add the PREFETCH flag to
the
+			 * type_mask and type.
+			 */
+			link = IOINDEX_LINK(child_bridge->index);
+			compute_resources(&dev->link[link],
child_bridge,
+					  type_mask |
IORESOURCE_PREFETCH,
+					  type | (child_bridge->flags &
+						  IORESOURCE_PREFETCH));
 		}
+	}
 
-		if (resource->flags & IORESOURCE_FIXED) {
+	/* Remember we haven't found anything yet. */
+	resource = NULL;
+
+	/* Walk through all the resources on the current bus and compute
the
+	 * amount of address space taken by them.  Take granularity and
+	 * alignment into account.
+	 */
+	while ((dev = largest_resource(bus, &resource, type_mask,
type))) {
+
+		/* Size 0 resources can be skipped. */
+		if (!resource->size) {
 			continue;
 		}
 
-		/* Propogate the resource limit to the bridge register
*/
+		/* Propagate the resource alignment to the bridge
resource. */
+		if (resource->align > bridge->align) {
+			bridge->align = resource->align;
+		}
+
+		/* Propagate the resource limit to the bridge register.
*/
 		if (bridge->limit > resource->limit) {
 			bridge->limit = resource->limit;
 		}
-#warning This heuristic should be replaced by real devices with fixed
resources.
-		/* Artificially deny limits between DEVICE_MEM_HIGH and
0xffffffff */
-		if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit
<= 0xffffffff)) {
-			bridge->limit = DEVICE_MEM_HIGH;
+
+		/* Warn if it looks like APICs aren't declared. */
+		if ((resource->limit == 0xffffffff) &&
+		    (resource->flags & IORESOURCE_ASSIGNED)) {
+			printk_err("Resource limit looks wrong! (no
APIC?)\n");
+			printk_err("%s %02lx limit %08Lx\n",
dev_path(dev),
+			           resource->index, resource->limit);
 		}
 
 		if (resource->flags & IORESOURCE_IO) {
-			/* Don't allow potential aliases over the
-			 * legacy pci expansion card addresses.
-			 * The legacy pci decodes only 10 bits,
-			 * uses 100h - 3ffh. Therefor, only 0 - ff
-			 * can be used out of each 400h block of io
-			 * space.
+			/* Don't allow potential aliases over the legacy
PCI
+			 * expansion card addresses. The legacy PCI
decodes
+			 * only 10 bits, uses 0x100 - 0x3ff. Therefore,
only
+			 * 0x00 - 0xff can be used out of each 0x400
block of
+			 * I/O space.
 			 */
 			if ((base & 0x300) != 0) {
 				base = (base & ~0x3ff) + 0x400;
 			}
-			/* Don't allow allocations in the VGA IO range.
+			/* Don't allow allocations in the VGA I/O range.
 			 * PCI has special cases for that.
 			 */
 			else if ((base >= 0x3b0) && (base <= 0x3df)) {
 				base = 0x3e0;
 			}
 		}
-		if (((round(base, align) + size) -1) <= resource->limit)
{
-			/* base must be aligned to size */
-			base = round(base, align);
-			resource->base = base;
-			resource->flags |= IORESOURCE_ASSIGNED;
-			resource->flags &= ~IORESOURCE_STORED;
-			base += size;
+		/* Base must be aligned. */
+		base = round(base, resource->align);
+		resource->base = base;
+		base += resource->size;
 
-			printk_spew("%s %02lx *  [0x%08Lx - 0x%08Lx]
%s\n",
-				dev_path(dev),
-				resource->index,
-				resource->base,
-				resource->base + resource->size - 1,
-				(resource->flags & IORESOURCE_IO)? "io":
-				(resource->flags & IORESOURCE_PREFETCH)?
"prefmem": "mem");
-		}
-#if CONFIG_PCIE_CONFIGSPACE_HOLE
-#warning Handle PCIe hole differently...
-		if (base >= 0xf0000000 && base < 0xf4000000) {
-			base = 0xf4000000;
-		}
-#endif
+		printk_spew("%s %02lx *  [0x%llx - 0x%llx] %s\n",
+			    dev_path(dev), resource->index,
+			    resource->base,
+			    resource->base + resource->size - 1,
+			    (resource->flags & IORESOURCE_IO) ? "io" :
+			    (resource->flags & IORESOURCE_PREFETCH) ?
+			     "prefmem" : "mem");
 	}
 	/* A pci bridge resource does not need to be a power
 	 * of two size, but it does have a minimum granularity.
@@ -378,23 +348,327 @@
 	 * know not to place something else at an address postitively
 	 * decoded by the bridge.
 	 */
-	bridge->size = round(base, bridge->gran) - bridge->base;
+	bridge->size = round(base, bridge->gran) -
+		       round(bridge->base, bridge->align);
 
-	printk_spew("%s compute_allocate_resource %s: base: %08Lx size:
%08Lx align: %d gran: %d done\n",
-		    dev_path(bus->dev),
-		    (bridge->flags & IORESOURCE_IO)? "io":
-		     (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" :
"mem",
-		    base, bridge->size, bridge->align, bridge->gran);
+	printk_spew("%s %s_%s: base: %llx size: %llx align: %d gran: %d
limit: %llx done\n",
+		    dev_path(bus->dev), __func__,
+		    (bridge->flags & IORESOURCE_IO) ? "io" :
+		     (bridge->flags & IORESOURCE_PREFETCH) ?  "prefmem"
: "mem",
+		    base, bridge->size, bridge->align, bridge->gran,
bridge->limit);
 }
 
+/**
+ * This function is the second part of the resource allocator.
+ *
+ * The problem.
+ *  - Allocate resource locations for every device.
+ *  - Don't overlap, and follow the rules of bridges.
+ *  - Don't overlap with resources in fixed locations.
+ *  - Be efficient so we don't have ugly strategies.
+ *
+ * The strategy.
+ * - Devices that have fixed addresses are the minority so don't
+ *   worry about them too much. Instead only use part of the address
+ *   space for devices with programmable addresses. This easily handles
+ *   everything except bridges.
+ *
+ * - PCI devices are required to have their sizes and their alignments
+ *   equal. In this case an optimal solution to the packing problem
+ *   exists. Allocate all devices from highest alignment to least
+ *   alignment or vice versa. Use this.
+ *
+ * - So we can handle more than PCI run two allocation passes on
bridges. The
+ *   first to see how large the resources are behind the bridge, and
what
+ *   their alignment requirements are. The second to assign a safe
address to
+ *   the devices behind the bridge. This allows us to treat a bridge as
just
+ *   a device with a couple of resources, and not need to special case
it in
+ *   the allocator. Also this allows handling of other types of
bridges.
+ *
+ * - This function assigns the resources a value.
+ *
+ * @param bus The bus we are traversing.
+ * @param bridge The bridge resource which must contain the bus'
resources.
+ * @param type_mask This value gets anded with the resource type.
+ * @param type This value must match the result of the and.
+ */
+void allocate_resources(struct bus *bus, struct resource *bridge,
+			unsigned long type_mask, unsigned long type)
+{
+	struct device *dev;
+	struct resource *resource;
+	resource_t base;
+	base = bridge->base;
+
+	printk_spew("%s %s_%s: base:%llx size:%llx align:%d gran:%d
limit:%llx\n",
+	       dev_path(bus->dev), __func__,
+	       (type & IORESOURCE_IO) ? "io" : (type &
IORESOURCE_PREFETCH) ?
+	       "prefmem" : "mem",
+	       base, bridge->size, bridge->align, bridge->gran,
bridge->limit);
+
+	/* Remember we haven't found anything yet. */
+	resource = NULL;
+
+	/* Walk through all the resources on the current bus and
allocate them
+	 * address space.
+	 */
+	while ((dev = largest_resource(bus, &resource, type_mask,
type))) {
+
+		/* Propagate the bridge limit to the resource register.
*/
+		if (resource->limit > bridge->limit) {
+			resource->limit = bridge->limit;
+		}
+
+		/* Size 0 resources can be skipped. */
+		if (!resource->size) {
+			/* Set the base to limit so it doesn't confuse
tolm. */
+			resource->base = resource->limit;
+			resource->flags |= IORESOURCE_ASSIGNED;
+			continue;
+		}
+
+		if (resource->flags & IORESOURCE_IO) {
+			/* Don't allow potential aliases over the legacy
PCI
+			 * expansion card addresses. The legacy PCI
decodes
+			 * only 10 bits, uses 0x100 - 0x3ff. Therefore,
only
+			 * 0x00 - 0xff can be used out of each 0x400
block of
+			 * I/O space.
+			 */
+			if ((base & 0x300) != 0) {
+				base = (base & ~0x3ff) + 0x400;
+			}
+			/* Don't allow allocations in the VGA I/O range.
+			 * PCI has special cases for that.
+			 */
+			else if ((base >= 0x3b0) && (base <= 0x3df)) {
+				base = 0x3e0;
+			}
+		}
+
+		if ((round(base, resource->align) + resource->size - 1)
<=
+		    resource->limit) {
+			/* Base must be aligned. */
+			base = round(base, resource->align);
+			resource->base = base;
+			resource->flags |= IORESOURCE_ASSIGNED;
+			resource->flags &= ~IORESOURCE_STORED;
+			base += resource->size;
+		} else {
+			printk_err("!! Resource didn't fit !!\n");
+			printk_err("   aligned base %llx size %llx limit
%llx\n",
+			       round(base, resource->align),
resource->size,
+			       resource->limit);
+			printk_err("   %llx needs to be <= %llx
(limit)\n",
+			       (round(base, resource->align) +
+				resource->size) - 1, resource->limit);
+			printk_err("   %s%s %02lx *  [0x%llx - 0x%llx]
%s\n",
+			       (resource->
+				flags & IORESOURCE_ASSIGNED) ?
"Assigned: " :
+			       "", dev_path(dev), resource->index,
+			       resource->base,
+			       resource->base + resource->size - 1,
+			       (resource->
+				flags & IORESOURCE_IO) ? "io" :
(resource->
+								 flags &
+
IORESOURCE_PREFETCH)
+			       ? "prefmem" : "mem");
+		}
+
+		printk_spew("%s%s %02lx *  [0x%llx - 0x%llx] %s\n",
+		       (resource->flags & IORESOURCE_ASSIGNED) ?
"Assigned: "
+		       : "",
+		       dev_path(dev), resource->index, resource->base,
+		       resource->size ? resource->base + resource->size
- 1 :
+		       resource->base,
+		       (resource->flags & IORESOURCE_IO) ? "io" :
+		       (resource->flags & IORESOURCE_PREFETCH) ?
"prefmem" :
+		       "mem");
+	}
+	/* A PCI bridge resource does not need to be a power of two
size, but
+	 * it does have a minimum granularity. Round the size up to that
+	 * minimum granularity so we know not to place something else at
an
+	 * address positively decoded by the bridge.
+	 */
+
+	bridge->flags |= IORESOURCE_ASSIGNED;
+
+	printk_spew("%s %s_%s: next_base: %llx size: %llx align: %d
gran: %d done\n",
+	       dev_path(bus->dev), __func__,
+	       (type & IORESOURCE_IO) ? "io" : (type &
IORESOURCE_PREFETCH) ?
+	       "prefmem" : "mem",
+	       base, bridge->size, bridge->align, bridge->gran);
+
+	/* For each child which is a bridge, allocate_resources. */
+	for (dev = bus->children; dev; dev = dev->sibling) {
+		unsigned i;
+		struct resource *child_bridge;
+
+		if (!dev->links)
+			continue;
+
+		/* Find the resources with matching type flags. */
+		for (i = 0; i < dev->resources; i++) {
+			unsigned link;
+			child_bridge = &dev->resource[i];
+
+			if (!(child_bridge->flags & IORESOURCE_BRIDGE)
||
+			    (child_bridge->flags & type_mask) != type)
+				continue;
+
+			/* Split prefetchable memory if combined.  Many
domains
+			 * use the same address space for prefetchable
memory
+			 * and non-prefetchable memory.  Bridges below
them
+			 * need it separated.  Add the PREFETCH flag to
the
+			 * type_mask and type.
+			 */
+			link = IOINDEX_LINK(child_bridge->index);
+			allocate_resources(&dev->link[link],
child_bridge,
+					   type_mask |
IORESOURCE_PREFETCH,
+					   type | (child_bridge->flags &
+
IORESOURCE_PREFETCH));
+		}
+	}
+}
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+	#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
+#else
+	#define MEM_MASK (IORESOURCE_MEM)
+#endif
+#define IO_MASK (IORESOURCE_IO)
+#define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM)
+#define MEM_TYPE (IORESOURCE_MEM)
+#define IO_TYPE (IORESOURCE_IO)
+
+struct constraints {
+	struct resource pref, io, mem;
+};
+
+static void constrain_resources(struct device *dev, struct constraints*
limits)
+{
+	struct device *child;
+	struct resource *res;
+	struct resource *lim;
+	int i;
+
+	printk_spew("%s: %s\n", __func__, dev_path(dev));
+
+	/* Constrain limits based on the fixed resources of this device.
*/
+	for (i = 0; i < dev->resources; i++) {
+		res = &dev->resource[i];
+		if (!(res->flags & IORESOURCE_FIXED))
+			continue;
+
+		/* PREFETCH, MEM, or I/O - skip any others. */
+		if ((res->flags & MEM_MASK) == PREF_TYPE)
+			lim = &limits->pref;
+		else if ((res->flags & MEM_MASK) == MEM_TYPE)
+			lim = &limits->mem;
+		else if ((res->flags & IO_MASK) == IO_TYPE)
+			lim = &limits->io;
+		else
+			continue;
+
+		/* Is it already outside the limits? */
+		if (res->size && (((res->base + res->size -1) <
lim->base) ||
+				  (res->base > lim->limit)))
+			continue;
+
+		/* Choose to be above or below fixed resources.  This
+		 * check is signed so that "negative" amounts of space
+		 * are handled correctly.
+		 */
+		if ((signed long long)(lim->limit - (res->base +
res->size -1)) >
+		    (signed long long)(res->base - lim->base))
+			lim->base = res->base + res->size;
+		else
+			lim->limit = res->base -1;
+	}
+
+	/* Descend into every enabled child and look for fixed
resources. */
+	for (i = 0; i < dev->links; i++)
+		for (child = dev->link[i].children; child;
+		     child = child->sibling)
+			if (child->enabled)
+				constrain_resources(child, limits);
+}
+
+static void avoid_fixed_resources(struct device *dev)
+{
+	struct constraints limits;
+	struct resource *res;
+	int i;
+
+	printk_spew("%s: %s\n", __func__, dev_path(dev));
+	/* Initialize constraints to maximum size. */
+
+	limits.pref.base = 0;
+	limits.pref.limit = 0xffffffffffffffffULL;
+	limits.io.base = 0;
+	limits.io.limit = 0xffffffffffffffffULL;
+	limits.mem.base = 0;
+	limits.mem.limit = 0xffffffffffffffffULL;
+
+	/* Constrain the limits to dev's initial resources. */
+	for (i = 0; i < dev->resources; i++) {
+		res = &dev->resource[i];
+		if ((res->flags & IORESOURCE_FIXED))
+			continue;
+		printk_spew("%s:@%s %02lx limit %08Lx\n", __func__,
+			     dev_path(dev), res->index, res->limit);
+		if ((res->flags & MEM_MASK) == PREF_TYPE &&
+		    (res->limit < limits.pref.limit))
+			limits.pref.limit = res->limit;
+		if ((res->flags & MEM_MASK) == MEM_TYPE &&
+		    (res->limit < limits.mem.limit))
+			limits.mem.limit = res->limit;
+		if ((res->flags & IO_MASK) == IO_TYPE &&
+		    (res->limit < limits.io.limit))
+			limits.io.limit = res->limit;
+	}
+
+	/* Look through the tree for fixed resources and update the
limits. */
+	constrain_resources(dev, &limits);
+
+	/* Update dev's resources with new limits. */
+	for (i = 0; i < dev->resources; i++) {
+		struct resource *lim;
+		res = &dev->resource[i];
+
+		if ((res->flags & IORESOURCE_FIXED))
+			continue;
+
+		/* PREFETCH, MEM, or I/O - skip any others. */
+		if ((res->flags & MEM_MASK) == PREF_TYPE)
+			lim = &limits.pref;
+		else if ((res->flags & MEM_MASK) == MEM_TYPE)
+			lim = &limits.mem;
+		else if ((res->flags & IO_MASK) == IO_TYPE)
+			lim = &limits.io;
+		else
+			continue;
+
+		printk_spew("%s2: %s@%02lx limit %08Lx\n", __func__,
+			     dev_path(dev), res->index, res->limit);
+		printk_spew("\tlim->base %08Lx lim->limit %08Lx\n",
+			     lim->base, lim->limit);
+
+		/* Is the resource outside the limits? */
+		if (lim->base > res->base)
+			res->base = lim->base;
+		if (res->limit > lim->limit)
+			res->limit = lim->limit;
+	}
+}
+
 #if CONFIG_CONSOLE_VGA == 1
 device_t vga_pri = 0;
 static void allocate_vga_resource(void)
 {
 #warning "FIXME modify allocate_vga_resource so it is less pci
centric!"
-#warning "This function knows to much about PCI stuff, it should be
just a ietrator/visitor."
+#warning "This function knows too much about PCI stuff, it should be
just a iterator/visitor."
 
-	/* FIXME handle the VGA pallette snooping */
+	/* FIXME: Handle the VGA palette snooping. */
 	struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last;
 	struct bus *bus;
 	bus = 0;
@@ -402,66 +676,63 @@
 	vga_onboard = 0;
 	vga_first = 0;
 	vga_last = 0;
-	for(dev = all_devices; dev; dev = dev->next) {
-		if (!dev->enabled) continue;
+	for (dev = all_devices; dev; dev = dev->next) {
+		if (!dev->enabled)
+			continue;
 		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
-			((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER))
-		{
-                        if (!vga_first) {
-                                if (dev->on_mainboard) {
-                                        vga_onboard = dev;
-                                } else {
-                                        vga_first = dev;
-                                }
-                        } else {
-                                if (dev->on_mainboard) {
-                                        vga_onboard = dev;
-                                } else {
-                                        vga_last = dev;
-                                }
-                        }
+		    ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
+			if (!vga_first) {
+				if (dev->on_mainboard) {
+					vga_onboard = dev;
+				} else {
+					vga_first = dev;
+				}
+			} else {
+				if (dev->on_mainboard) {
+					vga_onboard = dev;
+				} else {
+					vga_last = dev;
+				}
+			}
 
-			/* It isn't safe to enable other VGA cards */
+			/* It isn't safe to enable other VGA cards. */
 			dev->command &= ~(PCI_COMMAND_MEMORY |
PCI_COMMAND_IO);
 		}
 	}
 
-        vga = vga_last;
+	vga = vga_last;
 
-        if(!vga) {
-                vga = vga_first;
-        }
-
+	if (!vga) {
+		vga = vga_first;
+	}
 #if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1
-        if (vga_onboard) // will use on board vga as pri
+	if (vga_onboard)	// Will use on board VGA as pri.
 #else
-        if (!vga) // will use last add on adapter as pri
+	if (!vga)		// Will use last add on adapter as pri.
 #endif
-        {
-                vga = vga_onboard;
-        }
+	{
+		vga = vga_onboard;
+	}
 
-
 	if (vga) {
-		/* vga is first add on card or the only onboard vga */
+		/* VGA is first add on card or the only onboard VGA. */
 		printk_debug("Allocating VGA resource %s\n",
dev_path(vga));
-		/* All legacy VGA cards have MEM & I/O space registers
*/
+		/* All legacy VGA cards have MEM & I/O space registers.
*/
 		vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		vga_pri = vga;
 		bus = vga->bus;
 	}
-	/* Now walk up the bridges setting the VGA enable */
-	while(bus) {
+	/* Now walk up the bridges setting the VGA enable. */
+	while (bus) {
 		printk_debug("Setting PCI_BRIDGE_CTL_VGA for bridge
%s\n",
 			     dev_path(bus->dev));
 		bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
-		bus = (bus == bus->dev->bus)? 0 : bus->dev->bus;
+		bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
 	}
 }
 
 #endif
 
-
 /**
  * @brief  Assign the computed resources to the devices on the bus.
  *
@@ -480,21 +751,21 @@
 	struct device *curdev;
 
 	printk_spew("%s assign_resources, bus %d link: %d\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+		    dev_path(bus->dev), bus->secondary, bus->link);
 
-	for(curdev = bus->children; curdev; curdev = curdev->sibling) {
+	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
 		if (!curdev->enabled || !curdev->resources) {
 			continue;
 		}
 		if (!curdev->ops || !curdev->ops->set_resources) {
 			printk_err("%s missing set_resources\n",
-				dev_path(curdev));
+				   dev_path(curdev));
 			continue;
 		}
 		curdev->ops->set_resources(curdev);
 	}
 	printk_spew("%s assign_resources, bus %d link: %d\n",
-		dev_path(bus->dev), bus->secondary, bus->link);
+		    dev_path(bus->dev), bus->secondary, bus->link);
 }
 
 /**
@@ -539,8 +810,7 @@
  */
 int reset_bus(struct bus *bus)
 {
-	if (bus && bus->dev && bus->dev->ops &&
bus->dev->ops->reset_bus)
-	{
+	if (bus && bus->dev && bus->dev->ops &&
bus->dev->ops->reset_bus) {
 		bus->dev->ops->reset_bus(bus);
 		bus->reset_needed = 0;
 		return 1;
@@ -551,37 +821,34 @@
 /**
  * @brief Scan for devices on a bus.
  *
- * If there are bridges on the bus, recursively scan the buses behind
the bridges.
- * If the setting up and tuning of the bus causes a reset to be
required,
- * reset the bus and scan it again.
+ * If there are bridges on the bus, recursively scan the buses behind
the
+ * bridges. If the setting up and tuning of the bus causes a reset to
be
+ * required, reset the bus and scan it again.
  *
- * @param bus pointer to the bus device
- * @param max current bus number
- *
- * @return The maximum bus number found, after scanning all subordinate
busses
+ * @param busdev Pointer to the bus device.
+ * @param max Current bus number.
+ * @return The maximum bus number found, after scanning all subordinate
buses.
  */
-unsigned int scan_bus(device_t bus, unsigned int max)
+unsigned int scan_bus(struct device *busdev, unsigned int max)
 {
 	unsigned int new_max;
 	int do_scan_bus;
-	if (	!bus ||
-		!bus->enabled ||
-		!bus->ops ||
-		!bus->ops->scan_bus)
-	{
+	if (!busdev || !busdev->enabled || !busdev->ops ||
+	    !busdev->ops->scan_bus) {
 		return max;
 	}
+
 	do_scan_bus = 1;
-	while(do_scan_bus) {
+	while (do_scan_bus) {
 		int link;
-		new_max = bus->ops->scan_bus(bus, max);
+		new_max = busdev->ops->scan_bus(busdev, max);
 		do_scan_bus = 0;
-		for(link = 0; link < bus->links; link++) {
-			if (bus->link[link].reset_needed) {
-				if (reset_bus(&bus->link[link])) {
+		for (link = 0; link < busdev->links; link++) {
+			if (busdev->link[link].reset_needed) {
+				if (reset_bus(&busdev->link[link])) {
 					do_scan_bus = 1;
 				} else {
-					bus->bus->reset_needed = 1;
+					busdev->bus->reset_needed = 1;
 				}
 			}
 		}
@@ -589,7 +856,6 @@
 	return new_max;
 }
 
-
 /**
  * @brief Determine the existence of devices and extend the device
tree.
  *
@@ -619,7 +885,7 @@
 	printk_info("Enumerating buses...\n");
 	root = &dev_root;
 
-	show_all_devs(BIOS_DEBUG, "Before Phase 3.");
+	show_all_devs(BIOS_DEBUG, "Before Device Enumeration.");
 	printk_debug("Compare with tree...\n");
 
 	show_devs_tree(root, BIOS_DEBUG, 0, 0);
@@ -643,66 +909,115 @@
  * requried by each device. In the second pass, the resources ranges
are
  * relocated to their final position and stored to the hardware.
  *
- * I/O resources start at DEVICE_IO_START and grow upward. MEM
resources start
- * at DEVICE_MEM_HIGH and grow downward.
+ * I/O resources grow upward. MEM resources grow downward.
  *
  * Since the assignment is hierarchical we set the values into the
dev_root
  * struct.
  */
 void dev_configure(void)
 {
-	struct resource *io, *mem;
+	struct resource *res;
 	struct device *root;
+	struct device *child;
+	int i;
 
 	printk_info("Allocating resources...\n");
 
 	root = &dev_root;
 
-	print_resource_tree(root, BIOS_DEBUG, "Original.");
+	/* Each domain should create resources which contain the entire
address
+	 * space for IO, MEM, and PREFMEM resources in the domain. The
+	 * allocation of device resources will be done from this address
space.
+	 */
 
-	if (!root->ops || !root->ops->read_resources) {
-		printk_err("dev_root missing read_resources\n");
-		return;
-	}
-	if (!root->ops || !root->ops->set_resources) {
-		printk_err("dev_root missing set_resources\n");
-		return;
-	}
+	/* Read the resources for the entire tree. */
 
 	printk_info("Reading resources...\n");
-	root->ops->read_resources(root);
+	read_resources(&root->link[0]);
 	printk_info("Done reading resources.\n");
 
 	print_resource_tree(root, BIOS_DEBUG, "After reading.");
 
-	/* Get the resources */
-	io  = &root->resource[0];
-	mem = &root->resource[1];
-	/* Make certain the io devices are allocated somewhere safe. */
-	io->base = DEVICE_IO_START;
-	io->flags |= IORESOURCE_ASSIGNED;
-	io->flags &= ~IORESOURCE_STORED;
-	/* Now reallocate the pci resources memory with the
-	 * highest addresses I can manage.
+	/* Compute resources for all domains. */
+	for (child = root->link[0].children; child; child =
child->sibling) {
+		if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
+			continue;
+		for (i = 0; i < child->resources; i++) {
+			res = &child->resource[i];
+			if (res->flags & IORESOURCE_FIXED)
+				continue;
+			if (res->flags & IORESOURCE_PREFETCH) {
+				compute_resources(&child->link[0],
+					       res, MEM_MASK,
PREF_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_MEM) {
+				compute_resources(&child->link[0],
+					       res, MEM_MASK, MEM_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_IO) {
+				compute_resources(&child->link[0],
+					       res, IO_MASK, IO_TYPE);
+				continue;
+			}
+		}
+	}
+
+	/* For all domains. */
+	for (child = root->link[0].children; child;
child=child->sibling)
+		if (child->path.type == DEVICE_PATH_PCI_DOMAIN)
+			avoid_fixed_resources(child);
+
+	/* Now we need to adjust the resources. MEM resources need to
start at
+	 * the highest address managable.
 	 */
-	mem->base = resource_max(&root->resource[1]);
-	mem->flags |= IORESOURCE_ASSIGNED;
-	mem->flags &= ~IORESOURCE_STORED;
+	for (child = root->link[0].children; child; child =
child->sibling) {
+		if (child->path.type != DEVICE_PATH_PCI_DOMAIN)
+			continue;
+		for (i = 0; i < child->resources; i++) {
+			res = &child->resource[i];
+			if (!(res->flags & IORESOURCE_MEM) ||
+			    res->flags & IORESOURCE_FIXED)
+				continue;
+			res->base = resource_max(res);
+		}
+	}
 
 #if CONFIG_CONSOLE_VGA == 1
-	/* Allocate the VGA I/O resource.. */
+	/* Allocate the VGA I/O resource. */
 	allocate_vga_resource();
 	print_resource_tree(root, BIOS_DEBUG, "After VGA.");
 #endif
 
 	/* Store the computed resource allocations into device registers
... */
 	printk_info("Setting resources...\n");
-	root->ops->set_resources(root);
+	for (child = root->link[0].children; child; child =
child->sibling) {
+		if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
+			continue;
+		for (i = 0; i < child->resources; i++) {
+			res = &child->resource[i];
+			if (res->flags & IORESOURCE_FIXED)
+				continue;
+			if (res->flags & IORESOURCE_PREFETCH) {
+				allocate_resources(&child->link[0],
+					       res, MEM_MASK,
PREF_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_MEM) {
+				allocate_resources(&child->link[0],
+					       res, MEM_MASK, MEM_TYPE);
+				continue;
+			}
+			if (res->flags & IORESOURCE_IO) {
+				allocate_resources(&child->link[0],
+					       res, IO_MASK, IO_TYPE);
+				continue;
+			}
+		}
+	}
+	assign_resources(&root->link[0]);
 	printk_info("Done setting resources.\n");
-#if 0
-	mem->flags |= IORESOURCE_STORED;
-	report_resource_stored(root, mem, "");
-#endif
 	print_resource_tree(root, BIOS_DEBUG, "After assigning
values.");
 
 	printk_info("Done allocating resources.\n");
@@ -736,13 +1051,13 @@
 	struct device *dev;
 
 	printk_info("Initializing devices...\n");
-	for(dev = all_devices; dev; dev = dev->next) {
+	for (dev = all_devices; dev; dev = dev->next) {
 		if (dev->enabled && !dev->initialized &&
-			dev->ops && dev->ops->init)
-		{
+		    dev->ops && dev->ops->init) {
 			if (dev->path.type == DEVICE_PATH_I2C) {
- 				printk_debug("smbus: %s[%d]->",
-					dev_path(dev->bus->dev),
dev->bus->link);
+				printk_debug("smbus: %s[%d]->",
+					     dev_path(dev->bus->dev),
+					     dev->bus->link);
 			}
 			printk_debug("%s init\n", dev_path(dev));
 			dev->initialized = 1;
@@ -752,4 +1067,3 @@
 	printk_info("Devices initialized\n");
 	show_all_devs(BIOS_DEBUG, "After init.");
 }
-

Modified: trunk/coreboot-v2/src/devices/device_util.c
===================================================================
--- trunk/coreboot-v2/src/devices/device_util.c	2009-07-02 18:27:02 UTC
(rev 4393)
+++ trunk/coreboot-v2/src/devices/device_util.c	2009-07-02 18:56:24 UTC
(rev 4394)
@@ -487,7 +487,7 @@
 	for(curdev = bus->children; curdev; curdev = curdev->sibling) {
 		int i;
 		/* Ignore disabled devices */
-		if (!curdev->have_resources) continue;
+		if (!curdev->enabled) continue;
 		for(i = 0; i < curdev->resources; i++) {
 			struct resource *resource =
&curdev->resource[i];
 			/* If it isn't the right kind of resource ignore
it */
@@ -514,7 +514,7 @@
 	for(curdev = all_devices; curdev; curdev = curdev->next) {
 		int i;
 		/* Ignore disabled devices */
-		if (!curdev->have_resources) continue;
+		if (!curdev->enabled) continue;
 		for(i = 0; i < curdev->resources; i++) {
 			struct resource *resource =
&curdev->resource[i];
 			/* If it isn't the right kind of resource ignore
it */

Modified: trunk/coreboot-v2/src/devices/pci_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_device.c	2009-07-02 18:27:02 UTC
(rev 4393)
+++ trunk/coreboot-v2/src/devices/pci_device.c	2009-07-02 18:56:24 UTC
(rev 4394)
@@ -15,12 +15,12 @@
  */
 
 /*
- *      PCI Bus Services, see include/linux/pci.h for further
explanation.
+ * PCI Bus Services, see include/linux/pci.h for further explanation.
  *
- *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
- *      David Mosberger-Tang
+ * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
+ * David Mosberger-Tang
  *
- *      Copyright 1997 -- 1999 Martin Mares
<mj at atrey.karlin.mff.cuni.cz>
+ * Copyright 1997 -- 1999 Martin Mares <mj at atrey.karlin.mff.cuni.cz>
  */
 
 #include <console/console.h>
@@ -51,9 +51,9 @@
 #include <device/cardbus.h>
 #endif
 
-uint8_t pci_moving_config8(struct device *dev, unsigned reg)
+u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
-	uint8_t value, ones, zeroes;
+	u8 value, ones, zeroes;
 	value = pci_read_config8(dev, reg);
 
 	pci_write_config8(dev, reg, 0xff);
@@ -67,9 +67,9 @@
 	return ones ^ zeroes;
 }
 
-uint16_t pci_moving_config16(struct device *dev, unsigned reg)
+u16 pci_moving_config16(struct device * dev, unsigned int reg)
 {
-	uint16_t value, ones, zeroes;
+	u16 value, ones, zeroes;
 	value = pci_read_config16(dev, reg);
 
 	pci_write_config16(dev, reg, 0xffff);
@@ -83,9 +83,9 @@
 	return ones ^ zeroes;
 }
 
-uint32_t pci_moving_config32(struct device *dev, unsigned reg)
+u32 pci_moving_config32(struct device * dev, unsigned int reg)
 {
-	uint32_t value, ones, zeroes;
+	u32 value, ones, zeroes;
 	value = pci_read_config32(dev, reg);
 
 	pci_write_config32(dev, reg, 0xffffffff);
@@ -99,7 +99,16 @@
 	return ones ^ zeroes;
 }
 
-unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned
last)
+/**
+ * Given a device, a capability type, and a last position, return the
next
+ * matching capability. Always start at the head of the list.
+ *
+ * @param dev Pointer to the device structure.
+ * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking
for.
+ * @param last Location of the PCI capability register to start from.
+ */
+unsigned pci_find_next_capability(struct device *dev, unsigned cap,
+				  unsigned last)
 {
 	unsigned pos;
 	unsigned status;
@@ -109,7 +118,7 @@
 	if (!(status & PCI_STATUS_CAP_LIST)) {
 		return 0;
 	}
-	switch(dev->hdr_type & 0x7f) {
+	switch (dev->hdr_type & 0x7f) {
 	case PCI_HEADER_TYPE_NORMAL:
 	case PCI_HEADER_TYPE_BRIDGE:
 		pos = PCI_CAPABILITY_LIST;
@@ -121,11 +130,12 @@
 		return 0;
 	}
 	pos = pci_read_config8(dev, pos);
-	while(reps-- && (pos >= 0x40)) {   /* loop through the linked
list */
+	while (reps-- && (pos >= 0x40)) {	/* Loop through the
linked list. */
 		int this_cap;
 		pos &= ~3;
 		this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
-		printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
+		printk_spew("Capability: type 0x%02x @ 0x%02x\n",
this_cap,
+			    pos);
 		if (this_cap == 0xff) {
 			break;
 		}
@@ -140,64 +150,71 @@
 	return 0;
 }
 
+/**
+ * Given a device, and a capability type, return the next matching
+ * capability. Always start at the head of the list.
+ *
+ * @param dev Pointer to the device structure.
+ * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking
for.
+ */
 unsigned pci_find_capability(device_t dev, unsigned cap)
 {
 	return pci_find_next_capability(dev, cap, 0);
-
 }
 
-/** Given a device and register, read the size of the BAR for that
register.
- * @param dev       Pointer to the device structure
- * @param resource  Pointer to the resource structure
- * @param index     Address of the pci configuration register
+/**
+ * Given a device and register, read the size of the BAR for that
register.
+ *
+ * @param dev Pointer to the device structure.
+ * @param index Address of the PCI configuration register.
  */
 struct resource *pci_get_resource(struct device *dev, unsigned long
index)
 {
 	struct resource *resource;
 	unsigned long value, attr;
-	resource_t  moving, limit;
+	resource_t moving, limit;
 
-	/* Initialize the resources to nothing */
+	/* Initialize the resources to nothing. */
 	resource = new_resource(dev, index);
 
-	/* Get the initial value */
+	/* Get the initial value. */
 	value = pci_read_config32(dev, index);
 
-	/* See which bits move */
+	/* See which bits move. */
 	moving = pci_moving_config32(dev, index);
 
-	/* Initialize attr to the bits that do not move */
+	/* Initialize attr to the bits that do not move. */
 	attr = value & ~moving;
 
-	/* If it is a 64bit resource look at the high half as well */
+	/* If it is a 64bit resource look at the high half as well. */
 	if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
-		((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
PCI_BASE_ADDRESS_MEM_LIMIT_64))
-	{
-		/* Find the high bits that move */
-		moving |= ((resource_t)pci_moving_config32(dev, index +
4)) << 32;
+	    ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
+	     PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
+		/* Find the high bits that move. */
+		moving |=
+		    ((resource_t) pci_moving_config32(dev, index + 4))
<< 32;
 	}
 	/* Find the resource constraints.
-	 *
 	 * Start by finding the bits that move. From there:
 	 * - Size is the least significant bit of the bits that move.
 	 * - Limit is all of the bits that move plus all of the lower
bits.
-	 * See PCI Spec 6.2.5.1 ...
+	 * See PCI Spec 6.2.5.1.
 	 */
 	limit = 0;
 	if (moving) {
 		resource->size = 1;
 		resource->align = resource->gran = 0;
-		while(!(moving & resource->size)) {
+		while (!(moving & resource->size)) {
 			resource->size <<= 1;
 			resource->align += 1;
-			resource->gran  += 1;
+			resource->gran += 1;
 		}
 		resource->limit = limit = moving | (resource->size - 1);
 	}
-	/*
-	 * some broken hardware has read-only registers that do not
+
+	/* Some broken hardware has read-only registers that do not
 	 * really size correctly.
-	 * Example: the acer m7229 has BARs 1-4 normally read-only.
+	 * Example: the Acer M7229 has BARs 1-4 normally read-only.
 	 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
 	 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
 	 * violation of the spec.
@@ -207,21 +224,19 @@
 	 */
 	if (moving == 0) {
 		if (value != 0) {
-			printk_debug(
-				"%s register %02lx(%08lx), read-only
ignoring it\n",
-				dev_path(dev), index, value);
+			printk_debug
+			    ("%s register %02lx(%08lx), read-only
ignoring it\n",
+			     dev_path(dev), index, value);
 		}
 		resource->flags = 0;
-	}
-	else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
-		/* An I/O mapped base address */
+	} else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
+		/* An I/O mapped base address. */
 		attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
 		resource->flags |= IORESOURCE_IO;
-		/* I don't want to deal with 32bit I/O resources */
+		/* I don't want to deal with 32bit I/O resources. */
 		resource->limit = 0xffff;
-	}
-	else {
-		/* A Memory mapped base address */
+	} else {
+		/* A Memory mapped base address. */
 		attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 		resource->flags |= IORESOURCE_MEM;
 		if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
@@ -229,73 +244,65 @@
 		}
 		attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
 		if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
-			/* 32bit limit */
+			/* 32bit limit. */
 			resource->limit = 0xffffffffUL;
-		}
-		else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
-			/* 1MB limit */
+		} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
+			/* 1MB limit. */
 			resource->limit = 0x000fffffUL;
-		}
-		else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
-			/* 64bit limit */
+		} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
+			/* 64bit limit. */
 			resource->limit = 0xffffffffffffffffULL;
 			resource->flags |= IORESOURCE_PCI64;
-		}
-		else {
-			/* Invalid value */
+		} else {
+			/* Invalid value. */
+			printk_err("Broken BAR with value %lx\n", attr);
+			printk_err(" on dev %s at index %02lx\n",
+			       dev_path(dev), index);
 			resource->flags = 0;
 		}
 	}
-	/* Don't let the limit exceed which bits can move */
+	/* Don't let the limit exceed which bits can move. */
 	if (resource->limit > limit) {
 		resource->limit = limit;
 	}
-#if 0
-	if (resource->flags) {
-		printk_debug("%s %02x ->",
-			dev_path(dev), resource->index);
-		printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones:
0x%08Lx attr: %08lx\n",
-			value, zeroes, ones, attr);
-		printk_debug(
-			"%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ",
-			dev_path(dev),
-			resource->index,
-			resource->size,	resource->limit,
-			resource_type(resource));
-	}
-#endif
 
 	return resource;
 }
 
+/**
+ * Given a device and an index, read the size of the BAR for that
register.
+ *
+ * @param dev Pointer to the device structure.
+ * @param index Address of the PCI configuration register.
+ */
 static void pci_get_rom_resource(struct device *dev, unsigned long
index)
 {
 	struct resource *resource;
 	unsigned long value;
-	resource_t  moving;
+	resource_t moving;
 
-        if ((dev->on_mainboard) && (dev->rom_address == 0)) {
-		//skip it if rom_address is not set in MB Config.lb
-                return;
-        }
+	if ((dev->on_mainboard) && (dev->rom_address == 0)) {
+		/* Skip it if rom_address is not set in the MB
Config.lb. */
+		return;
+	}
 
-	/* Initialize the resources to nothing */
+	/* Initialize the resources to nothing. */
 	resource = new_resource(dev, index);
 
-	/* Get the initial value */
+	/* Get the initial value. */
 	value = pci_read_config32(dev, index);
 
-	/* See which bits move */
+	/* See which bits move. */
 	moving = pci_moving_config32(dev, index);
-	/* clear the Enable bit */
+
+	/* Clear the Enable bit. */
 	moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
 
 	/* Find the resource constraints.
-	 *
 	 * Start by finding the bits that move. From there:
 	 * - Size is the least significant bit of the bits that move.
 	 * - Limit is all of the bits that move plus all of the lower
bits.
-	 * See PCI Spec 6.2.5.1 ...
+	 * See PCI Spec 6.2.5.1.
 	 */
 	if (moving) {
 		resource->size = 1;
@@ -303,59 +310,57 @@
 		while (!(moving & resource->size)) {
 			resource->size <<= 1;
 			resource->align += 1;
-			resource->gran  += 1;
+			resource->gran += 1;
 		}
 		resource->limit = moving | (resource->size - 1);
-	}
-
-	if (moving == 0) {
+		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
+	} else {
 		if (value != 0) {
-			printk_debug("%s register %02lx(%08lx),
read-only ignoring it\n",
-				     dev_path(dev), index, value);
+			printk_debug
+			    ("%s register %02lx(%08lx), read-only
ignoring it\n",
+			     dev_path(dev), index, value);
 		}
 		resource->flags = 0;
-	} else {
-		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
 	}
 
-	/* for on board device with embedded ROM image, the ROM image is
at
+	/* For on board device with embedded ROM image, the ROM image is
at
 	 * fixed address specified in the Config.lb, the
dev->rom_address is
 	 * inited by driver_pci_onboard_ops::enable_dev() */
 	if ((dev->on_mainboard) && (dev->rom_address != 0)) {
-		resource->base   = dev->rom_address;
+		resource->base = dev->rom_address;
 		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY
|
-			IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+		    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 	}
 
 	compact_resources(dev);
 }
 
-/** Read the base address registers for a given device.
- * @param dev Pointer to the dev structure
- * @param howmany How many registers to read (6 for device, 2 for
bridge)
+/**
+ * Read the base address registers for a given device.
+ *
+ * @param dev Pointer to the dev structure.
+ * @param howmany How many registers to read (6 for device, 2 for
bridge).
  */
 static void pci_read_bases(struct device *dev, unsigned int howmany)
 {
 	unsigned long index;
 
-	for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 +
(howmany << 2)); ) {
+	for (index = PCI_BASE_ADDRESS_0;
+	     (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
 		struct resource *resource;
 		resource = pci_get_resource(dev, index);
-		index += (resource->flags & IORESOURCE_PCI64)?8:4;
+		index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
 	}
 
 	compact_resources(dev);
 }
 
-static void pci_set_resource(struct device *dev, struct resource
*resource);
-
-static void pci_record_bridge_resource(
-	struct device *dev, resource_t moving,
-	unsigned index, unsigned long mask, unsigned long type)
+static void pci_record_bridge_resource(struct device *dev, resource_t
moving,
+				       unsigned index, unsigned long
type)
 {
-	/* Initiliaze the constraints on the current bus */
+	/* Initialize the constraints on the current bus. */
 	struct resource *resource;
-	resource = 0;
+	resource = NULL;
 	if (moving) {
 		unsigned long gran;
 		resource_t step;
@@ -363,29 +368,15 @@
 		resource->size = 0;
 		gran = 0;
 		step = 1;
-		while((moving & step) == 0) {
+		while ((moving & step) == 0) {
 			gran += 1;
 			step <<= 1;
 		}
 		resource->gran = gran;
 		resource->align = gran;
 		resource->limit = moving | (step - 1);
-		resource->flags = type | IORESOURCE_PCI_BRIDGE;
-		compute_allocate_resource(&dev->link[0], resource, mask,
type);
-		/* If there is nothing behind the resource,
-		 * clear it and forget it.
-		 */
-		if (resource->size == 0) {
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
-			resource->base = moving;
-#else
-			resource->base = moving & 0xffffffff;
-#endif
-			resource->flags |= IORESOURCE_ASSIGNED;
-			resource->flags &= ~IORESOURCE_STORED;
-			pci_set_resource(dev, resource);
-			resource->flags = 0;
-		}
+		resource->flags = type | IORESOURCE_PCI_BRIDGE |
+				  IORESOURCE_BRIDGE;
 	}
 	return;
 }
@@ -394,47 +385,48 @@
 {
 	resource_t moving_base, moving_limit, moving;
 
-	/* See if the bridge I/O resources are implemented */
-	moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE))
<< 8;
-	moving_base |= ((uint32_t)pci_moving_config16(dev,
PCI_IO_BASE_UPPER16)) << 16;
+	/* See if the bridge I/O resources are implemented. */
+	moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
+	moving_base |=
+	    ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
 
-	moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT))
<< 8;
-	moving_limit |= ((uint32_t)pci_moving_config16(dev,
PCI_IO_LIMIT_UPPER16)) << 16;
+	moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) <<
8;
+	moving_limit |=
+	    ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) <<
16;
 
 	moving = moving_base & moving_limit;
 
-	/* Initialize the io space constraints on the current bus */
-	pci_record_bridge_resource(
-		dev, moving, PCI_IO_BASE,
-		IORESOURCE_IO, IORESOURCE_IO);
+	/* Initialize the I/O space constraints on the current bus. */
+	pci_record_bridge_resource(dev, moving, PCI_IO_BASE,
IORESOURCE_IO);
 
+	/* See if the bridge prefmem resources are implemented. */
+	moving_base =
+	    ((resource_t) pci_moving_config16(dev,
PCI_PREF_MEMORY_BASE)) << 16;
+	moving_base |=
+	    ((resource_t) pci_moving_config32(dev,
PCI_PREF_BASE_UPPER32)) <<
+	    32;
 
-	/* See if the bridge prefmem resources are implemented */
-	moving_base =  ((resource_t)pci_moving_config16(dev,
PCI_PREF_MEMORY_BASE)) << 16;
-	moving_base |= ((resource_t)pci_moving_config32(dev,
PCI_PREF_BASE_UPPER32)) << 32;
+	moving_limit =
+	    ((resource_t) pci_moving_config16(dev,
PCI_PREF_MEMORY_LIMIT)) <<
+	    16;
+	moving_limit |=
+	    ((resource_t) pci_moving_config32(dev,
PCI_PREF_LIMIT_UPPER32)) <<
+	    32;
 
-	moving_limit =  ((resource_t)pci_moving_config16(dev,
PCI_PREF_MEMORY_LIMIT)) << 16;
-	moving_limit |= ((resource_t)pci_moving_config32(dev,
PCI_PREF_LIMIT_UPPER32)) << 32;
-
 	moving = moving_base & moving_limit;
-	/* Initiliaze the prefetchable memory constraints on the current
bus */
-	pci_record_bridge_resource(
-		dev, moving, PCI_PREF_MEMORY_BASE,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH);
+	/* Initialize the prefetchable memory constraints on the current
bus. */
+	pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
+				   IORESOURCE_MEM |
IORESOURCE_PREFETCH);
 
+	/* See if the bridge mem resources are implemented. */
+	moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE))
<< 16;
+	moving_limit = ((u32) pci_moving_config16(dev,
PCI_MEMORY_LIMIT)) << 16;
 
-	/* See if the bridge mem resources are implemented */
-	moving_base = ((uint32_t)pci_moving_config16(dev,
PCI_MEMORY_BASE)) << 16;
-	moving_limit = ((uint32_t)pci_moving_config16(dev,
PCI_MEMORY_LIMIT)) << 16;
-
 	moving = moving_base & moving_limit;
 
-	/* Initialize the memory resources on the current bus */
-	pci_record_bridge_resource(
-		dev, moving, PCI_MEMORY_BASE,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM);
+	/* Initialize the memory resources on the current bus. */
+	pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
+				   IORESOURCE_MEM);
 
 	compact_resources(dev);
 }
@@ -452,34 +444,50 @@
 	pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
 }
 
+void pci_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Initialize the system-wide I/O space constraints. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED;
+
+	/* Initialize the system-wide memory resources constraints. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED;
+}
+
 static void pci_set_resource(struct device *dev, struct resource
*resource)
 {
 	resource_t base, end;
 
-	/* Make certain the resource has actually been set */
+	/* Make certain the resource has actually been assigned a value.
*/
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02lx %s size: 0x%010Lx not
assigned\n",
-			dev_path(dev), resource->index,
-			resource_type(resource),
-			resource->size);
+		printk_err("ERROR: %s %02lx %s size: 0x%010llx not
assigned\n",
+			   dev_path(dev), resource->index,
+			   resource_type(resource), resource->size);
 		return;
 	}
 
-	/* If I have already stored this resource don't worry about it
*/
+	/* If I have already stored this resource don't worry about it.
*/
 	if (resource->flags & IORESOURCE_STORED) {
 		return;
 	}
 
-	/* If the resources is substractive don't worry about it */
+	/* If the resource is subtractive don't worry about it. */
 	if (resource->flags & IORESOURCE_SUBTRACTIVE) {
 		return;
 	}
 
-	/* Only handle PCI memory and IO resources for now */
-	if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
+	/* Only handle PCI memory and I/O resources for now. */
+	if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 		return;
 
-	/* Enable the resources in the command register */
+	/* Enable the resources in the command register. */
 	if (resource->size) {
 		if (resource->flags & IORESOURCE_MEM) {
 			dev->command |= PCI_COMMAND_MEMORY;
@@ -491,19 +499,29 @@
 			dev->command |= PCI_COMMAND_MASTER;
 		}
 	}
-	/* Get the base address */
+	/* Get the base address. */
 	base = resource->base;
 
-	/* Get the end */
+	/* Get the end. */
 	end = resource_end(resource);
 
-	/* Now store the resource */
+	/* Now store the resource. */
 	resource->flags |= IORESOURCE_STORED;
+
+	/* PCI Bridges have no enable bit.  They are disabled if the
base of
+	 * the range is greater than the limit.  If the size is zero,
disable
+	 * by setting the base = limit and end = limit - 2^gran.
+	 */
+	if (resource->size == 0 && (resource->flags &
IORESOURCE_PCI_BRIDGE)) {
+		base = resource->limit;
+		end = resource->limit - (1 << resource->gran);
+		resource->base = base;
+	}
+
 	if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 		unsigned long base_lo, base_hi;
-		/*
-		 * some chipsets allow us to set/clear the IO bit.
-		 * (e.g. VIA 82c686a.) So set it to be safe)
+		/* Some chipsets allow us to set/clear the I/O bit
+		 * (e.g. VIA 82c686a). So set it to be safe.
 		 */
 		base_lo = base & 0xffffffff;
 		base_hi = (base >> 32) & 0xffffffff;
@@ -514,39 +532,27 @@
 		if (resource->flags & IORESOURCE_PCI64) {
 			pci_write_config32(dev, resource->index + 4,
base_hi);
 		}
-	}
-	else if (resource->index == PCI_IO_BASE) {
-		/* set the IO ranges */
-		compute_allocate_resource(&dev->link[0], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
-		pci_write_config8(dev,  PCI_IO_BASE, base >> 8);
+	} else if (resource->index == PCI_IO_BASE) {
+		/* Set the I/O ranges. */
+		pci_write_config8(dev, PCI_IO_BASE, base >> 8);
 		pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >>
16);
-		pci_write_config8(dev,  PCI_IO_LIMIT, end >> 8);
+		pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
 		pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >>
16);
-	}
-	else if (resource->index == PCI_MEMORY_BASE) {
-		/* set the memory range	 */
-		compute_allocate_resource(&dev->link[0], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
+	} else if (resource->index == PCI_MEMORY_BASE) {
+		/* Set the memory range. */
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
 		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
-	}
-	else if (resource->index == PCI_PREF_MEMORY_BASE) {
-		/* set the prefetchable memory range */
-		compute_allocate_resource(&dev->link[0], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
+	} else if (resource->index == PCI_PREF_MEMORY_BASE) {
+		/* Set the prefetchable memory range. */
 		pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >>
16);
 		pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >>
32);
 		pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >>
16);
 		pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >>
32);
-	}
-	else {
-		/* Don't let me think I stored the resource */
+	} else {
+		/* Don't let me think I stored the resource. */
 		resource->flags &= ~IORESOURCE_STORED;
 		printk_err("ERROR: invalid resource->index %lx\n",
-			resource->index);
+			   resource->index);
 	}
 	report_resource_stored(dev, resource, "");
 	return;
@@ -556,14 +562,14 @@
 {
 	struct resource *resource, *last;
 	unsigned link;
-	uint8_t line;
+	u8 line;
 
 	last = &dev->resource[dev->resources];
 
-	for(resource = &dev->resource[0]; resource < last; resource++) {
+	for (resource = &dev->resource[0]; resource < last; resource++)
{
 		pci_set_resource(dev, resource);
 	}
-	for(link = 0; link < dev->links; link++) {
+	for (link = 0; link < dev->links; link++) {
 		struct bus *bus;
 		bus = &dev->link[link];
 		if (bus->children) {
@@ -571,60 +577,64 @@
 		}
 	}
 
-	/* set a default latency timer */
+	/* Set a default latency timer. */
 	pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 
-	/* set a default secondary latency timer */
+	/* Set a default secondary latency timer. */
 	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
 		pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
 	}
 
-	/* zero the irq settings */
+	/* Zero the IRQ settings. */
 	line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
 	if (line) {
 		pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 	}
-	/* set the cache line size, so far 64 bytes is good for everyone
*/
+	/* Set the cache line size, so far 64 bytes is good for
everyone. */
 	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 }
 
 void pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
-	uint16_t command;
+	u16 command;
 
-	/* Set the subsystem vendor and device id for mainboard devices
*/
+	/* Set the subsystem vendor and device id for mainboard devices.
*/
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk_debug("%s subsystem <- %02x/%02x\n",
-			dev_path(dev),
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			     dev_path(dev),
+			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 		ops->set_subsystem(dev,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+
CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+
CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
+	/* v3 has
+	 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR);	// Error
check.
+	 */
 	printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
 }
 
 void pci_bus_enable_resources(struct device *dev)
 {
-	uint16_t ctrl;
-	/* enable IO in command register if there is VGA card
-	 * connected with (even it does not claim IO resource) */
+	u16 ctrl;
+
+	/* Enable I/O in command register if there is VGA card
+	 * connected with (even it does not claim I/O resource).
+	 */
 	if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
 		dev->command |= PCI_COMMAND_IO;
 	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 	ctrl |= dev->link[0].bridge_ctrl;
-	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error
check */
+	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR);	/* Error
check. */
 	printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
 	pci_dev_enable_resources(dev);
-
 	enable_childrens_resources(dev);
 }
 
@@ -640,17 +650,17 @@
 	delay(1);
 }
 
-void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned
device)
+void pci_dev_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
 {
 	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor &
0xffff));
 }
 
 /** default handler: only runs the relevant pci bios. */
 void pci_dev_init(struct device *dev)
 {
 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
-	void run_bios(struct device * dev, unsigned long addr);
+	void run_bios(struct device *dev, unsigned long addr);
 	struct rom_header *rom, *ram;
 
 #if CONFIG_PCI_ROM_RUN != 1
@@ -658,7 +668,7 @@
 	 * is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
 	 * all other option ROM types.
 	 */
-	if ((dev->class>>8)!=PCI_CLASS_DISPLAY_VGA)
+	if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
 		return;
 #endif
 
@@ -685,13 +695,13 @@
 };
 
 struct device_operations default_pci_ops_dev = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init		  = pci_dev_init,
-	.scan_bus	  = 0,
-	.enable           = 0,
-	.ops_pci          = &pci_dev_ops_pci,
+	.init = pci_dev_init,
+	.scan_bus = 0,
+	.enable = 0,
+	.ops_pci = &pci_dev_ops_pci,
 };
 
 /** Default device operations for PCI bridges */
@@ -700,32 +710,29 @@
 };
 
 struct device_operations default_pci_ops_bus = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
-	.init		  = 0,
-	.scan_bus	  = pci_scan_bridge,
-	.enable           = 0,
-	.reset_bus        = pci_bus_reset,
-	.ops_pci          = &pci_bus_ops_pci,
+	.init = 0,
+	.scan_bus = pci_scan_bridge,
+	.enable = 0,
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &pci_bus_ops_pci,
 };
 
 /**
  * @brief Detect the type of downstream bridge
  *
- * This function is a heuristic to detect which type
- * of bus is downstream of a pci to pci bridge.  This
- * functions by looking for various capability blocks
- * to figure out the type of downstream bridge.  PCI-X
- * PCI-E, and Hypertransport all seem to have appropriate
- * capabilities.
+ * This function is a heuristic to detect which type of bus is
downstream
+ * of a PCI-to-PCI bridge. This functions by looking for various
capability
+ * blocks to figure out the type of downstream bridge. PCI-X, PCI-E,
and
+ * Hypertransport all seem to have appropriate capabilities.
  *
  * When only a PCI-Express capability is found the type
  * is examined to see which type of bridge we have.
  *
- * @param dev
- *
- * @return appropriate bridge operations
+ * @param dev Pointer to the device structure of the bridge.
+ * @return Appropriate bridge operations.
  */
 static struct device_operations *get_pci_bridge_ops(device_t dev)
 {
@@ -743,13 +750,13 @@
 #endif
 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
 	pos = 0;
-	while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos)))
{
+	while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT,
pos))) {
 		unsigned flags;
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 		if ((flags >> 13) == 1) {
 			/* Host or Secondary Interface */
 			printk_debug("%s subbordinate bus
Hypertransport\n",
-				dev_path(dev));
+				     dev_path(dev));
 			return &default_ht_ops_bus;
 		}
 	}
@@ -759,16 +766,15 @@
 	if (pos) {
 		unsigned flags;
 		flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
-		switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
+		switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
 		case PCI_EXP_TYPE_ROOT_PORT:
 		case PCI_EXP_TYPE_UPSTREAM:
 		case PCI_EXP_TYPE_DOWNSTREAM:
 			printk_debug("%s subbordinate bus PCI
Express\n",
-				dev_path(dev));
+				     dev_path(dev));
 			return &default_pciexp_ops_bus;
 		case PCI_EXP_TYPE_PCI_BRIDGE:
-			printk_debug("%s subbordinate PCI\n",
-				dev_path(dev));
+			printk_debug("%s subbordinate PCI\n",
dev_path(dev));
 			return &default_pci_ops_bus;
 		default:
 			break;
@@ -779,11 +785,10 @@
 }
 
 /**
- * @brief Set up PCI device operation
+ * Set up PCI device operation.  Check if it already has a driver.  If
not, use
+ * find_device_operations, or set to a default based on type.
  *
- *
- * @param dev
- *
+ * @param dev Pointer to the device whose pci_ops you want to set.
  * @see pci_drivers
  */
 static void set_pci_ops(struct device *dev)
@@ -794,23 +799,22 @@
 	}
 
 	/* Look through the list of setup drivers and find one for
-	 * this pci device
+	 * this PCI device.
 	 */
-	for(driver = &pci_drivers[0]; driver != &epci_drivers[0];
driver++) {
+	for (driver = &pci_drivers[0]; driver != &epci_drivers[0];
driver++) {
 		if ((driver->vendor == dev->vendor) &&
-			(driver->device == dev->device))
-		{
+		    (driver->device == dev->device)) {
 			dev->ops = driver->ops;
 			printk_spew("%s [%04x/%04x] %sops\n",
-				dev_path(dev),
-				driver->vendor, driver->device,
-				(driver->ops->scan_bus?"bus ":""));
+				    dev_path(dev),
+				    driver->vendor, driver->device,
+				    (driver->ops->scan_bus ? "bus " :
""));
 			return;
 		}
 	}
 
 	/* If I don't have a specific driver use the default operations
*/
-	switch(dev->hdr_type & 0x7f) {	/* header type */
+	switch (dev->hdr_type & 0x7f) {	/* header type */
 	case PCI_HEADER_TYPE_NORMAL:	/* standard header */
 		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 			goto bad;
@@ -827,20 +831,18 @@
 		break;
 #endif
 	default:
-	bad:
+	      bad:
 		if (dev->enabled) {
 			printk_err("%s [%04x/%04x/%06x] has unknown
header "
-				"type %02x, ignoring.\n",
-				dev_path(dev),
-				dev->vendor, dev->device,
-				dev->class >> 8, dev->hdr_type);
+				   "type %02x, ignoring.\n",
+				   dev_path(dev),
+				   dev->vendor, dev->device,
+				   dev->class >> 8, dev->hdr_type);
 		}
 	}
 	return;
 }
 
-
-
 /**
  * @brief See if we have already allocated a device structure for a
given devfn.
  *
@@ -848,42 +850,43 @@
  * device structure correspond to the devfn, if present. This function
also
  * removes the device structure from the linked list.
  *
- * @param list the device structure list
- * @param devfn a device/function number
+ * @param list The device structure list.
+ * @param devfn A device/function number.
  *
- * @return pointer to the device structure found or null of we have not
+ * @return Pointer to the device structure found or NULL if we have not
  *	   allocated a device for this devfn yet.
  */
 static struct device *pci_scan_get_dev(struct device **list, unsigned
int devfn)
 {
 	struct device *dev;
 	dev = 0;
-	for(; *list; list = &(*list)->sibling) {
+	for (; *list; list = &(*list)->sibling) {
 		if ((*list)->path.type != DEVICE_PATH_PCI) {
 			printk_err("child %s not a pci device\n",
-				dev_path(*list));
+				   dev_path(*list));
 			continue;
 		}
 		if ((*list)->path.pci.devfn == devfn) {
-			/* Unlink from the list */
+			/* Unlink from the list. */
 			dev = *list;
 			*list = (*list)->sibling;
-			dev->sibling = 0;
+			dev->sibling = NULL;
 			break;
 		}
 	}
-	/* Just like alloc_dev add the device to the  list of device on
the bus.
-	 * When the list of devices was formed we removed all of the
parents
-	 * children, and now we are interleaving static and dynamic
devices in
-	 * order on the bus.
+
+	/* Just like alloc_dev() add the device to the list of devices
on the
+	 * bus. When the list of devices was formed we removed all of
the
+	 * parents children, and now we are interleaving static and
dynamic
+	 * devices in order on the bus.
 	 */
 	if (dev) {
-		device_t child;
-		/* Find the last child of our parent */
-		for(child = dev->bus->children; child && child->sibling;
) {
+		struct device *child;
+		/* Find the last child of our parent. */
+		for (child = dev->bus->children; child &&
child->sibling;) {
 			child = child->sibling;
 		}
-		/* Place the device on the list of children of it's
parent. */
+		/* Place the device on the list of children of its
parent. */
 		if (child) {
 			child->sibling = dev;
 		} else {
@@ -897,7 +900,8 @@
 /**
  * @brief Scan a PCI bus.
  *
- * Determine the existence of a given PCI device.
+ * Determine the existence of a given PCI device. Allocate a new struct
device
+ * if dev==NULL was passed in and the device exists in hardware.
  *
  * @param bus pointer to the bus structure
  * @param devfn to look at
@@ -905,107 +909,94 @@
  * @return The device structure for hte device (if found)
  *         or the NULL if no device is found.
  */
-device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
+device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
 {
-	uint32_t id, class;
-	uint8_t hdr_type;
+	u32 id, class;
+	u8 hdr_type;
 
-	/* Detect if a device is present */
+	/* Detect if a device is present. */
 	if (!dev) {
 		struct device dummy;
-		dummy.bus              = bus;
-		dummy.path.type        = DEVICE_PATH_PCI;
+		dummy.bus = bus;
+		dummy.path.type = DEVICE_PATH_PCI;
 		dummy.path.pci.devfn = devfn;
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
-		/* Have we found somthing?
+		/* Have we found something?
 		 * Some broken boards return 0 if a slot is empty.
 		 */
-		if (	(id == 0xffffffff) || (id == 0x00000000) ||
-			(id == 0x0000ffff) || (id == 0xffff0000))
-		{
+		if ((id == 0xffffffff) || (id == 0x00000000) ||
+		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			printk_spew("%s, bad id 0x%x\n",
dev_path(&dummy), id);
 			return NULL;
 		}
 		dev = alloc_dev(bus, &dummy.path);
-	}
-	else {
-		/* Enable/disable the device.  Once we have
-		 * found the device specific operations this
-		 * operations we will disable the device with
-		 * those as well.
+	} else {
+		/* Enable/disable the device. Once we have found the
device-
+		 * specific operations this operations we will disable
the
+		 * device with those as well.
 		 *
 		 * This is geared toward devices that have subfunctions
 		 * that do not show up by default.
 		 *
 		 * If a device is a stuff option on the motherboard
-		 * it may be absent and enable_dev must cope.
-		 *
+		 * it may be absent and enable_dev() must cope.
 		 */
-		/* Run the magice enable sequence for the device */
+		/* Run the magic enable sequence for the device. */
 		if (dev->chip_ops && dev->chip_ops->enable_dev) {
 			dev->chip_ops->enable_dev(dev);
 		}
-		/* Now read the vendor and device id */
+		/* Now read the vendor and device ID. */
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 
-
-		/* If the device does not have a pci id disable it.
-		 * Possibly this is because we have already disabled
-		 * the device.  But this also handles optional devices
-		 * that may not always show up.
+		/* If the device does not have a PCI ID disable it.
Possibly
+		 * this is because we have already disabled the device.
But
+		 * this also handles optional devices that may not
always
+		 * show up.
 		 */
 		/* If the chain is fully enumerated quit */
-		if (	(id == 0xffffffff) || (id == 0x00000000) ||
-			(id == 0x0000ffff) || (id == 0xffff0000))
-		{
+		if ((id == 0xffffffff) || (id == 0x00000000) ||
+		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			if (dev->enabled) {
 				printk_info("Disabling static device:
%s\n",
-					dev_path(dev));
+					    dev_path(dev));
 				dev->enabled = 0;
 			}
 			return dev;
 		}
 	}
-	/* Read the rest of the pci configuration information */
+	/* Read the rest of the PCI configuration information. */
 	hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 	class = pci_read_config32(dev, PCI_CLASS_REVISION);
 
-	/* Store the interesting information in the device structure */
+	/* Store the interesting information in the device structure. */
 	dev->vendor = id & 0xffff;
 	dev->device = (id >> 16) & 0xffff;
 	dev->hdr_type = hdr_type;
-	/* class code, the upper 3 bytes of PCI_CLASS_REVISION */
+
+	/* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
 	dev->class = class >> 8;
 
-
-	/* Architectural/System devices always need to
-	 * be bus masters.
-	 */
+	/* Architectural/System devices always need to be bus masters.
*/
 	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
 		dev->command |= PCI_COMMAND_MASTER;
 	}
-	/* Look at the vendor and device id, or at least the
-	 * header type and class and figure out which set of
-	 * configuration methods to use.  Unless we already
-	 * have some pci ops.
+	/* Look at the vendor and device ID, or at least the header type
and
+	 * class and figure out which set of configuration methods to
use.
+	 * Unless we already have some PCI ops.
 	 */
 	set_pci_ops(dev);
 
-	/* Now run the magic enable/disable sequence for the device */
+	/* Now run the magic enable/disable sequence for the device. */
 	if (dev->ops && dev->ops->enable) {
 		dev->ops->enable(dev);
 	}
 
-
-	/* Display the device and error if we don't have some pci
operations
-	 * for it.
-	 */
+	/* Display the device. */
 	printk_debug("%s [%04x/%04x] %s%s\n",
-		dev_path(dev),
-		dev->vendor, dev->device,
-		dev->enabled?"enabled": "disabled",
-		dev->ops?"" : " No operations"
-		);
+		     dev_path(dev),
+		     dev->vendor, dev->device,
+		     dev->enabled ? "enabled" : "disabled",
+		     dev->ops ? "" : " No operations");
 
 	return dev;
 }
@@ -1027,73 +1018,69 @@
  * @return The maximum bus number found, after scanning all subordinate
busses
  */
 unsigned int pci_scan_bus(struct bus *bus,
-	unsigned min_devfn, unsigned max_devfn,
-	unsigned int max)
+			  unsigned min_devfn, unsigned max_devfn,
+			  unsigned int max)
 {
 	unsigned int devfn;
-	device_t old_devices;
-	device_t child;
+	struct device *old_devices;
+	struct device *child;
 
 #if CONFIG_PCI_BUS_SEGN_BITS
-	printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
bus->secondary >> 8, bus->secondary & 0xff);
+	printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
+		     bus->secondary >> 8, bus->secondary & 0xff);
 #else
 	printk_debug("PCI: pci_scan_bus for bus %02x\n",
bus->secondary);
 #endif
 
 	old_devices = bus->children;
-	bus->children = 0;
+	bus->children = NULL;
 
 	post_code(0x24);
-	/* probe all devices/functions on this bus with some
optimization for
-	 * non-existence and single funcion devices
+	/* Probe all devices/functions on this bus with some
optimization for
+	 * non-existence and single function devices.
 	 */
 	for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
-		device_t dev;
+		struct device *dev;
 
 		/* First thing setup the device structure */
 		dev = pci_scan_get_dev(&old_devices, devfn);
 
-		/* See if a device is present and setup the device
-		 * structure.
-		 */
+		/* See if a device is present and setup the device
structure. */
 		dev = pci_probe_dev(dev, bus, devfn);
 
-		/* if this is not a multi function device,
-		 * or the device is not present don't waste
-		 * time probing another function.
+		/* If this is not a multi function device, or the device
is
+		 * not present don't waste time probing another
function.
 		 * Skip to next device.
 		 */
 		if ((PCI_FUNC(devfn) == 0x00) &&
-			(!dev || (dev->enabled && ((dev->hdr_type &
0x80) != 0x80))))
-		{
+		    (!dev
+		     || (dev->enabled && ((dev->hdr_type & 0x80) !=
0x80)))) {
 			devfn += 0x07;
 		}
 	}
 	post_code(0x25);
 
-	/* Die if any left over static devices are are found.
+	/* Warn if any leftover static devices are are found.
 	 * There's probably a problem in the Config.lb.
-	*/
-	if(old_devices) {
+	 */
+	if (old_devices) {
 		device_t left;
-		for(left = old_devices; left; left = left->sibling) {
-			printk_err("%s\n", dev_path(left));
+		printk_warning("PCI: Left over static devices:\n");
+		for (left = old_devices; left; left = left->sibling) {
+			printk_warning("%s\n", dev_path(left));
 		}
-		printk_warning("PCI: Left over static devices.  Check
your mainboard Config.lb\n");
+		printk_warning("PCI: Check your mainboard
Config.lb.\n");
 	}
 
-	/* For all children that implement scan_bus (i.e. bridges)
+	/* For all children that implement scan_bus() (i.e. bridges)
 	 * scan the bus behind that child.
 	 */
-	for(child = bus->children; child; child = child->sibling) {
+	for (child = bus->children; child; child = child->sibling) {
 		max = scan_bus(child, max);
 	}
 
-	/*
-	 * We've scanned the bus and so we know all about what's on
-	 * the other side of any bridges that may be on this bus plus
-	 * any devices.
-	 *
+	/* We've scanned the bus and so we know all about what's on the
other
+	 * side of any bridges that may be on this bus plus any devices.
 	 * Return how far we've got finding sub-buses.
 	 */
 	printk_debug("PCI: pci_scan_bus returning with max=%03x\n",
max);
@@ -1101,7 +1088,6 @@
 	return max;
 }
 
-
 /**
  * @brief Scan a PCI bridge and the buses behind the bridge.
  *
@@ -1110,18 +1096,19 @@
  *
  * This function is the default scan_bus() method for PCI bridge
devices.
  *
- * @param dev pointer to the bridge device
- * @param max the highest bus number assgined up to now
- *
- * @return The maximum bus number found, after scanning all subordinate
busses
+ * @param dev Pointer to the bridge device.
+ * @param max The highest bus number assigned up to now.
+ * @return The maximum bus number found, after scanning all subordinate
buses.
  */
 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
-	unsigned int (*do_scan_bus)(struct bus *bus,
-		unsigned min_devfn, unsigned max_devfn, unsigned int
max))
+				unsigned int (*do_scan_bus) (struct bus
* bus,
+							     unsigned
min_devfn,
+							     unsigned
max_devfn,
+							     unsigned
int max))
 {
 	struct bus *bus;
-	uint32_t buses;
-	uint16_t cr;
+	u32 buses;
+	u16 cr;
 
 	printk_spew("%s for %s\n", __func__, dev_path(dev));
 
@@ -1141,8 +1128,7 @@
 	pci_write_config16(dev, PCI_COMMAND, 0x0000);
 	pci_write_config16(dev, PCI_STATUS, 0xffff);
 
-	/*
-	 * Read the existing primary/secondary/subordinate bus
+	/* Read the existing primary/secondary/subordinate bus
 	 * number configuration.
 	 */
 	buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
@@ -1152,9 +1138,9 @@
 	 * correctly configured.
 	 */
 	buses &= 0xff000000;
-	buses |= (((unsigned int) (dev->bus->secondary) << 0) |
-		((unsigned int) (bus->secondary) << 8) |
-		((unsigned int) (bus->subordinate) << 16));
+	buses |= (((unsigned int)(dev->bus->secondary) << 0) |
+		  ((unsigned int)(bus->secondary) << 8) |
+		  ((unsigned int)(bus->subordinate) << 16));
 	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 
 	/* Now we can scan all subordinate buses
@@ -1166,8 +1152,7 @@
 	 * bus number to its real value.
 	 */
 	bus->subordinate = max;
-	buses = (buses & 0xff00ffff) |
-		((unsigned int) (bus->subordinate) << 16);
+	buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate)
<< 16);
 	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 	pci_write_config16(dev, PCI_COMMAND, cr);
 
@@ -1183,90 +1168,109 @@
  *
  * This function is the default scan_bus() method for PCI bridge
devices.
  *
- * @param dev pointer to the bridge device
+ * @param dev Pointer to the bridge device.
+ * @param max The highest bus number assigned up to now.
+ * @return The maximum bus number found, after scanning all subordinate
buses.
+ */
+unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
+{
+	return do_pci_scan_bridge(dev, max, pci_scan_bus);
+}
+
+/**
+ * @brief Scan a PCI domain.
+ *
+ * This function is the default scan_bus() method for PCI domains.
+ *
+ * @param dev pointer to the domain
  * @param max the highest bus number assgined up to now
  *
  * @return The maximum bus number found, after scanning all subordinate
busses
  */
-unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
+unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 {
-	return do_pci_scan_bridge(dev, max, pci_scan_bus);
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
 }
 
-/*
-    Tell the EISA int controller this int must be level triggered
-    THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
-*/
+/**
+ * Tell the EISA int controller this int must be level triggered.
+ *
+ * THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
+ */
 void pci_level_irq(unsigned char intNum)
 {
-	unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1))
<< 8);
+	unsigned short intBits = inb(0x4d0) | (((unsigned)inb(0x4d1)) <<
8);
 
 	printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
 	intBits |= (1 << intNum);
 
 	printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
 
-	// Write new values
-	outb((unsigned char) intBits, 0x4d0);
-	outb((unsigned char) (intBits >> 8), 0x4d1);
+	/* Write new values. */
+	outb((unsigned char)intBits, 0x4d0);
+	outb((unsigned char)(intBits >> 8), 0x4d1);
 
-	/* this seems like an error but is not ... */
-#if 1
+	/* This seems like an error but is not. */
 	if (inb(0x4d0) != (intBits & 0xff)) {
-	  printk_err("%s: lower order bits are wrong: want 0x%x, got
0x%x\n",
-		     __func__, intBits &0xff, inb(0x4d0));
+		printk_err(
+			   "%s: lower order bits are wrong: want 0x%x,
got 0x%x\n",
+			   __func__, intBits & 0xff, inb(0x4d0));
 	}
 	if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
-	  printk_err("%s: lower order bits are wrong: want 0x%x, got
0x%x\n",
-		     __func__, (intBits>>8) &0xff, inb(0x4d1));
+		printk_err(
+			   "%s: lower order bits are wrong: want 0x%x,
got 0x%x\n",
+			   __func__, (intBits >> 8) & 0xff, inb(0x4d1));
 	}
-#endif
 }
 
-/*
-    This function assigns IRQs for all functions contained within
-    the indicated device address.  If the device does not exist or does
-    not require interrupts then this function has no effect.
-
-    This function should be called for each PCI slot in your system.
-
-    pIntAtoD is an array of IRQ #s that are assigned to PINTA through
PINTD of
-    this slot.
-    The particular irq #s that are passed in depend on the routing
inside
-    your southbridge and on your motherboard.
-
-    -kevinh at ispiri.com
+/**
+ * This function assigns IRQs for all functions contained within the
+ * indicated device address. If the device does not exist or does not
+ * require interrupts then this function has no effect.
+ *
+ * This function should be called for each PCI slot in your system.
+ *
+ * pIntAtoD is an array of IRQ #s that are assigned to PINTA through
PINTD of
+ * this slot.
+ *
+ * The particular irq #s that are passed in depend on the routing
inside
+ * your southbridge and on your motherboard.
+ *
+ * -kevinh at ispiri.com
+ *
 */
 void pci_assign_irqs(unsigned bus, unsigned slot,
-	const unsigned char pIntAtoD[4])
+		     const unsigned char pIntAtoD[4])
 {
 	unsigned functNum;
-	device_t pdev;
+	struct device *pdev;
 	unsigned char line;
 	unsigned char irq;
 	unsigned char readback;
 
-	/* Each slot may contain up to eight functions */
+	/* Each slot may contain up to eight functions. */
 	for (functNum = 0; functNum < 8; functNum++) {
 		pdev = dev_find_slot(bus, (slot << 3) + functNum);
 
 		if (pdev) {
-		  line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
+			line = pci_read_config8(pdev,
PCI_INTERRUPT_PIN);
 
-			// PCI spec says all other values are reserved
+			/* PCI spec says all other values are reserved.
*/
 			if ((line >= 1) && (line <= 4)) {
 				irq = pIntAtoD[line - 1];
 
-				printk_debug("Assigning IRQ %d to
%d:%x.%d\n", \
-					irq, bus, slot, functNum);
+				printk_debug("Assigning IRQ %d to
%d:%x.%d\n",
+					     irq, bus, slot, functNum);
 
-				pci_write_config8(pdev,
PCI_INTERRUPT_LINE,\
-					pIntAtoD[line - 1]);
+				pci_write_config8(pdev,
PCI_INTERRUPT_LINE,
+						  pIntAtoD[line - 1]);
 
-				readback = pci_read_config8(pdev,
PCI_INTERRUPT_LINE);
+				readback =
+				    pci_read_config8(pdev,
PCI_INTERRUPT_LINE);
 				printk_debug("  Readback = %d\n",
readback);
 
-				// Change to level triggered
+				// Change to level triggered.
 				pci_level_irq(pIntAtoD[line - 1]);
 			}
 		}

Modified: trunk/coreboot-v2/src/devices/root_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/root_device.c	2009-07-02 18:27:02 UTC
(rev 4393)
+++ trunk/coreboot-v2/src/devices/root_device.c	2009-07-02 18:56:24 UTC
(rev 4394)
@@ -34,29 +34,7 @@
  */
 void root_dev_read_resources(device_t root)
 {
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(root, 0);
-	resource->base  = 0x400;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO;
-	compute_allocate_resource(&root->link[0], resource, 
-		IORESOURCE_IO, IORESOURCE_IO);
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(root, 1);
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM;
-	compute_allocate_resource(&root->link[0], resource,
-		IORESOURCE_MEM, IORESOURCE_MEM);
+	printk_err("%s should never be called.\n", __func__);
 }
 
 /**
@@ -68,14 +46,7 @@
  */
 void root_dev_set_resources(device_t root)
 {
-	struct bus *bus;
-
-	bus = &root->link[0];
-	compute_allocate_resource(bus,
-		&root->resource[0], IORESOURCE_IO, IORESOURCE_IO);
-	compute_allocate_resource(bus, 
-		&root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
-	assign_resources(bus);
+	printk_err("%s should never be called.\n", __func__);
 }
 
 /**

Modified: trunk/coreboot-v2/src/include/device/device.h
===================================================================
--- trunk/coreboot-v2/src/include/device/device.h	2009-07-02
18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/include/device/device.h	2009-07-02
18:56:24 UTC (rev 4394)
@@ -69,17 +69,16 @@
 	unsigned int	hdr_type;	/* PCI header type */
 	unsigned int    enabled : 1;	/* set if we should enable the
device */
 	unsigned int    initialized : 1; /* set if we have initialized
the device */
-	unsigned int    have_resources : 1; /* Set if we have read the
devices resources */
 	unsigned int    on_mainboard : 1;
 	unsigned long   rom_address;
 
-	uint8_t command;
+	u8 command;
 
 	/* Base registers for this device. I/O, MEM and Expansion ROM */
 	struct resource resource[MAX_RESOURCES];
 	unsigned int resources;
 
-	/* link are (down stream) buses attached to the device, usually
a leaf
+	/* links are (downstream) buses attached to the device, usually
a leaf
 	 * device with no children have 0 buses attached and a bridge
has 1 bus 
 	 */
 	struct bus link[MAX_LINKS];
@@ -106,8 +105,6 @@
 /* Generic device helper functions */
 int reset_bus(struct bus *bus);
 unsigned int scan_bus(struct device *bus, unsigned int max);
-void compute_allocate_resource(struct bus *bus, struct resource
*bridge,
-	unsigned long type_mask, unsigned long type);
 void assign_resources(struct bus *bus);
 void enable_resources(struct device *dev);
 void enumerate_static_device(void);
@@ -142,6 +139,8 @@
 #define DEVICE_MEM_ALIGN 4096
 
 extern struct device_operations default_dev_ops_root;
+void pci_domain_read_resources(struct device *dev);
+unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
 void root_dev_read_resources(device_t dev);
 void root_dev_set_resources(device_t dev);
 unsigned int scan_static_bus(device_t bus, unsigned int max);

Modified: trunk/coreboot-v2/src/include/device/resource.h
===================================================================
--- trunk/coreboot-v2/src/include/device/resource.h	2009-07-02
18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/include/device/resource.h	2009-07-02
18:56:24 UTC (rev 4394)
@@ -1,5 +1,5 @@
-#ifndef RESOURCE_H
-#define RESOURCE_H
+#ifndef DEVICE_RESOURCE_H
+#define DEVICE_RESOURCE_H
 
 #include <stdint.h>
 
@@ -19,6 +19,7 @@
 #define IORESOURCE_SUBTRACTIVE  0x00040000	/* This resource filters
all of the unclaimed transactions
 						 * to the bus below.
 						 */
+#define IORESOURCE_BRIDGE	0x00080000	/* The IO resource has a
bus below it. */
 #define IORESOURCE_STORED	0x20000000	/* The IO resource
assignment has been stored in the device */
 #define IORESOURCE_ASSIGNED	0x40000000	/* An IO resource that
has been assigned a value */
 #define IORESOURCE_FIXED	0x80000000	/* An IO resource the
allocator must not change */
@@ -62,7 +63,7 @@
 #define IORESOURCE_MEM_EXPANSIONROM	(1<<6)
 
 
-typedef uint64_t resource_t;
+typedef u64 resource_t;
 struct resource {
 	resource_t base;	/* Base address of the resource */
 	resource_t size;	/* Size of the resource */
@@ -74,10 +75,14 @@
 	/* Alignment must be >= the granularity of the resource */
 };
 
-/* Macros to generate index values for subtractive resources */
+/* Macros to generate index values for resources */
 #define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) +
LINK)
 #define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff)
 
+#define IOINDEX(IDX,LINK) (((LINK) << 16) + IDX)
+#define IOINDEX_LINK(IDX) (( IDX & 0xf0000) >> 16)
+#define IOINDEX_IDX(IDX) (IDX & 0xffff)
+
 /* Generic resource helper functions */
 struct device;
 struct bus;
@@ -101,4 +106,4 @@
 #define RESOURCE_TYPE_MAX 20
 extern const char *resource_type(struct resource *resource);
 
-#endif /* RESOURCE_H */
+#endif /* DEVICE_RESOURCE_H */

Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -341,7 +341,7 @@
 		if (!dev)
 			continue;
 		for(link = 0; !res && (link < 8); link++) {
-			res = probe_resource(dev, 0x1000 + reg +
(link<<16)); // 8 links, 0x1000 man f1,
+			res = probe_resource(dev, IOINDEX(0x1000 + reg,
link));
 		}
 	}
 	result = 2;
@@ -385,7 +385,7 @@
 		reg = 0x110+ (index<<24) + (4<<20); // index could be 0,
255
 	}
 
-	resource = new_resource(dev, 0x1000 + reg + (link<<16));
+		resource = new_resource(dev, IOINDEX(0x1000 + reg,
link));
 
 	return resource;
 }
@@ -421,7 +421,7 @@
 		reg = 0x110+ (index<<24) + (6<<20); // index could be 0,
63
 
 	}
-	resource = new_resource(dev, 0x1000 + reg + (link<<16));
+	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
 	return resource;
 }
 
@@ -447,8 +447,6 @@
 		resource->gran	= align;
 		resource->limit = 0xffffUL;
 		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource,
-					IORESOURCE_IO, IORESOURCE_IO);
 	}
 
 	/* Initialize the prefetchable memory constraints on the current
bus */
@@ -460,9 +458,6 @@
 		resource->gran	= log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
 
 #if CONFIG_EXT_CONF_SUPPORT == 1
 		if((resource->index & 0x1fff) == 0x1110) { // ext
@@ -481,9 +476,6 @@
 		resource->gran	= log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 
 #if CONFIG_EXT_CONF_SUPPORT == 1
 		if((resource->index & 0x1fff) == 0x1110) { // ext
@@ -541,19 +533,14 @@
 
 	/* Get the register and link */
 	reg  = resource->index & 0xfff; // 4k
-	link = ( resource->index>> 16)& 0x7; // 8 links
+	link = IOINDEX_LINK(resource->index);
 
 	if (resource->flags & IORESOURCE_IO) {
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 
 		set_io_addr_reg(dev, nodeid, link, reg, rbase>>8,
rend>>8);
 		store_conf_io_addr(nodeid, link, reg, (resource->index
>> 24), rbase>>8, rend>>8);
 	}
 	else if (resource->flags & IORESOURCE_MEM) {
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			resource->flags & (IORESOURCE_MEM |
IORESOURCE_PREFETCH));
 		set_mmio_addr_reg(nodeid, link, reg, (resource->index
>>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
 		store_conf_mmio_addr(nodeid, link, reg, (resource->index
>>24), rbase>>8, rend>>8);
 	}
@@ -657,7 +644,7 @@
 	.enable_dev = 0,
 };
 
-static void pci_domain_read_resources(device_t dev)
+static void amdfam10_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 	unsigned reg;
@@ -672,20 +659,20 @@
 		/* Is this register allocated? */
 		if ((base & 3) != 0) {
 			unsigned nodeid, link;
-			device_t dev;
+			device_t reg_dev;
 			if(reg<0xc0) { // mmio
 				nodeid = (limit & 0xf) + (base&0x30);
 			} else { // io
 				nodeid =  (limit & 0xf) +
((base>>4)&0x30);
 			}
 			link   = (limit >> 4) & 7;
-			dev = __f0_dev[nodeid];
-			if (dev) {
-				/* Reserve the resource	 */
-				struct resource *resource;
-				resource = new_resource(dev, 0x1000 +
reg + (link<<16));
-				if (resource) {
-					resource->flags = 1;
+			reg_dev = __f0_dev[nodeid];
+			if (reg_dev) {
+				/* Reserve the resource  */
+				struct resource *reg_resource;
+				reg_resource = new_resource(reg_dev,
IOINDEX(0x1000 + reg, link));
+				if (reg_resource) {
+					reg_resource->flags = 1;
 				}
 			}
 		}
@@ -711,24 +698,16 @@
 		resource->base	= 0x400;
 		resource->limit = 0xffffUL;
 		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 
 		/* Initialize the system wide prefetchable memory
resources constraints */
 		resource = new_resource(dev, 1|(link<<2));
 		resource->limit = 0xfcffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
 
 		/* Initialize the system wide memory resources
constraints */
 		resource = new_resource(dev, 2|(link<<2));
 		resource->limit = 0xfcffffffffULL;
 		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 	}
 #endif
 }
@@ -770,10 +749,6 @@
 	return tolm;
 }
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM |
IORESOURCE_PREFETCH)
-#endif
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 
 struct hw_mem_hole_info {
@@ -980,9 +955,6 @@
 		resource->flags |= IORESOURCE_ASSIGNED;
 		resource->flags &= ~IORESOURCE_STORED;
 		link = (resource>>2) & 3;
-		compute_allocate_resource(&dev->link[link], resource,
-			BRIDGE_IO_MASK, resource->flags &
BRIDGE_IO_MASK);
-
 		resource->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, resource, "");
 
@@ -1142,7 +1114,7 @@
 	}
 }
 
-static u32 pci_domain_scan_bus(device_t dev, u32 max)
+static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
 {
 	u32 reg;
 	int i;
@@ -1192,11 +1164,11 @@
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources	  = pci_domain_read_resources,
+	.read_resources	  = amdfam10_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init		  = 0,
-	.scan_bus	  = pci_domain_scan_bus,
+	.scan_bus	  = amdfam10_domain_scan_bus,
 #if CONFIG_MMCONF_SUPPORT_DEFAULT
 	.ops_pci_bus	  = &pci_ops_mmconf,
 #else

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -53,7 +53,7 @@
 	if (iommu) {
 		/* Add a Gart apeture resource */
 		resource = new_resource(dev, 0x94);
-		resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1;
+		resource->size = CONFIG_AGP_APERTURE_SIZE;
 		resource->align = log2(resource->size);
 		resource->gran  = log2(resource->size);
 		resource->limit = 0xffffffff; /* 4G */

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -297,7 +297,7 @@
 		if (!dev)
 			continue;
 		for(link = 0; !res && (link < 3); link++) {
-			res = probe_resource(dev, 0x100 + (reg | link));
+			res = probe_resource(dev, IOINDEX(0x100 + reg,
link));
 		}
 	}
 	result = 2;
@@ -335,7 +335,7 @@
 		reg = free_reg;
 	}
 	if (reg > 0) {
-		resource = new_resource(dev, 0x100 + (reg | link));
+		resource = new_resource(dev, IOINDEX(0x100 + reg,
link));
 	}
 	return resource;
 }
@@ -362,7 +362,7 @@
 		reg = free_reg;
 	}
 	if (reg > 0) {
-		resource = new_resource(dev, 0x100 + (reg | link));
+		resource = new_resource(dev, IOINDEX(0x100 + reg,
link));
 	}
 	return resource;
 }
@@ -379,9 +379,7 @@
 		resource->align = log2(HT_IO_HOST_ALIGN);
 		resource->gran  = log2(HT_IO_HOST_ALIGN);
 		resource->limit = 0xffffUL;
-		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
+		resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
 	}
 
 	/* Initialize the prefetchable memory constraints on the current
bus */
@@ -393,9 +391,9 @@
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
+#ifdef CONFIG_PCI_64BIT_PREF_MEM
+		resource->flags |= IORESOURCE_BRIDGE;
+#endif
 	}
 
 	/* Initialize the memory constraints on the current bus */
@@ -405,11 +403,8 @@
 		resource->size  = 0;
 		resource->align = log2(HT_MEM_HOST_ALIGN);
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
-		resource->limit = 0xffffffffffULL;
-		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
+		resource->limit = 0xffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
 	}
 }
 
@@ -432,11 +427,15 @@
 
 	/* Make certain the resource has actually been set */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		printk_err("%s: can't set unassigned resource @%lx
%lx\n",
+			   __func__, resource->index, resource->flags);
 		return;
 	}
 
 	/* If I have already stored this resource don't worry about it
*/
 	if (resource->flags & IORESOURCE_STORED) {
+		printk_err("%s: can't set stored resource @%lx %lx\n",
__func__,
+			   resource->index, resource->flags);
 		return;
 	}
 
@@ -448,6 +447,10 @@
 	if (resource->index < 0x100) {
 		return;
 	}
+
+	if (resource->size == 0)
+		return;
+
 	/* Get the base address */
 	rbase = resource->base;
 
@@ -456,12 +459,10 @@
 
 	/* Get the register and link */
 	reg  = resource->index & 0xfc;
-	link = resource->index & 3;
+	link = IOINDEX_LINK(resource->index);
 
 	if (resource->flags & IORESOURCE_IO) {
 		uint32_t base, limit;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0xfe000fcc;
@@ -486,9 +487,6 @@
 	}
 	else if (resource->flags & IORESOURCE_MEM) {
 		uint32_t base, limit;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			resource->flags & (IORESOURCE_MEM |
IORESOURCE_PREFETCH));
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0x000000f0;
@@ -634,7 +632,7 @@
 	.enable_dev = 0,
 };
 
-static void pci_domain_read_resources(device_t dev)
+static void amdk8_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 	unsigned reg;
@@ -655,48 +653,21 @@
 			if (reg_dev) {
 				/* Reserve the resource  */
 				struct resource *reg_resource;
-				reg_resource = new_resource(reg_dev,
0x100 + (reg | link));
+				reg_resource = new_resource(reg_dev,
IOINDEX(0x100 + reg, link));
 				if (reg_resource) {
 					reg_resource->flags = 1;
 				}
 			}
 		}
 	}
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base  = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
 
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-#else
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, 0);
-	resource->base  = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_IO, IORESOURCE_IO);
+	pci_domain_read_resources(dev);
 
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	/* Initialize the system wide prefetchable memory resources
constraints */
-	resource = new_resource(dev, 1);
-	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH);
-
-	/* Initialize the system wide memory resources constraints */
 	resource = new_resource(dev, 2);
 	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM);
+	resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 #endif
 }
 
@@ -739,10 +710,6 @@
 	return tolm;
 }
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM |
IORESOURCE_PREFETCH)
-#endif
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 
 struct hw_mem_hole_info {
@@ -898,7 +865,7 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void amdk8_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	struct resource *io, *mem1, *mem2;
@@ -964,13 +931,7 @@
 	last = &dev->resource[dev->resources];
 	for(resource = &dev->resource[0]; resource < last; resource++)
 	{
-#if 1
 		resource->flags |= IORESOURCE_ASSIGNED;
-		resource->flags &= ~IORESOURCE_STORED;
-#endif
-		compute_allocate_resource(&dev->link[0], resource,
-			BRIDGE_IO_MASK, resource->flags &
BRIDGE_IO_MASK);
-
 		resource->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, resource, "");
 
@@ -1125,7 +1086,7 @@
 
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int
max)
 {
 	unsigned reg;
 	int i;
@@ -1160,11 +1121,11 @@
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
+	.read_resources   = amdk8_domain_read_resources,
+	.set_resources    = amdk8_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = amdk8_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1,
 };
 

Modified: trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -66,27 +66,6 @@
 	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, 
 };
 
-
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -187,12 +166,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -356,25 +356,6 @@
 	.device = PCI_DEVICE_ID_NS_GX2,
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -468,12 +449,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -74,8 +74,6 @@
 #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr,
{.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
 #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr,
{.hi=(pdid1<<29)|(bizarro<<28),
.lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
 extern void graphics_init(void);
 extern void cpubug(void);
 extern void chipsetinit(void);
@@ -382,24 +380,6 @@
 	.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
 };
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -470,14 +450,6 @@
 	pci_set_method(dev);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
-
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources = pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,

Modified:
trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base	= 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->base	= 0x80000000ULL;
-	resource->limit = 0xfeffffffULL; /* We can put pci resources in
the system controll area */
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -53,13 +36,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = pci_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,

Modified:
trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base	= 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->base	= 0x80000000ULL;
-	resource->limit = 0xfeffffffULL; /* We can put pci resources in
the system controll area */
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -53,13 +36,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = pci_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -9,23 +9,6 @@
 #include <bitops.h>
 #include "chip.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-        unsigned reg;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base = 0x400; //yhlu
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -155,12 +138,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -28,30 +28,6 @@
 		IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
 }
 
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource
*new)
 {
 	struct resource **best_p = gp;
@@ -90,7 +66,7 @@
 
 #if 1
 	printk_debug("PCI mem marker = %x\n", pci_tolm);
-#endif	
+#endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
 		pci_tolm = 0xe0000000;
@@ -122,7 +98,7 @@
 			remapbasek   = 0x3ff << 16;
 			remaplimitk  = 0 << 16;
 			remapoffsetk = 0 << 16;
-		} 
+		}
 		else {
 			/* The PCI memory hole overlaps memory
 			 * setup the remap window.
@@ -165,7 +141,7 @@
 			ram_resource(dev, 5, 4096*1024, tomk -
4*1024*1024);
 		}
 		if (remaplimitk >= remapbasek) {
-			ram_resource(dev, 6, remapbasek, 
+			ram_resource(dev, 6, remapbasek,
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
@@ -178,13 +154,10 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static u32 e7520_domain_scan_bus(device_t dev, u32 max)
 {
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
-	if (max > max_bus) {
-		max_bus = max;
-	}
-	return max;
+	max_bus = pci_domain_scan_bus(dev, max);
+	return max_bus;
 }
 
 static struct device_operations pci_domain_ops = {
@@ -192,7 +165,7 @@
 	.set_resources    = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = e7520_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the
memory mapped space here? */
 };
 

Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -28,30 +28,6 @@
 		IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
 }
 
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource
*new)
 {
 	struct resource **best_p = gp;
@@ -90,7 +66,7 @@
 
 #if 1
 	printk_debug("PCI mem marker = %x\n", pci_tolm);
-#endif	
+#endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
 		pci_tolm = 0xe0000000;
@@ -122,7 +98,7 @@
 			remapbasek   = 0x3ff << 16;
 			remaplimitk  = 0 << 16;
 			remapoffsetk = 0 << 16;
-		} 
+		}
 		else {
 			/* The PCI memory hole overlaps memory
 			 * setup the remap window.
@@ -160,12 +136,12 @@
 
 		/* Report the memory regions */
     		ram_resource(dev, 3,   0, 640);
-		ram_resource(dev, 4, 768, tolmk - 768);
+		ram_resource(dev, 4, 768, (tolmk - 768));
 		if (tomk > 4*1024*1024) {
 			ram_resource(dev, 5, 4096*1024, tomk -
4*1024*1024);
 		}
 		if (remaplimitk >= remapbasek) {
-			ram_resource(dev, 6, remapbasek, 
+			ram_resource(dev, 6, remapbasek,
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
@@ -178,13 +154,10 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static u32 e7525_domain_scan_bus(device_t dev, u32 max)
 {
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
-	if (max > max_bus) {
-		max_bus = max;
-	}
-	return max;
+	max_bus = pci_domain_scan_bus(dev, max);
+	return max_bus;
 }
 
 static struct device_operations pci_domain_ops = {
@@ -192,7 +165,7 @@
 	.set_resources    = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = e7525_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the
memory mapped space here? */
 };
 

Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -49,30 +49,6 @@
 		IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
 }
 
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource
*new)
 {
 	struct resource **best_p = gp;
@@ -199,13 +175,10 @@
 	assign_resources(&dev->link[0]);
 }
 
-static u32 pci_domain_scan_bus(device_t dev, u32 max)
+static u32 i3100_domain_scan_bus(device_t dev, u32 max)
 {
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
-	if (max > max_bus) {
-		max_bus = max;
-	}
-	return max;
+	max_bus = pci_domain_scan_bus(dev, max);
+	return max_bus;
 }
 
 static struct device_operations pci_domain_ops = {
@@ -213,7 +186,7 @@
 	.set_resources    = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = i3100_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the
memory mapped space here? */
 };
 

Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -33,24 +33,6 @@
 	.device = 0x7190,
 };
 
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -95,7 +77,7 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void i440bx_domain_set_resources(device_t dev)
 {
 	device_t mc_dev;
 	uint32_t pci_tolm;
@@ -140,15 +122,9 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources		= pci_domain_read_resources,
-	.set_resources		= pci_domain_set_resources,
+	.set_resources		= i440bx_domain_set_resources,
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,

Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -52,27 +52,6 @@
 	.device	= 0x7120,
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-	unsigned reg;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -181,12 +160,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources		= pci_domain_read_resources,
 	.set_resources		= pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -51,25 +51,6 @@
 	.device = 0x3575,
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide I/O space constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -158,12 +139,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources		= pci_domain_read_resources,
 	.set_resources		= pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -31,24 +31,6 @@
 #include <cpu/x86/cache.h>
 #include "chip.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-        unsigned reg;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -156,12 +138,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -10,23 +10,6 @@
 #include <bitops.h>
 #include "chip.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -123,12 +106,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -43,31 +43,6 @@
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base = 0;
-	resource->size = 0;
-	resource->align = 0;
-	resource->gran = 0;
-	resource->limit = 0xffffUL;
-	resource->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->base = 0;
-	resource->size = 0;
-	resource->align = 0;
-	resource->gran = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource
*new)
 {
 	struct resource **best_p = gp;
@@ -184,15 +159,10 @@
 #endif
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
 	/* TODO We could determine how many PCIe busses we need in
 	 * the bar. For now that number is hardcoded to a max of 64.
+	 * See e7525/northbridge.c for an example.
 	 */
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources   = pci_domain_read_resources,
 	.set_resources    = pci_domain_set_resources,

Modified:
trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c
===================================================================
---
trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++
trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -16,7 +16,7 @@
  * be large enough to hold all expected resources for all PCI
  * devices.
  */
-static void pci_domain_read_resources(device_t dev)
+static void mpc107_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 
@@ -101,15 +101,8 @@
 	assign_resources(&dev->link[0]);
 }
 
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
-	.read_resources	  = pci_domain_read_resources,
+	.read_resources	  = mpc107_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init		  = 0,

Modified: trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -101,11 +101,11 @@
 	.device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL,
 };
 
-static void pci_domain_read_resources(device_t dev)
+static void cn400_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 
-	printk_spew("Entering cn400 pci_domain_read_resources.\n");
+	printk_spew("Entering %s.\n", __func__);
 
 	/* Initialize the system wide I/O space constraints. */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
@@ -119,7 +119,7 @@
 	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 	    IORESOURCE_ASSIGNED;
 
-	printk_spew("Leaving cn400 pci_domain_read_resources.\n");
+	printk_spew("Leaving %s.\n", __func__);
 }
 
 static void ram_resource(device_t dev, unsigned long index,
@@ -173,14 +173,14 @@
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void cn400_domain_set_resources(device_t dev)
 {
 	/* The order is important to find the correct RAM size. */
 	static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
 	device_t mc_dev;
 	u32 pci_tolm;
 
-	printk_spew("Entering cn400 pci_domain_set_resources.\n");
+	printk_spew("Entering %s.\n", __func__);
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -226,23 +226,23 @@
 	}
 	assign_resources(&dev->link[0]);
 	
-	printk_spew("Leaving cn400 pci_domain_set_resources.\n");
+	printk_spew("Leaving %s.\n", __func__);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int
max)
 {
-	printk_debug("Entering cn400 pci_domain_scan_bus.\n");
+	printk_debug("Entering %s.\n", __func__);
 
 	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 	return max;
 }
 
 static const struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
+	.read_resources   = cn400_domain_read_resources,
+	.set_resources    = cn400_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = cn400_domain_scan_bus,
 };
 
 static void cpu_bus_init(device_t dev)

Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -97,27 +97,6 @@
 	.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
 };
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	printk_spew("Entering cn700 pci_domain_read_resources.\n");
-
-	/* Initialize the system wide I/O space constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	printk_spew("Leaving cn700 pci_domain_read_resources.\n");
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -223,14 +202,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_debug("Entering cn700 pci_domain_scan_bus.\n");
-
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static const struct device_operations pci_domain_ops = {
 	.read_resources   = pci_domain_read_resources,
 	.set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -329,7 +329,7 @@
 
 void cx700_read_resources(device_t dev)
 {
-	struct resource *resource;
+	struct resource *res;
 
 	/* Make sure we call our childrens set/enable functions - these
 	 * are not called unless this device has a resource to set.
@@ -337,11 +337,16 @@
 
 	pci_dev_read_resources(dev);
 
-	resource = new_resource(dev, 1);
-	resource->flags |=
-	    IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO |
IORESOURCE_STORED;
-	resource->size = 2;
-	resource->base = 0x2e;
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 void cx700_set_resources(device_t dev)

Modified: trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -32,21 +32,6 @@
 #include "chip.h"
 #include "northbridge.h"
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -146,12 +131,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = pci_domain_read_resources,
 	.set_resources	  = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -45,23 +45,6 @@
 	.device = 0x0601, /* 0x8601 is the AGP bridge? */
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -160,12 +143,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -190,30 +190,6 @@
 	.device = 0x3122,
 };
 
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-	printk_spew("Entering vt8623 pci_domain_read_resources.\n");
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		IORESOURCE_ASSIGNED;
-
-	printk_spew("Leaving vt8623 pci_domain_read_resources.\n");
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -313,14 +289,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_spew("Entering vt8623 pci_domain_scan_bus.\n");
-
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -69,27 +69,6 @@
 	.device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL,
 };
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	printk_spew("Entering vx800 pci_domain_read_resources.\n");
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-	    IORESOURCE_ASSIGNED;
-
-	printk_spew("Leaving vx800 pci_domain_read_resources.\n");
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -195,14 +174,6 @@
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	printk_debug("Entering vx800 pci_domain_scan_bus.\n");
-
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static const struct device_operations pci_domain_ops = {
 	.read_resources = pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,

Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -162,15 +162,26 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-	
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 static void amd8111_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -364,9 +364,6 @@
 		/* set the memory range */
 		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		res->flags |= IORESOURCE_STORED;
-		compute_allocate_resource(&dev->link[0], res,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 		base = res->base;
 		end  = resource_end(res);
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);

Modified: trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -350,9 +350,6 @@
 		/* set the memory range */
 		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		res->flags |= IORESOURCE_STORED;
-		compute_allocate_resource(&dev->link[0], res,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 		base = res->base;
 		end  = resource_end(res);
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -25,6 +25,24 @@
 #include <device/pci_ids.h>
 #include "cs5530.h"
 
+static void cs5530_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+}
+
 static void isa_init(struct device *dev)
 {
 	uint8_t reg8;
@@ -45,7 +63,7 @@
 }
 
 static struct device_operations isa_ops = {
-	.read_resources		= pci_dev_read_resources,
+	.read_resources		= cs5530_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= cs5530_pci_dev_enable_resources,
 	.init			= isa_init,

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -69,6 +69,24 @@
 	printk_spew("%s: dev is %p\n", __func__, dev);
 }
 
+static void cs5535_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+}
+
 static void cs5535_pci_dev_enable_resources(device_t dev)
 {
 	printk_spew("cs5535.c: %s()\n", __func__);
@@ -77,7 +95,7 @@
 }
 
 static struct device_operations southbridge_ops = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources   = cs5535_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = cs5535_pci_dev_enable_resources,
 	.init             = southbridge_init,

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -607,6 +607,25 @@
 	}
 }
 
+static void cs5536_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+}
+
 static void southbridge_enable(struct device *dev)
 {
 	printk_err("cs5536: %s: dev is %p\n", __func__, dev);
@@ -621,7 +640,7 @@
 }
 
 static struct device_operations southbridge_ops = {
-	.read_resources = pci_dev_read_resources,
+	.read_resources = cs5536_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = cs5536_pci_dev_enable_resources,
 	.init = southbridge_init,

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -70,15 +70,24 @@
 
 	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
 	compact_resources(dev);
 }
 
@@ -111,7 +120,7 @@
 		for (child = dev->link[link].children; child;
 		     child = child->sibling) {
 			enable_resources(child);
-			if (child->have_resources
+			if (child->enabled
 			    && (child->path.type == DEVICE_PATH_PNP)) {
 				for (i = 0; i < child->resources; i++) {
 					struct resource *res;

Modified:
trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -29,18 +29,27 @@
 static void bcm5785_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
-	unsigned long index;
 
 	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev); 
-	
-        /* Add an extra subtractive resource for both memory and I/O */
-        res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-        res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
-        
-        res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	pci_dev_read_resources(dev);
 
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 /**     
@@ -69,7 +78,7 @@
                 device_t child;
                 for (child = dev->link[link].children; child; child =
child->sibling) {
                         enable_resources(child);
-			if(child->have_resources && (child->path.type ==
DEVICE_PATH_PNP)) {
+			if(child->enabled && (child->path.type ==
DEVICE_PATH_PNP)) {
 				for(i=0;i<child->resources;i++) {
 					struct resource *res;
 			                unsigned long base, end; //
don't need long long

Modified:
trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
===================================================================
---
trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
2009-07-02 18:27:02 UTC (rev 4393)
+++
trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -51,7 +51,6 @@
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); 		
-	
 	/* Get Resource for SMBUS */	
 	pci_get_resource(dev, 0x90);	
 

Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -361,12 +361,23 @@
 	/* Add the GPIO BAR */
 	res = pci_get_resource(dev, GPIO_BAR);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 static void esb6300_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -399,13 +399,24 @@
 	/* Add the GPIO BAR */
 	res = pci_get_resource(dev, GPIO_BAR);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
 	/* Add resource for RCBA */
 	res = new_resource(dev, RCBA);
 	res->size = 0x4000;

Modified:
trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -55,8 +55,31 @@
 	isa_dma_init();
 }
 
-static const struct device_operations isa_ops = {
-	.read_resources		= pci_dev_read_resources,
+static void sb_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 2);
+	res->base = 0xff800000UL;
+	res->size = 0x00800000UL; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+}
+
+const struct device_operations isa_ops = {
+	.read_resources		= sb_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= isa_init,

Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -207,15 +207,26 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 static void i82801ca_lpc_enable_resources(device_t dev)

Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -182,15 +182,26 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 static void i82801dbm_lpc_enable_resources(device_t dev)

Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -334,7 +334,7 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
 	/* Add the ACPI BAR */
@@ -343,12 +343,23 @@
 	/* Add the GPIO BAR */
 	res = pci_get_resource(dev, GPIO_BAR);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 static void i82801er_lpc_enable_resources(device_t dev)

Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -419,12 +419,21 @@
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 static void i82801gx_lpc_enable_resources(device_t dev)

Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -340,12 +340,21 @@
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 static void i82801xx_lpc_enable_resources(device_t dev)

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -275,12 +275,21 @@
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 /**
@@ -308,7 +317,7 @@
 		device_t child;
 		for (child = dev->link[link].children; child; child =
child->sibling) {
 			enable_resources(child);
-			if (child->have_resources && (child->path.type
== DEVICE_PATH_PNP)) {
+			if (child->enabled && (child->path.type ==
DEVICE_PATH_PNP)) {
 				for (i = 0; i < child->resources; i++) {
 					struct resource *res;
 					unsigned long base, end;
// don't need long long

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -5,6 +5,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/resource.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -13,10 +14,8 @@
 static void pci_init(struct device *dev)
 {
 	uint32_t dword;
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
-	struct resource *mem1, *mem2;
-#endif
+	struct resource *mem, *pref;
 
 	dword = pci_read_config32(dev, 0x04);
 	dword |= (1 << 8);	/* System error enable */
@@ -36,7 +35,6 @@
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
 	while (pci_domain_dev) {
 		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
@@ -47,21 +45,19 @@
 	if (!pci_domain_dev)
 		return;		/* Impossible */
 
-	mem1 = find_resource(pci_domain_dev, 1);	// prefmem, it
could be 64bit
-	mem2 = find_resource(pci_domain_dev, 2);	// mem
-	if (mem1->base > mem2->base) {
-		dword = mem2->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n",
mem2->base);
+	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
+	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
+
+	if (!mem)
+		return;		/* Impossible */
+
+	if (!pref || pref->base > mem->base) {
+		dword = mem->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n",
mem->base);
 	} else {
-		dword = mem1->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base =
0x%010Lx\n",
-			     mem1->base);
+		dword = pref->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n",
pref->base);
 	}
-#else
-	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n",
-		     dev_root.resource[1].base);
-#endif
 
 	printk_debug("[0x50] <-- 0x%08x\n", dword);
 	pci_write_config32(dev, 0x50, dword);	/* TOM */

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -248,16 +248,27 @@
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev); // We got one for APIC, or one more
for TRAP
+	/* Get the normal PCI resources of this device. */
+	/* We got one for APIC, or one more for TRAP. */
+	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 /**
@@ -265,7 +276,7 @@
  *
  * @param dev the device whos children's resources are to be enabled
  *
- * This function is call by the global enable_resources() indirectly
via the
+ * This function is called by the global enable_resources() indirectly
via the
  * device_operation::enable_resources() method of devices.
  *
  * Indirect mutual recursion:
@@ -286,7 +297,7 @@
 		device_t child;
 		for (child = dev->link[link].children; child; child =
child->sibling) {
 			enable_resources(child);
-			if(child->have_resources && (child->path.type ==
DEVICE_PATH_PNP)) {
+			if(child->enabled && (child->path.type ==
DEVICE_PATH_PNP)) {
 				for(i=0;i<child->resources;i++) {
 					struct resource *res;
 					unsigned long base, end; //
don't need long long

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -23,6 +23,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/resource.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -33,10 +34,8 @@
 
 	uint32_t dword;
 	uint16_t word;
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
-	struct resource *mem1, *mem2;
-#endif
+	struct resource *mem, *pref;
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
@@ -58,30 +57,32 @@
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
-	while(pci_domain_dev) {
-		if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
break;
+	while (pci_domain_dev) {
+		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
+			break;
 		pci_domain_dev = pci_domain_dev->bus->dev;
 	}
 
-	if(!pci_domain_dev) return; // impossiable
-	mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be
64bit
-	mem2 = find_resource(pci_domain_dev, 2); // mem
-	if(mem1->base > mem2->base) {
-		dword = mem2->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n",
mem2->base);
+	if (!pci_domain_dev)
+		return;		/* Impossible */
+
+	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
+	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
+
+	if (!mem)
+		return;		/* Impossible */
+
+	if (!pref || pref->base > mem->base) {
+		dword = mem->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n",
mem->base);
 	} else {
-		dword = mem1->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base =
0x%010Lx\n", mem1->base);
+		dword = pref->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n",
pref->base);
 	}
-#else
-	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n",
dev_root.resource[1].base);
-#endif
+
 	printk_debug("[0x50] <-- 0x%08x\n", dword);
-	pci_write_config32(dev, 0x50, dword); //TOM
-
+	pci_write_config32(dev, 0x50, dword);	/* TOM */
 }
 
 static struct pci_operations lops_pci = {

Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -172,7 +172,6 @@
 		resource = find_resource(dev,1);
 		if( !(resource->flags & IORESOURCE_STORED) ){
 			resource->flags |= IORESOURCE_STORED ;
-
compute_allocate_resource(&dev->link[0],resource,resource->flags,resourc
e->flags);
 			printk_debug("%s 1 ==>
%x\n",dev_path(dev),resource->base); 
 			cf_base = resource->base;
 		}

Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -239,13 +239,23 @@
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); // We got one for APIC, or one more
for TRAP
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
 
 /**
@@ -274,7 +284,7 @@
 		device_t child;
 		for (child = dev->link[link].children; child; child =
child->sibling) {
 			enable_resources(child);
-			if(child->have_resources && (child->path.type ==
DEVICE_PATH_PNP)) {
+			if(child->enabled && (child->path.type ==
DEVICE_PATH_PNP)) {
 				for(i=0;i<child->resources;i++) {
 					struct resource *res;
 					unsigned long base, end; //
don't need long long

Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -131,6 +131,24 @@
 	rtc_init(0);
 }
 
+void vt8231_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+}
+
 static void southbridge_init(struct device *dev)
 {
 	vt8231_init(dev);
@@ -138,7 +156,7 @@
 }
 
 static struct device_operations vt8231_lpc_ops = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources   = vt8231_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init		  = &southbridge_init,

Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -219,15 +219,22 @@
    device has a resource to set - so set a dummy one */
 void vt8235_read_resources(device_t dev)
 {
+	struct resource *res;
 
-	struct resource *resource;
 	pci_dev_read_resources(dev);
-	resource = new_resource(dev, 1);
-	resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED |
IORESOURCE_IO | IORESOURCE_STORED;
-	resource->size = 2;
-	resource->base = 0x2e;
 
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
 }
+
 void vt8235_set_resources(device_t dev)
 {
 	struct resource *resource;

Modified: trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
2009-07-02 18:27:02 UTC (rev 4393)
+++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c
2009-07-02 18:56:24 UTC (rev 4394)
@@ -188,8 +188,26 @@
 	enable_childrens_resources(dev);
 }
 
+static void w83c553_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
+}
+
 static struct device_operations w83c553_ops  = {
-        .read_resources   = pci_dev_read_resources,
+        .read_resources   = w83c553_read_resources,
         .set_resources    = pci_dev_set_resources,
         .enable_resources = w83c553_enable_resources,
         .init             = w83c553_init,


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From JasonZhao at viatech.com.cn  Fri Jul  3 09:53:58 2009
From: JasonZhao at viatech.com.cn (JasonZhao at viatech.com.cn)
Date: Fri, 3 Jul 2009 15:53:58 +0800
Subject: [coreboot] Share my code of running vgabios(in CBFS) in seabios
	when rusume from s3.
Message-ID: <9156F9F8217CD44898ABE1E581FAFF886A3247@exchbj02.viatech.com.bj>

Hi Rudolf	,
I work out some code to make seabios run vgabios when resuming from S3
(follow your advice on IRC, again :) ). And it is unbelievable easy,
only 2 step:

Setp 1: In acpi.c

void acpi_jump_to_wakeup(void *vector)
{
	/* just restore the SMP trampoline and continue with wakeup on
assembly level */
	memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
-//	acpi_jmp_to_realm_wakeup((u32) vector);

//	seabios at entry_post:(in romlayout.S) will check cmos[0x8f] it
as a S3 resuming flag.
+     outb(0x0f, RTC_BASE_PORT + 0); 
+     outb(0xfe, RTC_BASE_PORT + 1);  

+	//these two lines has same effect with the above two lines, and
I don know 8f or 0f which is better. cmos_read/write in coreboot do not
set bit 7.
+//	outb(0x8f, RTC_BASE_PORT + 0);  
+//	outb(0xfe, RTC_BASE_PORT + 1);  
+	acpi_jmp_to_realm_wakeup(0xffff0); 
}


Step 2: in seabios->resume.c->s3_resume()
    smm_init();
+   vga_setup();
    make_bios_readonly();
    u32 s3_resume_vector = find_resume_vector();


And my suggest is to rename acpi_jmp_to_realm_wakeup() to
jmp_to_realm_and_back(), and change wakeup.S to be more general by
supporting realmode code that running at >1M address.


-jasonzhao 



From uwe at hermann-uwe.de  Fri Jul  3 14:08:45 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Jul 2009 14:08:45 +0200
Subject: [coreboot] coreinfo compilation problem
In-Reply-To: <e37d376a0906280049s6066a18ap2fa4e7a438d56a5c@mail.gmail.com>
References: <e37d376a0906280049s6066a18ap2fa4e7a438d56a5c@mail.gmail.com>
Message-ID: <20090703120845.GA19126@greenwood>

On Sun, Jun 28, 2009 at 12:49:09AM -0700, Warren Turkal wrote:
> The following is the output I get when trying to compile coreinfo.
> 
> wt at mediakitchen:~/projects/coreboot/coreinfo$ make
>   CC      build/cpuinfo_module.o
>   AS      build/cpuid.S.o
>   CC      build/pci_module.o
>   CC      build/coreboot_module.o
>   CC      build/nvram_module.o
>   CC      build/bootlog_module.o
>   CC      build/ramdump_module.o
>   CC      build/lar_module.o
>   CC      build/multiboot_module.o
>   CC      build/coreinfo.o
>   LD      build/coreinfo.elf
> /home/wt/projects/coreboot/coreinfo/build/cpuinfo_module.o: In
> function `cpuinfo_module_init':
> cpuinfo_module.c:(.text+0x469): undefined reference to `__udivdi3'
> ../libpayload/bin/../lib/libpayload.a(timer.o): In function `get_cpu_speed':
> timer.c:(.text+0xe8): undefined reference to `__udivdi3'
> ../libpayload/bin/../lib/libpayload.a(printf.o): In function `print_number':
> printf.c:(.text+0x344): undefined reference to `__umoddi3'
> printf.c:(.text+0x379): undefined reference to `__udivdi3'
> collect2: ld returned 1 exit status
> make: *** [/home/wt/projects/coreboot/coreinfo/build/coreinfo.elf] Error 1
> 
> 
> Is there something I am not doing that I should be doing?

apt-get install gcc-multilib

That should fix your problem. You're on a 64bit system and need 32bit
libgcc.


> Also, I had to manually symlink libpayload.config to .config in my
> libpayload directory so that lpgcc would work. This should probably be
> automated.

There's no symlinking required, but I think the docs need some updating.
The problem is that coreinfo must be pointed to an _installed_ libpayload
dir, not to the libpayload source directory.

Here's what the canonical installation instructions look like (similar
to FILO trunk):

svn co svn://coreboot.org/repos/trunk/payloads/libpayload libpayload-source
cd libpayload-source
make menuconfig
make
make DESTDIR=.. install
cd ..

svn co svn://coreboot.org/repos/trunk/payloads/coreinfo
cd coreinfo
make

We could also make libpayload an svn:external in the coreinfo dir like
FILO does, dunno which is the better choice on the long run.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Fri Jul  3 14:25:48 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Jul 2009 14:25:48 +0200
Subject: [coreboot] Support for Asus A8M2N-LA ?
In-Reply-To: <loom.20090703T011652-263@post.gmane.org>
References: <loom.20090703T011652-263@post.gmane.org>
Message-ID: <20090703122547.GA24201@greenwood>

On Fri, Jul 03, 2009 at 02:08:08AM +0000, Goboster wrote:
> I've got a HP Pavilion desktop that has an ASUS OEM motherboard model A8M2N-LA.
> Manufacturer details are here (there is a nice schematic):
> http://tr.im/qHw7
> 
> It appears to have an MCP51 southbridge, ASUS A8000 SuperIO, a "GeForce 6150 LE"
> northbridge, Pm49FL004 flash, and also has a Nvidia C51PVG chip on it. I have no
> idea what that last chip is, but I saw some references to it in an earlier
> thread here http://tr.im/qHvZ .

I'm afraid this board will not be supported anytime soon. Both the
NVIDIA C51 and MCP51 are not supported and we generally don't have
_any_ NVIDIA datasheets, so this will not change a lot...

(Only MVIDIA MCP55 and CK804 are supported because a developer had
NDA datasheets back then, but he no longer has access to them also)


> superiotool -dV
> (all other probes not listed failed)
> Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
> Found ASUS A8000 (id=0x77, rev=0x03) at 0x2e

Nice, thanks! We didn't yet have a dump from an A8000, nice to see that
the code seems to work ok. Will link to it in the superiotool wiki page.


> flashrom -V
> Calibrating delay loop... 353M loops per second. OK.
> No coreboot table found.
> Found chipset "NVidia MCP51", enabling flash write... OK.
[...]
> Pm49FL004 found at physical address 0xfff80000.
> Flash part is Pm49FL004 (512 KB).
> No operations were specified.

Looks good so far. If you have a working backup chip (and the chip is
in a socket, not soldered) then you can try to erase the chip and write
random data on it to see if flashrom supports your board out of the box
or if any special flashrom code will be required. That would be helpful.

But please only attempt this if you are sure you can recover in case the
flashing doesn't work.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From goboster at yahoo.com  Fri Jul  3 15:10:17 2009
From: goboster at yahoo.com (Goboster)
Date: Fri, 03 Jul 2009 06:10:17 -0700
Subject: [coreboot] Support for Asus A8M2N-LA ?
Message-ID: <4A4E0339.6090805@yahoo.com>


Uwe Hermann wrote:
> Nice, thanks! We didn't yet have a dump from an A8000, nice to see that
> the code seems to work ok. Will link to it in the superiotool wiki page.

Glad I could be of some help!

> I'm afraid this board will not be supported anytime soon.

Oh well, thanks for letting me know

> Looks good so far. If you have a working backup chip (and the chip is
> in a socket, not soldered) then you can try to erase the chip and write
> random data on it to see if flashrom supports your board out of the box
> or if any special flashrom code will be required. That would be helpful.
> 
> But please only attempt this if you are sure you can recover in case the
> flashing doesn't work.

Unfortunately, I don't have a means of recovering a failed flashing.
I've been wanting to get a flash writer just for messing around with
this kind of stuff, but alas, none so far ;)




From harald.gutmann at gmx.net  Fri Jul  3 16:53:24 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Fri, 3 Jul 2009 16:53:24 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702212634.3905.qmail@stuge.se>
References: <20090701142139.GA7679@flashgordon>
	<200907022202.08049.harald.gutmann@gmx.net>
	<20090702212634.3905.qmail@stuge.se>
Message-ID: <200907031653.28436.harald.gutmann@gmx.net>

On Thursday 02 July 2009 23:26:34 Peter Stuge wrote:
> Harald Gutmann wrote:
> > > Is the port interrupt-driven, or polling, on your system, Andreas?
> >
> > Here on my system it says also polling, like on Andreas system.
> > What is the difference between interrupt driven and polling?
>
> Interrupt driven means the port has an interrupt assigned to it, and
> that communication over the port is event based.
>
> Polling means there is a timer running in the kernel which will check
> the port for activity every few milliseconds or something.
>
> > On vendor bios it is interrupt-driven.
> > Is an ACPI part missing to get it interrupt driven?
>
> I think so, yes.
I think this should be easy to fix if it is really acpi related, just a few 
lines in the dsdt.asl should do the job.

But right now I'm a little bit in a hurry, and maybe I'll find time to do that 
on sunday or even tomorrow.

>
> //Peter
Thanks,
Harald
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From harald.gutmann at gmx.net  Fri Jul  3 16:55:13 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Fri, 3 Jul 2009 16:55:13 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <4A4D3185.9070001@assembler.cz>
References: <20090701142139.GA7679@flashgordon>
	<200907021958.47574.harald.gutmann@gmx.net>
	<4A4D3185.9070001@assembler.cz>
Message-ID: <200907031655.13924.harald.gutmann@gmx.net>

On Friday 03 July 2009 00:15:33 Rudolf Marek wrote:
> > Maybe Rudolf Marek can us help here, because he wrote the automatic
> > generation for that ACPI table (SSDT).
>
> Hi,
>
> If I understand correctly, the 1800MHz is missing? If so, please check what
> is the portal frequency for this CPU. Maybe it is 2000 and not 1800 (so
> prop bios is wrong). Check the BKDG. I'm very busy so I think better would
> be if someone else could check.
I'll also check this, to see if coreboot or vendor is wrong.
Thanks for you fast reply!

> The interupt driven parport works now?
Right now the parport is just working with polling.
But I think I can fix it to get it interrupt driven with a little dsdt.asl 
patch.

(Maybe sunday, or even towmorrow.)
>
> Rudolf
Regards,
Harald
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From info at Ivn.cl  Fri Jul  3 17:11:20 2009
From: info at Ivn.cl (Ivan Barrera A.)
Date: Fri, 03 Jul 2009 11:11:20 -0400
Subject: [coreboot] coreboot on Asus G1 ... Possible ?
In-Reply-To: <20090703013257.20601.qmail@stuge.se>
References: <4A4CFC11.4070609@Ivn.cl>
	<20090702184531.27293.qmail@stuge.se>	<4A4D00D8.2020503@Ivn.cl>
	<20090702193838.7170.qmail@stuge.se>	<4A4D1296.1020604@Ivn.cl>	<1246580635.30256.30.camel@localhost.localdomain>
	<20090703013257.20601.qmail@stuge.se>
Message-ID: <4A4E1F98.2060506@Ivn.cl>

Peter Stuge escribi?:
> Cristi Magherusan wrote:
>> I think this could be a good testcase for SerialICE
>> What do you think?
> 
> I think it's difficult to use SerialICE without a serial port. :\


Well... instead of keep trying to find a way to mentally use a serial 
port, ive decided this weekend to just give it a try.

Im compiling coreboot-v2 using FILO as a payload, and, integrating the 
video blob (rom) that ive got before. (and i was tinkering with).

1 weird thing :

  after compiling coreboot-v2 (rev 4397) , the make file in 
coreboot-v2/targets/kontron/986lcd-m/kontron_986lcd_m
incorrectly had ./cbfs/cbfstool ./coreboot.rom add-payload 
../payload.elf fallback/payload $(CBFS_COMPRESS_FLAG)
(../payload.elf) in line 43. This made make complain about 
../payload.elf beign an unknown target, and if put it there, cbfstool 
complained about not finding it. Just replaced with ./payload.elf.

I'll be tinkering with the dsdt.asl , to see if i can get my own for my 
laptop now.

Tomorrow (or the day after) i'll be opening my laptop yet again for 
cleaning. i'll let you know if i killed the laptop.. if it did 
something... or if it did nothing, but still looked cool :D


PS: I think (just think) it shoulndt matter if im using the laptop 
screen (lvds) or external monitor (dvi/vga) right ? or should i use only 
the lvds screen ?
PS1: In the event that coreboot loads, and filo does get executed but no 
screen or there is no visible sign of "work"... what could be a good 
idea to try ? (added some specs in the end of this mail)
PS2: The SST 49LF004B is 4mbit (512KB). How can i know what is the max 
size and type of chip i can put on it ? ive seen someone using a SST 
49LF160C on a motherboard that also used the 49LF004B.

My laptop has the following put on :

- 4GB Ram = 2x2GB same brand,speed,timings. Also have to test 2X512MB 
same everything.
- SSD Disk on Sata port 1.
- Cdrom unit on Ide port 1.
- Compact flash adapter on pcmcia port
- PCI sd/mmc reader (ricoh)
- Integrated r8169 network card.
- Integrated modem (dont know which.. never used it)
- lots of extra leds.
- USB ports... i have Lots of USB adapters.. serial, parallel (only 
printer mode), eth, bluetooth (integrated), oled display (integrated), etc.

   Ive contacted the vendor (Asus) many times before on the issue of 
bios recovery. They are not helpful on anything beside windows/software 
problems. (more than that... they havent been able to tell me how to 
access the bootblock on my bios, because some asus-media feature kicks 
in first)


> 
> 
> //Peter
> 




From uwe at hermann-uwe.de  Fri Jul  3 18:12:23 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Jul 2009 18:12:23 +0200
Subject: [coreboot] FlashROM on VIA EPIA EN12000EG
In-Reply-To: <20090620130022.32261.qmail@stuge.se>
References: <bdca99240906190337o790368e0m58a0c2b7ee058a6e@mail.gmail.com>
	<20090620130022.32261.qmail@stuge.se>
Message-ID: <20090703161223.GB24201@greenwood>

On Sat, Jun 20, 2009 at 03:00:22PM +0200, Peter Stuge wrote:
> Sebastian Schuberth wrote:
> > I don't know if it's even technically possible to distinguish the
> > CN and EN series, or if they are simply too close / almost
> > identical from a chipset etc. view,
> 
> Yep, they are.
> 
> 
> > but I'd be happy to help out improving this, if I can.
> 
> I think the solution is to just change the string, since the code
> does what it should.

Yeah, by now I agree that we'll want to use more generic names for the
board enable (-m) option, e.g. "epia-mxxx" or so.

However, the -L and -z flashrom output of tested/supported boards should
list the exact names of the tested boards. I have a patch in preparation
to do that, will send soonish.

Sebastian, if you have a chance to test whether write/erase works fine
on your board, please let us know so we can add "VIA EPIA EN12000EG"
as supported / not supported.

Please only try to erase/write if you have a way to recover (backup chip etc).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From svn at coreboot.org  Fri Jul  3 18:29:52 2009
From: svn at coreboot.org (coreboot)
Date: Fri, 03 Jul 2009 16:29:52 -0000
Subject: [coreboot] #134: flashrom crashes systems with WPC876x/WPCE775x
 embedded controller on LPC bus () (was: flashrom crashes systems with
 WPC876x/WPCE775x embedded controller on LPC bus)
In-Reply-To: <079.4f83eff2e689d10d548530ef42e0e66a@coreboot.org>
References: <079.4f83eff2e689d10d548530ef42e0e66a@coreboot.org>
Message-ID: <088.9686fa5e3ac1d6b75898e6607f3af5bc@coreboot.org>

#134: flashrom crashes systems with WPC876x/WPCE775x embedded controller on LPC
bus ()
------------------------------------------------------------+---------------
    Reporter:  Timo Juhani Lindfors <timo.lindfors@?>       |         Owner:  somebody                                     
        Type:  defect                                       |        Status:  closed                                       
    Priority:  minor                                        |     Milestone:                                               
   Component:  flashrom                                     |       Version:                                               
  Resolution:  wontfix                                      |      Keywords:  aspire laptop wpce775l ec embedded controller
Dependencies:                                               |   Patchstatus:  there is no patch                            
------------------------------------------------------------+---------------

Comment(by uwe):

 Replying to [comment:2 Timo Juhani Lindfors <timo.lindfors@?>]:
 > Service manual says that this laptop has WPCE775L EC that talks LPC v1.0
 and that the flash chips are behind it. Also on IRC I was adviced that
 >
 > < carldani> lindi-: can you please add a small statement to the ticket
 which mentions the exact EC and that it translates LPC to SPI.

 Hi, can you please tell us (just for reference) which Acer Aspire One
 model this is exactly? It seems there are multiple laptops/netbooks that
 are called Aspire One.

 (we want to fix the string in the list of non-supported laptops at
 http://www.coreboot.org/Flashrom#Supported_laptops.2Fnotebooks)

 Thanks!

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/134#comment:6>
coreboot <http://www.coreboot.org/>


From peter at stuge.se  Fri Jul  3 20:31:16 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 3 Jul 2009 20:31:16 +0200
Subject: [coreboot] [v2] r4394 - in
	trunk/coreboot-v2/src:	cpu/amd/sc520cpu/emulation/qemu-x86
	cpu/ppc/ppc4xx
	devices	include/devicenorthbridge/amd/amdfam10	northbridge/amd/amdk8northbridge/amd/gx1
	northbridge/amd/gx2	northbridge/amd/lxnorthbridge/ibm/cpc710 n
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1702D2B5A7@sbjgexmb1.amd.com>
References: <20090702185642.082A845005B@mail154-va3.bigfish.com>
	<DD1CC71B621B004FA76856E5129D6B1702D2B5A7@sbjgexmb1.amd.com>
Message-ID: <20090703183116.9946.qmail@stuge.se>

Bao, Zheng wrote:
> This patch makes my AMD fam10 board not work (K8 works). The
> resource can not be allocated correctly.

Thanks for the report!

Could you send debug output from the Fam10 system?


//Peter



From kevin at koconnor.net  Fri Jul  3 22:13:07 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Fri, 3 Jul 2009 16:13:07 -0400
Subject: [coreboot] Share my code of running vgabios(in CBFS) in	seabios
	when rusume from s3.
In-Reply-To: <9156F9F8217CD44898ABE1E581FAFF886A3247@exchbj02.viatech.com.bj>
References: <9156F9F8217CD44898ABE1E581FAFF886A3247@exchbj02.viatech.com.bj>
Message-ID: <20090703201307.GA6123@morn.localdomain>

On Fri, Jul 03, 2009 at 03:53:58PM +0800, JasonZhao at viatech.com.cn wrote:
> I work out some code to make seabios run vgabios when resuming from S3
> (follow your advice on IRC, again :) ). And it is unbelievable easy,
> only 2 step:

Great!

> Setp 1: In acpi.c
[...]
> +	//these two lines has same effect with the above two lines, and
> I don know 8f or 0f which is better. cmos_read/write in coreboot do not
> set bit 7.

SeaBIOS sets bit 7 in order to disable the NMI - it shouldn't hurt to
always set bit 7.

> Step 2: in seabios->resume.c->s3_resume()
>     smm_init();
> +   vga_setup();
>     make_bios_readonly();
>     u32 s3_resume_vector = find_resume_vector();

That should work, but it will recopy the rom - adding something like
the following to optionroms.c is probably safer:

void
s3_resume_vga_init()
{
    if (!CONFIG_S3_RESUME_VGA_INIT)
        return;
    struct rom_header *rom = (void*)OPTION_ROM_START;
    if (! is_valid_rom(rom))
        return;
    callrom(rom, OPTION_ROM_INITVECTOR, 0);
}

-Kevin



From mylesgw at gmail.com  Sat Jul  4 01:27:54 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 3 Jul 2009 17:27:54 -0600
Subject: [coreboot] [PATCH] v3 Resource allocator to v2
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1702D2B52F@sbjgexmb1.amd.com>
References: <C9163063016E42B78E446D11A3429A0E@chimp><2831fecf0905271525mb32bef9s7ded9f8d813f22e@mail.gmail.com><13426df10905271801k60c6c1c8l71ea74a846d91a20@mail.gmail.com>
	<2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B1702D2B52F@sbjgexmb1.amd.com>
Message-ID: <263C36659BF3451D9F3E24977D0CDD80@chimp>

> In SB600, the IOAPIC is allocated in sb600_sm.c. Is there any conflict
> with sb600_lpc.c?

It was just for backward compatibility.  I put a fixed allocation at
0xfec00000 in most boards because that's where it used to be.  If there's
nothing that needs to be protected there, you can remove it.  You'd probably
need one for the local APICs for the processors, though.

Sorry for the confusion.

Thanks,
Myles




From tiagomnm at gmail.com  Sat Jul  4 03:06:37 2009
From: tiagomnm at gmail.com (Tiago Marques)
Date: Sat, 4 Jul 2009 02:06:37 +0100
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <200907031655.13924.harald.gutmann@gmx.net>
References: <20090701142139.GA7679@flashgordon>
	<200907021958.47574.harald.gutmann@gmx.net>
	<4A4D3185.9070001@assembler.cz>
	<200907031655.13924.harald.gutmann@gmx.net>
Message-ID: <b1335fe90907031806h5eb26b6t87583258b944bd39@mail.gmail.com>

Hi,

One thing I would like to ask, not just regarding this motherboard but
all AM2/AM2+/AM3 boards.
Would it be possible to implement a feature that would allow us to
configure custom P-States to save on CMOS, other than what the
manufacturer specifies? Most BIOS allow setting lower and higher
multipliers than stock on some CPUs but disable CPU power management
altogether when doing so. It would be quite a leap forward, when
compared with vendor BIOS to be able to specify at least one VID and
FID for the high power state and another FID and VID for the low power
state.

With overclocking the benefits are enormous in the power bill and also
for the low power state, since the manufacturer specifies 1.1v @ 1GHz
and most CPUs handle 0.8v @ 800MHz quite easily. I'd love to get those
low power states on my home server :)

I've been trying to get hold of one of these M57SLI-S4 boards to try
and implement this but would like to know if this is something
possible to achieve with the current code base.

Best regards,
Tiago Marques


On Fri, Jul 3, 2009 at 3:55 PM, Harald Gutmann<harald.gutmann at gmx.net> wrote:
> On Friday 03 July 2009 00:15:33 Rudolf Marek wrote:
>> > Maybe Rudolf Marek can us help here, because he wrote the automatic
>> > generation for that ACPI table (SSDT).
>>
>> Hi,
>>
>> If I understand correctly, the 1800MHz is missing? If so, please check what
>> is the portal frequency for this CPU. Maybe it is 2000 and not 1800 (so
>> prop bios is wrong). Check the BKDG. I'm very busy so I think better would
>> be if someone else could check.
> I'll also check this, to see if coreboot or vendor is wrong.
> Thanks for you fast reply!
>
>> The interupt driven parport works now?
> Right now the parport is just working with polling.
> But I think I can fix it to get it interrupt driven with a little dsdt.asl
> patch.
>
> (Maybe sunday, or even towmorrow.)
>>
>> Rudolf
> Regards,
> Harald
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From uwe at hermann-uwe.de  Sat Jul  4 04:08:37 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 4 Jul 2009 04:08:37 +0200
Subject: [coreboot] r4394 breaks on hardware (was: Re: [PATCH] v3 Resource
 allocator to v2)
In-Reply-To: <2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>
References: <C9163063016E42B78E446D11A3429A0E@chimp>
	<2831fecf0905271525mb32bef9s7ded9f8d813f22e@mail.gmail.com>
	<13426df10905271801k60c6c1c8l71ea74a846d91a20@mail.gmail.com>
	<2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>
Message-ID: <20090704020837.GC24201@greenwood>

On Thu, Jul 02, 2009 at 12:58:57PM -0600, Myles Watson wrote:
> On Wed, May 27, 2009 at 7:01 PM, ron minnich <rminnich at gmail.com> wrote:
> 
> >
> > Acked-by: Ronald G. Minnich <rminnich at gmail.com>
> >
> 
> Rev 4394.

This patch seems to cause trouble, at least on the Kontron board where I
tested recent trunk, but probably on other systems also I'd guess.

r4393 works fine, r4394 is the first broken revision.

What I see is a module not loading correctly (r8169), and a hard hang
later in the boot process (after blacklisting the r8169 module). It
seems the hang is caused by intel_agp or agpgart, not sure.

Attached is a log from the Kontron board using both r4393 and r4394.
The diff shows quite a lot of resource allocation changes, not sure
which of those is relevant and is causing the problems.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From andi.mundt at web.de  Sat Jul  4 08:06:03 2009
From: andi.mundt at web.de (Andreas B. Mundt)
Date: Sat, 4 Jul 2009 08:06:03 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702195231.GA5717@flashgordon>
References: <20090701142139.GA7679@flashgordon>
	<20090702155630.GA10928@flashgordon>
	<a06e08f95d2f5f58727826150ac44fb5@imap.1and1.com>
	<20090702195231.GA5717@flashgordon>
Message-ID: <20090704060603.GA5211@flashgordon>

Hi,

the patch below allows for interrupt driven parport usage (even when
CONFIG_PARPORT_PC_SUPERIO is not set in the kernel config). It has
been prepared with Rudolf's help on IRC. Please test and/or improve!

According to Rudolf, it would be better better to code something in
ACPI code which will get the resource info from hardware, or
alternatively, the superiocode should generate some simple acpi code.

from dmesg:
lp0: using parport0 (interrupt-driven).


Signed-off-by: Anreas B. Mundt <andi.mundt at web.de>

Regards, 
	 Andi   
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From mike at fireburn.co.uk  Sat Jul  4 10:17:13 2009
From: mike at fireburn.co.uk (Mike Lothian)
Date: Sat, 4 Jul 2009 09:17:13 +0100
Subject: [coreboot] Replacing Faulty Laptop BIOS
Message-ID: <f3f71ab90907040117x191f3209pe8092624f8564303@mail.gmail.com>

Hi

The BIOS on my Samsung R510 is faulty and causes major issues under ANY 64bit OS

As the laptop has 4G of RAM it' either I use 32bit OS and loose some
or suffer the consequences

If the laptop if unplugged (or plugged in) this causes an instant
reboot. I'm also unable to control the screen brighness.

I think the BIOS maybe using the 3-4GB range perhaps causing the reboot

As I said previously this effects all 64bit OSs (Vista and W7
included) and Samsung have shown no interest in fixing the problem

Is there a way to test out coreboot to see if it could replace my BIOS?

It's an Intel 4 series chipset.

Thanks in advance for any advice or pointers to HOWTOs you can provide

Cheers

Mike



From harald.gutmann at gmx.net  Sat Jul  4 11:02:36 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Sat, 4 Jul 2009 11:02:36 +0200
Subject: [coreboot] ACPI on m57sli v1.0
In-Reply-To: <20090702212634.3905.qmail@stuge.se>
References: <20090701142139.GA7679@flashgordon>
	<200907022202.08049.harald.gutmann@gmx.net>
	<20090702212634.3905.qmail@stuge.se>
Message-ID: <200907041102.44250.harald.gutmann@gmx.net>

On Thursday 02 July 2009 23:26:34 Peter Stuge wrote:
> Harald Gutmann wrote:
> > > Is the port interrupt-driven, or polling, on your system, Andreas?
> >
> > Here on my system it says also polling, like on Andreas system.
> > What is the difference between interrupt driven and polling?
>
> Interrupt driven means the port has an interrupt assigned to it, and
> that communication over the port is event based.
>
> Polling means there is a timer running in the kernel which will check
> the port for activity every few milliseconds or something.
>
> > On vendor bios it is interrupt-driven.
> > Is an ACPI part missing to get it interrupt driven?
>
> I think so, yes.
So, I've added the missing ACPI part, but it seems that some more work is 
needed to get parport interrupt driven working.

The dmesg output changes a little bit, and also mentions IRQ7, but lp0 is 
still noticed as polling:
[  745.974254] parport_pc 00:04: reported by Plug and Play ACPI
[  745.974371] parport0: PC-style at 0x378 (0x778) [PCSPP,TRISTATE]
[  746.104129] parport0: irq 7 detected
[  751.914593] ppdev: user-space parallel port driver
[  770.953504] lp0: using parport0 (polling).

I think that it is necessary to set some irq bit to get it working fine. This 
idea is from the vendors dsdt.asl [1] and the LPT1 (starting at line 5374) 
section of it.
Looking at that part there is something noticed about INTR which could be the 
IRQ bit I assume that this is needed.

Can anyone help me out here a little bit?

[1] http://coreboot.pastebin.com/f3e965943


Kind regards,
Harald


>
> //Peter

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From peter at stuge.se  Sat Jul  4 14:09:28 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 4 Jul 2009 14:09:28 +0200
Subject: [coreboot] Share my code of running vgabios(in CBFS) in	seabios
	when rusume from s3.
In-Reply-To: <20090703201307.GA6123@morn.localdomain>
References: <9156F9F8217CD44898ABE1E581FAFF886A3247@exchbj02.viatech.com.bj>
	<20090703201307.GA6123@morn.localdomain>
Message-ID: <20090704120928.23996.qmail@stuge.se>

Kevin O'Connor wrote:
> void
> s3_resume_vga_init()
> {
>     if (!CONFIG_S3_RESUME_VGA_INIT)
>         return;
>     struct rom_header *rom = (void*)OPTION_ROM_START;
>     if (! is_valid_rom(rom))
>         return;
>     callrom(rom, OPTION_ROM_INITVECTOR, 0);
> }

Would this remove the need for the acpi=s3_bios kernel parameter?

I guess this is doing the same thing?


//Peter



From kevin at koconnor.net  Sat Jul  4 17:47:41 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 4 Jul 2009 11:47:41 -0400
Subject: [coreboot] Share my code of running vgabios(in CBFS) in	seabios
	when rusume from s3.
In-Reply-To: <20090704120928.23996.qmail@stuge.se>
References: <9156F9F8217CD44898ABE1E581FAFF886A3247@exchbj02.viatech.com.bj>
	<20090703201307.GA6123@morn.localdomain>
	<20090704120928.23996.qmail@stuge.se>
Message-ID: <20090704154741.GA9152@morn.localdomain>

On Sat, Jul 04, 2009 at 02:09:28PM +0200, Peter Stuge wrote:
> Kevin O'Connor wrote:
> > void
> > s3_resume_vga_init()
> > {
> >     if (!CONFIG_S3_RESUME_VGA_INIT)
> >         return;
> >     struct rom_header *rom = (void*)OPTION_ROM_START;
> >     if (! is_valid_rom(rom))
> >         return;
> >     callrom(rom, OPTION_ROM_INITVECTOR, 0);
> > }
> 
> Would this remove the need for the acpi=s3_bios kernel parameter?
> 
> I guess this is doing the same thing?

I think it is doing the same thing.  I committed the above code to
seabios, but I left it disabled by default.

Jason, if you use "acpi=s3_bios" does it work without running the rom
from seabios?

-Kevin



From sschuberth at gmail.com  Fri Jul  3 23:15:36 2009
From: sschuberth at gmail.com (Sebastian Schuberth)
Date: Fri, 3 Jul 2009 23:15:36 +0200
Subject: [coreboot] FlashROM on VIA EPIA EN12000EG
In-Reply-To: <20090703161223.GB24201@greenwood>
References: <bdca99240906190337o790368e0m58a0c2b7ee058a6e@mail.gmail.com>
	<20090620130022.32261.qmail@stuge.se>
	<20090703161223.GB24201@greenwood>
Message-ID: <bdca99240907031415y731cc19bpa7fc6b6f781c300a@mail.gmail.com>

>> I think the solution is to just change the string, since the code
>> does what it should.
>
> Yeah, by now I agree that we'll want to use more generic names for the
> board enable (-m) option, e.g. "epia-mxxx" or so.
>
> However, the -L and -z flashrom output of tested/supported boards should
> list the exact names of the tested boards. I have a patch in preparation
> to do that, will send soonish.

So will your patch avoid the need to also mention the EPIA "EN" series
where currently only the "CN" series is mentioned?

> Sebastian, if you have a chance to test whether write/erase works fine
> on your board, please let us know so we can add "VIA EPIA EN12000EG"
> as supported / not supported.
>
> Please only try to erase/write if you have a way to recover (backup chip etc).

I'm sorry, as I have no way to recover I back away from testing write
support, but I can confirm reading seems to work just fine.

PS: Please CC me in replies as I'm not subscribed to the list.

-- 
Sebastian Schuberth



From Cristi.Magherusan at net.utcluj.ro  Sat Jul  4 23:27:18 2009
From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Sun, 05 Jul 2009 00:27:18 +0300
Subject: [coreboot] Replacing Faulty Laptop BIOS
In-Reply-To: <f3f71ab90907040117x191f3209pe8092624f8564303@mail.gmail.com>
References: <f3f71ab90907040117x191f3209pe8092624f8564303@mail.gmail.com>
Message-ID: <1246742838.31311.47.camel@localhost.localdomain>

Hello,

On Sat, 2009-07-04 at 09:17 +0100, Mike Lothian wrote:
> Hi
> 
> The BIOS on my Samsung R510 is faulty and causes major issues under ANY 64bit OS
> 
> As the laptop has 4G of RAM it' either I use 32bit OS and loose some
> or suffer the consequences
> 
> If the laptop if unplugged (or plugged in) this causes an instant
> reboot. I'm also unable to control the screen brighness.
> 
> I think the BIOS maybe using the 3-4GB range perhaps causing the reboot
32 bit OSes are limited to 3GB, unless you are using a kernel with PAE
support. This thread provides a quite good explanation:
http://lists.us.dell.com/pipermail/linux-poweredge/2006-August/026795.html
For more you can read the wikipedia page about PAE.

> As I said previously this effects all 64bit OSs (Vista and W7
> included) and Samsung have shown no interest in fixing the problem
> 
> Is there a way to test out coreboot to see if it could replace my BIOS?
Laptops are very tricky to work with, since they usually have some
special chips (called ECs) which do all kind of funky stuff. Those are
barely documented, if at all, so it's quite unlikely to support them,
unless you can invest a few months/years of work to get it done...
Coreboot is a work in progress, current versions work on a few
dozens/hundreds of desktop boards, and most of the time with incomplete
feature support, so don't expect too much of it either.

Also, you should be ready to hack your hardware (like soldering a socket
onto it - http://www.coreboot.org/Soldering_a_socket_on_your_board),
which will void your warranty, ofcourse.

Anyway, I didn't meant to discourage you. Feel free to browse our wiki
and read some docs about porting coreboot to a new platform, maybe you 
will get prepared to do it, but only attempt to do it after you have a
good backup plan and be aware of what can happen by reading the
documentation first.

Here you have some links that worth reading:
http://www.coreboot.org/Documentation
http://www.coreboot.org/Supported_Chipsets_and_Devices
http://www.coreboot.org/Developer_Manual

> It's an Intel 4 series chipset.
> 
> Thanks in advance for any advice or pointers to HOWTOs you can provide
> 
> Cheers
> 
> Mike
> 
Regards,
Cristi

-- 
Ing. Cristi M?gheru?an, System/Network Engineer
Technical University of Cluj-Napoca, Romania
http://cc.utcluj.ro  +40264 401247
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From mgold at ncf.ca  Sat Jul  4 23:36:20 2009
From: mgold at ncf.ca (Michael Gold)
Date: Sat, 4 Jul 2009 17:36:20 -0400
Subject: [coreboot] [PATCH] Add Mitac 6513WU mainboard support
Message-ID: <20090704213620.GA25256@iria.rilmarder.org>

This patch adds support for the Mitac 6513WU mainboard, a Compaq OEM
board using the i810 chipset.  Not all hardware has been tested, but my
test PC boots Linux (via FILO) without any problems.

The configuration leaves 32 kB for the video BIOS, but the onboard video
isn't currently working due to known problems with this chipset.

Signed-off-by: Michael Gold <mgold at ncf.ca>
---
(At Uwe's suggestion, I've based this on r4393, but hopefully it will
still apply.)
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From mylesgw at gmail.com  Sun Jul  5 03:41:09 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Sat, 4 Jul 2009 19:41:09 -0600
Subject: [coreboot] r4394 breaks on hardware (was: Re: [PATCH] v3
	Resource allocator to v2)
In-Reply-To: <20090704020837.GC24201@greenwood>
References: <C9163063016E42B78E446D11A3429A0E@chimp>
	<2831fecf0905271525mb32bef9s7ded9f8d813f22e@mail.gmail.com>
	<13426df10905271801k60c6c1c8l71ea74a846d91a20@mail.gmail.com>
	<2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>
	<20090704020837.GC24201@greenwood>
Message-ID: <6726B07F2AB2414BB7BA7AEA6234C9AE@chimp>

> > Rev 4394.
> 
> This patch seems to cause trouble, at least on the Kontron board where I
> tested recent trunk, but probably on other systems also I'd guess.
It could be, but the problem you're seeing is Kontron-specific.

Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.

This BAR is added in a way that the allocator doesn't understand.  That was
done on purpose because the old allocator didn't avoid fixed resources.
There are several proposed fixes, but it isn't clear what the best one is.

You can chime in.  Here are some possible solutions:
1. Let the allocator place the BAR.
	Care would need to be taken when the BAR was set and the value would
have to be passed to the ACPI code.

2. Mark the resource as fixed and let the allocator avoid it.
	Either you lose a significant portion of the address space or you
have to move it.  I think you could move it to 0xf8000000-0xfc000000.

3. Add a PCI hole option to the resource allocator and manually allocate
things that you want to live there.

> r4393 works fine, r4394 is the first broken revision.

Sorry about that.

Thanks,
Myles




From svn at coreboot.org  Sun Jul  5 17:50:30 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Jul 2009 17:50:30 +0200
Subject: [coreboot] [v2] r4398 -
	trunk/coreboot-v2/src/northbridge/intel/i82810
Message-ID: <mailman.3517.1355071592.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-07-05 17:50:30 +0200 (Sun, 05 Jul 2009)
New Revision: 4398

Modified:
   trunk/coreboot-v2/src/northbridge/intel/i82810/i82810.h
   trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
   trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c
Log:
Various Intel 82810/82810E changes which allow onboard VGA to work.
At the same time also make the 82810 code handle 82810E.

 - Set SMRAM register according to CONFIG_VIDEO_MB value:
    - 512 means 512 KB
    - 1 means 1 MB
    - Every other value for CONFIG_VIDEO_MB (e.g. 0) disables VGA.
   This is not very clean, changing CONFIG_VIDEO_MB to CONFIG_VIDEO_KB
   in a future patch may be nicer.

 - Set MISSC2 register bits as required per datasheet to make VGA work.
   The code handles both 82810 and 82810E.

 - northbridge.c: Add __pci_driver entry for the Intel 82810E.

Also:

 - Rename PAM register #define to PAMR as per datasheet.

 - Drop unused/commented code for now.

 - Don't explicitly set GMCHCFG for now, the default works ok. We'll
   have to figure out the proper/ideal settings later.

The code is based on a patch from Elia Yehuda <z4ziggy at gmail.com> but
has been modified quite a bit for correctness and minimalism.

Tested on hardware with a slightly modified MS-6178 target,
patches to enable onboard-VGA for MS-6178 will follow.

Signed-off-by: Elia Yehuda <z4ziggy at gmail.com>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/i82810.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/i82810.h	2009-07-02 21:19:33 UTC (rev 4397)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/i82810.h	2009-07-05 15:50:30 UTC (rev 4398)
@@ -35,7 +35,7 @@
  */
 
 #define GMCHCFG	0x50		/* GMCH Configuration */
-#define PAM	0x51		/* Programmable Attributes */
+#define PAMR	0x51		/* Programmable Attributes */
 #define DRP	0x52		/* DRAM Row Population */
 #define DRAMT	0x53		/* DRAM Timing */
 #define FDHC	0x58		/* Fixed DRAM Hole Control */

Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c	2009-07-02 21:19:33 UTC (rev 4397)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c	2009-07-05 15:50:30 UTC (rev 4398)
@@ -46,12 +46,20 @@
 	.ops_pci		= 0,
 };
 
-static const struct pci_driver northbridge_driver __pci_driver = {
+/* Intel 82810/82810-DC100 */
+static const struct pci_driver i810_northbridge_driver __pci_driver = {
 	.ops	= &northbridge_operations,
 	.vendor	= PCI_VENDOR_ID_INTEL,
 	.device	= 0x7120,
 };
 
+/* Intel 82810E */
+static const struct pci_driver i810e_northbridge_driver __pci_driver = {
+	.ops    = &northbridge_operations,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x7124,
+};
+
 static void ram_resource(device_t dev, unsigned long index,
 			 unsigned long basek, unsigned long sizek)
 {
@@ -139,6 +147,19 @@
 		/* Convert tomk from MB to KB. */
 		tomk = tomk << 10;
 
+#ifdef CONFIG_VIDEO_MB
+		/* Check for VGA reserved memory. */
+		if (CONFIG_VIDEO_MB == 512) {
+			tomk -= 512;
+			printk_debug("Allocating %s RAM for VGA\n", "512KB");
+		} else if (CONFIG_VIDEO_MB == 1) {
+			tomk -= 1024 ;
+			printk_debug("Allocating %s RAM for VGA\n", "1MB");
+		} else {
+			printk_debug("Allocating %s RAM for VGA\n", "0MB");
+		}
+#endif
+
 		/* Compute the top of Low memory. */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {

Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c	2009-07-02 21:19:33 UTC (rev 4397)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c	2009-07-05 15:50:30 UTC (rev 4398)
@@ -1,9 +1,9 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007-2008 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2007-2009 Uwe Hermann <uwe at hermann-uwe.de>
  * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
- * Copyright (C) 2008 Elia Yehuda <z4ziggy at gmail.com>
+ * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -360,45 +360,33 @@
 
 static void sdram_set_registers(void)
 {
-	unsigned long val;
+	u8 reg8;
+	u16 reg16, did;
 
-	/* TODO */
-	pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, 0x60);
+	did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
 
-	/* PAMR: Programmable Attributes Register
-	 * Every pair of bits controls an address range:
-	 * 00 = Disabled, all accesses are forwarded to the ICH
-	 * 01 = Read Only
-	 * 10 = Write Only
-	 * 11 = Read/Write
-
-	 * Bit  Range
-	 * 7:6  000F0000 - 000FFFFF
-	 * 5:4  000E0000 - 000EFFFF
-	 * 3:2  000D0000 - 000DFFFF
-	 * 1:0  000C0000 - 000CFFFF
-	 */
-
 	/* Ideally, this should be R/W for as many ranges as possible. */
-	pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0xff);
-
-	/* Enabling the VGA Framebuffer currently screws up the rest of the boot.
-	 * Disable for now */
+	pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
 	
-	/* Enable 1MB framebuffer. */
-	//pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, 0xC0);
+	/* Set size for onboard-VGA framebuffer. */
+	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
+	reg8 &= 0x3f;			     /* Disable graphics (for now). */
+	if (CONFIG_VIDEO_MB == 512)
+		reg8 |= (1 << 7);	     /* Enable graphics (512KB RAM). */
+	else if (CONFIG_VIDEO_MB == 1)
+		reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */
+	pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8);
 
-	//val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC);
-	/* Preserve reserved bits. */
-	//val &= 0xff06;
-	/* Set graphics cache window to 32MB, no power throttling. */
-	//val |= 0x0001;
-	//pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val);
-
-	//val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
-	/* Enable graphics palettes and clock gating (not optional!) */
-	//val |= 0x06;
-	//pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val);
+	/* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */
+	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
+	reg8 |= (1 << 1); /* Instruction Parser Unit-Level Clock Gating */
+	reg8 |= (1 << 2); /* Palette Load Select */
+	if (did == 0x7124) {
+		/* Bits 6 and 7 are only available on 82810E (not 82810). */
+		reg8 |= (1 << 6); /* Text Immediate Blit */
+		reg8 |= (1 << 7); /* Must be 1 as per datasheet. */
+	}
+	pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
 }
 
 static void sdram_set_spd_registers(void)
@@ -437,7 +425,7 @@
 	do_ram_command(RAM_COMMAND_MRS);
 	udelay(2);
 
-	/* 5. Normal operation (enables refresh) */
+	/* 5. Normal operation (enables refresh at 15.6usec). */
 	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
 	do_ram_command(RAM_COMMAND_NORMAL);
 	udelay(1);




From svn at coreboot.org  Sun Jul  5 18:01:57 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Jul 2009 18:01:57 +0200
Subject: [coreboot] [v2] r4399 - in trunk/coreboot-v2:
	src/mainboard/msi/ms6178 targets/msi/ms6178
Message-ID: <mailman.3518.1355071592.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-07-05 18:01:57 +0200 (Sun, 05 Jul 2009)
New Revision: 4399

Modified:
   trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c
   trunk/coreboot-v2/targets/msi/ms6178/Config.lb
Log:
Enable onboard VGA on the MS-6178 (i810 chipset) board (trivial).

Tested on hardware with the patch from r4398 and works fine as soon
as Linux boots (no VGA in FILO for some reason, will investigate).

In order to make the 'i810.vga' VGA blob from the vendor BIOS work
you have to make the check for PCI device ID mismatches non-fatal
(for now) in the src/devices/pci_rom.c file like this:

Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c       (Revision 4393)
+++ src/devices/pci_rom.c       (Arbeitskopie)
@@ -87,7 +87,7 @@
        if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
                printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
                           rom_data->vendor, rom_data->device);
-               return NULL;
+               // return NULL;
        }

        printk_spew("PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",

The reason is that the VGA blob thinks the proper VGA device ID is 0x7123
whereas it really is 0x7121 on hardware. There are multiple ways to work
around this (there have been many discussions in the past), we'll see which
method will be used in future...

Note: This has been tested against r4393 only for now to make sure there
are no problems because of the recent resource allocator changes, see
http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html.
Tests with trunk will follow.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb	2009-07-05 15:50:30 UTC (rev 4398)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb	2009-07-05 16:01:57 UTC (rev 4399)
@@ -77,11 +77,9 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      #   register "rom_address" = "0xfff80000"
-      # end
+    chip drivers/pci/onboard			# Onboard VGA
+      device pci 1.0 on end
+      register "rom_address" = "0xfff80000"	# 512 KB image
     end
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb	2009-07-05 15:50:30 UTC (rev 4398)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb	2009-07-05 16:01:57 UTC (rev 4399)
@@ -65,6 +65,7 @@
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_HAVE_HIGH_TABLES
+uses CONFIG_VIDEO_MB
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_HAVE_FALLBACK_BOOT = 1
@@ -98,4 +99,5 @@
 default CONFIG_PCI_ROM_RUN = 1
 default CONFIG_CBFS = 1
 default CONFIG_HAVE_HIGH_TABLES = 1
+default CONFIG_VIDEO_MB = 1
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c	2009-07-05 15:50:30 UTC (rev 4398)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c	2009-07-05 16:01:57 UTC (rev 4399)
@@ -36,6 +36,7 @@
 #include "cpu/x86/bist.h"
 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
 #include "pc80/udelay_io.c"
+#include "lib/debug.c"
 #include "northbridge/intel/i82810/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/coreboot-v2/targets/msi/ms6178/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/msi/ms6178/Config.lb	2009-07-05 15:50:30 UTC (rev 4398)
+++ trunk/coreboot-v2/targets/msi/ms6178/Config.lb	2009-07-05 16:01:57 UTC (rev 4399)
@@ -33,6 +33,7 @@
 
 option CONFIG_CONSOLE_VGA = 1
 option CONFIG_PCI_ROM_RUN = 1
+option CONFIG_VIDEO_MB = 1
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE = 0
@@ -48,5 +49,5 @@
 
 buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
 
-# pci_rom i810.vga vendor_id=0x8086 device_id=0x7120
+pci_rom /tmp/i810.vga vendor_id=0x8086 device_id=0x7121
 




From uwe at hermann-uwe.de  Sun Jul  5 18:06:36 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 5 Jul 2009 18:06:36 +0200
Subject: [coreboot] [patch] fix intel 82810 onboard VGA and SDRAM
 functions
In-Reply-To: <20090605002708.GE18065@greenwood>
References: <e19d85410905100521w123c5f68h11ab2e0ba34c0614@mail.gmail.com>
	<4f024cb6dadc710e0f0d4f7a8fcec73c@imap.1and1.com>
	<e19d85410905211754j580da3b5v2caea2cfdeeb429e@mail.gmail.com>
	<20090605002708.GE18065@greenwood>
Message-ID: <20090705160636.GA31506@greenwood>

Hi,

On Fri, Jun 05, 2009 at 02:27:09AM +0200, Uwe Hermann wrote:
> Haven't had much luck with the HIGH_TABLES stuff yet, need to look into
> it some more, will post the remainders of the patch (without the
> now-committed BUFF_SC parts) later and/or check what's going on with
> HIGH_TABLES...

OK, I've just committed (somewhat) working VGA support in r4398 for
82810 and 82810E and enabled it for my test board (MS-6178) in r4399.

http://www.coreboot.org/pipermail/coreboot/2009-July/050496.html
http://www.coreboot.org/pipermail/coreboot/2009-July/050497.html

The VGA support is probably not perfect, yet, I'll do some more testing
and fixing.

Please let me know if this also works on your 82810E board (it should)
and/or if it needs additional patching.

So far I see no problems with enabled HIGH_TABLES, will try SeaBIOS
soon, and also compare the logs of enabled/disabled HIGH_TABLES to
make sure everything works fine.


Cheers, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From info at coresystems.de  Sun Jul  5 18:12:21 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Jul 2009 18:12:21 +0200
Subject: [coreboot] build service results for r4398
Message-ID: <E1MNUKD-0008Pg-Ks@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 4398 to
the coreboot repository. This caused the following 
changes:

Change Log:
Various Intel 82810/82810E changes which allow onboard VGA to work.
At the same time also make the 82810 code handle 82810E.

 - Set SMRAM register according to CONFIG_VIDEO_MB value:
    - 512 means 512 KB
    - 1 means 1 MB
    - Every other value for CONFIG_VIDEO_MB (e.g. 0) disables VGA.
   This is not very clean, changing CONFIG_VIDEO_MB to CONFIG_VIDEO_KB
   in a future patch may be nicer.

 - Set MISSC2 register bits as required per datasheet to make VGA work.
   The code handles both 82810 and 82810E.

 - northbridge.c: Add __pci_driver entry for the Intel 82810E.

Also:

 - Rename PAM register #define to PAMR as per datasheet.

 - Drop unused/commented code for now.

 - Don't explicitly set GMCHCFG for now, the default works ok. We'll
   have to figure out the proper/ideal settings later.

The code is based on a patch from Elia Yehuda <z4ziggy at gmail.com> but
has been modified quite a bit for correctness and minimalism.

Tested on hardware with a slightly modified MS-6178 target,
patches to enable onboard-VGA for MS-6178 will follow.

Signed-off-by: Elia Yehuda <z4ziggy at gmail.com>
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of asus:mew-am has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4398&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4398&device=mew-vm&vendor=asus&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4398&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6178 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4398&device=ms6178&vendor=msi&num=2
Compilation of nec:powermate2000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4398&device=powermate2000&vendor=nec&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4398&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sun Jul  5 18:23:43 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Jul 2009 18:23:43 +0200
Subject: [coreboot] [v2] r4400 -
	trunk/coreboot-v2/src/northbridge/intel/i82810
Message-ID: <mailman.3519.1355071592.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-07-05 18:23:43 +0200 (Sun, 05 Jul 2009)
New Revision: 4400

Modified:
   trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c
Log:
Fix build for i810 boards that don't enable onboard VGA, yet.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c	2009-07-05 16:01:57 UTC (rev 4399)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c	2009-07-05 16:23:43 UTC (rev 4400)
@@ -371,10 +371,12 @@
 	/* Set size for onboard-VGA framebuffer. */
 	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
 	reg8 &= 0x3f;			     /* Disable graphics (for now). */
+#ifdef CONFIG_VIDEO_MB
 	if (CONFIG_VIDEO_MB == 512)
 		reg8 |= (1 << 7);	     /* Enable graphics (512KB RAM). */
 	else if (CONFIG_VIDEO_MB == 1)
 		reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */
+#endif
 	pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8);
 
 	/* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */




From info at coresystems.de  Sun Jul  5 18:43:40 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Jul 2009 18:43:40 +0200
Subject: [coreboot] build service results for r4399
Message-ID: <E1MNUoW-0001gm-QY@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 4399 to
the coreboot repository. This caused the following 
changes:

Change Log:
Enable onboard VGA on the MS-6178 (i810 chipset) board (trivial).

Tested on hardware with the patch from r4398 and works fine as soon
as Linux boots (no VGA in FILO for some reason, will investigate).

In order to make the 'i810.vga' VGA blob from the vendor BIOS work
you have to make the check for PCI device ID mismatches non-fatal
(for now) in the src/devices/pci_rom.c file like this:

Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c       (Revision 4393)
+++ src/devices/pci_rom.c       (Arbeitskopie)
@@ -87,7 +87,7 @@
        if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
                printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
                           rom_data->vendor, rom_data->device);
-               return NULL;
+               // return NULL;
        }

        printk_spew("PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",

The reason is that the VGA blob thinks the proper VGA device ID is 0x7123
whereas it really is 0x7121 on hardware. There are multiple ways to work
around this (there have been many discussions in the past), we'll see which
method will be used in future...

Note: This has been tested against r4393 only for now to make sure there
are no problems because of the recent resource allocator changes, see
http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html.
Tests with trunk will follow.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of asus:mew-am is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4399&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4399&device=mew-vm&vendor=asus&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4399&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of msi:ms6178 has been fixed
Compilation of nec:powermate2000 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4399&device=powermate2000&vendor=nec&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4399&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sun Jul  5 19:15:38 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Jul 2009 19:15:38 +0200
Subject: [coreboot] build service results for r4400
Message-ID: <E1MNVJS-0003e3-Nx@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 4400 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix build for i810 boards that don't enable onboard VGA, yet.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of asus:mew-am has been fixed
Compilation of asus:mew-vm has been fixed
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4400&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of nec:powermate2000 has been fixed
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4400&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sun Jul  5 21:29:39 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  5 Jul 2009 21:29:39 +0200
Subject: [coreboot] [v2] r4401 - in trunk/coreboot-v2: src/mainboard
	src/mainboard/mitac src/mainboard/mitac/6513wu
	src/superio/smsc/smscsuperio targets targets/mitac
	targets/mitac/6513wu
Message-ID: <mailman.3520.1355071592.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-07-05 21:29:39 +0200 (Sun, 05 Jul 2009)
New Revision: 4401

Added:
   trunk/coreboot-v2/src/mainboard/mitac/
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/Config.lb
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/chip.h
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/irq_tables.c
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/mainboard.c
   trunk/coreboot-v2/targets/mitac/
   trunk/coreboot-v2/targets/mitac/6513wu/
   trunk/coreboot-v2/targets/mitac/6513wu/Config.lb
Modified:
   trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c
Log:
Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the
i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.

Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.

Signed-off-by: Michael Gold <mgold at ncf.ca>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Config.lb	2009-07-05 19:29:39 UTC (rev 4401)
@@ -0,0 +1,142 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+arch i386 end
+driver mainboard.o
+if CONFIG_HAVE_PIRQ_TABLE
+	object irq_tables.o
+end
+makerule ./failover.E
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
+	action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
+	action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if CONFIG_USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i82810           # Northbridge
+  device apic_cluster 0 on              # APIC cluster
+    chip cpu/intel/socket_PGA370        # CPU
+      device apic 0 on end              # APIC
+    end
+  end
+  device pci_domain 0 on                # PCI domain
+    device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
+    chip drivers/pci/onboard
+      device pci 1.0 on end
+      register "rom_address" = "0xfff80000" # 512 KB image
+    end
+    chip southbridge/intel/i82801xx     # Southbridge
+      register "pirqa_routing" = "0x03"
+      register "pirqb_routing" = "0x05"
+      register "pirqc_routing" = "0x09"
+      register "pirqd_routing" = "0x0b"
+
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1e.0 on                # PCI bridge
+        device pci 5.0 on end           # Audio controller (ESS ES1988)
+      end
+      device pci 1f.0 on                # ISA bridge
+        chip superio/smsc/smscsuperio   # Super I/O (SMSC LPC47U332)
+          device pnp 4e.0 on            # Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 4e.3 on            # Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 4e.4 on            # COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 4e.5 on            # MIDI port (MPU-401)
+            io 0x60 = 0x330
+            irq 0x70 = 10
+          end
+          device pnp 4e.7 on            # PS/2 keyboard / mouse
+            io 0x60 = 0x60              # XXX: not relocatable
+            io 0x62 = 0x64              # XXX: not relocatable
+            irq 0x70 = 1                # PS/2 keyboard interrupt
+            irq 0x72 = 12               # PS/2 mouse interrupt
+          end
+          device pnp 4e.9 on            # Game port
+            io 0x60 = 0x201
+          end
+          device pnp 4e.a on            # Runtime registers
+            io 0x60 = 0x400
+          end
+          device pnp 4e.b off end       # SMBus
+        end
+      end
+      device pci 1f.1 on end            # IDE
+      device pci 1f.2 on end            # USB
+      device pci 1f.3 on end            # SMbus
+      device pci 1f.5 off end           # Audio controller
+      device pci 1f.6 off end           # Modem
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb	2009-07-05 19:29:39 UTC (rev 4401)
@@ -0,0 +1,110 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses CC
+uses CONFIG_CBFS
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_OBJCOPY
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_RAMBASE
+uses CONFIG_ROMBASE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_ROM_SECTION_OFFSET
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_XIP_ROM_SIZE
+uses COREBOOT_EXTRA_VERSION
+uses HOSTCC
+
+# Motherboard info, tables, etc.
+default CONFIG_MAINBOARD_VENDOR = "Mitac"
+default CONFIG_MAINBOARD_PART_NUMBER = "6513WU"
+default CONFIG_IRQ_SLOT_COUNT = 8
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_USE_OPTION_TABLE = 0
+
+# ROM layout
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_FALLBACK_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_ROM_PAYLOAD = 1
+default CONFIG_CBFS = 0
+
+# RAM layout
+default CONFIG_RAMBASE = 0x00004000
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+
+# Misc. settings
+default CONFIG_USE_INIT = 0
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+
+# Compiler setup
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+
+# Console settings
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3     # 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7  # No debugging/spew
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+# Enable onboard video
+default CONFIG_CONSOLE_VGA = 1
+default CONFIG_PCI_ROM_RUN = 1
+
+end

Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/auto.c	2009-07-05 19:29:39 UTC (rev 4401)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "northbridge/intel/i82810/raminit.h"
+#include "lib/debug.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i82810/raminit.c"
+/* #include "northbridge/intel/i82810/debug.c" */
+
+static void main(unsigned long bist)
+{
+	if (bist == 0)
+		early_mtrr_init();
+
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	report_bist_failure(bist);
+	enable_smbus();
+	/* dump_spd_registers(); */
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+	/* ram_check(0, 640 * 1024); */
+}

Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/chip.h	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/chip.h	2009-07-05 19:29:39 UTC (rev 4401)
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};

Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/irq_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/irq_tables.c	2009-07-05 19:29:39 UTC (rev 4401)
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+/*
+ * Each of PIRQA..D can be routed to IRQ 3-7, 9-12, 14, or 15; but the
+ * selected IRQs can't be shared with ISA devices (Intel DS 290655-003,
+ * section 5.7.6).
+ *
+ * Correspondingly, the IRQs used on the Super I/O (4,6,7,10,12) are
+ * excluded from the masks, leaving 0xca28 (3,5,9,11,14,15).
+ */
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,         /* u32 signature */
+	PIRQ_VERSION,           /* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,                   /* Interrupt router bus */
+	(0x1f << 3) | 0x0,      /* Interrupt router dev */
+	0,                      /* IRQs devoted exclusively to PCI usage */
+	0x8086,                 /* Vendor */
+	0x7000,                 /* Device */
+	0,                      /* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xb6,                   /* Checksum (has to be set to some value that
+	                         * would give 0 after the sum of all bytes
+	                         * for this structure (including checksum).
+	                         */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x61, 0xca28}, {0x00, 0x0000}, {0x63, 0xca28}}, 0x0, 0x0},
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x0, 0x0},
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x01, (0x05 << 3) | 0x0, {{0x63, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x01, (0x08 << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x1, 0x0},
+		{0x01, (0x09 << 3) | 0x0, {{0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}}, 0x2, 0x0},
+		{0x01, (0x0a << 3) | 0x0, {{0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}}, 0x3, 0x0},
+		{0x01, (0x0b << 3) | 0x0, {{0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}}, 0x4, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/mainboard.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/mainboard.c	2009-07-05 19:29:39 UTC (rev 4401)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Mitac 6513WU Mainboard")
+};

Modified: trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c	2009-07-05 16:23:43 UTC (rev 4400)
+++ trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c	2009-07-05 19:29:39 UTC (rev 4401)
@@ -51,6 +51,7 @@
 #define FDC37M81X	0x4d
 #define FDC37M60X	0x47
 #define LPC47B27X	0x51	/* a.k.a. LPC47B272 */
+#define LPC47U33X	0x54
 #define LPC47M10X	0x59	/* Same ID: LPC47M112, LPC47M13X */
 #define LPC47M15X	0x60	/* Same ID: LPC47M192 */
 #define LPC47S45X	0x62
@@ -129,6 +130,7 @@
 	{LPC47M15X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, 10, 11, -1, -1, -1}},
 	{LPC47S45X,{0, 3, 4,  5,  6,  7, -1,   8, -1,  -1, -1, -1, 10, -1, 11}},
 	{LPC47B397,{0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
+	{LPC47U33X,{0, 3, 4, -1, -1,  7, -1,  -1, -1,   9,  0,  5, 10,  0, 11}},
 	{A8000,    {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 	{DME1737,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 	{SCH3112,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},

Added: trunk/coreboot-v2/targets/mitac/6513wu/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/mitac/6513wu/Config.lb	                        (rev 0)
+++ trunk/coreboot-v2/targets/mitac/6513wu/Config.lb	2009-07-05 19:29:39 UTC (rev 4401)
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target 6513wu
+mainboard mitac/6513wu
+
+# Leave 32 KB free for VGA BIOS.
+option CONFIG_ROM_SIZE = (512 - 32) * 1024
+
+option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+
+romimage "normal"
+	option CONFIG_USE_FALLBACK_IMAGE = 0
+	option COREBOOT_EXTRA_VERSION = ".0Normal"
+	payload ../payload.elf
+end
+
+romimage "fallback"
+	option CONFIG_USE_FALLBACK_IMAGE = 1
+	option COREBOOT_EXTRA_VERSION = ".0Fallback"
+	payload ../payload.elf
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"




From uwe at hermann-uwe.de  Sun Jul  5 21:39:32 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 5 Jul 2009 21:39:32 +0200
Subject: [coreboot] [PATCH] Add Mitac 6513WU mainboard support
In-Reply-To: <20090704213620.GA25256@iria.rilmarder.org>
References: <20090704213620.GA25256@iria.rilmarder.org>
Message-ID: <20090705193932.GE24201@greenwood>

On Sat, Jul 04, 2009 at 05:36:20PM -0400, Michael Gold wrote:
> This patch adds support for the Mitac 6513WU mainboard, a Compaq OEM
> board using the i810 chipset.  Not all hardware has been tested, but my
> test PC boots Linux (via FILO) without any problems.
> 
> The configuration leaves 32 kB for the video BIOS, but the onboard video
> isn't currently working due to known problems with this chipset.
> 
> Signed-off-by: Michael Gold <mgold at ncf.ca>

Great stuff, thanks a lot! This is committed in r4401 with some minor
changes.

I dropped all "(C) Uwe Hermann", pretty much all these files are trivial
and/or generic, no need to carry over any (C) lines.


> +    device pci 1.0 on                   # Chipset Graphics Controller (CGC)
> +      chip drivers/pci/onboard
> +        device pci 1.0 on end
> +        register "rom_address" = "0xfff80000" #512k image
> +      end
> +    end

I changed this part a bit, this may be nested a bit too much, but maybe
I'm wrong, not sure. Either way, the version which is in svn now worked
for me on the MS-6178 board, please try a plain svn checkout (r4401) and
see if onboard VGA works (better) on your board.


> +romimage "normal"
> +	option CONFIG_USE_FALLBACK_IMAGE = 0
> +	option COREBOOT_EXTRA_VERSION = ".0Normal"
> +	payload ../../../../payloads/filo.elf

Changed this to the generic "../payload.elf" we try to use
everywhere now (but there may be more changes wrt to this
when we move to kconfig for v2).


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From info at coresystems.de  Sun Jul  5 21:51:37 2009
From: info at coresystems.de (coreboot information)
Date: Sun, 05 Jul 2009 21:51:37 +0200
Subject: [coreboot] build service results for r4401
Message-ID: <E1MNXkP-0003kx-S7@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 4401 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the
i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.

Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.

Signed-off-by: Michael Gold <mgold at ncf.ca>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4401&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4401&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From maciej.pijanka at gmail.com  Sun Jul  5 22:16:57 2009
From: maciej.pijanka at gmail.com (Maciej Pijanka)
Date: Sun, 5 Jul 2009 22:16:57 +0200
Subject: [coreboot] [blabla] especially for Carl-Daniel
Message-ID: <e7f94b360907051316k778f55deoab2c5b623b5641f6@mail.gmail.com>

-- 
Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161
POE/Perl user



From c-d.hailfinger.devel.2006 at gmx.net  Sun Jul  5 22:20:04 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 05 Jul 2009 22:20:04 +0200
Subject: [coreboot] [blabla] especially for Carl-Daniel
In-Reply-To: <e7f94b360907051316k778f55deoab2c5b623b5641f6@mail.gmail.com>
References: <e7f94b360907051316k778f55deoab2c5b623b5641f6@mail.gmail.com>
Message-ID: <4A510AF4.80704@gmx.net>

Thanks!
(Background: We're tresting an improved mailing list setup.)



From uwe at hermann-uwe.de  Mon Jul  6 01:14:23 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 6 Jul 2009 01:14:23 +0200
Subject: [coreboot] r4394 breaks on hardware (was: Re: [PATCH] v3
 Resource allocator to v2)
In-Reply-To: <6726B07F2AB2414BB7BA7AEA6234C9AE@chimp>
References: <C9163063016E42B78E446D11A3429A0E@chimp>
	<2831fecf0905271525mb32bef9s7ded9f8d813f22e@mail.gmail.com>
	<13426df10905271801k60c6c1c8l71ea74a846d91a20@mail.gmail.com>
	<2831fecf0907021158q7a6f2c2apaac3ebc07d69518a@mail.gmail.com>
	<20090704020837.GC24201@greenwood>
	<6726B07F2AB2414BB7BA7AEA6234C9AE@chimp>
Message-ID: <20090705231423.GF24201@greenwood>

On Sat, Jul 04, 2009 at 07:41:09PM -0600, Myles Watson wrote:
> > > Rev 4394.
> > 
> > This patch seems to cause trouble, at least on the Kontron board where I
> > tested recent trunk, but probably on other systems also I'd guess.
> It could be, but the problem you're seeing is Kontron-specific.

Hm, possible, but then there are other issues in the new code I guess.
Here are two dumps of r4393/r4394 from the MS-6178 (i810) board.

The first one works fine and shows a FILO menu (on serial), the second
one contains lots of "!! Resource didn't fit !!" lines among other
things, and I see a totally garbled or blank FILO screen (on serial) and
it seems to hang at that point.


> Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
> 
> This BAR is added in a way that the allocator doesn't understand.  That was
> done on purpose because the old allocator didn't avoid fixed resources.
> There are several proposed fixes, but it isn't clear what the best one is.
> 
> You can chime in.

Not really, I don't know enough about this stuff to post useful comments, sorry.


> 1. Let the allocator place the BAR.
> 	Care would need to be taken when the BAR was set and the value would
> have to be passed to the ACPI code.
> 
> 2. Mark the resource as fixed and let the allocator avoid it.
> 	Either you lose a significant portion of the address space or you
> have to move it.  I think you could move it to 0xf8000000-0xfc000000.
> 
> 3. Add a PCI hole option to the resource allocator and manually allocate
> things that you want to live there.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
-------------- next part --------------


coreboot-2.0.0-r4393M.0Fallback Mon Jul  6 00:46:00 CEST 2009 starting...
SMBus controller enabled
No DIMM found in slot 00
Found DIMM in slot 01
DIMM is 0x80MB
After translation, dimm_size is 0x0d
DRP calculated to 0xd0
BUFF_SC calculated to 0xddda
Uncompressing coreboot to RAM.
Jumping to image.
Check CBFS header at fffdffd0
magic is 4f524243
Found CBFS header at fffdffd0
Check normal/payload
CBFS: follow chain: fff80000 + 28 + 13003 + align -> fff93030
Check normal/coreboot_ram
CBFS: follow chain: fff93030 + 38 + b4f7 + align -> fff9e560
Check fallback/payload
CBFS: follow chain: fff9e560 + 38 + 13003 + align -> fffb15a0
Check fallback/coreboot_ram
Stage: load @ 16384/155648 bytes, enter @ 4000
Stage: done loading.
Jumping to image.
coreboot-2.0.0-r4393M.0Fallback Mon Jul  6 00:46:00 CEST 2009 booting...
Calibrating delay loop...
end 6e7d8dcb, start 21e596a0
32-bit delta 1225
calibrate_tsc 32-bit result is 1225
clocks_per_usec: 1225
Enumerating buses...
Show all devs...Before Phase 3.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 0, 0 resources
PCI: 00:1e.0: enabled 1, 0 resources
PCI: 00:1f.0: enabled 1, 0 resources
PNP: 002e.0: enabled 1, 3 resources
PNP: 002e.1: enabled 1, 3 resources
PNP: 002e.2: enabled 1, 2 resources
PNP: 002e.3: enabled 1, 2 resources
PNP: 002e.5: enabled 1, 4 resources
PNP: 002e.6: enabled 1, 0 resources
PNP: 002e.7: enabled 1, 3 resources
PNP: 002e.8: enabled 1, 0 resources
PNP: 002e.9: enabled 1, 0 resources
PNP: 002e.a: enabled 1, 0 resources
PNP: 002e.b: enabled 1, 2 resources
PCI: 00:1f.1: enabled 1, 0 resources
PCI: 00:1f.2: enabled 1, 0 resources
PCI: 00:1f.3: enabled 1, 0 resources
PCI: 00:1f.5: enabled 1, 0 resources
PCI: 00:1f.6: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:00.0: enabled 1, 0 resources
  PCI: 00:01.0: enabled 0, 0 resources
  PCI: 00:1e.0: enabled 1, 0 resources
  PCI: 00:1f.0: enabled 1, 0 resources
   PNP: 002e.0: enabled 1, 3 resources
   PNP: 002e.1: enabled 1, 3 resources
   PNP: 002e.2: enabled 1, 2 resources
   PNP: 002e.3: enabled 1, 2 resources
   PNP: 002e.5: enabled 1, 4 resources
   PNP: 002e.6: enabled 1, 0 resources
   PNP: 002e.7: enabled 1, 3 resources
   PNP: 002e.8: enabled 1, 0 resources
   PNP: 002e.9: enabled 1, 0 resources
   PNP: 002e.a: enabled 1, 0 resources
   PNP: 002e.b: enabled 1, 2 resources
  PCI: 00:1f.1: enabled 1, 0 resources
  PCI: 00:1f.2: enabled 1, 0 resources
  PCI: 00:1f.3: enabled 1, 0 resources
  PCI: 00:1f.5: enabled 1, 0 resources
  PCI: 00:1f.6: enabled 1, 0 resources
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7120] ops
PCI: 00:00.0 [8086/7120] enabled
PCI: 00:01.1, bad id 0xffffffff
PCI: 00:01.2, bad id 0xffffffff
PCI: 00:01.3, bad id 0xffffffff
PCI: 00:01.4, bad id 0xffffffff
PCI: 00:01.5, bad id 0xffffffff
PCI: 00:01.6, bad id 0xffffffff
PCI: 00:01.7, bad id 0xffffffff
PCI: 00:02.0, bad id 0xffffffff
PCI: 00:03.0, bad id 0xffffffff
PCI: 00:04.0, bad id 0xffffffff
PCI: 00:05.0, bad id 0xffffffff
PCI: 00:06.0, bad id 0xffffffff
PCI: 00:07.0, bad id 0xffffffff
PCI: 00:08.0, bad id 0xffffffff
PCI: 00:09.0, bad id 0xffffffff
PCI: 00:0a.0, bad id 0xffffffff
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0, bad id 0xffffffff
PCI: 00:10.0, bad id 0xffffffff
PCI: 00:11.0, bad id 0xffffffff
PCI: 00:12.0, bad id 0xffffffff
PCI: 00:13.0, bad id 0xffffffff
PCI: 00:14.0, bad id 0xffffffff
PCI: 00:15.0, bad id 0xffffffff
PCI: 00:16.0, bad id 0xffffffff
PCI: 00:17.0, bad id 0xffffffff
PCI: 00:18.0, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0, bad id 0xffffffff
PCI: 00:1e.0 [8086/2428] bus ops
PCI: 00:1e.0 [8086/2428] enabled
PCI: 00:1f.0 [8086/2420] bus ops
PCI: 00:1f.0 [8086/2420] enabled
PCI: 00:1f.1 [8086/2421] ops
PCI: 00:1f.1 [8086/2421] enabled
PCI: 00:1f.2 [8086/2422] ops
PCI: 00:1f.2 [8086/2422] enabled
PCI: 00:1f.3 [8086/2423] enabled
PCI: 00:1f.4, bad id 0xffffffff
PCI: 00:1f.5 [8086/2425] ops
PCI: 00:1f.5 [8086/2425] enabled
PCI: 00:1f.6 [8086/2426] ops
PCI: 00:1f.6 [8086/2426] enabled
PCI: 00:1f.7, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0, bad id 0xffffffff
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
PCI: 01:05.0, bad id 0xffffffff
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
PCI: 01:08.0, bad id 0xffffffff
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:1f.0
PNP: 002e.0 enabled
PNP: 002e.1 enabled
PNP: 002e.2 enabled
PNP: 002e.3 enabled
PNP: 002e.5 enabled
PNP: 002e.6 enabled
PNP: 002e.7 enabled
PNP: 002e.8 enabled
PNP: 002e.9 enabled
PNP: 002e.a enabled
PNP: 002e.b enabled
scan_static_bus for PCI: 00:1f.0 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Allocating resources...
Show resources in subtree (Root Device)...Original.
 Root Device links 1 child on link 0 Root Device
  APIC_CLUSTER: 0 links 1 child on link 0 APIC_CLUSTER: 0
   APIC: 00 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI_DOMAIN: 0000
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:01.0 links 0 child on link 0 NULL
   PCI: 00:1e.0 links 1 child on link 0 NULL
   PCI: 00:1f.0 links 1 child on link 0 PCI: 00:1f.0
    PNP: 002e.0 links 0 child on link 0 NULL
    PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 002e.1 links 0 child on link 0 NULL
    PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 002e.2 links 0 child on link 0 NULL
    PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.3 links 0 child on link 0 NULL
    PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.5 links 0 child on link 0 NULL
    PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
    PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
    PNP: 002e.6 links 0 child on link 0 NULL
    PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 002e.7 links 0 child on link 0 NULL
    PNP: 002e.7 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.7 resource base 330 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62
    PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.8 links 0 child on link 0 NULL
    PNP: 002e.9 links 0 child on link 0 NULL
    PNP: 002e.a links 0 child on link 0 NULL
    PNP: 002e.b links 0 child on link 0 NULL
    PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60
    PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
   PCI: 00:1f.1 links 0 child on link 0 NULL
   PCI: 00:1f.2 links 0 child on link 0 NULL
   PCI: 00:1f.3 links 0 child on link 0 NULL
   PCI: 00:1f.5 links 0 child on link 0 NULL
   PCI: 00:1f.6 links 0 child on link 0 NULL
Reading resources...
Root Device compute_allocate_resource io: base: 00000400 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:1e.0 compute_allocate_resource io: base: 00000000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource io: base: 00000000 size: 00000000 align: 12 gran: 12 done
PCI: 00:1e.0 compute_allocate_resource io: base: 0000f000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource io: base: 0000f000 size: 00000000 align: 12 gran: 12 done
PCI: 00:1e.0 1c <- [0x000000f000 - 0x000000efff] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1e.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_resource mem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource mem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
PCI: 00:1f.5 10 *  [0x00000400 - 0x000004ff] io
PCI: 00:1f.6 10 *  [0x00000800 - 0x000008ff] io
PCI: 00:1f.6 14 *  [0x00000c00 - 0x00000c7f] io
PCI: 00:1f.5 14 *  [0x00000c80 - 0x00000cbf] io
PCI: 00:1f.2 20 *  [0x00000cc0 - 0x00000cdf] io
PCI: 00:1f.1 20 *  [0x00000ce0 - 0x00000cef] io
PCI: 00:1f.3 20 *  [0x00000cf0 - 0x00000cff] io
Root Device compute_allocate_resource io: base: 00001000 size: 00000c00 align: 8 gran: 0 done
Root Device compute_allocate_resource mem: base: 00000000 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
Root Device compute_allocate_r