[coreboot] [v2] r4391 - trunk/coreboot-v2/src/cpu/intel/model_6fx

[svn at coreboot.org]

Author: myles
Date: 2009-07-01 18:34:03 +0200 (Wed, 01 Jul 2009)
New Revision: 4391

Modified:
   trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c
Log:
Fix typo and only output post code if the work was done.

Thanks to Thomas Jourdan <thomas.jourdan at gmail.com> for reporting it.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c	2009-07-01 15:08:19 UTC (rev 4390)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c	2009-07-01 16:34:03 UTC (rev 4391)
@@ -50,9 +50,9 @@
 	"wrmsr\n"
 	"movl	$MTRRphysMask_MSR(1), %ecx\n"
 	"wrmsr\n"
-#endif
 
 	"movb	$0x33, %al\noutb %al, $0x80\n"
+#endif
 #ifdef CLEAR_FIRST_1M_RAM
 	"movb	$0x34, %al\noutb %al, $0x80\n"
 	/* Enable Write Combining and Speculative Reads for the first 1MB */
@@ -120,7 +120,7 @@
 	"movb	$0x3b, %al\noutb %al, $0x80\n"
 
 	/* Enable prefetchers */
-	"movl	$0x01a0, %eax\n"
+	"movl	$0x01a0, %ecx\n"
 	"rdmsr\n"
 	"andl	$~((1 << 9) | (1 << 19)), %eax\n"
 	"andl	$~((1 << 5) | (1 << 7)), %edx\n"