[coreboot] ACPI on m57sli v1.0
tiagomnm at gmail.com
Mon Jul 13 15:37:21 CEST 2009
On Mon, Jul 6, 2009 at 9:20 PM, Rudolf Marek<r.marek at assembler.cz> wrote:
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> Hi I was X-AFK.
>>> One thing I would like to ask, not just regarding this motherboard but
>>> all AM2/AM2+/AM3 boards.
>>> Would it be possible to implement a feature that would allow us to
>>> configure custom P-States to save on CMOS, other than what the
>>> manufacturer specifies? Most BIOS allow setting lower and higher
>>> multipliers than stock on some CPUs but disable CPU power management
>>> altogether when doing so. It would be quite a leap forward, when
>>> compared with vendor BIOS to be able to specify at least one VID and
>>> FID for the high power state and another FID and VID for the low power
> Yes it would be possible.
>>> With overclocking the benefits are enormous in the power bill and also
>>> for the low power state, since the manufacturer specifies 1.1v @ 1GHz
>>> and most CPUs handle 0.8v @ 800MHz quite easily. I'd love to get those
>>> low power states on my home server :)
> Aha have you the revisionG? What about idle=halt. We can fine tune what the CPU
> will do when doing C1 (HLT) we change the PMM register values to more aggressive
> power save. Enabling the ALTvid maybe?
I have a G1 and an F3, both dual core.
The altvid isn't just the regular down to 1000MHz/1.1v power management?
>> I've been trying to get hold of one of these M57SLI-S4 boards to try
>>> and implement this but would like to know if this is something
>>> possible to achieve with the current code base.
> Yes it is. The acpigen generator will generate any ACPI powerstates you
> want/need. The ACPIgen generator is simply capable of generating the data
> structures which are holding the power state values. By altering the algorithm
> for P states, you can then create your own custom values. Problem is if the CPU
> will allow the "underclocking" sometimes it wont transition to any fid which is
> lower then minFID or startFID. Please consult the CPU manual (BKDG).
> For the Pstates algo - 10.5.1.1 P-state Recognition Algorithm and the "portal"
> frequencies to see how the VCO and core frequency differs.
Nice. Would it be possible to do that after flashing(after some heavy
programming, I suppose) or would it have to be done in source code?
So, about lower than minVID and startFID, one would have to use an
embedded controller to change the minVID supplied by the CPU? No way
around by using just the CPU registers?
> If you have revisionG CPU (dualcore) maybe it would be quite cool to implement
> the C1E state. This could save much more power.
I do, would have to mess around with the motherboard first. It's this one:
It's MCP55 based, so perhaps something would work if I messed around
with the M57SLI-S4 code?
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