[coreboot] [v2] r4446 - in trunk/coreboot-v2/src: config cpu/x86/lapic cpu/x86/tsc

[svn at coreboot.org]

Author: stepan
Date: 2009-07-21 23:19:06 +0200 (Tue, 21 Jul 2009)
New Revision: 4446

Added:
   trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c
Modified:
   trunk/coreboot-v2/src/config/Options.lb
   trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb
   trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
   trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c
Log:
* rework tsc based timer code to use inb instead of outb for calibration
* Add generic Local APIC based timer code. This timer does not need expensive
  calibration and thus reduces the boot time by up to more than a second.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2009-07-21 20:27:00 UTC (rev 4445)
+++ trunk/coreboot-v2/src/config/Options.lb	2009-07-21 21:19:06 UTC (rev 4446)
@@ -928,6 +928,11 @@
 	export used
 	comment "Implement udelay with x86 io registers"
 end
+define CONFIG_UDELAY_LAPIC
+	default 0
+	export used
+	comment "Implement udelay with the x86 Local APIC"
+end
 define CONFIG_FAKE_SPDROM
 	default 0
 	export always

Modified: trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb	2009-07-21 20:27:00 UTC (rev 4445)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb	2009-07-21 21:19:06 UTC (rev 4446)
@@ -1,3 +1,11 @@
+uses CONFIG_UDELAY_LAPIC
+
 object lapic.o
 object lapic_cpu_init.o
 object secondary.S
+
+if CONFIG_UDELAY_LAPIC
+	default HAVE_INIT_TIMER=1
+	object apic_timer.o
+end
+

Added: trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c	2009-07-21 21:19:06 UTC (rev 4446)
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <delay.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+
+/* NOTE: This code uses global variables, so it can not be used during
+ * memory init.
+ */
+
+#define FSB_CLOCK_STS 0xcd
+
+static u32 timer_fsb = 200; // default to 200MHz
+
+void init_timer(void)
+{
+	msr_t fsb_clock_sts;
+
+	/* Set the apic timer to no interrupts and periodic mode */
+	lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0));
+
+	/* Set the divider to 1, no divider */
+	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
+
+	/* Set the initial counter to 0xffffffff */
+	lapic_write(LAPIC_TMICT, 0xffffffff);
+
+	/* Set FSB frequency to a reasonable value */
+	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
+	switch ((fsb_clock_sts.lo >> 4) & 0x07) {
+	case 0: timer_fsb = 266; break;
+	case 1: timer_fsb = 133; break;
+	case 2: timer_fsb = 200; break;
+	case 3: timer_fsb = 166; break;
+	case 5: timer_fsb = 100; break;
+	}
+}
+
+void udelay(u32 usecs)
+{
+	u32 start, value, ticks;
+	/* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */
+	ticks = usecs * timer_fsb;
+	start = lapic_read(LAPIC_TMCCT);
+	do {
+		value = lapic_read(LAPIC_TMCCT);
+	} while((start - value) < ticks);
+}

Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-07-21 20:27:00 UTC (rev 4445)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-07-21 21:19:06 UTC (rev 4446)
@@ -55,7 +55,7 @@
 	/* need to save it for RAM resume */
 	lowmem_backup_size = code_size;
 	lowmem_backup = malloc(code_size);
-	lowmem_backup_ptr = (unsigned char *)start_eip;
+	lowmem_backup_ptr = (char *)start_eip;
 	
 	if (lowmem_backup == NULL)
 		die("Out of backup memory\n");

Modified: trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c	2009-07-21 20:27:00 UTC (rev 4445)
+++ trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c	2009-07-21 21:19:06 UTC (rev 4446)
@@ -106,10 +106,10 @@
 	
 	printk_spew("Calibrating delay loop...\n");
 	start = rdtscll();
-	// no udivdi3, dammit.
+	// no udivdi3 because we don't like libgcc. (only in x86emu)
 	// so we count to 1<< 20 and then right shift 20
 	for(count = 0; count < (1<<20); count ++)
-		outb(0x80, 0x80);
+		inb(0x80);
 	end = rdtscll();
 
 #if 0