[coreboot] IOAPIC Initialisation - How much do you have to do ??

Rudolf Marek r.marek at assembler.cz
Thu Jul 23 18:05:16 CEST 2009

Hash: SHA1


I will leave for a holiday today. Its difficult to answer that without the patch
 at hand.

The ..TIMER: vector=0x31 apic1=0 pin1=2 apic2=-1 pin2=-1
..MP-BIOS bug: 8254 timer not connected to IO-APIC

Means that:

ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)

For some reason this is wrong. You have same line in the orig bios?
If yes there is still smth wrong with APIC. Please check:

Assigned: PCI: 00:10.4 10 *  [0xfebffd00 - 0xfebffdff] mem
Assigned: PCI: 00:10.5 10 *  [0xfebffe00 - 0xfebffeff] mem
Assigned: PCI: 00:12.0 14 *  [0xfebfff00 - 0xfebfffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fec00000 size: 300 align: 8
gran: 0 done

This looks like the mem resources are setup from too high overlaping the IOAPIC
with some hardware. No good. Move all resource bases bellow f0000000. You will
need to adjust the northbridge.c and put the PCI resource limit to the address
above most likely. Others can help here.

Also it seems that you created something in half:

ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 6 7 *10 11 12)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 6 7 10 *11 12)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 6 7 10 11 *12)
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 6 7 10 *11 12), disabled.
ACPI: PCI Interrupt Link [ATAI] (IRQs *20)
ACPI: PCI Interrupt Link [USBI] (IRQs *21)
ACPI: PCI Interrupt Link [VT8I] (IRQs *22)
ACPI: PCI Interrupt Link [NICI] (IRQs *23)

This means you route half of IRQs through APIC and second half through the 8259.
Why not route all of them through APIC. Check M2V-MX se board _PRT methods.

INTA# to IRQ16
INTB# to IRQ17
INTC# to IRQ18
INTD# to IRQ19

uhci_hcd 0000:00:10.0: Unlink after no-IRQ?  Controller is probably
using the wrong IRQ.  <<---- Whoops !!

Yes maybe but I think all USBs are routed to IRQ21 so it must be smth else. Like
the resource conflict I mentioned above. If VT8237R apic is enabled (and it is)
this is routed like this:

IDE (Native Mode)/SATA IRQ & INTE to IRQ20
USB IRQ (all 5 functions) and INTF to IRQ21
AC'97 / MC'97 IRQ and INTG to IRQ22

So I would recommend to boot now with init=/bin/bash
and provide

cat /proc/iomem
cat /proc/interrupts
lspci -vvvxxx

I'm going to be most likely AFK for a week so hopefully others can try to help.

Most likely is the resource conflict in game. Also check if the APIC messages
should be routed by extra bus or as part of FSB messages (there is some bit for
that on 0xfec000smth) I think FSB routing is fine for VIA CPU too but not sure.

rest looks OK to me. Please provide the WIP patch next time so one can see how
you set things up.



Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org


More information about the coreboot mailing list