From patrick at georgi-clan.de Mon Jun 1 00:01:09 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 01 Jun 2009 00:01:09 +0200 Subject: [coreboot] Patch management In-Reply-To: <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> References: <4A21EB8B.7060905@gmx.net> <20090531040125.15505.qmail@stuge.se> <13426df10905311056u558159c5w274bdf57b8e029c6@mail.gmail.com> <20090531204158.22144.qmail@stuge.se> <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> Message-ID: <4A22FE25.6060100@georgi-clan.de> Am 31.05.2009 23:14, schrieb ron minnich: > No code review system, however automated, can fix that kind of problem. > No, but they give a good overview at outstanding reviews, so less stuff ends up on the floor. Patrick From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 01:14:55 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 01:14:55 +0200 Subject: [coreboot] [PATCH] flashrom: Add bus type support to -p dummy Message-ID: <4A230F6F.9010800@gmx.net> Add bus type support to the dummy external programmer. The syntax is explained in the man page. Example: flashrom -p dummy=lpc,fwh Tested, works perfectly. ;-) As a nice benefit, it allows easy testing of the "probe only compatible flashes" patch. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-dummy_bustype/flashrom.8 =================================================================== --- flashrom-dummy_bustype/flashrom.8 (Revision 557) +++ flashrom-dummy_bustype/flashrom.8 (Arbeitskopie) @@ -135,6 +135,18 @@ .sp .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" .sp +The dummy programmer has an optional parameter specifying the bus types it +should support. For that you have to use the +.B "flashrom -p dummy=type" +syntax where +.B type +can be any comma-separated combination of +.B parallel lpc fwh spi all +in any order. +.sp +Example: +.B "flashrom -p dummy=lpc,fwh" +.sp If you have multiple supported PCI cards which can program flash chips (NICs, SATA/IDE controllers, etc.) in your system, you must use the .B "flashrom -p xxxx=bb:dd.f" Index: flashrom-dummy_bustype/flash.h =================================================================== --- flashrom-dummy_bustype/flash.h (Revision 557) +++ flashrom-dummy_bustype/flash.h (Arbeitskopie) @@ -122,6 +122,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { + CHIP_BUSTYPE_NONE = 0, CHIP_BUSTYPE_PARALLEL = 1 << 0, CHIP_BUSTYPE_LPC = 1 << 1, CHIP_BUSTYPE_FWH = 1 << 2, @@ -646,6 +647,7 @@ #endif /* dummyflasher.c */ +extern char *dummytype; int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); Index: flashrom-dummy_bustype/dummyflasher.c =================================================================== --- flashrom-dummy_bustype/dummyflasher.c (Revision 557) +++ flashrom-dummy_bustype/dummyflasher.c (Arbeitskopie) @@ -20,16 +20,51 @@ #include #include +#include #include #include #include #include #include "flash.h" +char *dummytype = NULL; + int dummy_init(void) { + int i; printf_debug("%s\n", __func__); - spi_controller = SPI_CONTROLLER_DUMMY; + + /* "all" is equivalent to specifying no type. */ + if (!strcmp(dummytype, "all")) { + free(dummytype); + dummytype = NULL; + } + if (!dummytype) + dummytype = strdup("parallel,lpc,fwh,spi"); + for (i = 0; dummytype[i] != '\0'; i++) + dummytype[i] = (char)tolower(dummytype[i]); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(dummytype, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + printf_debug("Enabling support for parallel flash.\n"); + } + if (strstr(dummytype, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + printf_debug("Enabling support for LPC flash.\n"); + } + if (strstr(dummytype, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + printf_debug("Enabling support for FWH flash.\n"); + } + if (strstr(dummytype, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + printf_debug("Enabling support for SPI flash.\n"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + printf_debug("Support for all flash bus types disabled.\n"); + free(dummytype); return 0; } Index: flashrom-dummy_bustype/flashrom.c =================================================================== --- flashrom-dummy_bustype/flashrom.c (Revision 557) +++ flashrom-dummy_bustype/flashrom.c (Arbeitskopie) @@ -537,6 +537,8 @@ programmer = PROGRAMMER_INTERNAL; } else if (strncmp(optarg, "dummy", 5) == 0) { programmer = PROGRAMMER_DUMMY; + if (optarg[5] == '=') + dummytype = strdup(optarg + 6); } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=') -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_dummy_bustype.diff URL: From audiossis at netspace.net.au Mon Jun 1 01:27:33 2009 From: audiossis at netspace.net.au (audiossis at netspace.net.au) Date: Mon, 1 Jun 2009 09:27:33 +1000 Subject: [coreboot] Builing Coreboot Message-ID: <1243812453.4a2312657e939@webmail.netspace.net.au> Hi, I'm new to the Coreboot project. I am an experienced electronics technician, so desoldering and burning flash chips is second nature to me, but I'm not a programmer so please forgive me if this seems like a silly question. I've been poking around the Coreboot home pages for the last few days. I've downloaded all the required packages to my Gentoo box and had a good look at what is there. I've read through some of the various documents on the web site about how to build Coreboot and I think I now have a basic understanding of how it all works. My target system is a Clevo laptop with an Intel 82855PM/GM northbridge and an 82801DB(ICH-4m) south bridge. Both of these chips are listed on the supported chipsets page (albeit I understand that the 82855PM/GM is still a work in progress). My question is, do I have to set any build flags or edit any configuration files before building Coreboot, to support these chips? Or does Coreboot support every device on the supported chipsets page "out of the box" so to speak? I know that I have to edit a configuration file to specify the payload I wish to use, but I cannot find anything that tells me wether or not I have to configure Coreboot for the specific chipset on the target mainboard. Thanks for your time and keep up the good work. It's a very interesting project and I'm keen to help out even if only by testing on different platforms. Regards, Ben ------------------------------------------------------------ This email was sent from Netspace Webmail: http://www.netspace.net.au From uwe at hermann-uwe.de Mon Jun 1 01:40:28 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 1 Jun 2009 01:40:28 +0200 Subject: [coreboot] [PATCH] flashrom: Add bus type support to -p dummy In-Reply-To: <4A230F6F.9010800@gmx.net> References: <4A230F6F.9010800@gmx.net> Message-ID: <20090531234028.GX18065@greenwood> On Mon, Jun 01, 2009 at 01:14:55AM +0200, Carl-Daniel Hailfinger wrote: > Add bus type support to the dummy external programmer. > > The syntax is explained in the man page. > Example: flashrom -p dummy=lpc,fwh > > Tested, works perfectly. ;-) > > As a nice benefit, it allows easy testing of the "probe only compatible > flashes" patch. > > Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann with the small changes below. > Index: flashrom-dummy_bustype/dummyflasher.c > =================================================================== > --- flashrom-dummy_bustype/dummyflasher.c (Revision 557) > +++ flashrom-dummy_bustype/dummyflasher.c (Arbeitskopie) > @@ -20,16 +20,51 @@ > > #include > #include > +#include > #include > #include > #include > #include > #include "flash.h" > > +char *dummytype = NULL; > + > int dummy_init(void) > { > + int i; > printf_debug("%s\n", __func__); > - spi_controller = SPI_CONTROLLER_DUMMY; > + > + /* "all" is equivalent to specifying no type. */ > + if (!strcmp(dummytype, "all")) { Use strncmp() whereever possible please. > + free(dummytype); > + dummytype = NULL; > + } > + if (!dummytype) > + dummytype = strdup("parallel,lpc,fwh,spi"); > + for (i = 0; dummytype[i] != '\0'; i++) > + dummytype[i] = (char)tolower(dummytype[i]); > + > + buses_supported = CHIP_BUSTYPE_NONE; > + if (strstr(dummytype, "parallel")) { > + buses_supported |= CHIP_BUSTYPE_PARALLEL; > + printf_debug("Enabling support for parallel flash.\n"); > + } > + if (strstr(dummytype, "lpc")) { > + buses_supported |= CHIP_BUSTYPE_LPC; > + printf_debug("Enabling support for LPC flash.\n"); > + } > + if (strstr(dummytype, "fwh")) { > + buses_supported |= CHIP_BUSTYPE_FWH; > + printf_debug("Enabling support for FWH flash.\n"); > + } > + if (strstr(dummytype, "spi")) { > + buses_supported |= CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_DUMMY; > + printf_debug("Enabling support for SPI flash.\n"); > + } You can use this nice little trick Stefan mentioned last year or so, which will save a few bytes in binary size (not that it's too important in the case of flashrom, but still). printf_debug("Enabling support for %s flash.\n", "parallel"); printf_debug("Enabling support for %s flash.\n", "LPC"); printf_debug("Enabling support for %s flash.\n", "FWH"); printf_debug("Enabling support for %s flash.\n", "SPI"); Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 01:43:53 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 01:43:53 +0200 Subject: [coreboot] Builing Coreboot In-Reply-To: <1243812453.4a2312657e939@webmail.netspace.net.au> References: <1243812453.4a2312657e939@webmail.netspace.net.au> Message-ID: <4A231639.6010203@gmx.net> Hi Ben, On 01.06.2009 01:27, audiossis at netspace.net.au wrote: > I'm new to the Coreboot project. Welcome! > I am an experienced electronics technician, so > desoldering and burning flash chips is second nature to me, but I'm not a > programmer so please forgive me if this seems like a silly question. > There are no silly questions. > My target system is a Clevo laptop with an Intel 82855PM/GM northbridge and an > 82801DB(ICH-4m) south bridge. Both of these chips are listed on the supported > chipsets page (albeit I understand that the 82855PM/GM is still a work in > progress). > There's one problem with your target system: It's a laptop. Laptops have embedded controllers and those are _very_ hairy to deal with because they are usually undocumented and talking with them in unexpected ways can even turn off the machine or wreak other havoc. > My question is, do I have to set any build flags or edit any configuration > files before building Coreboot, to support these chips? Or does Coreboot > support every device on the supported chipsets page "out of the box" so to > speak? > Due to size constraints in today's flash chips, adding support for multiple chipsets (or even multiple mainboards with the same chipset) is almost infeasible. That's why coreboot has "targets" which are configurations specifying the exact chipset and each oddball mainboard setting. A target not exactly matching your mainboard is very unlikely to work. > I know that I have to edit a configuration file to specify the payload I wish > to use, but I cannot find anything that tells me wether or not I have to > configure Coreboot for the specific chipset on the target mainboard. > There are a few build tutorials in our wiki for various boards and I hope some of them can give you an insight into how building a particular target works. > I'm keen to help out even if only by testing on different platforms. > We're a team consisting of hardware specialists and software specialists and a few of us specialize in both. I hope you feel welcome and stick around. We have plenty of exciting projects which can use help from electronics specialists like you. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Mon Jun 1 02:02:12 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Mon, 1 Jun 2009 02:02:12 +0200 Subject: [coreboot] [flashrom] r559 - trunk Message-ID: Author: hailfinger Date: 2009-06-01 02:02:11 +0200 (Mon, 01 Jun 2009) New Revision: 559 Modified: trunk/dummyflasher.c trunk/flash.h trunk/flashrom.8 trunk/flashrom.c Log: Add bus type support to the dummy external programmer. The syntax is explained in the man page. Example: flashrom -p dummy=lpc,fwh Tested, works perfectly. ;-) As a nice benefit, it allows easy testing of the "probe only compatible flashes" patch. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/dummyflasher.c 2009-06-01 00:02:11 UTC (rev 559) @@ -20,16 +20,52 @@ #include #include +#include #include #include #include #include #include "flash.h" +char *dummytype = NULL; + int dummy_init(void) { + int i; printf_debug("%s\n", __func__); - spi_controller = SPI_CONTROLLER_DUMMY; + + /* "all" is equivalent to specifying no type. */ + if (!strcmp(dummytype, "all")) { + free(dummytype); + dummytype = NULL; + } + if (!dummytype) + dummytype = strdup("parallel,lpc,fwh,spi"); + /* Convert the parameters to lowercase. */ + for (i = 0; dummytype[i] != '\0'; i++) + dummytype[i] = (char)tolower(dummytype[i]); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(dummytype, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + printf_debug("Enabling support for %s flash.\n", "parallel"); + } + if (strstr(dummytype, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + printf_debug("Enabling support for %s flash.\n", "LPC"); + } + if (strstr(dummytype, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + printf_debug("Enabling support for %s flash.\n", "FWH"); + } + if (strstr(dummytype, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + printf_debug("Enabling support for %s flash.\n", "SPI"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + printf_debug("Support for all flash bus types disabled.\n"); + free(dummytype); return 0; } Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/flash.h 2009-06-01 00:02:11 UTC (rev 559) @@ -122,6 +122,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { + CHIP_BUSTYPE_NONE = 0, CHIP_BUSTYPE_PARALLEL = 1 << 0, CHIP_BUSTYPE_LPC = 1 << 1, CHIP_BUSTYPE_FWH = 1 << 2, @@ -646,6 +647,7 @@ #endif /* dummyflasher.c */ +extern char *dummytype; int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/flashrom.8 2009-06-01 00:02:11 UTC (rev 559) @@ -135,6 +135,18 @@ .sp .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" .sp +The dummy programmer has an optional parameter specifying the bus types it +should support. For that you have to use the +.B "flashrom -p dummy=type" +syntax where +.B type +can be any comma-separated combination of +.B parallel lpc fwh spi all +in any order. +.sp +Example: +.B "flashrom -p dummy=lpc,fwh" +.sp If you have multiple supported PCI cards which can program flash chips (NICs, SATA/IDE controllers, etc.) in your system, you must use the .B "flashrom -p xxxx=bb:dd.f" Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/flashrom.c 2009-06-01 00:02:11 UTC (rev 559) @@ -537,6 +537,8 @@ programmer = PROGRAMMER_INTERNAL; } else if (strncmp(optarg, "dummy", 5) == 0) { programmer = PROGRAMMER_DUMMY; + if (optarg[5] == '=') + dummytype = strdup(optarg + 6); } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=') From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 02:11:26 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 02:11:26 +0200 Subject: [coreboot] [PATCH] flashrom: Add bus type support to -p dummy In-Reply-To: <20090531234028.GX18065@greenwood> References: <4A230F6F.9010800@gmx.net> <20090531234028.GX18065@greenwood> Message-ID: <4A231CAE.4080208@gmx.net> On 01.06.2009 01:40, Uwe Hermann wrote: > On Mon, Jun 01, 2009 at 01:14:55AM +0200, Carl-Daniel Hailfinger wrote: > >> Add bus type support to the dummy external programmer. >> >> Signed-off-by: Carl-Daniel Hailfinger >> > > Acked-by: Uwe Hermann > Thanks, committed in r559. Regards, Carl-Daniel -- http://www.hailfinger.org/ From uwe at hermann-uwe.de Mon Jun 1 03:08:10 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 1 Jun 2009 03:08:10 +0200 Subject: [coreboot] [PATCH] flashrom: Refactor HT-1000 GPIO setting In-Reply-To: <13426df10905251858y18ed51a7oaa0646411db16d24@mail.gmail.com> References: <4A1B2D1C.3010303@gmx.net> <13426df10905251858y18ed51a7oaa0646411db16d24@mail.gmail.com> Message-ID: <20090601010809.GY18065@greenwood> On Mon, May 25, 2009 at 06:58:42PM -0700, ron minnich wrote: > Has this been tested anywhere? > > I get a little worried about changes like this, which look fine in the > abstract, unless they are tested. It "should" work, it looks fine to > me, but ... Yeah, should work. Sure, testing would be nice also, but I think it's ok to commit this. Acked-by: Uwe Hermann Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From uwe at hermann-uwe.de Mon Jun 1 03:10:34 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 1 Jun 2009 03:10:34 +0200 Subject: [coreboot] [flashrom] nic3com: address lines In-Reply-To: <20090523161930.GA17479@mea.homelinux.org> References: <20090523161930.GA17479@mea.homelinux.org> Message-ID: <20090601011034.GZ18065@greenwood> On Sat, May 23, 2009 at 06:19:30PM +0200, Mats Erik Andersson wrote: > Hello all, > > using a signal probe I can verify two facts: > > 1) 3c905B has address lines A0 -- A16 routed, but not A17. > Thus 128 kB is the maximal capacity achievable. > > 2) 3c905 only routes the adress lines A0 -- A15, and therefore > limits itself to only 64 kB. On the other hand, I have not > succeeded in getting even read capabilities going in my > own code (not your "flashrom"). I'm not sure if the 3c905 is even supposed to work, not all 3com cards support the parallel flash read/write interface via the registers we use in flashrom right now. If the registers aren't there the programming will fail, of course. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From peter at stuge.se Mon Jun 1 03:23:09 2009 From: peter at stuge.se (Peter Stuge) Date: Mon, 1 Jun 2009 03:23:09 +0200 Subject: [coreboot] Builing Coreboot In-Reply-To: <1243812453.4a2312657e939@webmail.netspace.net.au> References: <1243812453.4a2312657e939@webmail.netspace.net.au> Message-ID: <20090601012310.9719.qmail@stuge.se> Hi Ben, audiossis at netspace.net.au wrote: > My target system is a Clevo laptop What Carl-Daniel wrote about embedded controllers applies. But since you can recover, it might still be interesting to give it a go. > (albeit I understand that the 82855PM/GM is still a work in progress) I have met at least one person who has production 855 code, I will get in touch with them if you find that current code is lacking. > I know that I have to edit a configuration file to specify the > payload I wish to use, Yes. > but I cannot find anything that tells me wether or not I have to > configure Coreboot for the specific chipset on the target > mainboard. Carl-Daniel mentioned targets. This is the starting point when building coreboot. In the v2 tree, there is the targets/ directory. In there you find all targets, grouped by vendor. There is no target for your exact system, so find one that is as close as possible. One target which uses 855 is digitallogic/adl855pc. To build that, you do: cd targets ./buildtarget digitallogic/adl855pc cd digitallogic/adl855pc/adl855pc make (you can also run make -C digitallogic/adl855pc/adl855pc and skip cd) After those commands, you should have a coreboot.rom file. The payload is specified in digitallogic/adl855pc/Config.lb, which is parsed by buildtarget and used to create Makefiles underneath the final leaf directory. If you change Config.lb, you have to re-run buildtarget. Note that buildtarget doesn't check for the payload, so you'll get Makefiles which fail to build. Then try booting coreboot.rom in your system. Chances are zero that it will work, but if the laptop is a little similar to the digitallogic, you may get serial output. Most likely you'll have to change the superio though, in src/mainboard/digitallogic/adl855pc/Config.lb to the superio which is used in the laptop, before you get anything from the serial port. //Peter From peter at stuge.se Mon Jun 1 03:25:34 2009 From: peter at stuge.se (Peter Stuge) Date: Mon, 1 Jun 2009 03:25:34 +0200 Subject: [coreboot] Patch management In-Reply-To: <4A22FE25.6060100@georgi-clan.de> References: <4A21EB8B.7060905@gmx.net> <20090531040125.15505.qmail@stuge.se> <13426df10905311056u558159c5w274bdf57b8e029c6@mail.gmail.com> <20090531204158.22144.qmail@stuge.se> <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> <4A22FE25.6060100@georgi-clan.de> Message-ID: <20090601012534.12998.qmail@stuge.se> Good points Ron. I've also been on both ends of the spectrum. Patrick Georgi wrote: >> No code review system, however automated, can fix that kind of >> problem. > > No, but they give a good overview at outstanding reviews, so less > stuff ends up on the floor. This elegantly summarizes the point I tried to make. I'll have a look at the links David posted. Thanks David! //Peter From svn at coreboot.org Mon Jun 1 03:38:29 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Mon, 1 Jun 2009 03:38:29 +0200 Subject: [coreboot] [v2] r4328 - trunk/coreboot-v2/src/superio/serverengines/pilot Message-ID: Author: uwe Date: 2009-06-01 03:38:29 +0200 (Mon, 01 Jun 2009) New Revision: 4328 Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c Log: Cosmetics and consistency fixes in src/superio/serverengines/pilot/ (trivial). Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h 2009-05-31 17:00:25 UTC (rev 4327) +++ trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h 2009-06-01 01:38:29 UTC (rev 4328) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for University of Heidelberg + * Written by Mondrian Nuessle for Univ. Heidelberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,15 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* PILOT SuperIO is only based on LPC observation done on factory system. */ +/* PILOT Super I/O is only based on LPC observation done on factory system. */ -#define PILOT_SP1 0x02 -// Serial port COM1 -#define PILOT_LD1 0x01 -// logical device 1 -#define PILOT_LD4 0x04 -// logical device 4 -#define PILOT_LD5 0x05 -// logical device 5 -#define PILOT_LD7 0x07 -// logical device 7 +#define PILOT_SP1 0x02 /* Com1 */ +#define PILOT_LD1 0x01 /* Logical device 1 */ +#define PILOT_LD4 0x04 /* Logical device 4 */ +#define PILOT_LD5 0x05 /* Logical device 5 */ +#define PILOT_LD7 0x07 /* Logical device 7 */ Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c 2009-05-31 17:00:25 UTC (rev 4327) +++ trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c 2009-06-01 01:38:29 UTC (rev 4328) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for University of Heidelberg + * Written by Mondrian Nuessle for Univ. Heidelberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,78 +19,79 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* PILOT SuperIO is only based on LPC observation done on factory system. */ +/* PILOT Super I/O is only based on LPC observation done on factory system. */ #define BLUBB_DEV PNP_DEV(port, 0x04) -/* Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to - be another serial (?), it is also deactivated on the HP machine */ +/* + * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to + * be another serial (?), it is also deactivated on the HP machine. + */ static void pilot_early_init(device_t dev) { - unsigned port = dev>>8; - print_debug("Using port:");print_debug_hex16(port);print_debug("\r\n"); - pilot_disable_serial(PNP_DEV(port,0x1)); + unsigned port = dev >> 8; + + print_debug("Using port: "); + print_debug_hex16(port); + print_debug("\r\n"); + pilot_disable_serial(PNP_DEV(port, 0x1)); print_debug("disable serial 1\r\n"); /* -pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x3)); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port,0x3),0); + pnp_set_enable(PNP_DEV(port, 0x3), 0); pnp_exit_ext_func_mode(dev); */ pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x4)); + pnp_set_logical_device(PNP_DEV(port, 0x4)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port,0x4),0); + pnp_set_enable( PNP_DEV(port, 0x4), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x5)); + pnp_set_logical_device(PNP_DEV(port, 0x5)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x5),0); + pnp_set_enable(PNP_DEV(port, 0x5), 0); pnp_exit_ext_func_mode(dev); - /* +/* pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x6)); + pnp_set_logical_device(PNP_DEV(port, 0x6)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port,0x6),0); + pnp_set_enable( PNP_DEV(port, 0x6), 0); pnp_exit_ext_func_mode(dev); */ pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x7)); + pnp_set_logical_device(PNP_DEV(port, 0x7)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x7), 0); + pnp_set_enable(PNP_DEV(port, 0x7), 0); pnp_exit_ext_func_mode(dev); /* pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x8)); + pnp_set_logical_device(PNP_DEV(port, 0x8)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x8), 0); + pnp_set_enable(PNP_DEV(port, 0x8), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x9)); + pnp_set_logical_device(PNP_DEV(port, 0x9)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x9), 0); + pnp_set_enable(PNP_DEV(port, 0x9), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x10; + pnp_set_logical_device(PNP_DEV(port, 0x10)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x10 0); + pnp_set_enable(PNP_DEV(port, 0x10), 0); pnp_exit_ext_func_mode(dev); */ - } - - - Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c 2009-05-31 17:00:25 UTC (rev 4327) +++ trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c 2009-06-01 01:38:29 UTC (rev 4328) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for University of Heidelberg + * Written by Mondrian Nuessle for Univ. Heidelberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,25 +19,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* PILOT SuperIO is only based on LPC observation done on factory system. */ +/* PILOT Super I/O is only based on LPC observation done on factory system. */ #include #include "pilot.h" -/* pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access */ +/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ static inline void pnp_enter_ext_func_mode(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x5A, port); } static void pnp_exit_ext_func_mode(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xA5, port); } -/* serial config is failry standard procedure */ +/* Serial config is a fairly standard procedure. */ static void pilot_enable_serial(device_t dev, unsigned iobase) { pnp_enter_ext_func_mode(dev); @@ -55,4 +55,3 @@ pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); } - From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 03:38:46 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 03:38:46 +0200 Subject: [coreboot] [PATCH] flashrom: Only probe for chips with compatible bus protocols In-Reply-To: <13426df10905311416w46bb5511s397a3b6d1b377232@mail.gmail.com> References: <4A22D57C.3030508@gmx.net> <13426df10905311416w46bb5511s397a3b6d1b377232@mail.gmail.com> Message-ID: <4A233126.6010700@gmx.net> On 31.05.2009 23:16, ron minnich wrote: > Nice. can we get some confirmed tests? > I tested with the dummy external flasher and it worked perfectly. > This is a good change but I want to make sure people's hardware still > works with it. > Sure. Updated patch follows. Changes compared to the first version: - Print the bus types of the controller and the flash chip. Example for a LPC host and a SPI flash chip: Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Example for a SPI host and a non-SPI flash chip: Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel,LPC,FWH are incompatible. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-chiptype_avoid_bus_mismatch/it87spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Arbeitskopie) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Index: flashrom-chiptype_avoid_bus_mismatch/nic3com.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Arbeitskopie) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/satasii.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/satasii.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/satasii.c (Arbeitskopie) @@ -67,6 +67,8 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) printf("Warning: Flash seems unconnected.\n"); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Arbeitskopie) @@ -63,7 +63,10 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Arbeitskopie) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) @@ -174,10 +174,47 @@ return 0; } +char *strcat_realloc(char *dest, char *src) +{ + dest = realloc(dest, strlen(dest) + strlen(src) + 1); + if (!dest) + return NULL; + strcat(dest, src); + return dest; +} + +/* Return a string corresponding to the bustype parameter. + * Memory is obtained with malloc() and can be freed with free(). + */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + char *ret = calloc(1, 1); + if (bustype & CHIP_BUSTYPE_PARALLEL) { + ret = strcat_realloc(ret, "Parallel,"); + } + if (bustype & CHIP_BUSTYPE_LPC) { + ret = strcat_realloc(ret, "LPC,"); + } + if (bustype & CHIP_BUSTYPE_FWH) { + ret = strcat_realloc(ret, "FWH,"); + } + if (bustype & CHIP_BUSTYPE_SPI) { + ret = strcat_realloc(ret, "SPI,"); + } + if (bustype == CHIP_BUSTYPE_NONE) { + ret = strcat_realloc(ret, "None,"); + } + /* Kill last comma. */ + ret[strlen(ret) - 1] = '\0'; + ret = realloc(ret, strlen(ret) + 1); + return ret; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; unsigned long base = 0, size; + char *tmp; for (flash = first_flash; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) @@ -188,6 +225,15 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + tmp = flashbuses_to_text(buses_supported); + printf_debug("skipped. Host bus type %s ", tmp); + free(tmp); + tmp = flashbuses_to_text(flash->bustype); + printf_debug("and chip bus type %s are incompatible.\n", tmp); + free(tmp); + continue; + } size = flash->total_size * 1024; -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_chiptype_avoid_bus_mismatch01.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 03:48:40 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 03:48:40 +0200 Subject: [coreboot] [PATCH] flashrom: Only probe for chips with compatible bus protocols In-Reply-To: <4A233126.6010700@gmx.net> References: <4A22D57C.3030508@gmx.net> <13426df10905311416w46bb5511s397a3b6d1b377232@mail.gmail.com> <4A233126.6010700@gmx.net> Message-ID: <4A233378.1070001@gmx.net> New patch. Changes compared to version 2: - If a chip is listed as NONSPI, print "Non-SPI". - If a chip is listed as UNKNOWN, print "Unknown". Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-chiptype_avoid_bus_mismatch/it87spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Arbeitskopie) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Index: flashrom-chiptype_avoid_bus_mismatch/nic3com.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Arbeitskopie) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/satasii.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/satasii.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/satasii.c (Arbeitskopie) @@ -67,6 +67,8 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) printf("Warning: Flash seems unconnected.\n"); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Arbeitskopie) @@ -63,7 +63,10 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Arbeitskopie) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 559) +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) @@ -174,10 +174,56 @@ return 0; } +char *strcat_realloc(char *dest, char *src) +{ + dest = realloc(dest, strlen(dest) + strlen(src) + 1); + if (!dest) + return NULL; + strcat(dest, src); + return dest; +} + +/* Return a string corresponding to the bustype parameter. + * Memory is obtained with malloc() and can be freed with free(). + */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + char *ret = calloc(1, 1); + if (bustype == CHIP_BUSTYPE_UNKNOWN) { + ret = strcat_realloc(ret, "Unknown,"); + /* FIXME: Once all chipsets and flash chips have been updated, NONSPI + * will cease to exist and should be eliminated here as well. + */ + } else if (bustype == CHIP_BUSTYPE_NONSPI) { + ret = strcat_realloc(ret, "Non-SPI,"); + } else { + if (bustype & CHIP_BUSTYPE_PARALLEL) { + ret = strcat_realloc(ret, "Parallel,"); + } + if (bustype & CHIP_BUSTYPE_LPC) { + ret = strcat_realloc(ret, "LPC,"); + } + if (bustype & CHIP_BUSTYPE_FWH) { + ret = strcat_realloc(ret, "FWH,"); + } + if (bustype & CHIP_BUSTYPE_SPI) { + ret = strcat_realloc(ret, "SPI,"); + } + if (bustype == CHIP_BUSTYPE_NONE) { + ret = strcat_realloc(ret, "None,"); + } + } + /* Kill last comma. */ + ret[strlen(ret) - 1] = '\0'; + ret = realloc(ret, strlen(ret) + 1); + return ret; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; unsigned long base = 0, size; + char *tmp; for (flash = first_flash; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) @@ -188,6 +234,15 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + tmp = flashbuses_to_text(buses_supported); + printf_debug("skipped. Host bus type %s ", tmp); + free(tmp); + tmp = flashbuses_to_text(flash->bustype); + printf_debug("and chip bus type %s are incompatible.\n", tmp); + free(tmp); + continue; + } size = flash->total_size * 1024; -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_chiptype_avoid_bus_mismatch02.diff URL: From uwe at hermann-uwe.de Mon Jun 1 04:04:50 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 1 Jun 2009 04:04:50 +0200 Subject: [coreboot] [PATCH] flashrom: Only probe for chips with compatible bus protocols In-Reply-To: <4A233378.1070001@gmx.net> References: <4A22D57C.3030508@gmx.net> <13426df10905311416w46bb5511s397a3b6d1b377232@mail.gmail.com> <4A233126.6010700@gmx.net> <4A233378.1070001@gmx.net> Message-ID: <20090601020450.GA18065@greenwood> On Mon, Jun 01, 2009 at 03:48:40AM +0200, Carl-Daniel Hailfinger wrote: > New patch. Changes compared to version 2: > - If a chip is listed as NONSPI, print "Non-SPI". > - If a chip is listed as UNKNOWN, print "Unknown". > > Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Looks good, and I tested a successful read/write/erase of an LPC chip on actual hardware. > Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c > =================================================================== > --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 559) > +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) > @@ -174,10 +174,56 @@ > return 0; > } > > +char *strcat_realloc(char *dest, char *src) src can be 'const char *src' I think. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From svn at coreboot.org Mon Jun 1 04:08:58 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Mon, 1 Jun 2009 04:08:58 +0200 Subject: [coreboot] [flashrom] r560 - trunk Message-ID: Author: hailfinger Date: 2009-06-01 04:08:58 +0200 (Mon, 01 Jun 2009) New Revision: 560 Modified: trunk/chipset_enable.c trunk/flashrom.c trunk/it87spi.c trunk/nic3com.c trunk/satasii.c trunk/wbsio_spi.c Log: Only probe for chips with compatible bus protocols. It doesn't make sense to probe for SPI chips on a LPC host, nor does it make sense to probe for LPC chips on a Parallel host. This change is backwards compatible, but adding host protocol info to chipset init functions will speed up probing. Once all chipset init functions are updated and the Winbond W29EE011 and AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can be deleted as the W29/A49 conflict magically disappears. Signed-off-by: Carl-Daniel Hailfinger Tested on real hardware and Acked-by: Uwe Hermann Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/chipset_enable.c 2009-06-01 02:08:58 UTC (rev 560) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/flashrom.c 2009-06-01 02:08:58 UTC (rev 560) @@ -174,10 +174,51 @@ return 0; } +char *strcat_realloc(char *dest, const char *src) +{ + dest = realloc(dest, strlen(dest) + strlen(src) + 1); + if (!dest) + return NULL; + strcat(dest, src); + return dest; +} + +/* Return a string corresponding to the bustype parameter. + * Memory is obtained with malloc() and can be freed with free(). + */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + char *ret = calloc(1, 1); + if (bustype == CHIP_BUSTYPE_UNKNOWN) { + ret = strcat_realloc(ret, "Unknown,"); + /* FIXME: Once all chipsets and flash chips have been updated, NONSPI + * will cease to exist and should be eliminated here as well. + */ + } else if (bustype == CHIP_BUSTYPE_NONSPI) { + ret = strcat_realloc(ret, "Non-SPI,"); + } else { + if (bustype & CHIP_BUSTYPE_PARALLEL) + ret = strcat_realloc(ret, "Parallel,"); + if (bustype & CHIP_BUSTYPE_LPC) + ret = strcat_realloc(ret, "LPC,"); + if (bustype & CHIP_BUSTYPE_FWH) + ret = strcat_realloc(ret, "FWH,"); + if (bustype & CHIP_BUSTYPE_SPI) + ret = strcat_realloc(ret, "SPI,"); + if (bustype == CHIP_BUSTYPE_NONE) + ret = strcat_realloc(ret, "None,"); + } + /* Kill last comma. */ + ret[strlen(ret) - 1] = '\0'; + ret = realloc(ret, strlen(ret) + 1); + return ret; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; unsigned long base = 0, size; + char *tmp; for (flash = first_flash; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) @@ -188,6 +229,15 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + tmp = flashbuses_to_text(buses_supported); + printf_debug("skipped. Host bus type %s ", tmp); + free(tmp); + tmp = flashbuses_to_text(flash->bustype); + printf_debug("and chip bus type %s are incompatible.\n", tmp); + free(tmp); + continue; + } size = flash->total_size * 1024; Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/it87spi.c 2009-06-01 02:08:58 UTC (rev 560) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/nic3com.c 2009-06-01 02:08:58 UTC (rev 560) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Modified: trunk/satasii.c =================================================================== --- trunk/satasii.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/satasii.c 2009-06-01 02:08:58 UTC (rev 560) @@ -67,6 +67,8 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) printf("Warning: Flash seems unconnected.\n"); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/wbsio_spi.c 2009-06-01 02:08:58 UTC (rev 560) @@ -63,7 +63,10 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; + return 0; } From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 04:10:28 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 04:10:28 +0200 Subject: [coreboot] [PATCH] flashrom: Only probe for chips with compatible bus protocols In-Reply-To: <20090601020450.GA18065@greenwood> References: <4A22D57C.3030508@gmx.net> <13426df10905311416w46bb5511s397a3b6d1b377232@mail.gmail.com> <4A233126.6010700@gmx.net> <4A233378.1070001@gmx.net> <20090601020450.GA18065@greenwood> Message-ID: <4A233894.1040403@gmx.net> On 01.06.2009 04:04, Uwe Hermann wrote: > On Mon, Jun 01, 2009 at 03:48:40AM +0200, Carl-Daniel Hailfinger wrote: > > Acked-by: Uwe Hermann > Thanks, committed in r560. >> --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 559) >> +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) >> @@ -174,10 +174,56 @@ >> +char *strcat_realloc(char *dest, char *src) >> > > src can be 'const char *src' I think. > Changed. Regards, Carl-Daniel -- http://www.hailfinger.org/ From Zheng.Bao at amd.com Mon Jun 1 04:34:22 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Mon, 1 Jun 2009 10:34:22 +0800 Subject: [coreboot] [patch]: a little error is fixed. Message-ID: Modify it based on the RPR. 5.7.7. Switching GPPSB Configuration By Register Programming. Signed-off-by: Zheng Bao Index: src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- src/southbridge/amd/rs690/rs690_pcie.c (revision 469) +++ src/southbridge/amd/rs690/rs690_pcie.c (working copy) @@ -148,7 +148,7 @@ /* waits until SB has trained to L0, poll for bit0-5 = 0x10 */ do { reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0); - reg &= 0x1f; /* remain LSB 5 bits */ + reg &= 0x3f; /* remain LSB [5:0] bits */ } while (LC_STATE_RECONFIG_GPPSB != reg); /* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */ -------------- next part -------------- A non-text attachment was scrubbed... Name: gppsb_switching_small_not_trival.patch Type: application/octet-stream Size: 587 bytes Desc: gppsb_switching_small_not_trival.patch URL: From david.hendricks at gmail.com Mon Jun 1 04:41:44 2009 From: david.hendricks at gmail.com (David Hendricks) Date: Sun, 31 May 2009 19:41:44 -0700 Subject: [coreboot] MSI 7135 verbose lspci output Message-ID: Attached is an lspci dump for the MSI 7135 (K8N Neo3) board. jakllsch did a v2 port for this board last year. Flashrom works, but only if you do -m msi:k8n-neo3 for erase and write operations. Uwe suggested posting the lspci contents in case someone has a few spare cycles to try and implement auto-detect for this board in flashrom. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- 00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a2) Subsystem: Micro-Star International Co., Ltd. Device 7135 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- 00: de 10 5c 00 07 00 a0 00 a2 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 d0 d0 80 22 20: e0 fd e0 fd f0 fd f0 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 02 40: 00 00 07 00 01 00 02 00 07 00 00 00 00 00 44 01 50: 00 00 fe 7f 00 00 00 00 f0 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 03 00 00 80 00 00 00 00 00 00 00 08 00 00 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a2) Subsystem: Micro-Star International Co., Ltd. Device 7135 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit+ Count=1/2 Enable+ Address: 00000000fee0100c Data: 4149 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x2, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 8, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel Capabilities: [140] Root Complex Link Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 5d 00 07 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 c1 c1 00 00 20: d0 fd d0 fd c1 fd c1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40: 01 48 02 f8 00 00 00 00 05 58 83 00 0c 10 e0 fe 50: 00 00 00 00 49 41 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 21 34 01 03 90: 00 00 41 10 80 0c 40 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit+ Count=1/2 Enable+ Address: 00000000fee0100c Data: 4151 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 4, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel Capabilities: [140] Root Complex Link Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 5d 00 07 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 b1 b1 00 00 20: b0 fd b0 fd a1 fd a1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40: 01 48 02 f8 00 00 00 00 05 58 83 00 0c 10 e0 fe 50: 00 00 00 00 51 41 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 34 01 02 90: 00 00 41 10 00 05 20 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit+ Count=1/2 Enable+ Address: 00000000fee0100c Data: 4159 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 2, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel Capabilities: [140] Root Complex Link Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 5d 00 07 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 a1 a1 00 00 20: 90 fd 90 fd 81 fd 81 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40: 01 48 02 f8 00 00 00 00 05 58 83 00 0c 10 e0 fe 50: 00 00 00 00 59 41 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 34 01 01 90: 00 00 81 10 00 05 10 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit+ Count=1/2 Enable+ Address: 00000000fee0100c Data: 4161 Capabilities: [58] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 1, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel Capabilities: [140] Root Complex Link Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 5d 00 07 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 91 91 00 20 20: 70 fd 70 fd 01 d0 f1 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 08 00 40: 01 48 02 f8 00 00 00 00 05 58 83 00 0c 10 e0 fe 50: 00 00 00 00 61 41 00 00 08 80 00 a8 00 00 e0 fe 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 c0 04 00 00 10 28 00 00 01 35 01 00 90: 00 00 01 11 80 25 08 00 c0 01 40 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- I've completed the porting and refactoring of the LGPL vgabios. I'm looking for developers interested in reviewing the code and trying to port it to real hardware. The port to gcc consists of the basic VGA support. The new code is almost entirely written in C - there is only about 50 lines of assembler specific to VGA (for the entry functions). I've also refactored the code significantly. The new code has been split into several files - mostly by whether it implemented bios functionality, framebuffer manipulation, or IO port setting. I've also simplified the code and eliminated many redundancies. To obtain the code and compile an option rom, run: git clone git://git.linuxtogo.org/home/kevin/seabios.git cd seabios make out/vgabios.bin The code specific to vga is in the directory seabios/vgasrc/ . I've done some basic sanity tests with qemu. More testing is needed, but I think it's ready for a wider audience. -Kevin From patrick at georgi-clan.de Mon Jun 1 09:12:12 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 01 Jun 2009 09:12:12 +0200 Subject: [coreboot] Patch management In-Reply-To: <20090601012534.12998.qmail@stuge.se> References: <4A21EB8B.7060905@gmx.net> <20090531040125.15505.qmail@stuge.se> <13426df10905311056u558159c5w274bdf57b8e029c6@mail.gmail.com> <20090531204158.22144.qmail@stuge.se> <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> <4A22FE25.6060100@georgi-clan.de> <20090601012534.12998.qmail@stuge.se> Message-ID: <4A237F4C.4030703@georgi-clan.de> Peter Stuge schrieb: > This elegantly summarizes the point I tried to make. I'll have a look > at the links David posted. Thanks David! > One thing I found lacking with all those tools so far was proper integration with a mail feed, which seems to be a hard requirement for coreboot. It's not that hard to automatically fetch all attachments that look like patches from the mailing list and figure out which of our subprojects it belongs to. It's very hard to automatically figure out if a patch is committed, so the ticket in the patch queue / review tool could be closed. That means, that we'd either have to force people to use the tool instead of just the mailing list (good luck with that), or we'd need to clean up the database of that tool manually (good luck with that, too). The other missing feature in review board half a year ago, when I installed a test instance of it, was support for patch queues, eg. 6 successive patches that build on each other. That would require rather ugly workarounds. It might be supported by now. Patrick From peter at stuge.se Mon Jun 1 14:22:06 2009 From: peter at stuge.se (Peter Stuge) Date: Mon, 1 Jun 2009 14:22:06 +0200 Subject: [coreboot] LGPL vgabios on real hardware In-Reply-To: <20090601030358.GA29555@morn.localdomain> References: <20090601030358.GA29555@morn.localdomain> Message-ID: <20090601122206.4418.qmail@stuge.se> Kevin O'Connor wrote: > To obtain the code and compile an option rom, run: > > git clone git://git.linuxtogo.org/home/kevin/seabios.git > cd seabios > make out/vgabios.bin Exciting! > The code specific to vga is in the directory seabios/vgasrc/ . > > I've done some basic sanity tests with qemu. More testing is > needed, but I think it's ready for a wider audience. Please please put this in a separate repo. //Peter From kevin at koconnor.net Mon Jun 1 14:59:44 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Mon, 1 Jun 2009 08:59:44 -0400 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <13426df10905301800s5543048dj92dd3f3e5395abcd@mail.gmail.com> References: <20090529134428.GA13500@skynet.be> <20090530155900.GA11598@morn.localdomain> <13426df10905301800s5543048dj92dd3f3e5395abcd@mail.gmail.com> Message-ID: <20090601125944.GA1853@morn.localdomain> On Sat, May 30, 2009 at 09:00:42PM -0400, ron minnich wrote: > On Sat, May 30, 2009 at 11:59 AM, Kevin O'Connor wrote: > > The issues with using nvram: > > > > ?* it's small and it leads to weird hacks to store data > > > > ?* the coreboot layout conflicts with the vendor layout and it's a > > ? ?pain when switching between coreboot and factory bios > > > > ?* the batteries frequently get old and nvram storage becomes flaky > > the big concern is having to rewrite a 64K flash page to change one > bit. However! It would require dedicating a flash page for the config, and it would require using flashrom (or an equivalent) to change the config. I wouldn't worry about the flash wear - the config wont change frequently. [...] > Or should we just store options as files in cbfs? That seems simplest. That's a neat idea. It's not very compact, but it would work well for a handful of options. If we went with a config file, I propose something very simple - like text lines with "name=value\n". -Kevin From uwe at hermann-uwe.de Mon Jun 1 15:31:06 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Mon, 1 Jun 2009 15:31:06 +0200 Subject: [coreboot] Patch management In-Reply-To: <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> References: <4A21EB8B.7060905@gmx.net> <20090531040125.15505.qmail@stuge.se> <13426df10905311056u558159c5w274bdf57b8e029c6@mail.gmail.com> <20090531204158.22144.qmail@stuge.se> <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> Message-ID: <20090601133106.GB18065@greenwood> On Sun, May 31, 2009 at 05:14:37PM -0400, ron minnich wrote: > On Sun, May 31, 2009 at 4:41 PM, Peter Stuge wrote: > > ron minnich wrote: > >> > I would like to request a better patch management system than this > >> > mailing list. > >> > >> it's a hard problem. > > .. > >> All in all, I think the process works. > > > > I don't, when patches are untracked and linger for however long until > > the author or someone else sends a ping, at which point they may get > > some more attention, or will just continue to linger. > > all patches or some patches? Every time I svn, which is almost daily, > there are changes. > > Clearly, some patches are being reviewed and acked. Most of them, yes. I personally think our review/commit process is working very well. Sure, sometimes patches take a little longer to review/test, but that's not a problem of the process itself, it's simply because we have a limited number of developers with a limited amount of time. There is only one thing I suggest for improvement: if a patch doesn't reveice answers (review, test, ack, nack) after 2 weeks or so, the developer (or pretty much any user/developer on this list) should either (a) Post a *ping* mail, maybe the patch was just not noticed or forgotten and will then be swiftly reviewed/committed. (b) Add a trac issue, containing the URL to the mailing list post of the patch, so that it doesn't get forgotten. Other than that, the process works just fine, and I strongly believe that adding _more_ (web-based or other) tools in the mix will make things worse, not better. We already have trac for issues, no need for more tools. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From peter at stuge.se Mon Jun 1 15:38:26 2009 From: peter at stuge.se (Peter Stuge) Date: Mon, 1 Jun 2009 15:38:26 +0200 Subject: [coreboot] Patch management In-Reply-To: <20090601133106.GB18065@greenwood> References: <4A21EB8B.7060905@gmx.net> <20090531040125.15505.qmail@stuge.se> <13426df10905311056u558159c5w274bdf57b8e029c6@mail.gmail.com> <20090531204158.22144.qmail@stuge.se> <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> <20090601133106.GB18065@greenwood> Message-ID: <20090601133826.1747.qmail@stuge.se> Uwe Hermann wrote: > I strongly believe that adding _more_ (web-based or other) tools in > the mix will make things worse, not better. That surprises me. I think helpful tools are always an improvement. > We already have trac for issues, no need for more tools. Except we don't have Trac. Noone uses Trac, so noone else will use it either. It isn't used because it isn't helpful enough for us as a group. This thread is about tools which actually would be helpful, not about adding $RANDOMSTUFF which doesn't help us. It seems a little harsh to rule out all tools after one has been evaluated. (Thanks Patrick!) //Peter From stepan at coresystems.de Mon Jun 1 18:16:20 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Mon, 01 Jun 2009 18:16:20 +0200 Subject: [coreboot] Patch management In-Reply-To: <20090601133106.GB18065@greenwood> References: <4A21EB8B.7060905@gmx.net> <20090531040125.15505.qmail@stuge.se> <13426df10905311056u558159c5w274bdf57b8e029c6@mail.gmail.com> <20090531204158.22144.qmail@stuge.se> <13426df10905311414t40e4b72u83ac7bbff55dcc8b@mail.gmail.com> <20090601133106.GB18065@greenwood> Message-ID: <4A23FED4.8010103@coresystems.de> On 01.06.2009 15:31 Uhr, Uwe Hermann wrote: > Most of them, yes. > > I personally think our review/commit process is working very well. Sure, > sometimes patches take a little longer to review/test, but that's not a > problem of the process itself, it's simply because we have a limited > number of developers with a limited amount of time. > > There is only one thing I suggest for improvement: if a patch doesn't > reveice answers (review, test, ack, nack) after 2 weeks or so, the > developer (or pretty much any user/developer on this list) should either > > (a) Post a *ping* mail, maybe the patch was just not noticed or forgotten > and will then be swiftly reviewed/committed. > > (b) Add a trac issue, containing the URL to the mailing list post of > the patch, so that it doesn't get forgotten. > (c) If you think your patch is ignored / not handled properly, please do send a separate mail to rminnich at gmail.com and/or stepan at coresystems.de (maybe other core developers might want to offer the same?) discussing the issue. This can significantly speed up the process. > Other than that, the process works just fine, and I strongly believe > that adding _more_ (web-based or other) tools in the mix will make > things worse, not better. We already have trac for issues, no need for > more tools. > If you have a soup, adding 10 knifes does not solve the problem. And it looks like there simply is no spoon for some problems. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From harald.gutmann at gmx.net Mon Jun 1 18:22:45 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Mon, 1 Jun 2009 18:22:45 +0200 Subject: [coreboot] Mptable fix for M57SLI Message-ID: <200906011822.52326.harald.gutmann@gmx.net> Hello, I've given it another try to fix the mptable of the M57SLI. The attached patch fixes for me the following things: * Nvidia graphic device works on PCIe-16x slot (black). * Both PCI cards in the two available slots work fine. * Also the PCIe 1x slots should work fine. (untested) It would be fine if someone of you could test and verify if that patch works on hardware revision v1 too. I hope that this fixes all the problems along with interrupts for this mainboard and I'm looking forward that someone can verify/test this. Kind regards, Harald PS: Is it necessary to add PCI_INT for 00:08/07.01-03? -------------- next part -------------- A non-text attachment was scrubbed... Name: mptable-irq-fix.diff Type: text/x-patch Size: 4703 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From mylesgw at gmail.com Mon Jun 1 18:47:01 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 1 Jun 2009 10:47:01 -0600 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: <200905312010.40131.patrick@georgi-clan.de> References: <200905312010.40131.patrick@georgi-clan.de> Message-ID: <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> On Sun, May 31, 2009 at 12:10 PM, Patrick Georgi wrote: > Hi, > > attached patch changes the bootblock generation for CBFS images. > It uses coreboot.rom (padded and all), but defaults to smaller fallback/normal > image sizes. > It requires changes to each CBFS aware mainboard config (and requires adaption > on conversion), but it fixes using normal image (as the offsets are calculated > correctly). I thought the next step was normal in CBFS. This doesn't seem to get us closer to that. > I tried to get rid of ROM_IMAGE_SIZE and friends, but that'll have to wait > until non-CBFS images are gone - maintaining two separate build configurations > in a single build system isn't fun. Until non-CBFS images are gone per board, or for all boards? Thanks, Myles From patrick at georgi-clan.de Mon Jun 1 19:01:46 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 01 Jun 2009 19:01:46 +0200 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> References: <200905312010.40131.patrick@georgi-clan.de> <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> Message-ID: <4A24097A.2000700@georgi-clan.de> Myles Watson schrieb: > On Sun, May 31, 2009 at 12:10 PM, Patrick Georgi wrote: > >> Hi, >> >> attached patch changes the bootblock generation for CBFS images. >> It uses coreboot.rom (padded and all), but defaults to smaller fallback/normal >> image sizes. >> It requires changes to each CBFS aware mainboard config (and requires adaption >> on conversion), but it fixes using normal image (as the offsets are calculated >> correctly). >> > > I thought the next step was normal in CBFS. This doesn't seem to get > us closer to that. > The "normal" image is executed with "jmp __normal_image". __normal_image is defined as 8 bytes before the first byte of fallback/coreboot.rom (the reset vector of the normal image). Without this patch, we use fallback/coreboot.strip, which is typically smaller. That's a nice way to automatically reduce the size of the bootblock, but it's hard to figure out its size (without resorting to two link steps and weird calculations inbetween), but __normal_image points to some place where the normal image most likely doesn't reside. Thus, we actually have to change the coreboot.rom's sizes manually (to decrease the bootblock's size) if we want normal to work - we don't do that so far, we simply use coreboot.strip. >> I tried to get rid of ROM_IMAGE_SIZE and friends, but that'll have to wait >> until non-CBFS images are gone - maintaining two separate build configurations >> in a single build system isn't fun. >> > > Until non-CBFS images are gone per board, or for all boards? > I intend to kill the non-CBFS infrastructure some weeks after everything is officially moved over. This patch fixes the last known (to me) regression of CBFS over non-CBFS. So the timeline would be: - this patch + changes to CBFS boards to build correctly - patch to get all boards over to CBFS (test as many of them as possible: I can provide testing for 4 boards by three cpu/chipset vendors + qemu) - wait some weeks - remove non-CBFS code - clean up what's possible Regards, Patrick From mylesgw at gmail.com Mon Jun 1 19:13:20 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 1 Jun 2009 11:13:20 -0600 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: <4A24097A.2000700@georgi-clan.de> References: <200905312010.40131.patrick@georgi-clan.de> <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> <4A24097A.2000700@georgi-clan.de> Message-ID: > > I thought the next step was normal in CBFS. This doesn't seem to get > > us closer to that. > > > The "normal" image is executed with "jmp __normal_image". __normal_image > is defined as 8 bytes before the first byte of fallback/coreboot.rom > (the reset vector of the normal image). Yes. I thought we were going to do something like cbfs_call("normal"); //totally made up. Which would look in cbfs for the normal image, decompress it if necessary, and call it. What you're doing makes the normal image work again, but doesn't put it into CBFS. > Thus, we actually have to change the coreboot.rom's sizes manually (to > decrease the bootblock's size) if we want normal to work - we don't do > that so far, we simply use coreboot.strip. Right. > > Until non-CBFS images are gone per board, or for all boards? > > > I intend to kill the non-CBFS infrastructure some weeks after everything > is officially moved over. This patch fixes the last known (to me) > regression of CBFS over non-CBFS. > So the timeline would be: > > - this patch + changes to CBFS boards to build correctly > - patch to get all boards over to CBFS (test as many of them as > possible: I can provide testing for 4 boards by three cpu/chipset > vendors + qemu) > - wait some weeks > - remove non-CBFS code This is the place where you put in cbfs_call("normal") ? Thanks for the overview. Acked-by: Myles Watson Thanks, Myles From patrick at georgi-clan.de Mon Jun 1 19:19:24 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 01 Jun 2009 19:19:24 +0200 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: References: <200905312010.40131.patrick@georgi-clan.de> <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> <4A24097A.2000700@georgi-clan.de> Message-ID: <4A240D9C.1020908@georgi-clan.de> Myles Watson schrieb: > Yes. I thought we were going to do something like > > cbfs_call("normal"); //totally made up. > What we already do is storing coreboot_ram in CBFS. > Which would look in cbfs for the normal image, decompress it if necessary, > and call it. > The first stage is pre-raminit, so we can't decompress or copy it - it must be XIP. > What you're doing makes the normal image work again, but doesn't put it into > CBFS. > Ron was working on some support to allow XIP stages in CBFS (uncompressed, but registered in there), but that requires more work. I won't try to hack the build system anymore before non-CBFS is gone: separating the earlier coreboot stages into CBFS would require two different build code paths for that part again, and slowly, that's too much hassle for me. I'll revisit pushing the pre-raminit stage into CBFS after I don't have to care about non-CBFS anymore. By the way, one idea to solve the XIP execution might be to use %cs to allow running the stage from a semi-arbitrary memory location (by setting %cs in a way that addresses in code and ROM layout match again). That could already be looked into now. Patrick From mylesgw at gmail.com Mon Jun 1 19:23:25 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 1 Jun 2009 11:23:25 -0600 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: <4A240D9C.1020908@georgi-clan.de> References: <200905312010.40131.patrick@georgi-clan.de> <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> <4A24097A.2000700@georgi-clan.de> <4A240D9C.1020908@georgi-clan.de> Message-ID: <2831fecf0906011023n4ebfd468x8830b6dfb25276bd@mail.gmail.com> > The first stage is pre-raminit, so we can't decompress or copy it - it must > be XIP. Good reminder. I'm always forgetting that we have different raminits for fallback or normal. > I won't try to hack the build system anymore before non-CBFS is gone: > separating the earlier coreboot stages into CBFS would require two different > build code paths for that part again, and slowly, that's too much hassle for > me. Agreed. > I'll revisit pushing the pre-raminit stage into CBFS after I don't have to > care about non-CBFS anymore. Yes. I'll agree that's lower priority anyway. > By the way, one idea to solve the XIP execution might be to use %cs to allow > running the stage from a semi-arbitrary memory location (by setting %cs in a > way that addresses in code and ROM layout match again). That could already > be looked into now. OK. Thanks, Myles From mylesgw at gmail.com Mon Jun 1 19:58:59 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 1 Jun 2009 11:58:59 -0600 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: <4A24097A.2000700@georgi-clan.de> References: <200905312010.40131.patrick@georgi-clan.de> <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> <4A24097A.2000700@georgi-clan.de> Message-ID: <2831fecf0906011058h1fce0eb2i709e501f461ab430@mail.gmail.com> > I intend to kill the non-CBFS infrastructure some weeks after everything is > officially moved over. I'm not sure how much this buys us. Since we know this is the way we want to go, keeping the non-CBFS stuff around just confuses the issue. I think the fewer commits to kill it, the better. > So the timeline would be: > > - this patch + changes to CBFS boards to build correctly > - patch to get all boards over to CBFS (test as many of them as possible: I > can provide testing for 4 boards by three cpu/chipset vendors + qemu) > - remove non-CBFS code > - clean up what's possible The same without "wait some weeks." Things will break during this transition. Let's make it short. Thanks, Myles From patrick at georgi-clan.de Mon Jun 1 21:23:55 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 01 Jun 2009 21:23:55 +0200 Subject: [coreboot] [PATCH] Stop build if coreboot.rom.bootblock is larger than the area allocated to the bootblock Message-ID: <4A242ACB.8070603@georgi-clan.de> Hi, attached patch fixes an oversight in cbfstool related to bootblock handling. With this patch, cbfstool reacts to a too large bootblock file by stopping with an error code. Before, it did "whatever" (besides printing a warning). Signed-off-by: Patrick Georgi -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090601-stop-on-too-large-bootblock URL: From peter at stuge.se Mon Jun 1 21:33:05 2009 From: peter at stuge.se (Peter Stuge) Date: Mon, 1 Jun 2009 21:33:05 +0200 Subject: [coreboot] [PATCH] Stop build if coreboot.rom.bootblock is larger than the area allocated to the bootblock In-Reply-To: <4A242ACB.8070603@georgi-clan.de> References: <4A242ACB.8070603@georgi-clan.de> Message-ID: <20090601193306.28559.qmail@stuge.se> Patrick Georgi wrote: > Hi, > > attached patch fixes an oversight in cbfstool related to bootblock > handling. > With this patch, cbfstool reacts to a too large bootblock file by stopping > with an error code. Before, it did "whatever" (besides printing a warning). > > > Signed-off-by: Patrick Georgi Acked-by: Peter Stuge From stepan at coresystems.de Mon Jun 1 21:47:27 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Mon, 01 Jun 2009 21:47:27 +0200 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: <2831fecf0906011058h1fce0eb2i709e501f461ab430@mail.gmail.com> References: <200905312010.40131.patrick@georgi-clan.de> <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> <4A24097A.2000700@georgi-clan.de> <2831fecf0906011058h1fce0eb2i709e501f461ab430@mail.gmail.com> Message-ID: <4A24304F.60305@coresystems.de> On 01.06.2009 19:58 Uhr, Myles Watson wrote: >> - this patch + changes to CBFS boards to build correctly >> - patch to get all boards over to CBFS (test as many of them as possible: I >> can provide testing for 4 boards by three cpu/chipset vendors + qemu) >> - remove non-CBFS code >> - clean up what's possible >> > > The same without "wait some weeks." > > Things will break during this transition. Let's make it short. > > The waiting period is not about waiting, but rather careful preparation... Not sure we want to cut that. Also, there are still spurious bugs in CBFS. Let's make sure they're gone before we cut the bridges. We did that in v3 and it was a disaster. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mylesgw at gmail.com Mon Jun 1 21:55:05 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 1 Jun 2009 13:55:05 -0600 Subject: [coreboot] [PATCH] use coreboot.rom for CBFS images, but default to smaller size In-Reply-To: <4A24304F.60305@coresystems.de> References: <200905312010.40131.patrick@georgi-clan.de> <2831fecf0906010947t61a9d652i23dbcc8d28f43ec9@mail.gmail.com> <4A24097A.2000700@georgi-clan.de> <2831fecf0906011058h1fce0eb2i709e501f461ab430@mail.gmail.com> <4A24304F.60305@coresystems.de> Message-ID: <2831fecf0906011255u4e7a663cg481954ed87b9224a@mail.gmail.com> > The waiting period is not about waiting, but rather careful preparation... In that case I misunderstood the timeline. It looked like a "See if anyone screams" period to me. > Also, there are still spurious bugs in CBFS. Let's make sure they're gone > before we cut the bridges. We did that in v3 and it was a disaster. Agreed. I just don't want to prolong the pain or make too many intermediate steps. I think it's easier to say "Everyone test your board because the last commit may have broken it." than to say "Everyone test the next 8 commits." As long as we're sure of the direction we can fix what breaks. Thanks, Myles From svn at coreboot.org Mon Jun 1 22:02:21 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Mon, 1 Jun 2009 22:02:21 +0200 Subject: [coreboot] [v2] r4329 - trunk/coreboot-v2/util/cbfstool Message-ID: Author: oxygene Date: 2009-06-01 22:02:21 +0200 (Mon, 01 Jun 2009) New Revision: 4329 Modified: trunk/coreboot-v2/util/cbfstool/util.c Log: cbfstool reacts to a too large bootblock file by stopping with an error code now. Signed-off-by: Patrick Georgi Acked-by: Peter Stuge Modified: trunk/coreboot-v2/util/cbfstool/util.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/util.c 2009-06-01 01:38:29 UTC (rev 4328) +++ trunk/coreboot-v2/util/cbfstool/util.c 2009-06-01 20:02:21 UTC (rev 4329) @@ -222,7 +222,8 @@ rom->header->align = htonl(align); rom->header->offset = htonl(0); - add_bootblock(rom, bootblockname); + if (add_bootblock(rom, bootblockname) == -1) + return -1; /* Write the cbfs master header address at the end of the ROM. */ From audiossis at netspace.net.au Mon Jun 1 22:24:35 2009 From: audiossis at netspace.net.au (Ben) Date: Tue, 2 Jun 2009 06:24:35 +1000 Subject: [coreboot] Builing Coreboot In-Reply-To: <20090601012310.9719.qmail@stuge.se> References: <1243812453.4a2312657e939@webmail.netspace.net.au> <20090601012310.9719.qmail@stuge.se> Message-ID: <200906020624.35429.audiossis@netspace.net.au> On Monday 01 June 2009 11:23:09 Peter Stuge wrote: > Hi Ben, > > audiossis at netspace.net.au wrote: > > My target system is a Clevo laptop > > What Carl-Daniel wrote about embedded controllers applies. But since > you can recover, it might still be interesting to give it a go. > > > (albeit I understand that the 82855PM/GM is still a work in progress) > > I have met at least one person who has production 855 code, I will > get in touch with them if you find that current code is lacking. > > > I know that I have to edit a configuration file to specify the > > payload I wish to use, > > Yes. > > > but I cannot find anything that tells me wether or not I have to > > configure Coreboot for the specific chipset on the target > > mainboard. > > Carl-Daniel mentioned targets. This is the starting point when > building coreboot. > > In the v2 tree, there is the targets/ directory. In there you find > all targets, grouped by vendor. There is no target for your exact > system, so find one that is as close as possible. One target which > uses 855 is digitallogic/adl855pc. To build that, you do: > > cd targets > ./buildtarget digitallogic/adl855pc > cd digitallogic/adl855pc/adl855pc > make > > (you can also run make -C digitallogic/adl855pc/adl855pc and skip cd) > > After those commands, you should have a coreboot.rom file. > > The payload is specified in digitallogic/adl855pc/Config.lb, which is > parsed by buildtarget and used to create Makefiles underneath the > final leaf directory. If you change Config.lb, you have to re-run > buildtarget. > > Note that buildtarget doesn't check for the payload, so you'll get > Makefiles which fail to build. > > Then try booting coreboot.rom in your system. Chances are zero that > it will work, but if the laptop is a little similar to the > digitallogic, you may get serial output. Most likely you'll have to > change the superio though, in > src/mainboard/digitallogic/adl855pc/Config.lb to the superio which is > used in the laptop, before you get anything from the serial port. > > > //Peter Thanks guys, I've had another look at the source code as was suggested and read through the developer documents on the web site again. I think I have a better grasp of the situation now. I found what I think are the CPU and chipset config settings in the and over the next week I'll gear up to have a go at a desktop mainboard (simpler to repair if something goes wrong). If I get it working I'll post my config files. Then I'll consider trying on the laptop. I've no doubt I'll need to ask you some more questions very soon..... I'll try not to be too annoying though.... Thanks again for your time! Ben From svn at coreboot.org Mon Jun 1 23:30:42 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Mon, 1 Jun 2009 23:30:42 +0200 Subject: [coreboot] [flashrom] r561 - trunk Message-ID: Author: hailfinger Date: 2009-06-01 23:30:42 +0200 (Mon, 01 Jun 2009) New Revision: 561 Modified: trunk/board_enable.c Log: Refactor HT-1000 GPIO setting to use sio_mask. Although the HT-1000 GPIOs are not SuperIO related, the share the same index/data register access method. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-01 02:08:58 UTC (rev 560) +++ trunk/board_enable.c 2009-06-01 21:30:42 UTC (rev 561) @@ -365,25 +365,20 @@ static int board_ibm_x3455(const char *name) { - uint8_t byte; - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - OUTB(0x45, 0xcd6); - byte = INB(0xcd7); - OUTB(byte | 0x20, 0xcd7); + /* It's not a superio but it uses the same index/data port method. */ + sio_mask(0xcd6, 0x45, 0x20, 0x20); return 0; } static int board_hp_dl145_g3_enable(const char *name) { - uint8_t byte; - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - OUTB(0x44, 0xcd6); /* GPIO 0 reg from PM regs */ - byte = INB(0xcd7); + /* GPIO 0 reg from PM regs */ /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ - OUTB(byte | 0x24, 0xcd7); + /* It's not a superio but it uses the same index/data port method. */ + sio_mask(0xcd6, 0x44, 0x24, 0x24); return 0; } From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 23:31:38 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 23:31:38 +0200 Subject: [coreboot] [PATCH] flashrom: Refactor HT-1000 GPIO setting In-Reply-To: <20090601010809.GY18065@greenwood> References: <4A1B2D1C.3010303@gmx.net> <13426df10905251858y18ed51a7oaa0646411db16d24@mail.gmail.com> <20090601010809.GY18065@greenwood> Message-ID: <4A2448BA.9030209@gmx.net> Hi Mondrian, could you test if flashrom r561 still works for you? Thanks! On 01.06.2009 03:08, Uwe Hermann wrote: > On Mon, May 25, 2009 at 06:58:42PM -0700, ron minnich wrote: > >> Has this been tested anywhere? >> >> I get a little worried about changes like this, which look fine in the >> abstract, unless they are tested. It "should" work, it looks fine to >> me, but ... >> > > Yeah, should work. Sure, testing would be nice also, but I think it's ok > to commit this. > > Acked-by: Uwe Hermann > Thanks, committed in r561. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Mon Jun 1 23:37:01 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Mon, 1 Jun 2009 23:37:01 +0200 Subject: [coreboot] [flashrom] r562 - trunk Message-ID: Author: hailfinger Date: 2009-06-01 23:37:00 +0200 (Mon, 01 Jun 2009) New Revision: 562 Modified: trunk/flashrom.c Log: Add a missing free() in read_flash(). Signed-off-by: Stephan Guilloux Acked-by: Carl-Daniel Hailfinger Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-01 21:30:42 UTC (rev 561) +++ trunk/flashrom.c 2009-06-01 21:37:00 UTC (rev 562) @@ -332,6 +332,7 @@ numbytes = fwrite(buf, 1, size, image); fclose(image); + free(buf); printf("%s.\n", numbytes == size ? "done" : "FAILED"); if (numbytes != size) return 1; From c-d.hailfinger.devel.2006 at gmx.net Mon Jun 1 23:37:53 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 01 Jun 2009 23:37:53 +0200 Subject: [coreboot] [flashrom] Missing free() in read_flash (just for the form) In-Reply-To: <4A1B3623.8000002@free.fr> References: <4A1B3623.8000002@free.fr> Message-ID: <4A244A31.3020804@gmx.net> On 26.05.2009 02:21, Stephan GUILLOUX wrote: > Just a missing free() in read_flash(). > > Signed-off-by: Stephan Guilloux > Acked-by: Carl-Daniel Hailfinger Thanks, committed in r561. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Tue Jun 2 00:07:52 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 2 Jun 2009 00:07:52 +0200 Subject: [coreboot] [flashrom] r563 - trunk Message-ID: Author: hailfinger Date: 2009-06-02 00:07:52 +0200 (Tue, 02 Jun 2009) New Revision: 563 Modified: trunk/flashrom.c Log: Use read_flash() when flash chip probe is forced. Signed-off-by: Stephan Guilloux Acked-by: Carl-Daniel Hailfinger Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-01 21:37:00 UTC (rev 562) +++ trunk/flashrom.c 2009-06-01 22:07:52 UTC (rev 563) @@ -314,6 +314,11 @@ FILE *image; unsigned long size = flash->total_size * 1024; unsigned char *buf = calloc(size, sizeof(char)); + + if (!filename) { + printf("Error: No filename specified.\n"); + return 1; + } if ((image = fopen(filename, "w")) == NULL) { perror(filename); exit(1); @@ -670,35 +675,7 @@ printf("Run flashrom -L to view the hardware supported in this flashrom version.\n"); exit(1); } - if (!filename) { - printf("Error: No filename specified.\n"); - exit(1); - } - size = flashes[0]->total_size * 1024; - buf = (uint8_t *) calloc(size, sizeof(char)); - - if ((image = fopen(filename, "w")) == NULL) { - perror(filename); - exit(1); - } - printf("Force reading flash... "); - if (!flashes[0]->read) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); - return 1; - } else - flashes[0]->read(flashes[0], buf); - - if (exclude_end_position - exclude_start_position > 0) - memset(buf + exclude_start_position, 0, - exclude_end_position - - exclude_start_position); - - numbytes = fwrite(buf, 1, size, image); - fclose(image); - printf("%s.\n", numbytes == size ? "done" : "FAILED"); - free(buf); - return numbytes != size; + return read_flash(flashes[0], filename, exclude_start_position, exclude_end_position); } // FIXME: flash writes stay enabled! exit(1); From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 00:08:23 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 00:08:23 +0200 Subject: [coreboot] [flashrom] Patch to factorize read_flash() use In-Reply-To: <4A1B2549.1070003@free.fr> References: <4A1B2549.1070003@free.fr> Message-ID: <4A245157.5040509@gmx.net> On 26.05.2009 01:10, Stephan GUILLOUX wrote: > A simple patch to use read_flash() when flash chip probe is probed. > > Unfortunatelly, I cannot test it... If anyone can do the job for me... > > Signed-off-by: Stephan Guilloux I recreated your patch from scratch to verify it and our results match. Acked-by: Carl-Daniel Hailfinger Thanks, committed with some cosetic changes in r563. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 01:19:23 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 01:19:23 +0200 Subject: [coreboot] [PATCH] flashrom: Refactor SPI reads Message-ID: <4A2461FB.7040307@gmx.net> Every SPI host controller implemented its own way to read flash chips. This was partly due to a design problem in the abstraction layer. There should be exactly two different functions for reading SPI chips: - memory mapped reads - SPI command reads. Each of them should be contained in a separate function, optionally taking parameters where needed. This patch solves the problems mentioned above, shortens the code and makes the code logic a lot more obvious. Since open-coding the min() function leads to errors, include it in this patch as well. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-spi_read_refactor/flash.h =================================================================== --- flashrom-spi_read_refactor/flash.h (Revision 563) +++ flashrom-spi_read_refactor/flash.h (Arbeitskopie) @@ -679,6 +679,7 @@ extern int verbose; #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); +int min(int a, int b); int read_memmapped(struct flashchip *flash, uint8_t *buf); extern char *pcidev_bdf; @@ -726,6 +727,7 @@ int spi_disable_blockprotect(void); void spi_byte_program(int address, uint8_t byte); int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_read_generic(struct flashchip *flash, uint8_t *buf, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Index: flashrom-spi_read_refactor/it87spi.c =================================================================== --- flashrom-spi_read_refactor/it87spi.c (Revision 563) +++ flashrom-spi_read_refactor/it87spi.c (Arbeitskopie) @@ -260,18 +260,12 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; fast_spi = 0; if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - for (i = 0; i < total_size; i += 3) { - int toread = 3; - if (total_size - i < toread) - toread = total_size - i; - spi_nbyte_read(i, buf + i, toread); - } + spi_read_generic(flash, buf, 3); } else { - memcpy(buf, (const char *)flash->virtual_memory, total_size); + read_memmapped(flash, buf); } return 0; Index: flashrom-spi_read_refactor/spi.c =================================================================== --- flashrom-spi_read_refactor/spi.c (Revision 563) +++ flashrom-spi_read_refactor/spi.c (Arbeitskopie) @@ -652,6 +652,33 @@ return spi_command(sizeof(cmd), len, cmd, bytes); } +/* + * Read a complete flash chip. + * Each page is read separately in chunks with a maximum size of chunksize. + */ +int spi_read_generic(struct flashchip *flash, uint8_t *buf, int chunksize) +{ + int rc = 0; + int i, j; + int total_size = flash->total_size * 1024; + int page_size = flash->page_size; + int toread; + + for (j = 0; j < total_size / page_size; j++) { + for (i = 0; i < page_size; i += chunksize) { + toread = min(chunksize, page_size - i); + rc = spi_nbyte_read(j * page_size + i, + buf + j * page_size + i, toread); + if (rc) + break; + } + if (rc) + break; + } + + return rc; +} + int spi_chip_read(struct flashchip *flash, uint8_t *buf) { switch (spi_controller) { Index: flashrom-spi_read_refactor/wbsio_spi.c =================================================================== --- flashrom-spi_read_refactor/wbsio_spi.c (Revision 563) +++ flashrom-spi_read_refactor/wbsio_spi.c (Arbeitskopie) @@ -177,12 +177,12 @@ { int size = flash->total_size * 1024; - if (flash->total_size > 1024) { + if (size > 1024 * 1024) { fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - memcpy(buf, (const char *)flash->virtual_memory, size); + read_memmapped(flash, buf); return 0; } Index: flashrom-spi_read_refactor/sb600spi.c =================================================================== --- flashrom-spi_read_refactor/sb600spi.c (Revision 563) +++ flashrom-spi_read_refactor/sb600spi.c (Arbeitskopie) @@ -41,14 +41,8 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf) { - int rc = 0, i; - int total_size = flash->total_size * 1024; - int page_size = 8; - - for (i = 0; i < total_size / page_size; i++) - spi_nbyte_read(i * page_size, (void *)(buf + i * page_size), - page_size); - return rc; + /* Maximum read length is 8 bytes. */ + return spi_read_generic(flash, buf, 8); } uint8_t sb600_read_status_register(void) Index: flashrom-spi_read_refactor/flashrom.c =================================================================== --- flashrom-spi_read_refactor/flashrom.c (Revision 563) +++ flashrom-spi_read_refactor/flashrom.c (Arbeitskopie) @@ -174,6 +174,11 @@ return 0; } +int min(int a, int b) +{ + return (a < b) ? a : b; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); Index: flashrom-spi_read_refactor/ichspi.c =================================================================== --- flashrom-spi_read_refactor/ichspi.c (Revision 563) +++ flashrom-spi_read_refactor/ichspi.c (Arbeitskopie) @@ -148,8 +148,6 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, - int offset, int maxdata); static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata); @@ -614,38 +612,6 @@ return -1; } -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, - int maxdata) -{ - int page_size = flash->page_size; - uint32_t remaining = flash->page_size; - int a; - - printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, buf); - - for (a = 0; a < page_size; a += maxdata) { - if (remaining < maxdata) { - - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], remaining)) { - printf_debug("Error reading"); - return 1; - } - remaining = 0; - } else { - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], maxdata)) { - printf_debug("Error reading"); - return 1; - } - remaining -= maxdata; - } - } - - return 0; -} - static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata) { @@ -683,21 +649,12 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf) { - int i, rc = 0; - int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) { + if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; - } - for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { - rc = ich_spi_read_page(flash, (void *)(buf + i * page_size), - i * page_size, maxdata); - } - - return rc; + return spi_read_generic(flash, buf, maxdata); } int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_spi_read_refactor01.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 01:26:00 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 01:26:00 +0200 Subject: [coreboot] [flashrom][patch] enable/use flash chip read/erase return codes In-Reply-To: <4A1B3D13.8080501@free.fr> References: <4A1B3D13.8080501@free.fr> Message-ID: <4A246388.1080300@gmx.net> Hi Stephan, On 26.05.2009 02:51, Stephan GUILLOUX wrote: > Use chips read/erase return codes. erase() is not > fully modified, though. > flash_read() is unchanged, as I also have a patch pending in this area. > > Signed-off-by: Stephan Guilloux > > Index: flashrom-read-return-code/trunk/it87spi.c > [...] > Index: flashrom-read-return-code/trunk/sb600spi.c > [...] > I just sent a patch which refactors reading and probably conflicts with this part of your patch. > Index: flashrom-read-return-code/trunk/flashrom.c > =================================================================== > --- flashrom-read-return-code/trunk/flashrom.c (r?vision 547) > +++ flashrom-read-return-code/trunk/flashrom.c (copie de travail) > @@ -208,12 +208,19 @@ > + if (flash->read(flash, buf2)) { > + printf("FAILED!\n"); > + fprintf(stderr, "ERROR : flashrom cannot read this flash chip.\n"); > This error message is misleading. It's not the fault of the flash chip. I think the "FAILED" output is enough. > @@ -286,15 +293,28 @@ > + if (flash->erase(flash)) { > + printf("FAILED!\n"); > + fprintf(stderr, "ERROR: flashrom cannot erase this flash chip.\n"); > Same here and in other places in the patch. Can you take a look at my patch and check if it fixes the issues you pointed out in the first part of your patch? Can you resubmit the second part of your patch with changed error messages? Thanks. Regards, Carl-Daniel -- http://www.hailfinger.org/ From kevin at koconnor.net Tue Jun 2 01:56:14 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Mon, 1 Jun 2009 19:56:14 -0400 Subject: [coreboot] LGPL vgabios on real hardware In-Reply-To: <20090601122206.4418.qmail@stuge.se> References: <20090601030358.GA29555@morn.localdomain> <20090601122206.4418.qmail@stuge.se> Message-ID: <20090601235614.GA6486@morn.localdomain> On Mon, Jun 01, 2009 at 02:22:06PM +0200, Peter Stuge wrote: > Kevin O'Connor wrote: > > To obtain the code and compile an option rom, run: > > > > git clone git://git.linuxtogo.org/home/kevin/seabios.git > > cd seabios > > make out/vgabios.bin [...] > Please please put this in a separate repo. The VGA code uses code from SeaBIOS to implement some of the 16bit infrastructure. If the vga code was moved into a new repo, this code would have to be copied. It's possible to move it, but I don't think it's a high priority right now. The VGA bios is in many ways similar to the regular bios - so I don't think it's a total mismatch to keep them together. -Kevin From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 02:30:57 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 02:30:57 +0200 Subject: [coreboot] [patch]: a little error is fixed. In-Reply-To: References: Message-ID: <4A2472C1.8060105@gmx.net> On 01.06.2009 04:34, Bao, Zheng wrote: > Modify it based on the RPR. 5.7.7. Switching GPPSB Configuration By > Register Programming. > > Signed-off-by: Zheng Bao > Acked-by: Carl-Daniel Hailfinger Do you have commit rights or should I commit? Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Tue Jun 2 02:38:14 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 2 Jun 2009 02:38:14 +0200 Subject: [coreboot] [flashrom] r564 - trunk Message-ID: Author: hailfinger Date: 2009-06-02 02:38:14 +0200 (Tue, 02 Jun 2009) New Revision: 564 Modified: trunk/flash.h trunk/flashchips.c Log: Unify AMD manufacture_id and model_id Signed-off-by: Mateusz Murawski Acked-by: FENG Yu Ning Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-01 22:07:52 UTC (rev 563) +++ trunk/flash.h 2009-06-02 00:38:14 UTC (rev 564) @@ -248,7 +248,9 @@ #define AM_29F002BT 0xB0 #define AM_29F002BB 0x34 #define AM_29F040B 0xA4 +#define AM_29F080B 0xD5 #define AM_29LV040B 0x4F +#define AM_29LV081B 0x38 #define AM_29F016D 0xAD #define AMIC_ID 0x7F37 /* AMIC */ Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-01 22:07:52 UTC (rev 563) +++ trunk/flashchips.c 2009-06-02 00:38:14 UTC (rev 564) @@ -101,8 +101,8 @@ .vendor = "AMD", .name = "Am29F080B", .bustype = CHIP_BUSTYPE_NONSPI, - .manufacture_id = 0x01, - .model_id = 0xd5, + .manufacture_id = AMD_ID, + .model_id = AM_29F080B, .total_size = 1024, .page_size = 64 * 1024, .tested = TEST_UNTESTED, @@ -131,8 +131,8 @@ .vendor = "AMD", .name = "Am29LV081B", .bustype = CHIP_BUSTYPE_NONSPI, - .manufacture_id = 0x01, - .model_id = 0x38, + .manufacture_id = AMD_ID, + .model_id = AM_29LV081B, .total_size = 1024, .page_size = 64 * 1024, .tested = TEST_UNTESTED, From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 02:38:47 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 02:38:47 +0200 Subject: [coreboot] flashrom: small patch In-Reply-To: References: <4A06CE23.2080902@tlen.pl> <4A06CF71.1070208@tlen.pl> Message-ID: <4A247497.7050902@gmx.net> On 11.05.2009 16:27, FENG Yu Ning wrote: > Murawski Mateusz wrote: > >> Unify AMD manufacture_id and model_id >> Signed-off-by: Mateusz Murawski >> > > Acked-by: FENG Yu Ning > > This is a minor improvement. I think it is ready to commit. > Thanks, committed in r564. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 02:44:08 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 02:44:08 +0200 Subject: [coreboot] [FLASHROM] Add support for 3COM NICs and Atmel AT49BV512 In-Reply-To: References: <20090513021018.GC13677@greenwood> <4A0A9B6C.2050401@gmx.net> <20090513113641.GB18306@greenwood> Message-ID: <4A2475D8.3080002@gmx.net> On 15.05.2009 01:29, Idwer Vollering wrote: > Index: nic3com.c > =================================================================== > --- nic3com.c (revision 501) > +++ nic3com.c (working copy) > @@ -51,6 +51,9 @@ > int status; > const char *device_name; > } nics[] = { > + /* 3c90x */ > + {0x9050, OK, "3c905: Fast EtherLink XL PCI (3c905-TX)" }, > + > > Signed-off-by: Idwer > Can you please resend this patch as an attachment? It seems your mailer mangled the patch so it won't apply. Regards, Carl-Daniel -- http://www.hailfinger.org/ From vidwer at gmail.com Tue Jun 2 03:18:41 2009 From: vidwer at gmail.com (Idwer Vollering) Date: Tue, 2 Jun 2009 03:18:41 +0200 Subject: [coreboot] [FLASHROM] Add support for 3COM NICs and Atmel AT49BV512 In-Reply-To: <4A2475D8.3080002@gmx.net> References: <20090513021018.GC13677@greenwood> <4A0A9B6C.2050401@gmx.net> <20090513113641.GB18306@greenwood> <4A2475D8.3080002@gmx.net> Message-ID: 2009/6/2 Carl-Daniel Hailfinger > On 15.05.2009 01:29, Idwer Vollering wrote: > > Index: nic3com.c > > =================================================================== > > --- nic3com.c (revision 501) > > +++ nic3com.c (working copy) > > @@ -51,6 +51,9 @@ > > int status; > > const char *device_name; > > } nics[] = { > > + /* 3c90x */ > > + {0x9050, OK, "3c905: Fast EtherLink XL PCI (3c905-TX)" }, > > + > > > > Signed-off-by: Idwer > > > > Can you please resend this patch as an attachment? It seems your mailer > mangled the patch so it won't apply. Please don't use this patch, it is just there to make NIC detection work, not chip detection/programming/etcetera. Why I put "OK" in it: probably to make flashrom detect it (patch based on r501, beware). Also I have no idea what chip size this card can handle, <=64KB ? http://www.infracity.de/pxe/#list > > Regards, > Carl-Daniel > > -- > http://www.hailfinger.org/ > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From Zheng.Bao at amd.com Tue Jun 2 03:52:54 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Tue, 2 Jun 2009 09:52:54 +0800 Subject: [coreboot] [patch]: a little error is fixed. In-Reply-To: <4A2472C1.8060105@gmx.net> References: <4A2472C1.8060105@gmx.net> Message-ID: I don't have commit right. I don't know the exact process to apply it. It would be better if I can get the commit right to the amd/rs690 and amd/sb600. Zheng -----Original Message----- From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Carl-Daniel Hailfinger Sent: Tuesday, June 02, 2009 8:31 AM To: Bao, Zheng Cc: coreboot Subject: Re: [coreboot] [patch]: a little error is fixed. On 01.06.2009 04:34, Bao, Zheng wrote: > Modify it based on the RPR. 5.7.7. Switching GPPSB Configuration By > Register Programming. > > Signed-off-by: Zheng Bao > Acked-by: Carl-Daniel Hailfinger Do you have commit rights or should I commit? Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 04:23:36 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 04:23:36 +0200 Subject: [coreboot] [patch]: a little error is fixed. In-Reply-To: References: <4A2472C1.8060105@gmx.net> Message-ID: <4A248D28.3030103@gmx.net> Hi Zheng, On 02.06.2009 03:52, Bao, Zheng wrote: > I don't have commit right. I don't know the exact process to apply it. > It would be better if I can get the commit right to the amd/rs690 and > amd/sb600. > Commit rights are for the whole tree and are given to people who will work on the tree a lot in the future. I hope you can submit and commit the 780/SB700 code soon. Stefan manages commit rights. I have added him to this mail. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 05:10:58 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 05:10:58 +0200 Subject: [coreboot] Adding 740G support to RS690 code Message-ID: <4A249842.2010100@gmx.net> Hi Zheng, since the AMD web site says the 740G is just a shrunk 690G with new graphics, would it be possible to add 740G support to the RS690 code easily? Can we use the RS690 code without changes? Regards, Carl-Daniel -- http://www.hailfinger.org/ From Zheng.Bao at amd.com Tue Jun 2 05:55:18 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Tue, 2 Jun 2009 11:55:18 +0800 Subject: [coreboot] Adding 740G support to RS690 code In-Reply-To: <4A249842.2010100@gmx.net> References: <4A249842.2010100@gmx.net> Message-ID: I took a quick look at the rs740 rpr. It is true that it is almost the same as rs690. The only difference I got is the device id of internal graphics. Since it can be got by typing lspci, I guess it doesn't hurt anyone if I tell you. The rs740 (which I think is also 740G) is 796E, rs740M is 796F. I don't have 740 board here. Even if I had, my boss would be mad if I did this. He believes his job is higher priority. If you can try it, you can modify the device id and try to get the VGA Option Rom. I think that is only thing you have to do. Zheng -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] Sent: Tuesday, June 02, 2009 11:11 AM To: Bao, Zheng; Coreboot Subject: [coreboot] Adding 740G support to RS690 code Hi Zheng, since the AMD web site says the 740G is just a shrunk 690G with new graphics, would it be possible to add 740G support to the RS690 code easily? Can we use the RS690 code without changes? Regards, Carl-Daniel -- http://www.hailfinger.org/ From lasaine at lvk.cs.msu.su Tue Jun 2 10:56:42 2009 From: lasaine at lvk.cs.msu.su (Alexander Gordeev) Date: Tue, 2 Jun 2009 12:56:42 +0400 Subject: [coreboot] flashrom touches only 0x70000-0x80000 addresses of my bios flash In-Reply-To: <4A1FE199.9030701@gmx.net> References: <200905242019.44553.lasaine@lvk.cs.msu.su> <200905272331.59662.lasaine@lvk.cs.msu.su> <4A1E7C58.2000203@gmx.net> <200905282304.31381.lasaine@lvk.cs.msu.su> <4A1FC9B9.60303@gmx.net> <20090529164137.082fc377@desktopvm.lvknet> <4A1FE199.9030701@gmx.net> Message-ID: <20090602125642.282c7afd@desktopvm.lvknet> On Fri, 29 May 2009 15:22:33 +0200 Carl-Daniel Hailfinger wrote: > On 29.05.2009 14:41, Alexander Gordeev wrote: > > So it seems the right way this time: when WP# is pulled low and > > TBL# is high leads to exactly the same situation as I have. > > > > Yes. I looked at the wrong data sheet when I requested WE# > information. Sorry. Not a problem at all :) > > On Fri, 29 May 2009 13:40:41 +0200 > > Carl-Daniel Hailfinger wrote: > > > > > >> GPIOs: 11(SIO), 12(inverted), 13, 14(SIO), 16(SIO), 17(SIO), > >> 35(pullup), 40(pullup), 53 > >> all SIOs are Input > >> SIO base: 0x0800 > >> > >> That leads me to the assumption that the WP# pin is probably not > >> connected to the SuperIO and the WE# pin may be connected to the > >> SuperIO, but without function. > >> > > > > I hope WP# is connected... > > > > It may be connected to the southbridge instead. That would make adding > code for it very difficult unless we find someone with specs. I've checked several times and there are no signs that WP or TBL are connected to the SuperIO. So they should be connected to southbridge indeed. And I don't have specs as well. May be I can just cut WP# pin off to disable protection? Thanks for your help! -- Alexander From libv at skynet.be Tue Jun 2 14:05:25 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 14:05:25 +0200 Subject: [coreboot] [v2] r4323 - trunk/coreboot-v2/src/arch/i386/lib In-Reply-To: <20090529130853.7E5C3700038@maildelivery025.isp.belgacom.be> References: <20090529130853.7E5C3700038@maildelivery025.isp.belgacom.be> Message-ID: <20090602120525.GA24611@skynet.be> On Fri, May 29, 2009 at 03:08:27PM +0200, svn at coreboot.org wrote: > Author: stepan > Date: 2009-05-29 15:08:27 +0200 (Fri, 29 May 2009) > New Revision: 4323 > > Modified: > trunk/coreboot-v2/src/arch/i386/lib/c_start.S > Log: > drop most of the crappy vm86 code and replace it with a rewritten > version that has all assembler in a .S file and all C code in a .c > file. Also, remove requirement to move around between GDTs. > > This version includes the suggestions from Peter to clean up CR0 manipulation > and to guard critical code paths by cli/sti. Tested and working on my hardware. > > Signed-off-by: Stefan Reinauer > Acked-by: Peter Stuge > > > > Modified: trunk/coreboot-v2/src/arch/i386/lib/c_start.S > =================================================================== > --- trunk/coreboot-v2/src/arch/i386/lib/c_start.S 2009-05-29 03:44:47 UTC (rev 4322) > +++ trunk/coreboot-v2/src/arch/i386/lib/c_start.S 2009-05-29 13:08:27 UTC (rev 4323) > @@ -253,7 +253,7 @@ > > /* This is the gdt for GCC part of coreboot. > * It is different from the gdt in ROMCC/ASM part of coreboot > - * which is defined in entry32.inc */ > + * which is defined in entry32.inc */ /* BUT WHY?? */ > gdt: > /* selgdt 0, unused */ > .word 0x0000, 0x0000 /* dummy */ > @@ -275,6 +275,13 @@ > .word 0x0000, 0x0000 /* dummy */ > .byte 0x00, 0x00, 0x00, 0x00 > > + /* selgdt 0x28 16-bit 64k code at 0x00000000 */ > + .word 0xffff, 0x0000 > + .byte 0, 0x9a, 0, 0 > + > + /* selgdt 0x30 16-bit 64k data at 0x00000000 */ > + .word 0xffff, 0x0000 > + .byte 0, 0x92, 0, 0 > gdt_end: > > idtarg: Is this correct? Aren't some files supposed to be added and some supposed to be removed with this commit? At least i seem to remember something like that from the patch that was sent in a week or so ago, and the log message also points in this direction. Luc Verhaegen. From libv at skynet.be Tue Jun 2 15:40:34 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 15:40:34 +0200 Subject: [coreboot] flashrom touches only 0x70000-0x80000 addresses of my bios flash In-Reply-To: <200905270242.15946.lasaine@lvk.cs.msu.su> References: <200905242019.44553.lasaine@lvk.cs.msu.su> <20090526140401.2578b56d@desktopvm.lvknet> <20090526101926.GA2130@skynet.be> <200905270242.15946.lasaine@lvk.cs.msu.su> Message-ID: <20090602134034.GB24611@skynet.be> On Wed, May 27, 2009 at 02:42:15AM +0400, Alexander Gordeev wrote: > Hi Luc, > > On Tuesday 26 May 2009 14:19:26 you wrote: > > Can you provide the output of lspci -vvnxxx so that we: > > * get device/subsystem id pairs for the board enable table. > > * can spot the location of the pmio base address and make this function > > useful for both cases. > > Sure, attached it. > > -- > Alexander Device: NVIDIA CK804 LPC > 00:01.0 0601: 10de:0050 (rev a3) Dump of some extra io resource areas in pci config space of the lpc: > 60: 01 10 00 00 01 14 00 00 01 18 00 00 00 00 f9 ff This is it: ^^ ^^ ^^ ^^ Offset 0xE1 in this "System control area" is where we do our magic. The one in the trac interface uses a different offset in probably the same resource, because it is mcp55 or younger. I will write up a patch for this and send it in.. Luc Verhaegen From svn at coreboot.org Tue Jun 2 15:39:42 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 2 Jun 2009 15:39:42 +0200 Subject: [coreboot] [flashrom] r565 - trunk Message-ID: Author: uwe Date: 2009-06-02 15:39:42 +0200 (Tue, 02 Jun 2009) New Revision: 565 Modified: trunk/board_enable.c Log: Add two more boards supported by flashrom: - ASUS A8N-SLI (reported by Ryan McLean ) - MSI/Medion MS-7255 (P4M890M) (reported by J?\195?\182rg Schirottke ) Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-02 00:38:14 UTC (rev 564) +++ trunk/board_enable.c 2009-06-02 13:39:42 UTC (rev 565) @@ -704,6 +704,7 @@ { "ASI", "MB-5BLMP", }, { "ASUS", "A8N-E", }, { "ASUS", "A8NE-FM/S", }, + { "ASUS", "A8N-SLI", }, { "ASUS", "A8N-SLI Premium", }, { "ASUS", "A8V-E Deluxe", }, { "ASUS", "M2A-VM", }, @@ -733,6 +734,7 @@ { "MSI", "MS-7236 (945PL Neo3)", }, { "MSI", "MS-7345 (P35 Neo2-FIR)", }, { "MSI", "MS-7168 (Orion)", }, + { "MSI", "MS-7255 (P4M890M)", }, { "NEC", "PowerMate 2000", }, { "PC Engines", "Alix.1c", }, { "PC Engines", "Alix.2c2", }, From libv at skynet.be Tue Jun 2 16:13:52 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 16:13:52 +0200 Subject: [coreboot] [Patch] Flashrom: Add gA-k8n-sli board enable. Message-ID: <20090602141352.GA24880@skynet.be> Still needs to be tested by alexander. Luc Verhaegen. -------------- next part -------------- Board enable: Gigabyte GA K8N SLI. Raises bits 0 and 2 on offset 0xE1 in the system control area of the nvidia ck804 lpc. Signed-off-by: Luc Verhaegen Index: board_enable.c =================================================================== --- board_enable.c (revision 564) +++ board_enable.c (working copy) @@ -372,6 +372,31 @@ return 0; } +/** + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. + */ +static int board_ga_k8n_sli(const char *name) +{ + struct pci_dev *dev; + uint32_t base; + uint8_t tmp; + + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ + if (!dev) { + fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n"); + return -1; + } + + base = pci_read_long(dev, 0x64) & 0xFFFFFF00; /* System control area */ + + /* if anyone knows more about nvidia lpcs, feel free to explain this */ + tmp = inb(base + 0xE1); + tmp |= 0x05; + outb(tmp, base + 0xE1); + + return 0; +} + static int board_hp_dl145_g3_enable(const char *name) { /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ @@ -670,6 +695,7 @@ {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", board_biostar_p4m80_m4}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 16:34:14 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 16:34:14 +0200 Subject: [coreboot] [Patch] Flashrom: Add gA-k8n-sli board enable. In-Reply-To: <20090602141352.GA24880@skynet.be> References: <20090602141352.GA24880@skynet.be> Message-ID: <4A253866.2000501@gmx.net> On 02.06.2009 16:13, Luc Verhaegen wrote: > Board enable: Gigabyte GA K8N SLI. > > Raises bits 0 and 2 on offset 0xE1 in the system control area of the > nvidia ck804 lpc. > > Signed-off-by: Luc Verhaegen > With the comment below addressed, this is Acked-by: Carl-Daniel Hailfinger > Index: board_enable.c > =================================================================== > --- board_enable.c (revision 564) > +++ board_enable.c (working copy) > @@ -372,6 +372,31 @@ > + base = pci_read_long(dev, 0x64) & 0xFFFFFF00; /* System control area */ > base is an I/O port which is restricted to 16 bits on x86 compatible platforms. Suggestion: base = pci_read_long(dev, 0x64) & 0x0000FF00; Regards, Carl-Daniel -- http://www.hailfinger.org/ From stepan at coresystems.de Tue Jun 2 16:37:54 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 02 Jun 2009 16:37:54 +0200 Subject: [coreboot] [v2] r4323 - trunk/coreboot-v2/src/arch/i386/lib In-Reply-To: <20090602120525.GA24611@skynet.be> References: <20090529130853.7E5C3700038@maildelivery025.isp.belgacom.be> <20090602120525.GA24611@skynet.be> Message-ID: <4A253942.90708@coresystems.de> On 02.06.2009 14:05 Uhr, Luc Verhaegen wrote: > Is this correct? > > Aren't some files supposed to be added and some supposed to be removed > with this commit? At least i seem to remember something like that from > the patch that was sent in a week or so ago, and the log message also > points in this direction. > > Luc Verhaegen. > > check the following two commits. the added / removed stuff is svn:external'ed in from another repository. (what a pain!) -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From joe at settoplinux.org Tue Jun 2 17:13:30 2009 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 02 Jun 2009 11:13:30 -0400 Subject: [coreboot] Intel 8xx northbridge ram init is wrong Message-ID: <99aacbe9d2f9bb9cfb802ff6a8fe1fab@imap.1and1.com> Hello, Was anyone aware we are doing the do_ram_command() wrong on the i8xx nothbridges? We are sending the ram commands to all memory and doing our dummy reads at the end. I just found an Intel doc that says we are supposed to do all the ram commands to each row of memory. Quoting from doc: 1. Steps for JEDEC initilization for SDRAM devices during boot up: a. NOP command b. Pre-charge all banks (at least 200 us after NOP) c. 8 CBR refreshes (Auto Refresh) d. MRS command e. Set GMCH-M Mode Select bits back to NORMAL operation mode f. Perform a dummy memory read cycle 2. Repeat this sequence for all memory rows for all SO-DIMMs 3. Test all memory rows after JEDEC initialization sequence is done on all memory rows I will work on a patch for the i830, we should probibly fix this on the other Intle northbridges. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From wangqingpei at gmail.com Tue Jun 2 17:24:38 2009 From: wangqingpei at gmail.com (Jason Wang) Date: Tue, 2 Jun 2009 23:24:38 +0800 Subject: [coreboot] use libpayload in optionrom Message-ID: Hi all, I am trying to use libpayload in our optionrom, but does not work now... The main difference between optionrom use its own ldscript and head asm code. I main things I did now is set up the stack and heap in the pci_rom.ld. and include the "libpayload.h" and "libpayload-config.h" in the main.c. it doesn't work when i am trying to print out message which use " printf("hello optionrom")". Is there any other things i should do? All my source code was in http://vps.dorilex.net/cgi-bin/gitweb.cgi?p=optionrom.git;a=summary Need some help about this, thanks everyone... -- Jason Wang Peking University -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Tue Jun 2 17:40:55 2009 From: svn at coreboot.org (coreboot) Date: Tue, 02 Jun 2009 15:40:55 -0000 Subject: [coreboot] #95: Run coreboot in VirtualBox In-Reply-To: <039.8e5fad36b203068bd3071c0f2771ba88@coreboot.org> References: <039.8e5fad36b203068bd3071c0f2771ba88@coreboot.org> Message-ID: <048.71da7bd0087556c58a579a7c30a3e823@coreboot.org> #95: Run coreboot in VirtualBox ----------------------------+----------------------------------------------- Reporter: uwe | Owner: somebody Type: enhancement | Status: reopened Priority: minor | Milestone: Component: misc | Version: Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Changes (by uwe): * status: closed => reopened * resolution: wontfix => Comment: Reopen this issue, no progress so far doesn't mean there won't be any in the future. This is nice target for aspiring developers IMHO. -- Ticket URL: coreboot From libv at skynet.be Tue Jun 2 17:53:23 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 17:53:23 +0200 Subject: [coreboot] [v2] r4323 - trunk/coreboot-v2/src/arch/i386/lib In-Reply-To: <4A253942.90708@coresystems.de> References: <20090529130853.7E5C3700038@maildelivery025.isp.belgacom.be> <20090602120525.GA24611@skynet.be> <4A253942.90708@coresystems.de> Message-ID: <20090602155323.GA25121@skynet.be> On Tue, Jun 02, 2009 at 04:37:54PM +0200, Stefan Reinauer wrote: > On 02.06.2009 14:05 Uhr, Luc Verhaegen wrote: > > Is this correct? > > > > Aren't some files supposed to be added and some supposed to be removed > > with this commit? At least i seem to remember something like that from > > the patch that was sent in a week or so ago, and the log message also > > points in this direction. > > > > Luc Verhaegen. > > > > > > check the following two commits. the added / removed stuff is > svn:external'ed in from another repository. (what a pain!) Ah, that's why it didn't show in the git-log of this tree. Sorry for the noise, Luc Verhaegen. From libv at skynet.be Tue Jun 2 17:54:38 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 17:54:38 +0200 Subject: [coreboot] [Patch] Flashrom: Add gA-k8n-sli board enable. In-Reply-To: <4A253866.2000501@gmx.net> References: <20090602141352.GA24880@skynet.be> <4A253866.2000501@gmx.net> Message-ID: <20090602155438.GB25121@skynet.be> On Tue, Jun 02, 2009 at 04:34:14PM +0200, Carl-Daniel Hailfinger wrote: > On 02.06.2009 16:13, Luc Verhaegen wrote: > > Board enable: Gigabyte GA K8N SLI. > > > > Raises bits 0 and 2 on offset 0xE1 in the system control area of the > > nvidia ck804 lpc. > > > > Signed-off-by: Luc Verhaegen > > > > With the comment below addressed, this is > Acked-by: Carl-Daniel Hailfinger > > > > Index: board_enable.c > > =================================================================== > > --- board_enable.c (revision 564) > > +++ board_enable.c (working copy) > > @@ -372,6 +372,31 @@ > > + base = pci_read_long(dev, 0x64) & 0xFFFFFF00; /* System control area */ > > > > base is an I/O port which is restricted to 16 bits on x86 compatible > platforms. Suggestion: > > base = pci_read_long(dev, 0x64) & 0x0000FF00; > > > Regards, > Carl-Daniel Ok! Still waiting for alexander though, Luc Verhaegen. From ward at gnu.org Tue Jun 2 17:57:29 2009 From: ward at gnu.org (Ward Vandewege) Date: Tue, 2 Jun 2009 11:57:29 -0400 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> References: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> Message-ID: <20090602155729.GA22254@localdomain> Hey Marc et al, I just received a h8dmr box with quad core CPUs (2372HE) and 32GB of ram. I hacked up an h8dmr-fam10 patch which boots but still has tons of issues. Boot log here: http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-c.cap First problem is that it complains about not finding the microcode rev id. So I found the message below - did you ever get around to doing this? I also modified coreboot a little to print out the CPU version id (0x10042), which is not yet listed in amd/amdfam10/raminit_amdmct.c. A little further down in the log it seems I've got multiple cores talking at once so that's something else I'll need to figure out. It does actually get all the way to CBFS, but hangs after loadking the first stage. There is also some slowness during/after ram detection. Any hints on where I should look to fix those things would be welcome :) Thanks, Ward. On Wed, Mar 25, 2009 at 09:49:42AM -0600, Marc Jones wrote: > 2009/3/24 Bao, Zheng : > > Attached are the latest ucode patches for Family 10h: > > > > 9fh for RB/BL/DA Rev C; > > 96h for DR Rev B. > > > > Signed-off-by: > > > Acked-by: Marc Jones > r4028 > > I will work up a patch for the fam10 mainboards to use these new > microcode files. > > Marc > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > > !DSPAM:49ca52c0315921804284693! > -- Ward Vandewege From stepan at coresystems.de Tue Jun 2 18:00:53 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 02 Jun 2009 18:00:53 +0200 Subject: [coreboot] Intel 8xx northbridge ram init is wrong In-Reply-To: <99aacbe9d2f9bb9cfb802ff6a8fe1fab@imap.1and1.com> References: <99aacbe9d2f9bb9cfb802ff6a8fe1fab@imap.1and1.com> Message-ID: <4A254CB5.10805@coresystems.de> On 02.06.2009 17:13 Uhr, Joseph Smith wrote: > Hello, > Was anyone aware we are doing the do_ram_command() wrong on the i8xx > nothbridges? > We are sending the ram commands to all memory and doing our dummy reads at > the end. > I just found an Intel doc that says we are supposed to do all the ram > commands to each row of memory. > ... > I will work on a patch for the i830, we should probibly fix this on the > other Intle northbridges. > Check the i945 code for an example on how to do it... older chipsets might/might not be different... -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From stepan at coresystems.de Tue Jun 2 18:04:45 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 02 Jun 2009 18:04:45 +0200 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <20090602155729.GA22254@localdomain> References: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> <20090602155729.GA22254@localdomain> Message-ID: <4A254D9D.5000809@coresystems.de> On 02.06.2009 17:57 Uhr, Ward Vandewege wrote: > Hey Marc et al, > > I just received a h8dmr box with quad core CPUs (2372HE) and 32GB of ram. I > hacked up an h8dmr-fam10 patch which boots but still has tons of issues. Boot > log here: > > http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-c.cap > > First problem is that it complains about not finding the microcode rev id. So > I found the message below - did you ever get around to doing this? > To play the advocatus diaboli, for Intel CPUs you can download the latest microcode from their web page. Unfortunately, for AMD you need an NDA signed to get them. Best regards, Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From joe at settoplinux.org Tue Jun 2 18:06:44 2009 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 02 Jun 2009 12:06:44 -0400 Subject: [coreboot] Intel 8xx northbridge ram init is wrong In-Reply-To: <4A254CB5.10805@coresystems.de> References: <99aacbe9d2f9bb9cfb802ff6a8fe1fab@imap.1and1.com> <4A254CB5.10805@coresystems.de> Message-ID: <91142643581500eaca3028b62700885b@imap.1and1.com> On Tue, 02 Jun 2009 18:00:53 +0200, Stefan Reinauer wrote: > On 02.06.2009 17:13 Uhr, Joseph Smith wrote: >> Hello, >> Was anyone aware we are doing the do_ram_command() wrong on the i8xx >> nothbridges? >> We are sending the ram commands to all memory and doing our dummy reads > at >> the end. >> I just found an Intel doc that says we are supposed to do all the ram >> commands to each row of memory. >> > ... >> I will work on a patch for the i830, we should probibly fix this on the >> other Intle northbridges. >> > > > Check the i945 code for an example on how to do it... older chipsets > might/might not be different... > Would it be different for SDRAM vs DDR ? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From stepan at coresystems.de Tue Jun 2 18:11:42 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 02 Jun 2009 18:11:42 +0200 Subject: [coreboot] Intel 8xx northbridge ram init is wrong In-Reply-To: <91142643581500eaca3028b62700885b@imap.1and1.com> References: <99aacbe9d2f9bb9cfb802ff6a8fe1fab@imap.1and1.com> <4A254CB5.10805@coresystems.de> <91142643581500eaca3028b62700885b@imap.1and1.com> Message-ID: <4A254F3E.6090308@coresystems.de> > > > On Tue, 02 Jun 2009 18:00:53 +0200, Stefan Reinauer > wrote: > >> On 02.06.2009 17:13 Uhr, Joseph Smith wrote: >> >>> Hello, >>> Was anyone aware we are doing the do_ram_command() wrong on the i8xx >>> nothbridges? >>> We are sending the ram commands to all memory and doing our dummy reads >>> >> at >> >>> the end. >>> I just found an Intel doc that says we are supposed to do all the ram >>> commands to each row of memory. >>> >>> >> ... >> >>> I will work on a patch for the i830, we should probibly fix this on the >>> other Intle northbridges. >>> >>> >> Check the i945 code for an example on how to do it... older chipsets >> might/might not be different... >> >> > Would it be different for SDRAM vs DDR ? > > You need a couple more steps (different MRS commands etc) for DDR, but the loop itself is basically the same. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From libv at skynet.be Tue Jun 2 18:33:08 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 18:33:08 +0200 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <4A201F2E.1030805@coresystems.de> References: <20090529134428.GA13500@skynet.be> <20090529134809.22493.qmail@stuge.se> <20090529141407.GB13500@skynet.be> <4A201F2E.1030805@coresystems.de> Message-ID: <20090602163308.GA25218@skynet.be> On Fri, May 29, 2009 at 07:45:18PM +0200, Stefan Reinauer wrote: > On 29.05.2009 16:14 Uhr, Luc Verhaegen wrote: > > > Currently, our security of the cmos value being correct with respect to > > the options table, is the existence of the option name string in the > > optionstable, and the validity of the checksum. We need more than this, > > we need a better way of matching cmos data with the options table. > > > > Why? Example: Run native bios on epia-m. It stops booting, loads the defaults and tells you to go into the config. Alter the config, boot again, and it is happy. Then plug in a coreboot image. It flags that the checksum is invalid, and therefor most of the users of cmos data use a default, yet it continues booting. Alter a single value with nvramtool, and suddenly the cmos checksum is correct. No matter what the other values are. Sometimes you're lucky, but in the epia-m case, you lose serial output (as it suddenly is the lowest value, a value which screen wasn't used to) and seabios tries to boot off the network. All one can do is clear the cmos and then boot properly... What can be done to fix this: 1) track board and version information. 2) add some way to define the default settings in the cmos.layout. Then there are several situations possible. * when a legacy bios was run and the rtc is full of garbage (for us), or when a different board is used, or when the major is different. This should be treated the same way as an invalid checksum. Booting refuses to use it and feeds back defaults (which can also be overridden by code depending on the return value of get_option). Nvramtool can catch this nicely and can offer to fill in defaults, or at least refuse to correct the checksum. * when booting, and when a minor difference between cmos and option table is detected, treat the retrieved information as in the previous point. * when a minor difference between rom option table and cmos.layout is detected, then nvramtool can offer to program the default value of the difference, because it can find out the difference. * when the cmos.layout is for a different board, or of a lower version, then nvramtool should basically refuse to accept it. Also when nvramtool detects invalid values, it can offer to program defaults or at least refuse to validate the checksum. nvramtool should be able to write anything though, through the use of some argument like --force. It should also be able to just set up everything by default. Before any of this is done, the table generation code should get fixed to output more sensible things (why do we dump this to a list of chars in a table?) with things like defines or enums for the values. And we should be able to do checking at boottime as well. I know that this all nontrivial to implement, and that therefor it'll take some time for someone to implement it. But i believe it makes sense, and it will definitely avoid a board booting up with invalid settings, and at least go for defaults. Luc Verhaegen. From maciej.pijanka at gmail.com Tue Jun 2 18:27:13 2009 From: maciej.pijanka at gmail.com (Maciej Pijanka) Date: Tue, 2 Jun 2009 18:27:13 +0200 Subject: [coreboot] Flashrom patch Message-ID: Hello I tried vortex-diag on some 3com card and reading/writing flash was working, so i tried to add it to nic3com.c (patch attached) Also, i added AT29C512 Atmel flash chip to flashchips.c to get it autodetected (patch also attached). Final flashrom -p nic3com -V log is in patched-detection.log best regards Maciej Pijanka -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user -------------- next part -------------- A non-text attachment was scrubbed... Name: new-3com.patch Type: application/octet-stream Size: 1467 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: new-flashchip.patch Type: application/octet-stream Size: 1060 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: patched-detection.log Type: application/octet-stream Size: 16391 bytes Desc: not available URL: From svn at coreboot.org Tue Jun 2 18:34:30 2009 From: svn at coreboot.org (coreboot) Date: Tue, 02 Jun 2009 16:34:30 -0000 Subject: [coreboot] #139: flashrom: -c option should be case insensitive Message-ID: <039.b3816d99d5e189ee98476c22a68da93a@coreboot.org> #139: flashrom: -c option should be case insensitive ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ flashrom's -c option requires you to enter extact chip names. It should probably be case insensitive for easier usage. -- Ticket URL: coreboot From svn at coreboot.org Tue Jun 2 18:36:02 2009 From: svn at coreboot.org (coreboot) Date: Tue, 02 Jun 2009 16:36:02 -0000 Subject: [coreboot] #127: Add support for hp dl145g3 to coreboot v2 In-Reply-To: <063.75cfee69a8c0b08bc37bf05ba15aa071@coreboot.org> References: <063.75cfee69a8c0b08bc37bf05ba15aa071@coreboot.org> Message-ID: <072.423896811386d38f5822ac2d3d80cc58@coreboot.org> #127: Add support for hp dl145g3 to coreboot v2 --------------------------------------------+------------------------------- Reporter: samuel.verstraete@? | Owner: somebody Type: enhancement | Status: closed Priority: major | Milestone: Component: coreboot | Version: v2 Resolution: fixed | Keywords: Dependencies: | Patchstatus: patch has been committed --------------------------------------------+------------------------------- Changes (by uwe): * status: new => closed * patchstatus: patch needs review => patch has been committed * resolution: => fixed Comment: I think most (all?) of these patches have been committed. Please reopen if some stuff is still missing. -- Ticket URL: coreboot From libv at skynet.be Tue Jun 2 18:45:28 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 18:45:28 +0200 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <20090530155900.GA11598@morn.localdomain> References: <20090529134428.GA13500@skynet.be> <20090530155900.GA11598@morn.localdomain> Message-ID: <20090602164528.GB25218@skynet.be> On Sat, May 30, 2009 at 11:59:00AM -0400, Kevin O'Connor wrote: > On Fri, May 29, 2009 at 03:44:28PM +0200, Luc Verhaegen wrote: > > To ease some of my debugging pain on the unichrome, i decided i needed to > > move FB size selection into cmos, so i could test a size and then reset it > > to the default after loading this value so that the next reboot uses the > > (working) default again. This meant implementing set_option in parallel to > > get_option. > > As an aside, I think long-term coreboot should have a config file in > flash and use that instead of nvram. > > The issues with using nvram: > > * it's small and it leads to weird hacks to store data You have, iirc, 228 bytes to your disposal. Even if we would put all current cmos.layouts on byte boundaries, no-one would run out of space anyway. How would you want to store information, and how would you want to handle parsing of this information? Do you really want to store configuration in xml and include an xml parser in a bios? Do you want to invent your own structured information storage system? If so, what is wrong with what we do now, especially, since we do not have to reprogram part of our flash every 5 seconds? 228 bytes is plenty if you are not storing whole strings. > * the coreboot layout conflicts with the vendor layout and it's a > pain when switching between coreboot and factory bios This is what the board-id-ing and versioning in both cmos and optiom table will solve. > * the batteries frequently get old and nvram storage becomes flaky In such a case, too bad, get a new battery and program defaults. CMOS is the best part of 256bytes that's available for everyone to use. It's there, it's free, we know how to access it, we know how to make very efficient use of it. We can write to it almost infinitely and very quickly. Sure, you cannot stuff many kBs in there, but how would you use such space anyway? Why not make maximal use of infrastructure/hardware that is freely available? Luc Verhaegen. From marcj303 at gmail.com Tue Jun 2 18:39:56 2009 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 2 Jun 2009 10:39:56 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <20090602155729.GA22254@localdomain> References: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> <20090602155729.GA22254@localdomain> Message-ID: <534e5dc20906020939g80a70d6r37dc8084de676ab5@mail.gmail.com> On Tue, Jun 2, 2009 at 9:57 AM, Ward Vandewege wrote: > Hey Marc et al, > > I just received a h8dmr box with quad core CPUs (2372HE) and 32GB of ram. I > hacked up an h8dmr-fam10 patch which boots but still has tons of issues. Boot > log here: > > ?http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-c.cap > > First problem is that it complains about not finding the microcode rev id. So > I found the message below - did you ever get around to doing this? > > I also modified coreboot a little to print out the CPU version id (0x10042), > which is not yet listed in amd/amdfam10/raminit_amdmct.c. > We added for one of the C2 parts. It should be easy enough to add the other one. You will also need to change Options.lb for the C2 microcode. Shanghai rev DA-C2: "mc_patch_0100009f.h" > A little further down in the log it seems I've got multiple cores talking at > once so that's something else I'll need to figure out. > Yes, that stuff should be fine. > It does actually get all the way to CBFS, but hangs after loadking the first > stage. There is also some slowness during/after ram detection. There is slowness around the cache disable / mem copy.. I think that someone posted a fix to the list at one point. It would require some searching. > > Any hints on where I should look to fix those things would be welcome :) > > Thanks, > Ward. > > On Wed, Mar 25, 2009 at 09:49:42AM -0600, Marc Jones wrote: >> 2009/3/24 Bao, Zheng : >> > Attached are the latest ucode patches for Family 10h: >> > >> > 9fh for RB/BL/DA Rev C; >> > 96h for DR Rev B. >> > >> > Signed-off-by: >> > >> Acked-by: Marc Jones >> r4028 >> >> I will work up a patch for the fam10 mainboards to use these new >> microcode files. >> >> Marc >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> >> >> !DSPAM:49ca52c0315921804284693! >> > -- > Ward Vandewege > -- http://marcjonesconsulting.com From libv at skynet.be Tue Jun 2 18:49:10 2009 From: libv at skynet.be (Luc Verhaegen) Date: Tue, 2 Jun 2009 18:49:10 +0200 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <20090602164528.GB25218@skynet.be> References: <20090529134428.GA13500@skynet.be> <20090530155900.GA11598@morn.localdomain> <20090602164528.GB25218@skynet.be> Message-ID: <20090602164910.GC25218@skynet.be> On Tue, Jun 02, 2009 at 06:45:28PM +0200, Luc Verhaegen wrote: > On Sat, May 30, 2009 at 11:59:00AM -0400, Kevin O'Connor wrote: > > On Fri, May 29, 2009 at 03:44:28PM +0200, Luc Verhaegen wrote: > > > To ease some of my debugging pain on the unichrome, i decided i needed to > > > move FB size selection into cmos, so i could test a size and then reset it > > > to the default after loading this value so that the next reboot uses the > > > (working) default again. This meant implementing set_option in parallel to > > > get_option. > > > > As an aside, I think long-term coreboot should have a config file in > > flash and use that instead of nvram. > > > > The issues with using nvram: > > > > * it's small and it leads to weird hacks to store data > > You have, iirc, 228 bytes to your disposal. > > Even if we would put all current cmos.layouts on byte boundaries, no-one > would run out of space anyway. > > How would you want to store information, and how would you want to > handle parsing of this information? Do you really want to store > configuration in xml and include an xml parser in a bios? Do you want to > invent your own structured information storage system? If so, what is > wrong with what we do now, especially, since we do not have to reprogram > part of our flash every 5 seconds? > > 228 bytes is plenty if you are not storing whole strings. > > > * the coreboot layout conflicts with the vendor layout and it's a > > pain when switching between coreboot and factory bios > > This is what the board-id-ing and versioning in both cmos and optiom > table will solve. > > > * the batteries frequently get old and nvram storage becomes flaky > > In such a case, too bad, get a new battery and program defaults. > > CMOS is the best part of 256bytes that's available for everyone to use. > It's there, it's free, we know how to access it, we know how to make > very efficient use of it. We can write to it almost infinitely and very > quickly. Sure, you cannot stuff many kBs in there, but how would you use > such space anyway? > > Why not make maximal use of infrastructure/hardware that is freely > available? > > Luc Verhaegen. I cannot help but feel that this is just trying to be different for the sake of trying to be different. Luc Verhaegen. From svn at coreboot.org Tue Jun 2 18:45:59 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 2 Jun 2009 18:45:59 +0200 Subject: [coreboot] [flashrom] r566 - trunk Message-ID: Author: uwe Date: 2009-06-02 18:45:59 +0200 (Tue, 02 Jun 2009) New Revision: 566 Modified: trunk/flash.h trunk/flashchips.c trunk/nic3com.c Log: Add support for the 10b7:9058 3COM NIC (3C905B: Cyclone 10/100/BNC). Also, add Atmel AT29C512 support. Both are tested on hardware by Maciej Pijanka. Signed-off-by: Maciej Pijanka Acked-by: Uwe Hermann Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-02 13:39:42 UTC (rev 565) +++ trunk/flash.h 2009-06-02 16:45:59 UTC (rev 566) @@ -287,6 +287,7 @@ #define AT_29C040A 0xA4 #define AT_29C010A 0xD5 #define AT_29C020 0xDA +#define AT_29C512 0x5D #define AT_45BR3214B /* No ID available */ #define AT_45CS1282 0x2920 #define AT_45D011 /* No ID available */ Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-02 13:39:42 UTC (rev 565) +++ trunk/flashchips.c 2009-06-02 16:45:59 UTC (rev 566) @@ -400,6 +400,22 @@ { .vendor = "Atmel", + .name = "AT29C512", + .bustype = CHIP_BUSTYPE_NONSPI, + .manufacture_id = ATMEL_ID, + .model_id = AT_29C512, + .total_size = 64, + .page_size = 128, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .erase = erase_chip_jedec, + .write = write_jedec, + .read = read_memmapped, + + }, + + { + .vendor = "Atmel", .name = "AT29C010A", .bustype = CHIP_BUSTYPE_NONSPI, .manufacture_id = ATMEL_ID, Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-06-02 13:39:42 UTC (rev 565) +++ trunk/nic3com.c 2009-06-02 16:45:59 UTC (rev 566) @@ -46,6 +46,7 @@ {0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, {0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" }, {0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" }, + {0x10b7, 0x9058, PCI_NT, "3COM", "3C905B: Cyclone 10/100/BNC" }, /* 3C905C */ {0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, @@ -65,7 +66,7 @@ /* 3COM 3C90xB cards need a special fixup. */ if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 - || id == 0x9006 || id == 0x900a || id == 0x905a) { + || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { /* Select register window 3 and save the receiver status. */ OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS); internal_conf = INL(io_base_addr + INTERNAL_CONFIG); @@ -90,7 +91,7 @@ { /* 3COM 3C90xB cards need a special fixup. */ if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 - || id == 0x9006 || id == 0x900a || id == 0x905a) { + || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { /* Select register window 3 and restore the receiver status. */ OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS); OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG); From uwe at hermann-uwe.de Tue Jun 2 18:47:27 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Tue, 2 Jun 2009 18:47:27 +0200 Subject: [coreboot] Flashrom patch In-Reply-To: References: Message-ID: <20090602164727.GC18065@greenwood> Hi, On Tue, Jun 02, 2009 at 06:27:13PM +0200, Maciej Pijanka wrote: > I tried vortex-diag on some 3com card and reading/writing flash was > working, so i tried to add it to nic3com.c (patch attached) > > Also, i added AT29C512 Atmel flash chip to flashchips.c to get it > autodetected (patch also attached). > > Final flashrom -p nic3com -V log is in patched-detection.log Great, thanks for testing and for the patch! Committed in r566. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From stepan at coresystems.de Tue Jun 2 18:55:29 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 02 Jun 2009 18:55:29 +0200 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <20090602163308.GA25218@skynet.be> References: <20090529134428.GA13500@skynet.be> <20090529134809.22493.qmail@stuge.se> <20090529141407.GB13500@skynet.be> <4A201F2E.1030805@coresystems.de> <20090602163308.GA25218@skynet.be> Message-ID: <4A255981.6070007@coresystems.de> Luc wrote: > Also when nvramtool detects invalid values, it can offer to program > defaults or at least refuse to validate the checksum. nvramtool should > be able to write anything though, through the use of some argument like > --force. It should also be able to just set up everything by default. > I think this is the fix we want. Forget the other stuff. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From ward at gnu.org Tue Jun 2 19:35:33 2009 From: ward at gnu.org (Ward Vandewege) Date: Tue, 2 Jun 2009 13:35:33 -0400 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20906020939g80a70d6r37dc8084de676ab5@mail.gmail.com> References: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> <20090602155729.GA22254@localdomain> <534e5dc20906020939g80a70d6r37dc8084de676ab5@mail.gmail.com> Message-ID: <20090602173533.GA25977@localdomain> On Tue, Jun 02, 2009 at 10:39:56AM -0600, Marc Jones wrote: > We added for one of the C2 parts. It should be easy enough to add the other one. > You will also need to change Options.lb for the C2 microcode. > Shanghai rev DA-C2: "mc_patch_0100009f.h" Great, I made those changes, and the microcode update happens now. It also stopped complaining about the CPU version. Booting does not get very far anymore though, so I must be doing something wrong: ------------------------------------------------------------------------------ coreboot-2.0.0-r4329M_h8dmr_Fallback Tue Jun 2 13:24:42 EDT 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1062, current patch id = 0x00000000 microcode: patch id to apply = 0x0100009f microcode: updated to patch id = 0x0100009f success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 00 Exit amd_ht_init() cpuSetAMDPCI 00 done cpuSetAMDPCI 01 ------------------------------------------------------------------------------ It hangs right there. This started happening when I added case 0x10042: ret = AMD_RB_C2; break; to the switch statement in mctGetLogicalCPUID (northbridge/amd/amdfam10/raminit_amdmct.c), telling coreboot about this CPU version. If I remove that part again, the system reboots endlessly (this is with the microcode update now working, and the change in Options.lb that you suggested): http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-j.cap Thoughts? Thanks, Ward. -- Ward Vandewege From peter at stuge.se Tue Jun 2 19:47:06 2009 From: peter at stuge.se (Peter Stuge) Date: Tue, 2 Jun 2009 19:47:06 +0200 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <4A255981.6070007@coresystems.de> References: <20090529134428.GA13500@skynet.be> <20090529134809.22493.qmail@stuge.se> <20090529141407.GB13500@skynet.be> <4A201F2E.1030805@coresystems.de> <20090602163308.GA25218@skynet.be> <4A255981.6070007@coresystems.de> Message-ID: <20090602174706.7998.qmail@stuge.se> Stefan Reinauer wrote: > > Also when nvramtool detects invalid values, it can offer to program > > defaults or at least refuse to validate the checksum. nvramtool should > > be able to write anything though, through the use of some argument like > > --force. It should also be able to just set up everything by default. > > I think this is the fix we want. Forget the other stuff. I agree it is part of what we want, but I think it is also pretty important for coreboot to gracefully ignore what appears to be a cluttered NVRAM, without making any changes to it. //Peter From lasaine at lvk.cs.msu.su Tue Jun 2 20:43:56 2009 From: lasaine at lvk.cs.msu.su (Alexander Gordeev) Date: Tue, 2 Jun 2009 22:43:56 +0400 Subject: [coreboot] [Patch] Flashrom: Add gA-k8n-sli board enable. In-Reply-To: <20090602141352.GA24880@skynet.be> References: <20090602141352.GA24880@skynet.be> Message-ID: <200906022243.56600.lasaine@lvk.cs.msu.su> On Tuesday 02 June 2009 18:13:52 Luc Verhaegen wrote: > Still needs to be tested by alexander. > > Luc Verhaegen. WOW, it is working now! Thanks a lot! alex at tornado:~/bios$ sudo ../development/flashrom/trunk/flashrom flashrom v0.9.0-r566 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. Found board "GIGABYTE GA-K8N-SLI", enabling flash write... OK. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. No operations were specified. I also tested read, write, erase and verify operations and rebooted the machine with the new bios. Everything is ok! -- Alexander From stepan at coresystems.de Tue Jun 2 20:51:36 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 02 Jun 2009 20:51:36 +0200 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <20090602174706.7998.qmail@stuge.se> References: <20090529134428.GA13500@skynet.be> <20090529134809.22493.qmail@stuge.se> <20090529141407.GB13500@skynet.be> <4A201F2E.1030805@coresystems.de> <20090602163308.GA25218@skynet.be> <4A255981.6070007@coresystems.de> <20090602174706.7998.qmail@stuge.se> Message-ID: <4A2574B8.2070109@coresystems.de> > > Stefan Reinauer wrote: > >>> Also when nvramtool detects invalid values, it can offer to program >>> defaults or at least refuse to validate the checksum. nvramtool should >>> be able to write anything though, through the use of some argument like >>> --force. It should also be able to just set up everything by default. >>> >> I think this is the fix we want. Forget the other stuff. >> > > I agree it is part of what we want, but I think it is also pretty > important for coreboot to gracefully ignore what appears to be a > cluttered NVRAM, without making any changes to it. > > That's a one liner not to clear cmos in case the checksum is wrong. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From lasaine at lvk.cs.msu.su Tue Jun 2 20:54:36 2009 From: lasaine at lvk.cs.msu.su (Alexander Gordeev) Date: Tue, 2 Jun 2009 22:54:36 +0400 Subject: [coreboot] [Patch] Flashrom: Add gA-k8n-sli board enable. In-Reply-To: <200906022243.56600.lasaine@lvk.cs.msu.su> References: <20090602141352.GA24880@skynet.be> <200906022243.56600.lasaine@lvk.cs.msu.su> Message-ID: <200906022254.36484.lasaine@lvk.cs.msu.su> On Tuesday 02 June 2009 22:43:56 Alexander Gordeev wrote: > On Tuesday 02 June 2009 18:13:52 Luc Verhaegen wrote: > > Still needs to be tested by alexander. > > > > Luc Verhaegen. > > WOW, it is working now! Thanks a lot! > > alex at tornado:~/bios$ sudo ../development/flashrom/trunk/flashrom > flashrom v0.9.0-r566 > No coreboot table found. > Found chipset "NVIDIA CK804", enabling flash write... OK. > Found board "GIGABYTE GA-K8N-SLI", enabling flash write... OK. > Calibrating delay loop... OK. > Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. > No operations were specified. > > I also tested read, write, erase and verify operations and rebooted the > machine with the new bios. Everything is ok! P.S. The flash chip is currently soldered directly on the board but I'm going to replace it with a socket so feel free to contact me if you need a tester. -- Alexander From lasaine at lvk.cs.msu.su Tue Jun 2 21:02:12 2009 From: lasaine at lvk.cs.msu.su (Alexander Gordeev) Date: Tue, 2 Jun 2009 23:02:12 +0400 Subject: [coreboot] [Patch] Flashrom: Add gA-k8n-sli board enable. In-Reply-To: <200906022254.36484.lasaine@lvk.cs.msu.su> References: <20090602141352.GA24880@skynet.be> <200906022243.56600.lasaine@lvk.cs.msu.su> <200906022254.36484.lasaine@lvk.cs.msu.su> Message-ID: <200906022302.12294.lasaine@lvk.cs.msu.su> On Tuesday 02 June 2009 22:54:36 Alexander Gordeev wrote: > On Tuesday 02 June 2009 22:43:56 Alexander Gordeev wrote: > > On Tuesday 02 June 2009 18:13:52 Luc Verhaegen wrote: > > > Still needs to be tested by alexander. > > > > > > Luc Verhaegen. > > > > WOW, it is working now! Thanks a lot! > > > > alex at tornado:~/bios$ sudo ../development/flashrom/trunk/flashrom > > flashrom v0.9.0-r566 > > No coreboot table found. > > Found chipset "NVIDIA CK804", enabling flash write... OK. > > Found board "GIGABYTE GA-K8N-SLI", enabling flash write... OK. > > Calibrating delay loop... OK. > > Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. > > No operations were specified. > > > > I also tested read, write, erase and verify operations and rebooted the > > machine with the new bios. Everything is ok! > > P.S. The flash chip is currently soldered directly on the board but I'm > going to replace it with a socket so feel free to contact me if you need a > tester. P.P.S. Acked-by: Alexander Gordeev -- Alexander From svn at coreboot.org Tue Jun 2 21:54:22 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 2 Jun 2009 21:54:22 +0200 Subject: [coreboot] [flashrom] r567 - trunk Message-ID: Author: uwe Date: 2009-06-02 21:54:22 +0200 (Tue, 02 Jun 2009) New Revision: 567 Modified: trunk/chipset_enable.c trunk/dummyflasher.c trunk/flash.h trunk/flashrom.8 trunk/nic3com.c Log: Mark the 10b7:9058 3COM card (3C905B: Cyclone 10/100/BNC) as "OK", forgot this in the last commit. Also do some random cleanups while I'm at it. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-06-02 16:45:59 UTC (rev 566) +++ trunk/chipset_enable.c 2009-06-02 19:54:22 UTC (rev 567) @@ -781,15 +781,15 @@ static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) { - uint8_t tmp; + uint8_t tmp; - pci_write_byte(dev, 0x92, 0); + pci_write_byte(dev, 0x92, 0); - tmp = pci_read_byte(dev, 0x6d); - tmp |= 0x01; - pci_write_byte(dev, 0x6d, tmp); + tmp = pci_read_byte(dev, 0x6d); + tmp |= 0x01; + pci_write_byte(dev, 0x6d, tmp); - return 0; + return 0; } static int enable_flash_ck804(struct pci_dev *dev, const char *name) Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-06-02 16:45:59 UTC (rev 566) +++ trunk/dummyflasher.c 2009-06-02 19:54:22 UTC (rev 567) @@ -66,7 +66,7 @@ if (buses_supported == CHIP_BUSTYPE_NONE) printf_debug("Support for all flash bus types disabled.\n"); free(dummytype); - return 0; + return 0; } int dummy_shutdown(void) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-02 16:45:59 UTC (rev 566) +++ trunk/flash.h 2009-06-02 19:54:22 UTC (rev 567) @@ -346,8 +346,8 @@ #define EN_29F040A 0x7F04 #define EN_29LV010 0x7F6E #define EN_29LV040A 0x7F4F /* EN_29LV040(A) */ -#define EN_29F002T 0x7F92 -#define EN_29F002B 0x7F97 +#define EN_29F002T 0x7F92 /* Also EN29F002A */ +#define EN_29F002B 0x7F97 /* Also EN29F002AN */ #define FUJITSU_ID 0x04 /* Fujitsu */ #define MBM29F400BC 0xAB Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-06-02 16:45:59 UTC (rev 566) +++ trunk/flashrom.8 2009-06-02 19:54:22 UTC (rev 567) @@ -133,7 +133,7 @@ .sp .BR "* satasii" " (for flash ROMs on Silicon Image SATA/IDE controllers)" .sp -.BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" +.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI translation unit)" .sp The dummy programmer has an optional parameter specifying the bus types it should support. For that you have to use the Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-06-02 16:45:59 UTC (rev 566) +++ trunk/nic3com.c 2009-06-02 19:54:22 UTC (rev 567) @@ -46,7 +46,7 @@ {0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, {0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" }, {0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" }, - {0x10b7, 0x9058, PCI_NT, "3COM", "3C905B: Cyclone 10/100/BNC" }, + {0x10b7, 0x9058, PCI_OK, "3COM", "3C905B: Cyclone 10/100/BNC" }, /* 3C905C */ {0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, From maciej.pijanka at gmail.com Tue Jun 2 21:57:28 2009 From: maciej.pijanka at gmail.com (Maciej Pijanka) Date: Tue, 2 Jun 2009 21:57:28 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs Message-ID: Hello Carl-Daniel pointed me to easy tasks list in wiki, i tried to prepare some patch that allow to add probe_timing information (int uS value) used by jedec_probe (patch attached) best regards Maciej Pijanka -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user -------------- next part -------------- A non-text attachment was scrubbed... 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Name: jedec_probe_timing.patch Type: application/octet-stream Size: 11587 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Tue Jun 2 22:18:51 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 02 Jun 2009 22:18:51 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: References: Message-ID: <4A25892B.9010506@gmx.net> On 02.06.2009 21:57, Maciej Pijanka wrote: > Hello > > Carl-Daniel pointed me to easy tasks list in wiki, i tried to prepare some > patch that allow to add probe_timing information (int uS value) used > by jedec_probe (patch attached) > Thanks for the patch. Review follows: - probe_49fl00x is a wrapper for probe_jedec. Those chips need the probe_timing parameter as well. - probe_sst_fwhub has the same problem. - If someone forgets the probe_timing parameter, it will be zero. That's bad for almost all chips. Maybe add an explicit check for nonzero delays? - It might be best if every chip definition got that probe_timing parameter. Other probe functions could use similar delay info. - SPI chips want zero delay. Regards, Carl-Daniel -- http://www.hailfinger.org/ From marcj303 at gmail.com Tue Jun 2 22:27:58 2009 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 2 Jun 2009 14:27:58 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <20090602173533.GA25977@localdomain> References: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> <20090602155729.GA22254@localdomain> <534e5dc20906020939g80a70d6r37dc8084de676ab5@mail.gmail.com> <20090602173533.GA25977@localdomain> Message-ID: <534e5dc20906021327p24d9e41cx810c09f238edc4bc@mail.gmail.com> On Tue, Jun 2, 2009 at 11:35 AM, Ward Vandewege wrote: > On Tue, Jun 02, 2009 at 10:39:56AM -0600, Marc Jones wrote: >> We added for one of the C2 parts. It should be easy enough to add the other one. >> You will also need to change Options.lb for the C2 microcode. >> Shanghai rev DA-C2: "mc_patch_0100009f.h" > > Great, I made those changes, and the microcode update happens now. It also > stopped complaining about the CPU version. Booting does not get very far > anymore though, so I must be doing something wrong: > > ------------------------------------------------------------------------------ > coreboot-2.0.0-r4329M_h8dmr_Fallback Tue Jun ?2 13:24:42 EDT 2009 starting... > > BSP Family_Model: 00100f42 > *sysinfo range: [000cc000,000cdfa0] > bsp_apicid = 00 > cpu_init_detectedx = 00000000 > microcode: equivalent rev id ?= 0x1062, current patch id = 0x00000000 > microcode: patch id to apply = 0x0100009f > microcode: updated to patch id = 0x0100009f ?success > > cpuSetAMDMSR ?done > Enter amd_ht_init() > AMD_CB_EventNotify() > ?event class: 05 > ?event: 1004 > ?data: ?04 ?00 ?00 ?01 > AMD_CB_EventNotify() > ?event class: 05 > ?event: 2006 > ?data: ?04 ?00 ?02 ?00 > Exit amd_ht_init() > cpuSetAMDPCI 00 done > cpuSetAMDPCI 01 > ------------------------------------------------------------------------------ > > It hangs right there. This started happening when I added > > ?case 0x10042: > ? ?ret = AMD_RB_C2; > ? ?break; > > to the switch statement in mctGetLogicalCPUID > (northbridge/amd/amdfam10/raminit_amdmct.c), telling coreboot about this CPU > version. > > If I remove that part again, the system reboots endlessly (this is with the > microcode update now working, and the change in Options.lb that you > suggested): > > ?http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-j.cap > > Thoughts? You are the first to try this on a real system. Nothing is jumping out at me in the code. If you can put in some debug checks around there it will be helpful to figure out. Marc -- http://marcjonesconsulting.com From ward at gnu.org Tue Jun 2 23:02:37 2009 From: ward at gnu.org (Ward Vandewege) Date: Tue, 2 Jun 2009 17:02:37 -0400 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20906021327p24d9e41cx810c09f238edc4bc@mail.gmail.com> References: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> <20090602155729.GA22254@localdomain> <534e5dc20906020939g80a70d6r37dc8084de676ab5@mail.gmail.com> <20090602173533.GA25977@localdomain> <534e5dc20906021327p24d9e41cx810c09f238edc4bc@mail.gmail.com> Message-ID: <20090602210237.GA24394@localdomain> On Tue, Jun 02, 2009 at 02:27:58PM -0600, Marc Jones wrote: > You are the first to try this on a real system. Nothing is jumping out > at me in the code. If you can put in some debug checks around there it > will be helpful to figure out. Sure. I've sprinkled some debug code and traced the hang to this bit of code in cpu/amd/model_10xxx/init_cpus.c, void AMD_SetHtPhyRegister: /* Now get the current phy register data * LinkPhyDone = 0, LinkPhyWrite = 0 is a read */ phyReg |= fam10_htphy_default[entry].htreg; pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); do { val = pci_read_config32(NODE_PCI(node, 4), phyBase); } while (!(val & HTPHY_IS_COMPLETE_MASK)); That's an infinite loop on the second CPU, apparently. I've uploaded the boot log with debug output, as well as my modified init_cpus.c file with all the debug printing: http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-n.cap http://ward.vandewege.net/coreboot/h8dmr/fam10/init_cpus-n.c Thanks, Ward. -- Ward Vandewege From svn at coreboot.org Wed Jun 3 00:23:38 2009 From: svn at coreboot.org (FILO) Date: Tue, 02 Jun 2009 22:23:38 -0000 Subject: [coreboot] [FILO] #18: SD card support in FILO Message-ID: <043.dd8b65cfa027210ffe76479e0d2c88cc@coreboot.org> #18: SD card support in FILO ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: FILO | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Someone requested SD card support in FILO recently on IRC, let's add an issue for this so we don't forget about it. -- Ticket URL: FILO From maciej.pijanka at gmail.com Wed Jun 3 00:26:23 2009 From: maciej.pijanka at gmail.com (Maciej Pijanka) Date: Wed, 3 Jun 2009 00:26:23 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: <4A25892B.9010506@gmx.net> References: <4A25892B.9010506@gmx.net> Message-ID: On 02/06/2009, Carl-Daniel Hailfinger wrote: > On 02.06.2009 21:57, Maciej Pijanka wrote: >> Hello >> >> Carl-Daniel pointed me to easy tasks list in wiki, i tried to prepare some >> patch that allow to add probe_timing information (int uS value) used >> by jedec_probe (patch attached) >> > > Thanks for the patch. > Review follows: > - probe_49fl00x is a wrapper for probe_jedec. Those chips need the > probe_timing parameter as well. > - probe_sst_fwhub has the same problem. > - If someone forgets the probe_timing parameter, it will be zero. That's > bad for almost all chips. Maybe add an explicit check for nonzero delays? > - It might be best if every chip definition got that probe_timing > parameter. Other probe functions could use similar delay info. > - SPI chips want zero delay. fixed patch in attachment best regards Maciej Pijanka -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user -------------- next part -------------- A non-text attachment was scrubbed... Name: probe_timing.patch Type: application/octet-stream Size: 26681 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 00:44:25 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 00:44:25 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: References: <4A25892B.9010506@gmx.net> Message-ID: <4A25AB49.30305@gmx.net> On 03.06.2009 00:26, Maciej Pijanka wrote: > On 02/06/2009, Carl-Daniel Hailfinger wrote: > >> On 02.06.2009 21:57, Maciej Pijanka wrote: >> >>> Hello >>> >>> Carl-Daniel pointed me to easy tasks list in wiki, i tried to prepare some >>> patch that allow to add probe_timing information (int uS value) used >>> by jedec_probe (patch attached) >>> >>> >> Thanks for the patch. >> Review follows: >> - probe_49fl00x is a wrapper for probe_jedec. Those chips need the >> probe_timing parameter as well. >> - probe_sst_fwhub has the same problem. >> - If someone forgets the probe_timing parameter, it will be zero. That's >> bad for almost all chips. Maybe add an explicit check for nonzero delays? >> - It might be best if every chip definition got that probe_timing >> parameter. Other probe functions could use similar delay info. >> - SPI chips want zero delay. >> > > fixed patch in attachment > I really like it. Other than the comment on IRC, there is one minor nitpick: > Index: jedec.c > =================================================================== > --- jedec.c (revision 567) > +++ jedec.c (working copy) > @@ -91,7 +91,25 @@ > > + if (flash->probe_timing > 0) > + probe_timing_enter = probe_timing_exit = flash->probe_timing; > + else if (flash->probe_timing == TIMING_ZERO) { /* INTENTIONALLY NO DELAY */ > + probe_timing_enter = probe_timing_exit = 0; > + } else if (flash->probe_timing == TIMING_FIXME) { /* FIXME */ > + printf_debug("Chip lacks correct probe timing information, using default 10mS/40uS\n"); > + probe_timing_enter = 10000; > + probe_timing_exit = 40; > + } else if (flash->probe_timing == 0) { /* NOT SET at all ? */ > + printf_debug("Chip lacks correct probe timing information, using default 10mS/40uS\n"); > + probe_timing_enter = 10000; > + probe_timing_exit = 40; > If timing is not set (0), maybe fail as well? That would be accomplished by killing the above if branch and changing the message below to say "negative/ininitialized value". > + } else { > + printf_debug("Chip has negative value of probe_timing, failing without chip access\n"); > + return 0; > + } > Other than that, I think the patch can be Acked. Regards, Carl-Daniel -- http://www.hailfinger.org/ From rkrul at web.de Wed Jun 3 01:04:31 2009 From: rkrul at web.de (Robert) Date: Wed, 03 Jun 2009 01:04:31 +0200 Subject: [coreboot] broken tree error when building coreboot-v3 for qemu Message-ID: <4A25AFFF.6060702@web.de> Hello, i am getting the following error when trying to compile coreboot-v3 for qemu: CC build/northbridge/intel/i440bxemulation/i440bx.o CC build/southbridge/intel/i82371eb/i82371eb.o DTC build/mainboard/emulation/qemu-x86/statictree.c DTC mainboard/emulation/qemu-x86/dts (dts->lb) CC build/mainboard/emulation/qemu-x86/statictree.o AR build/util/x86emu/libx86emu.a ar: /home/robert/app/coreboot/coreboot-v3/build/util/x86emu/libx86emu.a: No such file or directory make: *** [/home/robert/app/coreboot/coreboot-v3/build/util/x86emu/libx86emu.a] Error 1 From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 01:06:16 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 01:06:16 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: References: <4A25892B.9010506@gmx.net> <4A25AB49.30305@gmx.net> Message-ID: <4A25B068.2010706@gmx.net> On 03.06.2009 00:58, Maciej Pijanka wrote: > On 03/06/2009, Carl-Daniel Hailfinger wrote: > >> If timing is not set (0), maybe fail as well? That would be accomplished >> by killing the above if branch and changing the message below to say >> "negative/ininitialized value". >> > > sure, but that will fail/skip silently most chips so we also should > change printf_debug to normal one otherwise nobody without -V notice > Yes! For the "not set" and the "negative value" case, this should definitely be printf, not printf_debug. > that they was skipped not probe failed > (maybe we need more than two levels of verbosity?) > > or some nice way to notify user when -V is not used something like > '%d chips probe were skipped, use -V to figure why' > I think your suggestion of using prinf instead of printf_debug is best. Regards, Carl-Daniel -- http://www.hailfinger.org/ From maciej.pijanka at gmail.com Wed Jun 3 01:09:43 2009 From: maciej.pijanka at gmail.com (Maciej Pijanka) Date: Wed, 3 Jun 2009 01:09:43 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: <4A25B068.2010706@gmx.net> References: <4A25892B.9010506@gmx.net> <4A25AB49.30305@gmx.net> <4A25B068.2010706@gmx.net> Message-ID: On 03/06/2009, Carl-Daniel Hailfinger wrote: > On 03.06.2009 00:58, Maciej Pijanka wrote: >> On 03/06/2009, Carl-Daniel Hailfinger >> wrote: >> >>> If timing is not set (0), maybe fail as well? That would be accomplished >>> by killing the above if branch and changing the message below to say >>> "negative/ininitialized value". >>> >> >> sure, but that will fail/skip silently most chips so we also should >> change printf_debug to normal one otherwise nobody without -V notice >> > > Yes! For the "not set" and the "negative value" case, this should > definitely be printf, not printf_debug. > > >> that they was skipped not probe failed >> (maybe we need more than two levels of verbosity?) >> >> or some nice way to notify user when -V is not used something like >> '%d chips probe were skipped, use -V to figure why' >> > > I think your suggestion of using prinf instead of printf_debug is best. > updated patch in attachment -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user -------------- next part -------------- A non-text attachment was scrubbed... Name: probe_timing.patch Type: application/octet-stream Size: 26645 bytes Desc: not available URL: From ward at gnu.org Wed Jun 3 01:23:18 2009 From: ward at gnu.org (Ward Vandewege) Date: Tue, 2 Jun 2009 19:23:18 -0400 Subject: [coreboot] broken tree error when building coreboot-v3 for qemu In-Reply-To: <4A25AFFF.6060702@web.de> References: <4A25AFFF.6060702@web.de> Message-ID: <20090602232318.GA32321@localdomain> On Wed, Jun 03, 2009 at 01:04:31AM +0200, Robert wrote: > Hello, > > i am getting the following error when trying to compile coreboot-v3 for > qemu: > > CC build/northbridge/intel/i440bxemulation/i440bx.o > CC build/southbridge/intel/i82371eb/i82371eb.o > DTC build/mainboard/emulation/qemu-x86/statictree.c > DTC mainboard/emulation/qemu-x86/dts (dts->lb) > CC build/mainboard/emulation/qemu-x86/statictree.o > AR build/util/x86emu/libx86emu.a > ar: /home/robert/app/coreboot/coreboot-v3/build/util/x86emu/libx86emu.a: > No such file or directory Do you have the 'ar' utility installed? It's part of binutils. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator From peter at stuge.se Wed Jun 3 01:26:38 2009 From: peter at stuge.se (Peter Stuge) Date: Wed, 3 Jun 2009 01:26:38 +0200 Subject: [coreboot] broken tree error when building coreboot-v3 for qemu In-Reply-To: <20090602232318.GA32321@localdomain> References: <4A25AFFF.6060702@web.de> <20090602232318.GA32321@localdomain> Message-ID: <20090602232638.14864.qmail@stuge.se> Ward Vandewege wrote: > > AR build/util/x86emu/libx86emu.a > > ar: /home/robert/app/coreboot/coreboot-v3/build/util/x86emu/libx86emu.a: > > No such file or directory > > Do you have the 'ar' utility installed? It's part of binutils. I suspect it isn't finding libx86emu.a. I'm not sure there are proper x86emu dependencies in the v3 Makefiles. Robert, can you try building libx86emu.a in that dir manually? //Peter From rkrul at web.de Wed Jun 3 01:44:29 2009 From: rkrul at web.de (Robert) Date: Wed, 03 Jun 2009 01:44:29 +0200 Subject: [coreboot] broken tree error when building coreboot-v3 for qemu Message-ID: <4A25B95D.6090904@web.de> >/ Do you have the 'ar' utility installed? It's part of binutils. Yes, i have it installed /> Robert, can you try building libx86emu.a in that dir manually? The dir is not there. From svn at coreboot.org Wed Jun 3 01:49:00 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 01:49:00 +0200 Subject: [coreboot] [v2] r4330 - trunk/coreboot-v2/util/optionlist Message-ID: Author: uwe Date: 2009-06-03 01:49:00 +0200 (Wed, 03 Jun 2009) New Revision: 4330 Modified: trunk/coreboot-v2/util/optionlist/Options-wiki.xsl Log: More compact format for wiki output at http://www.coreboot.org/Coreboot_Options (trivial). Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/coreboot-v2/util/optionlist/Options-wiki.xsl =================================================================== --- trunk/coreboot-v2/util/optionlist/Options-wiki.xsl 2009-06-01 20:02:21 UTC (rev 4329) +++ trunk/coreboot-v2/util/optionlist/Options-wiki.xsl 2009-06-02 23:49:00 UTC (rev 4330) @@ -25,29 +25,22 @@ indent="yes" /> -This is an automatically generated list of '''coreboot compile-time options'''. +This is an automatically generated list of '''coreboot v2 compile-time options'''. Last update: . -{| border="0" +{| border="0" style="font-size: smaller" |- bgcolor="#6699dd" ! align="left" | Option ! align="left" | Comment ! align="left" | Default ! align="left" | Export -! align="left" | Format +! align="left" | Format + |- bgcolor="#eeeeee" -| - -| - -| - -| - -| - +| || || || || + |} From kevin at koconnor.net Wed Jun 3 03:44:48 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Tue, 2 Jun 2009 21:44:48 -0400 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <20090602164910.GC25218@skynet.be> References: <20090529134428.GA13500@skynet.be> <20090530155900.GA11598@morn.localdomain> <20090602164528.GB25218@skynet.be> <20090602164910.GC25218@skynet.be> Message-ID: <20090603014448.GA17686@morn.localdomain> On Tue, Jun 02, 2009 at 06:49:10PM +0200, Luc Verhaegen wrote: > On Tue, Jun 02, 2009 at 06:45:28PM +0200, Luc Verhaegen wrote: > > How would you want to store information, and how would you want to > > handle parsing of this information? Do you really want to store > > configuration in xml and include an xml parser in a bios? Do you want to > > invent your own structured information storage system? If so, what is > > wrong with what we do now, especially, since we do not have to reprogram > > part of our flash every 5 seconds? I would place a configuration file in flash (a simple one). I would not use xml. I do not believe it is realistic that users will change bootup config setting every 5 seconds. > I cannot help but feel that this is just trying to be different for the > sake of trying to be different. Try the following: - Boot your machine with a factory bios and read the flash into a file. - poweroff the machine, remove (or add) a pci device, bootup, and read the flash to a new file - compare the files. I think you'll find (as I did on my machine) that the two flash images are different. I'm suggesting to be different, for the sake of being better. The existing factory bios developers ran out of space in cmos and so they use both cmos and flash. I think 200 bytes of storage is not enough space - and having two places to store things is silly. Why use 200 bytes and 250000 bytes when you can just use the 250000 bytes? -Kevin From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 04:52:55 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 04:52:55 +0200 Subject: [coreboot] [RFC] Configuration Data File Format Message-ID: <4A25E587.9030800@gmx.net> Since the topic of optimal flash usage for configuration data comes up repeatedly, I'd like to propose a flash-friendly and LAR/CBFS compatible way to store and update configuration data. The CDFF data is stored inside an uncompressed LAR/CBFS archive member which occupies a full flash erase block, either with the start of the header at the start of the erase block or with the start of the data section at the start of the erase block. The CDFF file format is as follows: File Format header: 4 bytes magic header "CDFF" 4 bytes total length of CDFF area excluding file header Configuration Data header: 2 bytes magic header "CD" 2 bytes version number of configuration data, at least 0x0001 (0x0000 means invalid) 4 bytes total length of Configuration Data excluding Configuration Data header Configuration Item header (version 0x0001): 2 bytes magic header "CI" 2 bytes data type, must not be 0x0000 (which is reserved) 4 bytes length of Configuration Item n bytes of Configuration Item content Each header is aligned at a 4 byte boundary. The File Format header exists exactly once at the start. Directly after the File Format header, the first Configuration Data header starts. It is a "container" for multiple Configuration Items. The version number has to be at least 0x0001. To mark the Configuation Data as invalid, the version number is set to 0x0000 which is a flash-friendly operation possible without erase. If the version number is 0x0000, the reader skips over CD total length bytes starting after the header and looks for the next CD header aligned to the next 4 byte boundary. Directly after the Configuration Data header, the first Configuration Item header starts. It holds a single configuration item or its description. The CI data type MSB is 0 if the data is a value and 1 for the matching (null-terminated) name/description. After the data there is the next CI header aligned at the next 4 byte boundary. If you need to update the data, simply write a new CD container with CI data directly after the end of the last valid CD container. If the write was successful, mark the previous container as invalid. If not, the old container will still be valid and everything is OK. If there's not enough room left for a new CD container, erase the whole block and write a new CDFF header, CD header and all CIs. This scheme keeps flash wear at a minium, has safe updates (except in the case where all space is used up and the block has to be erased), is fast and easy to walk and extensible enough to last a lifetime. Example file: 0x43444646 (CDFF magic) 0x00000FF8 (eraseblockisze 4096 - headersize 8) 0x4344 (CD magic) 0x0001 (version) 0xbla (CD length) 0x4349 (CI magic) 0x0001 (data type, data) 0x00000013 (CI length) "hda1:/boot/vmlinux\0" (data) 0xff (padding) 0x4349 (CI magic) 0x8001 (data type, description) 0x00000009 (CI length) "bootfile\0" 0xffffff (padding) 0x4349 (CI magic) 0x0002 (data type, data) 0x00000018 (CI length) "acpi=off root=/dev/sda2\0" (data) 0x4349 (CI magic) 0x8002 (data type, description) 0x0000000B (CI length) "bootparams\0" 0xff (padding) Since the CI name is (optionally) stored along with the CI data, running out of data types is only possible if we have more than 32767 different CIs. Any config reader can just search for the name if it wants some data. The naming also avoids having a central registry about which data type has which number, an annoyance present with our current NVRAM scheme. A checksum is possible (even in a mostly flash-friendly way), but it would have cluttered this design doc. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Wed Jun 3 05:15:05 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 05:15:05 +0200 Subject: [coreboot] [v2] r4331 - trunk/coreboot-v2/src/southbridge/amd/rs690 Message-ID: Author: zbao Date: 2009-06-03 05:15:05 +0200 (Wed, 03 Jun 2009) New Revision: 4331 Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c Log: Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming. Signed-off-by: Zheng Bao Acked-by: Carl-Daniel Hailfinger Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-02 23:49:00 UTC (rev 4330) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-03 03:15:05 UTC (rev 4331) @@ -148,7 +148,7 @@ /* waits until SB has trained to L0, poll for bit0-5 = 0x10 */ do { reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0); - reg &= 0x1f; /* remain LSB 5 bits */ + reg &= 0x3f; /* remain LSB [5:0] bits */ } while (LC_STATE_RECONFIG_GPPSB != reg); /* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */ From Zheng.Bao at amd.com Wed Jun 3 05:17:27 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Wed, 3 Jun 2009 11:17:27 +0800 Subject: [coreboot] [patch]: a little error is fixed. In-Reply-To: <4A2472C1.8060105@gmx.net> References: <4A2472C1.8060105@gmx.net> Message-ID: Thanks, committed in r4331. Zheng -----Original Message----- From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Carl-Daniel Hailfinger Sent: Tuesday, June 02, 2009 8:31 AM To: Bao, Zheng Cc: coreboot Subject: Re: [coreboot] [patch]: a little error is fixed. On 01.06.2009 04:34, Bao, Zheng wrote: > Modify it based on the RPR. 5.7.7. Switching GPPSB Configuration By > Register Programming. > > Signed-off-by: Zheng Bao > Acked-by: Carl-Daniel Hailfinger Do you have commit rights or should I commit? Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot From mylesgw at gmail.com Wed Jun 3 06:35:45 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 2 Jun 2009 22:35:45 -0600 Subject: [coreboot] broken tree error when building coreboot-v3 for qemu In-Reply-To: <4A25B95D.6090904@web.de> References: <4A25B95D.6090904@web.de> Message-ID: <2831fecf0906022135w371720beib6f3842c1374cd58@mail.gmail.com> On Tue, Jun 2, 2009 at 5:44 PM, Robert wrote: >> / Do you have the 'ar' utility installed? It's part of binutils. > > Yes, i have it installed > > /> Robert, can you try building libx86emu.a in that dir manually? > > The dir is not there. I have the same problem. Rev 1166 builds for me. 1168 has different breakage. Sorry I don't have the time to find it right now, but luckily there are only a few changes there. Thanks, Myles From Zheng.Bao at amd.com Wed Jun 3 08:22:48 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Wed, 3 Jun 2009 14:22:48 +0800 Subject: [coreboot] [patch] some obvious bugs in rs690 Message-ID: This patch is about some noticeable bugs which are made by no reason. 1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right? 2. In rs690_pcie.c, (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment). In rpr 5.10.2, step 2, step 2.1 & step 2.6 (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20, instead of PCIEIND_P: 0x20. In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation Signed-off-by: Zheng Bao ------------------ diff -Nuar -x .svn ./src/southbridge/amd/rs690/rs690_cmn.c ../coreboot-v2-current/src/southbridge/amd/rs690/rs690_cmn.c --- ./src/southbridge/amd/rs690/rs690_cmn.c 2009-05-12 17:32:24.000000000 +0800 +++ ../coreboot-v2-current/src/southbridge/amd/rs690/rs690_cmn.c 2009-06-02 16:58:01.000000000 +0800 @@ -49,7 +49,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { /*get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c); + u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ @@ -62,7 +62,7 @@ u32 reg_old, reg; /*get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c); + u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ diff -Nuar -x .svn ./src/southbridge/amd/rs690/rs690_pcie.c ../coreboot-v2-current/src/southbridge/amd/rs690/rs690_pcie.c --- ./src/southbridge/amd/rs690/rs690_pcie.c 2009-06-03 12:01:42.000000000 +0800 +++ ../coreboot-v2-current/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-03 14:40:00.000000000 +0800 @@ -212,8 +212,8 @@ set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0); /* no description in datasheet. */ /* init GPPSB port */ - /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 0*/ - set_pcie_enable_bits(dev, 0x70, 7 << 16, 0xd << 16); + /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 1*/ + set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0xd << 16); /* PCIE initialization 5.10.2: rpr 2.4 */ set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14); /* Do not gate the electrical idle from the PHY and enables the escape from L1L23 */ @@ -240,7 +240,7 @@ } /* step 5: dynamic slave CPL buffer allocation */ - set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); + set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 11, 1 << 11); /* step 5a: Training for GPP devices */ /* init GPP */ -------------- next part -------------- A non-text attachment was scrubbed... Name: rs690_small_bug_obviously.patch Type: application/octet-stream Size: 2864 bytes Desc: rs690_small_bug_obviously.patch URL: From svn at coreboot.org Wed Jun 3 09:50:40 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 09:50:40 +0200 Subject: [coreboot] [flashrom] r568 - trunk Message-ID: Author: libv Date: 2009-06-03 09:50:39 +0200 (Wed, 03 Jun 2009) New Revision: 568 Modified: trunk/board_enable.c Log: Board enable: Gigabyte GA K8N SLI. Raises bits 0 and 2 on offset 0xE1 in the system control area of the nvidia ck804 lpc. Signed-off-by: Luc Verhaegen Acked-by: Carl-Daniel Hailfinger Acked-by: Alexander Gordeev Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-02 19:54:22 UTC (rev 567) +++ trunk/board_enable.c 2009-06-03 07:50:39 UTC (rev 568) @@ -372,6 +372,31 @@ return 0; } +/** + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. + */ +static int board_ga_k8n_sli(const char *name) +{ + struct pci_dev *dev; + uint32_t base; + uint8_t tmp; + + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ + if (!dev) { + fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n"); + return -1; + } + + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + + /* if anyone knows more about nvidia lpcs, feel free to explain this */ + tmp = inb(base + 0xE1); + tmp |= 0x05; + outb(tmp, base + 0xE1); + + return 0; +} + static int board_hp_dl145_g3_enable(const char *name) { /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ @@ -670,6 +695,7 @@ {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", board_biostar_p4m80_m4}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, @@ -787,7 +813,6 @@ { "Boser", "HS-6637", }, { "DFI", "855GME-MGF", }, { "FIC", "VA-502", }, - { "GIGABYTE", "GA-K8N-SLI", }, { "MSI", "MS-6178", }, { "MSI", "MS-7260 (K9N Neo)", }, { "PCCHIPS", "M537DMA33", }, From libv at skynet.be Wed Jun 3 09:57:45 2009 From: libv at skynet.be (Luc Verhaegen) Date: Wed, 3 Jun 2009 09:57:45 +0200 Subject: [coreboot] [Patch] Flashrom: Add gA-k8n-sli board enable. In-Reply-To: <200906022243.56600.lasaine@lvk.cs.msu.su> References: <20090602141352.GA24880@skynet.be> <200906022243.56600.lasaine@lvk.cs.msu.su> Message-ID: <20090603075745.GA27549@skynet.be> On Tue, Jun 02, 2009 at 10:43:56PM +0400, Alexander Gordeev wrote: > On Tuesday 02 June 2009 18:13:52 Luc Verhaegen wrote: > > Still needs to be tested by alexander. > > > > Luc Verhaegen. > > WOW, it is working now! Thanks a lot! > > alex at tornado:~/bios$ sudo ../development/flashrom/trunk/flashrom > flashrom v0.9.0-r566 > No coreboot table found. > Found chipset "NVIDIA CK804", enabling flash write... OK. > Found board "GIGABYTE GA-K8N-SLI", enabling flash write... OK. > Calibrating delay loop... OK. > Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. > No operations were specified. > > I also tested read, write, erase and verify operations and rebooted the > machine with the new bios. Everything is ok! > > -- > Alexander Great, thanks! -> r568 Luc Verhaegen. From paulepanter at users.sourceforge.net Wed Jun 3 10:40:32 2009 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 03 Jun 2009 10:40:32 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: References: <4A25892B.9010506@gmx.net> <4A25AB49.30305@gmx.net> <4A25B068.2010706@gmx.net> Message-ID: <1244018432.5947.16.camel@mattotaupa.wohnung.familie-menzel.net> Dear Maciej, thank you for your patch. Just some typos and wording suggestions. Thanks and bests, Paul Am Mittwoch, den 03.06.2009, 01:09 +0200 schrieb Maciej Pijanka: > Signed-Off-by: Maciej Pijanka > Index: flash.h > =================================================================== > --- flash.h (revision 567) > +++ flash.h (working copy) > @@ -155,6 +155,7 @@ > uint32_t tested; > > int (*probe) (struct flashchip *flash); > + int probe_timing; > int (*erase) (struct flashchip *flash); > int (*write) (struct flashchip *flash, uint8_t *buf); > int (*read) (struct flashchip *flash, uint8_t *buf); > @@ -182,6 +183,18 @@ > #define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | > TEST_BAD_ERASE | TEST_BAD_WRITE) > #define TEST_BAD_MASK 0xf0 > > +/* Timing used in probe routines defined in chips definition Timing used in probe routines is defined in chip definition > + * to denote which chip uses which timing, additionally > + * in jedec_probe() chip with 0 in probe_timing field > + * will emit debug message about not set field. s/not set/unset/ > + * > + * SPI devices will always have zero and ignore this field. > + */ > +#define TIMING_FIXME -1 > +/* this is intentionally same value as fixme */ > +#define TIMING_IGNORED -1 > +#define TIMING_ZERO -2 > + > extern struct flashchip flashchips[]; > > struct penable { > Index: jedec.c > =================================================================== > --- jedec.c (revision 567) > +++ jedec.c (working copy) > @@ -91,7 +91,21 @@ > uint8_t id1, id2; > uint32_t largeid1, largeid2; > uint32_t flashcontent1, flashcontent2; > + int probe_timing_enter, probe_timing_exit; > > + if (flash->probe_timing > 0) > + probe_timing_enter = probe_timing_exit = flash->probe_timing; > + else if (flash->probe_timing == TIMING_ZERO) { /* INTENTIONALLY NO DELAY */ > + probe_timing_enter = probe_timing_exit = 0; > + } else if (flash->probe_timing == TIMING_FIXME) { /* FIXME or IGNORED */ > + printf_debug("Chip lacks correct probe timing information, using default 10mS/40uS\n"); Full stop (.) at the end of sentence. > + probe_timing_enter = 10000; > + probe_timing_exit = 40; > + } else { > + printf("Chip has negative value of probe_timing, failing without chip access\n"); To be consistent s/probe_timing/probe timing information/. Full stop at the end. [?] > Index: flashchips.c > =================================================================== > --- flashchips.c (revision 567) > +++ flashchips.c (working copy) [?] > @@ -77,6 +80,7 @@ > .page_size = 64 * 1024, > .tested = TEST_UNTESTED, > .probe = probe_29f040b, > + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ s/don't/does not/ (same for the other comments) > .erase = erase_29f040b, > .write = write_29f040b, > .read = read_memmapped, > @@ -92,6 +96,7 @@ > .page_size = 64 * 1024, > .tested = TEST_OK_PREW, > .probe = probe_29f040b, > + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ > .erase = erase_29f040b, > .write = write_29f040b, > .read = read_memmapped, > @@ -107,6 +112,7 @@ > .page_size = 64 * 1024, > .tested = TEST_UNTESTED, > .probe = probe_jedec, > + .probe_timing = TIMING_FIXME, > .erase = erase_29f040b, > .write = write_29f040b, > .read = read_memmapped, > @@ -122,6 +128,7 @@ > .page_size = 64 * 1024, > .tested = TEST_UNTESTED, > .probe = probe_29f040b, > + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ > .erase = erase_29f040b, > .write = write_29f040b, > .read = read_memmapped, > @@ -137,6 +144,7 @@ > .page_size = 64 * 1024, > .tested = TEST_UNTESTED, > .probe = probe_29f040b, > + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ > .erase = erase_29f040b, > .write = write_29f040b, > .read = read_memmapped, > @@ -152,6 +160,7 @@ > .page_size = 128, > .tested = TEST_UNTESTED, > .probe = probe_jedec, > + .probe_timing = TIMING_FIXME, > .erase = erase_chip_jedec, > .write = write_jedec, > .read = read_memmapped, > @@ -407,7 +416,8 @@ > .total_size = 64, > .page_size = 128, > .tested = TEST_OK_PREW, > - .probe = probe_jedec, > + .probe = probe_jedec, > + .probe_timing = 10000, /* 10mS, Enter=Exec */ > .erase = erase_chip_jedec, > .write = write_jedec, > .read = read_memmapped, > @@ -424,6 +434,7 @@ > .page_size = 128, > .tested = TEST_OK_PRE, > .probe = probe_jedec, > + .probe_timing = 10000, /* 10mS, Enter=Exec */ > .erase = erase_chip_jedec, > .write = write_jedec, /* FIXME */ > .read = read_memmapped, > @@ -439,6 +450,7 @@ > .page_size = 256, > .tested = TEST_OK_PREW, > .probe = probe_jedec, > + .probe_timing = TIMING_FIXME, > .erase = erase_chip_jedec, > .write = write_jedec, > .read = read_memmapped, > @@ -454,6 +466,7 @@ > .page_size = 256, > .tested = TEST_UNTESTED, > .probe = probe_jedec, > + .probe_timing = TIMING_FIXME, > .erase = erase_chip_jedec, > .write = write_jedec, > .read = read_memmapped, > @@ -604,6 +617,7 @@ > .page_size = 64, > .tested = TEST_OK_PREW, > .probe = probe_jedec, > + .probe_timing = TIMING_FIXME, > .erase = erase_chip_jedec, > .write = write_49f002, > .read = read_memmapped, > @@ -619,6 +633,7 @@ > .page_size = 256, > .tested = TEST_UNTESTED, > .probe = probe_jedec, > + .probe_timing = TIMING_FIXME, /* doc1008.pdf dont says anything about probe timing */ s/dont/does not/ [?] -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: Dies ist ein digital signierter Nachrichtenteil URL: From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 10:56:04 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 10:56:04 +0200 Subject: [coreboot] broken tree error when building coreboot-v3 for qemu In-Reply-To: <2831fecf0906022135w371720beib6f3842c1374cd58@mail.gmail.com> References: <4A25B95D.6090904@web.de> <2831fecf0906022135w371720beib6f3842c1374cd58@mail.gmail.com> Message-ID: <4A263AA4.8040904@gmx.net> On 03.06.2009 06:35, Myles Watson wrote: > On Tue, Jun 2, 2009 at 5:44 PM, Robert wrote: > >>> / Do you have the 'ar' utility installed? It's part of binutils. >>> >> Yes, i have it installed >> >> /> Robert, can you try building libx86emu.a in that dir manually? >> >> The dir is not there. >> > > I have the same problem. Rev 1166 builds for me. 1168 has different breakage. > > Sorry I don't have the time to find it right now, but luckily there > are only a few changes there. > Maybe a svn:external is missing? Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Wed Jun 3 12:47:19 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 12:47:19 +0200 Subject: [coreboot] [v2] r4332 - in trunk/coreboot-v2: src/console src/cpu/amd/dualcore src/cpu/amd/model_fxx src/cpu/amd/quadcore src/cpu/intel/hyperthreading src/include/console src/include/pc80 src/mainboard/amd/dbm690t src/mainboard/amd/pistachio src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/broadcom/blast src/mainboard/dell/s1850 src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli src/mainboard/hp/dl145_g3 src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/intel/jarrell src/mainboard/iwill/dk8_htx src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x src/mainboard/msi/ms7135 src/mainboard/msi/ms7260 src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/newisys/khepri src/mainboard/nvidia/l1_2pvv src/mainboard/sunw/ultra40 src/mainboard/supermicro/h8dme src/mainboard/supermicro/h8dmr src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion/tim8690 src/mainboard/tyan/s2735 src/mainboard/tyan/s2850 src/mainboard/tyan/s2875 src/mainboard/tyan/s2880 src/mainboard/tyan/s2881 src/mainboard/tyan/s2882 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/mainboard/tyan/s2912 src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880 src/mainboard/tyan/s4882 src/northbridge/amd/amdfam10 src/northbridge/amd/amdk8 src/pc80 src/southbridge/amd/amd8111 src/southbridge/amd/amd8131 src/southbridge/amd/sb600 src/southbridge/broadcom/bcm5785 src/southbridge/intel/esb6300 src/southbridge/intel/i3100 src/southbridge/intel/i82801ca src/southbridge/intel/i82801dbm src/southbridge/intel/i82801er src/southbridge/intel/i82801gx src/southbridge/intel/i82801xx src/southbridge/intel/pxhd src/southbridge/nvidia/ck804 src/southbridge/nvidia/mcp55 src/southbridge/sis/sis966 src/superio/winbond/w83627ehg src/superio/winbond/w83627hf util/options Message-ID: Author: libv Date: 2009-06-03 12:47:19 +0200 (Wed, 03 Jun 2009) New Revision: 4332 Modified: trunk/coreboot-v2/src/console/console.c trunk/coreboot-v2/src/console/printk.c trunk/coreboot-v2/src/console/uart8250_console.c trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c trunk/coreboot-v2/src/include/console/console.h trunk/coreboot-v2/src/include/pc80/mc146818rtc.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/pc80/mc146818rtc.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c trunk/coreboot-v2/util/options/build_opt_tbl.c Log: CMOS: Add set_option and rework get_option. To ease some of my debugging pain on the unichrome, i decided i needed to move FB size selection into cmos, so i could test a size and then reset it to the default after loading this value so that the next reboot uses the (working) default again. This meant implementing set_option in parallel to get_option. get_option was then found to have inversed argument ordering (like outb) and passing char * and then depending on the cmos layout length, which made me feel quite uncomfortable. Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go. So all users of get_option now have their arguments inversed and switched from using ints to unsigned ints now. The way get_cmos_value was implemented forced us to not overlap byte and to have multibyte values be byte aligned. This logic is now adapted to do a full uint32_t read (when needed) at any offset and any length up to 32, and the shifting all happens inside an uint32_t as well. set_cmos_value was implemented similarly. Both routines have been extensively tested in a quick separate little program as it is not easy to get this stuff right. build_opt_tbl.c was altered to function correctly within these new parameters. The enum value retrieval has been changed strol(..., NULL, 10) to stroul(..., NULL, 0), so that we not only are able to use unsigned ints now but so that we also interprete hex values correctly. The 32bit limit gets imposed on all entries not marked reserved, an unused "user_data" field that appeared in a lot of cmos.layouts has been changed to reserved as well. Signed-off-by: Luc Verhaegen Acked-by: Peter Stuge Modified: trunk/coreboot-v2/src/console/console.c =================================================================== --- trunk/coreboot-v2/src/console/console.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/console/console.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -14,9 +14,10 @@ void console_init(void) { struct console_driver *driver; - if(get_option(&console_loglevel, "debug_level")) - console_loglevel=DEFAULT_CONSOLE_LOGLEVEL; - + + if (get_option("debug_level", &console_loglevel)) + console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; + for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; Modified: trunk/coreboot-v2/src/console/printk.c =================================================================== --- trunk/coreboot-v2/src/console/printk.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/console/printk.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -9,18 +9,9 @@ #include #include -/* printk's without a loglevel use this.. */ -#define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */ - -/* We show everything that is MORE important than this.. */ -#define MINIMUM_CONSOLE_LOGLEVEL 1 /* Minimum loglevel we let people use */ - /* Keep together for sysctl support */ -int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; -int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL; -int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL; -int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +unsigned int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; void display(char*); extern int vtxprintf(void (*)(unsigned char), const char *, va_list); Modified: trunk/coreboot-v2/src/console/uart8250_console.c =================================================================== --- trunk/coreboot-v2/src/console/uart8250_console.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/console/uart8250_console.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -29,10 +29,10 @@ static void ttyS0_init(void) { static const unsigned char div[8]={1,2,3,6,12,24,48,96}; - int b_index=0; + unsigned int b_index=0; unsigned int divisor=TTYS0_DIV; - if(get_option(&b_index,"baud_rate")==0) { + if(!get_option("baud_rate", &b_index)) { divisor=div[b_index]; } uart8250_init(TTYS0_BASE, divisor, TTYS0_LCS); Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -14,7 +14,7 @@ #include static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; +static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS; #include "dualcore_id.c" @@ -62,7 +62,7 @@ unsigned nb_cfg_54; int bsp_apic_id = lapicid(); // bsp apicid - get_option(&disable_siblings, "dual_core"); + get_option("dual_core", &disable_siblings); //get the nodes number dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); @@ -127,7 +127,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - get_option(&disable_siblings, "dual_core"); + get_option("dual_core", &disable_siblings); } result = cpuid(0x80000008); /* See how many sibling cpus we have */ Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -248,7 +248,7 @@ struct mtrr_state mtrr_state; device_t f1_dev, f2_dev, f3_dev; - int enable_scrubbing; + uint32_t enable_scrubbing; uint32_t dcl; f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); @@ -266,7 +266,7 @@ /* See if we scrubbing should be enabled */ enable_scrubbing = 1; - get_option(&enable_scrubbing, "hw_scrubber"); + get_option("hw_scrubber", &enable_scrubbing); /* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) { Modified: trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -82,7 +82,7 @@ u32 disable_siblings = !CONFIG_LOGICAL_CPUS; - get_option(&disable_siblings, "quad_core"); + get_option("quad_core", &disable_siblings); siblings = get_max_siblings(sysconf.nodes); Modified: trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -7,7 +7,7 @@ #include static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; +static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS; void intel_sibling_init(device_t cpu) { @@ -17,7 +17,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - get_option(&disable_siblings, "hyper_threading"); + get_option("hyper_threading", &disable_siblings); } result = cpuid(1); /* Is hyperthreading supported */ Modified: trunk/coreboot-v2/src/include/console/console.h =================================================================== --- trunk/coreboot-v2/src/include/console/console.h 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/include/console/console.h 2009-06-03 10:47:19 UTC (rev 4332) @@ -26,7 +26,7 @@ extern struct console_driver console_drivers[]; extern struct console_driver econsole_drivers[]; -extern int console_loglevel; +extern unsigned int console_loglevel; int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) Modified: trunk/coreboot-v2/src/include/pc80/mc146818rtc.h =================================================================== --- trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-06-03 10:47:19 UTC (rev 4332) @@ -94,11 +94,9 @@ #if !defined(ASSEMBLY) void rtc_init(int invalid); -#if USE_OPTION_TABLE == 1 -int get_option(void *dest, char *name); -#else -static inline int get_option(void *dest, char *name) { return -2; } + +int get_option(char *name, unsigned int *value); +int set_option(char *name, unsigned int value); #endif -#endif #endif /* PC80_MC146818RTC_H */ Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -42,7 +42,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu - 728 256 h 0 user_data + 728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -39,7 +39,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -65,7 +65,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -41,7 +41,7 @@ 432 8 h 0 boot_countdown #440 4 e 9 slow_cpu 444 1 e 1 nmi -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 h 0 user_data +728 256 r 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -64,7 +64,7 @@ } iommu = 1; - get_option(&iommu, "iommu"); + get_option("iommu", &iommu); if (iommu) { /* Add a Gart apeture resource */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -1258,7 +1258,7 @@ unsigned nb_cfg_54; unsigned siblings; int cores_found; - int disable_siblings; + uint32_t disable_siblings; unsigned ApicIdCoreIdSize; nb_cfg_54 = 0; @@ -1271,7 +1271,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option(&disable_siblings, "quad_core"); + get_option("quad_core", &disable_siblings); #endif // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -48,7 +48,7 @@ } iommu = 1; - get_option(&iommu, "iommu"); + get_option("iommu", &iommu); if (iommu) { /* Add a Gart apeture resource */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -1177,7 +1177,7 @@ unsigned nb_cfg_54; unsigned siblings; int e0_later_single_core; - int disable_siblings; + uint32_t disable_siblings; nb_cfg_54 = 0; sysconf.enabled_apic_ext_id = 0; @@ -1190,7 +1190,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option(&disable_siblings, "dual_core"); + get_option("dual_core", &disable_siblings); #endif // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0) Modified: trunk/coreboot-v2/src/pc80/mc146818rtc.c =================================================================== --- trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -197,41 +197,69 @@ #if USE_OPTION_TABLE == 1 -/* This routine returns the value of the requested bits - input bit = bit count from the beginning of the cmos image - length = number of bits to include in the value - ret = a character pointer to where the value is to be returned - output the value placed in ret - returns 0 = successful, -1 = an error occurred -*/ -static int get_cmos_value(unsigned long bit, unsigned long length, void *vret) +/* + * Functions to save/return values stored in the 256byte cmos. + * + * To be able to use space maximally we want to only store as many bits as + * needed, and not be limited by byte boundaries. We therefor clamp the size + * down to an unsigned int. Since the values that we are allowed to touch are + * either an enum or a hexadecimal value, this size should suit most purposes. + * + * These two functions are doing bitshifting, and are therefor a bit + * nontrivial. To understand these operations, first read the ones outside the + * loop. The ones inside the loop are just adding i to the same calculations, + * with the shift twice inverted, as negative shifts aren't nice. + */ +static unsigned int +get_cmos_value(int bit, int length) { - unsigned char *ret; - unsigned long byte,byte_bit; - unsigned long i; - unsigned char uchar; + unsigned int tmp; + int i; - /* The table is checked when it is built to ensure all - values are valid. */ - ret = vret; - byte=bit/8; /* find the byte where the data starts */ - byte_bit=bit%8; /* find the bit in the byte where the data starts */ - if(length<9) { /* one byte or less */ - uchar = cmos_read(byte); /* load the byte */ - uchar >>= byte_bit; /* shift the bits to byte align */ - /* clear unspecified bits */ - ret[0] = uchar & ((1 << length) -1); + /* negative left shift --> right shift */ + tmp = cmos_read(bit / 8) >> (bit % 8); + + for (i = 1; (8 * i) < ((bit % 8) + length); i++) + tmp |= cmos_read((bit / 8) + i) << ((8 * i) - (bit % 8)); + + /* 1 << 32 - 1 isn't cool inside an int */ + if (length != 32) + tmp &= (1 << length) - 1; + + return tmp; +} + +static void +set_cmos_value(int bit, int length, unsigned int value) +{ + unsigned int mask; + unsigned char cmos; + int i; + + /* 1 << 32 - 1 isn't cool inside an int */ + if (length != 32) + mask = (1 << length) - 1; + else + mask = -1; + + value &= mask; + + /* negative right shifts --> left shifts */ + cmos = cmos_read(bit / 8); + cmos &= ~(mask << (bit % 8)); + cmos |= value << (bit % 8); + cmos_write(cmos, bit / 8); + + for (i = 1; (8 * i) < ((bit % 8) + length); i++) { + cmos = cmos_read((bit / 8) + i); + cmos &= ~(mask >> ((8 * i) - (bit % 8))); + cmos |= value >> ((8 * i) - (bit % 8)); + cmos_write(cmos, (bit / 8) + i); } - else { /* more that one byte so transfer the whole bytes */ - for(i=0;length;i++,length-=8,byte++) { - /* load the byte */ - ret[i]=cmos_read(byte); - } - } - return 0; } -int get_option(void *dest, char *name) +int +get_option(char *name, unsigned int *value) { extern struct cmos_option_table option_table; struct cmos_option_table *ct; @@ -241,7 +269,7 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - + /* find the requested entry record */ ct=&option_table; ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length); @@ -256,12 +284,72 @@ printk_err("ERROR: No cmos option '%s'\n", name); return(-2); } - - if(get_cmos_value(ce->bit, ce->length, dest)) - return(-3); + + if (ce->length > 32) { + printk_err("ERROR: cmos option '%s' is too large.\n", name); + return -3; + } + + + *value = get_cmos_value(ce->bit, ce->length); + if(!rtc_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC)) + LB_CKS_RANGE_END,LB_CKS_LOC)) return(-4); return(0); } + +int +set_option(char *name, unsigned int value) +{ + extern struct cmos_option_table option_table; + struct cmos_option_table *ct; + struct cmos_entries *ce; + size_t namelen; + int found = 0; + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + /* find the requested entry record */ + ct = &option_table; + ce = (struct cmos_entries*) ((unsigned char *) ct + ct->header_length); + + for(;ce->tag==LB_TAG_OPTION; + ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) { + if (memcmp(ce->name, name, namelen) == 0) { + found=1; + break; + } + } + + if (!found) { + printk_err("ERROR: Unknown cmos option '%s'\n", name); + return(-2); + } + + if (ce->length > 32) { + printk_err("ERROR: cmos option '%s' is too large.\n", name); + return -3; + } + + set_cmos_value(ce->bit, ce->length, value); + + /* We should not update the checksum here. */ + + return 0; +} +#else +int +get_option(char *name, unsigned int *value) +{ + return -2; +} + +int +set_option(char *name, unsigned int value) +{ + return -2; +} + #endif /* USE_OPTION_TABLE */ Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -76,7 +76,7 @@ uint16_t word; uint16_t pm10_bar; uint32_t dword; - int on; + uint32_t on; #if 0 printk_debug("ACPI: disabling NMI watchdog.. "); @@ -113,7 +113,7 @@ /* power on after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); + get_option("power_on_after_fail", &on); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -130,7 +130,7 @@ /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); + get_option("slow_cpu", &on); if(on) { pm10_bar = (pci_read_config16(dev, 0x58)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -108,7 +108,7 @@ static void lpc_init(struct device *dev) { uint8_t byte; - int nmi_option; + uint32_t nmi_option; /* IO APIC initialization */ byte = pci_read_config8(dev, 0x4B); @@ -142,7 +142,7 @@ byte |= (1 << 6); /* clear LPCERR */ pci_write_config8(dev, 0x40, byte); nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte |= (1 << 7); /* set NMI */ pci_write_config8(dev, 0x40, byte); Modified: trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -278,7 +278,7 @@ uint32_t dword; uint16_t word; uint8_t byte; - int nmi_option; + uint32_t nmi_option; /* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); @@ -323,7 +323,7 @@ /* NMI enable */ nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if(nmi_option) { dword = pci_read_config32(dev, 0x44); dword |= (1<<0); Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -165,7 +165,7 @@ /* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); + get_option("power_on_after_fail", &on); byte = pm_ioread(0x74); byte &= ~0x03; if (on) { @@ -226,7 +226,7 @@ byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ printk_info("++++++++++set NMI+++++\n"); Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -23,7 +23,7 @@ { uint8_t byte; uint8_t byte_old; - int nmi_option; + uint32_t nmi_option; uint32_t dword; @@ -31,8 +31,8 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { + get_option("nmi", &nmi_option); + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -277,7 +277,7 @@ { uint8_t byte; uint32_t value; - int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL; + uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL; /* sata settings */ pci_write_config32(dev, 0x58, 0x00001181); @@ -326,7 +326,7 @@ esb6300_enable_lpc(dev); - get_option(&pwr_on, "power_on_after_fail"); + get_option("power_on_after_fail", &pwr_on); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -297,7 +297,7 @@ static void lpc_init(struct device *dev) { u8 byte; - int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL; + uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL; setup_ioapic(dev); @@ -306,7 +306,7 @@ i3100_enable_serial_irqs(dev); - get_option(&pwr_on, "power_on_after_fail"); + get_option("power_on_after_fail", &pwr_on); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -88,7 +88,7 @@ { uint32_t dword; int rtc_failed; - int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3); rtc_failed = pmcon3 & RTC_BATTERY_DEAD; @@ -99,7 +99,7 @@ pmcon3 &= ~RTC_POWER_FAILED; } - get_option(&pwr_on, "power_on_after_fail"); + get_option("power_on_after_fail", &pwr_on); pmcon3 &= ~SLEEP_AFTER_POWER_FAIL; if (!pwr_on) { pmcon3 |= SLEEP_AFTER_POWER_FAIL; @@ -158,7 +158,7 @@ { uint8_t byte; int pwr_on=-1; - int nmi_option; + uint32_t nmi_option; /* IO APIC initialization */ i82801ca_enable_ioapic(dev); @@ -186,7 +186,7 @@ outb(byte, 0x61); byte = inb(0x70); nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -119,7 +119,7 @@ { uint8_t byte; int pwr_on=-1; - int nmi_option; + uint32_t nmi_option; /* IO APIC initialization */ i82801dbm_enable_ioapic(dev); @@ -159,7 +159,7 @@ outb(byte, 0x61); byte = inb(0x70); nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -283,7 +283,7 @@ { uint8_t byte; uint32_t value; - int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* IO APIC initialization */ value = pci_read_config32(dev, 0xd0); @@ -303,7 +303,7 @@ /* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00); - get_option(&pwr_on, "power_on_after_fail"); + get_option("power_on_after_fail", &pwr_on); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -185,14 +185,14 @@ u8 reg8; u16 reg16; - int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - int nmi_option; + uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + uint32_t nmi_option; /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off */ - get_option(&pwr_on, "power_on_after_fail"); + get_option("power_on_after_fail", &pwr_on); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; if (pwr_on) { @@ -216,7 +216,7 @@ reg8 = inb(0x70); nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { printk_info ("NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -180,7 +180,7 @@ { uint8_t byte; int pwr_on = -1; - int nmi_option; + uint32_t nmi_option; /* power after power fail */ /* FIXME this doesn't work! */ @@ -199,7 +199,7 @@ byte = inb(0x70); nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte &= ~(1 << 7); /* Set NMI. */ outb(byte, 0x70); Modified: trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -38,12 +38,12 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max) { - int bus_100Mhz = 0; + uint32_t bus_100Mhz = 0; dev->link[0].dev = dev; dev->links = 1; - get_option(&bus_100Mhz, "pxhd_bus_speed_100"); + get_option("pxhd_bus_speed_100", &bus_100Mhz); if(bus_100Mhz) { uint16_t word; @@ -66,7 +66,7 @@ uint32_t dword; uint16_t word; uint8_t byte; - int nmi_option; + uint32_t nmi_option; /* Bridge control ISA enable */ pci_write_config8(dev, 0x3e, 0x07); @@ -115,7 +115,7 @@ /* NMI enable */ nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if(nmi_option) { dword = pci_read_config32(dev, 0x44); dword |= (1<<0); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -179,7 +179,7 @@ static void lpc_init(device_t dev) { uint8_t byte, byte_old; - int on, nmi_option; + uint32_t on, nmi_option; lpc_common_init(dev); @@ -199,7 +199,7 @@ /* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); + get_option("power_on_after_fail", &on); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) @@ -209,7 +209,7 @@ /* Throttle the CPU speed down for testing. */ on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); + get_option("slow_cpu", &on); if (on) { uint16_t pm10_bar; uint32_t dword; @@ -238,7 +238,7 @@ byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte &= ~(1 << 7); /* Set NMI. */ } else { Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -170,8 +170,8 @@ { uint8_t byte; uint8_t byte_old; - int on; - int nmi_option; + uint32_t on; + uint32_t nmi_option; lpc_common_init(dev, 1); @@ -184,7 +184,7 @@ #if 1 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); + get_option("power_on_after_fail", &on); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -195,7 +195,7 @@ #endif /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); + get_option("slow_cpu", &on); if(on) { uint16_t pm10_bar; uint32_t dword; @@ -225,7 +225,7 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -167,8 +167,8 @@ { uint8_t byte; uint8_t byte_old; - int on; - int nmi_option; + uint32_t on; + uint32_t nmi_option; printk_debug("LPC_INIT -------->\n"); init_pc_keyboard(0x60, 0x64, 0); @@ -180,7 +180,7 @@ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); + get_option("power_on_after_fail", &on); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -191,7 +191,7 @@ /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); + get_option("slow_cpu", &on); if(on) { uint16_t pm10_bar; uint32_t dword; @@ -213,7 +213,7 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + get_option("nmi", &nmi_option); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { Modified: trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -69,9 +69,9 @@ static void init_acpi(device_t dev) { uint8_t value = 0x20; - int power_on = 1; + uint32_t power_on = 1; - get_option(&power_on, "power_on_after_fail"); + get_option("power_on_after_fail", &power_on); pnp_enter_ext_func_mode(dev); pnp_write_index(dev->path.pnp.port, 7, 0x0a); value = pnp_read_config(dev, 0xe4); Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -52,9 +52,9 @@ static void init_acpi(device_t dev) { uint8_t value = 0x20; - int power_on = 1; + uint32_t power_on = 1; - get_option(&power_on, "power_on_after_fail"); + get_option("power_on_after_fail", &power_on); pnp_enter_ext_func_mode(dev); pnp_write_index(dev->path.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4); Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c =================================================================== --- trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-06-03 03:15:05 UTC (rev 4331) +++ trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-06-03 10:47:19 UTC (rev 4332) @@ -17,85 +17,52 @@ static unsigned char cmos_table[4096]; -/* This array is used to isolate bits that are to be changed in a byte */ -static unsigned char clip[9]={0,1,3,7,0x0f,0x1f,0x3f,0x7f,0xff}; - - /* This routine loops through the entried and tests if any of the fields overlap input entry_start = the memory pointer to the start of the entries. entry_end = the byte past the entries. output none if there is an overlap, the routine exits, other wise it returns. */ + void test_for_entry_overlaps(void *entry_start, void *entry_end) { - int ptr; char *cptr; - int buffer_bit_size; - int offset; - int byte; - int byte_length; - struct cmos_entries *ce; + struct cmos_entries *ce = NULL; unsigned char test[CMOS_IMAGE_BUFFER_SIZE]; - unsigned char set; + int i; - /* calculate the size of the cmos buffer in bits */ - buffer_bit_size=(CMOS_IMAGE_BUFFER_SIZE*8); - /* clear the temporary test buffer */ - for(ptr=0; ptr < CMOS_IMAGE_BUFFER_SIZE; ptr++) - test[ptr]=0; + memset(test, 0, CMOS_IMAGE_BUFFER_SIZE); - /* loop through each entry in the table testing for errors */ - for(cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) { - ce=(struct cmos_entries *)cptr; + for (cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) { + ce = (struct cmos_entries *)cptr; + + /* Only reserved space can be larger than 32bits */ + if ((ce->length > 32) && (ce->config != 'r')) { + fprintf(stderr, "Error: Entry %s is longer than" + " 32bits.\n", ce->name); + exit(1); + } + /* test if entry goes past the end of the buffer */ - if((ce->bit+ce->length)>buffer_bit_size) { - printf("Error - Entry %s start bit + length must be less than %d\n", - ce->name,buffer_bit_size); + if ((ce->bit + ce->length) > (CMOS_IMAGE_BUFFER_SIZE * 8)) { + fprintf(stderr, "Error: Entry %s exceeds CMOS" + " space.\n", ce->name); exit(1); } - byte=ce->bit/8; - offset=ce->bit%8; - byte_length=ce->length/8; - if(byte_length) { /* entry is 8 bits long or more */ - if(offset) { /* if 8 bits or more long, it must be byte aligned */ - printf("Error - Entry %s length over 8 must be byte aligned\n", - ce->name); + + /* see whether our bits were marked before */ + for (i = ce->bit; i < (ce->bit + ce->length); i++) + if (test[i / 8] & (0x01 << (i % 8))) { + printf("Error: Entry %s overlaps at bit %d.\n", + ce->name, i); exit(1); } - /* test if entries 8 or more in length are even bytes */ - if(ce->length%8){ - printf("Error - Entry %s length over 8 must be a multiple of 8\n", - ce->name); - exit(1); - } - /* test if any of the bits have been previously used */ - for(;byte_length;byte_length--,byte++) { - if(test[byte]) { - printf("Error - Entry %s uses same bits previously used\n", - ce->name); - exit(1); - } - test[byte]=clip[8]; /* set the bits defined in test */ - } - } else { - /* test if bits overlap byte boundaries */ - if(ce->length>(8-offset)) { - printf("Error - Entry %s length overlaps a byte boundry\n", - ce->name); - exit(1); - } - /* test for bits previously used */ - set=(clip[ce->length]<name); - exit(1); - } - test[byte]|=set; /* set the bits defined in test */ - } + + /* now mark our bits */ + for (i = ce->bit; i < (ce->bit + ce->length); i++) + test[i / 8] |= 0x01 << (i % 8); + } - return; } /* This routine displays the usage options */ @@ -136,48 +103,14 @@ return value; } -static int is_ident_digit(int c) -{ - int result; - switch(c) { - case '0': case '1': case '2': case '3': - case '4': case '5': case '6': case '7': - case '8': case '9': - result = 1; - break; - default: - result = 0; - break; - } - return result; -} - static int is_ident_nondigit(int c) { - int result; - switch(c) { - case 'A': case 'B': case 'C': case 'D': - case 'E': case 'F': case 'G': case 'H': - case 'I': case 'J': case 'K': case 'L': - case 'M': case 'N': case 'O': case 'P': - case 'Q': case 'R': case 'S': case 'T': - case 'U': case 'V': case 'W': case 'X': - case 'Y': case 'Z': - case 'a': case 'b': case 'c': case 'd': - case 'e': case 'f': case 'g': case 'h': - case 'i': case 'j': case 'k': case 'l': - case 'm': case 'n': case 'o': case 'p': - case 'q': case 'r': case 's': case 't': - case 'u': case 'v': case 'w': case 'x': - case 'y': case 'z': - case '_': - result = 1; - break; - default: - result = 0; - break; - } - return result; + if (((c >= 'A') && (c <='Z')) || + ((c >= 'a') && (c <='z')) || + (c == '_')) + return 1; + else + return 0; } static int is_ident(char *str) @@ -190,7 +123,7 @@ do { str++; ch = *str; - } while(ch && (is_ident_nondigit(ch) || (is_ident_digit(ch)))); + } while(ch && (is_ident_nondigit(ch) || isdigit(ch))); result = (ch == '\0'); } return result; @@ -383,7 +316,7 @@ c_enums->config_id=strtol(&line[ptr],(char**)NULL,10); for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++); for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++); - c_enums->value=strtol(&line[ptr],(char**)NULL,10); + c_enums->value = strtoul(&line[ptr],(char**)NULL,0); for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++); for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++); for(cnt=0;(line[ptr]!='\n')&&(cnt<31);ptr++,cnt++) From libv at skynet.be Wed Jun 3 13:04:04 2009 From: libv at skynet.be (Luc Verhaegen) Date: Wed, 3 Jun 2009 13:04:04 +0200 Subject: [coreboot] [Patch] CMOS: Add set_option and rework get_option. In-Reply-To: <20090529141407.GB13500@skynet.be> References: <20090529134428.GA13500@skynet.be> <20090529134809.22493.qmail@stuge.se> <20090529141407.GB13500@skynet.be> Message-ID: <20090603110404.GA28067@skynet.be> On Fri, May 29, 2009 at 04:14:07PM +0200, Luc Verhaegen wrote: > On Fri, May 29, 2009 at 03:48:09PM +0200, Peter Stuge wrote: > > > Acked-by: Peter Stuge > > That was mighty fast :) > > Since this changes "known" behaviour of cmos options, i would prefer at > least a second Ack though, especially since the above reasoning might > not be agreed with fully by all. Since no has provided a secondary ack since friday, i have committed this anyway. -> r4332. Luc Verhaegen. From info at coresystems.de Wed Jun 3 13:07:21 2009 From: info at coresystems.de (coreboot information) Date: Wed, 03 Jun 2009 13:07:21 +0200 Subject: [coreboot] build service results for r4332 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "libv" checked in revision 4332 to the coreboot repository. This caused the following changes: Change Log: CMOS: Add set_option and rework get_option. To ease some of my debugging pain on the unichrome, i decided i needed to move FB size selection into cmos, so i could test a size and then reset it to the default after loading this value so that the next reboot uses the (working) default again. This meant implementing set_option in parallel to get_option. get_option was then found to have inversed argument ordering (like outb) and passing char * and then depending on the cmos layout length, which made me feel quite uncomfortable. Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go. So all users of get_option now have their arguments inversed and switched from using ints to unsigned ints now. The way get_cmos_value was implemented forced us to not overlap byte and to have multibyte values be byte aligned. This logic is now adapted to do a full uint32_t read (when needed) at any offset and any length up to 32, and the shifting all happens inside an uint32_t as well. set_cmos_value was implemented similarly. Both routines have been extensively tested in a quick separate little program as it is not easy to get this stuff right. build_opt_tbl.c was altered to function correctly within these new parameters. The enum value retrieval has been changed strol(..., NULL, 10) to stroul(..., NULL, 0), so that we not only are able to use unsigned ints now but so that we also interprete hex values correctly. The 32bit limit gets imposed on all entries not marked reserved, an unused "user_data" field that appeared in a lot of cmos.layouts has been changed to reserved as well. Signed-off-by: Luc Verhaegen Acked-by: Peter Stuge Build Log: Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4332&device=986lcd-m&vendor=kontron&num=2 If something broke during this checkin please be a pain in libv's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From paulepanter at users.sourceforge.net Wed Jun 3 13:50:46 2009 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 03 Jun 2009 13:50:46 +0200 Subject: [coreboot] LinuxTag 2009 in Berlin, June 24-27 In-Reply-To: <49F8D6CD.9070008@gmx.net> References: <20090429221636.23865.qmail@stuge.se> <49F8D6CD.9070008@gmx.net> Message-ID: <1244029846.5947.59.camel@mattotaupa.wohnung.familie-menzel.net> Dear Peter and Carl-Daniel, Am Donnerstag, den 30.04.2009, 00:38 +0200 schrieb Carl-Daniel Hailfinger: > On 30.04.2009 00:16, Peter Stuge wrote: [?] > > If you have experience from our booths in the past maybe you can > > comment on what must be improved this time? > > > > Having someone who is living in Berlin at the booth was a definite > advantage in 2008. Make sure we have Paul and Pierre on board again. Sorry for replying this late. If you need a helping hand, I would like to give you one or two. Just drop me a message. [?] Bests, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: Dies ist ein digital signierter Nachrichtenteil URL: From svn at coreboot.org Wed Jun 3 13:53:54 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 13:53:54 +0200 Subject: [coreboot] [v2] r4333 - trunk/coreboot-v2/src/mainboard/kontron/986lcd-m Message-ID: Author: libv Date: 2009-06-03 13:53:54 +0200 (Wed, 03 Jun 2009) New Revision: 4333 Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout Log: kontron 986lcd_m: cmos.layout: mark boot_devices as reserved. The kontron 986lcd_m cmos.layout had a 512bit area claimed for "boot_devices". The changes to the cmos code no longer allow usage of values larger than 32bits. Since this option was completely unused, mark it as reserved. Fixes build after the get_option change (r4332).. Signed-off-by: Luc Verhaegen Acked-by: Luc Verhaegen Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout 2009-06-03 10:47:19 UTC (rev 4332) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout 2009-06-03 11:53:54 UTC (rev 4333) @@ -89,8 +89,8 @@ 409 1 e 1 power_on_after_fail #410 6 r 0 unused -# coreboot config options: bootloader -416 512 s 0 boot_devices +# coreboot config options: bootloader : unused -> reserved. +416 512 r 0 boot_devices #928 80 r 0 unused # coreboot config options: check sums From paulepanter at users.sourceforge.net Wed Jun 3 13:54:08 2009 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Wed, 03 Jun 2009 13:54:08 +0200 Subject: [coreboot] DIP8 SPI flashes In-Reply-To: <20090514115605.GA11677@skynet.be> References: <4A095B0B.7010201@assembler.cz> <20090514115605.GA11677@skynet.be> Message-ID: <1244030048.5947.61.camel@mattotaupa.wohnung.familie-menzel.net> Dear Rudolf, Am Donnerstag, den 14.05.2009, 13:56 +0200 schrieb Luc Verhaegen: > On Tue, May 12, 2009 at 01:18:35PM +0200, Rudolf Marek wrote: [?] > > Is someone interrested? Thank you for the offer. > If the M2V takes 1MB, then i'll take 2. If it is not too late yet, I would also take 2. Bests, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: Dies ist ein digital signierter Nachrichtenteil URL: From libv at skynet.be Wed Jun 3 14:01:12 2009 From: libv at skynet.be (Luc Verhaegen) Date: Wed, 3 Jun 2009 14:01:12 +0200 Subject: [coreboot] build service results for r4332 In-Reply-To: References: Message-ID: <20090603120112.GA28196@skynet.be> On Wed, Jun 03, 2009 at 01:07:21PM +0200, coreboot information wrote: > Dear coreboot readers! > > This is the automatic build system of coreboot. > > The developer "libv" checked in revision 4332 to > the coreboot repository. This caused the following > changes: > > Build Log: > Compilation of kontron:986lcd-m has been broken > See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4332&device=986lcd-m&vendor=kontron&num=2 Should be fixed with r4333. Luc Verhaegen. From info at coresystems.de Wed Jun 3 14:13:44 2009 From: info at coresystems.de (coreboot information) Date: Wed, 03 Jun 2009 14:13:44 +0200 Subject: [coreboot] build service results for r4333 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "libv" checked in revision 4333 to the coreboot repository. This caused the following changes: Change Log: kontron 986lcd_m: cmos.layout: mark boot_devices as reserved. The kontron 986lcd_m cmos.layout had a 512bit area claimed for "boot_devices". The changes to the cmos code no longer allow usage of values larger than 32bits. Since this option was completely unused, mark it as reserved. Fixes build after the get_option change (r4332).. Signed-off-by: Luc Verhaegen Acked-by: Luc Verhaegen Build Log: Compilation of kontron:986lcd-m has been fixed If something broke during this checkin please be a pain in libv's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Wed Jun 3 16:19:20 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 16:19:20 +0200 Subject: [coreboot] [v2] r4334 - trunk/coreboot-v2/src/mainboard/kontron/986lcd-m Message-ID: Author: libv Date: 2009-06-03 16:19:20 +0200 (Wed, 03 Jun 2009) New Revision: 4334 Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout Log: Revert "kontron 986lcd_m: cmos.layout: mark boot_devices as reserved." This reverts commit c03527377db5951f0d3228e2a93b4c57dd81b8ec. Stepan pointed out that 's' means string, and that therefor strings do exist. Marking this as reserved breaks some payloads. Signed-off-by: Luc Verhaegen Acked-by: Luc Verhaegen Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout 2009-06-03 11:53:54 UTC (rev 4333) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) @@ -89,8 +89,8 @@ 409 1 e 1 power_on_after_fail #410 6 r 0 unused -# coreboot config options: bootloader : unused -> reserved. -416 512 r 0 boot_devices +# coreboot config options: bootloader +416 512 s 0 boot_devices #928 80 r 0 unused # coreboot config options: check sums From svn at coreboot.org Wed Jun 3 16:19:34 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 16:19:34 +0200 Subject: [coreboot] [v2] r4335 - in trunk/coreboot-v2: src/console src/cpu/amd/dualcore src/cpu/amd/model_fxx src/cpu/amd/quadcore src/cpu/intel/hyperthreading src/include/console src/include/pc80 src/mainboard/amd/dbm690t src/mainboard/amd/pistachio src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/broadcom/blast src/mainboard/dell/s1850 src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli src/mainboard/hp/dl145_g3 src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/intel/jarrell src/mainboard/iwill/dk8_htx src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x src/mainboard/msi/ms7135 src/mainboard/msi/ms7260 src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/newisys/khepri src/mainboard/nvidia/l1_2pvv src/mainboard/sunw/ultra40 src/mainboard/supermicro/h8dme src/mainboard/supermicro/h8dmr src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion/tim8690 src/mainboard/tyan/s2735 src/mainboard/tyan/s2850 src/mainboard/tyan/s2875 src/mainboard/tyan/s2880 src/mainboard/tyan/s2881 src/mainboard/tyan/s2882 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/mainboard/tyan/s2912 src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880 src/mainboard/tyan/s4882 src/northbridge/amd/amdfam10 src/northbridge/amd/amdk8 src/pc80 src/southbridge/amd/amd8111 src/southbridge/amd/amd8131 src/southbridge/amd/sb600 src/southbridge/broadcom/bcm5785 src/southbridge/intel/esb6300 src/southbridge/intel/i3100 src/southbridge/intel/i82801ca src/southbridge/intel/i82801dbm src/southbridge/intel/i82801er src/southbridge/intel/i82801gx src/southbridge/intel/i82801xx src/southbridge/intel/pxhd src/southbridge/nvidia/ck804 src/southbridge/nvidia/mcp55 src/southbridge/sis/sis966 src/superio/winbond/w83627ehg src/superio/winbond/w83627hf util/options Message-ID: Author: libv Date: 2009-06-03 16:19:33 +0200 (Wed, 03 Jun 2009) New Revision: 4335 Modified: trunk/coreboot-v2/src/console/console.c trunk/coreboot-v2/src/console/printk.c trunk/coreboot-v2/src/console/uart8250_console.c trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c trunk/coreboot-v2/src/include/console/console.h trunk/coreboot-v2/src/include/pc80/mc146818rtc.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/pc80/mc146818rtc.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c trunk/coreboot-v2/util/options/build_opt_tbl.c Log: Revert "CMOS: Add set_option and rework get_option." This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660. Stepan pointed out that "s" means string, which makes the following statement in this commit message invalid: "Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go." Signed-off-by: Luc Verhaegen Acked-by: Luc Verhaegen Modified: trunk/coreboot-v2/src/console/console.c =================================================================== --- trunk/coreboot-v2/src/console/console.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/console/console.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -14,10 +14,9 @@ void console_init(void) { struct console_driver *driver; - - if (get_option("debug_level", &console_loglevel)) - console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; - + if(get_option(&console_loglevel, "debug_level")) + console_loglevel=DEFAULT_CONSOLE_LOGLEVEL; + for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; Modified: trunk/coreboot-v2/src/console/printk.c =================================================================== --- trunk/coreboot-v2/src/console/printk.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/console/printk.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -9,9 +9,18 @@ #include #include +/* printk's without a loglevel use this.. */ +#define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */ + +/* We show everything that is MORE important than this.. */ +#define MINIMUM_CONSOLE_LOGLEVEL 1 /* Minimum loglevel we let people use */ + /* Keep together for sysctl support */ -unsigned int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL; +int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL; +int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; void display(char*); extern int vtxprintf(void (*)(unsigned char), const char *, va_list); Modified: trunk/coreboot-v2/src/console/uart8250_console.c =================================================================== --- trunk/coreboot-v2/src/console/uart8250_console.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/console/uart8250_console.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -29,10 +29,10 @@ static void ttyS0_init(void) { static const unsigned char div[8]={1,2,3,6,12,24,48,96}; - unsigned int b_index=0; + int b_index=0; unsigned int divisor=TTYS0_DIV; - if(!get_option("baud_rate", &b_index)) { + if(get_option(&b_index,"baud_rate")==0) { divisor=div[b_index]; } uart8250_init(TTYS0_BASE, divisor, TTYS0_LCS); Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -14,7 +14,7 @@ #include static int first_time = 1; -static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS; +static int disable_siblings = !CONFIG_LOGICAL_CPUS; #include "dualcore_id.c" @@ -62,7 +62,7 @@ unsigned nb_cfg_54; int bsp_apic_id = lapicid(); // bsp apicid - get_option("dual_core", &disable_siblings); + get_option(&disable_siblings, "dual_core"); //get the nodes number dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); @@ -127,7 +127,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - get_option("dual_core", &disable_siblings); + get_option(&disable_siblings, "dual_core"); } result = cpuid(0x80000008); /* See how many sibling cpus we have */ Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -248,7 +248,7 @@ struct mtrr_state mtrr_state; device_t f1_dev, f2_dev, f3_dev; - uint32_t enable_scrubbing; + int enable_scrubbing; uint32_t dcl; f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); @@ -266,7 +266,7 @@ /* See if we scrubbing should be enabled */ enable_scrubbing = 1; - get_option("hw_scrubber", &enable_scrubbing); + get_option(&enable_scrubbing, "hw_scrubber"); /* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) { Modified: trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -82,7 +82,7 @@ u32 disable_siblings = !CONFIG_LOGICAL_CPUS; - get_option("quad_core", &disable_siblings); + get_option(&disable_siblings, "quad_core"); siblings = get_max_siblings(sysconf.nodes); Modified: trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -7,7 +7,7 @@ #include static int first_time = 1; -static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS; +static int disable_siblings = !CONFIG_LOGICAL_CPUS; void intel_sibling_init(device_t cpu) { @@ -17,7 +17,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - get_option("hyper_threading", &disable_siblings); + get_option(&disable_siblings, "hyper_threading"); } result = cpuid(1); /* Is hyperthreading supported */ Modified: trunk/coreboot-v2/src/include/console/console.h =================================================================== --- trunk/coreboot-v2/src/include/console/console.h 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/include/console/console.h 2009-06-03 14:19:33 UTC (rev 4335) @@ -26,7 +26,7 @@ extern struct console_driver console_drivers[]; extern struct console_driver econsole_drivers[]; -extern unsigned int console_loglevel; +extern int console_loglevel; int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) Modified: trunk/coreboot-v2/src/include/pc80/mc146818rtc.h =================================================================== --- trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-06-03 14:19:33 UTC (rev 4335) @@ -94,9 +94,11 @@ #if !defined(ASSEMBLY) void rtc_init(int invalid); - -int get_option(char *name, unsigned int *value); -int set_option(char *name, unsigned int value); +#if USE_OPTION_TABLE == 1 +int get_option(void *dest, char *name); +#else +static inline int get_option(void *dest, char *name) { return -2; } #endif +#endif #endif /* PC80_MC146818RTC_H */ Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -42,7 +42,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu - 728 256 r 0 user_data + 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -39,7 +39,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -65,7 +65,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -41,7 +41,7 @@ 432 8 h 0 boot_countdown #440 4 e 9 slow_cpu 444 1 e 1 nmi -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ } iommu = 1; - get_option("iommu", &iommu); + get_option(&iommu, "iommu"); if (iommu) { /* Add a Gart apeture resource */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -1258,7 +1258,7 @@ unsigned nb_cfg_54; unsigned siblings; int cores_found; - uint32_t disable_siblings; + int disable_siblings; unsigned ApicIdCoreIdSize; nb_cfg_54 = 0; @@ -1271,7 +1271,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option("quad_core", &disable_siblings); + get_option(&disable_siblings, "quad_core"); #endif // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -48,7 +48,7 @@ } iommu = 1; - get_option("iommu", &iommu); + get_option(&iommu, "iommu"); if (iommu) { /* Add a Gart apeture resource */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -1177,7 +1177,7 @@ unsigned nb_cfg_54; unsigned siblings; int e0_later_single_core; - uint32_t disable_siblings; + int disable_siblings; nb_cfg_54 = 0; sysconf.enabled_apic_ext_id = 0; @@ -1190,7 +1190,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option("dual_core", &disable_siblings); + get_option(&disable_siblings, "dual_core"); #endif // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0) Modified: trunk/coreboot-v2/src/pc80/mc146818rtc.c =================================================================== --- trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -197,69 +197,41 @@ #if USE_OPTION_TABLE == 1 -/* - * Functions to save/return values stored in the 256byte cmos. - * - * To be able to use space maximally we want to only store as many bits as - * needed, and not be limited by byte boundaries. We therefor clamp the size - * down to an unsigned int. Since the values that we are allowed to touch are - * either an enum or a hexadecimal value, this size should suit most purposes. - * - * These two functions are doing bitshifting, and are therefor a bit - * nontrivial. To understand these operations, first read the ones outside the - * loop. The ones inside the loop are just adding i to the same calculations, - * with the shift twice inverted, as negative shifts aren't nice. - */ -static unsigned int -get_cmos_value(int bit, int length) +/* This routine returns the value of the requested bits + input bit = bit count from the beginning of the cmos image + length = number of bits to include in the value + ret = a character pointer to where the value is to be returned + output the value placed in ret + returns 0 = successful, -1 = an error occurred +*/ +static int get_cmos_value(unsigned long bit, unsigned long length, void *vret) { - unsigned int tmp; - int i; + unsigned char *ret; + unsigned long byte,byte_bit; + unsigned long i; + unsigned char uchar; - /* negative left shift --> right shift */ - tmp = cmos_read(bit / 8) >> (bit % 8); - - for (i = 1; (8 * i) < ((bit % 8) + length); i++) - tmp |= cmos_read((bit / 8) + i) << ((8 * i) - (bit % 8)); - - /* 1 << 32 - 1 isn't cool inside an int */ - if (length != 32) - tmp &= (1 << length) - 1; - - return tmp; -} - -static void -set_cmos_value(int bit, int length, unsigned int value) -{ - unsigned int mask; - unsigned char cmos; - int i; - - /* 1 << 32 - 1 isn't cool inside an int */ - if (length != 32) - mask = (1 << length) - 1; - else - mask = -1; - - value &= mask; - - /* negative right shifts --> left shifts */ - cmos = cmos_read(bit / 8); - cmos &= ~(mask << (bit % 8)); - cmos |= value << (bit % 8); - cmos_write(cmos, bit / 8); - - for (i = 1; (8 * i) < ((bit % 8) + length); i++) { - cmos = cmos_read((bit / 8) + i); - cmos &= ~(mask >> ((8 * i) - (bit % 8))); - cmos |= value >> ((8 * i) - (bit % 8)); - cmos_write(cmos, (bit / 8) + i); + /* The table is checked when it is built to ensure all + values are valid. */ + ret = vret; + byte=bit/8; /* find the byte where the data starts */ + byte_bit=bit%8; /* find the bit in the byte where the data starts */ + if(length<9) { /* one byte or less */ + uchar = cmos_read(byte); /* load the byte */ + uchar >>= byte_bit; /* shift the bits to byte align */ + /* clear unspecified bits */ + ret[0] = uchar & ((1 << length) -1); } + else { /* more that one byte so transfer the whole bytes */ + for(i=0;length;i++,length-=8,byte++) { + /* load the byte */ + ret[i]=cmos_read(byte); + } + } + return 0; } -int -get_option(char *name, unsigned int *value) +int get_option(void *dest, char *name) { extern struct cmos_option_table option_table; struct cmos_option_table *ct; @@ -269,7 +241,7 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - + /* find the requested entry record */ ct=&option_table; ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length); @@ -284,72 +256,12 @@ printk_err("ERROR: No cmos option '%s'\n", name); return(-2); } - - if (ce->length > 32) { - printk_err("ERROR: cmos option '%s' is too large.\n", name); - return -3; - } - - - *value = get_cmos_value(ce->bit, ce->length); - + + if(get_cmos_value(ce->bit, ce->length, dest)) + return(-3); if(!rtc_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC)) + LB_CKS_RANGE_END,LB_CKS_LOC)) return(-4); return(0); } - -int -set_option(char *name, unsigned int value) -{ - extern struct cmos_option_table option_table; - struct cmos_option_table *ct; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - - /* find the requested entry record */ - ct = &option_table; - ce = (struct cmos_entries*) ((unsigned char *) ct + ct->header_length); - - for(;ce->tag==LB_TAG_OPTION; - ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) { - if (memcmp(ce->name, name, namelen) == 0) { - found=1; - break; - } - } - - if (!found) { - printk_err("ERROR: Unknown cmos option '%s'\n", name); - return(-2); - } - - if (ce->length > 32) { - printk_err("ERROR: cmos option '%s' is too large.\n", name); - return -3; - } - - set_cmos_value(ce->bit, ce->length, value); - - /* We should not update the checksum here. */ - - return 0; -} -#else -int -get_option(char *name, unsigned int *value) -{ - return -2; -} - -int -set_option(char *name, unsigned int value) -{ - return -2; -} - #endif /* USE_OPTION_TABLE */ Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -76,7 +76,7 @@ uint16_t word; uint16_t pm10_bar; uint32_t dword; - uint32_t on; + int on; #if 0 printk_debug("ACPI: disabling NMI watchdog.. "); @@ -113,7 +113,7 @@ /* power on after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -130,7 +130,7 @@ /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if(on) { pm10_bar = (pci_read_config16(dev, 0x58)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -108,7 +108,7 @@ static void lpc_init(struct device *dev) { uint8_t byte; - uint32_t nmi_option; + int nmi_option; /* IO APIC initialization */ byte = pci_read_config8(dev, 0x4B); @@ -142,7 +142,7 @@ byte |= (1 << 6); /* clear LPCERR */ pci_write_config8(dev, 0x40, byte); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte |= (1 << 7); /* set NMI */ pci_write_config8(dev, 0x40, byte); Modified: trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -278,7 +278,7 @@ uint32_t dword; uint16_t word; uint8_t byte; - uint32_t nmi_option; + int nmi_option; /* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); @@ -323,7 +323,7 @@ /* NMI enable */ nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if(nmi_option) { dword = pci_read_config32(dev, 0x44); dword |= (1<<0); Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -165,7 +165,7 @@ /* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pm_ioread(0x74); byte &= ~0x03; if (on) { @@ -226,7 +226,7 @@ byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ printk_info("++++++++++set NMI+++++\n"); Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -23,7 +23,7 @@ { uint8_t byte; uint8_t byte_old; - uint32_t nmi_option; + int nmi_option; uint32_t dword; @@ -31,8 +31,8 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); - if (nmi_option) { + get_option(&nmi_option, "nmi"); + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -277,7 +277,7 @@ { uint8_t byte; uint32_t value; - uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL; + int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL; /* sata settings */ pci_write_config32(dev, 0x58, 0x00001181); @@ -326,7 +326,7 @@ esb6300_enable_lpc(dev); - get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -297,7 +297,7 @@ static void lpc_init(struct device *dev) { u8 byte; - uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL; + int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL; setup_ioapic(dev); @@ -306,7 +306,7 @@ i3100_enable_serial_irqs(dev); - get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -88,7 +88,7 @@ { uint32_t dword; int rtc_failed; - uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3); rtc_failed = pmcon3 & RTC_BATTERY_DEAD; @@ -99,7 +99,7 @@ pmcon3 &= ~RTC_POWER_FAILED; } - get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); pmcon3 &= ~SLEEP_AFTER_POWER_FAIL; if (!pwr_on) { pmcon3 |= SLEEP_AFTER_POWER_FAIL; @@ -158,7 +158,7 @@ { uint8_t byte; int pwr_on=-1; - uint32_t nmi_option; + int nmi_option; /* IO APIC initialization */ i82801ca_enable_ioapic(dev); @@ -186,7 +186,7 @@ outb(byte, 0x61); byte = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -119,7 +119,7 @@ { uint8_t byte; int pwr_on=-1; - uint32_t nmi_option; + int nmi_option; /* IO APIC initialization */ i82801dbm_enable_ioapic(dev); @@ -159,7 +159,7 @@ outb(byte, 0x61); byte = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -283,7 +283,7 @@ { uint8_t byte; uint32_t value; - uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* IO APIC initialization */ value = pci_read_config32(dev, 0xd0); @@ -303,7 +303,7 @@ /* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00); - get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -185,14 +185,14 @@ u8 reg8; u16 reg16; - uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - uint32_t nmi_option; + int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option; /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off */ - get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; if (pwr_on) { @@ -216,7 +216,7 @@ reg8 = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { printk_info ("NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -180,7 +180,7 @@ { uint8_t byte; int pwr_on = -1; - uint32_t nmi_option; + int nmi_option; /* power after power fail */ /* FIXME this doesn't work! */ @@ -199,7 +199,7 @@ byte = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* Set NMI. */ outb(byte, 0x70); Modified: trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -38,12 +38,12 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max) { - uint32_t bus_100Mhz = 0; + int bus_100Mhz = 0; dev->link[0].dev = dev; dev->links = 1; - get_option("pxhd_bus_speed_100", &bus_100Mhz); + get_option(&bus_100Mhz, "pxhd_bus_speed_100"); if(bus_100Mhz) { uint16_t word; @@ -66,7 +66,7 @@ uint32_t dword; uint16_t word; uint8_t byte; - uint32_t nmi_option; + int nmi_option; /* Bridge control ISA enable */ pci_write_config8(dev, 0x3e, 0x07); @@ -115,7 +115,7 @@ /* NMI enable */ nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if(nmi_option) { dword = pci_read_config32(dev, 0x44); dword |= (1<<0); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -179,7 +179,7 @@ static void lpc_init(device_t dev) { uint8_t byte, byte_old; - uint32_t on, nmi_option; + int on, nmi_option; lpc_common_init(dev); @@ -199,7 +199,7 @@ /* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) @@ -209,7 +209,7 @@ /* Throttle the CPU speed down for testing. */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if (on) { uint16_t pm10_bar; uint32_t dword; @@ -238,7 +238,7 @@ byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* Set NMI. */ } else { Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -170,8 +170,8 @@ { uint8_t byte; uint8_t byte_old; - uint32_t on; - uint32_t nmi_option; + int on; + int nmi_option; lpc_common_init(dev, 1); @@ -184,7 +184,7 @@ #if 1 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -195,7 +195,7 @@ #endif /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if(on) { uint16_t pm10_bar; uint32_t dword; @@ -225,7 +225,7 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -167,8 +167,8 @@ { uint8_t byte; uint8_t byte_old; - uint32_t on; - uint32_t nmi_option; + int on; + int nmi_option; printk_debug("LPC_INIT -------->\n"); init_pc_keyboard(0x60, 0x64, 0); @@ -180,7 +180,7 @@ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -191,7 +191,7 @@ /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if(on) { uint16_t pm10_bar; uint32_t dword; @@ -213,7 +213,7 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { Modified: trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -69,9 +69,9 @@ static void init_acpi(device_t dev) { uint8_t value = 0x20; - uint32_t power_on = 1; + int power_on = 1; - get_option("power_on_after_fail", &power_on); + get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); pnp_write_index(dev->path.pnp.port, 7, 0x0a); value = pnp_read_config(dev, 0xe4); Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -52,9 +52,9 @@ static void init_acpi(device_t dev) { uint8_t value = 0x20; - uint32_t power_on = 1; + int power_on = 1; - get_option("power_on_after_fail", &power_on); + get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); pnp_write_index(dev->path.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4); Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c =================================================================== --- trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -17,52 +17,85 @@ static unsigned char cmos_table[4096]; +/* This array is used to isolate bits that are to be changed in a byte */ +static unsigned char clip[9]={0,1,3,7,0x0f,0x1f,0x3f,0x7f,0xff}; + + /* This routine loops through the entried and tests if any of the fields overlap input entry_start = the memory pointer to the start of the entries. entry_end = the byte past the entries. output none if there is an overlap, the routine exits, other wise it returns. */ - void test_for_entry_overlaps(void *entry_start, void *entry_end) { + int ptr; char *cptr; - struct cmos_entries *ce = NULL; + int buffer_bit_size; + int offset; + int byte; + int byte_length; + struct cmos_entries *ce; unsigned char test[CMOS_IMAGE_BUFFER_SIZE]; - int i; + unsigned char set; - memset(test, 0, CMOS_IMAGE_BUFFER_SIZE); + /* calculate the size of the cmos buffer in bits */ + buffer_bit_size=(CMOS_IMAGE_BUFFER_SIZE*8); + /* clear the temporary test buffer */ + for(ptr=0; ptr < CMOS_IMAGE_BUFFER_SIZE; ptr++) + test[ptr]=0; - for (cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) { - ce = (struct cmos_entries *)cptr; - - /* Only reserved space can be larger than 32bits */ - if ((ce->length > 32) && (ce->config != 'r')) { - fprintf(stderr, "Error: Entry %s is longer than" - " 32bits.\n", ce->name); - exit(1); - } - + /* loop through each entry in the table testing for errors */ + for(cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) { + ce=(struct cmos_entries *)cptr; /* test if entry goes past the end of the buffer */ - if ((ce->bit + ce->length) > (CMOS_IMAGE_BUFFER_SIZE * 8)) { - fprintf(stderr, "Error: Entry %s exceeds CMOS" - " space.\n", ce->name); + if((ce->bit+ce->length)>buffer_bit_size) { + printf("Error - Entry %s start bit + length must be less than %d\n", + ce->name,buffer_bit_size); exit(1); } - - /* see whether our bits were marked before */ - for (i = ce->bit; i < (ce->bit + ce->length); i++) - if (test[i / 8] & (0x01 << (i % 8))) { - printf("Error: Entry %s overlaps at bit %d.\n", - ce->name, i); + byte=ce->bit/8; + offset=ce->bit%8; + byte_length=ce->length/8; + if(byte_length) { /* entry is 8 bits long or more */ + if(offset) { /* if 8 bits or more long, it must be byte aligned */ + printf("Error - Entry %s length over 8 must be byte aligned\n", + ce->name); exit(1); } - - /* now mark our bits */ - for (i = ce->bit; i < (ce->bit + ce->length); i++) - test[i / 8] |= 0x01 << (i % 8); - + /* test if entries 8 or more in length are even bytes */ + if(ce->length%8){ + printf("Error - Entry %s length over 8 must be a multiple of 8\n", + ce->name); + exit(1); + } + /* test if any of the bits have been previously used */ + for(;byte_length;byte_length--,byte++) { + if(test[byte]) { + printf("Error - Entry %s uses same bits previously used\n", + ce->name); + exit(1); + } + test[byte]=clip[8]; /* set the bits defined in test */ + } + } else { + /* test if bits overlap byte boundaries */ + if(ce->length>(8-offset)) { + printf("Error - Entry %s length overlaps a byte boundry\n", + ce->name); + exit(1); + } + /* test for bits previously used */ + set=(clip[ce->length]<name); + exit(1); + } + test[byte]|=set; /* set the bits defined in test */ + } } + return; } /* This routine displays the usage options */ @@ -103,14 +136,48 @@ return value; } +static int is_ident_digit(int c) +{ + int result; + switch(c) { + case '0': case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + case '8': case '9': + result = 1; + break; + default: + result = 0; + break; + } + return result; +} + static int is_ident_nondigit(int c) { - if (((c >= 'A') && (c <='Z')) || - ((c >= 'a') && (c <='z')) || - (c == '_')) - return 1; - else - return 0; + int result; + switch(c) { + case 'A': case 'B': case 'C': case 'D': + case 'E': case 'F': case 'G': case 'H': + case 'I': case 'J': case 'K': case 'L': + case 'M': case 'N': case 'O': case 'P': + case 'Q': case 'R': case 'S': case 'T': + case 'U': case 'V': case 'W': case 'X': + case 'Y': case 'Z': + case 'a': case 'b': case 'c': case 'd': + case 'e': case 'f': case 'g': case 'h': + case 'i': case 'j': case 'k': case 'l': + case 'm': case 'n': case 'o': case 'p': + case 'q': case 'r': case 's': case 't': + case 'u': case 'v': case 'w': case 'x': + case 'y': case 'z': + case '_': + result = 1; + break; + default: + result = 0; + break; + } + return result; } static int is_ident(char *str) @@ -123,7 +190,7 @@ do { str++; ch = *str; - } while(ch && (is_ident_nondigit(ch) || isdigit(ch))); + } while(ch && (is_ident_nondigit(ch) || (is_ident_digit(ch)))); result = (ch == '\0'); } return result; @@ -316,7 +383,7 @@ c_enums->config_id=strtol(&line[ptr],(char**)NULL,10); for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++); for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++); - c_enums->value = strtoul(&line[ptr],(char**)NULL,0); + c_enums->value=strtol(&line[ptr],(char**)NULL,10); for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++); for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++); for(cnt=0;(line[ptr]!='\n')&&(cnt<31);ptr++,cnt++) From info at coresystems.de Wed Jun 3 16:38:53 2009 From: info at coresystems.de (coreboot information) Date: Wed, 03 Jun 2009 16:38:53 +0200 Subject: [coreboot] build service results for r4334 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "libv" checked in revision 4334 to the coreboot repository. This caused the following changes: Change Log: Revert "kontron 986lcd_m: cmos.layout: mark boot_devices as reserved." This reverts commit c03527377db5951f0d3228e2a93b4c57dd81b8ec. Stepan pointed out that 's' means string, and that therefor strings do exist. Marking this as reserved breaks some payloads. Signed-off-by: Luc Verhaegen Acked-by: Luc Verhaegen Build Log: Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4334&device=986lcd-m&vendor=kontron&num=2 If something broke during this checkin please be a pain in libv's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Wed Jun 3 16:46:22 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 16:46:22 +0200 Subject: [coreboot] [flashrom] r569 - trunk Message-ID: Author: hailfinger Date: 2009-06-03 16:46:22 +0200 (Wed, 03 Jun 2009) New Revision: 569 Modified: trunk/flash.h trunk/flashchips.c trunk/jedec.c Log: Add probe_timing information (int uS value). This eliminates the conflicting delay requirements for old and new chips with the same probing sequence. Signed-Off-by: Maciej Pijanka Acked-by: Carl-Daniel Hailfinger Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-03 07:50:39 UTC (rev 568) +++ trunk/flash.h 2009-06-03 14:46:22 UTC (rev 569) @@ -155,6 +155,9 @@ uint32_t tested; int (*probe) (struct flashchip *flash); + + /* Delay after "enter/exit ID mode" commands in microseconds. */ + int probe_timing; int (*erase) (struct flashchip *flash); int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf); @@ -182,6 +185,16 @@ #define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | TEST_BAD_ERASE | TEST_BAD_WRITE) #define TEST_BAD_MASK 0xf0 +/* Timing used in probe routines. ZERO is -2 to differentiate between an unset + * field and zero delay. + * + * SPI devices will always have zero delay and ignore this field. + */ +#define TIMING_FIXME -1 +/* this is intentionally same value as fixme */ +#define TIMING_IGNORED -1 +#define TIMING_ZERO -2 + extern struct flashchip flashchips[]; struct penable { Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-03 07:50:39 UTC (rev 568) +++ trunk/flashchips.c 2009-06-03 14:46:22 UTC (rev 569) @@ -32,9 +32,10 @@ struct flashchip flashchips[] = { /* Vendor, Chip, Vendor ID, Chip ID, + * Bus Type, * Total size (kB), Page size (B), * Test status, - * Probe function, Erase function, Write function, Read function + * Probe function, Probe function timing argument, Erase function, Write function, Read function */ { @@ -47,6 +48,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_en29f002a, .read = read_memmapped, @@ -62,6 +64,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_en29f002a, .read = read_memmapped, @@ -77,6 +80,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_29f040b, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ .erase = erase_29f040b, .write = write_29f040b, .read = read_memmapped, @@ -92,6 +96,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_29f040b, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ .erase = erase_29f040b, .write = write_29f040b, .read = read_memmapped, @@ -107,6 +112,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_29f040b, .write = write_29f040b, .read = read_memmapped, @@ -122,6 +128,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_29f040b, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ .erase = erase_29f040b, .write = write_29f040b, .read = read_memmapped, @@ -137,6 +144,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_29f040b, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ .erase = erase_29f040b, .write = write_29f040b, .read = read_memmapped, @@ -152,6 +160,7 @@ .page_size = 128, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -407,7 +416,8 @@ .total_size = 64, .page_size = 128, .tested = TEST_OK_PREW, - .probe = probe_jedec, + .probe = probe_jedec, + .probe_timing = 10000, /* 10mS, Enter=Exec */ .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -424,6 +434,7 @@ .page_size = 128, .tested = TEST_OK_PRE, .probe = probe_jedec, + .probe_timing = 10000, /* 10mS, Enter=Exec */ .erase = erase_chip_jedec, .write = write_jedec, /* FIXME */ .read = read_memmapped, @@ -439,6 +450,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -454,6 +466,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -604,6 +617,7 @@ .page_size = 64, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -619,6 +633,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, /* doc1008.pdf dont says anything about probe timing */ .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -634,6 +649,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, /* doc1008.pdf dont says anything about probe timing */ .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -664,6 +680,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_29f002, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, .write = write_29f002, .read = read_memmapped, @@ -679,6 +696,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_29f002, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, .write = write_29f002, .read = read_memmapped, @@ -694,6 +712,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PR, .probe = probe_29f040b, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ .erase = erase_29f040b, .write = write_29f040b, .read = read_memmapped, @@ -709,6 +728,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_49fl00x, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ .erase = erase_49fl00x, .write = write_49fl00x, .read = read_memmapped, @@ -724,6 +744,7 @@ .page_size = 4096, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -739,6 +760,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_en29f002a, .read = read_memmapped, @@ -754,6 +776,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_en29f002a, .read = read_memmapped, @@ -769,6 +792,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = NULL, .write = NULL, .read = read_memmapped, @@ -784,6 +808,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = NULL, .write = NULL, .read = read_memmapped, @@ -799,6 +824,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_m29f400bt, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (m29f400bt.c) */ .erase = erase_m29f400bt, .write = write_coreboot_m29f400bt, .read = read_memmapped, @@ -814,6 +840,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_m29f400bt, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (m29f400bt.c) */ .erase = erase_m29f400bt, .write = write_coreboot_m29f400bt, .read = read_memmapped, @@ -829,6 +856,7 @@ .page_size = 128 * 1024, /* 8k + 2x4k + 112k */ .tested = TEST_BAD_ERASE|TEST_BAD_WRITE, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = NULL, .write = NULL, .read = read_memmapped, @@ -844,6 +872,7 @@ .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ .tested = TEST_OK_PR|TEST_BAD_ERASE|TEST_BAD_WRITE, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = NULL, .write = NULL, .read = read_memmapped, @@ -1054,6 +1083,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_29f002, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, .write = write_29f002, .read = read_memmapped, @@ -1069,6 +1099,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_29f002, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, .write = write_29f002, .read = read_memmapped, @@ -1084,6 +1115,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PR, .probe = probe_29f002, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, .write = write_29f002, .read = read_memmapped, @@ -1264,6 +1296,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1279,6 +1312,7 @@ .page_size = 16 * 1024, .tested = TEST_OK_PREW, .probe = probe_49fl00x, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ .erase = erase_49fl00x, .write = write_49fl00x, .read = read_memmapped, @@ -1294,6 +1328,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_49fl00x, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ .erase = erase_49fl00x, .write = write_49fl00x, .read = read_memmapped, @@ -1309,6 +1344,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_lhf00l04, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sharplhf00l04.c) */ .erase = erase_lhf00l04, .write = write_lhf00l04, .read = read_memmapped, @@ -1429,6 +1465,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_28sf040, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst28sf040.c) */ .erase = erase_28sf040, .write = write_28sf040, .read = read_memmapped, @@ -1444,6 +1481,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -1459,6 +1497,7 @@ .page_size = 128, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -1474,6 +1513,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -1489,6 +1529,7 @@ .page_size = 128, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -1504,6 +1545,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1519,6 +1561,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1534,6 +1577,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1549,6 +1593,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1564,6 +1609,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1579,6 +1625,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1594,6 +1641,7 @@ .page_size = 4096, .tested = TEST_OK_PROBE, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1609,6 +1657,7 @@ .page_size = 4096, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -1624,6 +1673,7 @@ .page_size = 16 * 1024, .tested = TEST_OK_PREW, .probe = probe_sst_fwhub, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (sst_fwhub.c) */ .erase = erase_sst_fwhub, .write = write_sst_fwhub, .read = read_memmapped, @@ -1639,6 +1689,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_sst_fwhub, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (sst_fwhub.c) */ .erase = erase_sst_fwhub, .write = write_sst_fwhub, .read = read_memmapped, @@ -1654,6 +1705,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_sst_fwhub, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (sst_fwhub.c) */ .erase = erase_sst_fwhub, .write = write_sst_fwhub, .read = read_memmapped, @@ -1669,6 +1721,7 @@ .page_size = 4 * 1024, .tested = TEST_UNTESTED, .probe = probe_49lfxxxc, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst49lfxxxc.c) */ .erase = erase_49lfxxxc, .write = write_49lfxxxc, .read = read_memmapped, @@ -1684,6 +1737,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_sst_fwhub, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (sst_fwhub.c) */ .erase = erase_sst_fwhub, .write = write_sst_fwhub, .read = read_memmapped, @@ -1699,6 +1753,7 @@ .page_size = 4 * 1024, .tested = TEST_UNTESTED, .probe = probe_49lfxxxc, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst49lfxxxc.c) */ .erase = erase_49lfxxxc, .write = write_49lfxxxc, .read = read_memmapped, @@ -1714,6 +1769,7 @@ .page_size = 4 * 1024, .tested = TEST_OK_PREW, .probe = probe_49lfxxxc, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst49lfxxxc.c) */ .erase = erase_49lfxxxc, .write = write_49lfxxxc, .read = read_memmapped, @@ -1729,6 +1785,7 @@ .page_size = 16 * 1024, .tested = TEST_OK_PR, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_49lf040, .write = write_49lf040, .read = read_memmapped, @@ -1744,6 +1801,7 @@ .page_size = 16 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_49lf040, .write = write_49lf040, .read = read_memmapped, @@ -1759,6 +1817,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_49lf040, .write = write_49lf040, .read = read_memmapped, @@ -1774,6 +1833,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_sst_fwhub, + .probe_timing = TIMING_FIXME, /* routine is wrapper to probe_jedec (sst_fwhub.c) */ .erase = erase_sst_fwhub, .write = write_sst_fwhub, .read = read_memmapped, @@ -1789,6 +1849,7 @@ .page_size = 4096, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_49lf040, .write = write_49lf040, .read = read_memmapped, @@ -1804,6 +1865,7 @@ .page_size = 4 * 1024, .tested = TEST_OK_PREW, .probe = probe_49lfxxxc, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst49lfxxxc.c) */ .erase = erase_49lfxxxc, .write = write_49lfxxxc, .read = read_memmapped, @@ -1969,6 +2031,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_m29f002, .write = write_m29f002b, .read = read_memmapped, @@ -1984,6 +2047,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_m29f002, .write = write_m29f002t, .read = read_memmapped, @@ -1999,6 +2063,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_29f040b, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (am29f040b.c) */ .erase = erase_29f040b, .write = write_29f040b, .read = read_memmapped, @@ -2014,6 +2079,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_m29f400bt, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (m29f400bt.c) */ .erase = erase_m29f400bt, .write = write_coreboot_m29f400bt, .read = read_memmapped, @@ -2029,6 +2095,7 @@ .page_size = 16 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2044,6 +2111,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2059,6 +2127,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_stm50flw0x0x, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (stm50flw0x0x.c) */ .erase = erase_stm50flw0x0x, .write = write_stm50flw0x0x, .read = read_memmapped, @@ -2074,6 +2143,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_stm50flw0x0x, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (stm50flw0x0x.c) */ .erase = erase_stm50flw0x0x, .write = write_stm50flw0x0x, .read = read_memmapped, @@ -2089,6 +2159,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_stm50flw0x0x, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (stm50flw0x0x.c) */ .erase = erase_stm50flw0x0x, .write = write_stm50flw0x0x, .read = read_memmapped, @@ -2104,6 +2175,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_stm50flw0x0x, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (stm50flw0x0x.c) */ .erase = erase_stm50flw0x0x, .write = write_stm50flw0x0x, .read = read_memmapped, @@ -2119,6 +2191,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_49lfxxxc, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst49lfxxxc.c) */ .erase = NULL, .write = NULL, .read = read_memmapped, @@ -2134,6 +2207,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_82802ab, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (82802ab.c) */ .erase = erase_82802ab, .write = write_82802ab, .read = read_memmapped, @@ -2149,6 +2223,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_82802ab, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (82802ab.c) */ .erase = erase_82802ab, .write = write_82802ab, .read = read_memmapped, @@ -2164,6 +2239,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_82802ab, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (82802ab.c) */ .erase = erase_82802ab, .write = write_82802ab, .read = read_memmapped, @@ -2179,6 +2255,7 @@ .page_size = 64 * 1024, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2194,6 +2271,7 @@ .page_size = 128, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2209,6 +2287,7 @@ .page_size = 128, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2224,6 +2303,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2239,6 +2319,7 @@ .page_size = 128, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2254,6 +2335,7 @@ .page_size = 16384, /* Non-uniform sectors */ .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = NULL, .write = NULL, .read = read_memmapped, @@ -2269,6 +2351,7 @@ .page_size = 16384, /* Non-uniform sectors */ .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = NULL, .write = NULL, .read = read_memmapped, @@ -2344,6 +2427,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2359,6 +2443,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2374,6 +2459,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2389,6 +2475,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_w29ee011, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (w29ee011.c) */ .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2404,6 +2491,7 @@ .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2419,6 +2507,7 @@ .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2434,6 +2523,7 @@ .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_w39v040c, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (w39v040c.c) */ .erase = erase_w39v040c, .write = write_w39v040c, .read = read_memmapped, @@ -2449,6 +2539,7 @@ .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2464,6 +2555,7 @@ .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2479,6 +2571,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2494,6 +2587,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2509,6 +2603,7 @@ .page_size = 128, .tested = TEST_UNTESTED, .probe = probe_jedec, + .probe_timing = TIMING_FIXME, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2524,6 +2619,7 @@ .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_winbond_fwhub, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (w39v080fa.c) */ .erase = erase_winbond_fwhub, .write = write_winbond_fwhub, .read = read_memmapped, @@ -2539,6 +2635,7 @@ .page_size = 64*1024, .tested = TEST_UNTESTED, .probe = probe_winbond_fwhub, + .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (w39v080fa.c) */ .erase = erase_winbond_fwhub, .write = write_winbond_fwhub, .read = read_memmapped, Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-06-03 07:50:39 UTC (rev 568) +++ trunk/jedec.c 2009-06-03 14:46:22 UTC (rev 569) @@ -91,7 +91,23 @@ uint8_t id1, id2; uint32_t largeid1, largeid2; uint32_t flashcontent1, flashcontent2; + int probe_timing_enter, probe_timing_exit; + if (flash->probe_timing > 0) + probe_timing_enter = probe_timing_exit = flash->probe_timing; + else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */ + probe_timing_enter = probe_timing_exit = 0; + } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */ + printf_debug("Chip lacks correct probe timing information, " + "using default 10mS/40uS\n"); + probe_timing_enter = 10000; + probe_timing_exit = 40; + } else { + printf("Chip has negative value in probe_timing, failing " + "without chip access\n"); + return 0; + } + /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); @@ -101,7 +117,7 @@ /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ - myusec_delay(10000); + myusec_delay(probe_timing_enter); /* Read product ID */ id1 = chip_readb(bios); @@ -127,7 +143,7 @@ chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + myusec_delay(probe_timing_exit); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); if (!oddparity(id1)) From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 16:49:26 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 16:49:26 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: References: <4A25892B.9010506@gmx.net> <4A25AB49.30305@gmx.net> <4A25B068.2010706@gmx.net> Message-ID: <4A268D76.6010106@gmx.net> On 03.06.2009 01:09, Maciej Pijanka wrote: > Add probe_timing information (int uS value). > > Signed-Off-by: Maciej Pijanka Thanks. Acked-by: Carl-Daniel Hailfinger and committed in r569 with some cosmetic fixes. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 16:51:06 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 16:51:06 +0200 Subject: [coreboot] Flashrom jedec probe patch + AT29C010A logs In-Reply-To: <1244018432.5947.16.camel@mattotaupa.wohnung.familie-menzel.net> References: <4A25892B.9010506@gmx.net> <4A25AB49.30305@gmx.net> <4A25B068.2010706@gmx.net> <1244018432.5947.16.camel@mattotaupa.wohnung.familie-menzel.net> Message-ID: <4A268DDA.3000504@gmx.net> Hi Paul, On 03.06.2009 10:40, Paul Menzel wrote: > Just some typos and wording suggestions. > Sorry, I saw your mail too late. Could you maybe send your suggestions as a patch against the current tree? Some of the texts have already been rewritten by me, but your flashchips.c comments (and maybe others) should still be valid. Regards, Carl-Daniel -- http://www.hailfinger.org/ From info at coresystems.de Wed Jun 3 16:59:20 2009 From: info at coresystems.de (coreboot information) Date: Wed, 03 Jun 2009 16:59:20 +0200 Subject: [coreboot] build service results for r4335 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "libv" checked in revision 4335 to the coreboot repository. This caused the following changes: Change Log: Revert "CMOS: Add set_option and rework get_option." This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660. Stepan pointed out that "s" means string, which makes the following statement in this commit message invalid: "Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go." Signed-off-by: Luc Verhaegen Acked-by: Luc Verhaegen Build Log: Compilation of kontron:986lcd-m has been fixed If something broke during this checkin please be a pain in libv's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From christian.leber at ziti.uni-heidelberg.de Wed Jun 3 17:01:56 2009 From: christian.leber at ziti.uni-heidelberg.de (Christian Leber) Date: Wed, 3 Jun 2009 17:01:56 +0200 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20906021327p24d9e41cx810c09f238edc4bc@mail.gmail.com> References: <20090602173533.GA25977@localdomain> <534e5dc20906021327p24d9e41cx810c09f238edc4bc@mail.gmail.com> Message-ID: <200906031701.56665.christian.leber@ziti.uni-heidelberg.de> On Tuesday 02 June 2009 22:27:58 Marc Jones wrote: Hi Marc > You are the first to try this on a real system. I also just tried it, it does not work (but fails a little bit later than Ward), log attached. The System is a tyan s2912_fam10 with the very same CPUs (00100f42). Without microcode patch we can boot the system, given that a HTX card is in the system. Without HTX card coreboot will fail. Christian -------------- next part -------------- coreboot-2.0.0-r4333M_Fallback Wed Jun 3 16:47:23 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1062, current patch id = 0x00000000 microcode: patch id to apply = 0x0100009f microcode: updated to patch id = 0x0100009f success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 01 01 00 Exit amd_ht_init() cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started core0: --- { APICID = 04 NODEID = 01 COREID = 00} --- i mCiocrroe0c osdet:ar teequdi vona lennotde :re v0 1 dW a=it 0ax1l0l 6c2o, rec0ursr estnat rptaedt cdh oined _= s0taxr0t00_0ot0h0e00r rcores(m)ic oincoidt en:o pdae:tc 0h0 i d cotro easp: p0l3y = S0tx0a1rt0 0o00t9hefr idciocrer oc-o dnoed: euipd:d at00e d tcoo repsat:c h03 : i= n0ixt0 1n00o0d0e9:f 0 1s u cccoersess 0 pu c o SSettaArMtD MoStRh er core do-n ne -e1--iitd_:f i0d1v i d ccocc_aroooprerreese(s:xxxt: ::a 0 g3 -- a=== --)--s atpa{{{ ir ctAAAiePPPddIII: CCC aIII0pDDD4 p FiIcDi000132Vd I:NNND OOO DDoDEEEn IIIADDDP :=== 00004000 CCCOOORRREEEIIIDDD === 000231}}} }NIT d ccceoootrerreeecxtxx:::e d --f--r-----o m {{ { -A-AAPP-PI IICCC{I IIDD D A ===P I CI000576D NNN- - - - I -- NIIsIITTTs u dddieneetttge eecccStOtteeeFdTdd _fRffrrrEoSoommmE T .-.-----.- From libv at skynet.be Wed Jun 3 17:13:39 2009 From: libv at skynet.be (Luc Verhaegen) Date: Wed, 3 Jun 2009 17:13:39 +0200 Subject: [coreboot] [v2] r4335 - in trunk/coreboot-v2: src/console src/cpu/amd/dualcore src/cpu/amd/model_fxx src/cpu/amd/quadcore src/cpu/intel/hyperthreading src/include/console src/include/pc80 src/mainboard/amd/dbm690t src/mainboard/amd/pistachio src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/broadcom/blast src/mainboard/dell/s1850 src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli src/mainboard/hp/dl145_g3 src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/intel/jarrell src/mainboard/iwill/dk8_htx src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x src/mainboard/msi/ms7135 src/mainboard/msi/ms7260 src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/newisys/khepri src/mainboard/nvidia/l1_2pvv src/mainboard/sunw/ultra40 src/mainboard/supermicro/h8dme src/mainboard/supermicro/h8dmr src/ mainb... In-Reply-To: <20090603141958.A744586C004@maildelivery026.isp.belgacom.be> References: <20090603141958.A744586C004@maildelivery026.isp.belgacom.be> Message-ID: <20090603151339.GA28419@skynet.be> On Wed, Jun 03, 2009 at 04:19:34PM +0200, svn at coreboot.org wrote: > Author: libv > Date: 2009-06-03 16:19:33 +0200 (Wed, 03 Jun 2009) > New Revision: 4335 > > Modified: > Log: > Revert "CMOS: Add set_option and rework get_option." > > This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660. > > Stepan pointed out that "s" means string, which makes the following statement > in this commit message invalid: "Since we either have reserved space (which > we shouldn't do anything with in these two functions), an enum or a > hexadecimal value, unsigned int seemed like the way to go." > > Signed-off-by: Luc Verhaegen > Acked-by: Luc Verhaegen Not to minimise my own part in this mess, but; several people found it necessary to chime in on a brainfart of mine, but only Peter spent the time reviewing this patch. If people had spent some time reviewing this, then maybe the wrong assumption would've been caught in time. Instead, several people, some of whom should have intimate enough knowledge of the cmos handling, found it necessary to weigh in on a discussion where it was clear that the person who started it (me) wasn't intending on putting his weight behind any code in the very near future anyway. The code that was actually there did get ignored, and with one ACK in the pocket, it ended up getting committed, with this mess as a result. This is where this whole acking system breaks down, and no tool, which will incur even more overhead and less willingness to review, will help, it will only make things worse. And another thing: the option table building tool is some of the worst examples of C code that i have seen in quite a while. Whatever option handling stuff you (whoever you are) are thinking up now, know that it also needs to be implemented, and properly this time, and you better be prepared to do so by yourself. Yes, i am quite miffed. I care about the code i produce and i spent quite some time on this patch, cleaning up several things that weren't ever given a single thought before, providing an actually working integer bit retrieval, trying hard to cover all angles, but apparently i still missed one. So what i got in return is 1 big commit, 1 build breakage with shortly after the fixing commit, then both getting quickly reverted, and i rather dislike this. I do not like to see halfarsed or broken stuff going out, especially not if i am myself responsible for having produced the crap in the first place. Luc Verhaegen. From marcj303 at gmail.com Wed Jun 3 17:45:23 2009 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 3 Jun 2009 09:45:23 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <20090602210237.GA24394@localdomain> References: <534e5dc20903250849n5eaf2df5ke8d98cdc945d9821@mail.gmail.com> <20090602155729.GA22254@localdomain> <534e5dc20906020939g80a70d6r37dc8084de676ab5@mail.gmail.com> <20090602173533.GA25977@localdomain> <534e5dc20906021327p24d9e41cx810c09f238edc4bc@mail.gmail.com> <20090602210237.GA24394@localdomain> Message-ID: <534e5dc20906030845v1bced821x1574a400c20fa49f@mail.gmail.com> On Tue, Jun 2, 2009 at 3:02 PM, Ward Vandewege wrote: > On Tue, Jun 02, 2009 at 02:27:58PM -0600, Marc Jones wrote: >> You are the first to try this on a real system. Nothing is jumping out >> at me in the code. If you can put in some debug checks around there it >> will be helpful to figure out. > > Sure. I've sprinkled some debug code and traced the hang to this bit of code > in cpu/amd/model_10xxx/init_cpus.c, void AMD_SetHtPhyRegister: > > ? ?/* Now get the current phy register data > ? ? * LinkPhyDone = 0, LinkPhyWrite = 0 is a read > ? ? */ > ? ?phyReg |= fam10_htphy_default[entry].htreg; > ? ?pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg); > > ? ?do { > ? ? ?val = pci_read_config32(NODE_PCI(node, 4), phyBase); > ? ?} while (!(val & HTPHY_IS_COMPLETE_MASK)); > > That's an infinite loop on the second CPU, apparently. It looks like the errata for C2 are needed with the microcode update. There are several new ones: Revision Guide for AMD Family 10h Processors. http://developer.amd.com/documentation/guides/Pages/default.aspx Errata 327 seems like it might be the issue since it is in the same registers. I'll look and see where the best place for making the change. I should have some free time this afternoon. Marc -- http://marcjonesconsulting.com From marcj303 at gmail.com Wed Jun 3 17:49:27 2009 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 3 Jun 2009 09:49:27 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <200906031701.56665.christian.leber@ziti.uni-heidelberg.de> References: <20090602173533.GA25977@localdomain> <534e5dc20906021327p24d9e41cx810c09f238edc4bc@mail.gmail.com> <200906031701.56665.christian.leber@ziti.uni-heidelberg.de> Message-ID: <534e5dc20906030849sf255c81v80f358612399b475@mail.gmail.com> On Wed, Jun 3, 2009 at 9:01 AM, Christian Leber wrote: > On Tuesday 02 June 2009 22:27:58 Marc Jones wrote: > > Hi Marc > >> You are the first to try this on a real system. > > I also just tried it, it does not work (but fails a little bit later than > Ward), log attached. > The System is a tyan s2912_fam10 with the very same CPUs (00100f42). > Without microcode patch we can boot the system, given that a HTX card is in > the system. Without HTX card coreboot will fail. Thanks for testing. It helps to have a few different cases to narrow down the problems. My guess is that the HTX card forces the HT link speed to a lower speed and that allows it to work. Marc -- http://marcjonesconsulting.com From vidwer at gmail.com Wed Jun 3 18:20:35 2009 From: vidwer at gmail.com (Idwer Vollering) Date: Wed, 3 Jun 2009 18:20:35 +0200 Subject: [coreboot] [flashrom] r568 - trunk In-Reply-To: <4a262b52.0167f10a.3c79.1be2SMTPIN_ADDED@mx.google.com> References: <4a262b52.0167f10a.3c79.1be2SMTPIN_ADDED@mx.google.com> Message-ID: 2009/6/3 > Author: libv > Date: 2009-06-03 09:50:39 +0200 (Wed, 03 Jun 2009) > New Revision: 568 > > Modified: > trunk/board_enable.c > Log: > Board enable: Gigabyte GA K8N SLI. > > Raises bits 0 and 2 on offset 0xE1 in the system control area of the > nvidia ck804 lpc. > > Signed-off-by: Luc Verhaegen > Acked-by: Carl-Daniel Hailfinger > Acked-by: Alexander Gordeev > > > Modified: trunk/board_enable.c > =================================================================== > --- trunk/board_enable.c 2009-06-02 19:54:22 UTC (rev 567) > +++ trunk/board_enable.c 2009-06-03 07:50:39 UTC (rev 568) > @@ -372,6 +372,31 @@ > return 0; > } > > +/** > + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. > + */ > +static int board_ga_k8n_sli(const char *name) > +{ > + struct pci_dev *dev; > + uint32_t base; > + uint8_t tmp; > + > + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ > + if (!dev) { > + fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n"); > + return -1; > + } > + > + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control > area */ > + > + /* if anyone knows more about nvidia lpcs, feel free to explain > this */ > + tmp = inb(base + 0xE1); > + tmp |= 0x05; > + outb(tmp, base + 0xE1); > + > + return 0; > +} > + > static int board_hp_dl145_g3_enable(const char *name) > { > /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ > @@ -670,6 +695,7 @@ > {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, > "epox", "ep-bx3", "EPoX", "EP-BX3", > board_epox_ep_bx3}, > {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, > "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", > it87xx_probe_spi_flash}, > {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, > NULL, NULL, "GIGABYTE", "GA-7VT600", > board_biostar_p4m80_m4}, > + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, > NULL, NULL, "GIGABYTE", "GA-K8N-SLI", > board_ga_k8n_sli}, > {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, > "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", > it87xx_probe_spi_flash}, > {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, > "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", > it87xx_probe_spi_flash}, > {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, > NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", > it87xx_probe_spi_flash}, > @@ -787,7 +813,6 @@ > { "Boser", "HS-6637", }, > { "DFI", "855GME-MGF", }, > { "FIC", "VA-502", }, > - { "GIGABYTE", "GA-K8N-SLI", }, > { "MSI", "MS-6178", }, > { "MSI", "MS-7260 (K9N Neo)", }, > { "PCCHIPS", "M537DMA33", }, > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Make FreeBSD's gmake happy. Signed-off-by: Idwer Vollering Index: board_enable.c =================================================================== --- board_enable.c (revision 568) +++ board_enable.c (working copy) @@ -390,9 +390,9 @@ base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ /* if anyone knows more about nvidia lpcs, feel free to explain this */ - tmp = inb(base + 0xE1); + tmp = INB(base + 0xE1); tmp |= 0x05; - outb(tmp, base + 0xE1); + OUTB(tmp, base + 0xE1); return 0; } -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom_fbsd_fix_r568.diff Type: text/x-patch Size: 464 bytes Desc: not available URL: From svn at coreboot.org Wed Jun 3 18:41:11 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 3 Jun 2009 18:41:11 +0200 Subject: [coreboot] [flashrom] r570 - trunk Message-ID: Author: hailfinger Date: 2009-06-03 18:41:11 +0200 (Wed, 03 Jun 2009) New Revision: 570 Modified: trunk/board_enable.c Log: Use macros for inb and outb which were forgotten in r568. This makes FreeBSD happy. Signed-off-by: Idwer Vollering Acked-by: Carl-Daniel Hailfinger Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-03 14:46:22 UTC (rev 569) +++ trunk/board_enable.c 2009-06-03 16:41:11 UTC (rev 570) @@ -390,9 +390,9 @@ base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ /* if anyone knows more about nvidia lpcs, feel free to explain this */ - tmp = inb(base + 0xE1); + tmp = INB(base + 0xE1); tmp |= 0x05; - outb(tmp, base + 0xE1); + OUTB(tmp, base + 0xE1); return 0; } From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 18:42:17 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 18:42:17 +0200 Subject: [coreboot] [flashrom] r568 - trunk In-Reply-To: References: <4a262b52.0167f10a.3c79.1be2SMTPIN_ADDED@mx.google.com> Message-ID: <4A26A7E9.4010700@gmx.net> On 03.06.2009 18:20, Idwer Vollering wrote: > Make FreeBSD's gmake happy. > > Signed-off-by: Idwer Vollering > Thanks. Acked-by: Carl-Daniel Hailfinger and committed in r570. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Wed Jun 3 19:31:37 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 03 Jun 2009 19:31:37 +0200 Subject: [coreboot] [PATCH] flashrom: add probe timings forgotten in r569 Message-ID: <4A26B379.60404@gmx.net> Add probe timings forgotten in r569. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-probe_timing/flashchips.c =================================================================== --- flashrom-probe_timing/flashchips.c (Revision 570) +++ flashrom-probe_timing/flashchips.c (Arbeitskopie) @@ -35,7 +35,7 @@ * Bus Type, * Total size (kB), Page size (B), * Test status, - * Probe function, Probe function timing argument, Erase function, Write function, Read function + * Probe function, Probe function timing, Erase function, Write function, Read function */ { @@ -176,6 +176,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -191,6 +192,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -206,6 +208,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -221,6 +224,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -236,6 +240,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -251,6 +256,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -266,6 +272,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -281,6 +288,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -296,6 +304,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -311,6 +320,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -326,6 +336,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, @@ -341,6 +352,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -356,6 +368,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -371,6 +384,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -387,6 +401,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -402,6 +417,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, @@ -482,6 +498,7 @@ .page_size = 1056 /* No power of two sizes */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL /* Incompatible Page write */, .read = NULL /* Incompatible read */, @@ -497,6 +514,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -512,6 +530,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -527,6 +546,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -542,6 +562,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -557,6 +578,7 @@ .page_size = 512 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -572,6 +594,7 @@ .page_size = 528 /* No power of two sizes */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL /* Incompatible read */, @@ -587,6 +610,7 @@ .page_size = 512 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -602,6 +626,7 @@ .page_size = 1024 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -665,6 +690,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -888,6 +914,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_82802ab, + .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .erase = erase_82802ab, .write = write_82802ab, .read = read_memmapped, @@ -903,6 +930,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_82802ab, + .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .erase = erase_82802ab, .write = write_82802ab, .read = read_memmapped, @@ -918,6 +946,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -933,6 +962,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -948,6 +978,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -963,6 +994,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -978,6 +1010,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -993,6 +1026,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1008,6 +1042,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1023,6 +1058,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1038,6 +1074,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1053,6 +1090,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1068,6 +1106,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1131,6 +1170,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1146,6 +1186,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1161,6 +1202,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1176,6 +1218,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1191,6 +1234,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1206,6 +1250,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1221,6 +1266,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1236,6 +1282,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1251,6 +1298,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1266,6 +1314,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1281,6 +1330,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1360,6 +1410,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1375,6 +1426,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1390,6 +1442,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1405,6 +1458,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1420,6 +1474,7 @@ .page_size = 64*1024, .tested = TEST_OK_PR, .probe = probe_spi_rems, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1435,6 +1490,7 @@ .page_size = 64*1024, .tested = TEST_OK_PR, .probe = probe_spi_rems, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1450,6 +1506,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1881,6 +1938,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1896,6 +1954,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1911,6 +1970,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1926,6 +1986,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1941,6 +2002,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1956,6 +2018,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1971,6 +2034,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1986,6 +2050,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2001,6 +2066,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2016,6 +2082,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2367,6 +2434,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2382,6 +2450,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2397,6 +2466,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2412,6 +2482,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2651,6 +2722,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2666,6 +2738,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2681,6 +2754,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2696,6 +2770,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2711,6 +2786,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2726,6 +2802,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_probe_timing.diff URL: From rminnich at gmail.com Wed Jun 3 22:21:39 2009 From: rminnich at gmail.com (ron minnich) Date: Wed, 3 Jun 2009 13:21:39 -0700 Subject: [coreboot] [patch] some obvious bugs in rs690 In-Reply-To: References: Message-ID: <13426df10906031321n1821d536if78831a054e900d5@mail.gmail.com> Acked-by; Ronald G. Minnich not tested but it looks ok to me. ron From joe at settoplinux.org Thu Jun 4 00:22:18 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 03 Jun 2009 18:22:18 -0400 Subject: [coreboot] Intel 8xx northbridge ram init is wrong In-Reply-To: <4A254F3E.6090308@coresystems.de> References: <99aacbe9d2f9bb9cfb802ff6a8fe1fab@imap.1and1.com> <4A254CB5.10805@coresystems.de> <91142643581500eaca3028b62700885b@imap.1and1.com> <4A254F3E.6090308@coresystems.de> Message-ID: <7342d5fa3c81f37c0e776df38eebc529@imap.1and1.com> On Tue, 02 Jun 2009 18:11:42 +0200, Stefan Reinauer wrote: >> >> >> On Tue, 02 Jun 2009 18:00:53 +0200, Stefan Reinauer > >> wrote: >> >>> On 02.06.2009 17:13 Uhr, Joseph Smith wrote: >>> >>>> Hello, >>>> Was anyone aware we are doing the do_ram_command() wrong on the i8xx >>>> nothbridges? >>>> We are sending the ram commands to all memory and doing our dummy > reads >>>> >>> at >>> >>>> the end. >>>> I just found an Intel doc that says we are supposed to do all the ram >>>> commands to each row of memory. >>>> >>>> >>> ... >>> >>>> I will work on a patch for the i830, we should probibly fix this on > the >>>> other Intle northbridges. >>>> >>>> >>> Check the i945 code for an example on how to do it... older chipsets >>> might/might not be different... >>> >>> >> Would it be different for SDRAM vs DDR ? >> >> > > You need a couple more steps (different MRS commands etc) for DDR, but > the loop itself is basically the same. > > Ok, I hope you don't mind but I have a few questions about how the i945 sdram_jedec_enable() does it? Just to clarify, jedec seems to call it "banks" and Intel calls it "rows" correct? I don't really understand how you are calculating the bank address (BA or bankaddr) which determines the row of memory to initialize, can you logically explain it or do you have a good source you can point me too? According to your for loop, it looks like you are running the set of initialize commands 8 times? If the i945 has a max of 2 memory sockets which means max of 4 rows, shouldn't this only run 4 times? Also it doesn't look like there is a control structure in place to skip the rows where no memory is found? Is that correct? Sorry if these questions are silly, I am just trying to understand it. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From svn at coreboot.org Thu Jun 4 03:57:03 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 4 Jun 2009 03:57:03 +0200 Subject: [coreboot] [v2] r4336 - trunk/coreboot-v2/src/southbridge/amd/rs690 Message-ID: Author: zbao Date: 2009-06-04 03:57:03 +0200 (Thu, 04 Jun 2009) New Revision: 4336 Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c Log: This patch is about some noticable bugs which was made by no reason. 1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right? 2. In rs690_pcie.c, (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment). In rpr 5.10.2, step 2, step 2.1 & step 2.6 (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20, instead of PCIEIND_P: 0x20. In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation Signed-off-by: Zheng Bao Acked-by: Ronald G. Minnich Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2009-06-03 14:19:33 UTC (rev 4335) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_cmn.c 2009-06-04 01:57:03 UTC (rev 4336) @@ -49,7 +49,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { /*get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c); + u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ @@ -62,7 +62,7 @@ u32 reg_old, reg; /*get BAR3 base address for nbcfg0x1c */ - u32 addr = pci_read_config32(nb_dev, 0x1c); + u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-03 14:19:33 UTC (rev 4335) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-04 01:57:03 UTC (rev 4336) @@ -212,8 +212,8 @@ set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0); /* no description in datasheet. */ /* init GPPSB port */ - /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 0*/ - set_pcie_enable_bits(dev, 0x70, 7 << 16, 0xd << 16); + /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 1*/ + set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0xd << 16); /* PCIE initialization 5.10.2: rpr 2.4 */ set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14); /* Do not gate the electrical idle from the PHY and enables the escape from L1L23 */ @@ -240,7 +240,7 @@ } /* step 5: dynamic slave CPL buffer allocation */ - set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); + set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 11, 1 << 11); /* step 5a: Training for GPP devices */ /* init GPP */ From Zheng.Bao at amd.com Thu Jun 4 04:00:00 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Thu, 4 Jun 2009 10:00:00 +0800 Subject: [coreboot] [patch] some obvious bugs in rs690 In-Reply-To: <13426df10906031321n1821d536if78831a054e900d5@mail.gmail.com> References: <13426df10906031321n1821d536if78831a054e900d5@mail.gmail.com> Message-ID: Thanks, committed to r4336. Zheng -----Original Message----- From: ron minnich [mailto:rminnich at gmail.com] Sent: Thursday, June 04, 2009 4:22 AM To: Bao, Zheng Cc: coreboot Subject: Re: [coreboot] [patch] some obvious bugs in rs690 Acked-by; Ronald G. Minnich not tested but it looks ok to me. ron From c-d.hailfinger.devel.2006 at gmx.net Thu Jun 4 04:41:46 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 04 Jun 2009 04:41:46 +0200 Subject: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. In-Reply-To: References: <4A093DA8.1090701@assembler.cz> Message-ID: <4A27346A.7050109@gmx.net> I found the HIGH_TABLES bug on the DBM690T. The K8 HIGH_TABLES code places these tables in UMA video memory. Of course that memory is cleared by some payloads and operating systems. However, if I fix that, Linux still crashes during boot because it only sees 32 MB instead of 2 MB RAM. If I disable high tables completely, Linux complains about corrupt ACPI tables and other stuff. Has the tables code been tested recently if it works even in the case where we don't want high tables? Regards, Carl-Daniel -- http://www.hailfinger.org/ From Zheng.Bao at amd.com Thu Jun 4 04:46:18 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Thu, 4 Jun 2009 10:46:18 +0800 Subject: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. In-Reply-To: <4A27346A.7050109@gmx.net> References: <4A093DA8.1090701@assembler.cz> <4A27346A.7050109@gmx.net> Message-ID: Based on my test, if I set HIVE_HIGH_TABLES=1 in northbridge/amd/amdk8/Config.lb, Linux will not crash and ACPI works well. Note. I use the old version filo without libpayload. Zheng -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] Sent: Thursday, June 04, 2009 10:42 AM To: Bao, Zheng Cc: coreboot at coreboot.org Subject: Re: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. I found the HIGH_TABLES bug on the DBM690T. The K8 HIGH_TABLES code places these tables in UMA video memory. Of course that memory is cleared by some payloads and operating systems. However, if I fix that, Linux still crashes during boot because it only sees 32 MB instead of 2 MB RAM. If I disable high tables completely, Linux complains about corrupt ACPI tables and other stuff. Has the tables code been tested recently if it works even in the case where we don't want high tables? Regards, Carl-Daniel -- http://www.hailfinger.org/ From Zheng.Bao at amd.com Thu Jun 4 04:48:55 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Thu, 4 Jun 2009 10:48:55 +0800 Subject: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. In-Reply-To: References: <4A27346A.7050109@gmx.net> Message-ID: Sorry, I set HIVE_HIGH_TABLES=0 not 1. Please delete my last mail. Based on my test, if I set HIVE_HIGH_TABLES=0 in northbridge/amd/amdk8/Config.lb, Linux will not crash and ACPI works well. Note. I use the old version filo without libpayload. Zheng -----Original Message----- From: Bao, Zheng Sent: Thursday, June 04, 2009 10:46 AM To: 'Carl-Daniel Hailfinger' Cc: 'coreboot at coreboot.org' Subject: RE: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. Based on my test, if I set HIVE_HIGH_TABLES=1 in northbridge/amd/amdk8/Config.lb, Linux will not crash and ACPI works well. Note. I use the old version filo without libpayload. Zheng -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] Sent: Thursday, June 04, 2009 10:42 AM To: Bao, Zheng Cc: coreboot at coreboot.org Subject: Re: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. I found the HIGH_TABLES bug on the DBM690T. The K8 HIGH_TABLES code places these tables in UMA video memory. Of course that memory is cleared by some payloads and operating systems. However, if I fix that, Linux still crashes during boot because it only sees 32 MB instead of 2 MB RAM. If I disable high tables completely, Linux complains about corrupt ACPI tables and other stuff. Has the tables code been tested recently if it works even in the case where we don't want high tables? Regards, Carl-Daniel -- http://www.hailfinger.org/ From patrick at georgi-clan.de Thu Jun 4 08:59:17 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Thu, 04 Jun 2009 08:59:17 +0200 Subject: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. In-Reply-To: <4A27346A.7050109@gmx.net> References: <4A093DA8.1090701@assembler.cz> <4A27346A.7050109@gmx.net> Message-ID: <4A2770C5.3010104@georgi-clan.de> Am 04.06.2009 04:41, schrieb Carl-Daniel Hailfinger: > I found the HIGH_TABLES bug on the DBM690T. > > The K8 HIGH_TABLES code places these tables in UMA video memory. Of > course that memory is cleared by some payloads and operating systems. > > However, if I fix that, Linux still crashes during boot because it only > sees 32 MB instead of 2 MB RAM. > Unless you're using SeaBIOS, you have to use both HAVE_HIGH_TABLES and HAVE_LOW_TABLES to have things work, otherwise the high tables aren't found. 32 MB is a good sign that the tables weren't found, so FILO (I think) defaults to "safe" 32MB. From prabhu.chavandi at gmail.com Thu Jun 4 09:09:44 2009 From: prabhu.chavandi at gmail.com (Prabhu Chawandi) Date: Thu, 4 Jun 2009 12:39:44 +0530 Subject: [coreboot] Regarding NVRAM Tool Message-ID: <241b8f7b0906040009m4b716cc6kd15f39f704eecade@mail.gmail.com> Hi all, I am writing the NVRAM tool. Which does basic flash operations. I have to run it using the BDI 2000, by loading on to RAM. I am not having the clear picture of the procedure to follow to be able to load on to RAM. Can any one share the steps ? What are the things to set up ? Initialization deails. Regards, Prabhu From c-d.hailfinger.devel.2006 at gmx.net Thu Jun 4 11:58:42 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 04 Jun 2009 11:58:42 +0200 Subject: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. In-Reply-To: <4A2770C5.3010104@georgi-clan.de> References: <4A093DA8.1090701@assembler.cz> <4A27346A.7050109@gmx.net> <4A2770C5.3010104@georgi-clan.de> Message-ID: <4A279AD2.3080008@gmx.net> On 04.06.2009 08:59, Patrick Georgi wrote: > Am 04.06.2009 04:41, schrieb Carl-Daniel Hailfinger: >> I found the HIGH_TABLES bug on the DBM690T. >> >> The K8 HIGH_TABLES code places these tables in UMA video memory. Of >> course that memory is cleared by some payloads and operating systems. >> >> However, if I fix that, Linux still crashes during boot because it only >> sees 32 MB instead of 2 MB RAM. >> > Unless you're using SeaBIOS, you have to use both HAVE_HIGH_TABLES and > HAVE_LOW_TABLES to have things work, otherwise the high tables aren't > found. > 32 MB is a good sign that the tables weren't found, so FILO (I think) > defaults to "safe" 32MB. I'm running an old version of FILO. Could you please take a look at the amd/dbm690t target and tell me what I have to enable there (HAVE_LOW_TABLES etc.) to have things work? I can probably get access to the hardware later today. Thanks! Regards, Carl-Daniel -- http://www.hailfinger.org/ From paulepanter at users.sourceforge.net Thu Jun 4 13:16:12 2009 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Thu, 04 Jun 2009 13:16:12 +0200 Subject: [coreboot] [PATCH] flashrom: add probe timings forgotten in r569 In-Reply-To: <4A26B379.60404@gmx.net> References: <4A26B379.60404@gmx.net> Message-ID: <1244114172.6062.148.camel@mattotaupa.wohnung.familie-menzel.net> Am Mittwoch, den 03.06.2009, 19:31 +0200 schrieb Carl-Daniel Hailfinger: > Add probe timings forgotten in r569. > > Signed-off-by: Carl-Daniel Hailfinger Applies, compiles, reads and verifies fine. I was not able to test writing. $ sudo ./flashrom -Vr test.rom [?] $ sudo ./flashrom -v test.rom flashrom v0.9.0-r570 No coreboot table found. Found chipset "VIA VT8237S", enabling flash write... Mapping VT8237S MMIO registers at 0xfed02000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Macronix MX25L4005" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. Acked-by: Paul Menzel -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: Dies ist ein digital signierter Nachrichtenteil URL: From joe at settoplinux.org Thu Jun 4 14:34:51 2009 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 04 Jun 2009 08:34:51 -0400 Subject: [coreboot] =?utf-8?q?=5Bdbm690t=5D_The_new_acpi_table_doesn=27t_s?= =?utf-8?q?eem_to=09be=09correct=2E?= In-Reply-To: <4A279AD2.3080008@gmx.net> References: <4A093DA8.1090701@assembler.cz> <4A27346A.7050109@gmx.net> <4A2770C5.3010104@georgi-clan.de> <4A279AD2.3080008@gmx.net> Message-ID: <49a5935cf6160edc2f9c3a7c4e5bcb06@imap.1and1.com> On Thu, 04 Jun 2009 11:58:42 +0200, Carl-Daniel Hailfinger wrote: > On 04.06.2009 08:59, Patrick Georgi wrote: >> Am 04.06.2009 04:41, schrieb Carl-Daniel Hailfinger: >>> I found the HIGH_TABLES bug on the DBM690T. >>> >>> The K8 HIGH_TABLES code places these tables in UMA video memory. Of >>> course that memory is cleared by some payloads and operating systems. >>> >>> However, if I fix that, Linux still crashes during boot because it only >>> sees 32 MB instead of 2 MB RAM. >>> >> Unless you're using SeaBIOS, you have to use both HAVE_HIGH_TABLES and >> HAVE_LOW_TABLES to have things work, otherwise the high tables aren't >> found. >> 32 MB is a good sign that the tables weren't found, so FILO (I think) >> defaults to "safe" 32MB. > > I'm running an old version of FILO. Could you please take a look at the > amd/dbm690t target and tell me what I have to enable there > (HAVE_LOW_TABLES etc.) to have things work? I can probably get access to > the hardware later today. > I have seen the 32mb problem before, if you update FILO it fixes the problem. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From patrick at georgi-clan.de Thu Jun 4 14:37:19 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Thu, 04 Jun 2009 14:37:19 +0200 Subject: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. In-Reply-To: <4A279AD2.3080008@gmx.net> References: <4A093DA8.1090701@assembler.cz> <4A27346A.7050109@gmx.net> <4A2770C5.3010104@georgi-clan.de> <4A279AD2.3080008@gmx.net> Message-ID: <4A27BFFF.10405@georgi-clan.de> Am 04.06.2009 11:58, schrieb Carl-Daniel Hailfinger: > I'm running an old version of FILO. Could you please take a look at the > amd/dbm690t target and tell me what I have to enable there > (HAVE_LOW_TABLES etc.) to have things work? I can probably get access to > the hardware later today. > It might be that your old FILO has no idea of the (relatively new) forwarding pointer field in the cbtable, so it doesn't find all the data. Patrick From christian.leber at ziti.uni-heidelberg.de Thu Jun 4 15:18:08 2009 From: christian.leber at ziti.uni-heidelberg.de (Christian Leber) Date: Thu, 4 Jun 2009 15:18:08 +0200 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20906030849sf255c81v80f358612399b475@mail.gmail.com> References: <200906031701.56665.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906030849sf255c81v80f358612399b475@mail.gmail.com> Message-ID: <200906041518.10203.christian.leber@ziti.uni-heidelberg.de> On Wednesday 03 June 2009 17:49:27 Marc Jones wrote: Hi Marc >>Without HTX card coreboot will fail. > > Thanks for testing. It helps to have a few different cases to narrow > down the problems. My guess is that the HTX card forces the HT link > speed to a lower speed and that allows it to work. No, with HTX card the link between the Opterons is running with HT3 at 2200 Mhz, that is not the problem. We repeated the test just to be sure, it is really the microcode patch that makes it fail like in the log of my last mail in this thread. Christian From marcj303 at gmail.com Thu Jun 4 18:08:59 2009 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 4 Jun 2009 10:08:59 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <200906041518.10203.christian.leber@ziti.uni-heidelberg.de> References: <200906031701.56665.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906030849sf255c81v80f358612399b475@mail.gmail.com> <200906041518.10203.christian.leber@ziti.uni-heidelberg.de> Message-ID: <534e5dc20906040908ub4333f2y1716ec2d0bfab83@mail.gmail.com> On Thu, Jun 4, 2009 at 7:18 AM, Christian Leber wrote: > On Wednesday 03 June 2009 17:49:27 Marc Jones wrote: > > Hi Marc > >>>Without HTX card coreboot will fail. >> >> Thanks for testing. It helps to have a few different cases to narrow >> down the problems. My guess is that the HTX card forces the HT link >> speed to a lower speed and that allows it to work. > > No, with HTX card the link between the Opterons is running with HT3 at 2200 > Mhz, that is not the problem. > > We repeated the test just to be sure, it is really the microcode patch that > makes it fail like in the log of my last mail in this thread. Thanks, As Myles pointed out, my comment didn't make sense. Putting it the errata is the next step. Marc -- http://marcjonesconsulting.com From svn at coreboot.org Thu Jun 4 20:53:03 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 4 Jun 2009 20:53:03 +0200 Subject: [coreboot] [flashrom] r571 - trunk Message-ID: Author: uwe Date: 2009-06-04 20:53:03 +0200 (Thu, 04 Jun 2009) New Revision: 571 Modified: trunk/README trunk/board_enable.c Log: Mark the ASUS A7N8X-E Deluxe as working. I finally found the machine (doesn't belong to me) where I originally tested this board as non-working and I can confirm that all operations work fine now (since the nForce2 patch in r548). Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/README =================================================================== --- trunk/README 2009-06-03 16:41:11 UTC (rev 570) +++ trunk/README 2009-06-04 18:53:03 UTC (rev 571) @@ -97,6 +97,7 @@ Please check the output of 'flashrom -L' for the list of supported flash chips, chipsets/southbridges, mainboards, and flash programmers. + Website ------- Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-03 16:41:11 UTC (rev 570) +++ trunk/board_enable.c 2009-06-04 18:53:03 UTC (rev 571) @@ -741,6 +741,7 @@ { "ASUS", "P2B-D", }, { "ASUS", "P2B-DS", }, { "ASUS", "A7N8X Deluxe", }, + { "ASUS", "A7N8X-E Deluxe", }, { "ASUS", "A7V400-MX", }, { "ASUS", "A7V8X-MX", }, { "ASUS", "A8V-E SE", }, From mylesgw at gmail.com Thu Jun 4 21:03:21 2009 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 4 Jun 2009 13:03:21 -0600 Subject: [coreboot] [PATCH] raminit cleanup for K8 Message-ID: <2831fecf0906041203s568e4c1dv757020979723fd8c@mail.gmail.com> This patch follows svn cp amdk8.h amdk8_pre_f.h This preserves the history of amdk8.h as it moves to amdk8_pre_f.h The point of the patch is to make it easier to understand the raminit code, specifically the difference between pre_f and f code. The only functional changes are in printk statements. The rest is white space. 1. Remove some #if 0 and #if 1 blocks 2. Remove #if USE_DCACHE_RAM blocks. All K8 boards use CAR. 2. Correct typos (canidate -> candidate) 3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h 4. Try to minimize the differences between raminit.c and raminit_f.c 5. Make boards that have rev_f processors include the correct raminit code There is much more that could be done, but it's a start. Abuild tested and boot tested on s2892 and serengeti_cheetah. Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: k8_raminit.diff Type: text/x-patch Size: 52778 bytes Desc: not available URL: From rminnich at gmail.com Thu Jun 4 21:17:34 2009 From: rminnich at gmail.com (ron minnich) Date: Thu, 4 Jun 2009 12:17:34 -0700 Subject: [coreboot] [PATCH] raminit cleanup for K8 In-Reply-To: <2831fecf0906041203s568e4c1dv757020979723fd8c@mail.gmail.com> References: <2831fecf0906041203s568e4c1dv757020979723fd8c@mail.gmail.com> Message-ID: <13426df10906041217n36007d53yc49031d776787223@mail.gmail.com> Acked-by: Ronald G. Minnich From svn at coreboot.org Thu Jun 4 21:25:55 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 4 Jun 2009 21:25:55 +0200 Subject: [coreboot] [flashrom] r572 - trunk Message-ID: Author: uwe Date: 2009-06-04 21:25:54 +0200 (Thu, 04 Jun 2009) New Revision: 572 Modified: trunk/board_enable.c Log: Let's actually sort the board lists alphabetically, and not just pretend we do (trivial). Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-04 18:53:03 UTC (rev 571) +++ trunk/board_enable.c 2009-06-04 19:25:54 UTC (rev 572) @@ -728,25 +728,25 @@ { "Abit", "AX8", }, { "Advantech", "PCM-5820", }, { "ASI", "MB-5BLMP", }, + { "ASUS", "A7N8X Deluxe", }, + { "ASUS", "A7N8X-E Deluxe", }, + { "ASUS", "A7V400-MX", }, + { "ASUS", "A7V8X-MX", }, { "ASUS", "A8N-E", }, { "ASUS", "A8NE-FM/S", }, { "ASUS", "A8N-SLI", }, { "ASUS", "A8N-SLI Premium", }, { "ASUS", "A8V-E Deluxe", }, + { "ASUS", "A8V-E SE", }, + { "ASUS", "M2A-MX", }, { "ASUS", "M2A-VM", }, { "ASUS", "M2N-E", }, { "ASUS", "M2V", }, { "ASUS", "P2B", }, - { "ASUS", "P2B-F", }, { "ASUS", "P2B-D", }, { "ASUS", "P2B-DS", }, - { "ASUS", "A7N8X Deluxe", }, - { "ASUS", "A7N8X-E Deluxe", }, - { "ASUS", "A7V400-MX", }, - { "ASUS", "A7V8X-MX", }, - { "ASUS", "A8V-E SE", }, + { "ASUS", "P2B-F", }, { "ASUS", "P2L97-S", }, - { "ASUS", "M2A-MX", }, { "ASUS", "P5B-Deluxe", }, { "ASUS", "P6T Deluxe V2", }, { "A-Trend", "ATC-6220", }, @@ -758,10 +758,10 @@ { "Jetway", "J7F4K1G5D-PB", }, { "MSI", "MS-6570 (K7N2)", }, { "MSI", "MS-7065", }, + { "MSI", "MS-7168 (Orion)", }, { "MSI", "MS-7236 (945PL Neo3)", }, + { "MSI", "MS-7255 (P4M890M)", }, { "MSI", "MS-7345 (P35 Neo2-FIR)", }, - { "MSI", "MS-7168 (Orion)", }, - { "MSI", "MS-7255 (P4M890M)", }, { "NEC", "PowerMate 2000", }, { "PC Engines", "Alix.1c", }, { "PC Engines", "Alix.2c2", }, @@ -769,10 +769,11 @@ { "PC Engines", "Alix.3c3", }, { "PC Engines", "Alix.3d3", }, { "RCA", "RM4100", }, + { "Sun", "Blade x6250", }, { "Supermicro", "H8QC8", }, - { "Sun", "Blade x6250", }, { "Thomson", "IP1000", }, { "T-Online", "S-100", }, + { "Tyan", "iS5375-1U", }, { "Tyan", "S1846", }, { "Tyan", "S2881", }, { "Tyan", "S2882", }, @@ -788,14 +789,13 @@ { "Tyan", "S5211-1U", }, { "Tyan", "S5220", }, { "Tyan", "S5375", }, - { "Tyan", "iS5375-1U", }, { "Tyan", "S5376G2NR/S5376WAG2NR", }, { "Tyan", "S5377", }, { "Tyan", "S5397", }, { "VIA", "EPIA-LN", }, - { "VIA", "VB700X", }, { "VIA", "NAB74X0", }, { "VIA", "pc2500e", }, + { "VIA", "VB700X", }, {}, }; @@ -818,9 +818,9 @@ { "MSI", "MS-7260 (K9N Neo)", }, { "PCCHIPS", "M537DMA33", }, { "Soyo", "SY-5VD", }, - { "Sun", "Fire x4540", }, { "Sun", "Fire x4150", }, { "Sun", "Fire x4200", }, + { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, {}, From rminnich at gmail.com Thu Jun 4 21:29:45 2009 From: rminnich at gmail.com (ron minnich) Date: Thu, 4 Jun 2009 12:29:45 -0700 Subject: [coreboot] fixed-location entities in cbfs. Message-ID: <13426df10906041229q1e8f428fx502a9f0b7e8724b1@mail.gmail.com> Attached are what I view as a transition plan for cbfs to implement cbfs files at fixed addresses. I call this transitional as the approach I am taking is to add capability to cbfstool but not change code in a way that will break existing usages. There is one additional command syntax, so, example: cbfstool add rom romstrap optionrom 0xffffd000 Will add the file to that fix location for a romstrap. The assumption is that the ROM is based at the end of a 32-bit address space. As you can see from the code, that assumption can easily be over-ridden, if we ever need to, with a command option. Here is one example output result. rminnich at xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0 Alignment: 16 bytes Name Offset Type Size h 0x0 optionrom 251 0x130 free 917120 h3 0xdffe0 optionrom 251 0xe0110 free 97960 The way this is implemented is pretty simple. I introduce a new operator, split, that splits an unallocated area into two unallocated areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits: 0 split -- the free area is the exact fit 1 splits -- need to split some off the front or back 2 splits -- need to split off BOTH the front and back I think you'll be able to see what I've done. I call this transitional because, in the end state, we only need one allocate function; for now I've left two in, to make sure I don't break compatibilty. Why I like this better than ldscript approach: I like having the ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes romstrap visible as a first class object. I think I would have latched onto a problem I was having much more quickly had I remembered the ROMSTRAP. It gets lost in the linker scripts. Anywhere, here it is.This will allow us to remove a lot of ldscript trickiness. ron From rminnich at gmail.com Thu Jun 4 21:52:12 2009 From: rminnich at gmail.com (ron minnich) Date: Thu, 4 Jun 2009 12:52:12 -0700 Subject: [coreboot] Fwd: fixed-location entities in cbfs. In-Reply-To: <13426df10906041229q1e8f428fx502a9f0b7e8724b1@mail.gmail.com> References: <13426df10906041229q1e8f428fx502a9f0b7e8724b1@mail.gmail.com> Message-ID: <13426df10906041252m5c079b58o8dba6a68eb6dd8d4@mail.gmail.com> weird. That's the second time google has dropped an attachment on the floor for me ... ron ---------- Forwarded message ---------- From: ron minnich Date: Thu, Jun 4, 2009 at 12:29 PM Subject: fixed-location entities in cbfs. To: coreboot Attached are what I view as a transition plan for cbfs to implement cbfs files at fixed addresses. I call this transitional as the approach I am taking is to add capability to cbfstool but not change code in a way that will break existing usages. There is one additional command syntax, so, example: cbfstool add rom romstrap optionrom 0xffffd000 Will add the file to that fix location for a romstrap. The assumption is that the ROM is based at the end of a 32-bit address space. As you can see from the code, that assumption can easily be over-ridden, if we ever need to, with a command option. Here is one example output result. rminnich at xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0 Alignment: 16 bytes Name ? ? ? ? ? ? ? ? ? ? ? ? ? Offset ? ? Type ? ? ? ? Size h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0x0 ? ? ? ?optionrom ? 251 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0x130 ? ? ?free ? ? ? ? 917120 h3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xdffe0 ? ?optionrom ? ?251 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0xe0110 ? ?free ? ? ? ? 97960 The way this is implemented is pretty simple. I introduce a new operator, split, that splits an unallocated area into two unallocated areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits: 0 split -- the free area is the exact fit 1 splits -- need to split some off the front or back 2 splits -- need to split off BOTH the front and back I think you'll be able to see what I've done. I call this transitional because, in the end state, we only need one allocate function; for now I've left two in, to make sure I don't break compatibilty. Why I like this better than ldscript approach: I like having the ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes romstrap visible as a first class object. I think I would have latched onto a problem I was having much more quickly had I remembered the ROMSTRAP. It gets lost in the linker scripts. Anywhere, here it is.This will allow us to remove a lot of ldscript trickiness. ron -------------- next part -------------- A non-text attachment was scrubbed... Name: fixed.diff Type: text/x-patch Size: 8757 bytes Desc: not available URL: From svn at coreboot.org Thu Jun 4 22:18:43 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 4 Jun 2009 22:18:43 +0200 Subject: [coreboot] [v2] r4337 - in trunk/coreboot-v2/src: mainboard/amd/dbm690t mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/technexion/tim8690 northbridge/amd/amdk8 Message-ID: Author: myles Date: 2009-06-04 22:18:42 +0200 (Thu, 04 Jun 2009) New Revision: 4337 Added: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_pre_f.h Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c Log: The point of the patch is to make it easier to understand the raminit code, specifically the difference between pre_f and f code. The only functional changes are in printk statements. The rest is white space. 1. Remove some #if 0 and #if 1 blocks 2. Remove #if USE_DCACHE_RAM blocks. All K8 boards use CAR. 2. Correct typos (canidate -> candidate) 3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h 4. Try to minimize the differences between raminit.c and raminit_f.c 5. Make boards that have rev_f processors include the correct raminit code There is much more that could be done, but it's a start. Abuild tested and boot tested on s2892 and serengeti_cheetah. Signed-off-by: Myles Watson Acked-by: Ronald G. Minnich Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-06-04 20:18:42 UTC (rev 4337) @@ -86,7 +86,7 @@ #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" #include "resourcemap.c" Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-06-04 20:18:42 UTC (rev 4337) @@ -80,7 +80,7 @@ #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" #include "resourcemap.c" Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-06-04 20:18:42 UTC (rev 4337) @@ -124,7 +124,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/raminit_f.c" #include "sdram/generic_sdram.c" Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-06-04 20:18:42 UTC (rev 4337) @@ -86,7 +86,7 @@ #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" #include "resourcemap.c" Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2009-06-04 20:18:42 UTC (rev 4337) @@ -1,6 +1,7 @@ uses AGP_APERTURE_SIZE uses HAVE_ACPI_TABLES uses HAVE_HIGH_TABLES +uses K8_REV_F_SUPPORT default AGP_APERTURE_SIZE=0x4000000 default HAVE_HIGH_TABLES=1 @@ -10,12 +11,25 @@ driver northbridge.o driver misc_control.o +if K8_REV_F_SUPPORT + makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" + depends "$(TOP)/src/northbridge/amd/amdk8/raminit_f.c" + action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" +end + +else + +makerule raminit_test + depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c" action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end +end + + if HAVE_ACPI_TABLES object amdk8_acpi.o end Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h 2009-06-04 20:18:42 UTC (rev 4337) @@ -4,269 +4,8 @@ #if K8_REV_F_SUPPORT == 1 #include "amdk8_f.h" - #else -/* Definitions of various K8 registers */ -/* Function 0 */ -#define HT_TRANSACTION_CONTROL 0x68 -#define HTTC_DIS_RD_B_P (1 << 0) -#define HTTC_DIS_RD_DW_P (1 << 1) -#define HTTC_DIS_WR_B_P (1 << 2) -#define HTTC_DIS_WR_DW_P (1 << 3) -#define HTTC_DIS_MTS (1 << 4) -#define HTTC_CPU1_EN (1 << 5) -#define HTTC_CPU_REQ_PASS_PW (1 << 6) -#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) -#define HTTC_DIS_P_MEM_C (1 << 8) -#define HTTC_DIS_RMT_MEM_C (1 << 9) -#define HTTC_DIS_FILL_P (1 << 10) -#define HTTC_RSP_PASS_PW (1 << 11) -#define HTTC_CHG_ISOC_TO_ORD (1 << 12) -#define HTTC_BUF_REL_PRI_SHIFT 13 -#define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 -#define HTTC_LIMIT_CLDT_CFG (1 << 15) -#define HTTC_LINT_EN (1 << 16) -#define HTTC_APIC_EXT_BRD_CST (1 << 17) -#define HTTC_APIC_EXT_ID (1 << 18) -#define HTTC_APIC_EXT_SPUR (1 << 19) -#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) -#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 -#define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 -#define HTTC_MED_PRI_BYP_CNT_SHIFT 24 -#define HTTC_MED_PRI_BYP_CNT_MASK 3 -#define HTTC_HI_PRI_BYP_CNT_SHIFT 26 -#define HTTC_HI_PRI_BYP_CNT_MASK 3 - - -/* Function 1 */ -#define PCI_IO_BASE0 0xc0 -#define PCI_IO_BASE1 0xc8 -#define PCI_IO_BASE2 0xd0 -#define PCI_IO_BASE3 0xd8 -#define PCI_IO_BASE_VGA_EN (1 << 4) -#define PCI_IO_BASE_NO_ISA (1 << 5) - - -/* Function 2 */ -#define DRAM_CSBASE 0x40 -#define DRAM_CSMASK 0x60 -#define DRAM_BANK_ADDR_MAP 0x80 - -#define DRAM_TIMING_LOW 0x88 -#define DTL_TCL_SHIFT 0 -#define DTL_TCL_MASK 0x7 -#define DTL_CL_2 1 -#define DTL_CL_3 2 -#define DTL_CL_2_5 5 -#define DTL_TRC_SHIFT 4 -#define DTL_TRC_MASK 0xf -#define DTL_TRC_BASE 7 -#define DTL_TRC_MIN 7 -#define DTL_TRC_MAX 22 -#define DTL_TRFC_SHIFT 8 -#define DTL_TRFC_MASK 0xf -#define DTL_TRFC_BASE 9 -#define DTL_TRFC_MIN 9 -#define DTL_TRFC_MAX 24 -#define DTL_TRCD_SHIFT 12 -#define DTL_TRCD_MASK 0x7 -#define DTL_TRCD_BASE 0 -#define DTL_TRCD_MIN 2 -#define DTL_TRCD_MAX 6 -#define DTL_TRRD_SHIFT 16 -#define DTL_TRRD_MASK 0x7 -#define DTL_TRRD_BASE 0 -#define DTL_TRRD_MIN 2 -#define DTL_TRRD_MAX 4 -#define DTL_TRAS_SHIFT 20 -#define DTL_TRAS_MASK 0xf -#define DTL_TRAS_BASE 0 -#define DTL_TRAS_MIN 5 -#define DTL_TRAS_MAX 15 -#define DTL_TRP_SHIFT 24 -#define DTL_TRP_MASK 0x7 -#define DTL_TRP_BASE 0 -#define DTL_TRP_MIN 2 -#define DTL_TRP_MAX 6 -#define DTL_TWR_SHIFT 28 -#define DTL_TWR_MASK 0x1 -#define DTL_TWR_BASE 2 -#define DTL_TWR_MIN 2 -#define DTL_TWR_MAX 3 - -#define DRAM_TIMING_HIGH 0x8c -#define DTH_TWTR_SHIFT 0 -#define DTH_TWTR_MASK 0x1 -#define DTH_TWTR_BASE 1 -#define DTH_TWTR_MIN 1 -#define DTH_TWTR_MAX 2 -#define DTH_TRWT_SHIFT 4 -#define DTH_TRWT_MASK 0x7 -#define DTH_TRWT_BASE 1 -#define DTH_TRWT_MIN 1 -#define DTH_TRWT_MAX 6 -#define DTH_TREF_SHIFT 8 -#define DTH_TREF_MASK 0x1f -#define DTH_TREF_100MHZ_4K 0x00 -#define DTH_TREF_133MHZ_4K 0x01 -#define DTH_TREF_166MHZ_4K 0x02 -#define DTH_TREF_200MHZ_4K 0x03 -#define DTH_TREF_100MHZ_8K 0x08 -#define DTH_TREF_133MHZ_8K 0x09 -#define DTH_TREF_166MHZ_8K 0x0A -#define DTH_TREF_200MHZ_8K 0x0B -#define DTH_TWCL_SHIFT 20 -#define DTH_TWCL_MASK 0x7 -#define DTH_TWCL_BASE 1 -#define DTH_TWCL_MIN 1 -#define DTH_TWCL_MAX 2 - -#define DRAM_CONFIG_LOW 0x90 -#define DCL_DLL_Disable (1<<0) -#define DCL_D_DRV (1<<1) -#define DCL_QFC_EN (1<<2) -#define DCL_DisDqsHys (1<<3) -#define DCL_Burst2Opt (1<<5) -#define DCL_DramInit (1<<8) -#define DCL_DualDIMMen (1<<9) -#define DCL_DramEnable (1<<10) -#define DCL_MemClrStatus (1<<11) -#define DCL_ESR (1<<12) -#define DCL_SRS (1<<13) -#define DCL_128BitEn (1<<16) -#define DCL_DimmEccEn (1<<17) -#define DCL_UnBufDimm (1<<18) -#define DCL_32ByteEn (1<<19) -#define DCL_x4DIMM_SHIFT 20 -#define DCL_DisInRcvrs (1<<24) -#define DCL_BypMax_SHIFT 25 -#define DCL_En2T (1<<28) -#define DCL_UpperCSMap (1<<29) - -#define DRAM_CONFIG_HIGH 0x94 -#define DCH_ASYNC_LAT_SHIFT 0 -#define DCH_ASYNC_LAT_MASK 0xf -#define DCH_ASYNC_LAT_BASE 0 -#define DCH_ASYNC_LAT_MIN 0 -#define DCH_ASYNC_LAT_MAX 15 -#define DCH_RDPREAMBLE_SHIFT 8 -#define DCH_RDPREAMBLE_MASK 0xf -#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ -#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ -#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ -#define DCH_IDLE_LIMIT_SHIFT 16 -#define DCH_IDLE_LIMIT_MASK 0x7 -#define DCH_IDLE_LIMIT_0 0 -#define DCH_IDLE_LIMIT_4 1 -#define DCH_IDLE_LIMIT_8 2 -#define DCH_IDLE_LIMIT_16 3 -#define DCH_IDLE_LIMIT_32 4 -#define DCH_IDLE_LIMIT_64 5 -#define DCH_IDLE_LIMIT_128 6 -#define DCH_IDLE_LIMIT_256 7 -#define DCH_DYN_IDLE_CTR_EN (1 << 19) -#define DCH_MEMCLK_SHIFT 20 -#define DCH_MEMCLK_MASK 0x7 -#define DCH_MEMCLK_100MHZ 0 -#define DCH_MEMCLK_133MHZ 2 -#define DCH_MEMCLK_166MHZ 5 -#define DCH_MEMCLK_200MHZ 7 -#define DCH_MEMCLK_VALID (1 << 25) -#define DCH_MEMCLK_EN0 (1 << 26) -#define DCH_MEMCLK_EN1 (1 << 27) -#define DCH_MEMCLK_EN2 (1 << 28) -#define DCH_MEMCLK_EN3 (1 << 29) - -/* Function 3 */ -#define MCA_NB_CONFIG 0x44 -#define MNC_ECC_EN (1 << 22) -#define MNC_CHIPKILL_EN (1 << 23) -#define SCRUB_CONTROL 0x58 -#define SCRUB_NONE 0 -#define SCRUB_40ns 1 -#define SCRUB_80ns 2 -#define SCRUB_160ns 3 -#define SCRUB_320ns 4 -#define SCRUB_640ns 5 -#define SCRUB_1_28us 6 -#define SCRUB_2_56us 7 -#define SCRUB_5_12us 8 -#define SCRUB_10_2us 9 -#define SCRUB_20_5us 10 -#define SCRUB_41_0us 11 -#define SCRUB_81_9us 12 -#define SCRUB_163_8us 13 -#define SCRUB_327_7us 14 -#define SCRUB_655_4us 15 -#define SCRUB_1_31ms 16 -#define SCRUB_2_62ms 17 -#define SCRUB_5_24ms 18 -#define SCRUB_10_49ms 19 -#define SCRUB_20_97ms 20 -#define SCRUB_42ms 21 -#define SCRUB_84ms 22 -#define SC_DRAM_SCRUB_RATE_SHFIT 0 -#define SC_DRAM_SCRUB_RATE_MASK 0x1f -#define SC_L2_SCRUB_RATE_SHIFT 8 -#define SC_L2_SCRUB_RATE_MASK 0x1f -#define SC_L1D_SCRUB_RATE_SHIFT 16 -#define SC_L1D_SCRUB_RATE_MASK 0x1f -#define SCRUB_ADDR_LOW 0x5C -#define SCRUB_ADDR_HIGH 0x60 -#define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_128Bit (1 << 0) -#define NBCAP_MP (1 << 1) -#define NBCAP_BIG_MP (1 << 2) -#define NBCAP_ECC (1 << 3) -#define NBCAP_CHIPKILL_ECC (1 << 4) -#define NBCAP_MEMCLK_SHIFT 5 -#define NBCAP_MEMCLK_MASK 3 -#define NBCAP_MEMCLK_100MHZ 3 -#define NBCAP_MEMCLK_133MHZ 2 -#define NBCAP_MEMCLK_166MHZ 1 -#define NBCAP_MEMCLK_200MHZ 0 -#define NBCAP_MEMCTRL (1 << 8) - - -#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) -#define ConnectionPending (1 << 4) - -#include "raminit.h" -//struct definitions - -struct link_pair_st { - device_t udev; - uint32_t upos; - uint32_t uoffs; - device_t dev; - uint32_t pos; - uint32_t offs; - -} __attribute__((packed)); - -struct sys_info { - uint8_t ctrl_present[NODE_NUMS]; - struct mem_controller ctrl[NODE_NUMS]; - - uint32_t nodes; - struct link_pair_st link_pair[16];// enough? only in_conherent - uint32_t link_pair_num; - uint32_t ht_c_num; - uint32_t sbdn; - uint32_t sblk; - uint32_t sbbusn; -} __attribute__((packed)); - + #include "amdk8_pre_f.h" #endif #endif /* AMDK8_H */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h 2009-06-04 20:18:42 UTC (rev 4337) @@ -456,7 +456,6 @@ #define NonCoherent (1 << 2) #define ConnectionPending (1 << 4) - #include "raminit.h" //struct definitions Copied: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_pre_f.h (from rev 4328, trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h) =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_pre_f.h (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_pre_f.h 2009-06-04 20:18:42 UTC (rev 4337) @@ -0,0 +1,266 @@ +#ifndef AMDK8_PRE_F_H + +#define AMDK8_PRE_F_H + +/* Definitions of various K8 registers */ +/* Function 0 */ +#define HT_TRANSACTION_CONTROL 0x68 +#define HTTC_DIS_RD_B_P (1 << 0) +#define HTTC_DIS_RD_DW_P (1 << 1) +#define HTTC_DIS_WR_B_P (1 << 2) +#define HTTC_DIS_WR_DW_P (1 << 3) +#define HTTC_DIS_MTS (1 << 4) +#define HTTC_CPU1_EN (1 << 5) +#define HTTC_CPU_REQ_PASS_PW (1 << 6) +#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) +#define HTTC_DIS_P_MEM_C (1 << 8) +#define HTTC_DIS_RMT_MEM_C (1 << 9) +#define HTTC_DIS_FILL_P (1 << 10) +#define HTTC_RSP_PASS_PW (1 << 11) +#define HTTC_CHG_ISOC_TO_ORD (1 << 12) +#define HTTC_BUF_REL_PRI_SHIFT 13 +#define HTTC_BUF_REL_PRI_MASK 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_LIMIT_CLDT_CFG (1 << 15) +#define HTTC_LINT_EN (1 << 16) +#define HTTC_APIC_EXT_BRD_CST (1 << 17) +#define HTTC_APIC_EXT_ID (1 << 18) +#define HTTC_APIC_EXT_SPUR (1 << 19) +#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) +#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 +#define HTTC_DS_NP_REQ_LIMIT_MASK 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3 +#define HTTC_MED_PRI_BYP_CNT_SHIFT 24 +#define HTTC_MED_PRI_BYP_CNT_MASK 3 +#define HTTC_HI_PRI_BYP_CNT_SHIFT 26 +#define HTTC_HI_PRI_BYP_CNT_MASK 3 + + +/* Function 1 */ +#define PCI_IO_BASE0 0xc0 +#define PCI_IO_BASE1 0xc8 +#define PCI_IO_BASE2 0xd0 +#define PCI_IO_BASE3 0xd8 +#define PCI_IO_BASE_VGA_EN (1 << 4) +#define PCI_IO_BASE_NO_ISA (1 << 5) + + +/* Function 2 */ +#define DRAM_CSBASE 0x40 +#define DRAM_CSMASK 0x60 +#define DRAM_BANK_ADDR_MAP 0x80 + +#define DRAM_TIMING_LOW 0x88 +#define DTL_TCL_SHIFT 0 +#define DTL_TCL_MASK 0x7 +#define DTL_CL_2 1 +#define DTL_CL_3 2 +#define DTL_CL_2_5 5 +#define DTL_TRC_SHIFT 4 +#define DTL_TRC_MASK 0xf +#define DTL_TRC_BASE 7 +#define DTL_TRC_MIN 7 +#define DTL_TRC_MAX 22 +#define DTL_TRFC_SHIFT 8 +#define DTL_TRFC_MASK 0xf +#define DTL_TRFC_BASE 9 +#define DTL_TRFC_MIN 9 +#define DTL_TRFC_MAX 24 +#define DTL_TRCD_SHIFT 12 +#define DTL_TRCD_MASK 0x7 +#define DTL_TRCD_BASE 0 +#define DTL_TRCD_MIN 2 +#define DTL_TRCD_MAX 6 +#define DTL_TRRD_SHIFT 16 +#define DTL_TRRD_MASK 0x7 +#define DTL_TRRD_BASE 0 +#define DTL_TRRD_MIN 2 +#define DTL_TRRD_MAX 4 +#define DTL_TRAS_SHIFT 20 +#define DTL_TRAS_MASK 0xf +#define DTL_TRAS_BASE 0 +#define DTL_TRAS_MIN 5 +#define DTL_TRAS_MAX 15 +#define DTL_TRP_SHIFT 24 +#define DTL_TRP_MASK 0x7 +#define DTL_TRP_BASE 0 +#define DTL_TRP_MIN 2 +#define DTL_TRP_MAX 6 +#define DTL_TWR_SHIFT 28 +#define DTL_TWR_MASK 0x1 +#define DTL_TWR_BASE 2 +#define DTL_TWR_MIN 2 +#define DTL_TWR_MAX 3 + +#define DRAM_TIMING_HIGH 0x8c +#define DTH_TWTR_SHIFT 0 +#define DTH_TWTR_MASK 0x1 +#define DTH_TWTR_BASE 1 +#define DTH_TWTR_MIN 1 +#define DTH_TWTR_MAX 2 +#define DTH_TRWT_SHIFT 4 +#define DTH_TRWT_MASK 0x7 +#define DTH_TRWT_BASE 1 +#define DTH_TRWT_MIN 1 +#define DTH_TRWT_MAX 6 +#define DTH_TREF_SHIFT 8 +#define DTH_TREF_MASK 0x1f +#define DTH_TREF_100MHZ_4K 0x00 +#define DTH_TREF_133MHZ_4K 0x01 +#define DTH_TREF_166MHZ_4K 0x02 +#define DTH_TREF_200MHZ_4K 0x03 +#define DTH_TREF_100MHZ_8K 0x08 +#define DTH_TREF_133MHZ_8K 0x09 +#define DTH_TREF_166MHZ_8K 0x0A +#define DTH_TREF_200MHZ_8K 0x0B +#define DTH_TWCL_SHIFT 20 +#define DTH_TWCL_MASK 0x7 +#define DTH_TWCL_BASE 1 +#define DTH_TWCL_MIN 1 +#define DTH_TWCL_MAX 2 + +#define DRAM_CONFIG_LOW 0x90 +#define DCL_DLL_Disable (1<<0) +#define DCL_D_DRV (1<<1) +#define DCL_QFC_EN (1<<2) +#define DCL_DisDqsHys (1<<3) +#define DCL_Burst2Opt (1<<5) +#define DCL_DramInit (1<<8) +#define DCL_DualDIMMen (1<<9) +#define DCL_DramEnable (1<<10) +#define DCL_MemClrStatus (1<<11) +#define DCL_ESR (1<<12) +#define DCL_SRS (1<<13) +#define DCL_128BitEn (1<<16) +#define DCL_DimmEccEn (1<<17) +#define DCL_UnBuffDimm (1<<18) +#define DCL_32ByteEn (1<<19) +#define DCL_x4DIMM_SHIFT 20 +#define DCL_DisInRcvrs (1<<24) +#define DCL_BypMax_SHIFT 25 +#define DCL_En2T (1<<28) +#define DCL_UpperCSMap (1<<29) + +#define DRAM_CONFIG_HIGH 0x94 +#define DCH_ASYNC_LAT_SHIFT 0 +#define DCH_ASYNC_LAT_MASK 0xf +#define DCH_ASYNC_LAT_BASE 0 +#define DCH_ASYNC_LAT_MIN 0 +#define DCH_ASYNC_LAT_MAX 15 +#define DCH_RDPREAMBLE_SHIFT 8 +#define DCH_RDPREAMBLE_MASK 0xf +#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ +#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ +#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_IDLE_LIMIT_SHIFT 16 +#define DCH_IDLE_LIMIT_MASK 0x7 +#define DCH_IDLE_LIMIT_0 0 +#define DCH_IDLE_LIMIT_4 1 +#define DCH_IDLE_LIMIT_8 2 +#define DCH_IDLE_LIMIT_16 3 +#define DCH_IDLE_LIMIT_32 4 +#define DCH_IDLE_LIMIT_64 5 +#define DCH_IDLE_LIMIT_128 6 +#define DCH_IDLE_LIMIT_256 7 +#define DCH_DYN_IDLE_CTR_EN (1 << 19) +#define DCH_MEMCLK_SHIFT 20 +#define DCH_MEMCLK_MASK 0x7 +#define DCH_MEMCLK_100MHZ 0 +#define DCH_MEMCLK_133MHZ 2 +#define DCH_MEMCLK_166MHZ 5 +#define DCH_MEMCLK_200MHZ 7 +#define DCH_MEMCLK_VALID (1 << 25) +#define DCH_MEMCLK_EN0 (1 << 26) +#define DCH_MEMCLK_EN1 (1 << 27) +#define DCH_MEMCLK_EN2 (1 << 28) +#define DCH_MEMCLK_EN3 (1 << 29) + +/* Function 3 */ +#define MCA_NB_CONFIG 0x44 +#define MNC_ECC_EN (1 << 22) +#define MNC_CHIPKILL_EN (1 << 23) +#define SCRUB_CONTROL 0x58 +#define SCRUB_NONE 0 +#define SCRUB_40ns 1 +#define SCRUB_80ns 2 +#define SCRUB_160ns 3 +#define SCRUB_320ns 4 +#define SCRUB_640ns 5 +#define SCRUB_1_28us 6 +#define SCRUB_2_56us 7 +#define SCRUB_5_12us 8 +#define SCRUB_10_2us 9 +#define SCRUB_20_5us 10 +#define SCRUB_41_0us 11 +#define SCRUB_81_9us 12 +#define SCRUB_163_8us 13 +#define SCRUB_327_7us 14 +#define SCRUB_655_4us 15 +#define SCRUB_1_31ms 16 +#define SCRUB_2_62ms 17 +#define SCRUB_5_24ms 18 +#define SCRUB_10_49ms 19 +#define SCRUB_20_97ms 20 +#define SCRUB_42ms 21 +#define SCRUB_84ms 22 +#define SC_DRAM_SCRUB_RATE_SHFIT 0 +#define SC_DRAM_SCRUB_RATE_MASK 0x1f +#define SC_L2_SCRUB_RATE_SHIFT 8 +#define SC_L2_SCRUB_RATE_MASK 0x1f +#define SC_L1D_SCRUB_RATE_SHIFT 16 +#define SC_L1D_SCRUB_RATE_MASK 0x1f +#define SCRUB_ADDR_LOW 0x5C +#define SCRUB_ADDR_HIGH 0x60 +#define NORTHBRIDGE_CAP 0xE8 +#define NBCAP_128Bit (1 << 0) +#define NBCAP_MP (1 << 1) +#define NBCAP_BIG_MP (1 << 2) +#define NBCAP_ECC (1 << 3) +#define NBCAP_CHIPKILL_ECC (1 << 4) +#define NBCAP_MEMCLK_SHIFT 5 +#define NBCAP_MEMCLK_MASK 3 +#define NBCAP_MEMCLK_100MHZ 3 +#define NBCAP_MEMCLK_133MHZ 2 +#define NBCAP_MEMCLK_166MHZ 1 +#define NBCAP_MEMCLK_200MHZ 0 +#define NBCAP_MEMCTRL (1 << 8) + + +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) + +#include "raminit.h" +//struct definitions + +struct link_pair_st { + device_t udev; + uint32_t upos; + uint32_t uoffs; + device_t dev; + uint32_t pos; + uint32_t offs; + +} __attribute__((packed)); + +struct sys_info { + uint8_t ctrl_present[NODE_NUMS]; + struct mem_controller ctrl[NODE_NUMS]; + + uint32_t nodes; + struct link_pair_st link_pair[16];// enough? only in_conherent + uint32_t link_pair_num; + uint32_t ht_c_num; + uint32_t sbdn; + uint32_t sblk; + uint32_t sbbusn; +} __attribute__((packed)); + +#endif /* AMDK8_PRE_F_H */ Property changes on: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_pre_f.h ___________________________________________________________________ Added: svn:keywords + Author Date Id Revision Added: svn:mergeinfo + Added: svn:eol-style + native Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-04 20:18:42 UTC (rev 4337) @@ -169,7 +169,7 @@ */ cmd_ref = 0x04e20707; /* Registered */ dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW); - if (dcl & DCL_UnBufDimm) { + if (dcl & DCL_UnBuffDimm) { cmd_ref = 0x000D0701; /* Unbuffered */ } cmd = pci_read_config32(dev, 0xd4); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-06-04 20:18:42 UTC (rev 4337) @@ -3,9 +3,6 @@ 2004.12 yhlu add D0 support 2005.02 yhlu add E0 memory hole support */ -#if K8_REV_F_SUPPORT == 1 - #include "raminit_f.c" -#else #include #include @@ -26,44 +23,23 @@ static void hard_reset(void); #endif -#if 1 static void setup_resource_map(const unsigned int *register_values, int max) { int i; -// print_debug("setting up resource map...."); -#if 0 - print_debug("\r\n"); -#endif - for(i = 0; i < max; i += 3) { +// printk_debug("setting up resource map...."); + for (i = 0; i < max; i += 3) { device_t dev; unsigned where; unsigned long reg; -#if 0 - #if CONFIG_USE_PRINTK_IN_CAR - prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]); - #else - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); - print_debug("\r\n"); - #endif -#endif dev = register_values[i] & ~0xfff; where = register_values[i] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2]; pci_write_config32(dev, where, reg); -#if 0 - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2] & ~register_values[i+1]; - pci_write_config32(register_values[i], reg); -#endif } -// print_debug("done.\r\n"); +// printk_debug("done.\n"); } -#endif static int controller_present(const struct mem_controller *ctrl) { @@ -78,7 +54,8 @@ { static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ + /* Careful set limit registers before base registers which + contain the enables */ /* DRAM Limit i Registers * F1:0x44 i = 0 * F1:0x4C i = 1 @@ -547,48 +524,26 @@ int i; int max; -#if 1 if (!controller_present(ctrl)) { -// print_debug("No memory controller present\r\n"); +// printk_debug("No memory controller present\n"); return; } -#endif - print_spew("setting up CPU"); - print_spew_hex8(ctrl->node_id); - print_spew(" northbridge registers\r\n"); + printk_spew("setting up CPU%02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); - for(i = 0; i < max; i += 3) { + for (i = 0; i < max; i += 3) { device_t dev; unsigned where; unsigned long reg; -#if 0 - #if CONFIG_USE_PRINTK_IN_CAR - prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]); - #else - print_spew_hex32(register_values[i]); - print_spew(" <-"); - print_spew_hex32(register_values[i+2]); - print_spew("\r\n"); - #endif -#endif dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; where = register_values[i] & 0xfff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2]; pci_write_config32(dev, where, reg); -#if 0 - - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(register_values[i], reg); -#endif } - print_spew("done.\r\n"); + printk_spew("done.\n"); } - static void hw_enable_ecc(const struct mem_controller *ctrl) { uint32_t dcl, nbcap; @@ -632,7 +587,7 @@ */ uint32_t dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - return !(dcl & DCL_UnBufDimm); + return !(dcl & DCL_UnBuffDimm); } struct dimm_size { @@ -720,7 +675,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -776,7 +731,7 @@ pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { + if (sz.rank == 4) { pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); } @@ -787,7 +742,7 @@ dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch |= DCH_MEMCLK_EN0 << index; #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { + if (sz.rank == 4) { dch |= DCH_MEMCLK_EN0 << (index + 2); } #endif @@ -809,7 +764,7 @@ map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { + if (sz.rank == 4) { map &= ~(0xf << ( (index + 2) * 4)); } #endif @@ -817,10 +772,10 @@ /* Make certain side1 of the dimm is at least 32MB */ if (sz.side1 >= (25 +3)) { - if(is_cpu_pre_d0()) { + if (is_cpu_pre_d0()) { map |= (sz.side1 - (25 + 3)) << (index *4); #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { + if (sz.rank == 4) { map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4); } #endif @@ -828,7 +783,7 @@ else { map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4); #if QRANK_DIMM_SUPPORT == 1 - if(sz.rank == 4) { + if (sz.rank == 4) { map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4); } #endif @@ -843,7 +798,7 @@ { int i; - for(i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (!(dimm_mask & (1 << i))) { continue; @@ -881,7 +836,7 @@ limit_reg = 0x44 + index; base_reg = 0x40 + index; - for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) { + for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) { pci_write_config32(device, limit_reg, limit); pci_write_config32(device, base_reg, base); } @@ -895,13 +850,11 @@ } /* Report the amount of memory. */ - print_spew("RAM: 0x"); - print_spew_hex32(tom_k); - print_spew(" KB\r\n"); + printk_spew("RAM: 0x%08x kB\n", tom_k); /* Now set top of memory */ msr_t msr; - if(tom_k > (4*1024*1024)) { + if (tom_k > (4*1024*1024)) { msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); @@ -912,7 +865,7 @@ */ if (tom_k >= 0x003f0000) { #if HW_MEM_HOLE_SIZEK != 0 - if(hole_startk != 0) { + if (hole_startk != 0) { tom_k = hole_startk; } else #endif @@ -965,7 +918,7 @@ chip_selects = 0; common_size = 0; common_cs_mode = 0; - for(index = 0; index < 8; index++) { + for (index = 0; index < 8; index++) { unsigned size; unsigned cs_mode; uint32_t value; @@ -988,12 +941,12 @@ value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); cs_mode =( value >> ((index>>1)*4)) & 0xf; - if(cs_mode == 0 ) continue; - if(common_cs_mode == 0) { + if (cs_mode == 0 ) continue; + if (common_cs_mode == 0) { common_cs_mode = cs_mode; } - /* The size differed fail */ - if(common_cs_mode != cs_mode) { + /* The cs_mode differed fail */ + if (common_cs_mode != cs_mode) { return 0; } } @@ -1007,12 +960,12 @@ } /* Find the bits of csbase that we need to interleave on */ - if(is_cpu_pre_d0()){ + if (is_cpu_pre_d0()){ csbase_inc = 1 << csbase_low_shift[common_cs_mode]; - if(is_dual_channel(ctrl)) { + if (is_dual_channel(ctrl)) { /* Also we run out of address mask bits if we try and interleave 8 4GB dimms */ if ((bits == 3) && (common_size == (1 << (32 - 3)))) { -// print_debug("8 4GB chip selects cannot be interleaved\r\n"); +// printk_debug("8 4GB chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -1020,9 +973,9 @@ } else { csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode]; - if(is_dual_channel(ctrl)) { - if( (bits==3) && (common_cs_mode > 8)) { -// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n"); + if (is_dual_channel(ctrl)) { + if ( (bits==3) && (common_cs_mode > 8)) { +// printk_debug("8 cs_mode>8 chip selects cannot be interleaved\n"); return 0; } csbase_inc <<=1; @@ -1036,7 +989,7 @@ csbase = 0 | 1; csmask = (((common_size << bits) - 1) << 21); csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc); - for(index = 0; index < 8; index++) { + for (index = 0; index < 8; index++) { uint32_t value; value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); @@ -1049,7 +1002,7 @@ csbase += csbase_inc; } - print_spew("Interleaved\r\n"); + printk_spew("Interleaved\n"); /* Return the memory size in K */ return common_size << (15 + bits); @@ -1061,14 +1014,14 @@ /* Remember which registers we have used in the high 8 bits of tom */ tom = 0; - for(;;) { - /* Find the largest remaining canidate */ - unsigned index, canidate; + for (;;) { + /* Find the largest remaining candidate */ + unsigned index, candidate; uint32_t csbase, csmask; unsigned size; csbase = 0; - canidate = 0; - for(index = 0; index < 8; index++) { + candidate = 0; + for (index = 0; index < 8; index++) { uint32_t value; value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); @@ -1086,11 +1039,12 @@ if (tom & (1 << (index + 24))) { continue; } - /* I have a new canidate */ + /* I have a new candidate */ csbase = value; - canidate = index; + candidate = index; } - /* See if I have found a new canidate */ + + /* See if I have found a new candidate */ if (csbase == 0) { break; } @@ -1099,7 +1053,7 @@ size = csbase >> 21; /* Remember I have used this register */ - tom |= (1 << (canidate + 24)); + tom |= (1 << (candidate + 24)); /* Recompute the cs base register value */ csbase = (tom << 21) | 1; @@ -1112,9 +1066,9 @@ csmask |= 0xfe00; /* For now don't optimize */ /* Write the new base register */ - pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase); + pci_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase); /* Write the new mask register */ - pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask); + pci_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask); } /* Return the memory size in K */ @@ -1127,7 +1081,7 @@ unsigned end_k; /* Find the last memory address used */ end_k = 0; - for(node_id = 0; node_id < max_node_id; node_id++) { + for (node_id = 0; node_id < max_node_id; node_id++) { uint32_t limit, base; unsigned index; index = node_id << 3; @@ -1149,12 +1103,14 @@ read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { - print_debug("Interleaving disabled\r\n"); + printk_debug("Interleaving disabled\n"); tom_k = 0; } + if (!tom_k) { tom_k = order_chip_selects(ctrl); } + /* Compute the memory base address */ base_k = memory_end_k(ctrl, ctrl->node_id); tom_k += base_k; @@ -1164,16 +1120,15 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask) { - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\r\n"); + printk_debug("disabling dimm %02x\n", index); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); dimm_mask &= ~(1 << index); return dimm_mask; } -static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask) +static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, + long dimm_mask) { int i; int registered; @@ -1182,7 +1137,7 @@ uint32_t dcl; unbuffered = 0; registered = 0; - for(i = 0; (i < DIMM_SOCKETS); i++) { + for (i = 0; (i < DIMM_SOCKETS); i++) { int value; if (!(dimm_mask & (1 << i))) { continue; @@ -1191,6 +1146,7 @@ if (value < 0) { return -1; } + /* Registered dimm ? */ if (value & (1 << 1)) { registered = 1; @@ -1205,10 +1161,10 @@ } dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - dcl &= ~DCL_UnBufDimm; + dcl &= ~DCL_UnBuffDimm; if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) { - dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */ + dcl |= DCL_UnBuffDimm; /* set DCL_DualDIMMen too? */ /* set DCL_En2T if you have non-equal DDR mem types! */ @@ -1217,17 +1173,17 @@ dcl |= DCL_UpperCSMap; } } else { - dcl |= DCL_UnBufDimm; + dcl |= DCL_UnBuffDimm; } } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); -#if 0 + if (is_registered(ctrl)) { - print_debug("Registered\r\n"); + printk_spew("Registered\n"); } else { - print_debug("Unbuffered\r\n"); + printk_spew("Unbuffered\n"); } -#endif + return dimm_mask; } @@ -1236,7 +1192,7 @@ unsigned dimm_mask; int i; dimm_mask = 0; - for(i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < DIMM_SOCKETS; i++) { int byte; unsigned device; device = ctrl->channel0[i]; @@ -1294,7 +1250,7 @@ if (!(nbcap & NBCAP_128Bit)) { goto single_channel; } - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { + for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { unsigned device0, device1; int value0, value1; int j; @@ -1304,7 +1260,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for(j = 0; j < ARRAY_SIZE(addresses); j++) { + for (j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr); @@ -1320,7 +1276,7 @@ } } } - print_spew("Enabling dual channel memory\r\n"); + printk_spew("Enabling dual channel memory\n"); uint32_t dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_32ByteEn; @@ -1350,7 +1306,7 @@ { static const struct mem_param speed[] = { { - .name = "100Mhz\r\n", + .name = "100Mhz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1364,7 +1320,7 @@ .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, { - .name = "133Mhz\r\n", + .name = "133Mhz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1378,7 +1334,7 @@ .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, { - .name = "166Mhz\r\n", + .name = "166Mhz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1392,7 +1348,7 @@ .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, { - .name = "200Mhz\r\n", + .name = "200Mhz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1410,7 +1366,7 @@ }, }; const struct mem_param *param; - for(param = &speed[0]; param->cycle_time ; param++) { + for (param = &speed[0]; param->cycle_time ; param++) { if (min_cycle_time > (param+1)->cycle_time) { break; } @@ -1418,10 +1374,7 @@ if (!param->cycle_time) { die("min_cycle_time to low"); } - print_spew(param->name); -#ifdef DRAM_MIN_CYCLE_TIME - print_debug(param->name); -#endif + printk_spew("%s\n", param->name); return param; } @@ -1458,7 +1411,7 @@ /* Compute the least latency with the fastest clock supported * by both the memory controller and the dimms. */ - for(i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < DIMM_SOCKETS; i++) { int new_cycle_time, new_latency; int index; int latencies; @@ -1489,7 +1442,7 @@ latency = log2(latencies) -2; /* Loop through and find a fast clock with a low latency */ - for(index = 0; index < 3; index++, latency++) { + for (index = 0; index < 3; index++, latency++) { int spd_value; if ((latency < 2) || (latency > 4) || (!(latencies & (1 << latency)))) { @@ -1522,7 +1475,7 @@ * any that cannot support the selected memclk and cas latency. */ - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { + for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int latencies; int latency; int index; @@ -1530,6 +1483,7 @@ if (!(dimm_mask & (1 << i))) { continue; } + latencies = spd_read_byte(ctrl->channel0[i], 18); if (latencies < 0) goto hw_error; if (latencies == 0) { @@ -1540,7 +1494,7 @@ latency = log2(latencies) -2; /* Walk through searching for the selected latency */ - for(index = 0; index < 3; index++, latency++) { + for (index = 0; index < 3; index++, latency++) { if (!(latencies & (1 << latency))) { continue; } @@ -1569,21 +1523,21 @@ #if 0 //down speed for full load 4 rank support #if QRANK_DIMM_SUPPORT - if(dimm_mask == (3|(3<channel0[i]); i++) { + for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int val; if (!(dimm_mask & (1 << i))) { continue; } val = spd_read_byte(ctrl->channel0[i], 5); - if(val!=ranks) { + if (val!=ranks) { ranks = val; break; } } - if(ranks==4) { - if(min_cycle_time <= 0x50 ) { + if (ranks==4) { + if (min_cycle_time <= 0x50 ) { min_cycle_time = 0x60; } } @@ -1599,8 +1553,8 @@ value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT); #if 0 /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/ - if(!is_cpu_pre_e0()) { - if(min_cycle_time==0x50) { + if (!is_cpu_pre_e0()) { + if (min_cycle_time==0x50) { value |= 1<<31; } } @@ -1610,6 +1564,7 @@ pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 }; + /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); @@ -1852,7 +1807,7 @@ dimm = 1<<(DCL_x4DIMM_SHIFT+i); #if QRANK_DIMM_SUPPORT == 1 - if(rank==4) { + if (rank==4) { dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } #endif @@ -1886,7 +1841,7 @@ int dimms; unsigned index; dimms = 0; - for(index = 0; index < 8; index += 2) { + for (index = 0; index < 8; index += 2) { uint32_t csbase; csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2))); if (csbase & 1) { @@ -1941,7 +1896,7 @@ clocks = param->dtl_trwt[lat][mtype]; if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) { - die("Unknown Trwt\r\n"); + die("Unknown Trwt\n"); } dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); @@ -1976,7 +1931,7 @@ slots = 0; - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { if (ctrl->channel0[i]) { slots += 1; } @@ -2061,7 +2016,7 @@ int i; init_Tref(ctrl, param); - for(i = 0; i < DIMM_SOCKETS; i++) { + for (i = 0; i < DIMM_SOCKETS; i++) { int rc; if (!(dimm_mask & (1 << i))) { continue; @@ -2114,7 +2069,7 @@ long dimm_mask; #if 1 if (!controller_present(ctrl)) { -// print_debug("No memory controller present\r\n"); +// printk_debug("No memory controller present\n"); return; } #endif @@ -2122,7 +2077,7 @@ activate_spd_rom(ctrl); dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_debug("No memory for this cpu\r\n"); + printk_debug("No memory for this cpu\n"); return; } dimm_mask = spd_enable_2channels(ctrl, dimm_mask); @@ -2146,7 +2101,7 @@ return; hw_spd_err: /* Unrecoverable error reading SPD data */ - print_err("SPD error - reset\r\n"); + print_err("SPD error - reset\n"); hard_reset(); return; } @@ -2164,30 +2119,30 @@ carry_over = (4*1024*1024) - hole_startk; - for(ii=controllers - 1;ii>i;ii--) { + for (ii=controllers - 1;ii>i;ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); - for(j = 0; j < controllers; j++) { + for (j = 0; j < controllers; j++) { pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2)); pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); } } limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); - for(j = 0; j < controllers; j++) { + for (j = 0; j < controllers; j++) { pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); } dev = ctrl[i].f1; base = pci_read_config32(dev, 0x40 + (i << 3)); basek = (base & 0xffff0000) >> 2; - if(basek == hole_startk) { + if (basek == hole_startk) { //don't need set memhole here, because hole off set will be 0, overflow //so need to change base reg instead, new basek will be 4*1024*1024 base &= 0x0000ffff; base |= (4*1024*1024)<<2; - for(j = 0; j < controllers; j++) { + for (j = 0; j < controllers; j++) { pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); } } @@ -2218,7 +2173,7 @@ * we need to decrease it. */ uint32_t basek_pri; - for(i=0; i> 2; - if(base_k == hole_startk) { + if (base_k == hole_startk) { /* decrease memory hole startk to make sure it is * in the middle of the previous node */ @@ -2238,7 +2193,7 @@ #endif /* Find node number that needs the memory hole configured */ - for(i=0; i= TIMEOUT_LOOPS) { - print_debug(" failed\r\n"); + printk_debug(" failed\n"); continue; } @@ -2365,13 +2318,13 @@ } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) ); } - print_debug(" done\r\n"); + printk_debug(" done\n"); } #if HW_MEM_HOLE_SIZEK != 0 // init hw mem hole here /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ - if(!is_cpu_pre_e0()) + if (!is_cpu_pre_e0()) set_hw_mem_hole(controllers, ctrl); #endif @@ -2384,34 +2337,19 @@ 5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node) */ -#if USE_DCACHE_RAM == 0 - /* Make certain the first 1M of memory is intialized */ - print_debug("Clearing initial memory region: "); - - /* Use write combine caching while we setup the first 1M */ - cache_lbmem(MTRR_TYPE_WRCOMB); - - /* clear memory 1meg */ - clear_memory((void *)0, CONFIG_LB_MEM_TOPK << 10); - - /* The first 1M is now setup, use it */ - cache_lbmem(MTRR_TYPE_WRBACK); - - print_debug(" done\r\n"); -#endif } -#if USE_DCACHE_RAM == 1 static void set_sysinfo_in_ram(unsigned val) { } -static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) +static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, + const uint16_t *spd_addr) { int i; int j; struct mem_controller *ctrl; - for(i=0;inode_id = i; ctrl->f0 = PCI_DEV(0, 0x18+i, 0); @@ -2419,14 +2357,11 @@ ctrl->f2 = PCI_DEV(0, 0x18+i, 2); ctrl->f3 = PCI_DEV(0, 0x18+i, 3); - if(spd_addr == (void *)0) continue; + if (spd_addr == (void *)0) continue; - for(j=0;jchannel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j]; ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j]; } } } -#endif - -#endif Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-06-04 01:57:03 UTC (rev 4336) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-06-04 20:18:42 UTC (rev 4337) @@ -712,11 +712,9 @@ reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - printk_spew("done.\n"); } - static int is_dual_channel(const struct mem_controller *ctrl) { uint32_t dcl; @@ -724,7 +722,6 @@ return dcl & DCL_Width128; } - static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. @@ -738,7 +735,6 @@ return !!(nbcap & NBCAP_128Bit); } - static int is_registered(const struct mem_controller *ctrl) { /* Test to see if we are dealing with registered SDRAM. @@ -834,7 +830,8 @@ static void set_dimm_size(const struct mem_controller *ctrl, - struct dimm_size *sz, unsigned index, struct mem_info *meminfo) + struct dimm_size *sz, unsigned index, + struct mem_info *meminfo) { uint32_t base0, base1; @@ -1009,14 +1006,13 @@ return -1; /* Report SPD error */ } set_dimm_size(ctrl, sz, i, meminfo); - set_dimm_cs_map (ctrl, sz, i, meminfo); + set_dimm_cs_map(ctrl, sz, i, meminfo); } return meminfo->dimm_mask; } - static void route_dram_accesses(const struct mem_controller *ctrl, - unsigned long base_k, unsigned long limit_k) + unsigned long base_k, unsigned long limit_k) { /* Route the addresses to the controller node */ unsigned node_id; @@ -1045,7 +1041,6 @@ } } - static void set_top_mem(unsigned tom_k, unsigned hole_startk) { /* Error if I don't have memory */ @@ -1056,9 +1051,9 @@ /* Report the amount of memory. */ printk_debug("RAM: 0x%08x kB\n", tom_k); + /* Now set top of memory */ msr_t msr; if (tom_k > (4*1024*1024)) { - /* Now set top of memory */ msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); @@ -1161,7 +1156,6 @@ csbase_inc <<=1; } - /* Compute the initial values for csbase and csbask. * In csbase just set the enable bit and the base to zero. * In csmask set the mask bits for the size and page level interleave. @@ -1189,6 +1183,7 @@ /* Return the memory size in K */ return common_size << ((27-10) + bits); } + static unsigned long order_chip_selects(const struct mem_controller *ctrl) { unsigned long tom; @@ -1278,7 +1273,6 @@ return end_k; } - static void order_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo) { @@ -1291,11 +1285,11 @@ printk_debug("Interleaving disabled\n"); tom_k = 0; } - + if (!tom_k) { tom_k = order_chip_selects(ctrl); } - + /* Compute the memory base address */ base_k = memory_end_k(ctrl, ctrl->node_id); tom_k += base_k; @@ -1303,7 +1297,6 @@ set_top_mem(tom_k, 0); } - static long disable_dimm(const struct mem_controller *ctrl, unsigned index, struct mem_info *meminfo) { @@ -1326,7 +1319,6 @@ return meminfo->dimm_mask; } - static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo) { @@ -1380,17 +1372,14 @@ } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); -#if 1 if (meminfo->is_registered) { - printk_debug("Registered\n"); + printk_spew("Registered\n"); } else { - printk_debug("Unbuffered\n"); + printk_spew("Unbuffered\n"); } -#endif return meminfo->dimm_mask; } - static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) { unsigned dimm_mask; @@ -1624,7 +1613,7 @@ if (!param->cycle_time) { die("min_cycle_time to low"); } - printk_debug("%s\n", param->name); + printk_spew("%s\n", param->name); return param; } @@ -2088,7 +2077,6 @@ return 1; } - static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask) { @@ -2126,17 +2114,14 @@ if (clocks < DTL_TRAS_MIN) { clocks = DTL_TRAS_MIN; } - if (clocks > DTL_TRAS_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE; if (old_clocks >= clocks) { // someone did it? return 1; } - dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT); dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT); pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); @@ -2201,7 +2186,6 @@ return 1; } - static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { @@ -2235,7 +2219,6 @@ #endif } - static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, struct mem_info *meminfo) { @@ -2363,7 +2346,6 @@ pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); } - static void set_ecc(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { @@ -2456,19 +2438,16 @@ set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr"); } - static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param) { set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd"); } - static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param) { set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS } - static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { static const uint8_t faw_1k[] = {8, 10, 13, 14}; @@ -2486,10 +2465,8 @@ } set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow"); - } - static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) { uint32_t dch; @@ -2507,7 +2484,6 @@ pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } - static void set_SlowAccessMode(const struct mem_controller *ctrl) { uint32_t dch; @@ -2519,7 +2495,6 @@ pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } - /* DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20 DRAM_ADDR_TIMING_CTRL 04, 0x24 @@ -2724,7 +2699,6 @@ #endif } - static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { @@ -2737,14 +2711,12 @@ pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm); } - static void set_RdWrQByp(const struct mem_controller *ctrl, const struct mem_param *param) { set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp"); } - static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) @@ -3058,14 +3030,6 @@ /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */ memreset(controllers, ctrl); -#if 0 - printk_debug("prepare to InitDram:"); - for (i=0; i<10; i++) { - printk_debug("%08x", i); - print_debug("\b\b\b\b\b\b\b\b"); - } - printk_debug("\n"); -#endif /* lets override the rest of the routine */ if (suspend) { @@ -3241,9 +3205,8 @@ } - static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, - const uint16_t *spd_addr) + const uint16_t *spd_addr) { int i; int j; From mylesgw at gmail.com Thu Jun 4 22:19:08 2009 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 4 Jun 2009 14:19:08 -0600 Subject: [coreboot] [PATCH] raminit cleanup for K8 In-Reply-To: <13426df10906041217n36007d53yc49031d776787223@mail.gmail.com> References: <2831fecf0906041203s568e4c1dv757020979723fd8c@mail.gmail.com> <13426df10906041217n36007d53yc49031d776787223@mail.gmail.com> Message-ID: <2831fecf0906041319v5c9510d4q5161c6ee9dc0e780@mail.gmail.com> On Thu, Jun 4, 2009 at 1:17 PM, ron minnich wrote: > Acked-by: Ronald G. Minnich > Rev 4337. Thanks, Myles From christian.leber at ziti.uni-heidelberg.de Fri Jun 5 00:31:29 2009 From: christian.leber at ziti.uni-heidelberg.de (Christian Leber) Date: Fri, 5 Jun 2009 00:31:29 +0200 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20906040908ub4333f2y1716ec2d0bfab83@mail.gmail.com> References: <200906041518.10203.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906040908ub4333f2y1716ec2d0bfab83@mail.gmail.com> Message-ID: <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> On Thursday 04 June 2009 18:08:59 Marc Jones wrote: Hi Marc > Thanks, As Myles pointed out, my comment didn't make sense. Putting it > the errata is the next step. I attached a log without htx card, the port80 shows 0x35. Probably the 42 is in the end not exactly the same like the 62. Christian -------------- next part -------------- ot-2.0.0-r4333:4334M_Fallback Wed Jun 3 18:42:34 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1062, current patch id = 0x00000000 microcode: patch id to apply = 0x0100009f microcode: updated to patch id = 0x0100009f success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 done cpuSetAMDPCI 01 From uwe at hermann-uwe.de Fri Jun 5 00:47:28 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 00:47:28 +0200 Subject: [coreboot] [PATCH] flashrom: Enable SST49* protection register debug Message-ID: <20090604224728.GD18065@greenwood> See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -------------- next part -------------- A non-text attachment was scrubbed... Name: flashrom_uncomment_debug.patch Type: text/x-diff Size: 2128 bytes Desc: not available URL: From mylesgw at gmail.com Fri Jun 5 00:56:07 2009 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 4 Jun 2009 16:56:07 -0600 Subject: [coreboot] [PATCH] flashrom: Enable SST49* protection register debug In-Reply-To: <20090604224728.GD18065@greenwood> References: <20090604224728.GD18065@greenwood> Message-ID: <2831fecf0906041556v6123436g44de3176b667734@mail.gmail.com> On Thu, Jun 4, 2009 at 4:47 PM, Uwe Hermann wrote: > See patch. - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); + printf("lockbits at address=%p is 0x%01x\n", (void *)(0xFFC00000 - size + (i * 65536) + 2), chip_readb(bios + (i * 65536) + 2) ); You probably meant printf_debug there too. - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); + printf_debug("lockbits at address=%p is 0x%01x\n", (void *)(0xFFc00000 - size + address + 2), chip_readb(bios + address + 2) ); I'd prefer 0xffc000 or 0xFFC000... Acked-by: Myles Watson Thanks, Myles From marcj303 at gmail.com Fri Jun 5 01:04:56 2009 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 4 Jun 2009 17:04:56 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> References: <200906041518.10203.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906040908ub4333f2y1716ec2d0bfab83@mail.gmail.com> <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> Message-ID: <534e5dc20906041604i2179c536wdd90a769eb3f4874@mail.gmail.com> On Thu, Jun 4, 2009 at 4:31 PM, Christian Leber wrote: > On Thursday 04 June 2009 18:08:59 Marc Jones wrote: > > Hi Marc > >> Thanks, As Myles pointed out, my comment didn't make sense. Putting it >> the errata is the next step. > > I attached a log without htx card, the port80 shows 0x35. > > Probably the 42 is in the end not exactly the same like the 62. I think it should just be a package difference. It looks like you hit the same thing as Ward without the HTX card. Not sure why that changes things. Marc -- http://marcjonesconsulting.com From urjaman at gmail.com Fri Jun 5 01:20:49 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 02:20:49 +0300 Subject: [coreboot] [flashrom] [patch] Some exact bustypes Message-ID: <460f92b70906041620j3facc29kf3334845fbe75f5d@mail.gmail.com> Exact bustypes for Atmel AT29C010A, AT29C020, AT29C040A, AT49BV512, AT49F002, AMIC A29040B, A49LF040A, EMST F49B002UA, EON EN29F002, Intel 28F001BX-B, 28F001BX-T, Winbond W29C020C and W29C040P. Checked from datasheets. A49LF040A is LPC, others parallel. Signed-off-by: Urja Rannikko --- patch also inlined: Index: flashchips.c =================================================================== --- flashchips.c (revision 558) +++ flashchips.c (working copy) @@ -401,7 +401,7 @@ { .vendor = "Atmel", .name = "AT29C010A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_29C010A, .total_size = 128, @@ -416,7 +416,7 @@ { .vendor = "Atmel", .name = "AT29C020", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_29C020, .total_size = 256, @@ -431,7 +431,7 @@ { .vendor = "Atmel", .name = "AT29C040A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_29C040A, .total_size = 512, @@ -581,7 +581,7 @@ { .vendor = "Atmel", .name = "AT49BV512", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_49BV512, .total_size = 64, @@ -596,7 +596,7 @@ { .vendor = "Atmel", .name = "AT49F002(N)", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_49F002N, .total_size = 256, @@ -611,7 +611,7 @@ { .vendor = "Atmel", .name = "AT49F002(N)T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_49F002NT, .total_size = 256, @@ -671,7 +671,7 @@ { .vendor = "AMIC", .name = "A29040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMIC_ID_NOPREFIX, .model_id = AMIC_A29040B, .total_size = 512, @@ -686,7 +686,7 @@ { .vendor = "AMIC", .name = "A49LF040A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = AMIC_ID_NOPREFIX, .model_id = AMIC_A49LF040A, .total_size = 512, @@ -701,7 +701,7 @@ { .vendor = "EMST", .name = "F49B002UA", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EMST_ID, .model_id = EMST_F49B002UA, .total_size = 256, @@ -716,7 +716,7 @@ { .vendor = "EON", .name = "EN29F002(A)(N)B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EON_ID, .model_id = EN_29F002B, .total_size = 256, @@ -731,7 +731,7 @@ { .vendor = "EON", .name = "EN29F002(A)(N)T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EON_ID, .model_id = EN_29F002T, .total_size = 256, @@ -806,7 +806,7 @@ { .vendor = "Intel", .name = "28F001BX-B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, .model_id = P28F001BXB, .total_size = 128, @@ -821,7 +821,7 @@ { .vendor = "Intel", .name = "28F001BX-T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, .model_id = P28F001BXT, .total_size = 128, @@ -2336,7 +2336,7 @@ { .vendor = "Winbond", .name = "W29C020C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, .model_id = W_29C020C, .total_size = 256, @@ -2351,7 +2351,7 @@ { .vendor = "Winbond", .name = "W29C040P", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, .model_id = W_29C040P, .total_size = 512, -- urjaman -------------- next part -------------- A non-text attachment was scrubbed... Name: some_bustypes.patch Type: application/octet-stream Size: 3544 bytes Desc: not available URL: From svn at coreboot.org Fri Jun 5 02:22:25 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 02:22:25 +0200 Subject: [coreboot] [v2] r4338 - trunk/coreboot-v2/src/northbridge/intel/i82810 Message-ID: Author: uwe Date: 2009-06-05 02:22:25 +0200 (Fri, 05 Jun 2009) New Revision: 4338 Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c Log: Add a hopefully more correct and flexible set_dram_buffer_strength() function based on test results with many different DIMMs. Tested by Uwe Hermann on hardware. Might need a small increase of ROM_IMAGE_SIZE for some boards, we'll see. Signed-off-by: Elia Yehuda Acked-by: Corey Osgood Acked-by: Uwe Hermann Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2009-06-04 20:18:42 UTC (rev 4337) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2009-06-05 00:22:25 UTC (rev 4338) @@ -72,6 +72,12 @@ /* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128, }; +struct dimm_info { + u8 ds; /* dual-sided */ + u8 ss; /* single-sided */ + u8 size; +}; + /*----------------------------------------------------------------------------- SDRAM configuration functions. -----------------------------------------------------------------------------*/ @@ -275,10 +281,77 @@ * 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided + * + * See also: + * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html */ static void set_dram_buffer_strength(void) { - pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, 0x77da); + struct dimm_info d0, d1; + u16 buff_sc; + + /* Check first slot. */ + d0.size = d0.ds = d0.ss = 0; + if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE) + == SPD_MEMORY_TYPE_SDRAM) { + d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY); + d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1; + d0.ss = !d0.ds; + } + + /* Check second slot. */ + d1.size = d1.ds = d1.ss = 0; + if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE) + == SPD_MEMORY_TYPE_SDRAM) { + d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY); + d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1, + SPD_NUM_DIMM_BANKS) > 1; + d1.ss = !d1.ds; + } + + buff_sc = 0; + + /* Tame the beast... */ + if ((d0.ds && d1.ds) || (d0.ds && d1.ss) || (d0.ss && d1.ds)) + buff_sc |= 1; + if ((d0.size && !d1.size) || (!d0.size && d1.size) || (d0.ss && d1.ss)) + buff_sc |= 1 << 1; + if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ss && d1.ss) + || (d0.ds && d1.ss) || (d0.ss && d1.ds)) + buff_sc |= 1 << 2; + if ((d0.ss && !d1.size) || (!d0.size && d1.ss)) + buff_sc |= 1 << 3; + if ((d0.size && !d1.size) || (!d0.size && d1.size)) + buff_sc |= 1 << 4; + if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ds && d1.ss) + || (d0.ss && d1.ds)) + buff_sc |= 1 << 6; + if ((d0.ss && !d1.size) || (!d0.size && d1.ss) || (d0.ss && d1.ss)) + buff_sc |= 3 << 6; + if ((!d0.size && d1.ss) || (d0.ds && d1.ss) || (d0.ss && d1.ss)) + buff_sc |= 1 << 8; + if (d0.size && !d1.size) + buff_sc |= 3 << 8; + if ((d0.ss && !d1.size) || (d0.ss && d1.ss) || (d0.ss && d1.ds)) + buff_sc |= 1 << 10; + if (!d0.size && d1.size) + buff_sc |= 3 << 10; + if ((d0.size && !d1.size) || (d0.ss && !d1.size) || (!d0.size && d1.ss) + || (d0.ss && d1.ss) || (d0.ds && d1.ss)) + buff_sc |= 1 << 12; + if (d0.size && !d1.size) + buff_sc |= 1 << 13; + if ((!d0.size && d1.size) || (d0.ss && !d1.size) || (d0.ss && d1.ss) + || (d0.ss && d1.ds)) + buff_sc |= 1 << 14; + if (!d0.size && d1.size) + buff_sc |= 1 << 15; + + print_debug("BUFF_SC calculated to 0x"); + print_debug_hex16(buff_sc); + print_debug("\r\n"); + + pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc); } /*----------------------------------------------------------------------------- From ward at gnu.org Fri Jun 5 02:25:18 2009 From: ward at gnu.org (Ward Vandewege) Date: Thu, 4 Jun 2009 20:25:18 -0400 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> References: <200906041518.10203.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906040908ub4333f2y1716ec2d0bfab83@mail.gmail.com> <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> Message-ID: <20090605002518.GA11517@localdomain> On Fri, Jun 05, 2009 at 12:31:29AM +0200, Christian Leber wrote: > On Thursday 04 June 2009 18:08:59 Marc Jones wrote: > > Hi Marc > > > Thanks, As Myles pointed out, my comment didn't make sense. Putting it > > the errata is the next step. > > I attached a log without htx card, the port80 shows 0x35. Same here. And my log is exactly the same. Thanks, Ward. -- Ward Vandewege From uwe at hermann-uwe.de Fri Jun 5 02:27:09 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 02:27:09 +0200 Subject: [coreboot] [patch] fix intel 82810 onboard VGA and SDRAM functions In-Reply-To: References: <4f024cb6dadc710e0f0d4f7a8fcec73c@imap.1and1.com> Message-ID: <20090605002708.GE18065@greenwood> On Fri, May 22, 2009 at 03:54:43AM +0300, Elia Yehuda wrote: > > On Sun, 10 May 2009 15:21:52 +0300, Elia Yehuda wrote: > > > This patch enables the onboard VGA found on 82810 boards and fixes the > > > memory procedures to support different kinds of DIMMs. also, support for > > > 82810e board had been added. The only drawback from this patch is the > > > HAVE_HIGH_TABLES being disabled since it disables (for unknown reason) > > > the onboard VGA. > > > > > > Signed-off-by: Elia Yehuda > > > > Elia, any progress on the high tables stuff yet? It would be real shame to > > see this great code goto the way side. Maybe you could split the patch in > > two and we can get all the non high tables stuff commited to svn? > > > im still waiting for Uwe to try the patch - he has some issues with his > hardware so we > need to have patience. Yeah, sorry for the long delay. I had hardware issues, which I fixed by replacing some dead capacitors on my i810 board. I have successfully tested the (slightly modified for cosmetics) BUFF_SC parts of the patch, which works fine and is thus committed as r4338 (thanks!) > If this won't work out, then i'll do my best and > trace the high-tables > issue myself and update the list as for my findings. > > as for splitting the patch - can be done, but i suggest we wait a bit and > give Uwe a chance In general I recommend to split patches into independent functional units indeed, that makes testing and reviewing a lot easier. Haven't had much luck with the HIGH_TABLES stuff yet, need to look into it some more, will post the remainders of the patch (without the now-committed BUFF_SC parts) later and/or check what's going on with HIGH_TABLES... Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From svn at coreboot.org Fri Jun 5 02:42:18 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 02:42:18 +0200 Subject: [coreboot] [flashrom] r573 - trunk Message-ID: Author: uwe Date: 2009-06-05 02:42:18 +0200 (Fri, 05 Jun 2009) New Revision: 573 Modified: trunk/sst49lfxxxc.c Log: Actually enable the protection register debug output on SST49LF160C and similar chips if -V is supplied. Signed-off-by: Uwe Hermann Acked-by: Myles Watson Modified: trunk/sst49lfxxxc.c =================================================================== --- trunk/sst49lfxxxc.c 2009-06-04 19:25:54 UTC (rev 572) +++ trunk/sst49lfxxxc.c 2009-06-05 00:42:18 UTC (rev 573) @@ -38,28 +38,37 @@ #define STATUS_ESS (1 << 6) #define STATUS_WSMS (1 << 7) -static int write_lockbits_49lfxxxc(chipaddr bios, int size, - unsigned char bits) +static int write_lockbits_49lfxxxc(chipaddr bios, int size, unsigned char bits) { int i, left = size; unsigned long address; - //printf("bios=0x%08lx\n", (unsigned long)bios); + printf_debug("\nbios=0x%08lx\n", bios); for (i = 0; left > 65536; i++, left -= 65536) { - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); + printf_debug("lockbits at address=%p is 0x%01x\n", + (void *)(0xffc00000 - size + (i * 65536) + 2), + chip_readb(bios + (i * 65536) + 2)); chip_writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); + printf_debug("lockbits at address=%p is 0x%01x\n", + (void *)(0xffc00000 - size + address + 2), + chip_readb(bios + address + 2)); chip_writeb(bits, bios + address + 2); address += 32768; - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); + printf_debug("lockbits at address=%p is 0x%01x\n", + (void *)(0xffc00000 - size + address + 2), + chip_readb(bios + address + 2)); chip_writeb(bits, bios + address + 2); address += 8192; - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); + printf_debug("lockbits at address=%p is 0x%01x\n", + (void *)(0xffc00000 - size + address + 2), + chip_readb(bios + address + 2)); chip_writeb(bits, bios + address + 2); address += 8192; - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); + printf_debug("lockbits at address=%p is 0x%01x\n", + (void *)(0xffc00000 - size + address + 2), + chip_readb(bios + address + 2)); chip_writeb(bits, bios + address + 2); return 0; @@ -118,7 +127,6 @@ int probe_49lfxxxc(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; - uint8_t id1, id2; chip_writeb(RESET, bios); From uwe at hermann-uwe.de Fri Jun 5 02:42:43 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 02:42:43 +0200 Subject: [coreboot] [PATCH] flashrom: Enable SST49* protection register debug In-Reply-To: <2831fecf0906041556v6123436g44de3176b667734@mail.gmail.com> References: <20090604224728.GD18065@greenwood> <2831fecf0906041556v6123436g44de3176b667734@mail.gmail.com> Message-ID: <20090605004242.GA10494@greenwood> On Thu, Jun 04, 2009 at 04:56:07PM -0600, Myles Watson wrote: > On Thu, Jun 4, 2009 at 4:47 PM, Uwe Hermann wrote: > > See patch. > - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned > long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); > + printf("lockbits at address=%p is 0x%01x\n", (void *)(0xFFC00000 - > size + (i * 65536) + 2), chip_readb(bios + (i * 65536) + 2) ); > > You probably meant printf_debug there too. True, fixed. > - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned > long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); > + printf_debug("lockbits at address=%p is 0x%01x\n", (void > *)(0xFFc00000 - size + address + 2), chip_readb(bios + address + 2) ); > > I'd prefer 0xffc000 or 0xFFC000... Yep, fixed. > Acked-by: Myles Watson Thanks, r573 with some additional whitespace fixes. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From joe at settoplinux.org Fri Jun 5 05:20:15 2009 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 04 Jun 2009 23:20:15 -0400 Subject: [coreboot] =?utf-8?q?=5Bpatch=5D_fix_intel_82810_onboard_VGA_and_?= =?utf-8?q?SDRAM=09functions?= In-Reply-To: <20090605002708.GE18065@greenwood> References: <4f024cb6dadc710e0f0d4f7a8fcec73c@imap.1and1.com> <20090605002708.GE18065@greenwood> Message-ID: On Fri, 5 Jun 2009 02:27:09 +0200, Uwe Hermann wrote: > On Fri, May 22, 2009 at 03:54:43AM +0300, Elia Yehuda wrote: >> > On Sun, 10 May 2009 15:21:52 +0300, Elia Yehuda > wrote: >> > > This patch enables the onboard VGA found on 82810 boards and fixes > the >> > > memory procedures to support different kinds of DIMMs. also, support > for >> > > 82810e board had been added. The only drawback from this patch is > the >> > > HAVE_HIGH_TABLES being disabled since it disables (for unknown > reason) >> > > the onboard VGA. >> > > >> > > Signed-off-by: Elia Yehuda >> > >> > Elia, any progress on the high tables stuff yet? It would be real > shame to >> > see this great code goto the way side. Maybe you could split the patch > in >> > two and we can get all the non high tables stuff commited to svn? >> >> >> im still waiting for Uwe to try the patch - he has some issues with his >> hardware so we >> need to have patience. > > Yeah, sorry for the long delay. I had hardware issues, which I fixed by > replacing some dead capacitors on my i810 board. > I have successfully tested the (slightly modified for cosmetics) BUFF_SC > parts of the patch, which works fine and is thus committed as r4338 > (thanks!) > > >> If this won't work out, then i'll do my best and >> trace the high-tables >> issue myself and update the list as for my findings. >> >> as for splitting the patch - can be done, but i suggest we wait a bit > and >> give Uwe a chance > > In general I recommend to split patches into independent functional > units indeed, that makes testing and reviewing a lot easier. > > Haven't had much luck with the HIGH_TABLES stuff yet, need to look into > it some more, will post the remainders of the patch (without the > now-committed BUFF_SC parts) later and/or check what's going on with > HIGH_TABLES... > Sweet thanks Uwe :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 10:05:40 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 10:05:40 +0200 Subject: [coreboot] [flashrom] r573 - trunk In-Reply-To: <20090605004245.2994gmx1@mx049.gmx.net> References: <20090605004245.2994gmx1@mx049.gmx.net> Message-ID: <4A28D1D4.6010309@gmx.net> On 05.06.2009 02:42, svn at coreboot.org wrote: > New Revision: 573 > > Modified: > trunk/sst49lfxxxc.c > Log: > Actually enable the protection register debug output on > SST49LF160C and similar chips if -V is supplied. > > Signed-off-by: Uwe Hermann > Acked-by: Myles Watson > > Modified: trunk/sst49lfxxxc.c > =================================================================== > --- trunk/sst49lfxxxc.c 2009-06-04 19:25:54 UTC (rev 572) > +++ trunk/sst49lfxxxc.c 2009-06-05 00:42:18 UTC (rev 573) > @@ -38,28 +38,37 @@ > > for (i = 0; left > 65536; i++, left -= 65536) { > - //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); > + printf_debug("lockbits at address=%p is 0x%01x\n", > + (void *)(0xffc00000 - size + (i * 65536) + 2), > + chip_readb(bios + (i * 65536) + 2)); > chip_writeb(bits, bios + (i * 65536) + 2); > Sorry, I don't get it. Why do you use a base of 0xffc00000 - size for printing the address and bios for printing the contents? There's flash->virtual_memory and flash->virtual_registers. Any reason you recalculate flash->virtual_registers even though it is passed in? Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Fri Jun 5 10:15:35 2009 From: svn at coreboot.org (coreboot) Date: Fri, 05 Jun 2009 08:15:35 -0000 Subject: [coreboot] #95: Run coreboot in VirtualBox In-Reply-To: <039.8e5fad36b203068bd3071c0f2771ba88@coreboot.org> References: <039.8e5fad36b203068bd3071c0f2771ba88@coreboot.org> Message-ID: <048.d230db838de8793ea9842302bb1cd479@coreboot.org> #95: Run coreboot in VirtualBox ----------------------------+----------------------------------------------- Reporter: uwe | Owner: somebody Type: enhancement | Status: reopened Priority: minor | Milestone: Component: misc | Version: Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Comment(by stepan): On the other hand, issue that nobody is working on and that seem to be of too little importance that anyone feels obligated to get the ticket assigned create nothing but white noise in the tracker and make it harder for people who plan to work on _real_ issues by using the tracker. -- Ticket URL: coreboot From svn at coreboot.org Fri Jun 5 10:16:57 2009 From: svn at coreboot.org (coreboot) Date: Fri, 05 Jun 2009 08:16:57 -0000 Subject: [coreboot] #129: Add support for high_tables_base for all chipsets that don't support it yet. In-Reply-To: <043.f0d4d7dbfec3d965f428cea23a580579@coreboot.org> References: <043.f0d4d7dbfec3d965f428cea23a580579@coreboot.org> Message-ID: <052.2c4031cad0d84d5c8403091f7ff97cea@coreboot.org> #129: Add support for high_tables_base for all chipsets that don't support it yet. ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: stepan Type: defect | Status: new Priority: critical | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Changes (by stepan): * owner: somebody => stepan Comment: All chipsets have support code for high tables now, but they're not all tested (and working?) yet. -- Ticket URL: coreboot From svn at coreboot.org Fri Jun 5 10:22:11 2009 From: svn at coreboot.org (coreboot) Date: Fri, 05 Jun 2009 08:22:11 -0000 Subject: [coreboot] #43: Add graphics memory hole to e820 map In-Reply-To: <042.2646597d34d93de14c1c08bf2fa47373@coreboot.org> References: <042.2646597d34d93de14c1c08bf2fa47373@coreboot.org> Message-ID: <051.7d88b7bdb033fe82e65ba5cf6f14cd4b@coreboot.org> #43: Add graphics memory hole to e820 map ---------------------------------+------------------------------------------ Reporter: stepan | Owner: stepan Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Changes (by stepan): * owner: somebody => stepan Comment: The e820 map is generated from the coreboot table memory map by the boot loaders (eg. FILO, GRUB2, SeaBIOS). We started putting more than just RAM areas in there, but I think there's more to be done. -- Ticket URL: coreboot From peter at stuge.se Fri Jun 5 10:37:08 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 5 Jun 2009 10:37:08 +0200 Subject: [coreboot] [flashrom] r573 - trunk In-Reply-To: <4A28D1D4.6010309@gmx.net> References: <20090605004245.2994gmx1@mx049.gmx.net> <4A28D1D4.6010309@gmx.net> Message-ID: <20090605083708.11146.qmail@stuge.se> Carl-Daniel Hailfinger wrote: > Any reason you recalculate It was like that in the code already. I don't know who wrote it initially. //Peter From svn at coreboot.org Fri Jun 5 10:47:37 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 10:47:37 +0200 Subject: [coreboot] [flashrom] r574 - trunk Message-ID: Author: hailfinger Date: 2009-06-05 10:47:37 +0200 (Fri, 05 Jun 2009) New Revision: 574 Modified: trunk/flashchips.c Log: Exact bustypes for Atmel AT29C010A, AT29C020, AT29C040A, AT49BV512, AT49F002, AMIC A29040B, A49LF040A, EMST F49B002UA, EON EN29F002, Intel 28F001BX-B, 28F001BX-T, Winbond W29C020C and W29C040P. Checked from datasheets. A49LF040A is LPC, others parallel. Signed-off-by: Urja Rannikko Acked-by: Carl-Daniel Hailfinger Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-05 00:42:18 UTC (rev 573) +++ trunk/flashchips.c 2009-06-05 08:47:37 UTC (rev 574) @@ -427,7 +427,7 @@ { .vendor = "Atmel", .name = "AT29C010A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_29C010A, .total_size = 128, @@ -443,7 +443,7 @@ { .vendor = "Atmel", .name = "AT29C020", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_29C020, .total_size = 256, @@ -459,7 +459,7 @@ { .vendor = "Atmel", .name = "AT29C040A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_29C040A, .total_size = 512, @@ -610,7 +610,7 @@ { .vendor = "Atmel", .name = "AT49BV512", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_49BV512, .total_size = 64, @@ -626,7 +626,7 @@ { .vendor = "Atmel", .name = "AT49F002(N)", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_49F002N, .total_size = 256, @@ -642,7 +642,7 @@ { .vendor = "Atmel", .name = "AT49F002(N)T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_49F002NT, .total_size = 256, @@ -705,7 +705,7 @@ { .vendor = "AMIC", .name = "A29040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMIC_ID_NOPREFIX, .model_id = AMIC_A29040B, .total_size = 512, @@ -721,7 +721,7 @@ { .vendor = "AMIC", .name = "A49LF040A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = AMIC_ID_NOPREFIX, .model_id = AMIC_A49LF040A, .total_size = 512, @@ -737,7 +737,7 @@ { .vendor = "EMST", .name = "F49B002UA", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EMST_ID, .model_id = EMST_F49B002UA, .total_size = 256, @@ -753,7 +753,7 @@ { .vendor = "EON", .name = "EN29F002(A)(N)B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EON_ID, .model_id = EN_29F002B, .total_size = 256, @@ -769,7 +769,7 @@ { .vendor = "EON", .name = "EN29F002(A)(N)T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EON_ID, .model_id = EN_29F002T, .total_size = 256, @@ -849,7 +849,7 @@ { .vendor = "Intel", .name = "28F001BX-B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, .model_id = P28F001BXB, .total_size = 128, @@ -865,7 +865,7 @@ { .vendor = "Intel", .name = "28F001BX-T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, .model_id = P28F001BXT, .total_size = 128, @@ -2436,7 +2436,7 @@ { .vendor = "Winbond", .name = "W29C020C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, .model_id = W_29C020C, .total_size = 256, @@ -2452,7 +2452,7 @@ { .vendor = "Winbond", .name = "W29C040P", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, .model_id = W_29C040P, .total_size = 512, From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 10:48:54 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 10:48:54 +0200 Subject: [coreboot] [flashrom] [patch] Some exact bustypes In-Reply-To: <460f92b70906041620j3facc29kf3334845fbe75f5d@mail.gmail.com> References: <460f92b70906041620j3facc29kf3334845fbe75f5d@mail.gmail.com> Message-ID: <4A28DBF6.4080206@gmx.net> On 05.06.2009 01:20, Urja Rannikko wrote: > Exact bustypes for Atmel AT29C010A, AT29C020, AT29C040A, AT49BV512, > AT49F002, AMIC A29040B, A49LF040A, > EMST F49B002UA, EON EN29F002, Intel 28F001BX-B, 28F001BX-T, Winbond > W29C020C and W29C040P. > Checked from datasheets. A49LF040A is LPC, others parallel. > > Signed-off-by: Urja Rannikko > Thanks. Acked-by: Carl-Daniel Hailfinger AMIC cross-checked and committed in r574. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 11:17:54 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 11:17:54 +0200 Subject: [coreboot] [PATCH] flashrom: Clean up sst49lfxxxc.c In-Reply-To: <4A28D1D4.6010309@gmx.net> References: <20090605004245.2994gmx1@mx049.gmx.net> <4A28D1D4.6010309@gmx.net> Message-ID: <4A28E2C2.4030200@gmx.net> On 05.06.2009 10:05, Carl-Daniel Hailfinger wrote: > On 05.06.2009 02:42, svn at coreboot.org wrote: > >> Revision: 573 >> >> Actually enable the protection register debug output on >> SST49LF160C and similar chips if -V is supplied. >> >> Signed-off-by: Uwe Hermann >> >> > There's flash->virtual_memory and flash->virtual_registers. Any reason > you recalculate flash->virtual_registers even though it is passed in? > Use flash->virtual_registers for what they were meant for instead of recalculating them every time. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-sst49lfxxxc_lockbits/sst49lfxxxc.c =================================================================== --- flashrom-sst49lfxxxc_lockbits/sst49lfxxxc.c (Revision 574) +++ flashrom-sst49lfxxxc_lockbits/sst49lfxxxc.c (Arbeitskopie) @@ -38,38 +38,39 @@ #define STATUS_ESS (1 << 6) #define STATUS_WSMS (1 << 7) -static int write_lockbits_49lfxxxc(chipaddr bios, int size, unsigned char bits) +static int write_lockbits_49lfxxxc(struct flashchip *flash, unsigned char bits) { - int i, left = size; + chipaddr registers = flash->virtual_registers; + int i, left = flash->total_size * 1024; unsigned long address; - printf_debug("\nbios=0x%08lx\n", bios); + printf_debug("\nbios=0x%08lx\n", registers); for (i = 0; left > 65536; i++, left -= 65536) { - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + (i * 65536) + 2), - chip_readb(bios + (i * 65536) + 2)); - chip_writeb(bits, bios + (i * 65536) + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + (i * 65536) + 2, + chip_readb(registers + (i * 65536) + 2)); + chip_writeb(bits, registers + (i * 65536) + 2); } address = i * 65536; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); address += 32768; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); address += 8192; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); address += 8192; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); return 0; } @@ -150,11 +151,10 @@ int erase_49lfxxxc(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; - chipaddr registers = flash->virtual_registers; int i; unsigned int total_size = flash->total_size * 1024; - write_lockbits_49lfxxxc(registers, total_size, 0); + write_lockbits_49lfxxxc(flash, 0); for (i = 0; i < total_size; i += flash->page_size) if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); @@ -171,7 +171,7 @@ int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; - write_lockbits_49lfxxxc(flash->virtual_registers, total_size, 0); + write_lockbits_49lfxxxc(flash, 0); printf("Programming page: "); for (i = 0; i < total_size / page_size; i++) { /* erase the page before programming */ -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_sst49lfxxxc_lockbits.diff URL: From Zheng.Bao at amd.com Fri Jun 5 11:17:55 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Fri, 5 Jun 2009 17:17:55 +0800 Subject: [coreboot] [patch]:Skip VC1 to fix dbm690t hanging Message-ID: After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a starts to play its role. Then the system hangs at HDA init. I dont know what the VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)" in 5.10.2. Before I know what it is, I think it is better to skip it. Tested on dbm690t. Signed-off-by: Zheng Bao -------------------- Index: src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- src/southbridge/amd/rs690/rs690_pcie.c (revision 4338) +++ src/southbridge/amd/rs690/rs690_pcie.c (working copy) @@ -276,6 +276,7 @@ /* step 6a: VCI */ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); if (port == 8) { +#if 0 /* Clear bits 7:1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1); /* Maps Traffic Class 1-7 to VC1 */ @@ -284,7 +285,7 @@ pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24); /* Enables VC1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31); -#if 0 + do { reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124); reg16 &= 0x2; -------------- next part -------------- A non-text attachment was scrubbed... Name: rs690_skip_VC1.patch Type: application/octet-stream Size: 1147 bytes Desc: rs690_skip_VC1.patch URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 11:21:44 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 11:21:44 +0200 Subject: [coreboot] [patch]:Skip VC1 to fix dbm690t hanging In-Reply-To: References: Message-ID: <4A28E3A8.7030103@gmx.net> On 05.06.2009 11:17, Bao, Zheng wrote: > After I modify the pci_ext_read_config32 and pci_ext_read_config32, the > step 6a > starts to play its role. Then the system hangs at HDA init. I dont know > what the > VC1 is. The RPR says "Optional Features (only needed if CMOS option is > enabled)" > in 5.10.2. Before I know what it is, I think it is better to skip it. > > Tested on dbm690t. > > Signed-off-by: Zheng Bao > If you add a comment before the #if 0 which says that this code causes a hang on HDA init, the patch is Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From r.marek at assembler.cz Fri Jun 5 11:33:39 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 05 Jun 2009 11:33:39 +0200 Subject: [coreboot] [patch]:Skip VC1 to fix dbm690t hanging In-Reply-To: <4A28E3A8.7030103@gmx.net> References: <4A28E3A8.7030103@gmx.net> Message-ID: <4A28E673.5000702@assembler.cz> Hi all, VC is virtual channel. Its used for isochronous transfer of data to sound card. The virtual channel guarantee "on time" delivery.In other words it sets up a channel for data to sound card, which means that that arrive in time and there will be no interruptions in audio stream. Unfortunately I never played with that. This is all I know ;) Rudolf From r.marek at assembler.cz Fri Jun 5 11:46:12 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 05 Jun 2009 11:46:12 +0200 Subject: [coreboot] [patch]:Skip VC1 to fix dbm690t hanging In-Reply-To: <4A28E673.5000702@assembler.cz> References: <4A28E3A8.7030103@gmx.net> <4A28E673.5000702@assembler.cz> Message-ID: <4A28E964.6070802@assembler.cz> Hi again, http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx Here is some writeup. HD Audio is a special case. Rudolf From svn at coreboot.org Fri Jun 5 12:00:07 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 12:00:07 +0200 Subject: [coreboot] [v2] r4339 - trunk/coreboot-v2/src/southbridge/amd/rs690 Message-ID: Author: zbao Date: 2009-06-05 12:00:07 +0200 (Fri, 05 Jun 2009) New Revision: 4339 Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c Log: After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a starts to play its role. Then the system hangs at HDA init. I dont know what the VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)" in 5.10.2. Before I know what it is, I think it is better to skip it. Tested on dbm690t. Add comment from Rudolf, " VC is virtual channel. Its used for isochronous transfer of data to sound card. The virtual channel guarantee "on time" delivery. In other words it sets up a channel for data to sound card, which means that that arrivs in time and there will be no interuptions in audio stream. http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx " Signed-off-by: Zheng Bao Acked-by: Carl-Daniel Hailfinger Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-05 00:22:25 UTC (rev 4338) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-05 10:00:07 UTC (rev 4339) @@ -276,6 +276,9 @@ /* step 6a: VCI */ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); if (port == 8) { + /* The code below between #if and #endif causes a hang on HDA init. + * So we skip it. */ +#if 0 /* Clear bits 7:1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1); /* Maps Traffic Class 1-7 to VC1 */ @@ -284,7 +287,7 @@ pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24); /* Enables VC1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31); -#if 0 + do { reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124); reg16 &= 0x2; From Zheng.Bao at amd.com Fri Jun 5 12:03:08 2009 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Fri, 5 Jun 2009 18:03:08 +0800 Subject: [coreboot] [patch]:Skip VC1 to fix dbm690t hanging In-Reply-To: <4A28E3A8.7030103@gmx.net> References: <4A28E3A8.7030103@gmx.net> Message-ID: The comment was added and Commited to r4339. I also add some comment from Rudolf in svn message. Zheng -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] Sent: Friday, June 05, 2009 5:22 PM To: Bao, Zheng Cc: coreboot at coreboot.org Subject: Re: [coreboot] [patch]:Skip VC1 to fix dbm690t hanging On 05.06.2009 11:17, Bao, Zheng wrote: > After I modify the pci_ext_read_config32 and pci_ext_read_config32, the > step 6a > starts to play its role. Then the system hangs at HDA init. I dont know > what the > VC1 is. The RPR says "Optional Features (only needed if CMOS option is > enabled)" > in 5.10.2. Before I know what it is, I think it is better to skip it. > > Tested on dbm690t. > > Signed-off-by: Zheng Bao > If you add a comment before the #if 0 which says that this code causes a hang on HDA init, the patch is Acked-by: Carl-Daniel Hailfinger Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 12:43:32 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 12:43:32 +0200 Subject: [coreboot] [PATCH] K8: Improve RAM init debug messages Message-ID: <4A28F6D4.7070608@gmx.net> K8 RAM init debug messages are pretty short and sometimes cryptic. Make them a bit more verbose and hopefully more understandable. Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-k8_raminit_debugmessages/src/northbridge/amd/amdk8/raminit.c =================================================================== --- LinuxBIOSv2-k8_raminit_debugmessages/src/northbridge/amd/amdk8/raminit.c (Revision 4339) +++ LinuxBIOSv2-k8_raminit_debugmessages/src/northbridge/amd/amdk8/raminit.c (Arbeitskopie) @@ -850,14 +850,18 @@ } /* Report the amount of memory. */ - printk_spew("RAM: 0x%08x kB\n", tom_k); + printk_debug("RAM end at 0x%08x kB, hole starts at 0x%08x kB\n", + tom_k, hole_startk); /* Now set top of memory */ msr_t msr; if (tom_k > (4*1024*1024)) { + printk_raminit("Handling memory mapped above 4 GB\n"); + printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); + printk_raminit("Correcting memory amount mapped below 4 GB\n"); } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 @@ -871,6 +875,7 @@ #endif tom_k = 0x3f0000; } + printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM, msr); @@ -2167,6 +2172,7 @@ hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), @@ -2191,6 +2197,7 @@ basek_pri = base_k; } + printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* Find node number that needs the memory hole configured */ for (i=0; i (4*1024*1024)) { + printk_raminit("Handling memory mapped above 4 GB\n"); + printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); + printk_raminit("Correcting memory amount mapped below 4 GB\n"); } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 @@ -1070,6 +1074,7 @@ #endif tom_k = 0x3f0000; } + printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM, msr); @@ -2938,6 +2943,7 @@ hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ @@ -2958,6 +2964,7 @@ } basek_pri = base_k; } + printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* find node index that need do set hole */ for (i=0; i < controllers; i++) { -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: linuxbios_k8_raminit_debugmessages01.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 12:51:46 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 12:51:46 +0200 Subject: [coreboot] [PATCH] Fix AMD 690 HIGH_TABLES Message-ID: <4A28F8C2.4090004@gmx.net> Zheng, can you please test this with HIGH_TABLES enabled (and a new FILO)? A full log would be appreciated. Thanks. This hopefully will fix AMD 690 HIGH_TABLES or at least give me an insight into why HIGH_TABLES fails. Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -896,6 +896,7 @@ #if HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; +extern uint64_t uma_memory_base, uma_memory_size; #endif static void pci_domain_set_resources(device_t dev) @@ -1066,7 +1067,9 @@ } -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + if ((uma_memory_base >> 10) < mmio_basek) + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -1080,7 +1083,7 @@ #if HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); @@ -1105,6 +1108,9 @@ sizek -= (4*1024*1024 - mmio_basek); } } + + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ @@ -1116,7 +1122,7 @@ i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; } #endif -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: linuxbios_amd_690_debug_hightables.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 13:19:34 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 13:19:34 +0200 Subject: [coreboot] [PATCH] Use die() properly Message-ID: <4A28FF46.8000308@gmx.net> die() does never return. Annotate it as such. Any endless loop after die() can be eliminated. Dereferencing a NULL pointer is bad. die() instead. Replace endless loops with die(). Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-die/src/console/console.c =================================================================== --- LinuxBIOSv2-die/src/console/console.c (Revision 4339) +++ LinuxBIOSv2-die/src/console/console.c (Arbeitskopie) @@ -92,7 +92,7 @@ } /* Report a fatal error */ -void die(const char *msg) +void __attribute__((noreturn)) die(const char *msg) { printk_emerg("%s", msg); post_code(0xff); Index: LinuxBIOSv2-die/src/devices/smbus_ops.c =================================================================== --- LinuxBIOSv2-die/src/devices/smbus_ops.c (Revision 4339) +++ LinuxBIOSv2-die/src/devices/smbus_ops.c (Arbeitskopie) @@ -34,7 +34,6 @@ if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_smbus_bus) { printk_alert("%s Cannot find smbus bus operations", dev_path(dev)); die(""); - for(;;); } return pbus; } Index: LinuxBIOSv2-die/src/devices/pci_ops.c =================================================================== --- LinuxBIOSv2-die/src/devices/pci_ops.c (Revision 4339) +++ LinuxBIOSv2-die/src/devices/pci_ops.c (Arbeitskopie) @@ -30,7 +30,7 @@ struct bus *pbus; if (!dev) - printk_alert("get_pbus: dev is NULL!\n"); + die("get_pbus: dev is NULL!\n"); pbus = dev->bus; @@ -44,9 +44,8 @@ pbus = pbus->dev->bus; } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { - printk_alert("%s Cannot find pci bus operations", dev_path(dev)); + printk_emerg("%s Cannot find pci bus operations\n", dev_path(dev)); die(""); - for(;;); } return pbus; } Index: LinuxBIOSv2-die/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c =================================================================== --- LinuxBIOSv2-die/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c (Revision 4339) +++ LinuxBIOSv2-die/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c (Arbeitskopie) @@ -37,12 +37,12 @@ dword=*ioapic_sbd; printk_debug("Southbridge apic id = %x\n",dword); if(dword!=(2<<24)) - for(;;); + die(""); //lyh *ioapic_sba=3; //lyh dword=*ioapic_sbd; //lyh printk_debug("Southbridge apic DT = %x\n",dword); //lyh if(dword!=1) - //lyh for(;;); + //lyh die(""); } -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: linuxbios_die.diff URL: From urjaman at gmail.com Fri Jun 5 13:24:54 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 14:24:54 +0300 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol Message-ID: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> Hi all, I have a device that i would like to make a flashrom supported external programmer, an atmega168 with 3 shift registers as address bus and a DIL32 socket connected via RS232. Currently it runs it's own special software and i have special software on the PC to use it - but this combination supports (at the moment) only AT29C020 and W29C020C, so using flashrom's great database of flash chips would be great. Ok, so i would just implement a protocol for passing read and write cycles though the serial bus, sounds easy but there's a caveeat: eg. for the W29C020C there's a timeout between the bytes in the page load algo, 200us. For serial only i might be able to do that, but as my device isnt really attached to my computer's serial port (it's transmitter is busted..) but instead an serial<->ethernet adapter, there's no way one can do a "ping" in 200us, same problem applies for the USB FTDI chips i think. Even if it would work, the performance would be way too low. So, i suggest a way for external programmers to provide alternatives to the normal flash chip functions like probe_jedec, read_memmapped, write_jedec, etc. In the external programmer init function the code could/would "attach" a table to a global pointer that defines re-mappings of chip functions, and before calling a chip function flashrom would check if the pointer is non-null and then check if there's an alternative to the function that is to be used, and would call the alternative instead. The alternative function would then use it's special protocol to actually cause the function to be "executed" on the programmer device, requiring much less bandwidth and making those timing requirements easy to meet. In case there's no re-mapping of some flash chip function (i wouldnt want to implement all the flash chip functions on my external programmer at once), the external programmer would ofcourse also implement the basic read and write cycles and the original flash chip access function would try to operate using those - whether that works is a different issue. That's the first part of this "RFC" ... comments please. Then i suggest that we would try to make some kind of a "standard" for an external serial programmer protocol - it could run over the normal serial port, an USB<->serial converter chip or over an TCP socket. This would allow use to reuse a simple "serialprog" external programmer module for any serial programming devices which some of us might make. That would allow eg. to support my device, but because that is propably an one-off device (it's cheap only because the base board was free for me) make the protocol usable with other possible devices too. My suggestion would be a simple protocol in wich "calls" are the sending of a lenght word + function byte + parameters. The device would return with support byte + optional return value. eg in theory a read cycle: PC: 0x04 0x00 0x00 0xAA 0xBB 0xCC ---- 16-bit little endian lenght (of bytes after it) + function number 0 (read byte) + 24-bit address then device would return eg: DEV: 0xAA 0xBB 0xAA = I support this function, 0xBB = data returned or DEV: 0x55 = I dont support this function. The values i picked are pretty much arbitary, but the idea is that different devices could support different sets of functions and could skip over not-supported functions in the data stream, just reporting that they dont support it. The scheme would allow upto 256 different functions with arbitary parameters (per-function). I chose 24-bit addresses as i havent heard of a bios flash chip that's even near 16MiB, and because we are tight on space in the protocol. I might be into implementing this all, but it will take some time, and i would like to get it right so that it's of best possible use for all. Any input is appreciated. -- urjaman From peter at stuge.se Fri Jun 5 13:35:26 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 5 Jun 2009 13:35:26 +0200 Subject: [coreboot] [PATCH] Use die() properly In-Reply-To: <4A28FF46.8000308@gmx.net> References: <4A28FF46.8000308@gmx.net> Message-ID: <20090605113526.10729.qmail@stuge.se> Carl-Daniel Hailfinger wrote: > die() does never return. Annotate it as such. > Any endless loop after die() can be eliminated. > Dereferencing a NULL pointer is bad. die() instead. > Replace endless loops with die(). > > Signed-off-by: Carl-Daniel Hailfinger Acked-by: Peter Stuge From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 13:39:15 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 13:39:15 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> Message-ID: <4A2903E3.6030301@gmx.net> What about introducing a per-programmer delay function pointer instead? Your programmer could buffer everything (delays, writes) until the first read, then send them as a batch. AFAICS this would solve almost all issues and be a good first step forward. The only remaining issue would be fast read, but for that it's easy to replace chip_readl (32bits) with chip_readn (n bytes). Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Fri Jun 5 13:41:51 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 13:41:51 +0200 Subject: [coreboot] [v2] r4340 - in trunk/coreboot-v2/src: console devices southbridge/intel/i82801dbm Message-ID: Author: hailfinger Date: 2009-06-05 13:41:51 +0200 (Fri, 05 Jun 2009) New Revision: 4340 Modified: trunk/coreboot-v2/src/console/console.c trunk/coreboot-v2/src/devices/pci_ops.c trunk/coreboot-v2/src/devices/smbus_ops.c trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c Log: die() does never return. Annotate it as such. Any endless loop after die() can be eliminated. Dereferencing a NULL pointer is bad. die() instead. Replace endless loops with die(). Signed-off-by: Carl-Daniel Hailfinger Acked-by: Peter Stuge Modified: trunk/coreboot-v2/src/console/console.c =================================================================== --- trunk/coreboot-v2/src/console/console.c 2009-06-05 10:00:07 UTC (rev 4339) +++ trunk/coreboot-v2/src/console/console.c 2009-06-05 11:41:51 UTC (rev 4340) @@ -92,7 +92,7 @@ } /* Report a fatal error */ -void die(const char *msg) +void __attribute__((noreturn)) die(const char *msg) { printk_emerg("%s", msg); post_code(0xff); Modified: trunk/coreboot-v2/src/devices/pci_ops.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_ops.c 2009-06-05 10:00:07 UTC (rev 4339) +++ trunk/coreboot-v2/src/devices/pci_ops.c 2009-06-05 11:41:51 UTC (rev 4340) @@ -30,7 +30,7 @@ struct bus *pbus; if (!dev) - printk_alert("get_pbus: dev is NULL!\n"); + die("get_pbus: dev is NULL!\n"); pbus = dev->bus; @@ -44,9 +44,8 @@ pbus = pbus->dev->bus; } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { - printk_alert("%s Cannot find pci bus operations", dev_path(dev)); + printk_emerg("%s Cannot find pci bus operations\n", dev_path(dev)); die(""); - for(;;); } return pbus; } Modified: trunk/coreboot-v2/src/devices/smbus_ops.c =================================================================== --- trunk/coreboot-v2/src/devices/smbus_ops.c 2009-06-05 10:00:07 UTC (rev 4339) +++ trunk/coreboot-v2/src/devices/smbus_ops.c 2009-06-05 11:41:51 UTC (rev 4340) @@ -34,7 +34,6 @@ if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_smbus_bus) { printk_alert("%s Cannot find smbus bus operations", dev_path(dev)); die(""); - for(;;); } return pbus; } Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-05 10:00:07 UTC (rev 4339) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-05 11:41:51 UTC (rev 4340) @@ -37,12 +37,12 @@ dword=*ioapic_sbd; printk_debug("Southbridge apic id = %x\n",dword); if(dword!=(2<<24)) - for(;;); + die(""); //lyh *ioapic_sba=3; //lyh dword=*ioapic_sbd; //lyh printk_debug("Southbridge apic DT = %x\n",dword); //lyh if(dword!=1) - //lyh for(;;); + //lyh die(""); } From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 13:42:15 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 13:42:15 +0200 Subject: [coreboot] [PATCH] Use die() properly In-Reply-To: <20090605113526.10729.qmail@stuge.se> References: <4A28FF46.8000308@gmx.net> <20090605113526.10729.qmail@stuge.se> Message-ID: <4A290497.1070806@gmx.net> On 05.06.2009 13:35, Peter Stuge wrote: > Carl-Daniel Hailfinger wrote: > >> die() does never return. Annotate it as such. >> Any endless loop after die() can be eliminated. >> Dereferencing a NULL pointer is bad. die() instead. >> Replace endless loops with die(). >> >> Signed-off-by: Carl-Daniel Hailfinger >> > > Acked-by: Peter Stuge > Thanks, committed in r4340. Regards, Carl-Daniel -- http://www.hailfinger.org/ From stepan at coresystems.de Fri Jun 5 13:44:22 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 05 Jun 2009 13:44:22 +0200 Subject: [coreboot] [PATCH] K8: Improve RAM init debug messages In-Reply-To: <4A28F6D4.7070608@gmx.net> References: <4A28F6D4.7070608@gmx.net> Message-ID: <4A290516.3050701@coresystems.de> On 05.06.2009 12:43 Uhr, Carl-Daniel Hailfinger wrote: > /* Report the amount of memory. */ > - printk_spew("RAM: 0x%08x kB\n", tom_k); > + printk_debug("RAM end at 0x%08x kB, hole starts at 0x%08x kB\n", > + tom_k, hole_startk); > > /* Now set top of memory */ > msr_t msr; > if (tom_k > (4*1024*1024)) { > + printk_raminit("Handling memory mapped above 4 GB\n"); > + printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); > I'm not sure it gets any easier to understand or less cryptic by calling the amount of RAM end of RAM and printing it twice? -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From saueimer at googlemail.com Fri Jun 5 12:59:47 2009 From: saueimer at googlemail.com (saueimer) Date: Fri, 5 Jun 2009 12:59:47 +0200 Subject: [coreboot] Is this boar/chipset combination supported? Message-ID: <51ec7b340906050359t56e6e82bn5c11679ec4d3873e@mail.gmail.com> Hi there, i read the "Will coreboot work on my machine?"-FAQ. Unfortunately I don't own my desired board and chipset yet, but I would like to know if this combination is supported, so i tried to collect some infromation: Board: Jetway JNC62K SocketAM2/AM2+ Mini-ITX (link to the homepage: http://www.jetwaycomputer.com/AMD3.html and as attachment the datasheet) Chipset:cpu AMD AM2 5050X2 Processor AMD Athlon? X2 Dual-Core Model 5050e OPN Tray ADH5050IAA5DO OPN PIB ADH5050IADOBOX Operating Mode 32 Bit Yes Operating Mode 64 Bit Yes Revision G2 Core Speed (MHz) 2600 Voltages 1.0-1.25V Max Temps (C) 78'C Wattage 45 W L1 Cache Size (KB) 128 L1 Cache Count 2 L2 Cache Size (KB) 512 L2 Cache Count 2 L3 Cache Size (KB) CMOS 65nm SOI Socket AM2 AMD Business Class No Black Edition No Kind regards and thanks for any information! -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: NC62K.pdf Type: application/pdf Size: 154701 bytes Desc: not available URL: From Stefan.Gaechter at sie.at Mon Jun 1 20:49:24 2009 From: Stefan.Gaechter at sie.at (Gaechter, Stefan) Date: Mon, 1 Jun 2009 20:49:24 +0200 Subject: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset References: Message-ID: <2F3951A78535124D960B1EFBB992F6D102832B6A@mailserver.sienet.local> hi, a view weeks ago i read about the start of a menlow port. has anybody started the port? Br, stefan On Tue, 14 Apr 2009 08:56:06 -0500, bari wrote: > Mansoor wrote: >> Hi, >> >> I have a Atom Silverthorne Poulsbo based board >> (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on this >> platform. >> >> I would like to know if anybody has started/suceeded in porting coreboot >> to Atom, also if there is anyone interested in such a port. > > There is lots of interest in Atom support. Nobody I am aware of has > enough documentation yet. Maybe you do since you have an Atom based COM > module? http://iwavesystems.com/iW-Q7.htm > >> 1)Which version of coreboot can be used (v2 or v3) ? >> 2)Which platform (CPU,motherboard,EC) can be taken as reference ? > > The i945 is supported by v2 so an Atom + i945 board would be the > shortest path to success. > Yes, I would have to agree with Bari here. You should start with the i945 code. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -------------- next part -------------- A non-text attachment was scrubbed... Name: winmail.dat Type: application/ms-tnef Size: 3393 bytes Desc: not available URL: From stepan at coresystems.de Fri Jun 5 13:47:57 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 05 Jun 2009 13:47:57 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <4A2903E3.6030301@gmx.net> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <4A2903E3.6030301@gmx.net> Message-ID: <4A2905ED.8040502@coresystems.de> On 05.06.2009 13:39 Uhr, Carl-Daniel Hailfinger wrote: > What about introducing a per-programmer delay function pointer instead? > Your programmer could buffer everything (delays, writes) until the first > read, then send them as a batch. > Which one is like that? Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 13:54:59 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 13:54:59 +0200 Subject: [coreboot] Is this boar/chipset combination supported? In-Reply-To: <51ec7b340906050359t56e6e82bn5c11679ec4d3873e@mail.gmail.com> References: <51ec7b340906050359t56e6e82bn5c11679ec4d3873e@mail.gmail.com> Message-ID: <4A290793.4050605@gmx.net> Hi, On 05.06.2009 12:59, saueimer wrote: > Jetway JNC62K SocketAM2/AM2+ Mini-ITX > Unfortunately the NVidia MCP78S chipset is not supported yet and it is unlikely we'll support it in the future because we don't have the needed data sheets and programming information. Regards, Carl-Daniel -- http://www.hailfinger.org/ From urjaman at gmail.com Fri Jun 5 14:02:41 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 15:02:41 +0300 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050455n692f17dfi637d922aeff00ee2@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <4A2903E3.6030301@gmx.net> <460f92b70906050455n692f17dfi637d922aeff00ee2@mail.gmail.com> Message-ID: <460f92b70906050502q1bfced80h5d7027859a8aceba@mail.gmail.com> > What about introducing a per-programmer delay function pointer instead? > Your programmer could buffer everything (delays, writes) until the first > read, then send them as a batch. > The only problem i see here that in order for this to work properly, i would need to create the buffer on the programmer side (otherwise there could be too big delays between the packets (even if streaming a buffered store from the computer), eg. network packet loss) and i'm not sure whether the AVR's 1k SRAM would be enough to hold even the low level description of a single page load, given address + data = 4 bytes + 1 byte operation = 5*256 = 1280 bytes. ofcourse the addresses could be "compressed" (sequential), but it still doesnt sound right - even simple op+byte would be 512+ bytes. We could compress down to op + n + n bytes ... that could work. Not sure. I sent this accidentally only to carl-daniel first, sorry. -- urjaman From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 14:17:16 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 14:17:16 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050502q1bfced80h5d7027859a8aceba@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <4A2903E3.6030301@gmx.net> <460f92b70906050455n692f17dfi637d922aeff00ee2@mail.gmail.com> <460f92b70906050502q1bfced80h5d7027859a8aceba@mail.gmail.com> Message-ID: <4A290CCC.2030209@gmx.net> On 05.06.2009 14:02, Urja Rannikko wrote: >> What about introducing a per-programmer delay function pointer instead? >> Your programmer could buffer everything (delays, writes) until the first >> read, then send them as a batch. >> Stefan pointed out that my text above is ambiguous. Let me retry: We have delays(mostly udelay) in the flashrom code, but almost always we don't want to delay flashrom operation, but make sure we honor the timing for flash chip accesses. For on-board programming, this is basically udelay. For external programmers, it is a bit more difficult. Some have builtin delay functions (like the TotalPhase Cheetah), some require the host to take care of delays. Having a per-programmer delay function would solve this nicely. > The only problem i see here that in order for this to work properly, i > would need to create the buffer on the programmer side (otherwise > there could be too big delays between the packets (even if streaming a > buffered store from the computer), eg. network packet loss) and i'm > not sure whether the AVR's 1k SRAM would be enough to hold even the > low level description of a single page load, given address + data = 4 > bytes + 1 byte operation = 5*256 = 1280 bytes. ofcourse the addresses > could be "compressed" (sequential), but it still doesnt sound right - > even simple op+byte would be 512+ bytes. We could compress down to op > + n + n bytes ... that could work. Not sure. > The buffer management would be performed by the programmer driver. So if your programmer can execute (or buffer) 1024 bytes of commands/address/data, make sure flashrom accumulates no more than 1024 bytes in its internal buffer before flushing its buffer to the device. >> The only remaining issue would be fast read, but for that it's easy to >> replace chip_readl (32bits) with chip_readn (n bytes). Your programmer driver could hook chip_readn (and possibly chip_writen) and implement optimized batch writes there. > I sent this accidentally only to carl-daniel first, sorry. > No problem. Thanks for resending. I hope my explanation was easier to understand this time. Regards, Carl-Daniel -- http://www.hailfinger.org/ From joe at settoplinux.org Fri Jun 5 14:17:53 2009 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 05 Jun 2009 08:17:53 -0400 Subject: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset In-Reply-To: <2F3951A78535124D960B1EFBB992F6D102832B6A@mailserver.sienet.local> References: <2F3951A78535124D960B1EFBB992F6D102832B6A@mailserver.sienet.local> Message-ID: On Mon, 1 Jun 2009 20:49:24 +0200, "Gaechter, Stefan" wrote: > hi, > > a view weeks ago i read about the start of a menlow port. > has anybody started the port? > > Br, stefan > > > > On Tue, 14 Apr 2009 08:56:06 -0500, bari wrote: >> Mansoor wrote: >>> Hi, >>> >>> I have a Atom Silverthorne Poulsbo based board >>> (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on > this >>> platform. >>> >>> I would like to know if anybody has started/suceeded in porting > coreboot >>> to Atom, also if there is anyone interested in such a port. >> >> There is lots of interest in Atom support. Nobody I am aware of has >> enough documentation yet. Maybe you do since you have an Atom based COM >> module? http://iwavesystems.com/iW-Q7.htm >> >>> 1)Which version of coreboot can be used (v2 or v3) ? >>> 2)Which platform (CPU,motherboard,EC) can be taken as reference ? >> >> The i945 is supported by v2 so an Atom + i945 board would be the >> shortest path to success. >> > Yes, I would have to agree with Bari here. You should start with the i945 > code. > > I would be very interested in porting/seeing coreboot on the Intel D945GCLF2 Atom board because it has TV-out (S-Video). I just can't seem to find a good deal on one, if anyone can find me one for around $50 us, I would really consider it :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From peter at stuge.se Fri Jun 5 14:48:50 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 5 Jun 2009 14:48:50 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> Message-ID: <20090605124850.25117.qmail@stuge.se> Hi Urja, Urja Rannikko wrote: > a way for external programmers to provide alternatives to the > normal flash chip functions like probe_jedec, read_memmapped, > write_jedec, etc. .. > That's the first part of this "RFC" ... comments please. > > Then i suggest that we would try to make some kind of a "standard" > for an external serial programmer protocol I think these two issues go hand in hand. You have the right idea about how this should work to be efficient. A similar scheme was discussed around the Windows flashrom GSoC project, where the "external serial programmer" would have been a Windows kernel driver. The conclusion back then was that while it would be a great solution it was maybe not feasible for the summer project, so another solution was implemented. Some of our ramblings back then are probably still good, and some are no longer useful. Two links to the archive for some of the discussion but there might be more: http://www.coreboot.org/pipermail/coreboot/2007-April/020206.html http://www.coreboot.org/pipermail/coreboot/2007-May/020488.html > I might be into implementing this all, but it will take some time, > and i would like to get it right so that it's of best possible use > for all. Any input is appreciated. I think there are two parts to it. One is about the flashrom data model, which has been expanded a little lately but really needs to be very different. The timing properties you mention are required for some chips and other chip types have other required property sets. The challenge here is to create a complete data model. The second part is to communicate that data from flashrom to satellite entities which all implement the same state machine. The challenge here is to create a state machine which works for abstracting all the different ways we want to reach flash chips. //Peter From uwe at hermann-uwe.de Fri Jun 5 15:21:36 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 15:21:36 +0200 Subject: [coreboot] [PATCH] Use die() properly In-Reply-To: <4A28FF46.8000308@gmx.net> References: <4A28FF46.8000308@gmx.net> Message-ID: <20090605132136.GF18065@greenwood> On Fri, Jun 05, 2009 at 01:19:34PM +0200, Carl-Daniel Hailfinger wrote: > printk_alert("%s Cannot find smbus bus operations", dev_path(dev)); > die(""); Can we also make die() accept variable argument numbers so we can do this? die("%s Cannot find smbus bus operations", dev_path(dev)); Or does this cause issues when die() is called very early (pre-RAM) or so? Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From uwe at hermann-uwe.de Fri Jun 5 15:25:57 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 15:25:57 +0200 Subject: [coreboot] [PATCH] flashrom: Clean up sst49lfxxxc.c In-Reply-To: <4A28E2C2.4030200@gmx.net> References: <20090605004245.2994gmx1@mx049.gmx.net> <4A28D1D4.6010309@gmx.net> <4A28E2C2.4030200@gmx.net> Message-ID: <20090605132556.GG18065@greenwood> On Fri, Jun 05, 2009 at 11:17:54AM +0200, Carl-Daniel Hailfinger wrote: > Use flash->virtual_registers for what they were meant for instead of > recalculating them every time. > > Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 15:28:34 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 15:28:34 +0200 Subject: [coreboot] [PATCH] Use die() properly In-Reply-To: <20090605132136.GF18065@greenwood> References: <4A28FF46.8000308@gmx.net> <20090605132136.GF18065@greenwood> Message-ID: <4A291D82.6090601@gmx.net> On 05.06.2009 15:21, Uwe Hermann wrote: > On Fri, Jun 05, 2009 at 01:19:34PM +0200, Carl-Daniel Hailfinger wrote: > >> printk_alert("%s Cannot find smbus bus operations", dev_path(dev)); >> die(""); >> > > Can we also make die() accept variable argument numbers so we can do this? > I wanted to do that, but AFAICS it fails for early ROMCC compiled code. > die("%s Cannot find smbus bus operations", dev_path(dev)); > > Or does this cause issues when die() is called very early (pre-RAM) or so? > It sure would be desirable. Once the CBFS conversion goes as planned and Ron's conversion to v3 startup is done, converting boards to CAR should be doable and give us (among others) die() with parameters. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Fri Jun 5 15:30:49 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 15:30:49 +0200 Subject: [coreboot] [flashrom] r575 - trunk Message-ID: Author: hailfinger Date: 2009-06-05 15:30:49 +0200 (Fri, 05 Jun 2009) New Revision: 575 Modified: trunk/sst49lfxxxc.c Log: Use flash->virtual_registers for what they were meant for instead of recalculating them every time. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Modified: trunk/sst49lfxxxc.c =================================================================== --- trunk/sst49lfxxxc.c 2009-06-05 08:47:37 UTC (rev 574) +++ trunk/sst49lfxxxc.c 2009-06-05 13:30:49 UTC (rev 575) @@ -38,38 +38,39 @@ #define STATUS_ESS (1 << 6) #define STATUS_WSMS (1 << 7) -static int write_lockbits_49lfxxxc(chipaddr bios, int size, unsigned char bits) +static int write_lockbits_49lfxxxc(struct flashchip *flash, unsigned char bits) { - int i, left = size; + chipaddr registers = flash->virtual_registers; + int i, left = flash->total_size * 1024; unsigned long address; - printf_debug("\nbios=0x%08lx\n", bios); + printf_debug("\nbios=0x%08lx\n", registers); for (i = 0; left > 65536; i++, left -= 65536) { - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + (i * 65536) + 2), - chip_readb(bios + (i * 65536) + 2)); - chip_writeb(bits, bios + (i * 65536) + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + (i * 65536) + 2, + chip_readb(registers + (i * 65536) + 2)); + chip_writeb(bits, registers + (i * 65536) + 2); } address = i * 65536; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); address += 32768; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); address += 8192; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); address += 8192; - printf_debug("lockbits at address=%p is 0x%01x\n", - (void *)(0xffc00000 - size + address + 2), - chip_readb(bios + address + 2)); - chip_writeb(bits, bios + address + 2); + printf_debug("lockbits at address=0x%08lx is 0x%01x\n", + registers + address + 2, + chip_readb(registers + address + 2)); + chip_writeb(bits, registers + address + 2); return 0; } @@ -150,11 +151,10 @@ int erase_49lfxxxc(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; - chipaddr registers = flash->virtual_registers; int i; unsigned int total_size = flash->total_size * 1024; - write_lockbits_49lfxxxc(registers, total_size, 0); + write_lockbits_49lfxxxc(flash, 0); for (i = 0; i < total_size; i += flash->page_size) if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); @@ -171,7 +171,7 @@ int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; - write_lockbits_49lfxxxc(flash->virtual_registers, total_size, 0); + write_lockbits_49lfxxxc(flash, 0); printf("Programming page: "); for (i = 0; i < total_size / page_size; i++) { /* erase the page before programming */ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 15:31:00 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 15:31:00 +0200 Subject: [coreboot] [PATCH] flashrom: Clean up sst49lfxxxc.c In-Reply-To: <20090605132556.GG18065@greenwood> References: <20090605004245.2994gmx1@mx049.gmx.net> <4A28D1D4.6010309@gmx.net> <4A28E2C2.4030200@gmx.net> <20090605132556.GG18065@greenwood> Message-ID: <4A291E14.8040607@gmx.net> On 05.06.2009 15:25, Uwe Hermann wrote: > On Fri, Jun 05, 2009 at 11:17:54AM +0200, Carl-Daniel Hailfinger wrote: > >> Use flash->virtual_registers for what they were meant for instead of >> recalculating them every time. >> >> Signed-off-by: Carl-Daniel Hailfinger >> > > Acked-by: Uwe Hermann > Thanks, committed in r575. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 15:34:59 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 15:34:59 +0200 Subject: [coreboot] [PATCH] K8: Improve RAM init debug messages In-Reply-To: <4A290516.3050701@coresystems.de> References: <4A28F6D4.7070608@gmx.net> <4A290516.3050701@coresystems.de> Message-ID: <4A291F03.1040001@gmx.net> On 05.06.2009 13:44, Stefan Reinauer wrote: > On 05.06.2009 12:43 Uhr, Carl-Daniel Hailfinger wrote: > >> /* Report the amount of memory. */ >> - printk_spew("RAM: 0x%08x kB\n", tom_k); >> + printk_debug("RAM end at 0x%08x kB, hole starts at 0x%08x kB\n", >> + tom_k, hole_startk); >> >> /* Now set top of memory */ >> msr_t msr; >> if (tom_k > (4*1024*1024)) { >> + printk_raminit("Handling memory mapped above 4 GB\n"); >> + printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); >> >> > > I'm not sure it gets any easier to understand or less cryptic by calling > the amount of RAM end of RAM and printing it twice? > Actually, it's the end of RAM. On my 4 GB machine, tom_k is 0x00500000 which is 5*1024*1024. The hole starts at 3 GB in that configuration. However, printing it twice serves no purpose. I'll fix and resend. Regards, Carl-Daniel -- http://www.hailfinger.org/ From urjaman at gmail.com Fri Jun 5 15:44:20 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 16:44:20 +0300 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <20090605124850.25117.qmail@stuge.se> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> Message-ID: <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> I'm essentially replying to two mails at once now ... On Fri, Jun 5, 2009 at 15:17, Carl-Daniel Hailfinger wrote: > The buffer management would be performed by the programmer driver. So if > your programmer can execute (or buffer) 1024 bytes of > commands/address/data, make sure flashrom accumulates no more than 1024 > bytes in its internal buffer before flushing its buffer to the device. > Actually this got me to thinking of the protocol and buffer storage format again. There would be commands to: - query buffer size (so different devices can support different amounts of buffer) - initialize/clear buffer - entering a write command to the buffer (with data and address) - appending to a previous write command with a byte - entering a delay command to the buffer (how long could it be? eg. is 16-bit udelay enough?) - execute buffer A write command with data and address would be if it's a single byte, 6 bytes on buffer - 1 byte op, 1 byte len, 3 byte addr, 1 byte data, but continuation with append data to buffer would be the minimalist 1 byte per byte, unless it's already 256 bytes of data inserted (encoded as 0-byte write) - then it would create a new write command. A delay would take 3 bytes on the buffer, 1 byte op, 2 byte delay value(?). This would allow for the programmer driver to feed the data to the device during flashrom execution, and upon the first read perform the execute buffer command. I think that with this format the AVR's SRAM is enough for this to work with all the parallel chips with 256 byte or less page size, propably even 512. (1 byte op, 1 byte len (0), 3 byte addr, 256 byte data = 261 bytes) And here i'm a bit worried about flow control - or actually the lack of it in my hardware. Making each command immediately return an "OK" byte - and waiting for it makes it way too slow, so I'm thinking of by default making those "add write/delay command to buffer" commands return nothing and adding a NOP command that returns a byte and a command that returns the size of the serial buffer on the device, so that the programmer driver can send n bytes of commands in a stream, then send NOP, then wait for answer, then again send n bytes. (Peter wrote:) (i lost the header when editing...) > I think these two issues go hand in hand. That's propably why i brought them both up in the same mail. > I think there are two parts to it. One is about the flashrom data > model, which has been expanded a little lately but really needs to be > very different. The timing properties you mention are required for > some chips and other chip types have other required property sets. > > The challenge here is to create a complete data model. > > > The second part is to communicate that data from flashrom to > satellite entities which all implement the same state machine. Hmm programming a satellite remotely :P (j/k) > The challenge here is to create a state machine which works for > abstracting all the different ways we want to reach flash chips. > You think of this a bit more abstract than i usually do, but basically i agree. Continuing on the protocol - it would need (ofcourse) also an n-byte read, I'm thinking that it could even be with 24-bit n so that the device could be instructed to read the entire chip in a single operation. Then maybe some command to return information about programmer functionality would be good - eg. - what bus type(s) it supports - if parallel, how many address lines it has attached to the chip socket - actually offtopic, but i think it would be good for external programmers to have the ability to report the size of chip they support (eg 128k for the 3C905B) and for flashrom to issue a warning in case a bigger chip is detected (dont bail - it's still of some use for some purposes where you dont for example need the lower half of an 256k chip). I think that LPC and FWH can be operated over the same read/write/delay protocol as parallel, but i dont know how different SPI chips are and what extensions (if any) using them would need. And in reality my programmer supports only parallel (at the moment), so that will be my priority - but i hope i can make a protocol that suits any chip type well. -- urjaman From svn at coreboot.org Fri Jun 5 15:46:18 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 15:46:18 +0200 Subject: [coreboot] [flashrom] r576 - trunk Message-ID: Author: hailfinger Date: 2009-06-05 15:46:17 +0200 (Fri, 05 Jun 2009) New Revision: 576 Modified: trunk/flashchips.c Log: Add probe timings forgotten in r569. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Paul Menzel Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-05 13:30:49 UTC (rev 575) +++ trunk/flashchips.c 2009-06-05 13:46:17 UTC (rev 576) @@ -35,7 +35,7 @@ * Bus Type, * Total size (kB), Page size (B), * Test status, - * Probe function, Probe function timing argument, Erase function, Write function, Read function + * Probe function, Probe function timing, Erase function, Write function, Read function */ { @@ -176,6 +176,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -191,6 +192,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -206,6 +208,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -221,6 +224,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -236,6 +240,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -251,6 +256,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -266,6 +272,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -281,6 +288,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -296,6 +304,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -311,6 +320,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -326,6 +336,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, @@ -341,6 +352,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -356,6 +368,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -371,6 +384,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -387,6 +401,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -402,6 +417,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, @@ -482,6 +498,7 @@ .page_size = 1056 /* No power of two sizes */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL /* Incompatible Page write */, .read = NULL /* Incompatible read */, @@ -497,6 +514,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -512,6 +530,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -527,6 +546,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -542,6 +562,7 @@ .page_size = 256 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -557,6 +578,7 @@ .page_size = 512 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -572,6 +594,7 @@ .page_size = 528 /* No power of two sizes */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL /* Incompatible read */, @@ -587,6 +610,7 @@ .page_size = 512 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -602,6 +626,7 @@ .page_size = 1024 /* Size can only be determined from status register */, .tested = TEST_BAD_READ, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -665,6 +690,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -888,6 +914,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_82802ab, + .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .erase = erase_82802ab, .write = write_82802ab, .read = read_memmapped, @@ -903,6 +930,7 @@ .page_size = 64 * 1024, .tested = TEST_OK_PREW, .probe = probe_82802ab, + .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .erase = erase_82802ab, .write = write_82802ab, .read = read_memmapped, @@ -918,6 +946,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -933,6 +962,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -948,6 +978,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -963,6 +994,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -978,6 +1010,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -993,6 +1026,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1008,6 +1042,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1023,6 +1058,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1038,6 +1074,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1053,6 +1090,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1068,6 +1106,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1131,6 +1170,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1146,6 +1186,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1161,6 +1202,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1176,6 +1218,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1191,6 +1234,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1206,6 +1250,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1221,6 +1266,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1236,6 +1282,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1251,6 +1298,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1266,6 +1314,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1281,6 +1330,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1360,6 +1410,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1375,6 +1426,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1390,6 +1442,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1405,6 +1458,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1420,6 +1474,7 @@ .page_size = 64*1024, .tested = TEST_OK_PR, .probe = probe_spi_rems, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1435,6 +1490,7 @@ .page_size = 64*1024, .tested = TEST_OK_PR, .probe = probe_spi_rems, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1450,6 +1506,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_60_c7, .write = spi_chip_write_1, .read = spi_chip_read, @@ -1881,6 +1938,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1896,6 +1954,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1911,6 +1970,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1926,6 +1986,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1941,6 +2002,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_res, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1956,6 +2018,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1971,6 +2034,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1986,6 +2050,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2001,6 +2066,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2016,6 +2082,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2367,6 +2434,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2382,6 +2450,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2397,6 +2466,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2412,6 +2482,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, @@ -2651,6 +2722,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2666,6 +2738,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2681,6 +2754,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2696,6 +2770,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2711,6 +2786,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, @@ -2726,6 +2802,7 @@ .page_size = 256, .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .erase = NULL, .write = NULL, .read = NULL, From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 15:47:50 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 15:47:50 +0200 Subject: [coreboot] [PATCH] flashrom: add probe timings forgotten in r569 In-Reply-To: <1244114172.6062.148.camel@mattotaupa.wohnung.familie-menzel.net> References: <4A26B379.60404@gmx.net> <1244114172.6062.148.camel@mattotaupa.wohnung.familie-menzel.net> Message-ID: <4A292206.5070600@gmx.net> On 04.06.2009 13:16, Paul Menzel wrote: > Am Mittwoch, den 03.06.2009, 19:31 +0200 schrieb Carl-Daniel Hailfinger: > >> Add probe timings forgotten in r569. >> >> Signed-off-by: Carl-Daniel Hailfinger >> > > Applies, compiles, reads and verifies fine. I was not able to test > writing. > > Acked-by: Paul Menzel > Thanks, committed in r576. Regards, Carl-Daniel -- http://www.hailfinger.org/ From bari at onelabs.com Fri Jun 5 15:51:18 2009 From: bari at onelabs.com (bari) Date: Fri, 05 Jun 2009 08:51:18 -0500 Subject: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset In-Reply-To: <2F3951A78535124D960B1EFBB992F6D102832B6A@mailserver.sienet.local> References: <2F3951A78535124D960B1EFBB992F6D102832B6A@mailserver.sienet.local> Message-ID: <4A2922D6.1040907@onelabs.com> Gaechter, Stefan wrote: > hi, > > a view weeks ago i read about the start of a menlow port. > has anybody started the port? I don't think anyone has specs yet. -Bari From fishbaoz at hotmail.com Fri Jun 5 15:51:44 2009 From: fishbaoz at hotmail.com (Zheng Bao) Date: Fri, 5 Jun 2009 13:51:44 +0000 Subject: [coreboot] [PATCH] Fix AMD 690 HIGH_TABLES In-Reply-To: <4A28F8C2.4090004@gmx.net> References: <4A28F8C2.4090004@gmx.net> Message-ID: I will have a vocation. I am gonna test next Thursday. Zheng > Date: Fri, 5 Jun 2009 12:51:46 +0200 > From: c-d.hailfinger.devel.2006 at gmx.net > To: coreboot at coreboot.org; Zheng.Bao at amd.com > Subject: [coreboot] [PATCH] Fix AMD 690 HIGH_TABLES > > Zheng, can you please test this with HIGH_TABLES enabled (and a new FILO)? > A full log would be appreciated. Thanks. > > This hopefully will fix AMD 690 HIGH_TABLES or at least give me an > insight into why HIGH_TABLES fails. > > Signed-off-by: Carl-Daniel Hailfinger > > Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c > =================================================================== > --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) > +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) > @@ -896,6 +896,7 @@ > #if HAVE_HIGH_TABLES==1 > #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB > extern uint64_t high_tables_base, high_tables_size; > +extern uint64_t uma_memory_base, uma_memory_size; > #endif > > static void pci_domain_set_resources(device_t dev) > @@ -1066,7 +1067,9 @@ > } > > > -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu > + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); > + if ((uma_memory_base >> 10) < mmio_basek) > + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); > > /* See if I need to split the region to accomodate pci memory space */ > if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { > @@ -1080,7 +1083,7 @@ > #if HAVE_HIGH_TABLES==1 > if (i==0 && high_tables_base==0) { > /* Leave some space for ACPI, PIRQ and MP tables */ > - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; > + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; > high_tables_size = HIGH_TABLES_SIZE * 1024; > printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, > high_tables_base); > @@ -1105,6 +1108,9 @@ > sizek -= (4*1024*1024 - mmio_basek); > } > } > + > + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); > + > /* If sizek == 0, it was split at mmio_basek without a hole. > * Don't create an empty ram_resource. > */ > @@ -1116,7 +1122,7 @@ > i, mmio_basek, basek, limitk); > if (i==0 && high_tables_base==0) { > /* Leave some space for ACPI, PIRQ and MP tables */ > - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; > + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; > high_tables_size = HIGH_TABLES_SIZE * 1024; > } > #endif > > > -- > http://www.hailfinger.org/ > _________________________________________________________________ Windows Live?: Keep your life in sync. Check it out! http://windowslive.com/explore?ocid=TXT_TAGLM_WL_t1_allup_explore_012009 -------------- next part -------------- An HTML attachment was scrubbed... URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 15:53:34 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 15:53:34 +0200 Subject: [coreboot] [PATCH] Fix AMD 690 HIGH_TABLES In-Reply-To: References: <4A28F8C2.4090004@gmx.net> Message-ID: <4A29235E.4020003@gmx.net> Hi Zheng, On 05.06.2009 15:51, Zheng Bao wrote: > I will have a vocation. I am gonna test next Thursday. > Enjoy your vacation! Regards, Carl-Daniel From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 16:18:19 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 16:18:19 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> Message-ID: <4A29292B.5000309@gmx.net> On 05.06.2009 15:44, Urja Rannikko wrote: > I'm essentially replying to two mails at once now ... > > On Fri, Jun 5, 2009 at 15:17, Carl-Daniel > Hailfinger wrote: > >> The buffer management would be performed by the programmer driver. So if >> your programmer can execute (or buffer) 1024 bytes of >> commands/address/data, make sure flashrom accumulates no more than 1024 >> bytes in its internal buffer before flushing its buffer to the device. >> One of the most important design considerations is to make buffer management optional. On-board programming doesn't need it (and would be slowed down by it), lots of external programmers don't need it either. > Actually this got me to thinking of the protocol and buffer storage > format again. > There would be commands to: > - query buffer size (so different devices can support different > amounts of buffer) > OK. > - initialize/clear buffer > Maybe two separate functions for this. > - entering a write command to the buffer (with data and address) > OK. > - appending to a previous write command with a byte > Special case, should not end up in the interface. Either the programmer driver performs auto-erge of write commands or it simply enters a new write command. > - entering a delay command to the buffer (how long could it be? eg. is > 16-bit udelay enough?) > Some chips have delays of more than 60 seconds (yes, not ms or us). 32bit udelay is the way to go forward. If your programmer can't handle a given delay length, the driver should either split it into multiple delays upon downloading it to the device or reject enqueuing such a delay. > - execute buffer > OK. - read byte is missing from your design. For SPI, you also need select_chip() and deselect_chip(). Please make sure that the flashrom buffer format has no dependencies on the programmer buffer format. Since hardware is more difficult to change than software, we definitely want to keep the flashrom buffer design changeable without breaking hardware. 16-bit vs. 32-bit delays could be one such difference. Some external programmers (Cheetah, some FT2232 designs) also have their own buffer management. Any buffer management design will have to be compatible with them. > A write command with data and address would be if it's a single byte, > 6 bytes on buffer - 1 byte op, 1 byte len, 3 byte addr, 1 byte data, > but continuation with append data to buffer would be the minimalist 1 > byte per byte, unless it's already 256 bytes of data inserted (encoded > as 0-byte write) - then it would create a new write command. A delay > would take 3 bytes on the buffer, 1 byte op, 2 byte delay value(?). > > This would allow for the programmer driver to feed the data to the > device during flashrom execution, and upon the first read perform the > execute buffer command. I think that with this format the AVR's SRAM > is enough for this to work with all the parallel chips with 256 byte > or less page size, propably even 512. (1 byte op, 1 byte len (0), 3 > byte addr, 256 byte data = 261 bytes) > > And here i'm a bit worried about flow control - or actually the lack > of it in my hardware. Making each command immediately return an "OK" > byte - and waiting for it makes it way too slow, so I'm thinking of by > default making those "add write/delay command to buffer" commands > return nothing and adding a NOP command that returns a byte and a > command that returns the size of the serial buffer on the device, so > that the programmer driver can send n bytes of commands in a stream, > then send NOP, then wait for answer, then again send n bytes. > What you want is an explicit execute_buffer() function. Writes and delays don't return anything by default. The programmer driver decides when to issue execute_buffer(). > Peter wrote: > >> I think there are two parts to it. One is about the flashrom data >> model, which has been expanded a little lately but really needs to be >> very different. The big problem with a totally different data model is that we can't know for sure if it will work for everything in the future. Our current model was extended when it didn't fit anymore and each time it seemed that the model would be good enough after the change. There's no guarantee that we won't fall into the same trap with a complete redesign. >> The timing properties you mention are required for >> some chips and other chip types have other required property sets. >> >> The challenge here is to create a complete data model. >> Agreed. However, the data model needs to be understandable as well. >> The second part is to communicate that data from flashrom to >> satellite entities which all implement the same state machine. >> We have two state machines: One in the external flasher driver and one in the external flasher. The only thing we need is translation capability. >> The challenge here is to create a state machine which works for >> abstracting all the different ways we want to reach flash chips. >> > > You think of this a bit more abstract than i usually do, but basically i agree. > > Continuing on the protocol - it would need (ofcourse) also an n-byte read, > I'm thinking that it could even be with 24-bit n so that the device > could be instructed to read the entire chip in a single operation. > That's what I wrote about the chip_readn function. > Then maybe some command to return information about programmer > functionality would be good - eg. > - what bus type(s) it supports > The code already does that. > - if parallel, how many address lines it has attached to the chip socket > - actually offtopic, but i think it would be good for external > programmers to have the ability to report the size of chip they > support (eg 128k for the 3C905B) and for flashrom to issue a warning > in case a bigger chip is detected (dont bail - it's still of some use > for some purposes where you dont for example need the lower half of an > 256k chip). > Let's add programmer_can_access(struct flashchip *flash) which performs size checking etc so that probe_* can indeed return success even for too big chips. Some SPI controllers need that badly. > I think that LPC and FWH can be operated over the same > read/write/delay protocol as parallel, but > i dont know how different SPI chips are and what extensions (if any) > using them would need. > > And in reality my programmer supports only parallel (at the moment), > so that will be my priority - but i hope i can make a protocol that > suits any chip type well. > For SPI, the design is necessarily different, but I'll submit a driver for the TotalPhase Cheetah SPI programmer soon. Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Fri Jun 5 16:19:05 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 08:19:05 -0600 Subject: [coreboot] Looking for pci-e memory In-Reply-To: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> References: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> Message-ID: <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> On Sat, May 16, 2009 at 4:19 PM, ron minnich wrote: > for a project. I need a pci-e card that has memory -- nothing else. I'm curious about this project and wondering if you found what you were looking for (did a VGA card work out, or did you need larger RAM than that?). I'm trying to write the code to replace raminit with a PCI device's memory. I think I'm making it harder than it needs to be and I'm wondering if you already have something like that going. Thanks, Myles From urjaman at gmail.com Fri Jun 5 16:43:47 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 17:43:47 +0300 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <4A29292B.5000309@gmx.net> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> Message-ID: <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> On Fri, Jun 5, 2009 at 17:18, Carl-Daniel Hailfinger wrote: >> - appending to a previous write command with a byte >> > > Special case, should not end up in the interface. Either the programmer > driver performs auto-erge of write commands or it simply enters a new > write command. > The point is here that the buffer management isnt visible outside of the programmer driver. Eg. when the programmers chip_writeb is called, it will check if the address is previous_address+1 and then send the combine. >> - entering a delay command to the buffer (how long could it be? eg. is >> 16-bit udelay enough?) >> > > Some chips have delays of more than 60 seconds (yes, not ms or us). > 32bit udelay is the way to go forward. If your programmer can't handle a > given delay length, the driver should either split it into multiple > delays upon downloading it to the device or reject enqueuing such a delay. > You mean delays or timeouts? I (@work) only had access to a bit old flashrom source (a webview or "LXR" would be nice, is there?), but there were no calls to myusec_delay bigger than the 10ms used for AT29C020 detect. > >> - execute buffer >> > > OK. > > - read byte > is missing from your design. I was listing only commands related to the buffer handling (at the serial protocol level, between the device and the flashrom external programmer driver) > > For SPI, you also need select_chip() and deselect_chip(). > I'll have to read more on SPI flash chips someday. > Please make sure that the flashrom buffer format has no dependencies on > the programmer buffer format. Since hardware is more difficult to change > than software, we definitely want to keep the flashrom buffer design > changeable without breaking hardware. 16-bit vs. 32-bit delays could be > one such difference. > The point in this was that there would be no buffer on flashrom's side - only on the device memory - although that buffer would be handled by the in-flashrom external programmer driver. I did consider skipping that write-combining so that the device would compress the stream, but then i thought that when using real serial, that would slow down writing manyfold to pass all the addresses to the device (AVR). > Some external programmers (Cheetah, some FT2232 designs) also have their > own buffer management. Any buffer management design will have to be > compatible with them. > > What you want is an explicit execute_buffer() function. Writes and > delays don't return anything by default. The programmer driver decides > when to issue execute_buffer(). > There will be execute buffer command on the AVR, but if (eg.) the AVR (for any reason) cannot process serial data as fast as it can receive serial data to it's serial buffer, then sending more bytes of commands than it's serial buffer to it could cause it to lose data. Eg. you need to be able to ask it that it has processed all the commands given. >> Peter wrote: >> >>> I think there are two parts to it. One is about the flashrom data >>> model, which has been expanded a little lately but really needs to be >>> very different. > > The big problem with a totally different data model is that we can't > know for sure if it will work for everything in the future. Our current > model was extended when it didn't fit anymore and each time it seemed > that the model would be good enough after the change. There's no > guarantee that we won't fall into the same trap with a complete redesign. > > >>> The timing properties you mention are required for >>> some chips and other chip types have other required property sets. >>> >>> The challenge here is to create a complete data model. >>> > > Agreed. However, the data model needs to be understandable as well. > > >>> The second part is to communicate that data from flashrom to >>> satellite entities which all implement the same state machine. >>> > > We have two state machines: One in the external flasher driver and one > in the external flasher. The only thing we need is translation capability. > > >>> The challenge here is to create a state machine which works for >>> abstracting all the different ways we want to reach flash chips. >>> I wouldnt go and change a lot of things just to find out that the new design has some big flaw... >> Then maybe some command to return information about programmer >> functionality would be good - eg. >> - what bus type(s) it supports >> > > The code already does that. I'm talking about the serial protocol - i knew that flashrom already has support for this information. > > Let's add > programmer_can_access(struct flashchip *flash) > which performs size checking etc so that probe_* can indeed return > success even for too big chips. Some SPI controllers need that badly. > > Ok. -- urjaman From christian.leber at ziti.uni-heidelberg.de Fri Jun 5 16:53:07 2009 From: christian.leber at ziti.uni-heidelberg.de (Christian Leber) Date: Fri, 5 Jun 2009 16:53:07 +0200 Subject: [coreboot] Looking for pci-e memory In-Reply-To: <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> References: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> Message-ID: <200906051653.07579.christian.leber@ziti.uni-heidelberg.de> On Friday 05 June 2009 16:19:05 Myles Watson wrote: Hi Myles, > I'm trying to write the code to replace raminit with a > PCI device's memory. why do you want to do this? To not have to do raminit on intel? Christian From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 16:55:44 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 16:55:44 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> Message-ID: <4A2931F0.4050507@gmx.net> On 05.06.2009 16:43, Urja Rannikko wrote: > On Fri, Jun 5, 2009 at 17:18, Carl-Daniel Hailfinger wrote: > >>> Then maybe some command to return information about programmer >>> functionality would be good - eg. >>> - what bus type(s) it supports >>> >> The code already does that. >> > > I'm talking about the serial protocol - i knew that flashrom already > has support for this information. > Sorry, can you elaborate? Which serial protocol are we talking about? Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Fri Jun 5 17:09:36 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 09:09:36 -0600 Subject: [coreboot] [PATCH] K8: Improve RAM init debug messages In-Reply-To: <4A291F03.1040001@gmx.net> References: <4A28F6D4.7070608@gmx.net> <4A290516.3050701@coresystems.de> <4A291F03.1040001@gmx.net> Message-ID: <2831fecf0906050809k70fe42cj13fe2e9b56c76337@mail.gmail.com> >> I'm not sure it gets any easier to understand or less cryptic by calling >> the amount of RAM end of RAM and printing it twice? >> > > Actually, it's the end of RAM. On my 4 GB machine, tom_k is 0x00500000 > which is 5*1024*1024. The hole starts at 3 GB in that configuration. > However, printing it twice serves no purpose. I'll fix and resend. I think it makes it easier to review patches like this (that only change debugging output) if you include before and after log snippets. Thanks, Myles From patrick at georgi-clan.de Fri Jun 5 17:10:22 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Fri, 5 Jun 2009 17:10:22 +0200 Subject: [coreboot] [PATCH]es: Fixes for AMD Fam10h Errata Message-ID: <200906051710.23113.patrick@georgi-clan.de> Hi, attached patches implement two errata fixes. Patrick -------------- next part -------------- A non-text attachment was scrubbed... Name: 20090605-1-erratum-343.diff Type: text/x-patch Size: 2595 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 20090605-2-erratum-350.diff Type: text/x-patch Size: 3833 bytes Desc: not available URL: From bari at onelabs.com Fri Jun 5 17:22:25 2009 From: bari at onelabs.com (bari) Date: Fri, 05 Jun 2009 10:22:25 -0500 Subject: [coreboot] Epia-m700 Patch Message-ID: <4A293831.3070808@onelabs.com> Here's an untested epia-m700 patch. VIA vx800 + C7. Please review and feel free to clean it up. -Bari -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: epia-m700 URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 17:36:06 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 17:36:06 +0200 Subject: [coreboot] [PATCH] flashrom: Add chip_{read,write}n Message-ID: <4A293B66.106@gmx.net> Sometimes we want to read/write more than 4 bytes of chip content at once. Add chip_{read,write}n to the external flasher infrastructure which read/write n bytes at once. Fix a few places where the code used memcpy/memcmp although that is strictly impossible with external flashers. Place a FIXME in the layout.c code because usage is not totally clear and needs to be fixed to support external flashers. As a nice side benefit, we get a noticeable speedup for builtin flash reading which is now a memcpy() of the full flash area instead of a series of single-byte reads. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-chip_readn_writen/flash.h =================================================================== --- flashrom-chip_readn_writen/flash.h (Revision 576) +++ flashrom-chip_readn_writen/flash.h (Arbeitskopie) @@ -100,9 +100,11 @@ void (*chip_writeb) (uint8_t val, chipaddr addr); void (*chip_writew) (uint16_t val, chipaddr addr); void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); uint8_t (*chip_readb) (const chipaddr addr); uint16_t (*chip_readw) (const chipaddr addr); uint32_t (*chip_readl) (const chipaddr addr); + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); }; extern const struct programmer_entry programmer_table[]; @@ -115,9 +117,11 @@ void chip_writeb(uint8_t val, chipaddr addr); void chip_writew(uint16_t val, chipaddr addr); void chip_writel(uint32_t val, chipaddr addr); +void chip_writen(uint8_t *buf, chipaddr addr, size_t len); uint8_t chip_readb(const chipaddr addr); uint16_t chip_readw(const chipaddr addr); uint32_t chip_readl(const chipaddr addr); +void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -646,6 +650,7 @@ uint8_t internal_chip_readb(const chipaddr addr); uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); +void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -656,8 +661,10 @@ void fallback_unmap(void *virt_addr, size_t len); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); +void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); +void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #if defined(__FreeBSD__) || defined(__DragonFly__) extern int io_fd; #endif @@ -671,9 +678,11 @@ void dummy_chip_writeb(uint8_t val, chipaddr addr); void dummy_chip_writew(uint16_t val, chipaddr addr); void dummy_chip_writel(uint32_t val, chipaddr addr); +void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len); uint8_t dummy_chip_readb(const chipaddr addr); uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); +void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Index: flashrom-chip_readn_writen/dummyflasher.c =================================================================== --- flashrom-chip_readn_writen/dummyflasher.c (Revision 576) +++ flashrom-chip_readn_writen/dummyflasher.c (Arbeitskopie) @@ -103,6 +103,18 @@ printf_debug("%s: addr=0x%lx, val=0x%08x\n", __func__, addr, val); } +void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len) +{ + size_t i; + printf_debug("%s: addr=0x%lx, len=0x%08lx, writing data (hex):", + __func__, addr, (unsigned long)len); + for (i = 0; i < len; i++) { + if ((i % 16) == 0) + printf_debug("\n"); + printf_debug("%02x ", buf[i]) + } +} + uint8_t dummy_chip_readb(const chipaddr addr) { printf_debug("%s: addr=0x%lx, returning 0xff\n", __func__, addr); @@ -121,6 +133,14 @@ return 0xffffffff; } +void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) +{ + printf_debug("%s: addr=0x%lx, len=0x%lx, returning array of 0xff\n", + __func__, addr, (unsigned long)len); + memset(buf, 0xff, len); + return; +} + int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { Index: flashrom-chip_readn_writen/stm50flw0x0x.c =================================================================== --- flashrom-chip_readn_writen/stm50flw0x0x.c (Revision 576) +++ flashrom-chip_readn_writen/stm50flw0x0x.c (Arbeitskopie) @@ -27,6 +27,7 @@ */ #include +#include #include "flash.h" void protect_stm50flw0x0x(chipaddr bios) @@ -255,6 +256,7 @@ int total_size = flash->total_size * 1024; int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; + uint8_t *tmpbuf = malloc(page_size); printf("Programming page: \n"); for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { @@ -269,8 +271,8 @@ * are not erased and rewritten; data is retained also * in sudden power off situations */ - if (!memcmp((void *)(buf + i * page_size), - (void *)(bios + i * page_size), page_size)) { + chip_readn(tmpbuf, bios + i * page_size, page_size); + if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { printf("SKIPPED\n"); continue; } @@ -284,6 +286,7 @@ } printf("\n"); protect_stm50flw0x0x(bios); + free(tmpbuf); return rc; } Index: flashrom-chip_readn_writen/flashrom.c =================================================================== --- flashrom-chip_readn_writen/flashrom.c (Revision 576) +++ flashrom-chip_readn_writen/flashrom.c (Arbeitskopie) @@ -43,9 +43,11 @@ .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, .chip_readl = internal_chip_readl, + .chip_readn = internal_chip_readn, .chip_writeb = internal_chip_writeb, .chip_writew = internal_chip_writew, .chip_writel = internal_chip_writel, + .chip_writen = fallback_chip_writen, }, { @@ -56,9 +58,11 @@ .chip_readb = dummy_chip_readb, .chip_readw = dummy_chip_readw, .chip_readl = dummy_chip_readl, + .chip_readn = dummy_chip_readn, .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .chip_writen = dummy_chip_writen, }, { @@ -69,9 +73,11 @@ .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, .chip_writeb = nic3com_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, }, { @@ -82,9 +88,11 @@ .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, .chip_writeb = satasii_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, }, { @@ -93,11 +101,13 @@ .map_flash_region = dummy_map, .unmap_flash_region = dummy_unmap, .chip_readb = dummy_chip_readb, - .chip_readw = dummy_chip_readw, - .chip_readl = dummy_chip_readl, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, .chip_writeb = dummy_chip_writeb, - .chip_writew = dummy_chip_writew, - .chip_writel = dummy_chip_writel, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, }, {}, @@ -140,6 +150,11 @@ programmer_table[programmer].chip_writel(val, addr); } +void chip_writen(uint8_t *buf, chipaddr addr, size_t len) +{ + programmer_table[programmer].chip_writen(buf, addr, len); +} + uint8_t chip_readb(const chipaddr addr) { return programmer_table[programmer].chip_readb(addr); @@ -155,6 +170,12 @@ return programmer_table[programmer].chip_readl(addr); } +void chip_readn(uint8_t *buf, chipaddr addr, size_t len) +{ + programmer_table[programmer].chip_readn(buf, addr, len); + return; +} + void map_flash_registers(struct flashchip *flash) { size_t size = flash->total_size * 1024; @@ -164,12 +185,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf) { - int i; - - /* We could do a memcpy as optimization if the flash is onboard */ - //memcpy(buf, (const char *)flash->virtual_memory, flash->total_size * 1024); - for (i = 0; i < flash->total_size * 1024; i++) - buf[i] = chip_readb(flash->virtual_memory + i); + chip_readn(buf, flash->virtual_memory, flash->total_size * 1024); return 0; } @@ -774,14 +790,10 @@ */ // //////////////////////////////////////////////////////////// - /* FIXME: This memcpy will not work for SPI nor external flashers. - * Convert to chip_readb. - */ if (exclude_end_position - exclude_start_position > 0) - memcpy(buf + exclude_start_position, - (const char *)flash->virtual_memory + - exclude_start_position, - exclude_end_position - exclude_start_position); + chip_readn(buf + exclude_start_position, + flash->virtual_memory + exclude_start_position, + exclude_end_position - exclude_start_position); exclude_start_page = exclude_start_position / flash->page_size; if ((exclude_start_position % flash->page_size) != 0) { @@ -792,6 +804,7 @@ // This should be moved into each flash part's code to do it // cleanly. This does the job. + /* FIXME: Adapt to the external flasher infrastructure. */ handle_romentries(buf, (uint8_t *) flash->virtual_memory); // //////////////////////////////////////////////////////////// Index: flashrom-chip_readn_writen/internal.c =================================================================== --- flashrom-chip_readn_writen/internal.c (Revision 576) +++ flashrom-chip_readn_writen/internal.c (Arbeitskopie) @@ -165,6 +165,12 @@ return mmio_readl((void *) addr); } +void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) +{ + memcpy(buf, (void *)addr, len); + return; +} + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; @@ -237,3 +243,19 @@ val |= chip_readw(addr + 2) << 16; return val; } + +void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len) +{ + size_t i; + for (i = 0; i < len; i++) + chip_writeb(buf[i], addr + i); + return; +} + +void fallback_chip_readn(uint8_t *buf, chipaddr addr, size_t len) +{ + size_t i; + for (i = 0; i < len; i++) + buf[i] = chip_readb(addr + i); + return; +} Index: flashrom-chip_readn_writen/layout.c =================================================================== --- flashrom-chip_readn_writen/layout.c (Revision 576) +++ flashrom-chip_readn_writen/layout.c (Arbeitskopie) @@ -220,6 +220,7 @@ if (rom_entries[i].included) continue; + /* FIXME: Adapt to the external flasher infrastructure. */ memcpy(buffer + rom_entries[i].start, content + rom_entries[i].start, rom_entries[i].end - rom_entries[i].start); Index: flashrom-chip_readn_writen/82802ab.c =================================================================== --- flashrom-chip_readn_writen/82802ab.c (Revision 576) +++ flashrom-chip_readn_writen/82802ab.c (Arbeitskopie) @@ -27,6 +27,7 @@ */ #include +#include #include "flash.h" // I need that Berkeley bit-map printer @@ -172,6 +173,7 @@ int total_size = flash->total_size * 1024; int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; + uint8_t *tmpbuf = malloc(page_size); printf("Programming page: \n"); for (i = 0; i < total_size / page_size; i++) { @@ -186,8 +188,8 @@ * or not erased and rewritten; their data is retained also in * sudden power off situations */ - if (!memcmp((void *)(buf + i * page_size), - (void *)(bios + i * page_size), page_size)) { + chip_readn(tmpbuf, bios + i * page_size, page_size); + if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { printf("SKIPPED\n"); continue; } @@ -199,6 +201,7 @@ } printf("\n"); protect_jedec(bios); + free(tmpbuf); return 0; } -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_chip_readn_writen.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 17:41:26 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 17:41:26 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> Message-ID: <4A293CA6.1050802@gmx.net> On 05.06.2009 16:43, Urja Rannikko wrote: > On Fri, Jun 5, 2009 at 17:18, Carl-Daniel > Hailfinger wrote: > >>> - appending to a previous write command with a byte >>> >> Special case, should not end up in the interface. Either the programmer >> driver performs auto-erge of write commands or it simply enters a new >> write command. >> > > The point is here that the buffer management isnt visible outside of > the programmer driver. Eg. when the programmers chip_writeb is called, > it will check if the address is previous_address+1 and then send the > combine. > Looks nice. Where's the problem? Sorry if I am being dense. >>> - entering a delay command to the buffer (how long could it be? eg. is >>> 16-bit udelay enough?) >>> >>> >> Some chips have delays of more than 60 seconds (yes, not ms or us). >> 32bit udelay is the way to go forward. If your programmer can't handle a >> given delay length, the driver should either split it into multiple >> delays upon downloading it to the device or reject enqueuing such a delay. >> >> > You mean delays or timeouts? I (@work) only had access to a bit old > flashrom source (a webview or "LXR" would be nice, is there?), but > Needs to be done for the new flashrom tree. I'll ping Stefan or Patrick. > there were no calls to myusec_delay bigger than the 10ms used for > AT29C020 detect. > We have sleep(1) in some places. >>> - execute buffer >>> >>> >> OK. >> >> - read byte >> is missing from your design. >> > > I was listing only commands related to the buffer handling (at the > serial protocol level, between the device and the flashrom external > programmer driver) > The Cheetah wants read commands to be added to the device buffer... Anyway, I just sent a patch which adds multi-byte read and write to the external programmer interface. Can you take a look at it? Regards, Carl-Daniel -- http://www.hailfinger.org/ From christian.leber at ziti.uni-heidelberg.de Fri Jun 5 17:49:52 2009 From: christian.leber at ziti.uni-heidelberg.de (Christian Leber) Date: Fri, 5 Jun 2009 17:49:52 +0200 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20906041604i2179c536wdd90a769eb3f4874@mail.gmail.com> References: <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906041604i2179c536wdd90a769eb3f4874@mail.gmail.com> Message-ID: <200906051749.53385.christian.leber@ziti.uni-heidelberg.de> On Friday 05 June 2009 01:04:56 Marc Jones wrote: Hi Marc > I think it should just be a package difference. It looks like you hit > the same thing as Ward without the HTX card. Not sure why that changes > things. Either some CPU register is set wrong or it is interpreted wrong, because a link is found that is neither C(oherent) nor NC. It tries to set then PHY options and waits afterwards forever for the completion. I attached 2 logs (with and without htx card) and a .c file that spills out that stuff. @Ward: probably you could try with this init_cpu.c this to see if on you box the same is happening. Christian -------------- next part -------------- coreboot-2.0.0-r4333:4334M_Fallback Fri Jun 5 16:58:18 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1062, current patch id = 0x00000000 microcode: patch id to apply = 0x0100009f microcode: updated to patch id = 0x0100009f success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 01 01 00 Exit amd_ht_init() nodes = 2 after 2e0 = pci_read_config32(NODE_HT(0), 0x64); after sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); before cpuSetAMDPCI 0 of 2 cpuSetAMDPCI 00after AMD_SetupPSIVID_d(platform, node); after for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=15 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=1a cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=12 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=17 cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=1e cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=16 cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3d cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3e cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3e cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=57 cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=52 cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5d before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[4].linktype=2 before AMD_SetHtPhyRegister(0,1,4) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[4].linktype=2 before AMD_SetHtPhyRegister(0,2,4) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7f cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(0,0,5) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7e cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(0,1,5) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7e cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(0,2,5) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=95 cpuSetAMDPCI: fam10_htphy_default[6].linktype=1 before AMD_SetHtPhyRegister(0,0,6) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9e before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=96 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9f cpuSetAMDPCI: fam10_htphy_default[7].linktype=1 before AMD_SetHtPhyRegister(0,0,7) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9a before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9a before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=b5 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=ba cpuSetAMDPCI: fam10_htphy_default[8].linktype=2 before AMD_SetHtPhyRegister(0,1,8) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=b2 cpuSetAMDPCI: fam10_htphy_default[8].linktype=2 before AMD_SetHtPhyRegister(0,2,8) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=d7 cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(0,0,9) AMD_SetHtPhyRegister: phyReg=c00052c1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=de cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(0,1,9) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=d6 cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(0,2,9) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) after for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { done before cpuSetAMDPCI 1 of 2 cpuSetAMDPCI 01after AMD_SetupPSIVID_d(platform, node); after for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=1a cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(1,0,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=15 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(1,1,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=12 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(1,2,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=1e cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(1,0,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=17 cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(1,1,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=16 cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(1,2,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3e cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(1,0,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3d cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(1,1,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3e cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(1,2,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(1,0,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=57 cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(1,1,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=52 cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(1,2,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[4].linktype=2 before AMD_SetHtPhyRegister(1,0,4) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5d before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[4].linktype=2 before AMD_SetHtPhyRegister(1,2,4) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7e cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(1,0,5) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7f cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(1,1,5) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7e cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(1,2,5) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9e before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=95 cpuSetAMDPCI: fam10_htphy_default[6].linktype=1 before AMD_SetHtPhyRegister(1,1,6) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=96 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9a before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9f cpuSetAMDPCI: fam10_htphy_default[7].linktype=1 before AMD_SetHtPhyRegister(1,1,7) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9a before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=ba cpuSetAMDPCI: fam10_htphy_default[8].linktype=2 before AMD_SetHtPhyRegister(1,0,8) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=b5 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=b2 cpuSetAMDPCI: fam10_htphy_default[8].linktype=2 before AMD_SetHtPhyRegister(1,2,8) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=de cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(1,0,9) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=d7 cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(1,1,9) AMD_SetHtPhyRegister: phyReg=c00052c1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,2,192) before AMD_checkLinkType(1,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=d6 cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(1,2,9) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,3,0) after for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { done cpuSetAMDPCI finished Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 prep_fid_change finished before setup_remote_node 1 of 2 setup_remote_node: 01 done before start_node 1 of 2 Start node 01 done. finalize_node_setup end reached Wait all cor ce0orse 0st:a r t-e--d { APICID = 04 NODEID = 01 COREID = 00} --- im Cicorroe0c odset:ar teequdi ovna lennodte :re 0v 1 d Wa i=t 0 xa1ll0 62c,o rec0ursr estnatr ptaedt cdh oined _= s0taxr0t00_0o0th0e00r ccores(m)i roinciodte :no pdeat:c h00 id ctoroe asp:p 0l3y = S0txa01r0t 0o0t09hfer idmiorcer oc-o ndoed: euidp:d at0e0d ctoo rpesa:tc h03 : i= n0ixt0 1n00od00e9:f 0 1s u cccoersess 0 p3 c duSSettaArMtD MoStRh er core d-o nneo {{gindi:t _ 0fc1cci ooodr rrveeceixxxodr:::_ e as p--:-(--- s0---t 3 a{ i e sA1AAP)tPP aIIIaCCCrpIIItDDDeic di=== d a:p 000a04p321 DDD cNNNFiOOOIdDDDD:EEEV IIIIDDDD == = o n000000 A CPCCOO:ORR RE0EE4III === 000321}}} ------ ---ccc INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... -------------- next part -------------- coreboot-2.0.0-r4333:4334M_Fallback Fri Jun 5 16:58:18 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1062, current patch id = 0x00000000 microcode: patch id to apply = 0x0100009f microcode: updated to patch id = 0x0100009f success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() nodes = 2 after 2e0 = pci_read_config32(NODE_HT(0), 0x64); after sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); before cpuSetAMDPCI 0 of 2 cpuSetAMDPCI 00after AMD_SetupPSIVID_d(platform, node); after for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=15 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=1a cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=12 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=17 cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=1e cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=16 cpuSetAMDPCI: fam10_htphy_default[1].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,1) AMD_SetHtPhyRegister: phyReg=e000520a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3d cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3e cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=3e cpuSetAMDPCI: fam10_htphy_default[2].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,2) AMD_SetHtPhyRegister: phyReg=e000530a AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=57 cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(0,0,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(0,1,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=52 cpuSetAMDPCI: fam10_htphy_default[3].linktype=7fffffff before AMD_SetHtPhyRegister(0,2,3) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5d before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[4].linktype=2 before AMD_SetHtPhyRegister(0,1,4) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=5a cpuSetAMDPCI: fam10_htphy_default[4].linktype=2 before AMD_SetHtPhyRegister(0,2,4) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7f cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(0,0,5) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7e cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(0,1,5) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=7e cpuSetAMDPCI: fam10_htphy_default[5].linktype=2 before AMD_SetHtPhyRegister(0,2,5) AMD_SetHtPhyRegister: phyReg=c00052cf AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=95 cpuSetAMDPCI: fam10_htphy_default[6].linktype=1 before AMD_SetHtPhyRegister(0,0,6) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9e before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=96 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9f cpuSetAMDPCI: fam10_htphy_default[7].linktype=1 before AMD_SetHtPhyRegister(0,0,7) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9a before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=9a before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=b5 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=ba cpuSetAMDPCI: fam10_htphy_default[8].linktype=2 before AMD_SetHtPhyRegister(0,1,8) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=b2 cpuSetAMDPCI: fam10_htphy_default[8].linktype=2 before AMD_SetHtPhyRegister(0,2,8) AMD_SetHtPhyRegister: phyReg=c00052df AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) before AMD_CpuFindCapability(0,0,0) before AMD_checkLinkType(0,0,160) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=d7 cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(0,0,9) AMD_SetHtPhyRegister: phyReg=c00052c1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,1,160) before AMD_checkLinkType(0,1,192) AMD_checkLinkType: NC AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=de cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(0,1,9) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,2,192) before AMD_checkLinkType(0,2,0) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=d6 cpuSetAMDPCI: fam10_htphy_default[9].linktype=2 before AMD_SetHtPhyRegister(0,2,9) AMD_SetHtPhyRegister: phyReg=c00052d1 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(0,3,0) after for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { done before cpuSetAMDPCI 1 of 2 cpuSetAMDPCI 01after AMD_SetupPSIVID_d(platform, node); after for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { before AMD_CpuFindCapability(1,0,0) before AMD_checkLinkType(1,0,160) AMD_checkLinkType: HT1 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=12 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(1,0,0) AMD_SetHtPhyRegister: phyReg=80000000 AMD_SetHtPhyRegister: before do/while 1 AMD_SetHtPhyRegister: after do/while 1 AMD_SetHtPhyRegister: before do/while 2 AMD_SetHtPhyRegister: after do/while 2 before AMD_CpuFindCapability(1,1,160) before AMD_checkLinkType(1,1,192) AMD_checkLinkType: C AMD_checkLinkType: HT3 AMD_checkLinkType: GANGED AMD_checkLinkType: linktype=15 cpuSetAMDPCI: fam10_htphy_default[0].linktype=7fffffff before AMD_SetHtPhyRegister(1,1,0) AMD_SetHtPhyRegister: phyReg=0 AMD_SetHtPhyRegister: before do/while 1 -------------- next part -------------- A non-text attachment was scrubbed... Name: init_cpus.c Type: text/x-csrc Size: 26096 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 18:03:26 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 18:03:26 +0200 Subject: [coreboot] [PATCH] flashrom: Fix a bug in dummyflasher.c special case Message-ID: <4A2941CE.9050909@gmx.net> Fix a bug in dummyflasher.c special case where no type parameter is given. Tested. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-dummyflasher_type_fix/dummyflasher.c =================================================================== --- flashrom-dummyflasher_type_fix/dummyflasher.c (Revision 576) +++ flashrom-dummyflasher_type_fix/dummyflasher.c (Arbeitskopie) @@ -35,7 +35,7 @@ printf_debug("%s\n", __func__); /* "all" is equivalent to specifying no type. */ - if (!strcmp(dummytype, "all")) { + if (dummytype && (!strcmp(dummytype, "all"))) { free(dummytype); dummytype = NULL; } -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_dummyflasher_type_fix.diff URL: From stepan at coresystems.de Fri Jun 5 18:08:43 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 05 Jun 2009 18:08:43 +0200 Subject: [coreboot] Epia-m700 Patch In-Reply-To: <4A293831.3070808@onelabs.com> References: <4A293831.3070808@onelabs.com> Message-ID: <4A29430B.20008@coresystems.de> On 05.06.2009 17:22 Uhr, bari wrote: > Here's an untested epia-m700 patch. VIA vx800 + C7. > > Please review and feel free to clean it up. > > -Bari Is it on purpose, that half of the ram init is done in mainboard specific code? (DrivingClkPhaseData.c) Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From stepan at coresystems.de Fri Jun 5 18:09:44 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 05 Jun 2009 18:09:44 +0200 Subject: [coreboot] [PATCH]es: Fixes for AMD Fam10h Errata In-Reply-To: <200906051710.23113.patrick@georgi-clan.de> References: <200906051710.23113.patrick@georgi-clan.de> Message-ID: <4A294348.20703@coresystems.de> On 05.06.2009 17:10 Uhr, Patrick Georgi wrote: > Hi, > > attached patches implement two errata fixes. > > > Patrick > Acked-by: Stefan Reinauer -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From stepan at coresystems.de Fri Jun 5 18:11:28 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 05 Jun 2009 18:11:28 +0200 Subject: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset In-Reply-To: <4A2922D6.1040907@onelabs.com> References: <2F3951A78535124D960B1EFBB992F6D102832B6A@mailserver.sienet.local> <4A2922D6.1040907@onelabs.com> Message-ID: <4A2943B0.7090802@coresystems.de> On 05.06.2009 15:51 Uhr, bari wrote: > Gaechter, Stefan wrote: >> hi, >> >> a view weeks ago i read about the start of a menlow port. >> has anybody started the port? > > I don't think anyone has specs yet. > > -Bari > coresystems does. Best regards, Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From stepan at coresystems.de Fri Jun 5 18:13:10 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 05 Jun 2009 18:13:10 +0200 Subject: [coreboot] Looking for pci-e memory In-Reply-To: <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> References: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> Message-ID: <4A294416.9030308@coresystems.de> On 05.06.2009 16:19 Uhr, Myles Watson wrote: > On Sat, May 16, 2009 at 4:19 PM, ron minnich wrote: > >> for a project. I need a pci-e card that has memory -- nothing else. >> > > I'm curious about this project and wondering if you found what you > were looking for (did a VGA card work out, or did you need larger RAM > than that?). I'm trying to write the code to replace raminit with a > PCI device's memory. I think I'm making it harder than it needs to be > and I'm wondering if you already have something like that going. > Remember that, on a graphics card, the option rom usually has to initialize a DDR controller, too. What's this going to save? Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 18:28:41 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 18:28:41 +0200 Subject: [coreboot] [PATCH] flashrom: Add external programmer delay functions Message-ID: <4A2947B9.6000909@gmx.net> Add external programmer delay functions so external programmers can handle the delay on their own if needed. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-programmer_delay/flash.h =================================================================== --- flashrom-programmer_delay/flash.h (Revision 576) +++ flashrom-programmer_delay/flash.h (Arbeitskopie) @@ -103,6 +103,8 @@ uint8_t (*chip_readb) (const chipaddr addr); uint16_t (*chip_readw) (const chipaddr addr); uint32_t (*chip_readl) (const chipaddr addr); + + void (*delay) (int usecs); }; extern const struct programmer_entry programmer_table[]; @@ -118,6 +120,7 @@ uint8_t chip_readb(const chipaddr addr); uint16_t chip_readw(const chipaddr addr); uint32_t chip_readl(const chipaddr addr); +void programmer_delay(uint32_t usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -590,7 +593,7 @@ #define W_49V002FA 0x32 /* udelay.c */ -void myusec_delay(int time); +void myusec_delay(int usecs); void myusec_calibrate_delay(void); /* pcidev.c */ @@ -652,6 +655,7 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void internal_delay(int usecs); void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); void fallback_chip_writew(uint16_t val, chipaddr addr); Index: flashrom-programmer_delay/en29f002a.c =================================================================== --- flashrom-programmer_delay/en29f002a.c (Revision 576) +++ flashrom-programmer_delay/en29f002a.c (Arbeitskopie) @@ -37,7 +37,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -70,7 +70,7 @@ chip_writeb(0x55, bios + 0xAAA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -97,7 +97,7 @@ chipaddr dst = bios; //chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_chip_jedec(flash); printf("Programming page: "); Index: flashrom-programmer_delay/it87spi.c =================================================================== --- flashrom-programmer_delay/it87spi.c (Revision 576) +++ flashrom-programmer_delay/it87spi.c (Arbeitskopie) @@ -220,7 +220,7 @@ * This usually takes 1-10 ms, so wait in 1 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(1000); + programmer_delay(1000); return 0; } @@ -245,7 +245,7 @@ return result; spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } /* resume normal ops... */ OUTB(0x20, it8716f_flashport); Index: flashrom-programmer_delay/jedec.c =================================================================== --- flashrom-programmer_delay/jedec.c (Revision 576) +++ flashrom-programmer_delay/jedec.c (Arbeitskopie) @@ -73,7 +73,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x20, bios + 0x5555); - usleep(200); + programmer_delay(200); } void protect_jedec(chipaddr bios) @@ -82,7 +82,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_jedec(struct flashchip *flash) @@ -110,14 +110,14 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ - myusec_delay(probe_timing_enter); + programmer_delay(probe_timing_enter); /* Read product ID */ id1 = chip_readb(bios); @@ -139,11 +139,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(probe_timing_exit); + programmer_delay(probe_timing_exit); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); if (!oddparity(id1)) @@ -179,18 +179,18 @@ { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x30, bios + page); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -202,18 +202,18 @@ { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x50, bios + block); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -227,18 +227,18 @@ /* Issue the JEDEC Chip Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x10, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); Index: flashrom-programmer_delay/w29ee011.c =================================================================== --- flashrom-programmer_delay/w29ee011.c (Revision 576) +++ flashrom-programmer_delay/w29ee011.c (Arbeitskopie) @@ -38,17 +38,17 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x60, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -56,11 +56,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Index: flashrom-programmer_delay/sharplhf00l04.c =================================================================== --- flashrom-programmer_delay/sharplhf00l04.c (Revision 576) +++ flashrom-programmer_delay/sharplhf00l04.c (Arbeitskopie) @@ -46,9 +46,9 @@ #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -58,7 +58,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -85,7 +85,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -118,7 +118,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); Index: flashrom-programmer_delay/spi.c =================================================================== --- flashrom-programmer_delay/spi.c (Revision 576) +++ flashrom-programmer_delay/spi.c (Arbeitskopie) @@ -425,7 +425,7 @@ */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000000); return 0; } @@ -453,7 +453,7 @@ */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000000); return 0; } @@ -485,7 +485,7 @@ * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -511,7 +511,7 @@ * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -557,7 +557,7 @@ * This usually takes 15-800 ms, so wait in 10 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(10 * 1000); + programmer_delay(10 * 1000); return 0; } @@ -690,7 +690,7 @@ spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } return 0; @@ -748,13 +748,13 @@ return result; spi_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; spi_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } spi_write_disable(); return 0; Index: flashrom-programmer_delay/wbsio_spi.c =================================================================== --- flashrom-programmer_delay/wbsio_spi.c (Revision 576) +++ flashrom-programmer_delay/wbsio_spi.c (Arbeitskopie) @@ -159,7 +159,7 @@ OUTB(writearr[0], wbsio_spibase); OUTB(mode, wbsio_spibase + 1); - myusec_delay(10); + programmer_delay(10); if (!readcnt) return 0; @@ -203,7 +203,7 @@ for (pos = 0; pos < size; pos++) { spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } spi_write_disable(); return 0; Index: flashrom-programmer_delay/m29f002.c =================================================================== --- flashrom-programmer_delay/m29f002.c (Revision 576) +++ flashrom-programmer_delay/m29f002.c (Arbeitskopie) @@ -29,7 +29,7 @@ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; } @@ -44,7 +44,7 @@ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); /* program */ Index: flashrom-programmer_delay/w39v040c.c =================================================================== --- flashrom-programmer_delay/w39v040c.c (Revision 576) +++ flashrom-programmer_delay/w39v040c.c (Arbeitskopie) @@ -26,22 +26,22 @@ uint8_t id1, id2, lock; chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 1); lock = chip_readb(bios + 0xfff2); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); if (!oddparity(id1)) Index: flashrom-programmer_delay/sst28sf040.c =================================================================== --- flashrom-programmer_delay/sst28sf040.c (Revision 576) +++ flashrom-programmer_delay/sst28sf040.c (Arbeitskopie) @@ -94,16 +94,16 @@ uint8_t id1, id2; chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(READ_ID, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); - myusec_delay(10); + programmer_delay(10); id2 = chip_readb(bios + 0x01); chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -121,7 +121,7 @@ chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Index: flashrom-programmer_delay/stm50flw0x0x.c =================================================================== --- flashrom-programmer_delay/stm50flw0x0x.c (Revision 576) +++ flashrom-programmer_delay/stm50flw0x0x.c (Arbeitskopie) @@ -35,7 +35,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_stm50flw0x0x(struct flashchip *flash) @@ -46,11 +46,11 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); /* Read product ID */ id1 = chip_readb(bios); @@ -72,11 +72,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, largeid2); @@ -101,7 +101,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); @@ -170,7 +170,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); wait_stm50flw0x0x(flash->virtual_memory); Index: flashrom-programmer_delay/am29f040b.c =================================================================== --- flashrom-programmer_delay/am29f040b.c (Revision 576) +++ flashrom-programmer_delay/am29f040b.c (Arbeitskopie) @@ -29,7 +29,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x30, bios + address); - sleep(2); + programmer_delay(1000000 * 2); /* wait for Toggle bit ready */ toggle_ready_jedec(bios + address); @@ -75,7 +75,7 @@ chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -95,7 +95,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Index: flashrom-programmer_delay/w39v080fa.c =================================================================== --- flashrom-programmer_delay/w39v080fa.c (Revision 576) +++ flashrom-programmer_delay/w39v080fa.c (Arbeitskopie) @@ -29,7 +29,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -39,7 +39,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -108,7 +108,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read Hardware Lock Bits */ locking = chip_readb(bios + 0xffff2); @@ -117,7 +117,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("Lockout bits:\n"); Index: flashrom-programmer_delay/flashrom.c =================================================================== --- flashrom-programmer_delay/flashrom.c (Revision 576) +++ flashrom-programmer_delay/flashrom.c (Arbeitskopie) @@ -46,6 +46,7 @@ .chip_writeb = internal_chip_writeb, .chip_writew = internal_chip_writew, .chip_writel = internal_chip_writel, + .delay = internal_delay, }, { @@ -59,6 +60,7 @@ .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, { @@ -72,6 +74,7 @@ .chip_writeb = nic3com_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -85,6 +88,7 @@ .chip_writeb = satasii_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -98,6 +102,7 @@ .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, {}, @@ -155,6 +160,11 @@ return programmer_table[programmer].chip_readl(addr); } +void programmer_delay(uint32_t usecs) +{ + programmer_table[programmer].delay(usecs); +} + void map_flash_registers(struct flashchip *flash) { size_t size = flash->total_size * 1024; Index: flashrom-programmer_delay/internal.c =================================================================== --- flashrom-programmer_delay/internal.c (Revision 576) +++ flashrom-programmer_delay/internal.c (Arbeitskopie) @@ -195,6 +195,18 @@ return *(volatile uint32_t *) addr; } +void internal_delay(int usecs) +{ + /* If the delay is >1 s, use usleep because timing does not need to + * be so precise. + */ + if (usecs > 1000000) { + usleep(usecs); + } else { + myusec_delay(usecs); + } +} + /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) { Index: flashrom-programmer_delay/ichspi.c =================================================================== --- flashrom-programmer_delay/ichspi.c (Revision 576) +++ flashrom-programmer_delay/ichspi.c (Arbeitskopie) @@ -453,7 +453,7 @@ /* wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); @@ -570,7 +570,7 @@ /*wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); Index: flashrom-programmer_delay/udelay.c =================================================================== --- flashrom-programmer_delay/udelay.c (Revision 576) +++ flashrom-programmer_delay/udelay.c (Arbeitskopie) @@ -24,10 +24,10 @@ // count to a billion. Time it. If it's < 1 sec, count to 10B, etc. unsigned long micro = 1; -void myusec_delay(int time) +void myusec_delay(int usecs) { volatile unsigned long i; - for (i = 0; i < time * micro; i++) ; + for (i = 0; i < usecs * micro; i++) ; } void myusec_calibrate_delay(void) Index: flashrom-programmer_delay/82802ab.c =================================================================== --- flashrom-programmer_delay/82802ab.c (Revision 576) +++ flashrom-programmer_delay/82802ab.c (Arbeitskopie) @@ -53,9 +53,9 @@ #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -65,7 +65,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -92,7 +92,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -124,7 +124,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); Index: flashrom-programmer_delay/mx29f002.c =================================================================== --- flashrom-programmer_delay/mx29f002.c (Revision 576) +++ flashrom-programmer_delay/mx29f002.c (Arbeitskopie) @@ -34,7 +34,7 @@ chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -55,7 +55,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(100); + programmer_delay(100); toggle_ready_jedec(bios); // while ((*bios & 0x40) != 0x40) @@ -82,7 +82,7 @@ chipaddr dst = bios; chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_29f002(flash); //*bios = 0xF0; #if 1 Index: flashrom-programmer_delay/m29f400bt.c =================================================================== --- flashrom-programmer_delay/m29f400bt.c (Revision 576) +++ flashrom-programmer_delay/m29f400bt.c (Arbeitskopie) @@ -26,7 +26,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0xA0, bios + 0xAAA); - usleep(200); + programmer_delay(200); } void write_page_m29f400bt(chipaddr bios, uint8_t *src, @@ -42,7 +42,7 @@ /* transfer data from source to destination */ chip_writeb(*src, dst); //chip_writeb(0xF0, bios); - //usleep(5); + //programmer_delay(5); toggle_ready_jedec(dst); printf ("Value in the flash at address 0x%lx = %#x, want %#x\n", @@ -61,7 +61,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0x90, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in @@ -73,7 +73,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0xF0, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -95,7 +95,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0x10, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; @@ -113,7 +113,7 @@ //chip_writeb(0x10, bios + 0xAAA); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_programmer_delay.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 18:29:40 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 18:29:40 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <4A293CA6.1050802@gmx.net> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A293CA6.1050802@gmx.net> Message-ID: <4A2947F4.4040308@gmx.net> On 05.06.2009 17:41, Carl-Daniel Hailfinger wrote: > Anyway, I just sent a patch which adds multi-byte read and write to the > external programmer interface. Can you take a look at it? > I also sent a patch to handle delays in the external programmer interface. Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Fri Jun 5 18:34:07 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 10:34:07 -0600 Subject: [coreboot] Looking for pci-e memory In-Reply-To: <200906051653.07579.christian.leber@ziti.uni-heidelberg.de> References: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> <200906051653.07579.christian.leber@ziti.uni-heidelberg.de> Message-ID: <2831fecf0906050934r3680b583j6c9b893f35f4f8ce@mail.gmail.com> On Fri, Jun 5, 2009 at 8:53 AM, Christian Leber wrote: > On Friday 05 June 2009 16:19:05 Myles Watson wrote: > > Hi Myles, > >> I'm trying to write the code to replace raminit with a >> PCI device's memory. > > why do you want to do this? Long story :) > To not have to do raminit on intel? No. The short version is that I'm doing a PhD project and I need to be able to capture memory references. Redirecting the memory references to my device is the only way to do that. Thanks, Myles From mylesgw at gmail.com Fri Jun 5 18:35:48 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 10:35:48 -0600 Subject: [coreboot] Looking for pci-e memory In-Reply-To: <4A294416.9030308@coresystems.de> References: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> <4A294416.9030308@coresystems.de> Message-ID: <2831fecf0906050935s325a62c1r155bf385bfe09511@mail.gmail.com> > Remember that, on a graphics card, the option rom usually has to initialize > a DDR controller, too. I had hoped that the DDR controller would be already initialized. Good to remember. In my case the DDR controller is in the FPGA and gets initialized at compile time. > What's this going to save? My hopes for a PhD :) Thanks, Myles From bari at onelabs.com Fri Jun 5 18:42:41 2009 From: bari at onelabs.com (bari) Date: Fri, 05 Jun 2009 11:42:41 -0500 Subject: [coreboot] Epia-m700 Patch In-Reply-To: <4A29430B.20008@coresystems.de> References: <4A293831.3070808@onelabs.com> <4A29430B.20008@coresystems.de> Message-ID: <4A294B01.4020005@onelabs.com> Stefan Reinauer wrote: > On 05.06.2009 17:22 Uhr, bari wrote: >> Here's an untested epia-m700 patch. VIA vx800 + C7. >> >> Please review and feel free to clean it up. >> >> -Bari > > Is it on purpose, that half of the ram init is done in mainboard > specific code? (DrivingClkPhaseData.c) The vx800 work is for everyone to share and enjoy now that it's free! -Bari From uwe at hermann-uwe.de Fri Jun 5 19:00:34 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 19:00:34 +0200 Subject: [coreboot] [PATCH] flashrom: Fix a bug in dummyflasher.c special case In-Reply-To: <4A2941CE.9050909@gmx.net> References: <4A2941CE.9050909@gmx.net> Message-ID: <20090605170033.GH18065@greenwood> On Fri, Jun 05, 2009 at 06:03:26PM +0200, Carl-Daniel Hailfinger wrote: > Fix a bug in dummyflasher.c special case where no type parameter is given. > > Tested. > > Signed-off-by: Carl-Daniel Hailfinger Indeed, segfaults without this patch. Acked-by: Uwe Hermann Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From svn at coreboot.org Fri Jun 5 19:04:37 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 19:04:37 +0200 Subject: [coreboot] [flashrom] r577 - trunk Message-ID: Author: hailfinger Date: 2009-06-05 19:04:37 +0200 (Fri, 05 Jun 2009) New Revision: 577 Modified: trunk/dummyflasher.c Log: Fix a bug in dummyflasher.c special case where no type parameter is given. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-06-05 13:46:17 UTC (rev 576) +++ trunk/dummyflasher.c 2009-06-05 17:04:37 UTC (rev 577) @@ -35,7 +35,7 @@ printf_debug("%s\n", __func__); /* "all" is equivalent to specifying no type. */ - if (!strcmp(dummytype, "all")) { + if (dummytype && (!strcmp(dummytype, "all"))) { free(dummytype); dummytype = NULL; } From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 19:05:05 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 19:05:05 +0200 Subject: [coreboot] [PATCH] flashrom: Fix a bug in dummyflasher.c special case In-Reply-To: <20090605170033.GH18065@greenwood> References: <4A2941CE.9050909@gmx.net> <20090605170033.GH18065@greenwood> Message-ID: <4A295041.5030509@gmx.net> On 05.06.2009 19:00, Uwe Hermann wrote: > On Fri, Jun 05, 2009 at 06:03:26PM +0200, Carl-Daniel Hailfinger wrote: > >> Fix a bug in dummyflasher.c special case where no type parameter is given. >> >> Signed-off-by: Carl-Daniel Hailfinger >> > > Acked-by: Uwe Hermann > Thanks, r577. Regards, Carl-Daniel -- http://www.hailfinger.org/ From urjaman at gmail.com Fri Jun 5 19:11:41 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 20:11:41 +0300 Subject: [coreboot] [PATCH] flashrom: Add chip_{read,write}n In-Reply-To: <4A293B66.106@gmx.net> References: <4A293B66.106@gmx.net> Message-ID: <460f92b70906051011x34e951cak5dbc7da8764737f4@mail.gmail.com> On Fri, Jun 5, 2009 at 18:36, Carl-Daniel Hailfinger wrote: > Sometimes we want to read/write more than 4 bytes of chip content at once. > Add chip_{read,write}n to the external flasher infrastructure which > read/write n bytes at once. > > Fix a few places where the code used memcpy/memcmp although that is > strictly impossible with external flashers. > Place a FIXME in the layout.c code because usage is not totally clear > and needs to be fixed to support external flashers. > > As a nice side benefit, we get a noticeable speedup for builtin flash > reading which is now a memcpy() of the full flash area instead of a > series of single-byte reads. > > Signed-off-by: Carl-Daniel Hailfinger > Acked-by: Urja Rannikko References: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> Message-ID: <13426df10906051015i4fd539e8xc46dba36a04eb2b1@mail.gmail.com> Ah, well, I want to set up all the RAM for a system to have the kind of timing that PCM FLASH has. This can't be done with any existing ram controller, but it could be done with a two-socket opteron system with an FPGA in one socket . ron From rminnich at gmail.com Fri Jun 5 19:18:58 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 5 Jun 2009 10:18:58 -0700 Subject: [coreboot] [PATCH] Use die() properly In-Reply-To: <20090605132136.GF18065@greenwood> References: <4A28FF46.8000308@gmx.net> <20090605132136.GF18065@greenwood> Message-ID: <13426df10906051018l2d216c2cke9374becc239e3b7@mail.gmail.com> On Fri, Jun 5, 2009 at 6:21 AM, Uwe Hermann wrote: > On Fri, Jun 05, 2009 at 01:19:34PM +0200, Carl-Daniel Hailfinger wrote: >> ? ? ? ? ? ? ? printk_alert("%s Cannot find smbus bus operations", dev_path(dev)); >> ? ? ? ? ? ? ? die(""); > > Can we also make die() accept variable argument numbers so we can do this? > > ?die("%s Cannot find smbus bus operations", dev_path(dev)); > > Or does this cause issues when die() is called very early (pre-RAM) or so? that's why it doesn't take variable arguments. You can not guarantee that it will always work. ron From mylesgw at gmail.com Fri Jun 5 19:21:36 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 11:21:36 -0600 Subject: [coreboot] Looking for pci-e memory In-Reply-To: <13426df10906051015i4fd539e8xc46dba36a04eb2b1@mail.gmail.com> References: <13426df10905161519y44cf0f8ch736b508e6c1c9146@mail.gmail.com> <2831fecf0906050719g5f692c47p77e0a1a966eaf079@mail.gmail.com> <13426df10906051015i4fd539e8xc46dba36a04eb2b1@mail.gmail.com> Message-ID: <2831fecf0906051021r39b3ba7et28ec9d9b04ebedd0@mail.gmail.com> On Fri, Jun 5, 2009 at 11:15 AM, ron minnich wrote: > Ah, well, I want to set up all the RAM for a system to have the kind > of timing that PCM FLASH has. This can't be done with any existing ram > controller, but it could be done with a two-socket opteron system with > an FPGA in one socket . Yes. So you want to just have an artificial delay which varies based on write/read, possibly address if you have some caching, etc. Very doable, I think. The problem I'm having right now is with unaligned writes. I was hoping that the Opteron would allocate a cache line on a miss to cacheable memory space, and therefore never write partial lines. So far I haven't gotten that to work. Reads are aligned, but partial writes are easy to generate. Am I forgetting something? TLB settings maybe? Opteron settings for allocate on write? Thanks, Myles From uwe at hermann-uwe.de Fri Jun 5 19:23:51 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 19:23:51 +0200 Subject: [coreboot] [PATCH] flashrom: Add external programmer delay functions In-Reply-To: <4A2947B9.6000909@gmx.net> References: <4A2947B9.6000909@gmx.net> Message-ID: <20090605172351.GI18065@greenwood> On Fri, Jun 05, 2009 at 06:28:41PM +0200, Carl-Daniel Hailfinger wrote: > Add external programmer delay functions so external programmers can > handle the delay on their own if needed. > > Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann ...but see below. > Index: flashrom-programmer_delay/flash.h > =================================================================== > --- flashrom-programmer_delay/flash.h (Revision 576) > +++ flashrom-programmer_delay/flash.h (Arbeitskopie) > @@ -103,6 +103,8 @@ > uint8_t (*chip_readb) (const chipaddr addr); > uint16_t (*chip_readw) (const chipaddr addr); > uint32_t (*chip_readl) (const chipaddr addr); > + > + void (*delay) (int usecs); > }; > > extern const struct programmer_entry programmer_table[]; > @@ -118,6 +120,7 @@ > uint8_t chip_readb(const chipaddr addr); > uint16_t chip_readw(const chipaddr addr); > uint32_t chip_readl(const chipaddr addr); > +void programmer_delay(uint32_t usecs); Why uint32_t here and int above? > Index: flashrom-programmer_delay/spi.c > =================================================================== > --- flashrom-programmer_delay/spi.c (Revision 576) > +++ flashrom-programmer_delay/spi.c (Arbeitskopie) > @@ -425,7 +425,7 @@ > */ > /* FIXME: We assume spi_read_status_register will never fail. */ > while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) > - sleep(1); > + programmer_delay(1000000); I'd also make this 100 * 1000 as below, easier on the eyes. > return 0; > } > > @@ -453,7 +453,7 @@ > */ > /* FIXME: We assume spi_read_status_register will never fail. */ > while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) > - sleep(1); > + programmer_delay(1000000); Ditto. > return 0; > } > > @@ -485,7 +485,7 @@ > * This usually takes 100-4000 ms, so wait in 100 ms steps. > */ > while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) > - usleep(100 * 1000); > + programmer_delay(100 * 1000); > return 0; > } > Index: flashrom-programmer_delay/am29f040b.c > =================================================================== > --- flashrom-programmer_delay/am29f040b.c (Revision 576) > +++ flashrom-programmer_delay/am29f040b.c (Arbeitskopie) > @@ -29,7 +29,7 @@ > chip_writeb(0x55, bios + 0x2AA); > chip_writeb(0x30, bios + address); > > - sleep(2); > + programmer_delay(1000000 * 2); Maybe 2 * 1000 * 1000, same format as above. > Index: flashrom-programmer_delay/internal.c > =================================================================== > --- flashrom-programmer_delay/internal.c (Revision 576) > +++ flashrom-programmer_delay/internal.c (Arbeitskopie) > @@ -195,6 +195,18 @@ > return *(volatile uint32_t *) addr; > } > > +void internal_delay(int usecs) > +{ > + /* If the delay is >1 s, use usleep because timing does not need to > + * be so precise. Hm, but why not use myusec_delay() always? Does it have drawbacks? > + */ > + if (usecs > 1000000) { > + usleep(usecs); > + } else { > + myusec_delay(usecs); > + } > +} Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From urjaman at gmail.com Fri Jun 5 19:26:34 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 20:26:34 +0300 Subject: [coreboot] [PATCH] flashrom: Add external programmer delay functions In-Reply-To: <20090605172351.GI18065@greenwood> References: <4A2947B9.6000909@gmx.net> <20090605172351.GI18065@greenwood> Message-ID: <460f92b70906051026h3e8da571la98bc41dfcbdf793@mail.gmail.com> On Fri, Jun 5, 2009 at 20:23, Uwe Hermann wrote: > On Fri, Jun 05, 2009 at 06:28:41PM +0200, Carl-Daniel Hailfinger wrote: >> Add external programmer delay functions so external programmers can >> handle the delay on their own if needed. >> >> Signed-off-by: Carl-Daniel Hailfinger > > Acked-by: Uwe Hermann > Also Acked-by: Urja Rannikko Hm, but why not use myusec_delay() always? Does it have drawbacks? Maybe the 100% CPU usage.... -- urjaman From marcj303 at gmail.com Fri Jun 5 19:36:19 2009 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 5 Jun 2009 11:36:19 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <200906051749.53385.christian.leber@ziti.uni-heidelberg.de> References: <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906041604i2179c536wdd90a769eb3f4874@mail.gmail.com> <200906051749.53385.christian.leber@ziti.uni-heidelberg.de> Message-ID: <534e5dc20906051036q4fae4c22s5c72c06a6b88a31b@mail.gmail.com> On Fri, Jun 5, 2009 at 9:49 AM, Christian Leber wrote: > On Friday 05 June 2009 01:04:56 Marc Jones wrote: > > Hi Marc > >> I think it should just be a package difference. It looks like you hit >> the same thing as Ward without the HTX card. Not sure why that changes >> things. > > Either some CPU register is set wrong or it is interpreted wrong, because a > link is found that is neither C(oherent) nor NC. > > It tries to set then PHY options and waits afterwards forever for the > completion. > > I attached 2 logs (with and without htx card) and a .c file that spills out > that stuff. > > @Ward: probably you could try with this init_cpu.c this to see if on you box > the same is happening. Thanks Christian. I'm trying to figure out why the HTX card changes things ( and remember how this works...). The INIT hang looks like errata 344/354, maybe. Marc -- http://marcjonesconsulting.com From urjaman at gmail.com Fri Jun 5 19:37:10 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Fri, 5 Jun 2009 20:37:10 +0300 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <4A293CA6.1050802@gmx.net> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A293CA6.1050802@gmx.net> Message-ID: <460f92b70906051037m75ca6724v45b31f662166cc64@mail.gmail.com> > > Looks nice. Where's the problem? Sorry if I am being dense. > Was just clarifying and checking if somebody thought that there's a problem. I'll propably get writing a real protocol spec, and then i'll have to write code for the ATmega168 to implement the device part, and then i'll do the flashrom part. Now that there's also that delay interface, flashrom in general will be pretty much ready for it. Thanks for the idea of buffering the operations. > > Regards, > Carl-Daniel > > -- > http://www.hailfinger.org/ > > -- urjaman From patrick at georgi-clan.de Fri Jun 5 19:37:26 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Fri, 05 Jun 2009 19:37:26 +0200 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS Message-ID: <4A2957D6.5080906@georgi-clan.de> Hi, as promised, here's a follow-up to my mail from 2009-05-31. The patch from back then (also reproduced here) breaks CBFS using boards, as switching to CBFS requires some more changes now. The benefit is that the normal image works again, which was broken with CBFS so far. The patches here fix the breakage for the already transitioned boards. 20090531-use-coreboot.rom-for-cbfs: Change the CBFS build process to use coreboot.rom instead of coreboot.strip, which fixes the calculation of the entry point of the normal image. (same patch as in the old mail, and Acked by myles) 20090605-3-fix-abuild-of-m2v-mx-se-with-crosscompiler: Properly use CROSS_COMPILE, so abuild uses i386-elf-gcc as compiler if it needs to. 20090605-4-move-CONFIG_CBFS-to-Options-lb: hp/dl145_g3 defined CONFIG_CBFS in the targets/* files, move to Options.lb like for every other CBFS-using board 20090605-5-fix-via-vt8454c: Fix up via/vt8454c after the 20090531 patch 20090605-6-fix-kontron-986lcd-m: Likewise for kontron/986lcd-m 20090605-7-fix-emulation-qemu-x86: Likewise for emulation/qemu-x86 20090605-8-fix-hp-dl145-g3: Likewise for hp/dl145_g3 The 20090605-[5678]-* patches give some indication on how to switch a board over to CBFS support. It's not as easy as without the 20090531 patch, but at least it works correctly then: For targets that use the src/config/*calculation.lb files, it's quite easy: 1. define FALLBACK_SIZE to ROM_IMAGE_SIZE (both normal and fallback are of that size now, that kludge can be dropped after non-CBFS is dropped) 2. drop most size definitions from the targets/*/*/Config*lb, except ROM_SIZE (the total size of the image) 3. ROM_IMAGE_SIZE must be set to the intended size of the up-to-raminit stage of coreboot (coreboot_ram is loaded from CBFS). Usually, 64kb is enough, and choosing smaller values only makes configuring the XIP range harder. For boards with coreboot_apc image (AMD stuff mostly), you also have to remove "ldscript /arch/i386/init/ldscript_apc.lb" from the mainboard's Config.lb (not shown in this patch set, as none of these boards uses it). coreboot_apc also resides in CBFS now, so this link hack in not required anymore. With this, I think CBFS has no regressions over the old style rom image layout anymore, so moving everything over to using CBFS would be a nice next step, as lots of stuff in the build system could disappear after that. Regards, Patrick -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090531-use-coreboot.rom-for-cbfs URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090605-3-fix-abuild-of-m2v-mx-se-with-crosscompiler URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090605-4-move-CONFIG_CBFS-to-Options-lb URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090605-5-fix-via-vt8454c URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090605-6-fix-kontron-986lcd-m URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090605-7-fix-emulation-qemu-x86 URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090605-8-fix-hp-dl145-g3 URL: From svn at coreboot.org Fri Jun 5 19:48:08 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 19:48:08 +0200 Subject: [coreboot] [flashrom] r578 - trunk Message-ID: Author: hailfinger Date: 2009-06-05 19:48:08 +0200 (Fri, 05 Jun 2009) New Revision: 578 Modified: trunk/82802ab.c trunk/am29f040b.c trunk/en29f002a.c trunk/flash.h trunk/flashrom.c trunk/ichspi.c trunk/internal.c trunk/it87spi.c trunk/jedec.c trunk/m29f002.c trunk/m29f400bt.c trunk/mx29f002.c trunk/sharplhf00l04.c trunk/spi.c trunk/sst28sf040.c trunk/stm50flw0x0x.c trunk/udelay.c trunk/w29ee011.c trunk/w39v040c.c trunk/w39v080fa.c trunk/wbsio_spi.c Log: Add external programmer delay functions so external programmers can handle the delay on their own if needed. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann Acked-by: Urja Rannikko Modified: trunk/82802ab.c =================================================================== --- trunk/82802ab.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/82802ab.c 2009-06-05 17:48:08 UTC (rev 578) @@ -53,9 +53,9 @@ #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -65,7 +65,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -92,7 +92,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -124,7 +124,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); Modified: trunk/am29f040b.c =================================================================== --- trunk/am29f040b.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/am29f040b.c 2009-06-05 17:48:08 UTC (rev 578) @@ -29,7 +29,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x30, bios + address); - sleep(2); + programmer_delay(2 * 1000 * 1000); /* wait for Toggle bit ready */ toggle_ready_jedec(bios + address); @@ -75,7 +75,7 @@ chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -95,7 +95,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Modified: trunk/en29f002a.c =================================================================== --- trunk/en29f002a.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/en29f002a.c 2009-06-05 17:48:08 UTC (rev 578) @@ -37,7 +37,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -70,7 +70,7 @@ chip_writeb(0x55, bios + 0xAAA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -97,7 +97,7 @@ chipaddr dst = bios; //chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_chip_jedec(flash); printf("Programming page: "); Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/flash.h 2009-06-05 17:48:08 UTC (rev 578) @@ -103,6 +103,8 @@ uint8_t (*chip_readb) (const chipaddr addr); uint16_t (*chip_readw) (const chipaddr addr); uint32_t (*chip_readl) (const chipaddr addr); + + void (*delay) (int usecs); }; extern const struct programmer_entry programmer_table[]; @@ -118,6 +120,7 @@ uint8_t chip_readb(const chipaddr addr); uint16_t chip_readw(const chipaddr addr); uint32_t chip_readl(const chipaddr addr); +void programmer_delay(int usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -590,7 +593,7 @@ #define W_49V002FA 0x32 /* udelay.c */ -void myusec_delay(int time); +void myusec_delay(int usecs); void myusec_calibrate_delay(void); /* pcidev.c */ @@ -652,6 +655,7 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void internal_delay(int usecs); void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); void fallback_chip_writew(uint16_t val, chipaddr addr); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/flashrom.c 2009-06-05 17:48:08 UTC (rev 578) @@ -46,6 +46,7 @@ .chip_writeb = internal_chip_writeb, .chip_writew = internal_chip_writew, .chip_writel = internal_chip_writel, + .delay = internal_delay, }, { @@ -59,6 +60,7 @@ .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, { @@ -72,6 +74,7 @@ .chip_writeb = nic3com_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -85,6 +88,7 @@ .chip_writeb = satasii_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -98,6 +102,7 @@ .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, {}, @@ -155,6 +160,11 @@ return programmer_table[programmer].chip_readl(addr); } +void programmer_delay(int usecs) +{ + programmer_table[programmer].delay(usecs); +} + void map_flash_registers(struct flashchip *flash) { size_t size = flash->total_size * 1024; Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/ichspi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -453,7 +453,7 @@ /* wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); @@ -570,7 +570,7 @@ /*wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/internal.c 2009-06-05 17:48:08 UTC (rev 578) @@ -195,6 +195,18 @@ return *(volatile uint32_t *) addr; } +void internal_delay(int usecs) +{ + /* If the delay is >1 s, use usleep because timing does not need to + * be so precise. + */ + if (usecs > 1000000) { + usleep(usecs); + } else { + myusec_delay(usecs); + } +} + /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) { Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/it87spi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -220,7 +220,7 @@ * This usually takes 1-10 ms, so wait in 1 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(1000); + programmer_delay(1000); return 0; } @@ -245,7 +245,7 @@ return result; spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } /* resume normal ops... */ OUTB(0x20, it8716f_flashport); Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/jedec.c 2009-06-05 17:48:08 UTC (rev 578) @@ -73,7 +73,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x20, bios + 0x5555); - usleep(200); + programmer_delay(200); } void protect_jedec(chipaddr bios) @@ -82,7 +82,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_jedec(struct flashchip *flash) @@ -110,14 +110,14 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ - myusec_delay(probe_timing_enter); + programmer_delay(probe_timing_enter); /* Read product ID */ id1 = chip_readb(bios); @@ -139,11 +139,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(probe_timing_exit); + programmer_delay(probe_timing_exit); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); if (!oddparity(id1)) @@ -179,18 +179,18 @@ { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x30, bios + page); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -202,18 +202,18 @@ { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x50, bios + block); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -227,18 +227,18 @@ /* Issue the JEDEC Chip Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x10, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); Modified: trunk/m29f002.c =================================================================== --- trunk/m29f002.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/m29f002.c 2009-06-05 17:48:08 UTC (rev 578) @@ -29,7 +29,7 @@ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; } @@ -44,7 +44,7 @@ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); /* program */ Modified: trunk/m29f400bt.c =================================================================== --- trunk/m29f400bt.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/m29f400bt.c 2009-06-05 17:48:08 UTC (rev 578) @@ -26,7 +26,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0xA0, bios + 0xAAA); - usleep(200); + programmer_delay(200); } void write_page_m29f400bt(chipaddr bios, uint8_t *src, @@ -42,7 +42,7 @@ /* transfer data from source to destination */ chip_writeb(*src, dst); //chip_writeb(0xF0, bios); - //usleep(5); + //programmer_delay(5); toggle_ready_jedec(dst); printf ("Value in the flash at address 0x%lx = %#x, want %#x\n", @@ -61,7 +61,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0x90, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in @@ -73,7 +73,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0xF0, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -95,7 +95,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0x10, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; @@ -113,7 +113,7 @@ //chip_writeb(0x10, bios + 0xAAA); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Modified: trunk/mx29f002.c =================================================================== --- trunk/mx29f002.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/mx29f002.c 2009-06-05 17:48:08 UTC (rev 578) @@ -34,7 +34,7 @@ chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -55,7 +55,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(100); + programmer_delay(100); toggle_ready_jedec(bios); // while ((*bios & 0x40) != 0x40) @@ -82,7 +82,7 @@ chipaddr dst = bios; chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_29f002(flash); //*bios = 0xF0; #if 1 Modified: trunk/sharplhf00l04.c =================================================================== --- trunk/sharplhf00l04.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/sharplhf00l04.c 2009-06-05 17:48:08 UTC (rev 578) @@ -46,9 +46,9 @@ #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -58,7 +58,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -85,7 +85,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -118,7 +118,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/spi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -425,7 +425,7 @@ */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000 * 1000); return 0; } @@ -453,7 +453,7 @@ */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000 * 1000); return 0; } @@ -485,7 +485,7 @@ * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -511,7 +511,7 @@ * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -557,7 +557,7 @@ * This usually takes 15-800 ms, so wait in 10 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(10 * 1000); + programmer_delay(10 * 1000); return 0; } @@ -690,7 +690,7 @@ spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } return 0; @@ -748,13 +748,13 @@ return result; spi_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; spi_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } spi_write_disable(); return 0; Modified: trunk/sst28sf040.c =================================================================== --- trunk/sst28sf040.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/sst28sf040.c 2009-06-05 17:48:08 UTC (rev 578) @@ -94,16 +94,16 @@ uint8_t id1, id2; chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(READ_ID, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); - myusec_delay(10); + programmer_delay(10); id2 = chip_readb(bios + 0x01); chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -121,7 +121,7 @@ chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Modified: trunk/stm50flw0x0x.c =================================================================== --- trunk/stm50flw0x0x.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/stm50flw0x0x.c 2009-06-05 17:48:08 UTC (rev 578) @@ -35,7 +35,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_stm50flw0x0x(struct flashchip *flash) @@ -46,11 +46,11 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); /* Read product ID */ id1 = chip_readb(bios); @@ -72,11 +72,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, largeid2); @@ -101,7 +101,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); @@ -170,7 +170,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); wait_stm50flw0x0x(flash->virtual_memory); Modified: trunk/udelay.c =================================================================== --- trunk/udelay.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/udelay.c 2009-06-05 17:48:08 UTC (rev 578) @@ -24,10 +24,10 @@ // count to a billion. Time it. If it's < 1 sec, count to 10B, etc. unsigned long micro = 1; -void myusec_delay(int time) +void myusec_delay(int usecs) { volatile unsigned long i; - for (i = 0; i < time * micro; i++) ; + for (i = 0; i < usecs * micro; i++) ; } void myusec_calibrate_delay(void) Modified: trunk/w29ee011.c =================================================================== --- trunk/w29ee011.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/w29ee011.c 2009-06-05 17:48:08 UTC (rev 578) @@ -38,17 +38,17 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x60, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -56,11 +56,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Modified: trunk/w39v040c.c =================================================================== --- trunk/w39v040c.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/w39v040c.c 2009-06-05 17:48:08 UTC (rev 578) @@ -26,22 +26,22 @@ uint8_t id1, id2, lock; chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 1); lock = chip_readb(bios + 0xfff2); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); if (!oddparity(id1)) Modified: trunk/w39v080fa.c =================================================================== --- trunk/w39v080fa.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/w39v080fa.c 2009-06-05 17:48:08 UTC (rev 578) @@ -29,7 +29,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -39,7 +39,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -108,7 +108,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read Hardware Lock Bits */ locking = chip_readb(bios + 0xffff2); @@ -117,7 +117,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("Lockout bits:\n"); Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/wbsio_spi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -159,7 +159,7 @@ OUTB(writearr[0], wbsio_spibase); OUTB(mode, wbsio_spibase + 1); - myusec_delay(10); + programmer_delay(10); if (!readcnt) return 0; @@ -203,7 +203,7 @@ for (pos = 0; pos < size; pos++) { spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } spi_write_disable(); return 0; From rminnich at gmail.com Fri Jun 5 19:49:02 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 5 Jun 2009 10:49:02 -0700 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS In-Reply-To: <4A2957D6.5080906@georgi-clan.de> References: <4A2957D6.5080906@georgi-clan.de> Message-ID: <13426df10906051049p38833b1fm31a3419bcfb6c4ea@mail.gmail.com> All acked. Acked-by: Ronald G. Minnich From mylesgw at gmail.com Fri Jun 5 19:54:31 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 11:54:31 -0600 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS In-Reply-To: <4A2957D6.5080906@georgi-clan.de> References: <4A2957D6.5080906@georgi-clan.de> Message-ID: <2831fecf0906051054v22a50b4clb5634ddaf3cbd0f@mail.gmail.com> > 20090605-8-fix-hp-dl145-g3: Likewise for hp/dl145_g3 This board was fallback only because CBFS didn't work for normal. Maybe now is the time to make it have a normal image again? > Index: targets/hp/dl145_g3/Config-abuild.lb > =================================================================== > --- targets/hp/dl145_g3/Config-abuild.lb.orig > +++ targets/hp/dl145_g3/Config-abuild.lb > @@ -13,8 +13,6 @@ __LOGLEVEL__ > ?option ROM_SIZE=1024*(1024-32) > ?option FALLBACK_SIZE=1024*512 I think this needs to be updated. > -option CONFIG_CBFS = 1 > - > ?romimage "fallback" > ? ? ? ?option USE_FALLBACK_IMAGE=1 > ? ? ? ?option ROM_IMAGE_SIZE=0x20000 Isn't this line supposed to be gone? Maybe we don't need a separate Config-abuild for the dl145_g3 since the problem was the ROM_IMAGE_SIZE on the build machine. Less to keep correct. Thanks, Myles From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 19:56:10 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 19:56:10 +0200 Subject: [coreboot] [PATCH] flashrom: Add external programmer delay functions In-Reply-To: <20090605172351.GI18065@greenwood> References: <4A2947B9.6000909@gmx.net> <20090605172351.GI18065@greenwood> Message-ID: <4A295C3A.9000308@gmx.net> On 05.06.2009 19:23, Uwe Hermann wrote: > On Fri, Jun 05, 2009 at 06:28:41PM +0200, Carl-Daniel Hailfinger wrote: > >> Add external programmer delay functions so external programmers can >> handle the delay on their own if needed. >> >> Signed-off-by: Carl-Daniel Hailfinger >> > > Acked-by: Uwe Hermann > > ...but see below. > Thanks for the review! >> Index: flashrom-programmer_delay/flash.h >> =================================================================== >> --- flashrom-programmer_delay/flash.h (Revision 576) >> +++ flashrom-programmer_delay/flash.h (Arbeitskopie) >> @@ -118,6 +120,7 @@ >> uint8_t chip_readb(const chipaddr addr); >> uint16_t chip_readw(const chipaddr addr); >> uint32_t chip_readl(const chipaddr addr); >> +void programmer_delay(uint32_t usecs); >> > > Why uint32_t here and int above? > Leftover from an earlier version. Should be int. >> Index: flashrom-programmer_delay/spi.c >> =================================================================== >> --- flashrom-programmer_delay/spi.c (Revision 576) >> +++ flashrom-programmer_delay/spi.c (Arbeitskopie) >> @@ -425,7 +425,7 @@ >> */ >> /* FIXME: We assume spi_read_status_register will never fail. */ >> while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) >> - sleep(1); >> + programmer_delay(1000000); >> > > I'd also make this 100 * 1000 as below, easier on the eyes. > 1000 * 1000, sure. Changed for all other calls as well. >> Index: flashrom-programmer_delay/internal.c >> =================================================================== >> --- flashrom-programmer_delay/internal.c (Revision 576) >> +++ flashrom-programmer_delay/internal.c (Arbeitskopie) >> @@ -195,6 +195,18 @@ >> return *(volatile uint32_t *) addr; >> } >> >> +void internal_delay(int usecs) >> +{ >> + /* If the delay is >1 s, use usleep because timing does not need to >> + * be so precise. >> > > Hm, but why not use myusec_delay() always? Does it have drawbacks? > Yes. myusec_delay is a busy-wait to get some precision. Hogging the CPU for more than 1 second is bad style. Committed with your suggestions in r578. Regards, Carl-Daniel -- http://www.hailfinger.org/ From uwe at hermann-uwe.de Fri Jun 5 20:07:43 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 20:07:43 +0200 Subject: [coreboot] [PATCH] flashrom: Add chip_{read,write}n In-Reply-To: <4A293B66.106@gmx.net> References: <4A293B66.106@gmx.net> Message-ID: <20090605180743.GJ18065@greenwood> On Fri, Jun 05, 2009 at 05:36:06PM +0200, Carl-Daniel Hailfinger wrote: > Sometimes we want to read/write more than 4 bytes of chip content at once. > Add chip_{read,write}n to the external flasher infrastructure which > read/write n bytes at once. > > Fix a few places where the code used memcpy/memcmp although that is > strictly impossible with external flashers. > Place a FIXME in the layout.c code because usage is not totally clear > and needs to be fixed to support external flashers. > > As a nice side benefit, we get a noticeable speedup for builtin flash > reading which is now a memcpy() of the full flash area instead of a > series of single-byte reads. > > Signed-off-by: Carl-Daniel Hailfinger Acked-by: Uwe Hermann But: - Please check the malloc() return value. - The patch needs some adaption, doesn't apply anymore to trunk. Other than that it looks ok. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From svn at coreboot.org Fri Jun 5 20:32:08 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 20:32:08 +0200 Subject: [coreboot] [flashrom] r579 - trunk Message-ID: Author: hailfinger Date: 2009-06-05 20:32:07 +0200 (Fri, 05 Jun 2009) New Revision: 579 Modified: trunk/82802ab.c trunk/dummyflasher.c trunk/flash.h trunk/flashrom.c trunk/internal.c trunk/layout.c trunk/stm50flw0x0x.c Log: Sometimes we want to read/write more than 4 bytes of chip content at once. Add chip_{read,write}n to the external flasher infrastructure which read/write n bytes at once. Fix a few places where the code used memcpy/memcmp although that is strictly impossible with external flashers. Place a FIXME in the layout.c code because usage is not totally clear and needs to be fixed to support external flashers. As a nice side benefit, we get a noticeable speedup for builtin flash reading which is now a memcpy() of the full flash area instead of a series of single-byte reads. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Urja Rannikko Acked-by: Uwe Hermann Modified: trunk/82802ab.c =================================================================== --- trunk/82802ab.c 2009-06-05 17:48:08 UTC (rev 578) +++ trunk/82802ab.c 2009-06-05 18:32:07 UTC (rev 579) @@ -27,6 +27,7 @@ */ #include +#include #include "flash.h" // I need that Berkeley bit-map printer @@ -172,7 +173,12 @@ int total_size = flash->total_size * 1024; int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; + uint8_t *tmpbuf = malloc(page_size); + if (!tmpbuf) { + printf("Could not allocate memory!\n"); + exit(1); + } printf("Programming page: \n"); for (i = 0; i < total_size / page_size; i++) { printf @@ -186,8 +192,8 @@ * or not erased and rewritten; their data is retained also in * sudden power off situations */ - if (!memcmp((void *)(buf + i * page_size), - (void *)(bios + i * page_size), page_size)) { + chip_readn(tmpbuf, bios + i * page_size, page_size); + if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { printf("SKIPPED\n"); continue; } @@ -199,6 +205,7 @@ } printf("\n"); protect_jedec(bios); + free(tmpbuf); return 0; } Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-06-05 17:48:08 UTC (rev 578) +++ trunk/dummyflasher.c 2009-06-05 18:32:07 UTC (rev 579) @@ -103,6 +103,18 @@ printf_debug("%s: addr=0x%lx, val=0x%08x\n", __func__, addr, val); } +void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len) +{ + size_t i; + printf_debug("%s: addr=0x%lx, len=0x%08lx, writing data (hex):", + __func__, addr, (unsigned long)len); + for (i = 0; i < len; i++) { + if ((i % 16) == 0) + printf_debug("\n"); + printf_debug("%02x ", buf[i]) + } +} + uint8_t dummy_chip_readb(const chipaddr addr) { printf_debug("%s: addr=0x%lx, returning 0xff\n", __func__, addr); @@ -121,6 +133,14 @@ return 0xffffffff; } +void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) +{ + printf_debug("%s: addr=0x%lx, len=0x%lx, returning array of 0xff\n", + __func__, addr, (unsigned long)len); + memset(buf, 0xff, len); + return; +} + int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-05 17:48:08 UTC (rev 578) +++ trunk/flash.h 2009-06-05 18:32:07 UTC (rev 579) @@ -100,10 +100,11 @@ void (*chip_writeb) (uint8_t val, chipaddr addr); void (*chip_writew) (uint16_t val, chipaddr addr); void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); uint8_t (*chip_readb) (const chipaddr addr); uint16_t (*chip_readw) (const chipaddr addr); uint32_t (*chip_readl) (const chipaddr addr); - + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); void (*delay) (int usecs); }; @@ -117,9 +118,11 @@ void chip_writeb(uint8_t val, chipaddr addr); void chip_writew(uint16_t val, chipaddr addr); void chip_writel(uint32_t val, chipaddr addr); +void chip_writen(uint8_t *buf, chipaddr addr, size_t len); uint8_t chip_readb(const chipaddr addr); uint16_t chip_readw(const chipaddr addr); uint32_t chip_readl(const chipaddr addr); +void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -649,6 +652,7 @@ uint8_t internal_chip_readb(const chipaddr addr); uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); +void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -660,8 +664,10 @@ void fallback_unmap(void *virt_addr, size_t len); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); +void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); +void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #if defined(__FreeBSD__) || defined(__DragonFly__) extern int io_fd; #endif @@ -675,9 +681,11 @@ void dummy_chip_writeb(uint8_t val, chipaddr addr); void dummy_chip_writew(uint16_t val, chipaddr addr); void dummy_chip_writel(uint32_t val, chipaddr addr); +void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len); uint8_t dummy_chip_readb(const chipaddr addr); uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); +void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-05 17:48:08 UTC (rev 578) +++ trunk/flashrom.c 2009-06-05 18:32:07 UTC (rev 579) @@ -43,9 +43,11 @@ .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, .chip_readl = internal_chip_readl, + .chip_readn = internal_chip_readn, .chip_writeb = internal_chip_writeb, .chip_writew = internal_chip_writew, .chip_writel = internal_chip_writel, + .chip_writen = fallback_chip_writen, .delay = internal_delay, }, @@ -57,9 +59,11 @@ .chip_readb = dummy_chip_readb, .chip_readw = dummy_chip_readw, .chip_readl = dummy_chip_readl, + .chip_readn = dummy_chip_readn, .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .chip_writen = dummy_chip_writen, .delay = internal_delay, }, @@ -71,9 +75,11 @@ .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, .chip_writeb = nic3com_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, .delay = internal_delay, }, @@ -85,9 +91,11 @@ .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, .chip_writeb = satasii_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, .delay = internal_delay, }, @@ -97,11 +105,13 @@ .map_flash_region = dummy_map, .unmap_flash_region = dummy_unmap, .chip_readb = dummy_chip_readb, - .chip_readw = dummy_chip_readw, - .chip_readl = dummy_chip_readl, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, .chip_writeb = dummy_chip_writeb, - .chip_writew = dummy_chip_writew, - .chip_writel = dummy_chip_writel, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, .delay = internal_delay, }, @@ -145,6 +155,11 @@ programmer_table[programmer].chip_writel(val, addr); } +void chip_writen(uint8_t *buf, chipaddr addr, size_t len) +{ + programmer_table[programmer].chip_writen(buf, addr, len); +} + uint8_t chip_readb(const chipaddr addr) { return programmer_table[programmer].chip_readb(addr); @@ -160,6 +175,12 @@ return programmer_table[programmer].chip_readl(addr); } +void chip_readn(uint8_t *buf, chipaddr addr, size_t len) +{ + programmer_table[programmer].chip_readn(buf, addr, len); + return; +} + void programmer_delay(int usecs) { programmer_table[programmer].delay(usecs); @@ -174,12 +195,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf) { - int i; - - /* We could do a memcpy as optimization if the flash is onboard */ - //memcpy(buf, (const char *)flash->virtual_memory, flash->total_size * 1024); - for (i = 0; i < flash->total_size * 1024; i++) - buf[i] = chip_readb(flash->virtual_memory + i); + chip_readn(buf, flash->virtual_memory, flash->total_size * 1024); return 0; } @@ -784,14 +800,10 @@ */ // //////////////////////////////////////////////////////////// - /* FIXME: This memcpy will not work for SPI nor external flashers. - * Convert to chip_readb. - */ if (exclude_end_position - exclude_start_position > 0) - memcpy(buf + exclude_start_position, - (const char *)flash->virtual_memory + - exclude_start_position, - exclude_end_position - exclude_start_position); + chip_readn(buf + exclude_start_position, + flash->virtual_memory + exclude_start_position, + exclude_end_position - exclude_start_position); exclude_start_page = exclude_start_position / flash->page_size; if ((exclude_start_position % flash->page_size) != 0) { @@ -802,6 +814,7 @@ // This should be moved into each flash part's code to do it // cleanly. This does the job. + /* FIXME: Adapt to the external flasher infrastructure. */ handle_romentries(buf, (uint8_t *) flash->virtual_memory); // //////////////////////////////////////////////////////////// Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-06-05 17:48:08 UTC (rev 578) +++ trunk/internal.c 2009-06-05 18:32:07 UTC (rev 579) @@ -165,6 +165,12 @@ return mmio_readl((void *) addr); } +void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) +{ + memcpy(buf, (void *)addr, len); + return; +} + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; @@ -249,3 +255,19 @@ val |= chip_readw(addr + 2) << 16; return val; } + +void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len) +{ + size_t i; + for (i = 0; i < len; i++) + chip_writeb(buf[i], addr + i); + return; +} + +void fallback_chip_readn(uint8_t *buf, chipaddr addr, size_t len) +{ + size_t i; + for (i = 0; i < len; i++) + buf[i] = chip_readb(addr + i); + return; +} Modified: trunk/layout.c =================================================================== --- trunk/layout.c 2009-06-05 17:48:08 UTC (rev 578) +++ trunk/layout.c 2009-06-05 18:32:07 UTC (rev 579) @@ -220,6 +220,7 @@ if (rom_entries[i].included) continue; + /* FIXME: Adapt to the external flasher infrastructure. */ memcpy(buffer + rom_entries[i].start, content + rom_entries[i].start, rom_entries[i].end - rom_entries[i].start); Modified: trunk/stm50flw0x0x.c =================================================================== --- trunk/stm50flw0x0x.c 2009-06-05 17:48:08 UTC (rev 578) +++ trunk/stm50flw0x0x.c 2009-06-05 18:32:07 UTC (rev 579) @@ -27,6 +27,7 @@ */ #include +#include #include "flash.h" void protect_stm50flw0x0x(chipaddr bios) @@ -255,7 +256,12 @@ int total_size = flash->total_size * 1024; int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; + uint8_t *tmpbuf = malloc(page_size); + if (!tmpbuf) { + printf("Could not allocate memory!\n"); + exit(1); + } printf("Programming page: \n"); for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { printf @@ -269,8 +275,8 @@ * are not erased and rewritten; data is retained also * in sudden power off situations */ - if (!memcmp((void *)(buf + i * page_size), - (void *)(bios + i * page_size), page_size)) { + chip_readn(tmpbuf, bios + i * page_size, page_size); + if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { printf("SKIPPED\n"); continue; } @@ -284,6 +290,7 @@ } printf("\n"); protect_stm50flw0x0x(bios); + free(tmpbuf); return rc; } From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 20:33:40 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 20:33:40 +0200 Subject: [coreboot] [PATCH] flashrom: Add chip_{read,write}n In-Reply-To: <20090605180743.GJ18065@greenwood> References: <4A293B66.106@gmx.net> <20090605180743.GJ18065@greenwood> Message-ID: <4A296504.9030204@gmx.net> On 05.06.2009 20:07, Uwe Hermann wrote: > On Fri, Jun 05, 2009 at 05:36:06PM +0200, Carl-Daniel Hailfinger wrote: > >> Sometimes we want to read/write more than 4 bytes of chip content at once. >> Add chip_{read,write}n to the external flasher infrastructure which >> read/write n bytes at once. >> >> Signed-off-by: Carl-Daniel Hailfinger >> > > Acked-by: Uwe Hermann > Thanks, committed in r579 with malloc() fixed. Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Fri Jun 5 20:34:37 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 12:34:37 -0600 Subject: [coreboot] svn blame -x-w Message-ID: <2831fecf0906051134u30d6d98ag5c7708d4db8f082e@mail.gmail.com> svn has a cool feature that I just ran into. It allows you to ignore white spaces when you're looking at blame. The first reason I think that is cool is because it would be nice to clean up the white space in many of our files. One reason not to do that is to preserve the blame. As long as developers know about this it isn't so much of an issue. The second reason I think it's cool is because it gives me an easy way to check if a white space patch really is just white space changes. svn blame -x-w svn blame -x-b It could have saved me a couple of times :) Thanks, Myles From svn at coreboot.org Fri Jun 5 20:50:29 2009 From: svn at coreboot.org (coreboot) Date: Fri, 05 Jun 2009 18:50:29 -0000 Subject: [coreboot] #140: flashrom: Consistently use stderr for error printing Message-ID: <039.2af1391403b8703f2bc3e3ff45d2b682@coreboot.org> #140: flashrom: Consistently use stderr for error printing ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ We're not very consistent with error printing in flashrom. Many errors go to stdout instead of stderr. We should fix that by using fprintf(stderr, "Foo") where needed. -- Ticket URL: coreboot From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 20:58:35 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 20:58:35 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906051037m75ca6724v45b31f662166cc64@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A293CA6.1050802@gmx.net> <460f92b70906051037m75ca6724v45b31f662166cc64@mail.gmail.com> Message-ID: <4A296ADB.1010109@gmx.net> On 05.06.2009 19:37, Urja Rannikko wrote: > Was just clarifying and checking if somebody thought that there's a problem. > I'll propably get writing a real protocol spec, and then i'll have to > write code for the ATmega168 to implement the device part, and then > i'll do the flashrom part. Neat. > Now that there's also that delay interface, > flashrom in general will be pretty much ready for it. Thanks for the > idea of buffering the operations. > You're welcome. I'm very interested in the buffer management code. Once you have an early prototype, please send it. The earlier the prototype is, the easier it is to change the design where you see problems. If you need anything else from flashrom, please speak up. Regards, Carl-Daniel -- http://www.hailfinger.org/ From uwe at hermann-uwe.de Fri Jun 5 21:00:03 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 21:00:03 +0200 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS In-Reply-To: <4A2957D6.5080906@georgi-clan.de> References: <4A2957D6.5080906@georgi-clan.de> Message-ID: <20090605190003.GK18065@greenwood> On Fri, Jun 05, 2009 at 07:37:26PM +0200, Patrick Georgi wrote: > The 20090605-[5678]-* patches give some indication on how to switch a > board over to CBFS support. It's not as easy as without the 20090531 > patch, but at least it works correctly then: > > For targets that use the src/config/*calculation.lb files, it's quite easy: > 1. define FALLBACK_SIZE to ROM_IMAGE_SIZE (both normal and fallback are > of that size now, that kludge can be dropped after non-CBFS is dropped) > > 2. drop most size definitions from the targets/*/*/Config*lb, except > ROM_SIZE (the total size of the image) > > 3. ROM_IMAGE_SIZE must be set to the intended size of the up-to-raminit > stage of coreboot (coreboot_ram is loaded from CBFS). > Usually, 64kb is enough, and choosing smaller values only makes > configuring the XIP range harder. > > For boards with coreboot_apc image (AMD stuff mostly), you also have to > remove "ldscript /arch/i386/init/ldscript_apc.lb" from the mainboard's > Config.lb (not shown in this patch set, as none of these boards uses > it). coreboot_apc also resides in CBFS now, so this link hack in not > required anymore. > > With this, I think CBFS has no regressions over the old style rom image > layout anymore, so moving everything over to using CBFS would be a nice > next step, as lots of stuff in the build system could disappear after > that. Most of the text above should make a good start for a "How to move a board to CBFS" page in the wiki. > Index: targets/asus/m2v-mx_se/Config-abuild.lb > =================================================================== > --- targets/asus/m2v-mx_se/Config-abuild.lb (revision 4340) > +++ targets/asus/m2v-mx_se/Config-abuild.lb (working copy) > @@ -20,6 +20,10 @@ > target asus_m2v-mx_se > mainboard asus/m2v-mx_se > > +option CC="CROSSCC" > +option CROSS_COMPILE="CROSS_PREFIX" > +option HOSTCC="CROSS_HOSTCC" Shouldn't this be option CC="$(CROSSCC)" option CROSS_COMPILE="$(CROSS_PREFIX)" option HOSTCC="$(CROSS_HOSTCC)" Does the syntax without braces work? I confirmed on hardware (the kontron board), that these patches do indeed build/work fine _and_ fix the currently broken kontron board build. Without the patches you get 0xff on POST cards, and no serial output at all. Acked-by: Uwe Hermann but please take Myles' comments into account. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 21:02:02 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 21:02:02 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050808v7714b892geee102519b712b10@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A2931F0.4050507@gmx.net> <460f92b70906050808v7714b892geee102519b712b10@mail.gmail.com> Message-ID: <4A296BAA.6050409@gmx.net> On 05.06.2009 17:08, Urja Rannikko wrote: > On Fri, Jun 5, 2009 at 17:55, Carl-Daniel Hailfinger wrote: > >> Which serial protocol are we talking about? >> > > The serial protocol between the (yet not existing) in-flashrom > external serial programmer driver (summoned with eg. "flashrom -p > serialprog=/dev/ttyS0,115200") and the ATmega168 (i originally had an > mega88) that goes on the RS-232 cable. Ah OK. The meaning of "serial protocol" was not clear to me. I thought you meant a SPI variant. > The point being that i want to > be able to change the ATmega168 to the next cool programmer somebody > creates without changing the flashrom part of the software, so i want > to make a device-independent protocol. > That would be neat. > I actually have an ATmega328 with an ethernet interface (ENC28J60), so > i thought that the next programmer i make might be ethernet based > instead of serial, but with the same protocol. > The turnaround times are probably similar to serial for single commands, but I am pretty excited by this prospect. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 21:12:50 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 21:12:50 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> Message-ID: <4A296E32.6060708@gmx.net> On 05.06.2009 16:43, Urja Rannikko wrote: > On Fri, Jun 5, 2009 at 17:18, Carl-Daniel Hailfinger wrote: > > > The point is here that the buffer management isnt visible outside of > the programmer driver. Eg. when the programmers chip_writeb is called, > it will check if the address is previous_address+1 and then send the > combine. > > >> Some chips have delays of more than 60 seconds (yes, not ms or us). >> 32bit udelay is the way to go forward. If your programmer can't handle a >> given delay length, the driver should either split it into multiple >> delays upon downloading it to the device or reject enqueuing such a delay. >> >> > You mean delays or timeouts? Usually, short delays are indeed timing-critical delays whereas longer delays are simple timeouts. >> Please make sure that the flashrom buffer format has no dependencies on >> the programmer buffer format. Since hardware is more difficult to change >> than software, we definitely want to keep the flashrom buffer design >> changeable without breaking hardware. 16-bit vs. 32-bit delays could be >> one such difference. >> >> > The point in this was that there would be no buffer on flashrom's side > - only on the device memory - although that buffer would be handled by > the in-flashrom external programmer driver. I did consider skipping > that write-combining so that the device would compress the stream, but > then i thought that when using real serial, that would slow down > writing manyfold to pass all the addresses to the device (AVR). > OK, that works as well. My idea was to have a buffer on the flashrom side which can then be compacted or optimized and translated by the programmer driver before sending it off to the device. Such a buffer inside flashrom is optional, though. >> What you want is an explicit execute_buffer() function. Writes and >> delays don't return anything by default. The programmer driver decides >> when to issue execute_buffer() > > There will be execute buffer command on the AVR, but if (eg.) the AVR > (for any reason) cannot process serial data as fast as it can receive > serial data to it's serial buffer, then sending more bytes of commands > than it's serial buffer to it could cause it to lose data. Eg. you > need to be able to ask it that it has processed all the commands > given. > Yes, for that you need flow control. For example, you you have the programmer return the amount of bytes free in the buffer after each command stream you send to the device. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 21:17:22 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 21:17:22 +0200 Subject: [coreboot] [PATCH] flashrom: Refactor SPI reads In-Reply-To: <4A2461FB.7040307@gmx.net> References: <4A2461FB.7040307@gmx.net> Message-ID: <4A296F42.1090500@gmx.net> On 02.06.2009 01:19, Carl-Daniel Hailfinger wrote: > Every SPI host controller implemented its own way to read flash chips. > This was partly due to a design problem in the abstraction layer. > > There should be exactly two different functions for reading SPI chips: > - memory mapped reads > - SPI command reads. > > Each of them should be contained in a separate function, optionally > taking parameters where needed. > > This patch solves the problems mentioned above, shortens the code and > makes the code logic a lot more obvious. > > Since open-coding the min() function leads to errors, include it in this > patch as well. > > Signed-off-by: Carl-Daniel Hailfinger > Ron pointed out that I should not only explain what a patch does, but also why we need it. Once this patch is merged, we get partial read support practically for free. Regards, Carl-Daniel -- http://www.hailfinger.org/ From uwe at hermann-uwe.de Fri Jun 5 21:17:39 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Fri, 5 Jun 2009 21:17:39 +0200 Subject: [coreboot] [PATCH]es: Fixes for AMD Fam10h Errata In-Reply-To: <200906051710.23113.patrick@georgi-clan.de> References: <200906051710.23113.patrick@georgi-clan.de> Message-ID: <20090605191739.GL18065@greenwood> On Fri, Jun 05, 2009 at 05:10:22PM +0200, Patrick Georgi wrote: > Hi, > > attached patches implement two errata fixes. Please also fix the coding style / whitespace when committing, some of the added code parts don't use TABs for indentation, for example. Haven't looked at the datasheets or tested the code on hardware, and the code looks non-trivial, so I don't feel confident to ack right now. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 21:28:12 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 21:28:12 +0200 Subject: [coreboot] [PATCH] flashrom: Make packagers happy In-Reply-To: <4A2142EC.2060205@gmx.net> References: <4A0B7FD6.8060204@gmx.net> <20090514022352.14901.qmail@stuge.se> <4A0BC7D5.5040904@gmx.net> <4A1B35C4.700@gmx.net> <20090528043413.6225.qmail@stuge.se> <4A1FE097.6060909@gmx.net> <20090529133033.412.qmail@stuge.se> <4A1FE7DC.1090807@gmx.net> <20090529141217.21018.qmail@stuge.se> <4A1FF0A0.4030201@gmx.net> <20090529145106.6856.qmail@stuge.se> <4A2142EC.2060205@gmx.net> Message-ID: <4A2971CC.6090602@gmx.net> On 30.05.2009 16:30, Carl-Daniel Hailfinger wrote: > Two new targets: > make export > make tarball > Both preserve svn revisions and the exported tree does not depend on > subversion in any way or shape. > > Signed-off-by: Carl-Daniel Hailfinger > We need this for five reasons: 1. Packagers currently have to patch flashrom source to compile it on systems without subversion. We should make it easier for them. 2. Snapshot tarballs currently have a .svn 1.5 directory included but this will cause errors for users with older svn 1.4. Not requiring subversion for snapshot compilation is best. 3. Since packagers seldom the svn revision in their fixup patches, some packages out there have incorrect or no revision, only major version numbers. 4. Releasing a new version of flashrom needs too many changes to the makefile which have to be reverted instantly after the release. That is unnecessary churn. 5. Making a release is easy with the change. Update the major version, then run "make tarball". Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 21:31:44 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 21:31:44 +0200 Subject: [coreboot] [dbm690t] The new acpi table doesn't seem to be correct. In-Reply-To: <4A27BFFF.10405@georgi-clan.de> References: <4A093DA8.1090701@assembler.cz> <4A27346A.7050109@gmx.net> <4A2770C5.3010104@georgi-clan.de> <4A279AD2.3080008@gmx.net> <4A27BFFF.10405@georgi-clan.de> Message-ID: <4A2972A0.6010905@gmx.net> On 04.06.2009 14:37, Patrick Georgi wrote: > Am 04.06.2009 11:58, schrieb Carl-Daniel Hailfinger: >> I'm running an old version of FILO. Could you please take a look at the >> amd/dbm690t target and tell me what I have to enable there >> (HAVE_LOW_TABLES etc.) to have things work? I can probably get access to >> the hardware later today. >> > It might be that your old FILO has no idea of the (relatively new) > forwarding pointer field in the cbtable, so it doesn't find all the data. Thanks, I'll retry with a new FILO once I have access to the hardware again. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 21:51:53 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 21:51:53 +0200 Subject: [coreboot] [PATCH] K8: Improve RAM init debug messages In-Reply-To: <2831fecf0906050809k70fe42cj13fe2e9b56c76337@mail.gmail.com> References: <4A28F6D4.7070608@gmx.net> <4A290516.3050701@coresystems.de> <4A291F03.1040001@gmx.net> <2831fecf0906050809k70fe42cj13fe2e9b56c76337@mail.gmail.com> Message-ID: <4A297759.1090208@gmx.net> On 05.06.2009 17:09, Myles Watson wrote: >>> I'm not sure it gets any easier to understand or less cryptic by calling >>> the amount of RAM end of RAM and printing it twice? >>> >>> >> Actually, it's the end of RAM. On my 4 GB machine, tom_k is 0x00500000 >> which is 5*1024*1024. The hole starts at 3 GB in that configuration. >> However, printing it twice serves no purpose. I'll fix and resend. >> Turns out it once prints the unadjusted RAM end and once the adjusted RAM end, so killing off either of the prinks is not advisable. > I think it makes it easier to review patches like this (that only > change debugging output) if you include before and after log snippets. > Old messages for my machine with 5 GB: RAM: 0x00400000 kB Ram3 [...] Initializing memory: done RAM: 0x00500000 kB New messages: RAM end at 0x00400000 kB, hole starts at 0x00000000 kB Adjusting lower RAM end Lower RAM end at 0x003f0000 kB Ram3 [...] Initializing memory: done Handling memory hole at 0x00300000 (default) RAM end at 0x00500000 kB, hole starts at 0x00300000 kB Handling memory mapped above 4 GB Upper RAM end at 0x00500000 kB Correcting memory amount mapped below 4 GB Adjusting lower RAM end Lower RAM end at 0x00300000 kB I hope this helps understand my patch better. Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Fri Jun 5 22:06:05 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 14:06:05 -0600 Subject: [coreboot] [PATCH] K8: Improve RAM init debug messages In-Reply-To: <4A297759.1090208@gmx.net> References: <4A28F6D4.7070608@gmx.net> <4A290516.3050701@coresystems.de> <4A291F03.1040001@gmx.net> <2831fecf0906050809k70fe42cj13fe2e9b56c76337@mail.gmail.com> <4A297759.1090208@gmx.net> Message-ID: > Old messages for my machine with 5 GB: > RAM: 0x00400000 kB > Ram3 > [...] > Initializing memory: done > RAM: 0x00500000 kB > > New messages: > RAM end at 0x00400000 kB, hole starts at 0x00000000 kB I liked this one better before. Here it really means there is 4 GB of RAM. The "hole at 0x0" part is not helpful. > Handling memory hole at 0x00300000 (default) > RAM end at 0x00500000 kB, hole starts at 0x00300000 kB Here the new message makes sense. Do we need to print out the hole start again? > I hope this helps understand my patch better. Yes. There's nothing like the real output for succinctness. Acked-by: Myles Watson Thanks, Myles From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 22:26:41 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 22:26:41 +0200 Subject: [coreboot] [PATCH] flashrom: Add all Eon EN25* SPI chips Message-ID: <4A297F81.2000306@gmx.net> Add all Eon EN25* SPI chips. Some IDs were already in flash.h. EN25B05 EN25B10 EN25B20 EN25B40 EN25B80 EN25B16 EN25B32 EN25B64 EN25F40 EN25F80 EN25F16 EN25P* are supported as well, but they seem to be identical to EN25B. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-eon_en25f/flash.h =================================================================== --- flashrom-eon_en25f/flash.h (Revision 579) +++ flashrom-eon_en25f/flash.h (Arbeitskopie) @@ -360,6 +360,10 @@ #define EN_25B80 0x2014 #define EN_25B16 0x2015 #define EN_25B32 0x2016 +#define EN_25B64 0x2017 +#define EN_25F40 0x3113 +#define EN_25F80 0x3114 +#define EN_25F16 0x3115 #define EN_29F512 0x7F21 #define EN_29F010 0x7F20 #define EN_29F040A 0x7F04 Index: flashrom-eon_en25f/flashchips.c =================================================================== --- flashrom-eon_en25f/flashchips.c (Revision 579) +++ flashrom-eon_en25f/flashchips.c (Arbeitskopie) @@ -777,6 +777,182 @@ }, { + .vendor = "Eon", + .name = "EN25B05", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B05, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B10", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B10, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B20", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B20, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B40", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B40, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B80", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B80, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B32", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B32, + .total_size = 4096, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B64", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B64, + .total_size = 8192, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25F40", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25F40, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25F80", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25F80, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25F16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25F16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "EON", .name = "EN29F002(A)(N)B", .bustype = CHIP_BUSTYPE_PARALLEL, -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_eon_en25f.diff URL: From stepan at coresystems.de Fri Jun 5 22:30:32 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 05 Jun 2009 22:30:32 +0200 Subject: [coreboot] [ANNOUNCE] SerialICE - QEMU based x86 firmware debugger Message-ID: <4A298068.6080206@coresystems.de> Dear x86 hardware and low-level software developers and enthusiasts! coresystems GmbH is proud to release the first version of our "Integrated Circuit Emulator over Serial", short SerialICE. This piece of software consists of two parts: - a serial console "rom shell" compiled with romcc, with minimal footprint. (Due to romcc the image is still 128k because it did not fit in 64k but this can be optimized later) - a patch to Qemu 0.10.4, which adds a new "SerialICE" machine. Short description: SerialICE is a BIOS/Firmware debugging tool. It allows you to run and observe BIOS images (such as coreboot?: http://www.coreboot.org/) written for real hardware in Qemu (http://www.nongnu.org/qemu) for debugging purposes. Thanks to Qemu's compelling feature set, it's also possible to debug this BIOS code with GNU GDB. SerialICE can be downloaded from http://www.coresystems.de/download/SerialICE-1.0.tar.bz2 With "qemu -m serialice -serialice /dev/ttyS0 -L path-to-your-bios.bin-dir -hda /dev/zero" you can run an arbitrary BIOS binary written for your target hardware in Qemu, thus logging all IO and memory accesses. Those operations will additionally be transmitted to the target system's shell and are executed there, while their results are submitted back to Qemu. Operations sent to the target: - memory reads/writes (some of them) - IO reads/writes - MSR reads/writes - CPUID calls (the bios code path might rely on this) Note: The code is very experimental and still buggy, but it was already useful in some debugging scenarios we had and was able to reveil information that would normally only be available with a hardware debugger of the price of a new car. Don't expect SerialICE to completely replace a ICE/JTAG/ITP device, but it might just work for your case, as it did for us. The code needs minimal board/chipset specific setup in order to have serial console operational for communication with Qemu. See mainboard/* for an example. This release contains demo code for two mainboards with Intel? CPUs. Also, some hardware accesses have to be caught in the Qemu code (hw/serialice.c) in order to prevent the system from locking up (ie. by disabling the serial console). Known issues: - The code is ugly, and the Qemu part is light years from a state where integration would be possible. - infrastructure for compiling with gcc + xmmstack is there, but it still fails with some odd assembler errors. This should push the SerialICE rom shell clearly below 64k again. - microcode updates from within emulated ROM code will fail. - some rarely used calls of cpuid will not give the correct information (those using two registers for input) Special thanks go to * Alex Graf for listening to my odd ideas while embedded world and supporting this project from early on. * Paul Brook for helping me find the last bug that prevented surviving all of RAM initialization on one board. * Patrick Georgi for Development and Testing. * Ron Minnich for advice and encouragement. * Eric Biederman for romcc Comments and patches are of course very welcome! Best regards, Stefan Reinauer -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From svn at coreboot.org Fri Jun 5 22:37:36 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 22:37:36 +0200 Subject: [coreboot] [v2] r4341 - trunk/coreboot-v2/src/northbridge/amd/amdk8 Message-ID: Author: hailfinger Date: 2009-06-05 22:37:35 +0200 (Fri, 05 Jun 2009) New Revision: 4341 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c Log: K8 RAM init debug messages are pretty short and sometimes cryptic. Make them a bit more verbose and hopefully more understandable. Old messages for my machine with 5 GB: RAM: 0x00400000 kB Ram3 [...] Initializing memory: done RAM: 0x00500000 kB New messages: RAM end at 0x00400000 kB Adjusting lower RAM end Lower RAM end at 0x003f0000 kB Ram3 [...] Initializing memory: done Handling memory hole at 0x00300000 (default) RAM end at 0x00500000 kB Handling memory mapped above 4 GB Upper RAM end at 0x00500000 kB Correcting memory amount mapped below 4 GB Adjusting lower RAM end Lower RAM end at 0x00300000 kB Signed-off-by: Carl-Daniel Hailfinger Acked-by: Myles Watson Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-06-05 11:41:51 UTC (rev 4340) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-06-05 20:37:35 UTC (rev 4341) @@ -850,14 +850,17 @@ } /* Report the amount of memory. */ - printk_spew("RAM: 0x%08x kB\n", tom_k); + printk_debug("RAM end at 0x%08x kB\n", tom_k); /* Now set top of memory */ msr_t msr; if (tom_k > (4*1024*1024)) { + printk_raminit("Handling memory mapped above 4 GB\n"); + printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); + printk_raminit("Correcting memory amount mapped below 4 GB\n"); } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 @@ -870,7 +873,9 @@ } else #endif tom_k = 0x3f0000; + printk_raminit("Adjusting lower RAM end\n"); } + printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM, msr); @@ -2167,6 +2172,7 @@ hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), @@ -2191,6 +2197,7 @@ basek_pri = base_k; } + printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* Find node number that needs the memory hole configured */ for (i=0; i (4*1024*1024)) { + printk_raminit("Handling memory mapped above 4 GB\n"); + printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); + printk_raminit("Correcting memory amount mapped below 4 GB\n"); } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 @@ -1069,7 +1072,9 @@ } else #endif tom_k = 0x3f0000; + printk_raminit("Adjusting lower RAM end\n"); } + printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM, msr); @@ -2938,6 +2943,7 @@ hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ @@ -2958,6 +2964,7 @@ } basek_pri = base_k; } + printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* find node index that need do set hole */ for (i=0; i < controllers; i++) { From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 22:37:44 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 22:37:44 +0200 Subject: [coreboot] [PATCH] K8: Improve RAM init debug messages In-Reply-To: References: <4A28F6D4.7070608@gmx.net> <4A290516.3050701@coresystems.de> <4A291F03.1040001@gmx.net> <2831fecf0906050809k70fe42cj13fe2e9b56c76337@mail.gmail.com> <4A297759.1090208@gmx.net> Message-ID: <4A298218.1050702@gmx.net> On 05.06.2009 22:06, Myles Watson wrote: >> Old messages for my machine with 5 GB: >> RAM: 0x00400000 kB >> Ram3 >> [...] >> Initializing memory: done >> RAM: 0x00500000 kB >> >> New messages: >> RAM end at 0x00400000 kB, hole starts at 0x00000000 kB >> > I liked this one better before. Here it really means there is 4 GB of RAM. > The "hole at 0x0" part is not helpful. > Since we already print hole location in a separate function, I'll kill it here. >> Handling memory hole at 0x00300000 (default) >> RAM end at 0x00500000 kB, hole starts at 0x00300000 kB >> > Here the new message makes sense. Do we need to print out the hole start > again? > Good question. The "Handling memory hole" message is in a separate function. I'll kill the "hole starts at" message. >> I hope this helps understand my patch better. >> > Yes. There's nothing like the real output for succinctness. > I'll to do that in the future. Thanks for the hint. > Acked-by: Myles Watson > Thanks, committed in r4341. Regards, Carl-Daniel -- http://www.hailfinger.org/ From rminnich at gmail.com Fri Jun 5 22:51:02 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 5 Jun 2009 13:51:02 -0700 Subject: [coreboot] [PATCH] flashrom: Add all Eon EN25* SPI chips In-Reply-To: <4A297F81.2000306@gmx.net> References: <4A297F81.2000306@gmx.net> Message-ID: <13426df10906051351o77e8f055j8b34fd8968fa5fae@mail.gmail.com> cool. Acked-by: Ronald G. Minnich w.r.t. your other patch: I am waiting to see if others with more expert opinions have anything to say. ron From svn at coreboot.org Fri Jun 5 22:53:07 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 5 Jun 2009 22:53:07 +0200 Subject: [coreboot] [flashrom] r580 - trunk Message-ID: Author: hailfinger Date: 2009-06-05 22:53:07 +0200 (Fri, 05 Jun 2009) New Revision: 580 Modified: trunk/flash.h trunk/flashchips.c Log: Add all Eon EN25* SPI chips. Some IDs were already in flash.h. EN25B05 EN25B10 EN25B20 EN25B40 EN25B80 EN25B16 EN25B32 EN25B64 EN25F40 EN25F80 EN25F16 EN25P* are supported as well, but they seem to be identical to EN25B. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Ronald G. Minnich Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-05 18:32:07 UTC (rev 579) +++ trunk/flash.h 2009-06-05 20:53:07 UTC (rev 580) @@ -360,6 +360,10 @@ #define EN_25B80 0x2014 #define EN_25B16 0x2015 #define EN_25B32 0x2016 +#define EN_25B64 0x2017 +#define EN_25F40 0x3113 +#define EN_25F80 0x3114 +#define EN_25F16 0x3115 #define EN_29F512 0x7F21 #define EN_29F010 0x7F20 #define EN_29F040A 0x7F04 Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-05 18:32:07 UTC (rev 579) +++ trunk/flashchips.c 2009-06-05 20:53:07 UTC (rev 580) @@ -777,6 +777,182 @@ }, { + .vendor = "Eon", + .name = "EN25B05", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B05, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B10", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B10, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B20", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B20, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B40", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B40, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B80", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B80, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B32", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B32, + .total_size = 4096, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25B64", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25B64, + .total_size = 8192, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25F40", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25F40, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25F80", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25F80, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25F16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID, + .model_id = EN_25F16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "EON", .name = "EN29F002(A)(N)B", .bustype = CHIP_BUSTYPE_PARALLEL, From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 22:55:26 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 22:55:26 +0200 Subject: [coreboot] [PATCH] flashrom: Add all Eon EN25* SPI chips In-Reply-To: <13426df10906051351o77e8f055j8b34fd8968fa5fae@mail.gmail.com> References: <4A297F81.2000306@gmx.net> <13426df10906051351o77e8f055j8b34fd8968fa5fae@mail.gmail.com> Message-ID: <4A29863E.7030003@gmx.net> On 05.06.2009 22:51, ron minnich wrote: > cool. > > Acked-by: Ronald G. Minnich > That was fast. Thanks, committed in r580. > w.r.t. your other patch: I am waiting to see if others with more > expert opinions have anything to say. > Sure. Regards, Carl-Daniel -- http://www.hailfinger.org/ From info at coresystems.de Fri Jun 5 22:57:01 2009 From: info at coresystems.de (coreboot information) Date: Fri, 05 Jun 2009 22:57:01 +0200 Subject: [coreboot] build service results for r4341 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4341 to the coreboot repository. This caused the following changes: Change Log: K8 RAM init debug messages are pretty short and sometimes cryptic. Make them a bit more verbose and hopefully more understandable. Old messages for my machine with 5 GB: RAM: 0x00400000 kB Ram3 [...] Initializing memory: done RAM: 0x00500000 kB New messages: RAM end at 0x00400000 kB Adjusting lower RAM end Lower RAM end at 0x003f0000 kB Ram3 [...] Initializing memory: done Handling memory hole at 0x00300000 (default) RAM end at 0x00500000 kB Handling memory mapped above 4 GB Upper RAM end at 0x00500000 kB Correcting memory amount mapped below 4 GB Adjusting lower RAM end Lower RAM end at 0x00300000 kB Signed-off-by: Carl-Daniel Hailfinger Acked-by: Myles Watson Build Log: Compilation of arima:hdama has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=hdama&vendor=arima&num=2 Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=a8n_e&vendor=asus&num=2 Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=a8v-e_se&vendor=asus&num=2 Compilation of broadcom:blast has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=blast&vendor=broadcom&num=2 Compilation of ibm:e325 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=e325&vendor=ibm&num=2 Compilation of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=e326&vendor=ibm&num=2 Compilation of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=dk8_htx&vendor=iwill&num=2 Compilation of iwill:dk8s2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=dk8s2&vendor=iwill&num=2 Compilation of iwill:dk8x has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=dk8x&vendor=iwill&num=2 Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=ms7135&vendor=msi&num=2 Compilation of newisys:khepri has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=khepri&vendor=newisys&num=2 Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=ultra40&vendor=sunw&num=2 Compilation of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2850&vendor=tyan&num=2 Compilation of tyan:s2875 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2875&vendor=tyan&num=2 Compilation of tyan:s2880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2880&vendor=tyan&num=2 Compilation of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2881&vendor=tyan&num=2 Compilation of tyan:s2882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2882&vendor=tyan&num=2 Compilation of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2885&vendor=tyan&num=2 Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2891&vendor=tyan&num=2 Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2892&vendor=tyan&num=2 Compilation of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2895&vendor=tyan&num=2 Compilation of tyan:s4880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s4880&vendor=tyan&num=2 Compilation of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s4882&vendor=tyan&num=2 If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 23:06:25 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 23:06:25 +0200 Subject: [coreboot] build service results for r4341 In-Reply-To: References: Message-ID: <4A2988D1.3020906@gmx.net> On 05.06.2009 22:57, coreboot information wrote: > The developer "hailfinger" checked in revision 4341 > > Change Log: > K8 RAM init debug messages are pretty short and sometimes cryptic. Make > them a bit more verbose and hopefully more understandable. > > Signed-off-by: Carl-Daniel Hailfinger > Acked-by: Myles Watson > > [Broken compilation] > arima:hdama asus:a8n_e asus:a8v-e_se broadcom:blast ibm:e325 ibm:e326 > iwill:dk8_htx iwill:dk8s2 iwill:dk8x msi:ms7135 newisys:khepri > sunw:ultra40 tyan:s2850 tyan:s2875 tyan:s2880 tyan:s2881 tyan:s2882 > tyan:s2885 tyan:s2891 tyan:s2892 tyan:s2895 tyan:s4880 tyan:s4882 Sorry. It seems I overlooked these during my abuild run. Basically, all non-revF K8 are broken because printk_raminit is not defined. I'll send a fixup. Regards, Carl-Daniel -- http://www.hailfinger.org/ From urjaman at gmail.com Fri Jun 5 23:12:41 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Sat, 6 Jun 2009 00:12:41 +0300 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <4A296E32.6060708@gmx.net> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A296E32.6060708@gmx.net> Message-ID: <460f92b70906051412r15ed6e01v3d52bff81ffb66d@mail.gmail.com> > Yes, for that you need flow control. For example, you you have the > programmer return the amount of bytes free in the buffer after each > command stream you send to the device. > For a moment i was adding a "return bytes free in buffer" command to the protocol, but then i realized that if the code sent that command as the last in command stream, and waited for the answer, the answer would always be that the buffer is empty, because it just had to go though all the data in the buffer to get the command. So i'm sticking with the - query buffer size in the beginning - when doing opbuf writes, count bytes sent - if about to have sent too many bytes, instead send NOP and wait for the ACK and clear the counter and continue I have the protocol specification ready and the AVR code compiles already, i'm just moving to flashrom code. I'll attach the .txt to this mail, it's better viewed with proper tabs and fixed-width font (leafpad fullscreen 1280x1024 is nice :P). -- urjaman -------------- next part -------------- Serial Flasher Protocol Specification Command And Answer Sequence - not all commands give an answer PC: LENGHT(8bit) COMMAND(8bit) DEV: ACK/NAK(8bit) or nothing ACK = 0xAA NAK = 0x55 All multibyte values are little-endian. COMMAND Description Parameters Return Value 0x00 NOP none ACK 0x01 Query serial buffer size none ACK + 16bit size / NAK 0x02 Query supported bustypes none ACK + 8-bit flags (as per flashrom) / NAK: bit 0: PARALLEL bit 1: LPC bit 2: FWH bit 3: SPI if ever supported 0x03 Query supported chip size none ACK + 8bit power of two / NAK 0x04 Query operation buffer size none ACK + 16bit size / NAK 0x05 Read byte 24-bit addr ACK + BYTE / NAK 0x06 Read n bytes 24-bit addr + 24-bit lenght ACK + lenght bytes / NAK 0x07 Initialize operation buffer none ACK / NAK 0x08 Write to opbuf: Write byte 24-bit addr + 8-bit byte nothing / NAK (NOTE: takes 6 bytes in opbuf) 0x09 Write to opbuf: Write byte seq 8-bit byte nothing / NAK (NOTE: takes 1 bytes in opbuf) 0x0A Write to opbuf: delay 32-bit usecs nothing / NAK (NOTE: takes 5 bytes in opbuf) 0x0B Execute operation buffer none ACK / NAK - Execute operation buffer will also clear it 0x?? unimplemented command any NAK From lasaine at lvk.cs.msu.su Fri Jun 5 23:16:43 2009 From: lasaine at lvk.cs.msu.su (Alexander Gordeev) Date: Sat, 6 Jun 2009 01:16:43 +0400 Subject: [coreboot] flashrom: Gigabyte GA-EP35-DS3L test report Message-ID: <200906060116.43276.lasaine@lvk.cs.msu.su> Hi all! I've tested Gigabyte GA-EP35-DS3L board (http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2778) and it is supported by flashrom out of the box: flashrom v0.9.0+r544 No coreboot table found. Found chipset "Intel ICH9", enabling flash write... OK. Calibrating delay loop... OK. Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. No operations were specified. I've tested all the operations and rebooted to a new BIOS and everything is ok so far. I'll be happy to provide any additional information so please feel free to ask! -- Alexander From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 23:37:22 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 23:37:22 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906051412r15ed6e01v3d52bff81ffb66d@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A296E32.6060708@gmx.net> <460f92b70906051412r15ed6e01v3d52bff81ffb66d@mail.gmail.com> Message-ID: <4A299012.6060409@gmx.net> On 05.06.2009 23:12, Urja Rannikko wrote: >> Yes, for that you need flow control. For example, you you have the >> programmer return the amount of bytes free in the buffer after each >> command stream you send to the device. >> >> > For a moment i was adding a "return bytes free in buffer" command to > the protocol, but then i realized that if the code sent that command > as the last in command stream, and waited for the answer, the answer > would always be that the buffer is empty, because it just had to go > though all the data in the buffer to get the command. So i'm sticking > with the > - query buffer size in the beginning > - when doing opbuf writes, count bytes sent > - if about to have sent too many bytes, instead send NOP and wait for > the ACK and clear the counter and continue > Good idea. > I have the protocol specification ready and the AVR code compiles > already, i'm just moving to flashrom code. I'll attach the .txt to > this mail, it's better viewed with proper tabs and fixed-width font > (leafpad fullscreen 1280x1024 is nice :P). I like the protocol specification. A few minor design notes, though. > Serial Flasher Protocol Specification > > > Command And Answer Sequence - not all commands give an answer > PC: LENGHT(8bit) COMMAND(8bit) > DEV: ACK/NAK(8bit) or nothing > > ACK = 0xAA > NAK = 0x55 > Since you comunicate over serial, it may happen that one bit is lost/inserted. Since you specified ACK = NAK <<1 this could result in spurious acks if there are synchronization problems. I have seen bitstream sync problems too often with SPI communication, so I'm extra careful. What about ACK = 0x10 (Is Ok) NAK = 0xBA (BAd) Your choice, though. Anything else would be just as good if one value is not a shift of the other. > All multibyte values are little-endian. > > COMMAND Description Parameters Return Value > 0x00 NOP none ACK > Maybe call it NOPACK. > 0x01 Query serial buffer size none ACK + 16bit size / NAK > 0x02 Query supported bustypes none ACK + 8-bit flags (as per flashrom) / NAK: > bit 0: PARALLEL > bit 1: LPC > bit 2: FWH > bit 3: SPI if ever supported > 0x03 Query supported chip size none ACK + 8bit power of two / NAK > 0x04 Query operation buffer size none ACK + 16bit size / NAK > 0x05 Read byte 24-bit addr ACK + BYTE / NAK > 0x06 Read n bytes 24-bit addr + 24-bit lenght ACK + lenght bytes / NAK > lenght -> length > 0x07 Initialize operation buffer none ACK / NAK > 0x08 Write to opbuf: Write byte 24-bit addr + 8-bit byte nothing / NAK (NOTE: takes 6 bytes in opbuf) > 0x09 Write to opbuf: Write byte seq 8-bit byte nothing / NAK (NOTE: takes 1 bytes in opbuf) > Hm. I don't understand the opbuf lengths here. By the way, having a single-byte write command (like you have) and a multi-byte write command would probably be a more future-proof design. 0x09 Write to opbuf: Write byte seq 24-bit addr + 24-bit length + n bytes data ACK/NAK (Note: takes 7+n bytes in opbuf) > 0x0A Write to opbuf: delay 32-bit usecs nothing / NAK (NOTE: takes 5 bytes in opbuf) > I'd like all commands to send a return code. All those write opcodes could be returning ACK even before they are sent. > 0x0B Execute operation buffer none ACK / NAK > - Execute operation buffer will also clear it > 0x?? unimplemented command any NAK > 0x0C Query programmer interface version 4 bytes "pRoG" ACK + 2 bytes version (>0) 0x0D Query programmer name none ACK + 16 bytes string (NULL padding) I'd insert interface version and programmer name as 0x00 and 0x01, moving everything else down. That way, we can change the interface later and query it easily. The only thing we need to keep constant in the interface is opcode 0x00. Everything else can be changed as needed. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 23:42:37 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 23:42:37 +0200 Subject: [coreboot] flashrom source browser Message-ID: <4A29914D.20402@gmx.net> Thanks to Patrick Georgi, we now can look at the flashrom source with a web browser. http://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk Regards, Carl-Daniel From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 23:54:38 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 23:54:38 +0200 Subject: [coreboot] [PATCH] Fix non-revF K8 ram init compilation In-Reply-To: <4A2988D1.3020906@gmx.net> References: <4A2988D1.3020906@gmx.net> Message-ID: <4A29941E.4020209@gmx.net> On 05.06.2009 23:06, Carl-Daniel Hailfinger wrote: > Sorry. It seems I overlooked these during my abuild run. Basically, all > non-revF K8 are broken because printk_raminit is not defined. > Fix non-revF K8 ram init compilation which was broken in r4341. abuild tested on affected targets. Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-k8_raminit_debugmessages_fix/src/northbridge/amd/amdk8/raminit.c =================================================================== --- LinuxBIOSv2-k8_raminit_debugmessages_fix/src/northbridge/amd/amdk8/raminit.c (Revision 4341) +++ LinuxBIOSv2-k8_raminit_debugmessages_fix/src/northbridge/amd/amdk8/raminit.c (Arbeitskopie) @@ -19,6 +19,14 @@ #define QRANK_DIMM_SUPPORT 0 #endif +#define RAM_TIMING_DEBUG 0 + +#if RAM_TIMING_DEBUG == 1 +#define printk_raminit printk_debug +#else +#define printk_raminit(fmt, arg...) +#endif + #if defined (__GNUC__) static void hard_reset(void); #endif @@ -2106,7 +2114,7 @@ return; hw_spd_err: /* Unrecoverable error reading SPD data */ - print_err("SPD error - reset\n"); + printk_err("SPD error - reset\n"); hard_reset(); return; } -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: linuxbios_k8_raminit_debugmessages_fix.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Jun 5 23:57:53 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 05 Jun 2009 23:57:53 +0200 Subject: [coreboot] [ANNOUNCE] SerialICE - QEMU based x86 firmware debugger In-Reply-To: <4A298068.6080206@coresystems.de> References: <4A298068.6080206@coresystems.de> Message-ID: <4A2994E1.6010403@gmx.net> On 05.06.2009 22:30, Stefan Reinauer wrote: > SerialICE is a BIOS/Firmware debugging tool. It allows you to run and > observe BIOS images (such as coreboot?: http://www.coreboot.org/) > written for real hardware in Qemu (http://www.nongnu.org/qemu) for > debugging purposes. Thanks to Qemu's compelling feature set, it's also > possible to debug this BIOS code with GNU GDB. > Wow! Thank you for creating and publishing this! > Known issues: > - infrastructure for compiling with gcc + xmmstack is there, but it > still fails with some odd assembler errors. This should push the > SerialICE rom shell clearly below 64k again. > I think xmmstack had some dependencies on the gcc version. Maybe Urbez knows more. Regards, Carl-Daniel -- http://www.hailfinger.org/ From marcj303 at gmail.com Sat Jun 6 00:00:57 2009 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 5 Jun 2009 16:00:57 -0600 Subject: [coreboot] [patch][v2]:fam10 microcode In-Reply-To: <534e5dc20906051036q4fae4c22s5c72c06a6b88a31b@mail.gmail.com> References: <200906050031.29342.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906041604i2179c536wdd90a769eb3f4874@mail.gmail.com> <200906051749.53385.christian.leber@ziti.uni-heidelberg.de> <534e5dc20906051036q4fae4c22s5c72c06a6b88a31b@mail.gmail.com> Message-ID: <534e5dc20906051500y315b0cc0t6c19cbad4f402ba5@mail.gmail.com> Patch for errata 327, 344, 346, 354. Three of those are HT errata so I hope that fixes the issue. Signed-off-by: Marc Jones -- http://marcjonesconsulting.com -------------- next part -------------- A non-text attachment was scrubbed... Name: fam10c2errata.patch Type: application/octet-stream Size: 4723 bytes Desc: not available URL: From mylesgw at gmail.com Sat Jun 6 00:03:16 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 16:03:16 -0600 Subject: [coreboot] [PATCH] Fix non-revF K8 ram init compilation In-Reply-To: <4A29941E.4020209@gmx.net> References: <4A2988D1.3020906@gmx.net> <4A29941E.4020209@gmx.net> Message-ID: <2831fecf0906051503l1df73256va0f7b98df3ef157c@mail.gmail.com> On Fri, Jun 5, 2009 at 3:54 PM, Carl-Daniel Hailfinger wrote: > On 05.06.2009 23:06, Carl-Daniel Hailfinger wrote: >> Sorry. It seems I overlooked these during my abuild run. Basically, all >> non-revF K8 are broken because printk_raminit is not defined. >> > > Fix non-revF K8 ram init compilation which was broken in r4341. I'd prefer to fix it by changing all printk_raminit -> printk_spew. I'm sorry I didn't catch that. I don't like the idea of adding more #defines and #if segments. Thanks, Myles From marcj303 at gmail.com Sat Jun 6 00:08:10 2009 From: marcj303 at gmail.com (Marc Jones) Date: Fri, 5 Jun 2009 16:08:10 -0600 Subject: [coreboot] [PATCH]es: Fixes for AMD Fam10h Errata In-Reply-To: <200906051710.23113.patrick@georgi-clan.de> References: <200906051710.23113.patrick@georgi-clan.de> Message-ID: <534e5dc20906051508v46651ac1pecf2d5b9896d7d54@mail.gmail.com> On Fri, Jun 5, 2009 at 9:10 AM, Patrick Georgi wrote: > Hi, > > attached patches implement two errata fixes. > Could you add a CPU revision check to errata 350? Something like this: if (pDCTstat->LogicalCPUID & AMD_RB_C2) { vErrata350(pMCTstat, pDCTstatA); } Marc -- http://marcjonesconsulting.com From urjaman at gmail.com Sat Jun 6 00:08:56 2009 From: urjaman at gmail.com (Urja Rannikko) Date: Sat, 6 Jun 2009 01:08:56 +0300 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <4A299012.6060409@gmx.net> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A296E32.6060708@gmx.net> <460f92b70906051412r15ed6e01v3d52bff81ffb66d@mail.gmail.com> <4A299012.6060409@gmx.net> Message-ID: <460f92b70906051508k2745004fse20b17198d983c82@mail.gmail.com> On Sat, Jun 6, 2009 at 00:37, Carl-Daniel Hailfinger wrote: > On 05.06.2009 23:12, Urja Rannikko wrote: >>> Yes, for that you need flow control. For example, you you have the >>> programmer return the amount of bytes free in the buffer after each >>> command stream you send to the device. >>> >>> >> For a moment i was adding a "return bytes free in buffer" command to >> the protocol, but then i realized that if the code sent that command >> as the last in command stream, and waited for the answer, the answer >> would always be that the buffer is empty, because it just had to go >> though all the data in the buffer to get the command. So i'm sticking >> with the >> - query buffer size in the beginning >> - when doing opbuf writes, count bytes sent >> - if about to have sent too many bytes, instead send NOP and wait for >> the ACK and clear the counter and continue >> > > Good idea. > >> I have the protocol specification ready and the AVR code compiles >> already, i'm just moving to flashrom code. I'll attach the .txt to >> this mail, it's better viewed with proper tabs and fixed-width font >> (leafpad fullscreen 1280x1024 is nice :P). > > I like the protocol specification. A few minor design notes, though. > >> Serial Flasher Protocol Specification >> >> >> Command And Answer Sequence - not all commands give an answer >> PC: LENGHT(8bit) COMMAND(8bit) >> DEV: ACK/NAK(8bit) or nothing >> >> ACK = 0xAA >> NAK = 0x55 >> > > Since you comunicate over serial, it may happen that one bit is > lost/inserted. Since you specified > ACK = NAK <<1 > this could result in spurious acks if there are synchronization > problems. I have seen bitstream sync problems too often with SPI > communication, so I'm extra careful. > What about > ACK = 0x10 (Is Ok) > NAK = 0xBA (BAd) > > Your choice, though. Anything else would be just as good if one value is > not a shift of the other. 0x10 and 0xBA are ok. >> All multibyte values are little-endian. >> >> COMMAND ? ? ? Description ? ? ? ? ? ? ? ? ? ? Parameters ? ? ? ? ? ? ? ? ? ? ?Return Value >> 0x00 ?NOP ? ? ? ? ? ? ? ? ? ? ? ? ? ? none ? ? ? ? ? ? ? ? ? ? ? ? ? ?ACK >> > > Maybe call it NOPACK. > >> 0x01 ?Query serial buffer size ? ? ? ?none ? ? ? ? ? ? ? ? ? ? ? ? ? ?ACK + 16bit size / NAK >> 0x02 ?Query supported bustypes ? ? ? ?none ? ? ? ? ? ? ? ? ? ? ? ? ? ?ACK + 8-bit flags (as per flashrom) / NAK: >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit 0: PARALLEL >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit 1: LPC >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit 2: FWH >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit 3: SPI if ever supported >> 0x03 ?Query supported chip size ? ? ? none ? ? ? ? ? ? ? ? ? ? ? ? ? ?ACK + 8bit power of two / NAK >> 0x04 ?Query operation buffer size ? ? none ? ? ? ? ? ? ? ? ? ? ? ? ? ?ACK + 16bit size / NAK >> 0x05 ?Read byte ? ? ? ? ? ? ? ? ? ? ? 24-bit addr ? ? ? ? ? ? ? ? ? ? ACK + BYTE / NAK >> 0x06 ?Read n bytes ? ? ? ? ? ? ? ? ? ?24-bit addr + 24-bit lenght ? ? ACK + lenght bytes / NAK >> > > lenght -> length > >> 0x07 ?Initialize operation buffer ? ? none ? ? ? ? ? ? ? ? ? ? ? ? ? ?ACK / NAK >> 0x08 ?Write to opbuf: Write byte ? ? ?24-bit addr + 8-bit byte ? ? ? ?nothing / NAK (NOTE: takes 6 bytes in opbuf) >> 0x09 ?Write to opbuf: Write byte seq ?8-bit byte ? ? ? ? ? ? ? ? ? ? ?nothing / NAK (NOTE: takes 1 bytes in opbuf) >> > > Hm. I don't understand the opbuf lengths here. > By the way, having a single-byte write command (like you have) and a > multi-byte write command would probably be a more future-proof design. > 0x09 ? ? Write to opbuf: Write byte seq 24-bit addr + 24-bit length + n > bytes data ? ? ? ? ? ? ? ? ? ACK/NAK (Note: takes 7+n bytes in opbuf) Firstly, realize that the above command would have a second length parameter of different size than the first in parameters - a parser without knowledge of the commands parameters would surely fail. the opbuf lenghts are because the driver must take note not to buffer too much operations in the AVR before executing them. A write command format in the AVR memory is essentially 0x00 (writeop) 0xnn (lenght) 0xaa 0xbb 0cc (begin address) + n bytes of data. the 0x08 operation creates the initial 1-lenght write op that takes 6 bytes (1 op, 1 lenght, 3 addr, 1 data) and each 0x09 operation adds one to lenght and appends the data. In case the length is already 0 (meaning 256), a new write operation with modified address (+256) is created, etc. So a continouous write of 256 bytes takes 261 bytes in the buffer. I considered adding a write n function, but realized that it would make the parameter lenght variable - now i can check that it is correct with a simple op2len table (a double-check that the parameters are correct). I dont see it worth the hassle, and it could code at a maximum 252 bytes of data with the current opcode lenght format - and the AVR's memory would surely run out if i asked it to take in some >1k operation anyways. The read n operation is in many ways different - it can have the length in parameters because that is the return data length (not command parameter length), and the AVR doesnt need to buffer the data it sends in a reply. >> 0x0A ?Write to opbuf: delay ? ? ? ? ? 32-bit usecs ? ? ? ? ? ? ? ? ? ?nothing / NAK (NOTE: takes 5 bytes in opbuf) >> > > I'd like all commands to send a return code. All those write opcodes > could be returning ACK even before they are sent. Huh? (My AVR doesnt know the future... And the computer would surely be baffled about an ACK before sending the command :P) >> 0x0B ?Execute operation buffer ? ? ? ?none ? ? ? ? ? ? ? ? ? ? ? ? ? ?ACK / NAK >> ? ? ? ? ? ? ? - Execute operation buffer will also clear it >> 0x?? ?unimplemented command ? ? ? ? ? any ? ? ? ? ? ? ? ? ? ? ? ? ? ? NAK >> > > 0x0C ? ? Query programmer interface version ? ? 4 bytes "pRoG" ? ACK + 2 > bytes version (>0) > 0x0D ? ? Query programmer name ? ?none ? ?ACK + 16 bytes string (NULL > padding) > > I'd insert interface version and programmer name as 0x00 and 0x01, > moving everything else down. That way, we can change the interface later > and query it easily. The only thing we need to keep constant in the > interface is opcode 0x00. Everything else can be changed as needed. > Implementing... -- urjaman From patrick at georgi-clan.de Sat Jun 6 00:27:06 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 06 Jun 2009 00:27:06 +0200 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS In-Reply-To: <20090605190003.GK18065@greenwood> References: <4A2957D6.5080906@georgi-clan.de> <20090605190003.GK18065@greenwood> Message-ID: <4A299BBA.9090900@georgi-clan.de> Uwe Hermann schrieb: > Shouldn't this be > > option CC="$(CROSSCC)" > option CROSS_COMPILE="$(CROSS_PREFIX)" > option HOSTCC="$(CROSS_HOSTCC)" > > Does the syntax without braces work? > They're replaced by abuild, and not part of make's variable expansion. Using $(..) would actually break them > but please take Myles' comments into account. > That is, remove the Config-abuild.lb for the HP board? Thanks, Patrick From patrick at georgi-clan.de Sat Jun 6 00:27:00 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sat, 06 Jun 2009 00:27:00 +0200 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS In-Reply-To: <2831fecf0906051054v22a50b4clb5634ddaf3cbd0f@mail.gmail.com> References: <4A2957D6.5080906@georgi-clan.de> <2831fecf0906051054v22a50b4clb5634ddaf3cbd0f@mail.gmail.com> Message-ID: <4A299BB4.1040605@georgi-clan.de> Myles Watson schrieb: >> -option CONFIG_CBFS = 1 >> - >> romimage "fallback" >> option USE_FALLBACK_IMAGE=1 >> option ROM_IMAGE_SIZE=0x20000 >> > Isn't this line supposed to be gone? > There are two patches that affect the HP board: one moves the CONFIG_CBFS variable to Options.lb, the other changes the CBFS configuration to work with the patch. > Maybe we don't need a separate Config-abuild for the dl145_g3 since > the problem was the ROM_IMAGE_SIZE on the build machine. Less to keep > correct. > I'll test with that file removed. If that works, I'll do that. Thanks, Patrick From c-d.hailfinger.devel.2006 at gmx.net Sat Jun 6 00:36:27 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 06 Jun 2009 00:36:27 +0200 Subject: [coreboot] [RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol In-Reply-To: <460f92b70906051508k2745004fse20b17198d983c82@mail.gmail.com> References: <460f92b70906050424p749885afud7f63434b4b4e0f9@mail.gmail.com> <20090605124850.25117.qmail@stuge.se> <460f92b70906050644p411dae6di835a8a52d1e2967c@mail.gmail.com> <4A29292B.5000309@gmx.net> <460f92b70906050743v4711adbdke4954b9a6563089@mail.gmail.com> <4A296E32.6060708@gmx.net> <460f92b70906051412r15ed6e01v3d52bff81ffb66d@mail.gmail.com> <4A299012.6060409@gmx.net> <460f92b70906051508k2745004fse20b17198d983c82@mail.gmail.com> Message-ID: <4A299DEB.8020303@gmx.net> On 06.06.2009 00:08, Urja Rannikko wrote: > On Sat, Jun 6, 2009 at 00:37, Carl-Daniel Hailfinger > wrote: > >> On 05.06.2009 23:12, Urja Rannikko wrote: >> >>> Serial Flasher Protocol Specification >>> >>> All multibyte values are little-endian. >>> >>> COMMAND Description Parameters Return Value >>> >>> 0x07 Initialize operation buffer none ACK / NAK >>> 0x08 Write to opbuf: Write byte 24-bit addr + 8-bit byte nothing / NAK (NOTE: takes 6 bytes in opbuf) >>> 0x09 Write to opbuf: Write byte seq 8-bit byte nothing / NAK (NOTE: takes 1 bytes in opbuf) >>> >>> >> Hm. I don't understand the opbuf lengths here. >> By the way, having a single-byte write command (like you have) and a >> multi-byte write command would probably be a more future-proof design. >> 0x09 Write to opbuf: Write byte seq 24-bit addr + 24-bit length + n >> bytes data ACK/NAK (Note: takes 7+n bytes in opbuf) >> > Firstly, realize that the above command would have a second length > parameter of different size than the first in parameters - a parser > without knowledge of the commands parameters would surely fail. > We're misunderstanding each other here. I propose that flashrom does all the merging internally (up to a maximum write size). Thus the n-byte read command and the n-byte write command would be very similar. > the opbuf lenghts are because the driver must take note not to buffer > too much operations in the AVR before executing them. A write command > format in the AVR memory is essentially 0x00 (writeop) 0xnn (lenght) > 0xaa 0xbb 0cc (begin address) + n bytes of data. the 0x08 operation > creates the initial 1-lenght write op that takes 6 bytes (1 op, 1 > lenght, 3 addr, 1 data) and each 0x09 operation adds one to lenght and > appends the data. In case the length is already 0 (meaning 256), a new > write operation with modified address (+256) is created, etc. So a > continouous write of 256 bytes takes 261 bytes in the buffer. > Unless there is some device limitation, I think it is easier to already send a byte stream the AVR uses internally than having the AVR translate it in a complicated way. OTOH, your AVR internal representation is designed for compactness. > I considered adding a write n function, but realized that it would > make the parameter lenght variable - now i can check that it is > correct with a simple op2len table (a double-check that the parameters > are correct). I dont see it worth the hassle, and it could code at a > maximum 252 bytes of data with the current opcode lenght format - and > the AVR's memory would surely run out if i asked it to take in some > >1k operation anyways. > So you check the commands the AVR receives from the host, but not the commands in the internal AVR buffer? Because according to your description, the internal commands can have variable size. > The read n operation is in many ways different - it can have the > length in parameters because that is the return data length (not > command parameter length), and the AVR doesnt need to buffer the data > it sends in a reply. > If I understand this correctly, your command-from-host parser in the AVR is easier to write if the commands from the host have per-opcode constant length? If that is the case, I propose to add an additional opcode 0x02 which returns a 32-bit field of supported opcodes. Then your device could mark the write-n as unsupported and the write-next as supported. >> I'd like all commands to send a return code. All those write opcodes >> could be returning ACK even before they are sent. >> > > Huh? (My AVR doesnt know the future... And the computer would surely > be baffled about an ACK before sending the command :P) > Bad wording on my side. A write opcode should be acked after it is received by the programmer. No need to wait until the write reaches the flash chip. From uwe at hermann-uwe.de Sat Jun 6 00:44:31 2009 From: uwe at hermann-uwe.de (Uwe Hermann) Date: Sat, 6 Jun 2009 00:44:31 +0200 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS In-Reply-To: <4A299BBA.9090900@georgi-clan.de> References: <4A2957D6.5080906@georgi-clan.de> <20090605190003.GK18065@greenwood> <4A299BBA.9090900@georgi-clan.de> Message-ID: <20090605224431.GM18065@greenwood> On Sat, Jun 06, 2009 at 12:27:06AM +0200, Patrick Georgi wrote: > Uwe Hermann schrieb: >> Shouldn't this be >> >> option CC="$(CROSSCC)" >> option CROSS_COMPILE="$(CROSS_PREFIX)" >> option HOSTCC="$(CROSS_HOSTCC)" >> >> Does the syntax without braces work? >> > They're replaced by abuild, and not part of make's variable expansion. > Using $(..) would actually break them >> but please take Myles' comments into account. >> > That is, remove the Config-abuild.lb for the HP board? Yes, but it's also fine if you can fix this in another way. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org From mylesgw at gmail.com Sat Jun 6 00:47:01 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 5 Jun 2009 16:47:01 -0600 Subject: [coreboot] [PATCH]es to get normal image to work again with CBFS In-Reply-To: <4A299BB4.1040605@georgi-clan.de> References: <4A2957D6.5080906@georgi-clan.de> <2831fecf0906051054v22a50b4clb5634ddaf3cbd0f@mail.gmail.com> <4A299BB4.1040605@georgi-clan.de> Message-ID: <2831fecf0906051547v6c4086adm957b82376b530b8b@mail.gmail.com> >> Isn't this line supposed to be gone? >> > > There are two patches that affect the HP board: one moves the CONFIG_CBFS > variable to Options.lb, the other changes the CBFS configuration to work > with the patch. I was confused by the order in which the patches were inlined in gmail. Sorry about that. > I'll test with that file removed. If that works, I'll do that. Great. Thanks, Myles From svn at coreboot.org Sat Jun 6 01:02:43 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Sat, 6 Jun 2009 01:02:43 +0200 Subject: [coreboot] [v2] r4342 - in trunk/coreboot-v2/src/mainboard/via: . epia-m700 Message-ID: Author: uwe Date: 2009-06-06 01:02:43 +0200 (Sat, 06 Jun 2009) New Revision: 4342 Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/ trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/via/epia-m700/chip.h trunk/coreboot-v2/src/mainboard/via/epia-m700/cmos.layout trunk/coreboot-v2/src/mainboard/via/epia-m700/dsdt.c trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c trunk/coreboot-v2/src/mainboard/via/epia-m700/mainboard.c trunk/coreboot-v2/src/mainboard/via/epia-m700/ssdt.c trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.h Log: Initial untested board code for the VIA EPIA-M700 Mini-ITX board. The patch has been submitted by bari and written by OLPC. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,146 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 One Laptop per Child, Association, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +#default XIP_ROM_SIZE = ROM_IMAGE_SIZE +#default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) + + +arch i386 end +driver mainboard.o +driver wakeup.o +if HAVE_PIRQ_TABLE object irq_tables.o end +if HAVE_MP_TABLE object mptable.o end +if HAVE_ACPI_TABLES + object fadt.o + object dsdt.o +# object ssdt.o + object acpi_tables.o +end +# these lines maybe noused +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +if USE_DCACHE_RAM + if CONFIG_USE_INIT + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + end + else + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end + end +end +mainboardinit cpu/via/16bit/entry16.inc +ldscript /cpu/via/16bit/entry16.lds + +mainboardinit northbridge/via/vx800/romstrap.inc +ldscript /northbridge/via/vx800/romstrap.lds + +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +#mainboardinit arch/i386/lib/cpu_reset.inc +#here cpu_reset.inc have label _cpu_reset, which is needed in failover,c, but cpu_reset.inc also has code to jump to __main() which is not included in cache_as_ram_auto_auto.c + + +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +if USE_DCACHE_RAM + mainboardinit cpu/via/car/cache_as_ram.inc +end + +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +# failover.inc need defination in cpu_reset.inc, but we do not include cpu_reset.inc,so ... +# mainboardinit ./failover.inc +end +#mainboardinit cpu/x86/fpu/enable_fpu.inc +#mainboardinit cpu/x86/mmx/enable_mmx.inc + + +if USE_DCACHE_RAM + if CONFIG_USE_INIT + initobject cache_as_ram_auto.o + else + mainboardinit ./cache_as_ram_auto.inc + end +end + +#mainboardinit cpu/x86/mmx/disable_mmx.inc +dir /pc80 + +config chip.h + + +chip northbridge/via/vx800 # Northbridge + device pci_domain 0 on + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + #device pci f.0 on end # IDE/SATA + #device pci f.1 on end # IDE + #device pci 10.0 on end # USB 1.1 + #device pci 10.1 on end # USB 1.1 + #device pci 10.2 on end # USB 1.1 + #device pci 10.4 on end # USB 2.0 + #device pci 11.0 on # Southbridge LPC + #end # pci 11.0 + + end # pci domain 0 + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end # vx800 Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "northbridge/via/vx800/DrivingClkPhaseData.h" + +// DQS Driving +//Reg0xE0, 0xE1 +// According to #Bank to set DRAM DQS Driving +// #Bank 1 2 3 4 5 6 7 8 +static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE}; +static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE}; + +// DQ Driving +//Reg0xE2, 0xE3 +// For DDR2: According to bank to set DRAM DQ Driving +static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; +static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; + + +// CS Driving +//Reg0xE4, 0xE5 +// According to #Bank to set DRAM CS Driving +// DDR1 #Bank 1 2 3 4 5 6 7 8 +static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; +static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44}; +static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44}; +static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44}; +// MAA Driving +//Reg0xE8, Reg0xE9 +static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = + { + //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 + { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 + { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 + {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~ + }; + +static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = + { + // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 + { 6, 0x86 }, // total MAB chips = 00 ~ 06 + { 18, 0x86 }, // total MAB chips = 06 ~ 18 + {255, 0xDB } // total MAB chips = 18 ~ + }; + +// DCLK Driving +//Reg0xE6, 0xE7 +// For DDR2: According to #Freq to set DRAM DCLK Driving +// freq 400M, 533M, 667M, 800M + +static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; +static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; + +/* +Duty cycle +Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB +D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF +According to DRAM frequency to control Duty Cycle +*/ +static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank + {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 }, + {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30} + }; + +static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank + {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 } + }; + + +/* +DRAM Clock Phase Control for FeedBack Mode +Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 +Processing: + 1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode + 2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b + 3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO + ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b + */ +static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } + }; + +static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank + {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 }, + {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 } + }; + +//vt6413c +/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank + {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, + {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 } + };*/ + +//vt6413d +static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } + }; + +/* +DRAM Write Data phase control +Modify NB Reg: Rx74/Rx75/Rx76 +*/ +//vt6413c +/*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank + {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, + {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 } + };*/ + +//vt6413D +static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank + {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 }, + {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 }, + {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } + }; + +/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank + {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, + {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 } + }; +*/ +/* +DQ/DQS Output Delay Control +Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 +*/ +static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = + { + // RxF0 RxF1 RxF2 RxF3 + { 0x00, 0x00, 0x00, 0x00 },// DDR400 + { 0x00, 0x00, 0x00, 0x00 },// DDR533 + { 0x00, 0x00, 0x00, 0x00 },// DDR667 + { 0x00, 0x00, 0x00, 0x00 }// DDR800 + }; +static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = + { + // RxF4 RxF5 RxF6 RxF7 + { 0x00, 0x00, 0x00, 0x00 },// DDR400 + { 0x00, 0x00, 0x00, 0x00 },// DDR533 + { 0x00, 0x00, 0x00, 0x00 },// DDR667 + { 0x00, 0x00, 0x00, 0x00 }// DDR800 + }; + +/* +DQ/DQS input Capture Control +modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B +*/ +//vt6413C +/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } + };*/ + +//Vt6413D +static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 } + }; + +static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = + { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank + {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 }, + {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 } + }; + +static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = +{ +// Rx70 Rx71 + { 0x00, 0x05 }, // DDR800 + { 0x00, 0x06 }, // DDR667 + { 0x00, 0x04 }, // DDR533 + { 0x00, 0x05 } // DDR400 +}; +static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = +{ +// Rx70 Rx71 + {0x00 , 0x04}, // DDR800 + {0x00 , 0x04}, // DDR667 + {0x00 , 0x03}, // DDR533 + {0x00 , 0x04} // DDR400 +}; Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,158 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 One Laptop per Child, Association, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses CONFIG_CBFS +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses HAVE_ACPI_TABLES +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_PCI_ROM_RUN +uses CONFIG_CONSOLE_VGA +uses CONFIG_MAX_PCI_BUSES +uses TTYS0_BAUD +uses CONFIG_VIDEO_MB +uses CONFIG_IOAPIC + + + +## +## new options +## +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses CONFIG_USE_INIT +uses MAX_RAM_SLOTS +uses USB_ENABLE +uses EHCI_ENABLE +uses HPET_ENABLE +uses USB_PORTNUM +uses FULL_ROM_SIZE +uses FULL_ROM_BASE +uses PAYLOAD_IS_SEABIOS +uses VIACONFIG_TOP_SM_SIZE_MB +uses VIACONFIG_VGA_PCI_10 +uses VIACONFIG_VGA_PCI_14 + +## +## new options +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xffef0000 +#default DCACHE_RAM_BASE=0xffbf0000 +#default DCACHE_RAM_BASE=0xfec00000 //hpet may use this +default DCACHE_RAM_SIZE=0x2000 +default CONFIG_USE_INIT=0 +default MAX_RAM_SLOTS=2 +default USB_ENABLE=1 +default EHCI_ENABLE=1 +default HPET_ENABLE=1 +default USB_PORTNUM=2 +default FULL_ROM_SIZE = 512 * 1024 +default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE+ 1) +default VIACONFIG_TOP_SM_SIZE_MB=0 +#default VIACONFIG_VGA_PCI_10=0xd0000008 +#default VIACONFIG_VGA_PCI_14=0xfd000000 +default VIACONFIG_VGA_PCI_10=0xf8000008 +default VIACONFIG_VGA_PCI_14=0xfc000000 + + +default ROM_SIZE = 512 * 1024 +default CONFIG_IOAPIC = 1 + +#define framebuffer size of VX800's integrated graphics card. support 32 64 128 256 +default CONFIG_VIDEO_MB = 64 + +default CONFIG_CONSOLE_SERIAL8250 = 1 +default CONFIG_PCI_ROM_RUN = 0 +default CONFIG_CONSOLE_VGA = 0 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_HARD_RESET = 0 +default HAVE_PIRQ_TABLE = 0 +default IRQ_SLOT_COUNT = 10 +default HAVE_ACPI_TABLES = 1 +default HAVE_OPTION_TABLE = 1 +default ROM_IMAGE_SIZE = 128 * 1024 +default FALLBACK_SIZE = ROM_SIZE +default USE_FALLBACK_IMAGE = 1 +default STACK_SIZE = 16 * 1024 +default HEAP_SIZE = 20 * 1024 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" + +## +## Set this to the max PCI bus number you would ever use for PCI config I/O. +## Setting this number very high will make pci_locate_device() take a long +## time when it can't find a device. +## +default CONFIG_MAX_PCI_BUSES = 3 +end + +# +# CBFS +# +# +default CONFIG_CBFS=0 +end Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * LinuxBIOS ACPI Table support + * written by Stefan Reinauer + * ACPI FADT, FACS, and DSDT table support added by + * Nick Barker , and those portions + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2005 Stefan Reinauer + * (C) Copyright 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * most parts of this file copied from src\mainboard\asus\a8v-e_se\acpi_tables.c, + * acpi_is_wakeup() is from Rudolf's S3 patch and SSDT was added + */ + +#include +#include +#include +#include +#include +#include <../../../northbridge/via/vx800/vx800.h> + +extern unsigned char AmlCode_dsdt[]; +extern unsigned char AmlCode_ssdt[]; + +/* +These four macro copied from #include , I have to do this since "default HAVE_MP_TABLE = 0" in option.lb, +and also since mainboard/via/*.* have no Mptable.c(so that I can not set HAVE_MP_TABLE = 1) as many other mainboard. +So I have to copy these four to here. acpi_fill_madt() need this. +*/ +#define MP_IRQ_POLARITY_HIGH 0x1 +#define MP_IRQ_POLARITY_LOW 0x3 +#define MP_IRQ_TRIGGER_EDGE 0x4 +#define MP_IRQ_TRIGGER_LEVEL 0xc + + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* NO MCFG in VX855, no pci-e*/ + return current; +} + +unsigned long acpi_create_madt_lapics(unsigned long current) +{ + device_t cpu; + int cpu_index = 0; + + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + continue; + } + if (!cpu->enabled) { + continue; + } + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + +unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) +{ + device_t cpu; + int cpu_index = 0; + + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + continue; + } + if (!cpu->enabled) { + continue; + } + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); + cpu_index++; + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VX800SB_APIC_ID, VX800SB_APIC_BASE, 0); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ +} + +#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_mcfg_t *mcfg; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + /* Align ACPI tables to 16byte */ + start = ( start + 0x0f ) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk_debug("ACPI: * FACS\n"); + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + printk_debug("ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + current += ((acpi_header_t *)AmlCode_dsdt)->length; + memcpy((void *)dsdt,(void *)AmlCode_dsdt, ((acpi_header_t *)AmlCode_dsdt)->length); + dsdt->checksum = 0; /* don't trust intel iasl compiler to get this right. */ + dsdt->checksum = acpi_checksum(dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); + + printk_debug("ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdt,fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk_debug("ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + /* NO MCFG in VX855, no pci-e*/ + + printk_debug("ACPI: * HPET\n"); + hpet = (acpi_mcfg_t *) current; + acpi_create_hpet(hpet); + current += hpet->header.length; + acpi_add_table(rsdt, hpet); +/* + printk_debug("ACPI: * SSDT\n"); + ssdt = (acpi_header_t *) current; + current += ((acpi_header_t *)AmlCode_ssdt)->length; + memcpy((void *)ssdt,(void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length); + ssdt->checksum = 0; // don't trust intel iasl compiler to get this right + ssdt->checksum = acpi_checksum(ssdt, ssdt->length); + acpi_add_table(rsdt, ssdt); + printk_debug("ACPI: * SSDT @ %08x Length %x\n", ssdt, ssdt->length); +*/ + + printk_info("ACPI: done.\n"); + return current; +} + +extern u32 wake_vec; +extern u8 acpi_sleep_type; + +int acpi_is_wakeup(void) { + return (acpi_sleep_type == 3); +} + Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,724 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * part of this file is from cx700 port, part of is from cn700 port, + * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch + */ + +#define ASSEMBLY 1 +#define __ROMCC__ +#define RAMINIT_SYSINFO 1 +#define CACHE_AS_RAM_ADDRESS_DEBUG 0 + +#include +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/via/vx800/vx800.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif +#include "cpu/x86/lapic/boot_cpu.c" + +/* this file contains the board-special SI value for raminit.c*/ +#include "mainboard/via/6413e/DrivingClkPhaseData.c" + +#include "northbridge/via/vx800/raminit.h" +#include "northbridge/via/vx800/raminit.c" +#include "cpu/x86/car/copy_and_run.c" +#include "mainboard/via/6413e/wakeup.h" + +/* this acpi_is_wakeup_early_via_VX800 is from Rudolf's patch post in maillist in 2008-9-8, + http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. +*/ + +void jason_tsc_count_car(void) +{/* + unsigned long long start; + asm volatile ("rdtsc" : "=A" (start)); + start >>= 20; + print_emerg("jason_tsc_count_car= "); + print_emerg_hex32((unsigned long) start); + print_emerg("\n");*/ +} + +int acpi_is_wakeup_early_via_vx800(void) { + device_t dev; + u16 tmp,result; + + print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX855_LPC), 0); + + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\r\n"); + + /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + tmp = inw(VX800_ACPI_IO_BASE + 0x04); + result= ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; + print_debug(" boot_mode="); + print_debug_hex16(result); + print_debug("\r\n"); + return result ; +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + + +/* all content of this function came from the cx700 port of coreboot. + */ +static void enable_mainboard_devices(void) +{ + device_t dev; + uint16_t values; + +#if 0 // add and close this switch, since some line cause error, some written at elsewhere (stage1 stage2), + u8 regdata; + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX855_LPC), 0); + + /* Disable GP3 */ + pci_write_config8(dev, 0x98, 0x00); + + pci_write_config8(dev, 0x50, 0x80);//disable mc97 + //martin disable internal KBC Configuration + pci_write_config8(dev, 0x51, 0x2d); //internal Config is needed to decide which key can be pressed to resume from s3 + + // this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. + //pci_write_config8(dev, 0x58, 0x42); + + //these writing may + regdata=pci_read_config8(dev, 0x58); + regdata|=0x41; + pci_write_config8(dev, 0x58,regdata); + pci_write_config8(dev, 0x59, 0x80); + pci_write_config8(dev, 0x5b, 0x01); +#endif + print_debug("In enable_mainboard_devices \r\n"); + + /*--AUTHOR-NOTE-- + Enable P2P Bridge Header for External PCI BUS. +--AUTHOR-NOTE--*/ + dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); + pci_write_config8(dev, 0x4f, 0x41); + + /* "5324" already is the default value of PCI ide device, cancel this pci write*/ + /*[william 20080124]: fix bug that can not boot ubuntu at the begnning time*/ + /* dev = 0; + dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0); + values = pci_read_config16(dev, 0xBA); + values &= ~0xffff; + values |= 0x5324; + pci_write_config16(dev, 0xBA, values);*/ +} + +/* most content of this function came from the cx700 port of coreboot. + Turn on the shadow of E-seg. + */ +static void enable_shadow_ram(void) +{ + uint8_t shadowreg; + /*changed the value from 0x2a to 0x3f. "read only" may block "write"? + and maybe in C-seg "write" will be needed?*/ + pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); + /* 0xf0000-0xfffff - ACPI tables */ + shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); + shadowreg |= 0x30; + pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); + /* 0xe0000-0xeffff - elfload? */ + /*in s3 resume process, wakeup.c, I use E-seg to hold the code(which can not locate in the area to be covered) that will copy 0-A-seg and F-seg from TOP-mem back to their normal location.*/ + pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); + +#if 0 + /* Enable shadow ram as normal dram */ + /* 0xc0000-0xcffff - VGA BIOS */ + pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a); + pci_write_config8(PCI_DEV(0, 0, 7), 0x61, 0x00); + /* 0xd0000-0xdffff - ?? */ + //pci_write_config8(PCI_DEV(0, 0, 3), 0x81, 0xff); + //pci_write_config8(PCI_DEV(0, 0, 7), 0x62, 0xff); + + /* Do it again for the vlink controller */ + shadowreg = pci_read_config8(PCI_DEV(0, 0, 7), 0x63); + shadowreg |= 0x30; + pci_write_config8(PCI_DEV(0, 0, 7), 0x63, shadowreg); +#endif +} + + +/*added this table 2008-11-28, +this table contains the value needed to be set before begin to init dram. +Note: REV_Bx should be checked for changes when porting a new board!!!!! */ +static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[]= { + //VT3409 no pcie + 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range + 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie + //0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control + // Set ROMSIP value by software + + /*0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 + 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 + 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 + 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 + 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl + 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl + 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit + 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status + 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset + 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset + 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status + 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status + 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group + 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group + 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group + 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) + 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 + 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 + 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB + 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD + 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) + 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) + 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) + 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3)*/ + + + // CPU Host Bus Control + 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 + //0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance + //0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK + 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK + 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access + //0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 + 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 + 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 + //0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL + //0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 + 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy + 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer + 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl + // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 + //0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 + 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 + 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 + 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 + + + // Set APIC and SMRAM + 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control + 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg + 0x00, 0xFF, 0x00, 0x00, 0x00,0x00, 0x00, 0x00 // End of the table +}; + +#define USE_VCP 1//0 means use DVP +#define USE_COM1 1 +#define USE_COM2 0 + +#define gCom1Base 0x3f8 +#define gCom2Base 0x2f8 +void EmbedComInit() +{ + u8 ByteVal; + u16 ComBase; + + //enable NB multiple function control + ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f); + ByteVal = ByteVal |0x01; + pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal); + + //VGA Enable + ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1); + ByteVal = ByteVal |0x80; + pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal); + + ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7); + ByteVal = ByteVal |0x08; + pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal); + + //Enable p2p IO/mem + ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4); + ByteVal = ByteVal |0x07; + pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal); + + //Turn on Graphic chip IO port port access + ByteVal = inb(0x3C3); + ByteVal = ByteVal |0x01; + outb(ByteVal,0x3C3); + + //Turn off Graphic chip Register protection + outb(0x10,0x3C4); + ByteVal = inb(0x3C5); + ByteVal = ByteVal |0x01; + outb(ByteVal,0x3C5); + + //south module pad share enable 0x3C5.78[7] + outb(0x78,0x3C4); + ByteVal = inb(0x3C5); + ByteVal = ByteVal |0x80; + outb(ByteVal,0x3C5); + + //enable UART Function multiplex with DVP or VCP pad D17F0Rx46[7,6] + ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46); + //multiplex with VCP + if(USE_VCP == 1) + ByteVal = (ByteVal & 0x3F) | 0x40; + //multiplex with DVP + else + ByteVal = (ByteVal & 0x3F) | 0xC0; + pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); + + + + //enable embeded com1 and com2 D17F0RxB0[5,4] + ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); + ByteVal = ByteVal & 0xcf; + //multiplex with VCP + if(USE_COM1==1) + ByteVal = ByteVal | 0x10; + if(USE_COM2==1) + ByteVal = ByteVal | 0x20; + pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal); + + if(USE_COM1 == 1) + ComBase = gCom1Base; + else + ComBase = gCom2Base; + +//noharddrive + + //set embeded com1 IO base = 0x3E8 + //D17F0RB4 + //ByteVal = 0xFD; + if(USE_COM1==1){ + ByteVal = (u8)((gCom1Base >> 3) |0x80); + pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); + ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); + ByteVal = (ByteVal&0xf0)|0x04; + pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); + } + + //set embeded com2 IO base = 0x2E8 + //D17F0RB5 + //ByteVal = 0xDD; + if(USE_COM2==1){ + ByteVal = (u8)((gCom2Base >> 3) |0x80); + pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); + ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); + ByteVal = (ByteVal&0x0f)|0x30; + pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); + } + + //no port 80 biger then 0x10 + + //disable interrupt + ByteVal = inb(ComBase + 3); + outb(ByteVal & 0x7F,ComBase + 3); + outb( 0x00,ComBase + 1); + + //set baudrate + ByteVal = inb(ComBase + 3); + outb( ByteVal | 0x80,ComBase + 3); + outb(0x01,ComBase); + outb(0x00,ComBase + 1 ); + + //set frame fromat + ByteVal = inb(ComBase + 3); + outb( ByteVal & 0x3F,ComBase + 3); + outb(0x03,ComBase + 3 ); + outb(0x00,ComBase + 2); + outb(0x00,ComBase + 4); + + //SOutput("Embeded com output\n"); + //while(1); +} + +/*cache_as_ram.inc jump to here +*/ +void amd64_main(unsigned long bist) +{ unsigned cpu_reset = 0; + u16 boot_mode; + u8 rambits; + + //device_t dev; + /* Enable multifunction for northbridge. These 4 lines(until console_init();) are the same with epia-cn port.*/ + pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); + EmbedComInit(); + //enable_vx800_serial(); + //uart_init(); + + +/* 1. D15F0 + +a) RxBAh = 71h + +b) RxBBh = 05h + +c) RxBEh = 71h + +d) RxBFh = 05h + +2. D17F0 + +a) RxA0h = 06h + +b) RxA1h = 11h + +c) RxA2h = 27h + +d) RxA3h = 32h + +e) Rx79h = 40h + +f) Rx72h = 27h + +g) Rx73h = 32h +*/ + + u8 Data8; + + jason_tsc_count_car(); + pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); + pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE, PCI_DEVICE_ID_VIA_VX855_IDE); + pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA); + pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC); + Data8=pci_read_config8(PCI_DEV(0, 0x11, 0),0x79); + Data8 &= ~0x40; + Data8 |=0x40; + pci_write_config8(PCI_DEV(0, 0x11, 0),0x79,Data8); + pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72, PCI_DEVICE_ID_VIA_VX855_LPC); + + console_init();//there are to function defination of console_init(), while the src/archi386/lib is the right one. + + /* decide if this is a s3 wakeup or a normal boot*/ + boot_mode=acpi_is_wakeup_early_via_vx800(); + /* 2008-11-27 add this, to transfer "cpu restart" to "cold boot" + When this boot is not a S3 resume, and PCI registers had been written, + then this must be a cpu restart(result of os reboot cmd), so we need a real "cold boot".*/ + jason_tsc_count_car(); + if((boot_mode!=3)&&(pci_read_config8(PCI_DEV(0, 0, 3), 0x80)!=0)) + {outb(6, 0xcf9);} /*x86 cold boot I/O cmd*/ + + /* this 2 lines is the same with epia-cn port.*/ + enable_smbus(); + jason_tsc_count_car(); + //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 doesn't need this + + if (bist == 0) { + //CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); + //print_debug("doing early_mtrr\r\n"); + //early_mtrr_init(); + } + + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + print_debug("Enabling mainboard devices\r\n"); + enable_mainboard_devices(); + + u8 Data; + device_t device; + /*2008-11-27 Get NB Chip revision from D0F4RxF6, revision will be used in via_pci_inittable*/ + device=PCI_DEV(0, 0, 4); + Data=pci_read_config8(device,0xf6); + print_debug("NB chip revision ="); + print_debug_hex8(Data); + print_debug("\r\n"); + /*2008-11-27, make NB ready before draminit*/ + via_pci_inittable(Data,mNbStage1InitTbl); + + /*2008-11-27 add this. + When resume from s3, draminit is skiped, so need to recovery any PCI register related to draminit. d0f3 didnt lose its Power during whole s3 time, so any register not belonging to d0f3 needs to be recovered .*/ +#if 1 + if (boot_mode==3) { + u8 i; + u8 ramregs[] = {0x43, 0x42, 0x41, 0x40}; + DRAM_SYS_ATTR DramAttr; + + print_debug("This is a S3 wakeup\r\n"); + + memset (&DramAttr, 0,sizeof (DRAM_SYS_ATTR)); + /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T*/ + DRAMDetect(&DramAttr); + + /*begin to get ram size, 43,42 41 40 contains the end address of last rank in ddr2-slot*/ + device=PCI_DEV(0, 0, 3); + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { + rambits = pci_read_config8(device, ramregs[i]); + if (rambits != 0) + break; + } + + DRAMDRDYSetting (&DramAttr); + + Data = 0x80;//this value is same with DevInit.c + pci_write_config8(PCI_DEV(0,0,4), 0xa3, Data); + pci_write_config8(PCI_DEV(0,17,7), 0x60, rambits<<2); + Data=pci_read_config8(MEMCTRL, 0x88); + pci_write_config8(PCI_DEV(0,17,7), 0xE5, Data); + + DRAMRegFinalValue(&DramAttr); //Just copy this function from draminit to here! + SetUMARam();//Just copy this function from draminit to here! + print_debug("Resume from S3, RAM init was ignored\r\n"); + } + else{ + ddr2_ram_setup(); + ram_check(0, 640 * 1024); + } +#endif + //ddr2_ram_setup(); + /*2008-11-27 this line is the same with cx700 port .*/ + enable_shadow_ram(); + + jason_tsc_count_car(); + /*2008-11-27 + For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty, + so before this happen, I need to backup the content of mem to top-mem. + I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c + */ +#if PAYLOAD_IS_SEABIOS==1 // + if(boot_mode==3){ + /* An Idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html + I want move the 1M data, I have to set some MTRRs myself.*/ + /*Setting mtrr before back memoy save s3 resume time about 0.14 seconds*/ + /*!!!!!!!!Since CAR stack uses cache, and we are using cache here, we must be careful, + 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) + 2 before stack switch, no use variable that have value set before this + 3 due to 2, take care of "cpu_reset", I directlly set it to ZERO. + */ + u32 memtop=*(u32*)WAKE_MEM_INFO; + u32 memtop1=*(u32*)WAKE_MEM_INFO-0x100000; + u32 memtop2=*(u32*)WAKE_MEM_INFO-0x200000; + u32 memtop3=*(u32*)WAKE_MEM_INFO- 64*1024-0x100000; + u32 memtop4=*(u32*)WAKE_MEM_INFO- 64*1024-0x100000+0xe0000; + /* __asm__ volatile ( + "movl $0x204, %%ecx\n\t" + "xorl %%edx, %%edx\n\t" + "movl %0,%%eax\n\t" + "orl $(0 | 6), %%eax\n\t" + "wrmsr\n\t" + + "movl $0x205, %%ecx\n\t" + "xorl %%edx, %%edx\n\t" + "movl $0x100000,%%eax\n\t" + "decl %%eax\n\t" + "notl %%eax\n\t" + "orl $(0 | 0x800), %%eax\n\t" + "wrmsr\n\t" + ::"g"(memtop2) + ); + __asm__ volatile ( + "movl $0x206, %%ecx\n\t" + "xorl %%edx, %%edx\n\t" + "movl %0,%%eax\n\t" + "orl $(0 | 6), %%eax\n\t" + "wrmsr\n\t" + + "movl $0x207, %%ecx\n\t" + "xorl %%edx, %%edx\n\t" + "movl $0x100000,%%eax\n\t" + "decl %%eax\n\t" + "notl %%eax\n\t" + "orl $(0 | 0x800), %%eax\n\t" + "wrmsr\n\t" + ::"g"(memtop1) + ); + __asm__ volatile ( + "movl $0x208, %ecx\n\t" + "xorl %edx, %edx\n\t" + "movl $0,%eax\n\t" + "orl $(0 | 6), %eax\n\t" + "wrmsr\n\t" + + "movl $0x209, %ecx\n\t" + "xorl %edx, %edx\n\t" + "movl $0x100000,%eax\n\t" + "decl %eax\n\t" + "notl %eax\n\t" + "orl $(0 | 0x800), %eax\n\t" + "wrmsr\n\t" + ); + */ + // WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c + // these two memcpy not not be enabled if set the MTRR around this two lines. + /*__asm__ volatile ( + "movl $0, %%esi\n\t" + "movl %0, %%edi\n\t" + "movl $0xa0000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"g"(memtop3) + ); + __asm__ volatile ( + "movl $0xe0000, %%esi\n\t" + "movl %0, %%edi\n\t" + "movl $0x20000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"g"(memtop4) + );*/ + print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n");//this can have function call, because no variable used before this + memcpy((unsigned char *)((*(u32*)WAKE_MEM_INFO) - 64*1024-0x100000),(unsigned char *)0,0xa0000); + memcpy((unsigned char *)((*(u32*)WAKE_MEM_INFO) - 64*1024-0x100000+0xe0000),(unsigned char *)0xe0000,0x20000); + + /* restore the MTRR previously modified. */ +/* __asm__ volatile ( + "wbinvd\n\t" + "xorl %edx, %edx\n\t" + "xorl %eax, %eax\n\t" + "movl $0x204, %ecx\n\t" + "wrmsr\n\t" + "movl $0x205, %ecx\n\t" + "wrmsr\n\t" + "movl $0x206, %ecx\n\t" + "wrmsr\n\t" + "movl $0x207, %ecx\n\t" + "wrmsr\n\t" + "movl $0x208, %ecx\n\t" + "wrmsr\n\t" + "movl $0x209, %ecx\n\t" + "wrmsr\n\t" + );*/ + } + #endif +/*2008-11-27 +the following code is copied from src\mainboard\tyan\s2735\cache_as_ram_auto.c +Only the code around CLEAR_FIRST_1M_RAM is changed. +Removed all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c" +the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, +and cpu/x86/car/cache_as_ram_post.c do not cache my $XIP_ROM_BASE+SIZE area. + +Uuse: #include "cpu/via/car/cache_as_ram_post.c". this version post.c have some diff withx86-version +*/ +#if 1 + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); +#if CONFIG_USE_INIT + printk_debug("v_esp=%08x\r\n", v_esp); +#else + print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); +#endif + } + +#endif +#if 1 + +cpu_reset_x: +// it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy +//stack +cpu_reset=0; +#if CONFIG_USE_INIT + printk_debug("cpu_reset = %08x\r\n",cpu_reset); +#else + print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); +#endif + + if(cpu_reset == 0) { + print_debug("Clearing initial memory region: "); + } + print_debug("No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + + +/* Cancel these lines, CLEAR_FIRST_1M_RAM cause the cpu/x86/car/cache_as_ram_post.c stop at somewhere + + if(cpu_reset==0) { +#define CLEAR_FIRST_1M_RAM 1 +#include "cpu/via/car/cache_as_ram_post.c" + } + else { +#undef CLEAR_FIRST_1M_RAM +#include "cpu/via/car/cache_as_ram_post.c" + } +*/ +#include "cpu/via/car/cache_as_ram_post.c" +//#include "cpu/x86/car/cache_as_ram_post.c" + __asm__ volatile ( + /* set new esp */ /* before _RAMBASE */ + "subl %0, %%ebp\n\t" + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n\t" + :"=a" (new_cpu_reset) + ); + + /* We can not go back any more, we lost old stack data in cache as ram*/ + if(new_cpu_reset==0) { + print_debug("Use Ram as Stack now - done\r\n"); + } else + { + print_debug("Use Ram as Stack now - \r\n"); + } +#if CONFIG_USE_INIT + printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset); +#else + print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); +#endif + jason_tsc_count_car(); + /*copy and execute coreboot_ram */ + copy_and_run(new_cpu_reset); + /* We will not return */ + } +#endif + + + print_debug("should not be here -\r\n"); + +} Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/chip.h 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config { + int nothing; +}; Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cmos.layout 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/dsdt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/dsdt.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/dsdt.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned char AmlCode_dsdt[] = +{ + 0x44,0x53,0x44,0x54,0x0F,0x3C,0x00,0x00, + /* Removed for lincense issue. See get_dsdt script. */ +}; Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,170 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include <../../../northbridge/via/vx800/vx800.h> + +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ + acpi_header_t *header =& (fadt->header); + + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, "VX800 ", 6); + memcpy(header->oem_table_id, "LNXBACPI", 8); + memcpy(header->asl_compiler_id, "LXB", 8); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = facs; + fadt->dsdt = dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 0x9; + + fadt->smi_cmd = VX800_ACPI_IO_BASE+0x2F; + fadt->acpi_enable = 0xA1; + fadt->acpi_disable = 0xA0; + + /* value 42F,A1,A0, if we dont want SMI, then set them to zero. + fadt->smi_cmd = 0x0; + fadt->acpi_enable = 0x0; + fadt->acpi_disable = 0x0; + */ + + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = VX800_ACPI_IO_BASE; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = VX800_ACPI_IO_BASE+0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x22;//to support cpu-c3 +// fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = VX800_ACPI_IO_BASE+0x8; + fadt->gpe0_blk = VX800_ACPI_IO_BASE+0x20; + fadt->gpe1_blk = VX800_ACPI_IO_BASE+0x50; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1;//to support cpu-c3 +// fadt->pm2_cnt_len = 0; + + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 4; + fadt->gpe1_base = 0x10; + fadt->cst_cnt = 0; + + fadt->p_lvl2_lat = 0x50; //this is the coreboot source + fadt->p_lvl3_lat = 0x320;// +// fadt->p_lvl2_lat = 0x80; // +// fadt->p_lvl3_lat = 0x800;// +// fadt->p_lvl2_lat = 0x1; // +// fadt->p_lvl3_lat = 0x23; + +// fadt->p_lvl2_lat = 0x200; //disable +// fadt->p_lvl3_lat = 0x2000; + + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; +// fadt->duty_width = 1; + fadt->duty_width = 4; + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x0; + fadt->flags = 0xa5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 4; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = VX800_ACPI_IO_BASE; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 2; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = VX800_ACPI_IO_BASE+0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + +// fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = 0; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 4; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = VX800_ACPI_IO_BASE+0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = VX800_ACPI_IO_BASE+0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,43 @@ +#!/bin/bash +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 One Laptop per Child, Association, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# Simple script to dump the factory ACPI DSDT and convert it to C +# Needs to be run as root on some systems, and always run on the target machine + +if [ ! iasl ] +then echo "Intel ASL Compiler required to recompile DSDT table" +fi + +if [ ! -f /proc/acpi/dsdt ] +then echo "Cannot find DSDT table, check that your kernel supports and uses ACPI" +fi + +cat /proc/acpi/dsdt > dsdt +if [ ! -f dsdt ] +then echo "Failed copying DSDT, please check your permissions" +fi + +iasl -d -vr -vs dsdt +iasl -tc -vr -vs dsdt.dsl +mv dsdt.hex dsdt.c +echo "Done, cleaning up" +rm -f dsdt dsdt.dsl dsdt.aml dsdt.hex +exit Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef GETPIR +#include "pirq_routing.h" +#else +#include +#endif + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*14, /* There can be total 14 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0xc20, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x8409, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc6, /* u8 checksum. This has to be set to some + //0xa0?? value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x08<<3)|0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + } +}; + +inline unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/mainboard.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("VIA EPIA-M700 Mainboard") +}; Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/ssdt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/ssdt.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/ssdt.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned char AmlCode_ssdt[] = +{ + 0x53,0x53,0x44,0x54,0xA7,0x01,0x00,0x00, /* 00000000 "SSDT...." */ + /* Removed for licese issue. */ +}; Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c 2009-06-05 23:02:43 UTC (rev 4342) @@ -0,0 +1,447 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Rudolf Marek + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a cop