[coreboot] [v2] r4331 - trunk/coreboot-v2/src/southbridge/amd/rs690

[svn at coreboot.org]

Author: zbao
Date: 2009-06-03 05:15:05 +0200 (Wed, 03 Jun 2009)
New Revision: 4331

Modified:
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c
Log:
Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming.
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c	2009-06-02 23:49:00 UTC (rev 4330)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c	2009-06-03 03:15:05 UTC (rev 4331)
@@ -148,7 +148,7 @@
 	/* waits until SB has trained to L0, poll for bit0-5 = 0x10 */
 	do {
 		reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
-		reg &= 0x1f;	/* remain LSB 5 bits */
+		reg &= 0x3f;	/* remain LSB [5:0] bits */
 	} while (LC_STATE_RECONFIG_GPPSB != reg);
 
 	/* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */