[coreboot] Raminit help
mylesgw at gmail.com
Tue Jun 9 19:16:18 CEST 2009
> > set_var_mtrr(0, 0x08000000, 0x10000000, MTRR_TYPE_WRBACK);
> Hm.. doesn't the base address need at least an alignment of size?
> Have you tried disabling caching completely for the area?
Not here, I did before. I was hoping that caching would avoid the alignment
issues I've been seeing.
> > // Try to force the values out of the cache.
> If you are trying to avoid the accesses from being cached, they need to
> cross a cache line.
I wasn't trying to cross a cache line. I was trying to write to the same
cache line enough times that it would force it to write it back.
> The above accesses would imho not cross a cache line, unless a cache
> line on opteron is as small as 8 byte, which I find hard to believe.
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