[coreboot] [Patch] Flashrom: board enable for Soyo SY-6BA+III.

[Luc Verhaegen]

Board enable for soyo sy-6ba+iii.

This board enable drops GPO26 on the southbridge (PIIX4). Since there
was another board raising GPO22 on the same southbridge, a general
routine was created reducing both board enables to a single line.

This routine does full gpo pin checking and filters out those which
are most likely in use already, enables dual-function gpo pins properly,
and then sets the relevant gpo line. It should be fully implemented for
all gpo setting on PIIX4, except when a supposed used gpo pin does happen
to be available for gpio.

The board itself predates proper subsystem id usage and can therefor not
be autodetected.

Signed-off-by: Luc Verhaegen <libv at skynet.be>
Index: board_enable.c
===================================================================
--- board_enable.c	(revision 602)
+++ board_enable.c	(working copy)
@@ -208,6 +208,78 @@
 }
 
 /**
+ * Helper function to raise/drop a given gpo line on intel PIIX4*
+ */
+static int intel_piix4_gpo_set(int gpo, int raise)
+{
+	struct pci_dev *dev;
+	uint32_t tmp, base;
+
+	dev = pci_dev_find(0x8086, 0x7110);	/* Intel PIIX4 ISA bridge */
+	if (!dev) {
+		fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n");
+		return -1;
+	}
+
+	/* sanity check */
+	if ((gpo < 0) || (gpo > 30)) {
+		fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
+		return -1;
+	}
+
+	/* these are dual function pins which are most likely in use already */
+	if (((gpo >= 1) && (gpo <= 7)) ||
+	    ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
+		fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
+		return -1;
+	}
+
+	/* dual function that need special enable. */
+	if ((gpo >= 22) && (gpo <= 26)) {
+		tmp = pci_read_long(dev, 0xB0); /* GENCFG */
+		switch (gpo) {
+		case 22: /* XBUS: XDIR#/GPO22 */
+		case 23: /* XBUS: XOE#/GPO23 */
+			tmp |= 0x10000000;
+			break;
+		case 24: /* RTCSS#/GPO24 */
+			tmp |= 0x20000000;
+			break;
+		case 25: /* RTCALE/GPO25 */
+			tmp |= 0x40000000;
+			break;
+		case 26: /* KBCSS#/GPO26 */
+			tmp |= 0x80000000;
+			break;
+		default:
+			fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
+			return -1;
+		}
+		pci_write_long(dev, 0xB0, tmp);
+	}
+
+	/* GPO {0,8,27,28,30} are always available. */
+
+	dev = pci_dev_find(0x8086, 0x7113);	/* Intel PIIX4 PM */
+	if (!dev) {
+		fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n");
+		return -1;
+	}
+
+	/* PM IO base */
+	base = pci_read_long(dev, 0x40) & 0x0000FFC0;
+
+	tmp = INL(base + 0x34); /* GPO register */
+	if (raise)
+		tmp |= 0x01 << gpo;
+	else
+		tmp |= ~(0x01 << gpo);
+	OUTL(tmp, base + 0x34);
+
+	return 0;
+}
+
+/**
  * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
  *
  * We don't need to do this when using coreboot, GPIO15 is never lowered there.
@@ -413,18 +485,7 @@
  */
 static int board_epox_ep_bx3(const char *name)
 {
-	uint8_t tmp;
-
-	/* Raise GPIO22. */
-	tmp = INB(0x4036);
-	OUTB(tmp, 0xEB);
-
-	tmp |= 0x40;
-
-	OUTB(tmp, 0x4036);
-	OUTB(tmp, 0xEB);
-
-	return 0;
+	return intel_piix4_gpo_set(22, 1);
 }
 
 /**
@@ -661,6 +722,16 @@
 }
 
 /**
+ * Suited for Soyo SY-6BA+III: i440BX + PIIX4.
+ * Might also work on other SY-6BA+ variations, as there is no superio poking.
+ */
+static int board_soyo_sy_6ba_plus_iii(const char *name)
+{
+	return intel_piix4_gpo_set(26, 0);
+}
+
+
+/**
  * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
  */
 static int board_soyo_sy_7vca(const char *name)
@@ -747,6 +818,7 @@
 	{0x1106, 0x0571, 0x1462, 0x7120,       0,      0,      0,      0, "msi",        "kt4v",        "MSI",         "MS-6712 (KT4V)",     board_msi_kt4v},
 	{0x13f6, 0x0111, 0x1462, 0x5900,  0x1106, 0x3177, 0x1106,      0, "msi",        "kt4ultra",    "MSI",         "MS-6590 (KT4 Ultra)",board_msi_kt4v},
 	{0x8086, 0x2658, 0x1462, 0x7046,  0x1106, 0x3044, 0x1462, 0x046d, NULL,         NULL,          "MSI",         "MS-7046",            ich6_gpio19_raise},
+	{0x8086, 0x7190,      0,      0,  0x8086, 0x7110,      0,      0, "soyo",       "sy-6ba+iii",  "Soyo",        "SY-6BA+III",         board_soyo_sy_6ba_plus_iii},
 	{0x1106, 0x3038, 0x0925, 0x1234,  0x1106, 0x3058, 0x15DD, 0x7609, NULL,         NULL,          "Soyo",        "SY-7VCA",            board_soyo_sy_7vca},
 	{0x8086, 0x1076, 0x8086, 0x1176,  0x1106, 0x3059, 0x10f1, 0x2498, NULL,         NULL,          "Tyan",        "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
 	{0x1106, 0x0314, 0x1106, 0xaa08,  0x1106, 0x3227, 0x1106, 0xAA08, NULL,         NULL,          "VIA",         "EPIA-CN",            board_via_epia_sp},