[coreboot] Does the fam10 code work now?
Zheng.Bao at amd.com
Fri Jun 19 05:07:54 CEST 2009
1. The processor I work on is Socket AM2r2. Is it supported?
2. The board I work on is Fam10(AM2r2)+RS780+SB700, somehow like
dbm690t. what is the configuration in Option.lb. HT_CHAIN_UNITID_BASE?
HT_CHAIN_END_UNITID_BASE? I am still confused about these settings.
3. If the HT can not be configured to HT3 mode, can the MCT be set at
From: Marc Jones [mailto:marcj303 at gmail.com]
Sent: Friday, June 19, 2009 12:15 AM
To: Bao, Zheng
Cc: coreboot at coreboot.org
Subject: Re: Does the fam10 code work now?
On Wed, Jun 17, 2009 at 9:00 PM, Bao, Zheng<Zheng.Bao at amd.com> wrote:
> Now I am trying the coreboot for family 10. But I found that the
> linkOptimization()->selectOptimalWidthAndFrequency() in h2finit.c can
> not set the "Optimized" width and frequency, because the
> AMD_CB_Cpu2RCBLimits is NULL in amd_ht_init() in ht_wrapper.c. This
> causes the HT bus Configuration can not be done. According to the
> comment in mct_d.c, the requirement of mctSutoInitMCT_D() can not be
> Does it mean currently the family 10 code can not work at all?
There are several people that have working (at varying levels) of
Fam10 systems. So, most stuff does work. We knocked out a few bugs
this week that should help more people get their configurations
The AMD_CB_Cpu2RCBLimits is NULL because coreboot doesn't limit the HT
frequency. The limit would be an upper limit not lower, since HT all
start at 200MHz.
The requirement in mctAutoInitMCT_D is that HT init be done and that
includes the reset. coreboot should fail in the HT init phase if it
can't be initialized and you wouldn't get to mctAutoInitMCT_D.
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