[coreboot] GSOC USBROM linking problem

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Fri Jun 19 11:30:15 CEST 2009

On 17.06.2009 19:18, ron minnich wrote:
> On Wed, Jun 17, 2009 at 10:15 AM, Marc Jones<marcj303 at gmail.com> wrote:
>> The code is a PCI option ROM that can be copied and run at some
>> arbitrary location between 0xC0000 and 0x100000. For 16bit code the
>> segment would be loaded and there is no problem. I don't know the
>> right way to do this for 32bit flat mode code.
> I think we need to seek a common solution, and after discussion with
> segher from a while back I think -fpic and -fpie as we do it in v3 are
> rather questionable.

-fpic/-fpie may not be an universally preferred solution, but if GCC
developers ever decide to drop support for it, we can still move to
v3 initram is a bit of a special case because it is PIC calling non-PIC.
As far as I can see, GDT trickery would not work for such a case.

> What we should look to do is a run command which sets a new entry in
> the gdt and does a ljmp which sets CS to that entry. Then we link with
> that code to run at 0. This is what FILO does and it works well.

As long as the code does not have to call outside code, using the GDT
may indeed be the best option.



More information about the coreboot mailing list