[coreboot] [flashrom] r613 - trunk

[svn at coreboot.org]

Author: uwe
Date: 2009-06-19 17:54:39 +0200 (Fri, 19 Jun 2009)
New Revision: 613

Modified:
   trunk/flashchips.c
   trunk/flashchips.h
   trunk/satasii.c
Log:
Add support for the AMD Am29F010A/B chips.

Also, add support for the Silicon Image 3112(A) SATA controller.

Both have been tested by Andrew Morgan <ziltro at ziltro.com> on hardware
and work fine.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Andrew Morgan <ziltro at ziltro.com>



Modified: trunk/flashchips.c
===================================================================
--- trunk/flashchips.c	2009-06-19 14:22:16 UTC (rev 612)
+++ trunk/flashchips.c	2009-06-19 15:54:39 UTC (rev 613)
@@ -41,6 +41,22 @@
 
 	{
 		.vendor		= "AMD",
+		.name		= "Am29F010A/B",
+		.bustype	= CHIP_BUSTYPE_PARALLEL,
+		.manufacture_id	= AMD_ID,
+		.model_id	= AM_29F010B,	/* Same as Am29F010A */
+		.total_size	= 128,
+		.page_size	= 16 * 1024,
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_29f040b,
+		.probe_timing	= TIMING_FIXME,
+		.erase		= erase_29f040b,
+		.write		= write_pm29f002,
+		.read		= read_memmapped,
+	},
+
+	{
+		.vendor		= "AMD",
 		.name		= "Am29F002(N)BB",
 		.bustype	= CHIP_BUSTYPE_NONSPI,
 		.manufacture_id	= AMD_ID,

Modified: trunk/flashchips.h
===================================================================
--- trunk/flashchips.h	2009-06-19 14:22:16 UTC (rev 612)
+++ trunk/flashchips.h	2009-06-19 15:54:39 UTC (rev 613)
@@ -39,6 +39,7 @@
 #define ALLIANCE_ID		0x52	/* Alliance Semiconductor */
 
 #define AMD_ID			0x01	/* AMD */
+#define AM_29F010B		0x20	/* Same as Am29F010A */
 #define AM_29F002BT		0xB0
 #define AM_29F002BB		0x34
 #define AM_29F040B		0xA4

Modified: trunk/satasii.c
===================================================================
--- trunk/satasii.c	2009-06-19 14:22:16 UTC (rev 612)
+++ trunk/satasii.c	2009-06-19 15:54:39 UTC (rev 613)
@@ -35,6 +35,7 @@
 
 struct pcidev_status satas_sii[] = {
 	{0x1095, 0x0680, PCI_OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"},
+	{0x1095, 0x3112, PCI_OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"},
 	{0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"},
 	{0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"},
 	{0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},