[coreboot] [flashrom] getting SST SST49LF020A working

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Fri Jun 26 19:19:53 CEST 2009

Hi Simon,

thank you for your report.

On 10.06.2009 15:01, Simon Wunderlich wrote:
> we are using flashrom to flash our bios from the running linux system.
> The SST SST49LF020A is currently in state "untested" in on your Wiki. In the
> source code, a page size of 16 * 1024
> is configured, which is not correct for this chip (WRITE and ERASE fails). I
> could see in the hexdump that the regions
> 0x1000 - 0x1FFF, 0x3000 - 0x3FFFF, 0x5000 - 0x5FFFF ... have not been
> erased.
> After changing the page size to 4 * 1024 in flashchips.c, writing and
> erasing works fine. Reading also worked with the
> wrong page size. I guess PROBE works fine too since the chip is detected.
> Hope that helps you to complete your list of supported chips. :)

Can you please try the attached patch?
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

If it works, can you respond with a line saying
Acked-by: Simon Wunderlich <simon.wunderlich at saxnet.de>



-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: flashrom_sst49lf020a.diff
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090626/1530a397/attachment.ksh>

More information about the coreboot mailing list