[coreboot] [v2] r4381 - in trunk/coreboot-v2: documentation documentation/RFC src/arch/i386 src/arch/i386/boot src/arch/i386/include/arch src/arch/i386/init src/arch/i386/lib src/arch/i386/smp src/arch/ppc/boot src/arch/ppc/include/arch src/arch/ppc/init src/arch/ppc/lib src/boot src/config src/console src/cpu/amd/car src/cpu/amd/dualcore src/cpu/amd/model_10xxx src/cpu/amd/model_fxx src/cpu/amd/model_gx2 src/cpu/amd/model_lx src/cpu/amd/mtrr src/cpu/amd/quadcore src/cpu/amd/socket_AM2 src/cpu/amd/socket_F src/cpu/amd/socket_F_1207 src/cpu/amd/socket_S1G1 src/cpu/emulation/qemu-x86 src/cpu/intel/model_6ex src/cpu/intel/model_6fx src/cpu/intel/model_f0x src/cpu/intel/model_f1x src/cpu/intel/model_f2x src/cpu/intel/model_f3x src/cpu/intel/model_f4x src/cpu/ppc/mpc74xx src/cpu/ppc/ppc4xx src/cpu/ppc/ppc7xx src/cpu/ppc/ppc970 src/cpu/via/car src/cpu/x86/16bit src/cpu/x86/32bit src/cpu/x86/car src/cpu/x86/lapic src/cpu/x86/mtrr src/cpu/x86/pae src/cpu/x86/smm src/cpu/x86/tsc src/devices src/drivers/generic/debug src/drivers/i2c/adm1026 src/drivers/pci/onboard src/include src/include/console src/include/cpu/amd src/include/device src/include/part src/include/pc80 src/include/x86emu src/lib src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/norwich src/mainboard/amd/pistachio src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/artecgroup/dbe61 src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/asus/p2b src/mainboard/asus/p2b-d src/mainboard/asus/p2b-ds src/mainboard/asus/p2b-f src/mainboard/asus/p3b-f src/mainboard/axus/tc320 src/mainboard/azza/pt-6ibd src/mainboard/bcom/winnet100 src/mainboard/bcom/winnetp680 src/mainboard/biostar/m6tba src/mainboard/broadcom/blast src/mainboard/compaq/deskpro_en_sff_p600 src/mainboard/dell/s1850 src/mainboard/digitallogic/adl855pc src/mainboard/digitallogic/msm586seg src/mainboard/digitallogic/msm800sev src/mainboard/eaglelion/5bcm src/mainboard/embeddedplanet/ep405pc src/mainboard/emulation/qemu-x86 src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli src/mainboard/hp/dl145_g3 src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/iei/juki-511p src/mainboard/iei/nova4899r src/mainboard/iei/pcisa-lx-800-r10 src/mainboard/intel/jarrell src/mainboard/intel/mtarvon src/mainboard/intel/truxton src/mainboard/intel/xe7501devkit src/mainboard/iwill/dk8_htx src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x src/mainboard/jetway/j7f24 src/mainboard/kontron/986lcd-m src/mainboard/lippert/frontrunner src/mainboard/lippert/roadrunner-lx src/mainboard/lippert/spacerunner-lx src/mainboard/motorola/sandpoint src/mainboard/motorola/sandpointx3_altimus_mpc7410 src/mainboard/msi/ms6119 src/mainboard/msi/ms6147 src/mainboard/msi/ms6178 src/mainboard/msi/ms7135 src/mainboard/msi/ms7260 src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/nec/powermate2000 src/mainboard/newisys/khepri src/mainboard/nvidia/l1_2pvv src/mainboard/olpc/btest src/mainboard/olpc/rev_a src/mainboard/pcengines/alix1c src/mainboard/rca/rm4100 src/mainboard/soyo/sy-6ba-plus-iii src/mainboard/sunw/ultra40 src/mainboard/supermicro/h8dme src/mainboard/supermicro/h8dmr src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion/tim8690 src/mainboard/technologic/ts5300 src/mainboard/televideo/tc7020 src/mainboard/thomson/ip1000 src/mainboard/totalimpact/briq src/mainboard/tyan/s1846 src/mainboard/tyan/s2735 src/mainboard/tyan/s2850 src/mainboard/tyan/s2875 src/mainboard/tyan/s2880 src/mainboard/tyan/s2881 src/mainboard/tyan/s2882 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/mainboard/tyan/s2912 src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880 src/mainboard/tyan/s4882 src/mainboard/via/epia src/mainboard/via/epia-cn src/mainboard/via/epia-m src/mainboard/via/epia-m700 src/mainboard/via/pc2500e src/mainboard/via/vt8454c src/northbridge/amd/amdfam10 src/northbridge/amd/amdht src/northbridge/amd/amdk8 src/northbridge/amd/gx1 src/northbridge/amd/gx2 src/northbridge/amd/lx src/northbridge/ibm/cpc710 src/northbridge/intel/e7501 src/northbridge/intel/e7520 src/northbridge/intel/e7525 src/northbridge/intel/i3100 src/northbridge/intel/i440bx src/northbridge/intel/i82810 src/northbridge/intel/i82830 src/northbridge/intel/i855gme src/northbridge/intel/i855pm src/northbridge/intel/i945 src/northbridge/via/cn700 src/northbridge/via/cx700 src/northbridge/via/vt8601 src/northbridge/via/vt8623 src/northbridge/via/vx800 src/northbridge/via/vx800/examples src/pc80 src/ram src/southbridge/amd/amd8111 src/southbridge/amd/cs5530 src/southbridge/amd/cs5536 src/southbridge/amd/sb600 src/southbridge/broadcom/bcm5785 src/southbridge/intel/i82801ca src/southbridge/intel/i82801dbm src/southbridge/intel/i82801er src/southbridge/intel/i82801gx src/southbridge/intel/i82801xx src/southbridge/nvidia/ck804 src/southbridge/nvidia/mcp55 src/southbridge/sis/sis966 src/southbridge/via/k8t890 src/southbridge/via/vt8237r src/stream src/superio/ite/it8716f targets/a-trend/atc-6220 targets/a-trend/atc-6240 targets/abit/be6-ii_v2_0 targets/advantech/pcm-5820 targets/amd/db800 targets/amd/dbm690t targets/amd/norwich targets/amd/pistachio targets/amd/rumba targets/amd/serengeti_cheetah targets/amd/serengeti_cheetah_fam10 targets/arima/hdama targets/artecgroup/dbe61 targets/asi/mb_5blgp targets/asi/mb_5blmp targets/asus/a8n_e targets/asus/a8v-e_se targets/asus/m2v-mx_se targets/asus/mew-am targets/asus/mew-vm targets/asus/p2b targets/asus/p2b-d targets/asus/p2b-ds targets/asus/p2b-f targets/asus/p3b-f targets/axus/tc320 targets/azza/pt-6ibd targets/bcom/winnet100 targets/bcom/winnetp680 targets/biostar/m6tba targets/broadcom/blast targets/compaq/deskpro_en_sff_p600 targets/dell/s1850 targets/digitallogic/adl855pc targets/digitallogic/msm586seg targets/digitallogic/msm800sev targets/eaglelion/5bcm targets/embeddedplanet/ep405pc targets/emulation/qemu-x86 targets/gigabyte/ga-6bxc targets/gigabyte/ga_2761gxdk targets/gigabyte/m57sli targets/hp/dl145_g3 targets/ibm/e325 targets/ibm/e326 targets/iei/juki-511p targets/iei/nova4899r targets/iei/pcisa-lx-800-r10 targets/intel/mtarvon targets/intel/truxton targets/intel/xe7501devkit targets/iwill/dk8_htx targets/iwill/dk8s2 targets/iwill/dk8x targets/jetway/j7f24 targets/kontron/986lcd-m targets/lippert/frontrunner targets/lippert/roadrunner-lx targets/lippert/spacerunner-lx targets/momentum/apache targets/motorola/sandpoint targets/msi/ms6119 targets/msi/ms6147 targets/msi/ms6178 targets/msi/ms7135 targets/msi/ms7260 targets/msi/ms9185 targets/msi/ms9282 targets/nec/powermate2000 targets/newisys/khepri targets/nvidia/l1_2pvv targets/olpc/btest targets/olpc/rev_a targets/pcengines/alix1c targets/rca/rm4100 targets/soyo/sy-6ba-plus-iii targets/sunw/ultra40 targets/supermicro/h8dme targets/supermicro/h8dmr targets/technexion/tim8690 targets/technologic/ts5300 targets/televideo/tc7020 targets/thomson/ip1000 targets/totalimpact/briq targets/tyan/s1846 targets/tyan/s2735 targets/tyan/s2850 targets/tyan/s2875 targets/tyan/s2880 targets/tyan/s2881 targets/tyan/s2882 targets/tyan/s2885 targets/tyan/s2891 targets/tyan/s2892 targets/tyan/s2895 targets/tyan/s2912 targets/tyan/s2912_fam10 targets/tyan/s4880 targets/tyan/s4882 targets/via/epia targets/via/epia-cn targets/via/epia-m targets/via/epia-m700 targets/via/pc2500e targets/via/vt8454c util/abuild util/analysis util/cbfstool util/cbfstool/tools util/newconfig util/options util/romcc/tests util/vgabios util/vgabios/x86emu/include util/vgabios/x86emu/include/x86emu util/vgabios/x86emu/src/x86emu util/vgabios/x86emu/src/x86emu/x86emu

svn at coreboot.org svn at coreboot.org
Tue Jun 30 17:17:50 CEST 2009


Author: stepan
Date: 2009-06-30 17:17:49 +0200 (Tue, 30 Jun 2009)
New Revision: 4381

Modified:
   trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex
   trunk/coreboot-v2/documentation/RFC/config.tex
   trunk/coreboot-v2/src/arch/i386/Config.lb
   trunk/coreboot-v2/src/arch/i386/boot/Config.lb
   trunk/coreboot-v2/src/arch/i386/boot/acpi.c
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c
   trunk/coreboot-v2/src/arch/i386/boot/tables.c
   trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h
   trunk/coreboot-v2/src/arch/i386/include/arch/cpu.h
   trunk/coreboot-v2/src/arch/i386/include/arch/pci_ops.h
   trunk/coreboot-v2/src/arch/i386/include/arch/pciconf.h
   trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h
   trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h
   trunk/coreboot-v2/src/arch/i386/init/car.S
   trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
   trunk/coreboot-v2/src/arch/i386/init/ldscript.lb
   trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb
   trunk/coreboot-v2/src/arch/i386/init/ldscript_cbfs.lb
   trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb
   trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb
   trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb
   trunk/coreboot-v2/src/arch/i386/lib/Config.lb
   trunk/coreboot-v2/src/arch/i386/lib/console_printk.c
   trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds
   trunk/coreboot-v2/src/arch/i386/lib/id.inc
   trunk/coreboot-v2/src/arch/i386/lib/id.lds
   trunk/coreboot-v2/src/arch/i386/lib/pci_ops_conf1.c
   trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c
   trunk/coreboot-v2/src/arch/i386/lib/printk_init.c
   trunk/coreboot-v2/src/arch/i386/smp/Config.lb
   trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c
   trunk/coreboot-v2/src/arch/ppc/include/arch/cpu.h
   trunk/coreboot-v2/src/arch/ppc/include/arch/io.h
   trunk/coreboot-v2/src/arch/ppc/include/arch/pirq_routing.h
   trunk/coreboot-v2/src/arch/ppc/init/crt0.S.lb
   trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb
   trunk/coreboot-v2/src/arch/ppc/lib/pci_dev.c
   trunk/coreboot-v2/src/arch/ppc/lib/printk_init.c
   trunk/coreboot-v2/src/boot/filo.c
   trunk/coreboot-v2/src/boot/hardwaremain.c
   trunk/coreboot-v2/src/config/Config.lb
   trunk/coreboot-v2/src/config/Options.lb
   trunk/coreboot-v2/src/config/coreboot_apc.ld
   trunk/coreboot-v2/src/config/coreboot_ram.ld
   trunk/coreboot-v2/src/config/failovercalculation.lb
   trunk/coreboot-v2/src/config/nofailovercalculation.lb
   trunk/coreboot-v2/src/console/console.c
   trunk/coreboot-v2/src/console/printk.c
   trunk/coreboot-v2/src/console/uart8250_console.c
   trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc
   trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
   trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
   trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c
   trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c
   trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c
   trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c
   trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb
   trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c
   trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c
   trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c
   trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
   trunk/coreboot-v2/src/cpu/amd/model_fxx/powernow_acpi.c
   trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c
   trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c
   trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc
   trunk/coreboot-v2/src/cpu/amd/model_lx/syspreinit.c
   trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c
   trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c
   trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c
   trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c
   trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb
   trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
   trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb
   trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc
   trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c
   trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb
   trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc
   trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c
   trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb
   trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb
   trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb
   trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb
   trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb
   trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb
   trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/cache.S
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/ppc4xx.inc
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/sdram.c
   trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb
   trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc
   trunk/coreboot-v2/src/cpu/ppc/ppc970/Config.lb
   trunk/coreboot-v2/src/cpu/via/car/cache_as_ram.inc
   trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c
   trunk/coreboot-v2/src/cpu/x86/16bit/reset16.lds
   trunk/coreboot-v2/src/cpu/x86/32bit/reset32.lds
   trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc
   trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram_post.c
   trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
   trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
   trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c
   trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c
   trunk/coreboot-v2/src/cpu/x86/smm/Config.lb
   trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c
   trunk/coreboot-v2/src/cpu/x86/smm/smmrelocate.S
   trunk/coreboot-v2/src/cpu/x86/tsc/Config.lb
   trunk/coreboot-v2/src/devices/device_util.c
   trunk/coreboot-v2/src/devices/hypertransport.c
   trunk/coreboot-v2/src/devices/pci_device.c
   trunk/coreboot-v2/src/devices/pci_ops.c
   trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c
   trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c
   trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c
   trunk/coreboot-v2/src/include/assert.h
   trunk/coreboot-v2/src/include/console/console.h
   trunk/coreboot-v2/src/include/console/loglevel.h
   trunk/coreboot-v2/src/include/cpu/amd/model_fxx_rev.h
   trunk/coreboot-v2/src/include/device/pci_ops.h
   trunk/coreboot-v2/src/include/part/fallback_boot.h
   trunk/coreboot-v2/src/include/part/hard_reset.h
   trunk/coreboot-v2/src/include/part/init_timer.h
   trunk/coreboot-v2/src/include/part/watchdog.h
   trunk/coreboot-v2/src/include/pc80/mc146818rtc.h
   trunk/coreboot-v2/src/include/x86emu/fpu_regs.h
   trunk/coreboot-v2/src/include/x86emu/regs.h
   trunk/coreboot-v2/src/include/x86emu/x86emu.h
   trunk/coreboot-v2/src/lib/fallback_boot.c
   trunk/coreboot-v2/src/lib/uart8250.c
   trunk/coreboot-v2/src/lib/version.c
   trunk/coreboot-v2/src/lib/xmodem.c
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/irq_tables.c
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/irq_tables.c
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/irq_tables.c
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/irq_tables.c
   trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
   trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/mptable.c
   trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
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   trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb
   trunk/coreboot-v2/targets/iwill/dk8x/Config.lb
   trunk/coreboot-v2/targets/jetway/j7f24/Config-abuild.lb
   trunk/coreboot-v2/targets/jetway/j7f24/Config.lb
   trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb
   trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb
   trunk/coreboot-v2/targets/lippert/frontrunner/Config.lb
   trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb
   trunk/coreboot-v2/targets/lippert/spacerunner-lx/Config.lb
   trunk/coreboot-v2/targets/momentum/apache/Config.lb
   trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb
   trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb.ide_stream
   trunk/coreboot-v2/targets/msi/ms6119/Config.lb
   trunk/coreboot-v2/targets/msi/ms6147/Config.lb
   trunk/coreboot-v2/targets/msi/ms6178/Config.lb
   trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb
   trunk/coreboot-v2/targets/msi/ms7135/Config.lb
   trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb
   trunk/coreboot-v2/targets/msi/ms7260/Config.lb
   trunk/coreboot-v2/targets/msi/ms9185/Config-abuild.lb
   trunk/coreboot-v2/targets/msi/ms9185/Config.lb
   trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb
   trunk/coreboot-v2/targets/msi/ms9282/Config.lb
   trunk/coreboot-v2/targets/nec/powermate2000/Config.lb
   trunk/coreboot-v2/targets/newisys/khepri/Config.lb
   trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb
   trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb
   trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb.kernel
   trunk/coreboot-v2/targets/olpc/btest/Config.lb
   trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb
   trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb
   trunk/coreboot-v2/targets/olpc/rev_a/Config.kernel.lb
   trunk/coreboot-v2/targets/olpc/rev_a/Config.lb
   trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb
   trunk/coreboot-v2/targets/rca/rm4100/Config-abuild.lb
   trunk/coreboot-v2/targets/rca/rm4100/Config.lb
   trunk/coreboot-v2/targets/soyo/sy-6ba-plus-iii/Config.lb
   trunk/coreboot-v2/targets/sunw/ultra40/Config.lb
   trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb
   trunk/coreboot-v2/targets/supermicro/h8dme/Config-lab.lb
   trunk/coreboot-v2/targets/supermicro/h8dme/Config.lb
   trunk/coreboot-v2/targets/supermicro/h8dme/Config.lb.kernel
   trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb
   trunk/coreboot-v2/targets/supermicro/h8dmr/Config-lab.lb
   trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb
   trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb.kernel
   trunk/coreboot-v2/targets/technexion/tim8690/Config-abuild.lb
   trunk/coreboot-v2/targets/technexion/tim8690/Config.lb
   trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb
   trunk/coreboot-v2/targets/technologic/ts5300/Config.lb
   trunk/coreboot-v2/targets/televideo/tc7020/Config.lb
   trunk/coreboot-v2/targets/thomson/ip1000/Config-abuild.lb
   trunk/coreboot-v2/targets/thomson/ip1000/Config.lb
   trunk/coreboot-v2/targets/totalimpact/briq/Config.lb
   trunk/coreboot-v2/targets/tyan/s1846/Config.lb
   trunk/coreboot-v2/targets/tyan/s2735/Config.lb
   trunk/coreboot-v2/targets/tyan/s2850/Config.lb
   trunk/coreboot-v2/targets/tyan/s2875/Config.lb
   trunk/coreboot-v2/targets/tyan/s2880/Config.lb
   trunk/coreboot-v2/targets/tyan/s2881/Config-lab.lb
   trunk/coreboot-v2/targets/tyan/s2881/Config.lb
   trunk/coreboot-v2/targets/tyan/s2882/Config-lab.lb
   trunk/coreboot-v2/targets/tyan/s2882/Config.lb
   trunk/coreboot-v2/targets/tyan/s2885/Config.lb
   trunk/coreboot-v2/targets/tyan/s2891/Config-abuild.lb
   trunk/coreboot-v2/targets/tyan/s2891/Config-lab.lb
   trunk/coreboot-v2/targets/tyan/s2891/Config.lb
   trunk/coreboot-v2/targets/tyan/s2891/Config.lb.com2
   trunk/coreboot-v2/targets/tyan/s2892/Config-abuild.lb
   trunk/coreboot-v2/targets/tyan/s2892/Config-lab.lb
   trunk/coreboot-v2/targets/tyan/s2892/Config.lb
   trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb
   trunk/coreboot-v2/targets/tyan/s2895/Config-lab.lb
   trunk/coreboot-v2/targets/tyan/s2895/Config.lb
   trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb
   trunk/coreboot-v2/targets/tyan/s2912/Config.lb
   trunk/coreboot-v2/targets/tyan/s2912/Config.lb.kernel
   trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb
   trunk/coreboot-v2/targets/tyan/s2912_fam10/Config.lb
   trunk/coreboot-v2/targets/tyan/s2912_fam10/Config.lb.kernel
   trunk/coreboot-v2/targets/tyan/s4880/Config.lb
   trunk/coreboot-v2/targets/tyan/s4882/Config.lb
   trunk/coreboot-v2/targets/via/epia-cn/Config-abuild.lb
   trunk/coreboot-v2/targets/via/epia-cn/Config.lb
   trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb
   trunk/coreboot-v2/targets/via/epia-m/Config.512kflash.lb
   trunk/coreboot-v2/targets/via/epia-m/Config.etherboot.lb
   trunk/coreboot-v2/targets/via/epia-m/Config.filo.lb
   trunk/coreboot-v2/targets/via/epia-m/Config.lb
   trunk/coreboot-v2/targets/via/epia-m/Config.vga.filo
   trunk/coreboot-v2/targets/via/epia-m700/Config.lb
   trunk/coreboot-v2/targets/via/epia/Config.512kflash.lb
   trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb
   trunk/coreboot-v2/targets/via/epia/Config.filo.lb
   trunk/coreboot-v2/targets/via/epia/Config.ituner.filo.lb
   trunk/coreboot-v2/targets/via/epia/Config.lb
   trunk/coreboot-v2/targets/via/pc2500e/Config-abuild.lb
   trunk/coreboot-v2/targets/via/pc2500e/Config.lb
   trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb
   trunk/coreboot-v2/targets/via/vt8454c/Config.lb
   trunk/coreboot-v2/util/abuild/abuild
   trunk/coreboot-v2/util/analysis/Makefile
   trunk/coreboot-v2/util/cbfstool/Makefile
   trunk/coreboot-v2/util/cbfstool/tools/Makefile
   trunk/coreboot-v2/util/newconfig/config.g
   trunk/coreboot-v2/util/options/build_opt_tbl.c
   trunk/coreboot-v2/util/romcc/tests/hello_world.c
   trunk/coreboot-v2/util/romcc/tests/hello_world1.c
   trunk/coreboot-v2/util/romcc/tests/hello_world2.c
   trunk/coreboot-v2/util/romcc/tests/raminit_test.c
   trunk/coreboot-v2/util/romcc/tests/raminit_test1.c
   trunk/coreboot-v2/util/romcc/tests/raminit_test2.c
   trunk/coreboot-v2/util/romcc/tests/simple_test.c
   trunk/coreboot-v2/util/romcc/tests/simple_test1.c
   trunk/coreboot-v2/util/romcc/tests/simple_test20.c
   trunk/coreboot-v2/util/romcc/tests/simple_test27.c
   trunk/coreboot-v2/util/romcc/tests/simple_test4.c
   trunk/coreboot-v2/util/vgabios/helper_mem.c
   trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu.h
   trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/fpu_regs.h
   trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/regs.h
   trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/debug.c
   trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/decode.c
   trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/fpu.c
   trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/makefile
   trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/ops.c
   trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/x86emu/debug.h
Log:
This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex
===================================================================
--- trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex	2009-06-30 15:17:49 UTC (rev 4381)
@@ -286,7 +286,7 @@
 All local configuration variables have to be declared before they can be
 used. Example:
 \begin{verbatim}
-        uses ROM_IMAGE_SIZE
+        uses CONFIG_ROM_IMAGE_SIZE
 \end{verbatim}
 
 \textbf{NOTE:} Only configuration variables known to the configuration
@@ -303,20 +303,20 @@
 Example:
 
 \begin{verbatim}
-        default ROM_IMAGE_SIZE=0x10000
+        default CONFIG_ROM_IMAGE_SIZE=0x10000
 \end{verbatim}
 
 It is also possible to assign the value of one configuration variable to
 another one, i.e.:
 
 \begin{verbatim}
-        default FALLBACK_SIZE=ROM_SIZE
+        default CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
 \end{verbatim}
 
 Also, simple expressions are allowed:
 
 \begin{verbatim}
-        default FALLBACK_SIZE=(ROM_SIZE -  NORMAL_SIZE)
+        default CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE -  NORMAL_SIZE)
 \end{verbatim}
 
 If an option contains a string, this string has to be protected with
@@ -365,8 +365,8 @@
 
 \begin{verbatim}
 romimage "normal"
-        option USE_FALLBACK_IMAGE=0
-        option ROM_IMAGE_SIZE=0x10000
+        option CONFIG_USE_FALLBACK_IMAGE=0
+        option CONFIG_ROM_IMAGE_SIZE=0x10000
         option COREBOOT_EXTRA_VERSION=".0Normal"
         mainboard amd/solo
         payload /suse/stepan/tg3ide_
@@ -382,7 +382,7 @@
 the images and the final image size:
 
 \begin{verbatim}
-        buildrom ./solo.rom ROM_SIZE "normal" "fallback"
+        buildrom ./solo.rom CONFIG_ROM_SIZE "normal" "fallback"
 \end{verbatim}
 
 \end{itemize}
@@ -408,12 +408,12 @@
 Use new \textit{chip\_configure} method for configuring (nonpci)
 devices. Set to \texttt{1} for all AMD64 mainboards.
 
-\item \begin{verbatim}MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim}
+\item \begin{verbatim}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim}
 
 Errors or log messages up to this level can be printed. Default is
 \texttt{8}, minimum is \texttt{0}, maximum is \texttt{10}.
 
-\item \begin{verbatim}DEFAULT_CONSOLE_LOGLEVEL\end{verbatim}
+\item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim}
 
 Console will log at this level unless changed. Default is \texttt{7}, 
 minimum is \texttt{0}, maximum is \texttt{10}.
@@ -424,16 +424,16 @@
 (don't log to serial console). This value should be set to \texttt{1}
 for all AMD64 builds.
 
-\item \begin{verbatim}ROM_SIZE\end{verbatim}
+\item \begin{verbatim}CONFIG_ROM_SIZE\end{verbatim}
 
 Size of final ROM image. This option has no default value.
 
-\item \begin{verbatim}FALLBACK_SIZE\end{verbatim}
+\item \begin{verbatim}CONFIG_FALLBACK_SIZE\end{verbatim}
 
 Fallback image size. Defaults to \texttt{65536} bytes. \textbf{NOTE:} 
 This does not include the fallback payload.
 
-\item \begin{verbatim}HAVE_OPTION_TABLE\end{verbatim}
+\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
 
 Export CMOS option table. Default is \texttt{0}. Set to \texttt{1} if
 your mainboard has CMOS memory and you want to use it to store
@@ -444,7 +444,7 @@
 Boot image is located in ROM (as opposed to \texttt{CONFIG\_IDE\_PAYLOAD}, which
 will boot from an IDE disk)
 
-\item \begin{verbatim}HAVE_FALLBACK_BOOT\end{verbatim}
+\item \begin{verbatim}CONFIG_HAVE_FALLBACK_BOOT\end{verbatim}
 
 Set to \texttt{1} if fallback booting is required. Defaults to
 \texttt{0}.
@@ -456,11 +456,11 @@
 
 \begin{itemize}
 
-\item \begin{verbatim}USE_FALLBACK_IMAGE\end{verbatim}
+\item \begin{verbatim}CONFIG_USE_FALLBACK_IMAGE\end{verbatim}
 
 Set to \texttt{1} to build a fallback image. Defaults to \texttt{0}
 
-\item \begin{verbatim}ROM_IMAGE_SIZE\end{verbatim}
+\item \begin{verbatim}CONFIG_ROM_IMAGE_SIZE\end{verbatim}
 
 Default image size. Defaults to \texttt{65535} bytes.
 
@@ -544,14 +544,14 @@
 
 \begin{verbatim}
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
         action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
-		$(MAINBOARD)/auto.c -o $@"
+		$(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
         action "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
-                $(MAINBOARD)/auto.c -o $@"
+                $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 \end{verbatim}
 
@@ -747,26 +747,26 @@
 
 \begin{itemize}
 
-\item \begin{verbatim}HAVE_HARD_RESET\end{verbatim}
+\item \begin{verbatim}CONFIG_HAVE_HARD_RESET\end{verbatim}
 
 If set to \texttt{1}, this option defines that there is a hard reset
 function for this mainboard.  This option is not defined per default.
 
-\item \begin{verbatim}HAVE_PIRQ_TABLE\end{verbatim}
+\item \begin{verbatim}CONFIG_HAVE_PIRQ_TABLE\end{verbatim}
 
 If set to \texttt{1}, this option defines that there is an IRQ Table for
 this mainboard. This option is not defined per default.
 
-\item \begin{verbatim}IRQ_SLOT_COUNT\end{verbatim}
+\item \begin{verbatim}CONFIG_IRQ_SLOT_COUNT\end{verbatim}
 
 Number of IRQ slots. This option is not defined per default.
 
-\item \begin{verbatim}HAVE_MP_TABLE\end{verbatim}
+\item \begin{verbatim}CONFIG_HAVE_MP_TABLE\end{verbatim}
 
 Define this option to build an MP table (v1.4). The default is not to
 build an MP table.
 
-\item \begin{verbatim}HAVE_OPTION_TABLE\end{verbatim}
+\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
 
 Define this option to export a CMOS option table. The default is not to
 export a CMOS option table.
@@ -787,23 +787,23 @@
 Set this option to \texttt{1} to enable IOAPIC support. This is
 mandatory if you want to boot a 64bit Linux kernel on an AMD64 system.
 
-\item \begin{verbatim}STACK_SIZE\end{verbatim}
+\item \begin{verbatim}CONFIG_STACK_SIZE\end{verbatim}
 
 coreboot stack size. The size of the function call stack defaults to
 \texttt{0x2000} (8k).
 
-\item \begin{verbatim}HEAP_SIZE\end{verbatim}
+\item \begin{verbatim}CONFIG_HEAP_SIZE\end{verbatim}
 
 coreboot heap size. The heap is used when coreboot allocates memory
 with malloc(). The default heap size is \texttt{0x2000}, but AMD64 boards
 generally set it to \texttt{0x4000} (16k)
 
-\item \begin{verbatim}XIP_ROM_BASE\end{verbatim}
+\item \begin{verbatim}CONFIG_XIP_ROM_BASE\end{verbatim}
 
 Start address of area to cache during coreboot execution directly from
 ROM.
 
-\item \begin{verbatim}XIP_ROM_SIZE\end{verbatim}
+\item \begin{verbatim}CONFIG_XIP_ROM_SIZE\end{verbatim}
 
 Size of area to cache during coreboot execution directly from ROM
 
@@ -1075,8 +1075,8 @@
 variables set in their \texttt{Config.lb} file:
 
 \begin{verbatim}
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=7
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=7
 \end{verbatim}
 
 This will make coreboot look for the file \\
@@ -1106,7 +1106,7 @@
 \begin{verbatim}
 default CONFIG_SMP=1
 default CONFIG_MAX_CPUS=1 # 2,4,..
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 \end{verbatim}
 
 coreboot will then look for a function for setting up the MP table in
@@ -1136,9 +1136,9 @@
 To enable ACPI in your coreboot build, add the following lines to your
 configuration files:
 \begin{verbatim}
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_TABLES
 [..]
-option HAVE_ACPI_TABLES=1
+option CONFIG_HAVE_ACPI_TABLES=1
 \end{verbatim}
 
 To keep Linux doing it's pci ressource allocation based on IRQ tables and MP
@@ -1234,12 +1234,12 @@
 coreboot has to either assert an LDTSTOP or a reset to make the changes
 become active.  Additionally Linux can do a firmware reset, if coreboot
 provides the needed infrastructure. To use this capability, define the
-option \texttt{HAVE\_HARD\_RESET} and add an object file specifying the
+option \texttt{HAVE\_HARD\CONFIG_RESET} and add an object file specifying the
 reset code in your mainboard specific configuration file
 \texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/Config.lb}:
 
 \begin{verbatim}
-        default HAVE_HARD_RESET=1
+        default CONFIG_HAVE_HARD_RESET=1
         object reset.o
 \end{verbatim}
 
@@ -1529,7 +1529,7 @@
 There are two big additions to the build process and, furthermore, more than two new CONFIG variables to control them. 
 
 \begin{itemize}
-\item \begin{verbatim}USE_DCACHE_RAM\end{verbatim}
+\item \begin{verbatim}CONFIG_USE_DCACHE_RAM\end{verbatim}
 
 Set to \texttt{1} to use Cache As Ram (CAR). Defaults to \texttt{0}
 
@@ -1552,7 +1552,7 @@
 ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only 
 one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c. 
 \subsubsection{How it is built}
-Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CRT0\_INCLUDES variable. crt0.s is then assembled. 
+Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG_CRT0\_INCLUDES variable. crt0.s is then assembled. 
 
 File for the ram part are compiled in a conventional manner. 
 
@@ -1575,8 +1575,8 @@
 
 \begin{itemize}
 \item PAYLOAD\_SIZE. Each image may have a different payload size. 
-\item \_ROMBASE Each image must have a different base in rom. 
-\item \_RESET Unclear what this is used for. 
+\item \CONFIG_ROMBASE Each image must have a different base in rom. 
+\item \CONFIG_RESET Unclear what this is used for. 
 \item \_EXCEPTION\_VECTORS where an optional IDT might go.
 \item USE\_OPTION\_TABLE if set, an option table section will be linked in. 
 \item CONFIG\_ROM\_PAYLOAD\_START This is the soon-to-be-deprecated way of locating a payload. cbfs eliminates this. 
@@ -1608,7 +1608,7 @@
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -1619,7 +1619,7 @@
 How does the fallback image get the symbol for normal entry? Via magic in the ldscript.ld -- remember, the images are not linked to each other. 
 Finally, we can see this in the Config.lb for most mainboards: 
 \begin{verbatim}
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/reset16.inc
         ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -1771,10 +1771,10 @@
 The fallback and normal builds are the same. The target config has a new clause that looks like this: 
 \begin{verbatim}
 romimage "failover"
-        option USE_FAILOVER_IMAGE=1
-        option USE_FALLBACK_IMAGE=0
-        option ROM_IMAGE_SIZE=FAILOVER_SIZE
-        option XIP_ROM_SIZE=FAILOVER_SIZE
+        option CONFIG_USE_FAILOVER_IMAGE=1
+        option CONFIG_USE_FALLBACK_IMAGE=0
+        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover"
 end
 \end{verbatim}

Modified: trunk/coreboot-v2/documentation/RFC/config.tex
===================================================================
--- trunk/coreboot-v2/documentation/RFC/config.tex	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/documentation/RFC/config.tex	2009-06-30 15:17:49 UTC (rev 4381)
@@ -173,7 +173,7 @@
 target x
 
 # over-ride the default rom size in the mainboard file
-option ROM_SIZE=1024*1024
+option CONFIG_ROM_SIZE=1024*1024
 mainboard amd/solo
 end
 
@@ -188,8 +188,8 @@
 arch i386 end
 cpu k8 end
 #
-option DEBUG=1
-default USE_FALLBACK_IMAGE=1
+option CONFIG_DEBUG=1
+default CONFIG_USE_FALLBACK_IMAGE=1
 option A=(1+2)
 option B=0xa
 #
@@ -204,7 +204,7 @@
 ###
 ### Build our reset vector (This is where linuxBIOS is entered)
 ###
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/i386/reset16.inc 
 	ldscript cpu/i386/reset16.lds 
 else
@@ -214,15 +214,15 @@
 .
 .
 .
-if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
+if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
 #
 ###
 ### Romcc output
 ###
-#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
+#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
 #mainboardinit ./failover.inc
-makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
 makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
 mainboardinit ./auto.inc
 #
@@ -250,8 +250,8 @@
 ##object mainboard.o
 driver mainboard.o
 object static_devices.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 ### Location of the DIMM EEPROMS on the SMBUS
 ### This is fixed into a narrow range by the DIMM package standard.
 ###
@@ -261,8 +261,8 @@
 #
 ### The linuxBIOS bootloader.
 ###
-option PAYLOAD_SIZE            = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 #
 
 \end{verbatim}
@@ -272,17 +272,17 @@
 \begin{verbatim}
 TOP:=/home/rminnich/src/yapps2/freebios2
 TARGET_DIR:=x
-export MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
-export ARCH:=i386
-export _RAMBASE:=0x4000
-export ROM_IMAGE_SIZE:=65535
-export PAYLOAD_SIZE:=131073
+export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
+export CONFIG_ARCH:=i386
+export CONFIG_RAMBASE:=0x4000
+export CONFIG_ROM_IMAGE_SIZE:=65535
+export CONFIG_PAYLOAD_SIZE:=131073
 export CONFIG_MAX_CPUS:=1
-export HEAP_SIZE:=8192
-export STACK_SIZE:=8192
-export MEMORY_HOLE:=0
+export CONFIG_HEAP_SIZE:=8192
+export CONFIG_STACK_SIZE:=8192
+export CONFIG_MEMORY_HOLE:=0
 export COREBOOT_VERSION:=1.1.0
-export CC:=$(CROSS_COMPILE)gcc
+export CC:=$(CONFIG_CROSS_COMPILE)gcc
 
 \end{verbatim}
 

Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -2,14 +2,14 @@
 uses CONFIG_SMP
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_USE_INIT
-uses HAVE_FAILOVER_BOOT
-uses USE_FAILOVER_IMAGE
-uses USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_USE_FALLBACK_IMAGE
 
 init init/crt0.S.lb
 
 if CONFIG_CBFS
-	if USE_FAILOVER_IMAGE
+	if CONFIG_USE_FAILOVER_IMAGE
 	else
 		initobject /src/lib/cbfs.o
 		initobject /src/console/vsprintf.o
@@ -17,8 +17,8 @@
 	end
 end
 
-if HAVE_FAILOVER_BOOT
-	if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
 		ldscript init/ldscript_failover.lb
 	else
 		if CONFIG_CBFS
@@ -29,13 +29,13 @@
 	end
 else
 	if CONFIG_CBFS
-		if USE_FALLBACK_IMAGE
+		if CONFIG_USE_FALLBACK_IMAGE
 			ldscript init/ldscript_fallback_cbfs.lb
 		else
 			ldscript init/ldscript_cbfs.lb
 		end
 	else
-		if USE_FALLBACK_IMAGE
+		if CONFIG_USE_FALLBACK_IMAGE
 			ldscript init/ldscript_fallback.lb
 		else
 			ldscript init/ldscript.lb
@@ -54,7 +54,7 @@
 
 makerule nrv2b 
 	depends	"$(TOP)/util/nrv2b/nrv2b.c"
-	action	"$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
+	action	"$(CONFIG_HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
 end
 
 makerule payload
@@ -91,7 +91,7 @@
 	makedefine PAYLOAD-1:=payload
 end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 	makedefine COREBOOT_APC:=
 	makedefine COREBOOT_RAM_ROM:=
 
@@ -102,13 +102,13 @@
 else
 	makerule coreboot.rom 
 		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
-		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
+		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
 		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi"
 	end
 end
 
 makerule crt0.S
-	depends "$(CRT0)"
+	depends "$(CONFIG_CRT0)"
 	action  "cp $< $@"
 end
 
@@ -118,13 +118,13 @@
 	makerule init.o
         	depends "$(INIT-OBJECTS)"
 	        action  "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
-	        action  "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
+	        action  "$(CONFIG_OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
 	end
 
         makerule coreboot   
 		depends	"crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
 		action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
-		action	"$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
+		action	"$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
         end
 
 end

Modified: trunk/coreboot-v2/src/arch/i386/boot/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/boot/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_MULTIBOOT
-uses HAVE_ACPI_RESUME
+uses CONFIG_HAVE_ACPI_RESUME
 
 object boot.o
 object coreboot_table.o
@@ -9,13 +9,13 @@
 object multiboot.o
 end
 object tables.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 object pirq_routing.o 
 end
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 object acpi.o
 object acpigen.o
-if HAVE_ACPI_RESUME
+if CONFIG_HAVE_ACPI_RESUME
 object wakeup.S
 end
 end

Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/acpi.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -390,18 +390,18 @@
 	rsdp->ext_checksum	= acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t));
 }
 
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 void suspend_resume(void)
 {
 	void *wake_vec;
 
 #if 0
-#if MEM_TRAIN_SEQ != 0
-	#error "So far it works on AMD and MEM_TRAIN_SEQ == 0"
+#if CONFIG_MEM_TRAIN_SEQ != 0
+	#error "So far it works on AMD and CONFIG_MEM_TRAIN_SEQ == 0"
 #endif
 
-#if _RAMBASE < 0x1F00000
-	#error "For ACPI RESUME you need to have _RAMBASE at least 31MB"
+#if CONFIG_RAMBASE < 0x1F00000
+	#error "For ACPI RESUME you need to have CONFIG_RAMBASE at least 31MB"
 	#error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)"
 	#error "And coreboot memory reserved in mainboard.c"
 #endif

Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -76,15 +76,15 @@
 
 struct lb_serial *lb_serial(struct lb_header *header)
 {
-#if defined(TTYS0_BASE)
+#if defined(CONFIG_TTYS0_BASE)
 	struct lb_record *rec;
 	struct lb_serial *serial;
 	rec = lb_new_record(header);
 	serial = (struct lb_serial *)rec;
 	serial->tag = LB_TAG_SERIAL;
 	serial->size = sizeof(*serial);
-	serial->ioport = TTYS0_BASE;
-	serial->baud = TTYS0_BAUD;
+	serial->ioport = CONFIG_TTYS0_BASE;
+	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
 #else
 	return header;
@@ -157,9 +157,9 @@
 
 	cmos_checksum->size = (sizeof(*cmos_checksum));
 
-	cmos_checksum->range_start = LB_CKS_RANGE_START * 8;
-	cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
-	cmos_checksum->location = LB_CKS_LOC * 8;
+	cmos_checksum->range_start = CONFIG_LB_CKS_RANGE_START * 8;
+	cmos_checksum->range_end = ( CONFIG_LB_CKS_RANGE_END * 8 ) + 7;
+	cmos_checksum->location = CONFIG_LB_CKS_LOC * 8;
 	cmos_checksum->type = CHECKSUM_PCBIOS;
 	
 	return cmos_checksum;
@@ -413,7 +413,7 @@
 	return mem;
 }
 
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
@@ -424,7 +424,7 @@
 	struct lb_header *head;
 	struct lb_memory *mem;
 
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
 	printk_debug("Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
@@ -460,7 +460,7 @@
 	rom_table_end &= ~0xffff;
 	printk_debug("0x%08lx \n", rom_table_end);
 
-#if (HAVE_OPTION_TABLE == 1) 
+#if (CONFIG_HAVE_OPTION_TABLE == 1) 
 	{
 		struct lb_record *rec_dest, *rec_src;
 		/* Write the option config table... */
@@ -482,13 +482,13 @@
 	lb_add_memory_range(mem, LB_MEM_TABLE, 
 		rom_table_start, rom_table_end-rom_table_start);
 
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
 	printk_debug("Adding high table area\n");
 	lb_add_memory_range(mem, LB_MEM_TABLE,
 		high_tables_base, high_tables_size);
 #endif
 
-#if (HAVE_MAINBOARD_RESOURCES == 1)
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
 	add_mainboard_resources(mem);
 #endif
 

Modified: trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -3,7 +3,7 @@
 #include <string.h>
 #include <device/pci.h>
 
-#if (DEBUG==1 && HAVE_PIRQ_TABLE==1)
+#if (CONFIG_DEBUG==1 && CONFIG_HAVE_PIRQ_TABLE==1)
 static void check_pirq_routing_table(struct irq_routing_table *rt)
 {
 	uint8_t *addr = (uint8_t *)rt;
@@ -12,7 +12,7 @@
 
 	printk_info("Checking Interrupt Routing Table consistency...\n");
 
-#if defined(IRQ_SLOT_COUNT)
+#if defined(CONFIG_IRQ_SLOT_COUNT)
 	if (sizeof(struct irq_routing_table) != rt->size) {
 		printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
 			       sizeof(struct irq_routing_table),
@@ -83,7 +83,7 @@
 #define verify_copy_pirq_routing_table(addr)
 #endif
 
-#if HAVE_PIRQ_TABLE==1
+#if CONFIG_HAVE_PIRQ_TABLE==1
 unsigned long copy_pirq_routing_table(unsigned long addr)
 {
 	/* Align the table to be 16 byte aligned. */
@@ -100,7 +100,7 @@
 }
 #endif
 
-#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1)
 void pirq_routing_irqs(unsigned long addr)
 {
 	int i, j, k, num_entries;

Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/boot/tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -104,7 +104,7 @@
 	post_code(0x9a);
 
 	/* Write ACPI tables to F segment and high tables area */
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
 	if (high_tables_base) {
 		unsigned long acpi_start = high_table_end;
 		rom_table_end = ALIGN(rom_table_end, 16);
@@ -129,7 +129,7 @@
 #endif
 	post_code(0x9b);
 
-#if HAVE_MP_TABLE == 1
+#if CONFIG_HAVE_MP_TABLE == 1
 	/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
 	rom_table_end = write_smp_table(rom_table_end);
 	rom_table_end = ALIGN(rom_table_end, 1024);
@@ -139,7 +139,7 @@
 		high_table_end = write_smp_table(high_table_end);
 		high_table_end = ALIGN(high_table_end, 1024);
 	}
-#endif /* HAVE_MP_TABLE */
+#endif /* CONFIG_HAVE_MP_TABLE */
 
 	post_code(0x9c);
 

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -13,11 +13,11 @@
 #ifndef __ASM_ACPI_H
 #define __ASM_ACPI_H
 
-#if HAVE_ACPI_TABLES==1
+#if CONFIG_HAVE_ACPI_TABLES==1
 
 #include <stdint.h>
  
-#if HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME
 /* 0 = S0, 1 = S1 ...*/
 extern u8 acpi_slp_type;
 #endif
@@ -88,13 +88,13 @@
 /* RSDT */
 typedef struct acpi_rsdt {
 	struct acpi_table_header header;
-	u32 entry[7+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
+	u32 entry[7+CONFIG_ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
 } __attribute__ ((packed)) acpi_rsdt_t;
 
 /* XSDT */
 typedef struct acpi_xsdt {
 	struct acpi_table_header header;
-	u64 entry[6+ACPI_SSDTX_NUM];
+	u64 entry[6+CONFIG_ACPI_SSDTX_NUM];
 } __attribute__ ((packed)) acpi_xsdt_t;
 
 /* HPET TIMERS */
@@ -367,7 +367,7 @@
 void acpi_write_rsdt(acpi_rsdt_t *rsdt);
 void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt);
 
-#if HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME
 void suspend_resume(void);
 void *acpi_find_wakeup_vector(void);
 void *acpi_get_wakeup_rsdp(void);
@@ -390,7 +390,7 @@
 
 #define IO_APIC_ADDR	0xfec00000UL
 
-#else // HAVE_ACPI_TABLES
+#else // CONFIG_HAVE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
 

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/cpu.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/cpu.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/cpu.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -128,8 +128,8 @@
 	__asm__("andl %%esp,%0; "
 		"orl  %2, %0 "
 		:"=r" (ci) 
-		: "0" (~(STACK_SIZE - 1)), 
-		"r" (STACK_SIZE - sizeof(struct cpu_info))
+		: "0" (~(CONFIG_STACK_SIZE - 1)), 
+		"r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info))
 	);
 	return ci;
 }

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/pci_ops.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/pci_ops.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/pci_ops.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -4,7 +4,7 @@
 extern const struct pci_bus_operations pci_cf8_conf1;
 extern const struct pci_bus_operations pci_cf8_conf2;
 
-#if MMCONF_SUPPORT==1
+#if CONFIG_MMCONF_SUPPORT==1
 extern const struct pci_bus_operations pci_ops_mmconf;
 #endif
 

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/pciconf.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/pciconf.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/pciconf.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -5,7 +5,7 @@
 #define	PCI_CONF_REG_INDEX	0xcf8
 #define	PCI_CONF_REG_DATA	0xcfc
 
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
 #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
 #else
 #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) )

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -16,8 +16,8 @@
 	uint8_t rfu;
 } __attribute__((packed));
 
-#if defined(IRQ_SLOT_COUNT)
-#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT
+#if defined(CONFIG_IRQ_SLOT_COUNT)
+#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
 #elif (__GNUC__ < 3)
 #define IRQ_SLOTS_COUNT 1
 #else
@@ -39,10 +39,10 @@
 
 extern const struct irq_routing_table intel_irq_routing_table;
 
-#if HAVE_PIRQ_TABLE==1
+#if CONFIG_HAVE_PIRQ_TABLE==1
 unsigned long copy_pirq_routing_table(unsigned long start);
 unsigned long write_pirq_routing_table(unsigned long start);
-#if PIRQ_ROUTE==1
+#if CONFIG_PIRQ_ROUTE==1
 void pirq_routing_irqs(unsigned long start);
 void pirq_assign_irqs(const unsigned char pIntAtoD[4]);
 #else

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -34,7 +34,7 @@
 	*((volatile uint32_t *)(addr)) = value;
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 
 #include <arch/mmio_conf.h>
 
@@ -92,7 +92,7 @@
 static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
 	addr = (dev>>4) | where;
 #else
 	addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
@@ -101,17 +101,17 @@
 	return inb(0xCFC + (addr & 3));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         return read8x(addr);
 }
 #endif
 static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	return pci_mmio_read_config8(dev, where);
 #else
 	return pci_io_read_config8(dev, where);
@@ -121,7 +121,7 @@
 static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -130,18 +130,18 @@
 	return inw(0xCFC + (addr & 2));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         return read16x(addr);
 }
 #endif
 
 static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	return pci_mmio_read_config16(dev, where);
 #else
         return pci_io_read_config16(dev, where);
@@ -152,7 +152,7 @@
 static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -161,18 +161,18 @@
 	return inl(0xCFC);
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         return read32x(addr);
 }
 #endif
 
 static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	return pci_mmio_read_config32(dev, where);
 #else
         return pci_io_read_config32(dev, where);
@@ -182,7 +182,7 @@
 static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -191,18 +191,18 @@
 	outb(value, 0xCFC + (addr & 3));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         write8x(addr, value);
 }
 #endif
 
 static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	pci_mmio_write_config8(dev, where, value);
 #else
         pci_io_write_config8(dev, where, value);
@@ -213,7 +213,7 @@
 static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
 {
         unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -222,18 +222,18 @@
         outw(value, 0xCFC + (addr & 2));
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         write16x(addr, value);
 }
 #endif
 
 static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	pci_mmio_write_config16(dev, where, value);
 #else
 	pci_io_write_config16(dev, where, value);
@@ -244,7 +244,7 @@
 static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
         addr = (dev>>4) | where;
 #else
         addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -253,18 +253,18 @@
 	outl(value, 0xCFC);
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
 {
         unsigned addr;
-        addr = MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
         write32x(addr, value);
 }
 #endif
 
 static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
 {
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
 	pci_mmio_write_config32(dev, where, value);
 #else
         pci_io_write_config32(dev, where, value);
@@ -286,7 +286,7 @@
 
 static device_t pci_locate_device(unsigned pci_id, device_t dev)
 {
-	for(; dev <= PCI_DEV(255|(((1<<PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
+	for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
 		unsigned int id;
 		id = pci_read_config32(dev, 0);
 		if (id == pci_id) {

Modified: trunk/coreboot-v2/src/arch/i386/init/car.S
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/car.S	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/car.S	2009-06-30 15:17:49 UTC (rev 4381)
@@ -72,8 +72,8 @@
  * the other is very similar to the AMD CAR, except remove amd specific msr
  */
 
-#define CacheSize DCACHE_RAM_SIZE
-#define CacheBase DCACHE_RAM_BASE
+#define CacheSize CONFIG_DCACHE_RAM_SIZE
+#define CacheBase CONFIG_DCACHE_RAM_BASE
 
 #include <cpu/x86/mtrr.h>
 
@@ -241,14 +241,14 @@
 	 */
 	movl    $0x202, %ecx
 	xorl    %edx, %edx
-	movl    $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl    $0x203, %ecx
 	movl    $0x0000000f, %edx
-	movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
 	/* enable cache */
 	movl    %cr0, %eax

Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -37,14 +37,14 @@
 
 #include "crt0_includes.h"
 
-#if USE_DCACHE_RAM == 0
+#if CONFIG_USE_DCACHE_RAM == 0
 #ifndef CONSOLE_DEBUG_TX_STRING
 	/* uses:	 esp, ebx, ax, dx */
 # define __CRT_CONSOLE_TX_STRING(string) \
 	mov	string, %ebx	; \
 	CALLSP(crt_console_tx_string)
 
-# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
 #  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
 # else
 #  define CONSOLE_DEBUG_TX_STRING(string)
@@ -102,26 +102,26 @@
 	RETSP
 9:
 /* Base Address */
-#ifndef TTYS0_BASE
-#define TTYS0_BASE	0x3f8
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE	0x3f8
 #endif
 /* Data */
-#define TTYS0_RBR (TTYS0_BASE+0x00)
+#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
 
 /* Control */
 #define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (TTYS0_BASE+0x01)
-#define TTYS0_IIR (TTYS0_BASE+0x02)
+#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
+#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
 #define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (TTYS0_BASE+0x03)
-#define TTYS0_MCR (TTYS0_BASE+0x04)
+#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
+#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
 #define TTYS0_DLL TTYS0_RBR
 #define TTYS0_DLM TTYS0_IER
 
 /* Status */
-#define TTYS0_LSR (TTYS0_BASE+0x05)
-#define TTYS0_MSR (TTYS0_BASE+0x06)
-#define TTYS0_SCR (TTYS0_BASE+0x07)
+#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
+#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
+#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
 	
 	mov	%al, %ah
 10:	mov	$TTYS0_LSR, %dx
@@ -143,7 +143,7 @@
 str_copying_to_ram:  .string "Copying coreboot to RAM.\r\n"
 #endif
 #if CONFIG_CBFS
-# if USE_FALLBACK_IMAGE == 1
+# if CONFIG_USE_FALLBACK_IMAGE == 1
 str_coreboot_ram_name:	.string "fallback/coreboot_ram"
 # else
 str_coreboot_ram_name:	.string "normal/coreboot_ram"
@@ -154,4 +154,4 @@
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
 
-#endif /* USE_DCACHE_RAM */
+#endif /* CONFIG_USE_DCACHE_RAM */

Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -35,7 +35,7 @@
 INPUT(coreboot_ram.rom)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	.ram . : {
 		_ram = . ;
@@ -56,7 +56,7 @@
 
 	_lrom = LOADADDR(.rom);
 	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
-	_iseg = _RAMBASE;
+	_iseg = CONFIG_RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
 	_liseg = _ram;
 	_eliseg = _eram;

Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -6,7 +6,7 @@
                 coreboot_apc.rom(*)
                 _eapcrom = .;
         }
-        _iseg_apc = DCACHE_RAM_BASE;
+        _iseg_apc = CONFIG_DCACHE_RAM_BASE;
         _eiseg_apc = _iseg_apc + SIZEOF(.apcrom);
         _liseg_apc = _apcrom;
         _eliseg_apc = _eapcrom;

Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_cbfs.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_cbfs.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_cbfs.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -34,7 +34,7 @@
 TARGET(binary)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/* This section might be better named .setup */
 	.rom . : {

Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -34,7 +34,7 @@
 TARGET(binary)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/* This section might be better named .setup */
 	.rom . : {

Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -35,7 +35,7 @@
 INPUT(coreboot_ram.rom)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	.ram . : {
 		_ram = . ;
@@ -45,7 +45,7 @@
 
 	/* cut _start into last 64k*/
 	_x = .;
-	. = (_x < (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE) : _x;
+	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE) : _x;
 
 	/* This section might be better named .setup */
 	.rom . : {
@@ -61,7 +61,7 @@
 
 	_lrom = LOADADDR(.rom);
 	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
-	_iseg = _RAMBASE;
+	_iseg = CONFIG_RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
 	_liseg = _ram;
 	_eliseg = _eram;

Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,12 +1,12 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
  *				: stack
- *	_ROMBASE
+ *	CONFIG_ROMBASE
  *				: coreboot text 
  *				: readonly text
  */
@@ -34,11 +34,11 @@
 TARGET(binary)
 SECTIONS
 {
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/* cut _start into last 64k*/
 	_x = .;
-	. = (_x < (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 +  ROM_IMAGE_SIZE) : _x;
+	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE) : _x;
 
 	/* This section might be better named .setup */
 	.rom . : {

Modified: trunk/coreboot-v2/src/arch/i386/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,6 +1,6 @@
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
-uses USE_FAILOVER_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
 uses CONFIG_CBFS
 
 object c_start.S
@@ -13,7 +13,7 @@
 
 initobject printk_init.o
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
 	if CONFIG_CBFS
 		initobject cbfs_and_run.o

Modified: trunk/coreboot-v2/src/arch/i386/lib/console_printk.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/console_printk.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/console_printk.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -11,39 +11,39 @@
 #define printk_debug(fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
 #define printk_spew(fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
 
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
 #undef  printk_emerg
 #define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
 #undef  printk_alert
 #define printk_alert(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
 #undef  printk_crit
 #define printk_crit(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
 #undef  printk_err
 #define printk_err(fmt, arg...)     do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
 #undef  printk_warning
 #define printk_warning(fmt, arg...) do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
 #undef  printk_notice
 #define printk_notice(fmt, arg...)  do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
 #undef  printk_info
 #define printk_info(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
 #undef  printk_debug
 #define printk_debug(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
 #undef  printk_spew
 #define printk_spew(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif

Modified: trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,2 +1,2 @@
 	__fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
-	__normal_image = ((CONFIG_ROM_PAYLOAD_START - FALLBACK_SIZE) & 0xfffffff0) - 8;
+	__normal_image = ((CONFIG_ROM_PAYLOAD_START - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8;

Modified: trunk/coreboot-v2/src/arch/i386/lib/id.inc
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/id.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/id.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -3,12 +3,12 @@
 	.globl __id_start
 __id_start:
 vendor:	
-	.asciz MAINBOARD_VENDOR
+	.asciz CONFIG_MAINBOARD_VENDOR
 part:		
-	.asciz MAINBOARD_PART_NUMBER
+	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x10 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x10 - part    /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
 	.globl __id_end
 
 __id_end:

Modified: trunk/coreboot-v2/src/arch/i386/lib/id.lds
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/id.lds	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/id.lds	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}

Modified: trunk/coreboot-v2/src/arch/i386/lib/pci_ops_conf1.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/pci_ops_conf1.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/pci_ops_conf1.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -8,7 +8,7 @@
  * Functions for accessing PCI configuration space with type 1 accesses
  */
 
-#if PCI_IO_CFG_EXT == 0
+#if CONFIG_PCI_IO_CFG_EXT == 0
 #define CONFIG_CMD(bus,devfn, where)   (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
 #else
 #define CONFIG_CMD(bus,devfn, where)   (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) )

Modified: trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,4 +1,4 @@
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 
 #include <console/console.h>
 #include <arch/io.h>
@@ -13,7 +13,7 @@
  */
 
 #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \
-	MMCONF_BASE_ADDRESS | \
+	CONFIG_MMCONF_BASE_ADDRESS | \
         (((SEGBUS) & 0xFFF) << 20) | \
         (((DEVFN) & 0xFF) << 12) | \
         ((WHERE) & 0xFFF))

Modified: trunk/coreboot-v2/src/arch/i386/lib/printk_init.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/printk_init.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/lib/printk_init.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -14,7 +14,7 @@
 /* Keep together for sysctl support */
 /* Using an global varible can cause problem when we reset the stack from cache as ram to ram*/
 #if 0
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 #else
 #define console_loglevel ASM_CONSOLE_LOGLEVEL
 #endif
@@ -25,8 +25,8 @@
 void console_tx_byte(unsigned char byte)
 {
 	if (byte == '\n')
-		uart8250_tx_byte(TTYS0_BASE, '\r');
-	uart8250_tx_byte(TTYS0_BASE, byte);
+		uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
+	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
 }
 
 int do_printk(int msg_level, const char *fmt, ...)

Modified: trunk/coreboot-v2/src/arch/i386/smp/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/smp/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/i386/smp/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,6 +1,6 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 
-if HAVE_MP_TABLE
+if CONFIG_HAVE_MP_TABLE
   object mpspec.o 
 end
 #object ioapic.o CONFIG_IOAPIC

Modified: trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -340,7 +340,7 @@
 
 	head = lb_table_init(low_table_end);
 	low_table_end = (unsigned long)head;
-	if (HAVE_OPTION_TABLE == 1) {
+	if (CONFIG_HAVE_OPTION_TABLE == 1) {
 		struct lb_record *rec_dest, *rec_src;
 		/* Write the option config table... */
 		rec_dest = lb_new_record(head);

Modified: trunk/coreboot-v2/src/arch/ppc/include/arch/cpu.h
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/include/arch/cpu.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/include/arch/cpu.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -13,24 +13,24 @@
 	struct cpu_device_id *id_table;
 };
 
-#ifndef STACK_SIZE
-#error STACK_SIZE not defined
+#ifndef CONFIG_STACK_SIZE
+#error CONFIG_STACK_SIZE not defined
 #endif
 
 /* The basic logic comes from the Linux kernel.
- * The invariant is that (1 << 31 - STACK_BITS) == STACK_SIZE
+ * The invariant is that (1 << 31 - STACK_BITS) == CONFIG_STACK_SIZE
  * I wish there was simpler way to support multiple stack sizes.
  * Oh well.
  */
-#if STACK_SIZE == 4096
+#if CONFIG_STACK_SIZE == 4096
 #define STACK_BITS "19"
-#elif STACK_SIZE == 8192
+#elif CONFIG_STACK_SIZE == 8192
 #define STACK_BITS "18"
-#elif STACK_SIZE == 16384
+#elif CONFIG_STACK_SIZE == 16384
 #define STACK_BITS "17"
-#elif STACK_SIZE == 32768
+#elif CONFIG_STACK_SIZE == 32768
 #define STACK_BITS "16"
-#elif STACK_SIZE == 65536
+#elif CONFIG_STACK_SIZE == 65536
 #define STACK_BITS "15"
 #else
 #error Unimplemented stack size

Modified: trunk/coreboot-v2/src/arch/ppc/include/arch/io.h
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/include/arch/io.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/include/arch/io.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -11,8 +11,8 @@
 
 #define SLOW_DOWN_IO
 
-#ifndef _IO_BASE
-#define _IO_BASE	0
+#ifndef CONFIG_IO_BASE
+#define CONFIG_IO_BASE	0
 #endif
 
 #define readb(addr) in_8((volatile uint8_t *)(addr))
@@ -36,15 +36,15 @@
  * are arrays of bytes, and byte-swapping is not appropriate in
  * that case.  - paulus
  */
-#define insw(port, buf, ns)	_insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-#define outsw(port, buf, ns)	_outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns)	_insw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)	_outsw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
 
-#define inb(port)		in_8((uint8_t *)((port)+_IO_BASE))
-#define outb(val, port)		out_8((uint8_t *)((port)+_IO_BASE), (val))
-#define inw(port)		in_le16((uint16_t *)((port)+_IO_BASE))
-#define outw(val, port)		out_le16((uint16_t *)((port)+_IO_BASE), (val))
-#define inl(port)		in_le32((uint32_t *)((port)+_IO_BASE))
-#define outl(val, port)		out_le32((uint32_t *)((port)+_IO_BASE), (val))
+#define inb(port)		in_8((uint8_t *)((port)+CONFIG_IO_BASE))
+#define outb(val, port)		out_8((uint8_t *)((port)+CONFIG_IO_BASE), (val))
+#define inw(port)		in_le16((uint16_t *)((port)+CONFIG_IO_BASE))
+#define outw(val, port)		out_le16((uint16_t *)((port)+CONFIG_IO_BASE), (val))
+#define inl(port)		in_le32((uint32_t *)((port)+CONFIG_IO_BASE))
+#define outl(val, port)		out_le32((uint32_t *)((port)+CONFIG_IO_BASE), (val))
 
 #define inb_p(port)		inb((port))
 #define outb_p(val, port)	outb((val), (port))
@@ -56,8 +56,8 @@
 /*
  * The *_ns versions below do byte-swapping.
  */
-#define insw_ns(port, buf, ns)	_insw((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-#define outsw_ns(port, buf, ns)	_outsw((uint16_t *)((port)+_IO_BASE), (buf), (ns))
+#define insw_ns(port, buf, ns)	_insw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns)	_outsw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
 
 
 #define IO_SPACE_LIMIT ~0

Modified: trunk/coreboot-v2/src/arch/ppc/include/arch/pirq_routing.h
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/include/arch/pirq_routing.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/include/arch/pirq_routing.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -16,8 +16,8 @@
 	u8 rfu;
 } __attribute__((packed));
 
-#if defined(IRQ_SLOT_COUNT)
-#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT
+#if defined(CONFIG_IRQ_SLOT_COUNT)
+#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
 #elif (__GNUC__ < 3)
 #define IRQ_SLOTS_COUNT 1
 #else
@@ -39,13 +39,13 @@
 
 extern const struct irq_routing_table intel_irq_routing_table;
 
-#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE)
+#if defined(CONFIG_DEBUG) && defined(CONFIG_HAVE_PIRQ_TABLE)
 void check_pirq_routing_table(void);
 #else
 #define check_pirq_routing_table() do {} while(0)
 #endif
 
-#if defined(HAVE_PIRQ_TABLE)
+#if defined(CONFIG_HAVE_PIRQ_TABLE)
 unsigned long copy_pirq_routing_table(unsigned long start);
 #else
 #define copy_pirq_routing_table(start) (start)

Modified: trunk/coreboot-v2/src/arch/ppc/init/crt0.S.lb
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/init/crt0.S.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/init/crt0.S.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -30,8 +30,8 @@
 	 */
 %%PROCESSOR_INIT%%
 
-#if USE_DCACHE_RAM == 1
-#define DCACHE_RAM_END	(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1)
+#if CONFIG_USE_DCACHE_RAM == 1
+#define DCACHE_RAM_END	(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
 	/*
 	 * Initialize data cache blocks 
 	 * (assumes cache block size of 32 bytes)
@@ -39,9 +39,9 @@
 	 * NOTE: This may need to be moved to FAMILY_INIT if
 	 *       dcbz is not supported on all CPU's
 	 */
-	lis     r1, DCACHE_RAM_BASE at h
-	ori     r1, r1, DCACHE_RAM_BASE at l
-	li      r3, (DCACHE_RAM_SIZE / 32)
+	lis     r1, CONFIG_DCACHE_RAM_BASE at h
+	ori     r1, r1, CONFIG_DCACHE_RAM_BASE at l
+	li      r3, (CONFIG_DCACHE_RAM_SIZE / 32)
 	mtctr   r3
 0:      dcbz    r0, r1
 	addi    r1, r1, 32
@@ -53,8 +53,8 @@
 	 * it 16-byte aligned to cover both cases. Also we have to ensure that
 	 * the first word is located within the cache.
 	 */
-	lis     r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@h
-	ori     r1, r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@l
+	lis     r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
+	ori     r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
 	lis	r0, 0
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
@@ -65,8 +65,8 @@
 	/*
 	 * Clear stack
 	 */
-	lis	r4, DCACHE_RAM_BASE at h
-	ori	r4, r4, DCACHE_RAM_BASE at l
+	lis	r4, CONFIG_DCACHE_RAM_BASE at h
+	ori	r4, r4, CONFIG_DCACHE_RAM_BASE at l
 	lis	r7, DCACHE_RAM_END at h
 	ori	r7, r7, DCACHE_RAM_END at l
 	lis	r5, 0
@@ -110,7 +110,7 @@
 	 * Complete rest of initialization in C (ppc_main)
 	 */
 	rfi
-#endif /* USE_DCACHE_RAM */
+#endif /* CONFIG_USE_DCACHE_RAM */
 
 	/*
 	 * Stop here if something goes wrong

Modified: trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,14 +1,14 @@
 /*
  *	Memory map:
  *
- *	_ROMBASE		: start of ROM
- *	_RESET			: reset vector (may be at top of ROM)
+ *	CONFIG_ROMBASE		: start of ROM
+ *	CONFIG_RESET			: reset vector (may be at top of ROM)
  *	_EXCEPTIONS_VECTORS	: exception table
  *
- *	_ROMSTART 		: coreboot text 
+ *	CONFIG_ROMSTART 		: coreboot text 
  *				: payload text
  *
- *	_RAMBASE		: address to copy payload
+ *	CONFIG_RAMBASE		: address to copy payload
  */
 
 /*
@@ -32,13 +32,13 @@
 	/* 
 	 * Absolute location of base of ROM 
 	 */
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/*
 	 * Absolute location of reset vector. This may actually be at the
 	 * the top of ROM.
 	 */
-	. = _RESET;
+	. = CONFIG_RESET;
 	.reset . : {
 		*(.rom.reset);
 		. = ALIGN(16);
@@ -47,7 +47,7 @@
 	/*
 	 * Absolute location of exception vector table.
 	 */
-	. = _EXCEPTION_VECTORS;
+	. = CONFIG_EXCEPTION_VECTORS;
 	.exception_vectors . : {
 		*(.rom.exception_vectors);
 		. = ALIGN(16);
@@ -56,7 +56,7 @@
 	/*
 	 * Absolute location of coreboot initialization code in ROM.
 	 */
-	. = _ROMSTART;
+	. = CONFIG_ROMSTART;
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
@@ -94,7 +94,7 @@
 	/*
 	 * Absolute location of where coreboot will be relocated in RAM.
 	 */
-	_iseg = _RAMBASE;
+	_iseg = CONFIG_RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
 	_liseg = _ram;
 	_eliseg = _eram;

Modified: trunk/coreboot-v2/src/arch/ppc/lib/pci_dev.c
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/lib/pci_dev.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/lib/pci_dev.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -9,8 +9,8 @@
 {
 	uint8_t res;
 
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	res = in_8((unsigned char *)PCIC0_CFGDATA + (where & 3));
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	res = in_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3));
 	return res;
 }
 
@@ -18,8 +18,8 @@
 {
 	uint16_t res;
 
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	res = in_le16((unsigned short *)PCIC0_CFGDATA + (where & 2));
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	res = in_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2));
 	return res;
 }
 
@@ -27,28 +27,28 @@
 {
 	uint32_t res;
 
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	res = in_le32((unsigned *)PCIC0_CFGDATA);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	res = in_le32((unsigned *)CONFIG_PCIC0_CFGDATA);
 	return res;
 }
 
 int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data)
 {
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	out_8((unsigned char *)PCIC0_CFGDATA + (where & 3), data);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	out_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3), data);
 	return 0;
 }
 
 int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data)
 {
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	out_le16((unsigned short *)PCIC0_CFGDATA + (where & 2), data);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	out_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2), data);
 	return 0;
 }
 
 int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data)
 {
-	out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
-	out_le32((unsigned *)PCIC0_CFGDATA, data);
+	out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
+	out_le32((unsigned *)CONFIG_PCIC0_CFGDATA, data);
 	return 0;
 }

Modified: trunk/coreboot-v2/src/arch/ppc/lib/printk_init.c
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/lib/printk_init.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/arch/ppc/lib/printk_init.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -12,7 +12,7 @@
 
 /* Keep together for sysctl support */
 
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 
 extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
 extern void uart8250_tx_byte(unsigned, unsigned char);
@@ -20,8 +20,8 @@
 void console_tx_byte(unsigned char byte)
 {
 	if (byte == '\n')
-		uart8250_tx_byte(TTYS0_BASE, '\r');
-	uart8250_tx_byte(TTYS0_BASE, byte);
+		uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
+	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
 }
 
 int do_printk(int msg_level, const char *fmt, ...)

Modified: trunk/coreboot-v2/src/boot/filo.c
===================================================================
--- trunk/coreboot-v2/src/boot/filo.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/boot/filo.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -14,11 +14,11 @@
 #define ENTER '\r'
 #define ESCAPE '\x1b'
 
-#ifndef AUTOBOOT_CMDLINE
+#ifndef CONFIG_AUTOBOOT_CMDLINE
 #define autoboot(mem)
 #endif
 
-#if !AUTOBOOT_DELAY
+#if !CONFIG_AUTOBOOT_DELAY
 #define autoboot_delay() 0 /* success */
 #endif
 
@@ -115,8 +115,8 @@
     free(boot_file);
 }
 
-#ifdef AUTOBOOT_CMDLINE
-#if AUTOBOOT_DELAY
+#ifdef CONFIG_AUTOBOOT_CMDLINE
+#if CONFIG_AUTOBOOT_DELAY
 static inline int autoboot_delay(void)
 {
     unsigned int timeout;
@@ -126,7 +126,7 @@
     key = 0;
 
     printk_info("Press <Enter> for default boot, or <Esc> for boot prompt... ");
-    for (sec = AUTOBOOT_DELAY; sec>0 && key==0; sec--) {
+    for (sec = CONFIG_AUTOBOOT_DELAY; sec>0 && key==0; sec--) {
 	printk_info("%d", sec);
 	timeout = 10;
 	while (timeout-- > 0) {
@@ -151,7 +151,7 @@
 	    return 0; /* default accepted */
     }
 }
-#endif /* AUTOBOOT_DELAY */
+#endif /* CONFIG_AUTOBOOT_DELAY */
 
 static void autoboot(struct lb_memory *mem)
 {
@@ -160,11 +160,11 @@
 	return;
 
     if (autoboot_delay()==0) {
-	printk_info("boot: %s\n", AUTOBOOT_CMDLINE);
-	boot(mem, AUTOBOOT_CMDLINE);
+	printk_info("boot: %s\n", CONFIG_AUTOBOOT_CMDLINE);
+	boot(mem, CONFIG_AUTOBOOT_CMDLINE);
     }
 }
-#endif /* AUTOBOOT_CMDLINE */
+#endif /* CONFIG_AUTOBOOT_CMDLINE */
 
 /* The main routine */
 int filo(struct lb_memory *mem)
@@ -179,8 +179,8 @@
     /* The above didn't work, ask user */
     while (havechar())
 	getchar();
-#ifdef AUTOBOOT_CMDLINE
-    strncpy(line, AUTOBOOT_CMDLINE, sizeof(line)-1);
+#ifdef CONFIG_AUTOBOOT_CMDLINE
+    strncpy(line, CONFIG_AUTOBOOT_CMDLINE, sizeof(line)-1);
     line[sizeof(line)-1] = '\0';
 #else
     line[0] = '\0';

Modified: trunk/coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- trunk/coreboot-v2/src/boot/hardwaremain.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/boot/hardwaremain.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -37,7 +37,7 @@
 #include <boot/tables.h>
 #include <boot/elf.h>
 #include <cbfs.h>
-#if HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME
 #include <arch/acpi.h>
 #endif
 
@@ -88,7 +88,7 @@
 	dev_initialize();
 	post_code(0x89);
 
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 	suspend_resume();
 	post_code(0x8a);
 #endif
@@ -98,7 +98,7 @@
 	 */
 	lb_mem = write_tables();
 #if CONFIG_CBFS == 1
-# if USE_FALLBACK_IMAGE == 1
+# if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_load_payload(lb_mem, "fallback/payload");
 # else
 	cbfs_load_payload(lb_mem, "normal/payload");

Modified: trunk/coreboot-v2/src/config/Config.lb
===================================================================
--- trunk/coreboot-v2/src/config/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/config/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,18 +1,18 @@
 ## This is Architecture independant part of the makefile
 
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_AP_CODE_IN_CAR
-uses ASSEMBLER_DEBUG
+uses CONFIG_ASSEMBLER_DEBUG
 
 makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
 makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
 makedefine GCC ?= $(CC)
 makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
 
-makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
+makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(CONFIG_ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
+makedefine CFLAGS := $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 
-if ASSEMBLER_DEBUG
+if CONFIG_ASSEMBLER_DEBUG
 makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm
 end
 
@@ -35,25 +35,25 @@
 
 makerule coreboot.strip  
 	depends	"coreboot" 
-	action	"$(OBJCOPY) -O binary coreboot coreboot.strip"
+	action	"$(CONFIG_OBJCOPY) -O binary coreboot coreboot.strip"
 end
 
 makerule coreboot.a
         depends "$(OBJECTS)"
         action  "rm -f coreboot.a"
-        action  "$(CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)"
+        action  "$(CONFIG_CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)"
 end
 
 
 makerule coreboot_ram.o
-	depends	"src/arch/$(ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" 
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(ARCH)/lib/c_start.o $(DRIVER) -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)"
+	depends	"src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" 
+	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)"
 end
 
 makerule coreboot_ram
 	depends	"coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" 
 	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
-	action 	"$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
+	action 	"$(CONFIG_CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
 end
 
 ##
@@ -64,7 +64,7 @@
 
 makerule coreboot_ram.bin 
 	depends	"coreboot_ram" 
-	action	"$(OBJCOPY) -O binary $< $@"
+	action	"$(CONFIG_OBJCOPY) -O binary $< $@"
 end
 
 makerule coreboot_ram.nrv2b 
@@ -85,18 +85,18 @@
 	makerule coreboot_apc.a
 		depends "apc_auto.o"
 		action  "rm -f coreboot_apc.a"
-		action  "$(CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o"
+		action  "$(CONFIG_CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o"
 	end
 
 	makerule coreboot_apc.o
-		depends "src/arch/$(ARCH)/lib/c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
+		depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)"
         	action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
 	end
 
 	makerule coreboot_apc
 		depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld ldoptions"
 		action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
-		action  "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
+		action  "$(CONFIG_CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
 	end
 
 	##
@@ -107,7 +107,7 @@
 
 	makerule coreboot_apc.bin
 		depends "coreboot_apc"
-		action  "$(OBJCOPY) -O binary $< $@"
+		action  "$(CONFIG_OBJCOPY) -O binary $< $@"
 	end
 
 	makerule coreboot_apc.nrv2b
@@ -129,14 +129,14 @@
 makerule coreboot   
 	depends	"crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
 	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
-	action	"$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
-	action 	"$(CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm"	
+	action	"$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
+	action 	"$(CONFIG_CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm"	
 end
 
 # the buildrom tool
 makerule buildrom 
 	depends	"$(TOP)/util/buildrom/buildrom.c" 
-	action	"$(HOSTCC) -o $@ $<"
+	action	"$(CONFIG_HOSTCC) -o $@ $<"
 end
 
 # Force crt0.s (which has build time version code in it to rebuild every time)
@@ -149,7 +149,7 @@
 # generate an assembly listing via -a switch.
 makerule crt0.o  
 	depends	"crt0.s" 
-	action	"$(CC) -Wa,-acdlns -c $(CPU_OPT) -o $@ $< >crt0.disasm"
+	action	"$(CC) -Wa,-acdlns -c $(CONFIG_CPU_OPT) -o $@ $< >crt0.disasm"
 end
 
 makerule etags   
@@ -178,21 +178,21 @@
 # be in a correct and valid state if it exists because the move is atomic.
 makerule ../romcc   
 	depends	"$(TOP)/util/romcc/romcc.c" 
-	action	"$(HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile"
+	action	"$(CONFIG_HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile"
 	action	"mv romcc.tmpfile $@"
 end
 
 makerule build_opt_tbl   
 	depends	"$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/coreboot_tables.h Makefile.settings Makefile"
-	action	"$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" 
+	action	"$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" 
 end
 
 makerule option_table.h option_table.c
-	depends	"build_opt_tbl $(MAINBOARD)/cmos.layout" 
-	action	"./build_opt_tbl --config $(MAINBOARD)/cmos.layout --header option_table.h --option option_table.c"
+	depends	"build_opt_tbl $(CONFIG_MAINBOARD)/cmos.layout" 
+	action	"./build_opt_tbl --config $(CONFIG_MAINBOARD)/cmos.layout --header option_table.h --option option_table.c"
 end
 
-if HAVE_OPTION_TABLE
+if CONFIG_HAVE_OPTION_TABLE
 object ./option_table.o 
 end
 

Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/config/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -61,12 +61,12 @@
 	export always
 	comment "X86 is the default"
 end
-define ARCH
+define CONFIG_ARCH
 	default "i386"
 	export always
 	comment "Default architecture is i386, options are alpha and ppc"
 end
-define HAVE_MOVNTI
+define CONFIG_HAVE_MOVNTI
 	default 0
 	export always
 	comment "This cpu supports the MOVNTI directive"
@@ -76,28 +76,28 @@
 # Build options
 ###############################################
 
-define CROSS_COMPILE
+define CONFIG_CROSS_COMPILE
 	default ""
 	export always
 	comment "Cross compiler prefix"
 end
 define CC
-	default "$(CROSS_COMPILE)gcc"
+	default "$(CONFIG_CROSS_COMPILE)gcc"
 	export always
 	comment "Target C Compiler"
 end
-define HOSTCC
+define CONFIG_HOSTCC
 	default "gcc"
 	export always
 	comment "Host C Compiler"
 end
-define CPU_OPT
+define CONFIG_CPU_OPT
 	default none
 	export used
 	comment "Additional per-cpu CFLAGS"
 end
-define OBJCOPY
-	default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
+define CONFIG_OBJCOPY
+	default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff"
 	export always
 	comment "Objcopy command"
 end
@@ -186,143 +186,143 @@
 # ROM image options
 ###############################################
 
-define HAVE_FALLBACK_BOOT
+define CONFIG_HAVE_FALLBACK_BOOT
 	format "%d"
 	default 0
 	export always
 	comment "Set if fallback booting required"
 end
-define HAVE_FAILOVER_BOOT
+define CONFIG_HAVE_FAILOVER_BOOT
 	format "%d"
 	default 0
 	export always
 	comment "Set if failover booting required"
 end
-define USE_FALLBACK_IMAGE
+define CONFIG_USE_FALLBACK_IMAGE
 	format "%d"
 	default 0
 	export used
 	comment "Set to build a fallback image"
 end
-define USE_FAILOVER_IMAGE
+define CONFIG_USE_FAILOVER_IMAGE
         format "%d"
         default 0
         export used
         comment "Set to build a failover image"
 end
-define FALLBACK_SIZE
+define CONFIG_FALLBACK_SIZE
 	default 65536
 	format "0x%x"
 	export used
 	comment "Default fallback image size"
 end
-define FAILOVER_SIZE
+define CONFIG_FAILOVER_SIZE
         default 0
         format "0x%x"
         export used
         comment "Default failover image size"
 end
-define ROM_SIZE
+define CONFIG_ROM_SIZE
 	default none
 	format "0x%x"
 	export used
 	comment "Size of your ROM"
 end
-define ROM_IMAGE_SIZE
+define CONFIG_ROM_IMAGE_SIZE
 	default 65535
 	format "0x%x"
 	export always
 	comment "Default image size"
 end
-define ROM_SECTION_SIZE
-	default {FALLBACK_SIZE}
+define CONFIG_ROM_SECTION_SIZE
+	default {CONFIG_FALLBACK_SIZE}
 	format "0x%x"
 	export used
 	comment "Default rom section size"
 end
-define ROM_SECTION_OFFSET
-	default {ROM_SIZE - FALLBACK_SIZE}
+define CONFIG_ROM_SECTION_OFFSET
+	default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE}
 	format "0x%x"
 	export used
 	comment "Default rom section offset"
 end
-define PAYLOAD_SIZE
-	default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
+define CONFIG_PAYLOAD_SIZE
+	default {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE}
 	format "0x%x"
 	export always
 	comment "Default payload size"
 end
-define _ROMBASE
-	default {PAYLOAD_SIZE}
+define CONFIG_ROMBASE
+	default {CONFIG_PAYLOAD_SIZE}
 	format "0x%x"
 	export always
 	comment "Base address of coreboot in ROM"
 end
-define _ROMSTART
+define CONFIG_ROMSTART
 	default none
 	format "0x%x"
 	export used
 	comment "Start address of coreboot in ROM"
 end
-define _RESET
-	default {_ROMBASE}
+define CONFIG_RESET
+	default {CONFIG_ROMBASE}
 	format "0x%x"
 	export always
 	comment "Hardware reset vector address"
 end
-define _EXCEPTION_VECTORS
-	default {_ROMBASE+0x100}
+define CONFIG_EXCEPTION_VECTORS
+	default {CONFIG_ROMBASE+0x100}
 	format "0x%x"
 	export always
 	comment "Address of exception vector table"
 end
-define STACK_SIZE
+define CONFIG_STACK_SIZE
 	default 0x2000
 	format "0x%x"
 	export always
 	comment "Default stack size"
 end
-define HEAP_SIZE
+define CONFIG_HEAP_SIZE
 	default 0x2000
 	format "0x%x"
 	export always
 	comment "Default heap size"
 end
-define _RAMBASE
+define CONFIG_RAMBASE
 	default none
 	format "0x%x"
 	export always
 	comment "Base address of coreboot in RAM"
 end
-define _RAMSTART
+define CONFIG_RAMSTART
 	default none
 	format "0x%x"
 	export used
 	comment "Start address of coreboot in RAM"
 end
-define USE_DCACHE_RAM
+define CONFIG_USE_DCACHE_RAM
 	default 0
 	export always
 	comment "Use data cache as temporary RAM if possible"
 end
-define CAR_FAM10
+define CONFIG_CAR_FAM10
 	default 0
 	export always
 	comment "AMD family 10 CAR requires additional setup"
 end
-define DCACHE_RAM_BASE
+define CONFIG_DCACHE_RAM_BASE
 	default 0xc0000
 	format "0x%x"
 	export always
 	comment "Base address of data cache when using it for temporary RAM"
 end
-define DCACHE_RAM_SIZE
+define CONFIG_DCACHE_RAM_SIZE
 	default 0x1000
 	format "0x%x"
 	export always
 	comment "Size of data cache when using it for temporary RAM"
 end
-define DCACHE_RAM_GLOBAL_VAR_SIZE
+define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 	default 0
 	format "0x%x"
 	export always
@@ -333,23 +333,23 @@
         export always
         comment "will copy coreboot_apc to AP cache ane execute in AP"
 end
-define MEM_TRAIN_SEQ
+define CONFIG_MEM_TRAIN_SEQ
         default 0
         export always
         comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
 end
-define WAIT_BEFORE_CPUS_INIT
+define CONFIG_WAIT_BEFORE_CPUS_INIT
         default 0
         export always
         comment "execute cpus_ready_for_init if it is set to 1"
 end
-define XIP_ROM_BASE
+define CONFIG_XIP_ROM_BASE
 	default 0
 	format "0x%x"
 	export used
 	comment "Start address of area to cache during coreboot execution directly from ROM"
 end
-define XIP_ROM_SIZE
+define CONFIG_XIP_ROM_SIZE
 	default 0
 	format "0x%x"
 	export used
@@ -372,14 +372,14 @@
 	export always
 	comment "Kilobytes of memory to initialized before executing code from RAM"
 end
-define HAVE_OPTION_TABLE
+define CONFIG_HAVE_OPTION_TABLE
 	default 0
 	export always
 	comment "Export CMOS option table"
 end
-define USE_OPTION_TABLE
+define CONFIG_USE_OPTION_TABLE
 	format "%d"
-	default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
+	default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE}
 	export always
 	comment "Use option table"
 end
@@ -387,19 +387,19 @@
 ###############################################
 # CMOS variable options
 ###############################################
-define LB_CKS_RANGE_START
+define CONFIG_LB_CKS_RANGE_START
 	default 49
 	format "%d"
 	export always
 	comment "First CMOS byte to use for coreboot options"
 end
-define LB_CKS_RANGE_END
+define CONFIG_LB_CKS_RANGE_END
 	default 125
 	format "%d"
 	export always
 	comment "Last CMOS byte to use for coreboot options"
 end
-define LB_CKS_LOC
+define CONFIG_LB_CKS_LOC
 	default 126
 	format "%d"
 	export always
@@ -411,8 +411,8 @@
 # Build targets
 ###############################################
 
-define CRT0
-	default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
+define CONFIG_CRT0
+	default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb"
 	export always
 	comment "Main initialization target"
 end
@@ -421,7 +421,7 @@
 # Debugging/Logging options
 ###############################################
 
-define DEBUG
+define CONFIG_DEBUG
 	default 0
 	export always
 	comment "Enable x86emu debugging code"
@@ -466,12 +466,12 @@
 	export always
 	comment "Log messages to ehci debug port console"
 end
-define DEFAULT_CONSOLE_LOGLEVEL
+define CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 	default 7
 	export always
 	comment "Console will log at this level unless changed"
 end
-define MAXIMUM_CONSOLE_LOGLEVEL
+define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 	default 8
 	export always
  	comment "Error messages up to this level can be printed"
@@ -481,29 +481,29 @@
 	export always
 	comment "Enable SERIAL POST codes"
 end
-define NO_POST
+define CONFIG_NO_POST
 	default none
 	export used
 	comment "Disable POST codes"
 end
-define TTYS0_BASE
+define CONFIG_TTYS0_BASE
 	default 0x3f8
 	format "0x%x"
 	export always
 	comment "Base address for 8250 uart for the serial console"
 end
-define TTYS0_BAUD
+define CONFIG_TTYS0_BAUD
 	default 115200
 	export always
 	comment "Default baud rate for serial console"
 end
-define TTYS0_DIV
+define CONFIG_TTYS0_DIV
 	default none
 	format "%d"
 	export used
 	comment "Allow UART divisor to be set explicitly"
 end
-define TTYS0_LCS
+define CONFIG_TTYS0_LCS
 	default 0x3
 	format "0x%x"
 	export always
@@ -515,7 +515,7 @@
 	export always
 	comment "use printk instead of print in CAR stage code"
 end
-define ASSEMBLER_DEBUG
+define CONFIG_ASSEMBLER_DEBUG
 	default 0
 	export always
 	comment "Create disassembly files for debugging"
@@ -525,35 +525,35 @@
 # Mainboard options
 ###############################################
 
-define MAINBOARD
+define CONFIG_MAINBOARD
 	default "Mainboard_not_set"
 	export always
 	comment "Mainboard name"
 end
-define MAINBOARD_PART_NUMBER
+define CONFIG_MAINBOARD_PART_NUMBER
 	default "Part_number_not_set"
 	export always
 	format "\"%s\""
 	comment "Part number of mainboard"
 end
-define MAINBOARD_VENDOR
+define CONFIG_MAINBOARD_VENDOR
 	default "Vendor_not_set"
 	export always
 	format "\"%s\""
 	comment "Vendor of mainboard"
 end
-define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 	default 0
 	export always
 	comment "PCI Vendor ID of mainboard manufacturer"
 end
-define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	default 0
 	format "0x%x"
 	export always
 	comment "PCI susbsystem device id assigned my mainboard manufacturer"
 end
-define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 	default none
 	export used
 	comment "Default power on after power fail setting"
@@ -597,27 +597,27 @@
 	export always
 	comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
 end
-define HAVE_MP_TABLE
+define CONFIG_HAVE_MP_TABLE
 	default none
 	export used
 	comment "Define to build an MP table"
 end
-define SERIAL_CPU_INIT
+define CONFIG_SERIAL_CPU_INIT
         default 1
         export always
         comment "Serialize CPU init"
 end
-define APIC_ID_OFFSET
+define CONFIG_APIC_ID_OFFSET
 	default 0
 	export always
 	comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
 end
-define ENABLE_APIC_EXT_ID
+define CONFIG_ENABLE_APIC_EXT_ID
 	default 0
 	export always
 	comment "Enable APIC ext id mode 8 bit"
 end
-define LIFT_BSP_APIC_ID
+define CONFIG_LIFT_BSP_APIC_ID
 	default 0
 	export always
 	comment "decide if we lift bsp apic id while ap apic id"
@@ -642,7 +642,7 @@
 	comment "Boot image is located in ROM" 
 end
 define CONFIG_ROM_PAYLOAD_START
-	default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
+	default {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1}
 	format "0x%x"
 	export always
 	comment "ROM stream start location"
@@ -692,19 +692,19 @@
 	export always
 	comment "The new CBFS file system"
 end
-define AUTOBOOT_DELAY
+define CONFIG_AUTOBOOT_DELAY
 	default 2
 	export always
 	comment "Delay (in seconds) before autobooting"
 end
-define AUTOBOOT_CMDLINE
+define CONFIG_AUTOBOOT_CMDLINE
 	default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
 	export always
 	format "\"%s\""
 	comment "Default command line when autobooting"
 end
 
-define USE_WATCHDOG_ON_BOOT
+define CONFIG_USE_WATCHDOG_ON_BOOT
 	default 0
 	export always
 	comment "Use the watchdog on booting"
@@ -744,17 +744,17 @@
 # IRQ options
 ###############################################
 
-define HAVE_PIRQ_TABLE
+define CONFIG_HAVE_PIRQ_TABLE
 	default none
 	export used
 	comment "Define if we have a PIRQ table"
 end
-define PIRQ_ROUTE
+define CONFIG_PIRQ_ROUTE
 	default 0
 	export always
 	comment "Define if we have a PIRQ table and want routing IRQs"
 end
-define IRQ_SLOT_COUNT
+define CONFIG_IRQ_SLOT_COUNT
 	default none
 	export used
 	comment "Number of IRQ slots"
@@ -779,17 +779,17 @@
 	export always
 	comment "Define to include IDE support"
 end
-define IDE_BOOT_DRIVE
+define CONFIG_IDE_BOOT_DRIVE
 	default 0
 	export always
 	comment "Disk number of boot drive"
 end
-define IDE_SWAB
+define CONFIG_IDE_SWAB
 	default none
 	export used
 	comment "Swap bytes when reading from IDE device"
 end
-define IDE_OFFSET
+define CONFIG_IDE_OFFSET
 	default 0
 	export always
 	comment "Sector at which to start searching for boot image"
@@ -799,49 +799,49 @@
 # Options for memory mapped I/O
 ###############################################
 
-define PCI_IO_CFG_EXT
+define CONFIG_PCI_IO_CFG_EXT
 	default 0
 	export always
 	comment "allow 4K register space via io CFG port"
 end
 
-define PCIC0_CFGADDR
+define CONFIG_PCIC0_CFGADDR
 	default none
 	format "0x%x"
 	export used
 	comment "Address of PCI Configuration Address Register"
 end
-define PCIC0_CFGDATA
+define CONFIG_PCIC0_CFGDATA
 	default none
 	format "0x%x"
 	export used
 	comment "Address of PCI Configuration Data Register"
 end
-define ISA_IO_BASE
+define CONFIG_ISA_IO_BASE
 	default none
 	format "0x%x"
 	export used
 	comment "Base address of PCI/ISA I/O address range"
 end
-define ISA_MEM_BASE
+define CONFIG_ISA_MEM_BASE
 	default none
 	format "0x%x"
 	export used
 	comment "Base address of PCI/ISA memory address range"
 end
-define PNP_CFGADDR
+define CONFIG_PNP_CFGADDR
 	default none
 	format "0x%x"
 	export used
 	comment "PNP Configuration Address Register offset"
 end
-define PNP_CFGDATA
+define CONFIG_PNP_CFGDATA
 	default none
 	format "0x%x"
 	export used
 	comment "PNP Configuration Data Register offset"
 end
-define _IO_BASE
+define CONFIG_IO_BASE
 	default none
 	format "0x%x"
 	export used
@@ -852,7 +852,7 @@
 # Options for embedded systems
 ###############################################
 
-define EMBEDDED_RAM_SIZE
+define CONFIG_EMBEDDED_RAM_SIZE
 	default none
 	export used
 	comment "Embedded boards generally have fixed RAM size"
@@ -868,27 +868,27 @@
 	comment "Compile in gdb stub support?"
 end
 
-define HAVE_INIT_TIMER
+define CONFIG_HAVE_INIT_TIMER
 	default 0
 	export always
 	comment "Have a init_timer function"
 end
-define HAVE_HARD_RESET
+define CONFIG_HAVE_HARD_RESET
 	default none
 	export used
 	comment "Have hard reset"
 end
-define HAVE_SMI_HANDLER
+define CONFIG_HAVE_SMI_HANDLER
 	default 0
 	export always
 	comment "Set, if the board needs an SMI handler"
 end
-define MEMORY_HOLE
+define CONFIG_MEMORY_HOLE
 	default none
 	export used
 	comment "Set to deal with memory hole"
 end
-define MAX_REBOOT_CNT
+define CONFIG_MAX_REBOOT_CNT
 	default 3
 	export always
 	comment "Set maximum reboots"
@@ -898,7 +898,7 @@
 # Misc device options
 ###############################################
 
-define HAVE_FANCTL
+define CONFIG_HAVE_FANCTL
 	default 0
 	export used
 	comment "Include board specific FAN control initialization"
@@ -908,7 +908,7 @@
 	export used
 	comment "Use timer2 to callibrate the x86 time stamp counter"
 end
-define INTEL_PPRO_MTRR
+define CONFIG_INTEL_PPRO_MTRR
 	default none
 	export used
 	comment ""
@@ -923,93 +923,93 @@
 	export used
 	comment "Implement udelay with x86 io registers"
 end
-define FAKE_SPDROM
+define CONFIG_FAKE_SPDROM
 	default 0
 	export always
 	comment "Use this to fake spd rom values"
 end
 
-define HAVE_ACPI_TABLES
+define CONFIG_HAVE_ACPI_TABLES
 	default 0
 	export always
 	comment "Define to build ACPI tables"
 end
 
-define HAVE_ACPI_RESUME
+define CONFIG_HAVE_ACPI_RESUME
 	default 0
 	export always
 	comment "Define to build ACPI with resume support"
 end
 
-define ACPI_SSDTX_NUM
+define CONFIG_ACPI_SSDTX_NUM
 	default 0
 	export always
 	comment "extra ssdt num for PCI Device"
 end
 
-define AGP_APERTURE_SIZE
+define CONFIG_AGP_APERTURE_SIZE
 	default none
 	export used
 	format "0x%x"
 	comment "AGP graphics virtual memory aperture size"
 end
 
-define HT_CHAIN_UNITID_BASE
+define CONFIG_HT_CHAIN_UNITID_BASE
 	default 1
 	export always
 	comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
 end
 
-define HT_CHAIN_END_UNITID_BASE
+define CONFIG_HT_CHAIN_END_UNITID_BASE
         default 0x20
         export always
-        comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
+        comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0"
 end
 
-define SB_HT_CHAIN_UNITID_OFFSET_ONLY
+define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
         default 1
         export always
         comment "this will decided if only offset SB hypertransport chain"
 end
 
-define SB_HT_CHAIN_ON_BUS0
+define CONFIG_SB_HT_CHAIN_ON_BUS0
         default 0 
         export always
         comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
 end
 
-define PCI_BUS_SEGN_BITS
+define CONFIG_PCI_BUS_SEGN_BITS
         default 0
         export always
         comment "It could be 0, 1, 2, 3 and 4 only"
 end
 
-define MMCONF_SUPPORT
+define CONFIG_MMCONF_SUPPORT
 	default 0
 	export always
 	comment "enable mmconfig for pci conf"
 end
 
-define MMCONF_SUPPORT_DEFAULT
+define CONFIG_MMCONF_SUPPORT_DEFAULT
 	default 0
 	export always
 	comment "enable mmconfig for pci conf"
 end
 
-define MMCONF_BASE_ADDRESS
+define CONFIG_MMCONF_BASE_ADDRESS
 	default none
 	format "0x%x"
 	export used
 	comment "enable mmconfig base address"
 end
 
-define HW_MEM_HOLE_SIZEK
+define CONFIG_HW_MEM_HOLE_SIZEK
         default 0
         export always
         comment "Opteron E0 later memory hole size in K, 0 mean disable"
 end
 
-define HW_MEM_HOLE_SIZE_AUTO_INC
+define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
         default 0
         export always
         comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
@@ -1021,62 +1021,62 @@
 	comment "using hole in MTRR instead of increasing method"
 end
 
-define K8_HT_FREQ_1G_SUPPORT
+define CONFIG_K8_HT_FREQ_1G_SUPPORT
 	default 0 
 	export always
 	comment "Optern E0 later could support 1G HT, but still depends MB design"
 end
 
-define K8_REV_F_SUPPORT
+define CONFIG_K8_REV_F_SUPPORT
         default 0
         export always
         comment "Opteron Rev F (DDR2) support"
 end
 
-define CBB
+define CONFIG_CBB
 	default 0
 	export always
 	comment "Opteron cpu bus num base"
 end
 
-define CDB
+define CONFIG_CDB
 	default 0x18
 	export always
 	comment "Opteron cpu device num base"
 end
 
-define HT3_SUPPORT
+define CONFIG_HT3_SUPPORT
 	default 0
 	export always
 	comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
 end
 
-define EXT_RT_TBL_SUPPORT
+define CONFIG_EXT_RT_TBL_SUPPORT
 	default 0
 	export always
 	comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
 end
 
-define EXT_CONF_SUPPORT
+define CONFIG_EXT_CONF_SUPPORT
 	default 0
 	export always
 	comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
 end
 
-define DIMM_SUPPORT
+define CONFIG_DIMM_SUPPORT
         default 0x0108
 	format "0x%x"
         export always
         comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
 end
 
-define CPU_SOCKET_TYPE
+define CONFIG_CPU_SOCKET_TYPE
 	default 0x10
 	export always
 	comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
 end
 
-define CPU_ADDR_BITS
+define CONFIG_CPU_ADDR_BITS
 	default 36
 	export always
 	comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
@@ -1137,14 +1137,14 @@
 	comment "use AMD MCT to init RAM instead of native code"
 end
 
-define AMD_UCODE_PATCH_FILE
+define CONFIG_AMD_UCODE_PATCH_FILE
 	default none
 	export used
 	format "\"%s\""
 	comment "name of the microcode patch file"	
 end
 
-define K8_MEM_BANK_B_ONLY
+define CONFIG_K8_MEM_BANK_B_ONLY
 	default 0
 	export always
 	comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
@@ -1162,19 +1162,19 @@
         comment "GFX UMA"
 end
 
-define HAVE_MAINBOARD_RESOURCES
+define CONFIG_HAVE_MAINBOARD_RESOURCES
 	default 0
 	export always
 	comment "Enable if the mainboard/chipset requires extra entries in the memory map"
 end
 
-define HAVE_LOW_TABLES
+define CONFIG_HAVE_LOW_TABLES
 	default 1
 	export always
 	comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
 end
 
-define HAVE_HIGH_TABLES
+define CONFIG_HAVE_HIGH_TABLES
 	default 0
 	export always
 	comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"

Modified: trunk/coreboot-v2/src/config/coreboot_apc.ld
===================================================================
--- trunk/coreboot-v2/src/config/coreboot_apc.ld	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/config/coreboot_apc.ld	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
 /*
  *	Memory map:
  *
- *	DCACHE_RAM_BASE		
+ *	CONFIG_DCACHE_RAM_BASE		
  *				: data segment
  *				: bss segment
  *				: heap
@@ -28,7 +28,7 @@
 
 SECTIONS
 {
-	. = DCACHE_RAM_BASE;
+	. = CONFIG_DCACHE_RAM_BASE;
 	/*
 	 * First we place the code and read only data (typically const declared).
 	 * This get placed in rom.
@@ -90,7 +90,7 @@
 	_ram_seg = _text; 
 	_eram_seg = _eheap;
 
-	_bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
+	_bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
 
 	/DISCARD/ : {
 		*(.comment)

Modified: trunk/coreboot-v2/src/config/coreboot_ram.ld
===================================================================
--- trunk/coreboot-v2/src/config/coreboot_ram.ld	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/config/coreboot_ram.ld	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
 /*
  *	Memory map:
  *
- *	_RAMBASE		
+ *	CONFIG_RAMBASE		
  *				: data segment
  *				: bss segment
  *				: heap
@@ -27,7 +27,7 @@
 
 SECTIONS
 {
-	. = _RAMBASE;
+	. = CONFIG_RAMBASE;
 	/*
 	 * First we place the code and read only data (typically const declared).
 	 * This get placed in rom.
@@ -99,18 +99,18 @@
 	}
 	_ebss = .;
 	_end = .;
-	. = ALIGN(STACK_SIZE);
+	. = ALIGN(CONFIG_STACK_SIZE);
 	_stack = .;
 	.stack . : {
 		/* Reserve a stack for each possible cpu */
 		/* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/
-		. = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? STACK_SIZE : (CONFIG_MAX_CPUS*STACK_SIZE);
+		. = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
 	}
 	_estack = .;
         _heap = .;
         .heap . : {
-                /* Reserve HEAP_SIZE bytes for the heap */
-                . = HEAP_SIZE ;
+                /* Reserve CONFIG_HEAP_SIZE bytes for the heap */
+                . = CONFIG_HEAP_SIZE ;
                 . = ALIGN(4);
         }
         _eheap = .;
@@ -122,7 +122,7 @@
 
 	_bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK");
 
-        _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M");
+        _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set CONFIG_RAMBASE more than 1M");
 
 	/DISCARD/ : {
 		*(.comment)

Modified: trunk/coreboot-v2/src/config/failovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/failovercalculation.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/config/failovercalculation.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -2,20 +2,20 @@
 ## Compute the location and size of where this firmware image
 ## (coreboot plus bootloader) will live in the boot rom chip.
 ##
-if USE_FAILOVER_IMAGE
-	default ROM_SECTION_SIZE   = FAILOVER_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
+if CONFIG_USE_FAILOVER_IMAGE
+	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FAILOVER_SIZE
+	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FAILOVER_SIZE )
 else
-    if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+    if CONFIG_USE_FALLBACK_IMAGE
+	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
     else
 	if CONFIG_CBFS
-		default ROM_SECTION_SIZE   = FALLBACK_SIZE
-		default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+		default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+		default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
 	else
-		default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
-		default ROM_SECTION_OFFSET = 0
+		default CONFIG_ROM_SECTION_SIZE   = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
+		default CONFIG_ROM_SECTION_OFFSET = 0
 	end
     end
 end
@@ -24,29 +24,29 @@
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
-## XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
+## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
 ##
 
-if USE_FAILOVER_IMAGE
-	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+if CONFIG_USE_FAILOVER_IMAGE
+	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
 else
-    if USE_FALLBACK_IMAGE
-	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+    if CONFIG_USE_FALLBACK_IMAGE
+	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE + CONFIG_FAILOVER_SIZE)
     else
-	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
     end
 end
 

Modified: trunk/coreboot-v2/src/config/nofailovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/nofailovercalculation.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/config/nofailovercalculation.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -2,16 +2,16 @@
 ## Compute the location and size of where this firmware image
 ## (coreboot plus bootloader) will live in the boot rom chip.
 ##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+if CONFIG_USE_FALLBACK_IMAGE
+	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
 else
 	if CONFIG_CBFS
-		default ROM_SECTION_SIZE   = FALLBACK_SIZE
-		default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE )
+		default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+		default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE )
 	else
-		default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-		default ROM_SECTION_OFFSET = 0
+		default CONFIG_ROM_SECTION_SIZE   = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
+		default CONFIG_ROM_SECTION_OFFSET = 0
 	end
 end
 
@@ -19,19 +19,19 @@
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
-## XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
+## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
 ##
-default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )

Modified: trunk/coreboot-v2/src/console/console.c
===================================================================
--- trunk/coreboot-v2/src/console/console.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/console/console.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -15,7 +15,7 @@
 {
 	struct console_driver *driver;
 	if(get_option(&console_loglevel, "debug_level"))
-		console_loglevel=DEFAULT_CONSOLE_LOGLEVEL;
+		console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 	
 	for(driver = console_drivers; driver < econsole_drivers; driver++) {
 		if (!driver->init)
@@ -83,7 +83,7 @@
  */
 void post_code(uint8_t value)
 {
-#if !defined(NO_POST) || NO_POST==0
+#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
 #if CONFIG_SERIAL_POST==1
 	printk_emerg("POST: 0x%02x\n", value);
 #endif

Modified: trunk/coreboot-v2/src/console/printk.c
===================================================================
--- trunk/coreboot-v2/src/console/printk.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/console/printk.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,10 +17,10 @@
 
 /* Keep together for sysctl support */
 
-int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL;
 int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL;
-int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 
 void display(char*);
 extern int vtxprintf(void (*)(unsigned char), const char *, va_list);

Modified: trunk/coreboot-v2/src/console/uart8250_console.c
===================================================================
--- trunk/coreboot-v2/src/console/uart8250_console.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/console/uart8250_console.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -3,54 +3,54 @@
 #include <pc80/mc146818rtc.h>
 
 /* Base Address */
-#ifndef TTYS0_BASE
-#define TTYS0_BASE 0x3f8
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE 0x3f8
 #endif
 
-#ifndef TTYS0_BAUD
-#define TTYS0_BAUD 115200
+#ifndef CONFIG_TTYS0_BAUD
+#define CONFIG_TTYS0_BAUD 115200
 #endif
 
-#ifndef TTYS0_DIV
-#if ((115200%TTYS0_BAUD) != 0)
+#ifndef CONFIG_TTYS0_DIV
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
 #error Bad ttys0 baud rate
 #endif
-#define TTYS0_DIV	(115200/TTYS0_BAUD)
+#define CONFIG_TTYS0_DIV	(115200/CONFIG_TTYS0_BAUD)
 #endif
 
 /* Line Control Settings */
-#ifndef TTYS0_LCS
+#ifndef CONFIG_TTYS0_LCS
 /* Set 8bit, 1 stop bit, no parity */
-#define TTYS0_LCS	0x3
+#define CONFIG_TTYS0_LCS	0x3
 #endif
 
-#define UART_LCS	TTYS0_LCS
+#define UART_LCS	CONFIG_TTYS0_LCS
 
 static void ttyS0_init(void)
 {
 	static const unsigned char div[8]={1,2,3,6,12,24,48,96};
 	int b_index=0;
-	unsigned int divisor=TTYS0_DIV;
+	unsigned int divisor=CONFIG_TTYS0_DIV;
 
 	if(get_option(&b_index,"baud_rate")==0) {
 		divisor=div[b_index];
 	}
-	uart8250_init(TTYS0_BASE, divisor, TTYS0_LCS);
+	uart8250_init(CONFIG_TTYS0_BASE, divisor, CONFIG_TTYS0_LCS);
 }
 
 static void ttyS0_tx_byte(unsigned char data) 
 {
-	uart8250_tx_byte(TTYS0_BASE, data);
+	uart8250_tx_byte(CONFIG_TTYS0_BASE, data);
 }
 
 static unsigned char ttyS0_rx_byte(void) 
 {
-	return uart8250_rx_byte(TTYS0_BASE);
+	return uart8250_rx_byte(CONFIG_TTYS0_BASE);
 }
 
 static int ttyS0_tst_byte(void) 
 {
-	return uart8250_can_rx_byte(TTYS0_BASE);
+	return uart8250_can_rx_byte(CONFIG_TTYS0_BASE);
 }
 
 static const struct console_driver uart8250_console __console = {

Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,13 +18,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CacheSize DCACHE_RAM_SIZE
+#define CacheSize CONFIG_DCACHE_RAM_SIZE
 #define CacheBase (0xd0000 - CacheSize)
 
 /* leave some space for global variable to pass to RAM stage */
-#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
+#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 
-/* for CAR_FAM10 */
+/* for CONFIG_CAR_FAM10 */
 #define CacheSizeAPStack 0x400 /* 1K */
 
 #define MSR_FAM10      0xC001102A
@@ -72,7 +72,7 @@
 	cvtsd2si %xmm3, %ebx
 
 	/* hope we can skip the double set for normal part */
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 	/* check if cpu_init_detected */
 	movl	$MTRRdefType_MSR, %ecx
@@ -248,10 +248,10 @@
 	xorl	%edx, %edx
 	movl	$(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
 	wrmsr
-#endif /*  USE_FAILOVER_IMAGE == 1*/
+#endif /*  CONFIG_USE_FAILOVER_IMAGE == 1*/
 
 
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0))
+#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
 	/* disable cache */
 	movl	%cr0, %eax
 	orl		$(1 << 30),%eax
@@ -259,25 +259,25 @@
 
 #endif
 
-#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* enable write base caching so we can do execute in place
 	 * on the flash rom.
 	 */
 	movl	$0x202, %ecx
 	xorl	%edx, %edx
-	movl	$(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	movl	$(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$0x203, %ecx
-	movl	$0xff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for K8 (CPU_ADDR_BITS = 40) */
+	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
 	jmp_if_k8(wbcache_post_fam10_setup)
-	movl	$0xffff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for FAM10 (CPU_ADDR_BITS = 48) */
+	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
 wbcache_post_fam10_setup:
-	movl	$(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 	/* Set the default memory type and enable fixed and variable MTRRs */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
@@ -313,7 +313,7 @@
 	movb	$0xA2, %al
 	outb	%al, $0x80
 
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 		/* Read the range with lodsl*/
 	cld
 	movl	$CacheBase, %esi
@@ -325,7 +325,7 @@
 	xorl	%eax, %eax
 	rep		stosl
 
-#endif /*USE_FAILOVER_IMAGE == 1*/
+#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
 
 	/* set up the stack pointer */
 	movl	$(CacheBase + CacheSize - GlobalVarSize), %eax

Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -7,11 +7,11 @@
 	// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
 	// so noline clear_init_ram
 
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 	/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
-	clear_memory( _RAMBASE,  (CONFIG_LB_MEM_TOPK << 10) -  _RAMBASE - DCACHE_RAM_SIZE);
+	clear_memory( CONFIG_RAMBASE,  (CONFIG_LB_MEM_TOPK << 10) -  CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
 #else
-        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
+        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE));
 #endif
 }
 

Modified: trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -8,7 +8,7 @@
 
 static void copy_and_run(void)
 {
-# if USE_FALLBACK_IMAGE == 1
+# if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_and_run_core("fallback/coreboot_ram", 0);
 # else
       	cbfs_and_run_core("normal/coreboot_ram", 0);
@@ -19,7 +19,7 @@
 
 static void copy_and_run_ap_code_in_car(unsigned ret_addr)
 {
-# if USE_FALLBACK_IMAGE == 1
+# if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_and_run_core("fallback/coreboot_apc", ret_addr);
 # else
       	cbfs_and_run_core("normal/coreboot_apc", ret_addr);

Modified: trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -16,7 +16,7 @@
         "xorl    %edx, %edx\n\t"
         "xorl    %eax, %eax\n\t"
 	"wrmsr\n\t"
-#if DCACHE_RAM_SIZE > 0x8000
+#if CONFIG_DCACHE_RAM_SIZE > 0x8000
 	"movl    $0x268, %ecx\n\t"  /* fix4k_c0000*/
         "wrmsr\n\t"
 #endif

Modified: trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -64,7 +64,7 @@
 	
 	set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
 
-//	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00);
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
 	print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
 
 	/* from here don't store more data in CAR */
@@ -76,14 +76,14 @@
         );
 #endif
 
-        memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
+        memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
 //        dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
 
         __asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
+                /* set new esp */ /* before CONFIG_RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
         ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
 #if 0
         __asm__ volatile (
@@ -102,18 +102,18 @@
 	disable_cache_as_ram_bsp();  
 
         print_debug("Clearing initial memory region: ");
-        clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
+        clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
         print_debug("Done\r\n");
 
 //	dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
 
-#ifndef MEM_TRAIN_SEQ
-#define MEM_TRAIN_SEQ 0
+#ifndef CONFIG_MEM_TRAIN_SEQ
+#define CONFIG_MEM_TRAIN_SEQ 0
 #endif
         set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
-#if MEM_TRAIN_SEQ == 1
-//	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+#if CONFIG_MEM_TRAIN_SEQ == 1
+//	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         // wait for ap memory to trained
 //        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c

Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -110,7 +110,7 @@
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
+		printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
 		enable_apic_ext_id(nodes);
 	}
 	

Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,7 +19,7 @@
 #if SET_NB_CFG_54 == 1
 static inline uint8_t set_apicid_cpuid_lo(void)
 {
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
         if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
 #endif
 
@@ -56,7 +56,7 @@
 	unsigned nodes;
 	unsigned nodeid;
 
-	if (HAVE_OPTION_TABLE &&
+	if (CONFIG_HAVE_OPTION_TABLE &&
 	    read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0)  {
 		return; // disable dual_core
 	}
@@ -70,7 +70,7 @@
 	}
 
 }
-#if USE_DCACHE_RAM == 0
+#if CONFIG_USE_DCACHE_RAM == 0
 static void do_k8_init_and_stop_secondaries(void)
 {
 	struct node_core_id id;
@@ -106,22 +106,22 @@
 	pci_write_config32(dev_f0, 0x68, val);
 
 	/* Set the lapicid */
-        #if (ENABLE_APIC_EXT_ID == 1)
+        #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
                 unsigned initial_apicid = get_initial_apicid();
-                #if LIFT_BSP_APIC_ID == 0
+                #if CONFIG_LIFT_BSP_APIC_ID == 0
                 if( initial_apicid != 0 ) // other than bsp
                 #endif
                 {
                                 /* use initial apic id to lift it */
                                 uint32_t dword = lapic_read(LAPIC_ID);
                                 dword &= ~(0xff<<24);
-                                dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24);
+                                dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
 
                                 lapic_write(LAPIC_ID, dword);
                 }
 
-                #if LIFT_BSP_APIC_ID == 1
-                bsp_apicid += APIC_ID_OFFSET;
+                #if CONFIG_LIFT_BSP_APIC_ID == 1
+                bsp_apicid += CONFIG_APIC_ID_OFFSET;
                 #endif
 
         #endif

Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,13 +17,13 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-uses HAVE_INIT_TIMER
-uses HAVE_MOVNTI
-uses CPU_ADDR_BITS
+uses CONFIG_HAVE_INIT_TIMER
+uses CONFIG_HAVE_MOVNTI
+uses CONFIG_CPU_ADDR_BITS
 
-default HAVE_INIT_TIMER=1
-default HAVE_MOVNTI=1
-default CPU_ADDR_BITS=48
+default CONFIG_HAVE_INIT_TIMER=1
+default CONFIG_HAVE_MOVNTI=1
+default CONFIG_CPU_ADDR_BITS=48
 dir /cpu/x86/tsc
 dir /cpu/x86/fpu
 dir /cpu/x86/mmx

Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,7 +19,7 @@
 
 #include "defaults.h"
 
-//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
+//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef FAM10_SET_FIDVID
 	#define FAM10_SET_FIDVID 1
 #endif
@@ -58,13 +58,13 @@
 static void init_fidvid_stage2(u32 apicid, u32 nodeid);
 void cpuSetAMDMSR(void);
 
-#if PCI_IO_CFG_EXT == 1
+#if CONFIG_PCI_IO_CFG_EXT == 1
 static void set_EnableCf8ExtCfg(void)
 {
 	// set the NB_CFG[46]=1;
 	msr_t msr;
 	msr = rdmsr(NB_CFG_MSR);
-	// EnableCf8ExtCfg: We need that to access PCI_IO_CFG_EXT 4K range
+	// EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
 	msr.hi |= (1<<(46-32));
 	wrmsr(NB_CFG_MSR, msr);
 }
@@ -80,12 +80,12 @@
 
 static void set_pci_mmio_conf_reg(void)
 {
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	msr_t msr;
 	msr = rdmsr(0xc0010058);
 	msr.lo &= ~(0xfff00000 | (0xf << 2));
 	// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
-	msr.lo |= ((8+PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
+	msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
 	msr.hi &= ~(0x0000ffff);
 	msr.hi |= (PCI_MMIO_BASE >> (32-8));
 	wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
@@ -168,11 +168,11 @@
 		for (j = jstart; j <= jend; j++) {
 			ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64);
 
-		#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
-			#if LIFT_BSP_APIC_ID == 0
+		#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
+			#if CONFIG_LIFT_BSP_APIC_ID == 0
 			if( (i != 0) || (j != 0)) /* except bsp */
 			#endif
-				ap_apicid += APIC_ID_OFFSET;
+				ap_apicid += CONFIG_APIC_ID_OFFSET;
 		#endif
 
 			if(ap_apicid == bsp_apicid) continue;
@@ -307,8 +307,8 @@
 }
 
 
-#ifndef MEM_TRAIN_SEQ
-#define MEM_TRAIN_SEQ 0
+#ifndef CONFIG_MEM_TRAIN_SEQ
+#define CONFIG_MEM_TRAIN_SEQ 0
 #endif
 
 #if RAMINIT_SYSINFO == 1
@@ -337,7 +337,7 @@
 	if(id.coreid == 0) {
 		set_apicid_cpuid_lo(); /* only set it on core0 */
 		set_EnableCf8ExtCfg(); /* only set it on core0 */
-		#if (ENABLE_APIC_EXT_ID == 1)
+		#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
 		enable_apic_ext_id(id.nodeid);
 		#endif
 	}
@@ -345,23 +345,23 @@
 	enable_lapic();
 
 
-#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
+#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
 	u32 initial_apicid = get_initial_apicid();
 
-	#if LIFT_BSP_APIC_ID == 0
+	#if CONFIG_LIFT_BSP_APIC_ID == 0
 	if( initial_apicid != 0 ) // other than bsp
 	#endif
 	{
 		/* use initial apic id to lift it */
 		u32 dword = lapic_read(LAPIC_ID);
 		dword &= ~(0xff << 24);
-		dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff) << 24);
+		dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
 
 		lapic_write(LAPIC_ID, dword);
 	}
 
-	#if LIFT_BSP_APIC_ID == 1
-	bsp_apicid += APIC_ID_OFFSET;
+	#if CONFIG_LIFT_BSP_APIC_ID == 1
+	bsp_apicid += CONFIG_APIC_ID_OFFSET;
 	#endif
 
 #endif
@@ -478,8 +478,8 @@
 	/* Enable routing table */
 	printk_debug("Start node %02x", node);
 
-#if CAR_FAM10 == 1
-	/* For CAR_FAM10 support, we need to set Dram base/limit for the new node */
+#if CONFIG_CAR_FAM10 == 1
+	/* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */
 	pci_write_config32(NODE_MP(node), 0x44, 0);
 	pci_write_config32(NODE_MP(node), 0x40, 3);
 #endif

Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -47,7 +47,7 @@
  * 00100F62h (DA-C2)     1062h                  0100009Fh
  */
 
-#include AMD_UCODE_PATCH_FILE
+#include CONFIG_AMD_UCODE_PATCH_FILE
 
 #endif
 	/*  Dummy terminator  */

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,10 +1,10 @@
-uses HAVE_INIT_TIMER
-uses HAVE_MOVNTI
-uses CPU_ADDR_BITS
+uses CONFIG_HAVE_INIT_TIMER
+uses CONFIG_HAVE_MOVNTI
+uses CONFIG_CPU_ADDR_BITS
 
-default HAVE_INIT_TIMER=1
-default HAVE_MOVNTI=1
-default CPU_ADDR_BITS=40
+default CONFIG_HAVE_INIT_TIMER=1
+default CONFIG_HAVE_MOVNTI=1
+default CONFIG_CPU_ADDR_BITS=40
 dir /cpu/x86/tsc
 dir /cpu/x86/fpu
 dir /cpu/x86/mmx

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/fidvid.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -73,7 +73,7 @@
 //		dword = 0x00070000; /* enable FID/VID change */
 		pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
 
-#if HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME
 		dword = 0x21132113;
 #else
 		dword = 0x00132113;

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,6 +1,6 @@
-//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
+//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef K8_SET_FIDVID
-	#if K8_REV_F_SUPPORT == 0
+	#if CONFIG_K8_REV_F_SUPPORT == 0
 		#define K8_SET_FIDVID 0
 	#else
 		// for rev F, need to set FID to max
@@ -72,7 +72,7 @@
 	nodes = get_nodes();
 
         disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1
+#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
         if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core
                 disable_siblings = 1;
         }
@@ -87,7 +87,7 @@
                 j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
                 if(nb_cfg_54) {
  	               if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation 
-                       #if K8_REV_F_SUPPORT == 0
+                       #if CONFIG_K8_REV_F_SUPPORT == 0
         	               e0_later_single_core = is_e0_later_in_bsp(i);  // single core
                        #else
                                e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
@@ -119,11 +119,11 @@
 
                         ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
 
-                #if (ENABLE_APIC_EXT_ID == 1)
-			#if LIFT_BSP_APIC_ID == 0
+                #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+			#if CONFIG_LIFT_BSP_APIC_ID == 0
 			if( (i!=0) || (j!=0)) /* except bsp */
 			#endif
-                        	ap_apicid += APIC_ID_OFFSET;
+                        	ap_apicid += CONFIG_APIC_ID_OFFSET;
                 #endif
 
 			if(ap_apicid == bsp_apicid) continue;
@@ -238,12 +238,12 @@
 	stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
 }
 
-#ifndef MEM_TRAIN_SEQ
-#define MEM_TRAIN_SEQ 0
+#ifndef CONFIG_MEM_TRAIN_SEQ
+#define CONFIG_MEM_TRAIN_SEQ 0
 #endif
 
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); 
 #endif
 
@@ -268,7 +268,7 @@
                 /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started  */
 		if(id.coreid == 0) {
                 	set_apicid_cpuid_lo(); /* only set it on core0 */
-			#if ENABLE_APIC_EXT_ID == 1
+			#if CONFIG_ENABLE_APIC_EXT_ID == 1
                         enable_apic_ext_id(id.nodeid);
 			#endif
                 }
@@ -276,22 +276,22 @@
 		enable_lapic();
 //              init_timer(); // We need TMICT to pass msg for FID/VID change
 
-        #if (ENABLE_APIC_EXT_ID == 1)
+        #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
 		unsigned initial_apicid = get_initial_apicid();	
-                #if LIFT_BSP_APIC_ID == 0
+                #if CONFIG_LIFT_BSP_APIC_ID == 0
                 if( initial_apicid != 0 ) // other than bsp
                 #endif
                 {
                                 /* use initial apic id to lift it */
                                 uint32_t dword = lapic_read(LAPIC_ID);
                                 dword &= ~(0xff<<24);
-                                dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24);
+                                dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
 
                                 lapic_write(LAPIC_ID, dword);
                 }
 
-                #if LIFT_BSP_APIC_ID == 1
-                bsp_apicid += APIC_ID_OFFSET;
+                #if CONFIG_LIFT_BSP_APIC_ID == 1
+                bsp_apicid += CONFIG_APIC_ID_OFFSET;
                 #endif
 
         #endif
@@ -346,7 +346,7 @@
 			}
                         lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
                         set_init_ram_access();
-	#if MEM_TRAIN_SEQ == 1
+	#if CONFIG_MEM_TRAIN_SEQ == 1
 			train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU);
 	#endif
 

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -32,15 +32,15 @@
 
 void cpus_ready_for_init(void)
 {
-#if MEM_TRAIN_SEQ == 1
-        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+#if CONFIG_MEM_TRAIN_SEQ == 1
+        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
         // wait for ap memory to trained
         wait_all_core0_mem_trained(sysinfox);
 #endif
 }
 
 
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 int is_e0_later_in_bsp(int nodeid)
 {
         uint32_t val;
@@ -67,7 +67,7 @@
 }
 #endif
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 int is_cpu_f0_in_bsp(int nodeid)
 {
         uint32_t dword;
@@ -289,8 +289,8 @@
 	startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
 	endk   = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
 
-#if HW_MEM_HOLE_SIZEK != 0
-	#if K8_REV_F_SUPPORT == 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+	#if CONFIG_K8_REV_F_SUPPORT == 0
         if (!is_cpu_pre_e0()) 
 	{
 	#endif
@@ -300,7 +300,7 @@
                 if(val & 1) {
         	        hole_startk = ((val & (0xff<<24)) >> 10);
                 }
-	#if K8_REV_F_SUPPORT == 0
+	#if CONFIG_K8_REV_F_SUPPORT == 0
         }
 	#endif
 #endif
@@ -322,7 +322,7 @@
 	disable_lapic();
 
 	/* Walk through 2M chunks and zero them */
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 	/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
         if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
 		        for(basek = begink; basek < hole_startk;
@@ -368,7 +368,7 @@
 static inline void k8_errata(void)
 {
 	msr_t msr;
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 	if (is_cpu_pre_c0()) {
 		/* Erratum 63... */
 		msr = rdmsr(HWCR_MSR);
@@ -438,7 +438,7 @@
  	}
 #endif
 
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 	if (!is_cpu_pre_e0()) 
 #endif
 	{
@@ -453,7 +453,7 @@
 	msr.lo |= 1 << 6;
 	wrmsr(HWCR_MSR, msr);
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
         /* Erratum 131... */
         msr = rdmsr(NB_CFG_MSR);
         msr.lo |= 1 << 20;
@@ -478,7 +478,7 @@
 	unsigned siblings;
 #endif
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 	struct cpuinfo_x86 c;
 	
 	get_fms(&c, dev->device);
@@ -564,7 +564,7 @@
 };
 
 static struct cpu_device_id cpu_table[] = {
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 	{ X86_VENDOR_AMD, 0xf40 },   /* SH-B0 (socket 754) */
 	{ X86_VENDOR_AMD, 0xf50 },   /* SH-B0 (socket 940) */
 	{ X86_VENDOR_AMD, 0xf51 },   /* SH-B3 (socket 940) */
@@ -606,7 +606,7 @@
 	{ X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
 #endif
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 	/*
 	 * AMD F0 support.
 	 *

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_update_microcode.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -52,13 +52,13 @@
 
 static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
 
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 	#include "microcode_rev_c.h"
 	#include "microcode_rev_d.h"
 	#include "microcode_rev_e.h"
 #endif
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 //	#include "microcode_rev_f.h"
 #endif
         /*  Dummy terminator  */
@@ -70,7 +70,7 @@
 
 static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
 	static unsigned id_mapping_table[] = {
-	#if K8_REV_F_SUPPORT == 0
+	#if CONFIG_K8_REV_F_SUPPORT == 0
 	        0x0f48, 0x0048,
 	        0x0f58, 0x0048,
 
@@ -93,7 +93,7 @@
 	        0x20fb1, 0x0210,
 	#endif
 
-	#if K8_REV_F_SUPPORT == 1
+	#if CONFIG_K8_REV_F_SUPPORT == 1
 	
 	#endif
 

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/powernow_acpi.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/powernow_acpi.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/powernow_acpi.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -169,7 +169,7 @@
 	cpuid1 = cpuid(0x80000001);
 	pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
 	for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
-		if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
+		if (TDP[index].socket_type == CONFIG_CPU_SOCKET_TYPE &&
 		    TDP[index].cmp_cap == cmp_cap &&
 		    TDP[index].pwr_lmt == pwr_lmt) {
 			power_limit = TDP[index].power_limit;

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -41,7 +41,7 @@
  * your mainboard will not be posted on the AMD Recommended Motherboard Website
  */
 
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 static char *processor_names[]={
 	/* 0x00 */ "AMD Engineering Sample",
 	/* 0x01-0x03 */ NULL, NULL, NULL,
@@ -163,7 +163,7 @@
 	char program_string[48];
 	unsigned int *program_values = (unsigned int *)program_string;
 
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 	/* Find out which CPU brand it is */
 	EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;
 	BrandId = cpuid_ebx(0x80000001) & 0xffff;
@@ -187,7 +187,7 @@
 		processor_name_string = "AMD Processor model unknown";
 #endif
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 	u32 Socket;
 	u32 CmpCap;
 	u32 PwrLmt;
@@ -343,7 +343,7 @@
 	for (i=0; i<47; i++) { // 48 -1 
 		if(program_string[i] == program_string[i+1]) {
 			switch (program_string[i]) {
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 			case 'X': ModelNumber = 22+ NN; break;
 			case 'Y': ModelNumber = 38 + (2*NN); break;
 			case 'Z':
@@ -352,7 +352,7 @@
 			case 'V': ModelNumber =  9 + NN; break;
 #endif
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 			case 'R': ModelNumber = NN - 1; break;
 			case 'P': ModelNumber = 26 + NN; break;
 			case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break;

Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -271,7 +271,7 @@
 	//rom = 0xfff80000;
 	//rom = 0xfffc0000;
 	/* the VSA starts at the base of rom - 64 */
-	rom = ((unsigned long) 0) - (ROM_SIZE  + 64*1024);
+	rom = ((unsigned long) 0) - (CONFIG_ROM_SIZE  + 64*1024);
 
 	buf = (unsigned char *) 0x60000;
 	olen = unrv2b((uint8_t *)rom, buf, &ilen);

Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
-#define	LX_STACK_END		LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
+#define	LX_STACK_BASE		CONFIG_DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
+#define	LX_STACK_END		LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
 
 #define	LX_NUM_CACHELINES	0x080	/* there are 128lines per way */
 #define	LX_CACHELINE_SIZE	0x020	/* there are 32bytes per line */
@@ -82,7 +82,7 @@
 	xorl	%esi, %esi
 	xorl	%ebp, %ebp
 
-	/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
+	/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
 	/* remember,  there is NO stack yet... */
 
 	/* Tell cache we want to fill WAY 0 starting at the top */
@@ -192,7 +192,7 @@
 	mov	string, %ebx	; \
 	CALLSP(crt_console_tx_string)
 
-# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
 #  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
 # else
 #  define CONSOLE_DEBUG_TX_STRING(string)
@@ -333,26 +333,26 @@
 	RETSP
 9:
 /* Base Address */
-#ifndef TTYS0_BASE
-#define TTYS0_BASE	0x3f8
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE	0x3f8
 #endif
 /* Data */
-#define TTYS0_RBR (TTYS0_BASE+0x00)
+#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
 
 /* Control */
 #define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (TTYS0_BASE+0x01)
-#define TTYS0_IIR (TTYS0_BASE+0x02)
+#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
+#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
 #define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (TTYS0_BASE+0x03)
-#define TTYS0_MCR (TTYS0_BASE+0x04)
+#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
+#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
 #define TTYS0_DLL TTYS0_RBR
 #define TTYS0_DLM TTYS0_IER
 
 /* Status */
-#define TTYS0_LSR (TTYS0_BASE+0x05)
-#define TTYS0_MSR (TTYS0_BASE+0x06)
-#define TTYS0_SCR (TTYS0_BASE+0x07)
+#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
+#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
+#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
 
 	mov	%al, %ah
 10:	mov	$TTYS0_LSR, %dx

Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/syspreinit.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_lx/syspreinit.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_lx/syspreinit.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -39,7 +39,7 @@
 {
 
 	/* they want a jump ... */
-#ifndef USE_DCACHE_RAM
+#ifndef CONFIG_USE_DCACHE_RAM
 	__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
 #endif
 	StartTimer1();

Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -292,7 +292,7 @@
 	 */
 
 	//VSA is cat onto the end after LB builds
-	rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024);
+	rom = ((unsigned long)0) - (CONFIG_ROM_SIZE + 36 * 1024);
 	buf = (unsigned char *)VSA2_BUFFER;
 	olen = unrv2b((uint8_t *) rom, buf, &ilen);
 	printk_debug("buf ilen %d olen%d\n", ilen, olen);

Modified: trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -41,11 +41,11 @@
         msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
         wrmsr(TOP_MEM, msr);
 
-#if defined(XIP_ROM_SIZE)
+#if defined(CONFIG_XIP_ROM_SIZE)
         /* enable write through caching so we can do execute in place
          * on the flash rom.
          */
-        set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+        set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
         /* Set the default memory type and enable fixed and variable MTRRs 

Modified: trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -180,7 +180,7 @@
 	/* FIXME we should probably query the cpu for this
 	 * but so far this is all any recent AMD cpu has supported.
 	 */
-	address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
+	address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
 
 	/* Now that I have mapped what is memory and what is not
 	 * Setup the mtrrs so we can cache the memory.

Modified: trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -114,7 +114,7 @@
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
+		printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
 		enable_apic_ext_id(sysconf.nodes);
 	}
 

Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,15 +1,15 @@
-uses K8_REV_F_SUPPORT
-uses K8_HT_FREQ_1G_SUPPORT
-uses DIMM_SUPPORT
-uses CPU_SOCKET_TYPE
+uses CONFIG_K8_REV_F_SUPPORT
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_DIMM_SUPPORT
+uses CONFIG_CPU_SOCKET_TYPE
 
 config chip.h
 
-default K8_REV_F_SUPPORT=1
+default CONFIG_K8_REV_F_SUPPORT=1
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-default DIMM_SUPPORT=0x0004  #DDR2 unbuffered
-default CPU_SOCKET_TYPE=0x11
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_DIMM_SUPPORT=0x0004  #DDR2 unbuffered
+default CONFIG_CPU_SOCKET_TYPE=0x11
 
 object socket_AM2.o
 

Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,15 +1,15 @@
-uses K8_REV_F_SUPPORT
-uses K8_HT_FREQ_1G_SUPPORT
-uses DIMM_SUPPORT
-uses CPU_SOCKET_TYPE
+uses CONFIG_K8_REV_F_SUPPORT
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_DIMM_SUPPORT
+uses CONFIG_CPU_SOCKET_TYPE
 
 config chip.h
 
-default K8_REV_F_SUPPORT=1
+default CONFIG_K8_REV_F_SUPPORT=1
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-default DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CPU_SOCKET_TYPE=0x10
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
+default CONFIG_CPU_SOCKET_TYPE=0x10
 
 object socket_F.o
 

Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,37 +17,37 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-uses PCI_IO_CFG_EXT
-uses MMCONF_SUPPORT
-uses HT3_SUPPORT
-uses EXT_RT_TBL_SUPPORT
-uses EXT_CONF_SUPPORT
-uses DIMM_SUPPORT
-uses CPU_SOCKET_TYPE
-uses CBB
-uses CDB
-uses PCI_BUS_SEGN_BITS
-uses CAR_FAM10
+uses CONFIG_PCI_IO_CFG_EXT
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_HT3_SUPPORT
+uses CONFIG_EXT_RT_TBL_SUPPORT
+uses CONFIG_EXT_CONF_SUPPORT
+uses CONFIG_DIMM_SUPPORT
+uses CONFIG_CPU_SOCKET_TYPE
+uses CONFIG_CBB
+uses CONFIG_CDB
+uses CONFIG_PCI_BUS_SEGN_BITS
+uses CONFIG_CAR_FAM10
 
 config chip.h
 
-default PCI_IO_CFG_EXT=1
+default CONFIG_PCI_IO_CFG_EXT=1
 
-default HT3_SUPPORT=1
-default EXT_RT_TBL_SUPPORT=0
-default EXT_CONF_SUPPORT=0
-default DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CPU_SOCKET_TYPE=0x10
+default CONFIG_HT3_SUPPORT=1
+default CONFIG_EXT_RT_TBL_SUPPORT=0
+default CONFIG_EXT_CONF_SUPPORT=0
+default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
+default CONFIG_CPU_SOCKET_TYPE=0x10
 
-default CAR_FAM10=1
+default CONFIG_CAR_FAM10=1
 
-if EXT_RT_TBL_SUPPORT
-	default CBB=0xff
-	default CDB=0
+if CONFIG_EXT_RT_TBL_SUPPORT
+	default CONFIG_CBB=0xff
+	default CONFIG_CDB=0
 end
 
-#default MMCONF_SUPPORT=1
-#default MMCONF_SUPPORT_DEFAULT=1
+#default CONFIG_MMCONF_SUPPORT=1
+#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
 
 object socket_F_1207.o
 

Modified: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,15 +1,15 @@
-uses K8_REV_F_SUPPORT
-uses K8_HT_FREQ_1G_SUPPORT
-uses DIMM_SUPPORT
-uses CPU_SOCKET_TYPE
+uses CONFIG_K8_REV_F_SUPPORT
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_DIMM_SUPPORT
+uses CONFIG_CPU_SOCKET_TYPE
 
 config chip.h
 
-default K8_REV_F_SUPPORT=1
+default CONFIG_K8_REV_F_SUPPORT=1
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-default DIMM_SUPPORT=0x0204  #DDR2 and REG, S1G1
-default CPU_SOCKET_TYPE=0x12
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_DIMM_SUPPORT=0x0204  #DDR2 and REG, S1G1
+default CONFIG_CPU_SOCKET_TYPE=0x12
 
 object socket_S1G1.o
 

Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -65,7 +65,7 @@
 	return tolm;
 }
 
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
 #define HIGH_TABLES_SIZE 64	// maximum size of high tables in KB
 extern uint64_t high_tables_base, high_tables_size;
 #endif
@@ -118,7 +118,7 @@
 		ram_resource(dev, idx++, 0, 640);
 		ram_resource(dev, idx++, 768, tolmk - 768);
 
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
 		/* Leave some space for ACPI, PIRQ and MP tables */
 		high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = HIGH_TABLES_SIZE * 1024;

Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-uses HAVE_MOVNTI
-default HAVE_MOVNTI=1
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
 
 dir /cpu/x86/tsc
 dir /cpu/x86/mtrr

Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
-#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 #define post_code(x) intel_chip_post_macro(x)
 
 #include <cpu/x86/mtrr.h>
@@ -29,7 +29,7 @@
 	movl    %eax, %ebp
 
 cache_as_ram:
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 	post_code(0x20)
 
@@ -101,18 +101,18 @@
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
-#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
         movl    $0x0000000f, %edx
-        movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
         wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
         /* enable cache */
         movl	%cr0, %eax

Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -27,7 +27,7 @@
 {
 	unsigned int cpu_reset = 0;
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
                 goto normal_image;
@@ -87,10 +87,10 @@
 	}
 
 	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
+                /* set new esp */ /* before CONFIG_RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
 	);
 
 	{

Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-uses HAVE_MOVNTI
-default HAVE_MOVNTI=1
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
 
 dir /cpu/x86/tsc
 dir /cpu/x86/mtrr

Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
-#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 #define post_code(x) intel_chip_post_macro(x)
 
 #include <cpu/x86/mtrr.h>
@@ -29,7 +29,7 @@
 	movl    %eax, %ebp
 
 cache_as_ram:
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 	post_code(0x20)
 
@@ -108,18 +108,18 @@
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
-#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
         movl    $0x0000000f, %edx
-        movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
         wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
         /* enable cache */
         movl	%cr0, %eax

Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -27,7 +27,7 @@
 {
 	unsigned int cpu_reset = 0;
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
                 goto normal_image;
@@ -87,10 +87,10 @@
 	}
 
 	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
+                /* set new esp */ /* before CONFIG_RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
 	);
 
 	{

Modified: trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-uses HAVE_MOVNTI
-default HAVE_MOVNTI=1
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
 dir /cpu/x86/tsc
 dir /cpu/x86/mtrr
 dir /cpu/x86/fpu

Modified: trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-uses HAVE_MOVNTI
-default HAVE_MOVNTI=1
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
 dir /cpu/x86/tsc
 dir /cpu/x86/mtrr
 dir /cpu/x86/fpu

Modified: trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-uses HAVE_MOVNTI
-default HAVE_MOVNTI=1
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
 dir /cpu/x86/tsc
 dir /cpu/x86/mtrr
 dir /cpu/x86/fpu

Modified: trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-uses HAVE_MOVNTI
-default HAVE_MOVNTI=1
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
 dir /cpu/x86/tsc
 dir /cpu/x86/mtrr
 dir /cpu/x86/fpu

Modified: trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-uses HAVE_MOVNTI
-default HAVE_MOVNTI=1
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
 dir /cpu/x86/tsc
 dir /cpu/x86/mtrr
 dir /cpu/x86/fpu

Modified: trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,19 +1,19 @@
 ##
 ## CPU initialization
 ##
-uses _RAMBASE
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 
 ##
 ## Use cache ram for initial setup
 ##
-default USE_DCACHE_RAM=1
+default CONFIG_USE_DCACHE_RAM=1
 ## Set dcache ram above coreboot image
-default DCACHE_RAM_BASE=_RAMBASE+0x100000
+default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
 ## Dcache size is 32Kb
-default DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_SIZE=0x8000
 
 initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
 object cache.S

Modified: trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -30,7 +30,7 @@
  * - enable L1 I/D caches, otherwise performance will be slow
  * - set up DBATs for the following regions:
  *   - RAM (generally 0x00000000 -> 0x7fffffff)
- *   - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
+ *   - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
  *   - I/O (generally 0xfc000000 -> 0xfdffffff)
  *   - the main purpose for setting up the DBATs is so the I/O region
  *     can be marked cache inhibited/write through
@@ -147,7 +147,7 @@
 	 * IBATS
 	 *
 	 * IBAT0 covers RAM (0 -> 256Mb)
-	 * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
+	 * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
 	 */
         lis     r2, 0 at h
         ori     r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -156,8 +156,8 @@
         mtibatl 0, r2
 	isync
 
-        lis     r2, _ROMBASE at h
-#if ROM_SIZE > 1048576
+        lis     r2, CONFIG_ROMBASE at h
+#if CONFIG_ROM_SIZE > 1048576
         ori     r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
 #else
         ori     r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,19 +1,19 @@
 ##
 ## CPU initialization
 ##
-uses _RAMBASE
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 
 ##
 ## PPC4XX always uses cache ram for initial setup
 ##
-default USE_DCACHE_RAM=1
+default CONFIG_USE_DCACHE_RAM=1
 ## Set dcache ram above coreboot image
-default DCACHE_RAM_BASE=_RAMBASE+0x100000
+default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
 ## Dcache size is 16Kb
-default DCACHE_RAM_SIZE=16384
+default CONFIG_DCACHE_RAM_SIZE=16384
 
 initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
 initobject cache.S

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/cache.S
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/cache.S	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/cache.S	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 invalidate_dcache:
 	li	r6,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
-	li	r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
+	li	r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 1:
@@ -79,8 +79,8 @@
 	mtdccr	r10
 
 	/* do loop for # of congruence classes. */
-	li	r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
-	li	r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
+	li	r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
+	li	r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
 	mtctr	r10
 	li	r10,(0xE000-0x10000)	/* start at 0xFFFFE000 */
 	add	r11,r10,r11		/* add to get to other side of cache line */

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -47,7 +47,7 @@
 {
 	int idx = 3; /* who knows? */
 
-	ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10);
+	ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10);
 	assign_resources(&dev->link[0]);
 }
 

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/ppc4xx.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/ppc4xx.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/ppc4xx.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -94,15 +94,15 @@
 	isync
 
 	/*
-	 * Enable dcache region containing DCACHE_RAM_BASE
+	 * Enable dcache region containing CONFIG_DCACHE_RAM_BASE
 	 * On reset all regions are set to write-back, so we
 	 * just leave them alone.
 	 *
-	 * dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27))
+	 * dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27))
 	 */
 
-        lis     r4, DCACHE_RAM_BASE at ha
-	ori     r4, r4, DCACHE_RAM_BASE at l
+        lis     r4, CONFIG_DCACHE_RAM_BASE at ha
+	ori     r4, r4, CONFIG_DCACHE_RAM_BASE at l
 	srwi	r4, r4, 27
 	subfic	r4, r4, 31
 	li	r0, 1

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/sdram.c
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/sdram.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/sdram.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -98,17 +98,17 @@
 /* TODO: work out why this trashes cache ram */
 	//mtsdram0(mem_mcopt1, 0x00000000);
 
-#if EMBEDDED_RAM_SIZE==128*1024*1024
+#if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024
 	/* TODO */
-#elif EMBEDDED_RAM_SIZE==64*1024*1024
+#elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024
 	set_sdram0(mem_sdtr1, TR);
 	set_sdram0(mem_mb0cf, B0CR);
 	set_sdram0(mem_rtr, RTR);
 	set_sdram0(mem_ecccf, ECCCF);
 	set_sdram0(mem_pmit, PMIT);
-#elif EMBEDDED_RAM_SIZE==32*1024*1024
+#elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024
 	/* TODO */
-#elif EMBEDDED_RAM_SIZE==16*1024*1024
+#elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024
 	/* TODO */
 #endif
 

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,19 +1,19 @@
 ##
 ## CPU initialization
 ##
-uses _RAMBASE
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 
 ##
 ## PPC7XX always uses cache ram for initial setup
 ##
-default USE_DCACHE_RAM=1
+default CONFIG_USE_DCACHE_RAM=1
 ## Set dcache ram above coreboot image
-default DCACHE_RAM_BASE=_RAMBASE+0x100000
+default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
 ## Dcache size is 16Kb
-default DCACHE_RAM_SIZE=16384
+default CONFIG_DCACHE_RAM_SIZE=16384
 
 initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc
 

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -30,7 +30,7 @@
  * - enable L1 I/D caches, otherwise performance will be slow
  * - set up DBATs for the following regions:
  *   - RAM (generally 0x00000000 -> 0x7fffffff)
- *   - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
+ *   - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
  *   - I/O (generally 0xfc000000 -> 0xfdffffff)
  *   - the main purpose for setting up the DBATs is so the I/O region
  *     can be marked cache inhibited/write through
@@ -113,7 +113,7 @@
 	 * IBATS
 	 *
 	 * IBAT0 covers RAM (0 -> 256Mb)
-	 * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
+	 * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
 	 */
         lis     r2, 0 at h
         ori     r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -122,8 +122,8 @@
         mtibatl 0, r2
 	isync
 
-        lis     r2, _ROMBASE at h
-#if ROM_SIZE > 1048576
+        lis     r2, CONFIG_ROMBASE at h
+#if CONFIG_ROM_SIZE > 1048576
         ori     r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
 #else
         ori     r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -161,9 +161,9 @@
 	 * Initialize data cache blocks 
 	 * (assumes cache block size of 32 bytes)
 	 */
-	lis	r1, DCACHE_RAM_BASE at h
-	ori	r1, r1, DCACHE_RAM_BASE at l
-	li 	r3, (DCACHE_RAM_SIZE / 32)
+	lis	r1, CONFIG_DCACHE_RAM_BASE at h
+	ori	r1, r1, CONFIG_DCACHE_RAM_BASE at l
+	li 	r3, (CONFIG_DCACHE_RAM_SIZE / 32)
 	mtctr	r3
 0:	dcbz	r0, r1
 	addi	r1, r1, 32

Modified: trunk/coreboot-v2/src/cpu/ppc/ppc970/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/ppc970/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/ppc/ppc970/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,15 +1,15 @@
 ##
 ## CPU initialization
 ##
-uses _RAMBASE
-uses USE_DCACHE_RAM
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
 
 ##
 ## Assumes RAM already initialiazed
 ## This is true for the Apache board, but may
 ## not be for other 970 systems.
 ##
-default USE_DCACHE_RAM=0
+default CONFIG_USE_DCACHE_RAM=0
 
 initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc
 

Modified: trunk/coreboot-v2/src/cpu/via/car/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/via/car/cache_as_ram.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/via/car/cache_as_ram.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -25,8 +25,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define	CacheSize DCACHE_RAM_SIZE
-#define	CacheBase DCACHE_RAM_BASE
+#define	CacheSize CONFIG_DCACHE_RAM_SIZE
+#define	CacheBase CONFIG_DCACHE_RAM_BASE
 
 
 #include	<cpu/x86/mtrr.h>
@@ -82,13 +82,13 @@
 	/* MTRRPhysBase */
 	movl    $0x202, %ecx
 	xorl    %edx, %edx
-	movl    $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
+	movl    $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
 	wrmsr
 
 	/* MTRRPhysMask */
 	movl    $0x203, %ecx
 	movl    $0x0000000f,%edx
-	movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 
 
@@ -119,9 +119,9 @@
 	xorl    $0x5c5c5c5c,%eax
 	rep     stosl
 
-	movl    XIP_ROM_BASE, %esi
+	movl    CONFIG_XIP_ROM_BASE, %esi
 	movl    %esi, %edi
-	movl    $(XIP_ROM_SIZE>>2), %ecx
+	movl    $(CONFIG_XIP_ROM_SIZE>>2), %ecx
 	rep     lodsl
 
 	/* The key point of this CAR code is C7 cache does not turn into

Modified: trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c
===================================================================
--- trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -78,16 +78,16 @@
  	 			"movl    $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t"
         "wrmsr\n\t"        
         
-	/*jasonzhao at viatech.com.cn add this 2008-11-27, cache XIP_ROM_BASE-SIZE to speedup the coreboot code*/
+	/*jasonzhao at viatech.com.cn add this 2008-11-27, cache CONFIG_XIP_ROM_BASE-SIZE to speedup the coreboot code*/
 	 			"movl    $0x206, %ecx\n\t"
         "xorl    %edx, %edx\n\t"
-        "movl     $XIP_ROM_BASE,%eax\n\t"
+        "movl     $CONFIG_XIP_ROM_BASE,%eax\n\t"
         "orl     $(0 | 6), %eax\n\t"
         "wrmsr\n\t"
 
 	 			"movl    $0x207, %ecx\n\t"
         "xorl    %edx, %edx\n\t"
-        "movl     $XIP_ROM_SIZE,%eax\n\t"
+        "movl     $CONFIG_XIP_ROM_SIZE,%eax\n\t"
         "decl	%eax\n\t"
         "notl	%eax\n\t"
         "orl     $(0 | 0x800), %eax\n\t"

Modified: trunk/coreboot-v2/src/cpu/x86/16bit/reset16.lds
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/16bit/reset16.lds	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/16bit/reset16.lds	2009-06-30 15:17:49 UTC (rev 4381)
@@ -5,7 +5,7 @@
 
 SECTIONS {
 	/* Trigger an error if I have an unuseable start address */
-	_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease ROM_IMAGE_SIZE");
+	_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_ROM_IMAGE_SIZE");
 	_ROMTOP = 0xfffffff0;
 	. = _ROMTOP;
 	.reset . : {

Modified: trunk/coreboot-v2/src/cpu/x86/32bit/reset32.lds
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/32bit/reset32.lds	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/32bit/reset32.lds	2009-06-30 15:17:49 UTC (rev 4381)
@@ -4,7 +4,7 @@
  */
 
 SECTIONS {
-	_ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10;
+	_ROMTOP = CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10;
 	. = _ROMTOP;
 	.reset (.): {
 		*(.reset)

Modified: trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram.inc	2009-06-30 15:17:49 UTC (rev 4381)
@@ -27,7 +27,7 @@
 /* disable HyperThreading is done by eswar*/
 /* other's is the same as AMD except remove amd specific msr */
 
-#define CacheSize DCACHE_RAM_SIZE
+#define CacheSize CONFIG_DCACHE_RAM_SIZE
 #define CacheBase (0xd0000 - CacheSize) 
 
 #include <cpu/x86/mtrr.h>
@@ -37,7 +37,7 @@
 
 CacheAsRam:
 	/* hope we can skip the double set for normal part */
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
         // Check whether the processor has HT capability
         movl    $01, %eax
@@ -197,29 +197,29 @@
         orl    $(0x1<<30),%eax
         movl    %eax, %cr0
 
-#endif /*  USE_FALLBACK_IMAGE == 1*/
+#endif /*  CONFIG_USE_FALLBACK_IMAGE == 1*/
 
-#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
         /* enable write base caching so we can do execute in place
          * on the flash rom.
          */
         movl    $0x202, %ecx
         xorl    %edx, %edx
-        movl    $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
         wrmsr
 
         movl    $0x203, %ecx
         movl    $0x0000000f, %edx
-        movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
         wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
         /* enable cache */
         movl    %cr0, %eax
         andl    $0x9fffffff,%eax
         movl    %eax, %cr0
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 	/* Read the range with lodsl*/
         movl    $CacheBase, %esi
@@ -277,7 +277,7 @@
 .xout1x:
 
 #endif
-#endif /*USE_FALLBACK_IMAGE == 1*/
+#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
 
 
 	movl	$(CacheBase+CacheSize-4), %eax
@@ -314,7 +314,7 @@
         .long   0x20C, 0x20D, 0x20E, 0x20F
         .long   0x000 /* NULL, end of table */
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         .align 0x1000
         .code16
 .global LogicalAP_SIPI
@@ -344,5 +344,5 @@
         hlt
         jmp     Halt_LogicalAP
         .code32
-#endif /*USE_FALLBACK_IMAGE == 1*/
+#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
 .CacheAsRam_out:

Modified: trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram_post.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram_post.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/car/cache_as_ram_post.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -16,7 +16,7 @@
         "xorl    %edx, %edx\n\t"
         "xorl    %eax, %eax\n\t"
 	"wrmsr\n\t"
-#if DCACHE_RAM_SIZE > 0x8000
+#if CONFIG_DCACHE_RAM_SIZE > 0x8000
 	"movl    $0x268, %ecx\n\t"  /* fix4k_c0000*/
         "wrmsr\n\t"
 #endif

Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -10,7 +10,7 @@
 	if (cpu_reset == 1) cpu_reset = -1;
 	else cpu_reset = 0;
 
-# if USE_FALLBACK_IMAGE == 1
+# if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_and_run_core("fallback/coreboot_ram", cpu_reset);
 # else
 	cbfs_and_run_core("normal/coreboot_ram", cpu_reset);

Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,6 +1,6 @@
 /*
 	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
-	2005.12 yhlu add _RAMBASE above 1M support for SMP
+	2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
 	2008.05 stepan add support for going back to sipi wait state
 */
 
@@ -17,7 +17,7 @@
 
 #if CONFIG_SMP == 1
 
-#if _RAMBASE >= 0x100000
+#if CONFIG_RAMBASE >= 0x100000
 /* This is a lot more paranoid now, since Linux can NOT handle
  * being told there is a CPU when none exists. So any errors 
  * will return 0, meaning no CPU. 
@@ -31,7 +31,7 @@
 }
 #endif
 
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 char *lowmem_backup;
 char *lowmem_backup_ptr;
 int  lowmem_backup_size;
@@ -39,7 +39,7 @@
 
 static void copy_secondary_start_to_1m_below(void) 
 {
-#if _RAMBASE >= 0x100000
+#if CONFIG_RAMBASE >= 0x100000
         extern char _secondary_start[];
         extern char _secondary_start_end[];
         unsigned long code_size;
@@ -51,7 +51,7 @@
         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
 
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 	/* need to save it for RAM resume */
 	lowmem_backup_size = code_size;
 	lowmem_backup = malloc(code_size);
@@ -137,7 +137,7 @@
 		return 0;
 	}
 
-#if _RAMBASE >= 0x100000
+#if CONFIG_RAMBASE >= 0x100000
 	start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 #else
 	start_eip = (unsigned long)_secondary_start;
@@ -246,14 +246,14 @@
 	index = ++last_cpu_index;
 	
 	/* Find end of the new processors stack */
-#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
+#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
 	if(index<1) { // only keep bsp on low 
-		stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
+		stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
 	} else {
 		// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
-		stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
-#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
-		#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS)\n"
+		stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
+#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
+		#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
 #endif
 		if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
 			printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
@@ -262,7 +262,7 @@
 		stack_end -= sizeof(struct cpu_info);
 	}
 #else
-	stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
+	stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
 #endif
 
 	
@@ -363,13 +363,13 @@
 void secondary_cpu_init(void)
 {
 	atomic_inc(&active_cpus);
-#if SERIAL_CPU_INIT == 1
+#if CONFIG_SERIAL_CPU_INIT == 1
   #if CONFIG_MAX_CPUS>2
 	spin_lock(&start_cpu_lock);
   #endif
 #endif
 	cpu_initialize();
-#if SERIAL_CPU_INIT == 1
+#if CONFIG_SERIAL_CPU_INIT == 1
   #if CONFIG_MAX_CPUS>2
 	spin_unlock(&start_cpu_lock);
   #endif
@@ -389,7 +389,7 @@
 		if (cpu->path.type != DEVICE_PATH_APIC) {
 			continue;
 		}
-	#if SERIAL_CPU_INIT == 0
+	#if CONFIG_SERIAL_CPU_INIT == 0
 		if(cpu==bsp_cpu) {
 			continue; 
 		}
@@ -408,7 +408,7 @@
 			printk_err("CPU 0x%02x would not start!\n",
 				cpu->path.apic.apic_id);
 		}
-#if SERIAL_CPU_INIT == 1
+#if CONFIG_SERIAL_CPU_INIT == 1
   #if CONFIG_MAX_CPUS>2
 		udelay(10);
   #endif
@@ -448,13 +448,13 @@
 #define initialize_other_cpus(root) do {} while(0)
 #endif /* CONFIG_SMP */
 
-#if WAIT_BEFORE_CPUS_INIT==0
+#if CONFIG_WAIT_BEFORE_CPUS_INIT==0
 	#define cpus_ready_for_init() do {} while(0)
 #else
 	void cpus_ready_for_init(void);
 #endif
 
-#if HAVE_SMI_HANDLER
+#if CONFIG_HAVE_SMI_HANDLER
 void smm_init(void);
 #endif
 
@@ -486,14 +486,14 @@
 	copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 #endif
 
-#if HAVE_SMI_HANDLER
+#if CONFIG_HAVE_SMI_HANDLER
 	smm_init();
 #endif
 
         cpus_ready_for_init(); 
 
 #if CONFIG_SMP == 1
-	#if SERIAL_CPU_INIT == 0
+	#if CONFIG_SERIAL_CPU_INIT == 0
 	/* start all aps at first, so we can init ECC all together */
         start_other_cpus(cpu_bus, info->cpu);
 	#endif
@@ -503,7 +503,7 @@
         cpu_initialize();
 
 #if CONFIG_SMP == 1
-        #if SERIAL_CPU_INIT == 1
+        #if CONFIG_SERIAL_CPU_INIT == 1
         start_other_cpus(cpu_bus, info->cpu);
         #endif
 

Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -4,22 +4,22 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
-#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
-# error "XIP_ROM_SIZE without XIP_ROM_BASE"
+/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
+#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
+# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
 #endif
-#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
-# error "XIP_ROM_BASE without XIP_ROM_SIZE"
+#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
+# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
 #endif
 #if !defined(CONFIG_LB_MEM_TOPK)
 # error "CONFIG_LB_MEM_TOPK not defined"
 #endif
 
-#if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
-# error "XIP_ROM_SIZE is not a power of 2"
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
 #endif
-#if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
-# error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
+# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
 #endif
 
 #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
@@ -48,7 +48,7 @@
 	basem.hi = 0;
 	wrmsr(MTRRphysBase_MSR(reg), basem);
 	maskm.lo = ~(size - 1) | 0x800;
-	maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
+	maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
 	wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
@@ -59,9 +59,9 @@
         /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
         msr_t basem, maskm;
         basem.lo = (base_lo & 0xfffff000) | type;
-        basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
+        basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1);
         wrmsr(MTRRphysBase_MSR(reg), basem);
-       	maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
+       	maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
 	if(size_lo) {
 	        maskm.lo = ~(size_lo - 1) | 0x800;
 	} else {
@@ -99,11 +99,11 @@
 		wrmsr(msr_nr, msr);
 	}
 
-#if defined(XIP_ROM_SIZE)
+#if defined(CONFIG_XIP_ROM_SIZE)
 	/* enable write through caching so we can do execute in place
 	 * on the flash rom.
 	 */
-	set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+	set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
 	/* Set the default memory type and enable fixed and variable MTRRs 

Modified: trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -54,7 +54,7 @@
 		struct pde pdp[512];
 	} __attribute__ ((packed));
 
-#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
+#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
 	/*
 	 pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, 
 	 and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config

Modified: trunk/coreboot-v2/src/cpu/x86/smm/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/smm/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/smm/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,9 +18,9 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_SMI_HANDLER
+uses CONFIG_HAVE_SMI_HANDLER
 
-if HAVE_SMI_HANDLER
+if CONFIG_HAVE_SMI_HANDLER
 	object smmrelocate.S
 
 	smmobject smmhandler.S
@@ -34,8 +34,8 @@
 	makerule smm
 		depends	"smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" 
 		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
-		action 	"$(CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
-		action  "$(OBJCOPY) -O binary smm.elf smm"
+		action 	"$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
+		action  "$(CONFIG_OBJCOPY) -O binary smm.elf smm"
 	end
 
 	makerule smm_bin.c

Modified: trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -89,7 +89,7 @@
 
 static int uart_can_tx_byte(void)
 {
-	return inb(TTYS0_BASE + UART_LSR) & 0x20;
+	return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
 }
 
 static void uart_wait_to_tx_byte(void)
@@ -100,14 +100,14 @@
 
 static void uart_wait_until_sent(void)
 {
-	while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
+	while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
 	; 
 }
 
 static void uart_tx_byte(unsigned char data)
 {
 	uart_wait_to_tx_byte();
-	outb(data, TTYS0_BASE + UART_TBR);
+	outb(data, CONFIG_TTYS0_BASE + UART_TBR);
 	/* Make certain the data clears the fifos */
 	uart_wait_until_sent();
 }
@@ -169,7 +169,7 @@
 	node=nodeid();
 
 #ifdef DEBUG_SMI
-	console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+	console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 #else
 	console_loglevel = 1;
 #endif

Modified: trunk/coreboot-v2/src/cpu/x86/smm/smmrelocate.S
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/smm/smmrelocate.S	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/smm/smmrelocate.S	2009-06-30 15:17:49 UTC (rev 4381)
@@ -140,7 +140,7 @@
 	/* End of hardware specific section. */
 #ifdef DEBUG_SMM_RELOCATION
 	/* print [SMM-x] so we can determine if CPUx went to SMM */
-	movw $TTYS0_BASE, %dx
+	movw $CONFIG_TTYS0_BASE, %dx
 	mov $'[', %al
 	outb %al, %dx
 	mov $'S', %al

Modified: trunk/coreboot-v2/src/cpu/x86/tsc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/tsc/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/cpu/x86/tsc/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,9 +1,9 @@
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
 if CONFIG_UDELAY_TSC 
-	default HAVE_INIT_TIMER=1
+	default CONFIG_HAVE_INIT_TIMER=1
 	object delay_tsc.o  
 end

Modified: trunk/coreboot-v2/src/devices/device_util.c
===================================================================
--- trunk/coreboot-v2/src/devices/device_util.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/devices/device_util.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -163,7 +163,7 @@
 			memcpy(buffer, "Root Device", 12);
 			break;
 		case DEVICE_PATH_PCI:
-#if PCI_BUS_SEGN_BITS
+#if CONFIG_PCI_BUS_SEGN_BITS
 			sprintf(buffer, "PCI: %04x:%02x:%02x.%01x",
 				dev->bus->secondary>>8, dev->bus->secondary & 0xff, 
 				PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
@@ -461,7 +461,7 @@
 		end = resource_end(resource);
 		buf[0] = '\0';
 		if (resource->flags & IORESOURCE_PCI_BRIDGE) {
-#if PCI_BUS_SEGN_BITS
+#if CONFIG_PCI_BUS_SEGN_BITS
 			sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link[0].secondary & 0xff);
 #else
 			sprintf(buf, "bus %02x ", dev->link[0].secondary);
@@ -662,7 +662,7 @@
 	buf[0] = '\0';
 /*
 	if (resource->flags & IORESOURCE_BRIDGE) {
-#if PCI_BUS_SEGN_BITS
+#if CONFIG_PCI_BUS_SEGN_BITS
 		sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8,
 			dev->link[0].secondary & 0xff);
 #else

Modified: trunk/coreboot-v2/src/devices/hypertransport.c
===================================================================
--- trunk/coreboot-v2/src/devices/hypertransport.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/devices/hypertransport.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -103,8 +103,8 @@
 	}
 	/* AMD K8 Unsupported 1Ghz? */
 	if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
-#if K8_HT_FREQ_1G_SUPPORT == 1 
-	#if K8_REV_F_SUPPORT == 0 
+#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 
+	#if CONFIG_K8_REV_F_SUPPORT == 0 
 		if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT
 			freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 		} 
@@ -326,14 +326,14 @@
 	} while((ctrl & (1 << 5)) == 0);
 
 	        //actually, only for one HT device HT chain, and unitid is 0
-#if HT_CHAIN_UNITID_BASE == 0
+#if CONFIG_HT_CHAIN_UNITID_BASE == 0
         if(offset_unitid) {
                 return;
         }
 #endif
 
         /* Check if is already collapsed */
-        if((!offset_unitid)|| (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) {
+        if((!offset_unitid)|| (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
                 struct device dummy;
                 uint32_t id;
                 dummy.bus              = bus;
@@ -381,17 +381,17 @@
 unsigned int hypertransport_scan_chain(struct bus *bus, 
 	unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid)
 {
-	//even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
+	//even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
 	unsigned next_unitid, last_unitid;
 	device_t old_devices, dev, func;
-	unsigned min_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE:1;
+	unsigned min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
 	struct ht_link prev;
 	device_t last_func = 0;
 	int ht_dev_num = 0;
 	unsigned max_unitid;
 
-#if HT_CHAIN_END_UNITID_BASE != 0x20
-        //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+        //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
         unsigned real_last_unitid; 
         uint8_t real_last_pos;
 	device_t real_last_dev;
@@ -483,11 +483,11 @@
 		flags &= ~0x1f; /* mask out base Unit ID */
 
 		count = (flags >> 5) & 0x1f; /* get unit count */
-#if HT_CHAIN_END_UNITID_BASE != 0x20
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 		if(offset_unitid) {
 			if(next_unitid > (max_devfn>>3)) { // max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7
 				if(!end_used) {
-			                next_unitid = HT_CHAIN_END_UNITID_BASE;
+			                next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
 					end_used = 1;
 				} else {
 					goto end_of_chain;
@@ -519,7 +519,7 @@
 		ht_unitid_base[ht_dev_num] = next_unitid;
 		ht_dev_num++;
 
-#if HT_CHAIN_END_UNITID_BASE != 0x20
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 		if (offset_unitid) {
         	        real_last_pos = pos;
 			real_last_unitid = next_unitid;
@@ -550,25 +550,25 @@
 	}
 #endif
 
-#if HT_CHAIN_END_UNITID_BASE != 0x20
-        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE)  && !end_used) {
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE)  && !end_used) {
                 uint16_t flags;
                 int i;
 		device_t last_func = 0;
                 flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS);
                 flags &= ~0x1f;
-                flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
+                flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
                 pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
 
                 for(func = real_last_dev; func; func = func->sibling) {
-                        func->path.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3);
+                        func->path.pci.devfn -= ((real_last_unitid - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
 			last_func = func;
                 }
 
-		ht_unitid_base[ht_dev_num-1] = HT_CHAIN_END_UNITID_BASE; // update last one
+		ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one
 		
 		printk_debug(" unitid: %04x --> %04x\n",
-				real_last_unitid, HT_CHAIN_END_UNITID_BASE);
+				real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
 
         }
 #endif

Modified: trunk/coreboot-v2/src/devices/pci_device.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_device.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/devices/pci_device.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -598,11 +598,11 @@
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
 		printk_debug("%s subsystem <- %02x/%02x\n",
 			dev_path(dev),
-			MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 		ops->set_subsystem(dev,
-			MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
-			MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
 	}
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
@@ -1034,7 +1034,7 @@
 	device_t old_devices;
 	device_t child;
 
-#if PCI_BUS_SEGN_BITS
+#if CONFIG_PCI_BUS_SEGN_BITS
 	printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
 #else
 	printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);

Modified: trunk/coreboot-v2/src/devices/pci_ops.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_ops.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/devices/pci_ops.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -86,7 +86,7 @@
 	ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
 }
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
 {
 	struct bus *pbus = get_pbus(dev);

Modified: trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c
===================================================================
--- trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -238,7 +238,7 @@
 	switch(dev->path.pnp.device) {
 	case 0:
 		parent = dev->bus->dev;
-		printk_debug("DEBUG: %s", dev_path(parent));
+		printk_debug("CONFIG_DEBUG: %s", dev_path(parent));
 		if(parent->chip_ops && parent->chip_ops->name) {
 			printk_debug(": %s\n", parent->chip_ops->name);
 		} else {

Modified: trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c
===================================================================
--- trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/drivers/i2c/adm1026/adm1026.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,7 +17,7 @@
 #define CFG1_THERM_HOT   0x10
 #define CFT1_DAC_AFC     0x20
 #define CFG1_PWM_AFC     0x40
-#define CFG1_RESET       0x80
+#define CFG1CONFIG_RESET       0x80
 #define ADM1026_REG_CONFIG2 0x01
 #define ADM1026_REG_CONFIG3 0x07
 
@@ -40,7 +40,7 @@
         int result;
         result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
 
-        result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
+        result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1CONFIG_RESET);
         result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
 
         result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);

Modified: trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c
===================================================================
--- trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
  * 2. Reduce the size of your normal (or fallback) image, by adding the
  *    following lines to your target Config.lb, after romimage "normal"
  *      # 48K for SCSI FW or ATI ROM
- *      option ROM_SIZE = 512*1024-48*1024
+ *      option CONFIG_ROM_SIZE = 512*1024-48*1024
  * 3. Create your vgabios.bin, for example using awardeco and put it in the
  *    directory of your target Config.lb. You can also read an option rom from
  *    a running system, but this is unreliable, as some option roms are changed

Modified: trunk/coreboot-v2/src/include/assert.h
===================================================================
--- trunk/coreboot-v2/src/include/assert.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/assert.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 
 // ROMCC doesn't support __FILE__ or __LINE__  :^{
 
-#if DEBUG
+#if CONFIG_DEBUG
 #ifdef __ROMCC__
 #define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
 #else
@@ -35,7 +35,7 @@
 						}			\
 					}
 #endif		// __ROMCC__
-#else		// !DEBUG
+#else		// !CONFIG_DEBUG
 #define ASSERT(x)	{ }
 #endif
 

Modified: trunk/coreboot-v2/src/include/console/console.h
===================================================================
--- trunk/coreboot-v2/src/include/console/console.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/console/console.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -39,39 +39,39 @@
 #define printk_debug(fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
 #define printk_spew(fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
 
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
 #undef  printk_emerg
 #define printk_emerg(fmt, arg...)   do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
 #undef  printk_alert
 #define printk_alert(fmt, arg...)   do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
 #undef  printk_crit
 #define printk_crit(fmt, arg...)    do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
 #undef  printk_err
 #define printk_err(fmt, arg...)     do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
 #undef  printk_warning
 #define printk_warning(fmt, arg...) do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
 #undef  printk_notice
 #define printk_notice(fmt, arg...)  do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
 #undef  printk_info
 #define printk_info(fmt, arg...)    do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
 #undef  printk_debug
 #define printk_debug(fmt, arg...)   do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
+#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
 #undef  printk_spew
 #define printk_spew(fmt, arg...)    do {} while(0)
 #endif

Modified: trunk/coreboot-v2/src/include/console/loglevel.h
===================================================================
--- trunk/coreboot-v2/src/include/console/loglevel.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/console/loglevel.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -3,19 +3,19 @@
 
 /* Safe for inclusion in assembly */
 
-#ifndef MAXIMUM_CONSOLE_LOGLEVEL
-#define MAXIMUM_CONSOLE_LOGLEVEL 8
+#ifndef CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+#define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 8
 #endif
 
-#ifndef DEFAULT_CONSOLE_LOGLEVEL
-#define DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than BIOS_SPEW */
+#ifndef CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+#define CONFIG_DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than BIOS_SPEW */
 #endif
 
 #ifndef ASM_CONSOLE_LOGLEVEL
-#if (DEFAULT_CONSOLE_LOGLEVEL <= MAXIMUM_CONSOLE_LOGLEVEL)
-#define ASM_CONSOLE_LOGLEVEL DEFAULT_CONSOLE_LOGLEVEL
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL <= CONFIG_MAXIMUM_CONSOLE_LOGLEVEL)
+#define ASM_CONSOLE_LOGLEVEL CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 #else
-#define ASM_CONSOLE_LOGLEVEL MAXIMUM_CONSOLE_LOGLEVEL
+#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 #endif
 #endif
 

Modified: trunk/coreboot-v2/src/include/cpu/amd/model_fxx_rev.h
===================================================================
--- trunk/coreboot-v2/src/include/cpu/amd/model_fxx_rev.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/cpu/amd/model_fxx_rev.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,6 +1,6 @@
 #include <arch/cpu.h>
 
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
 static inline int is_cpu_rev_a0(void)
 {
 	return (cpuid_eax(1) & 0xfffef) == 0x0f00;
@@ -77,7 +77,7 @@
 
 #endif
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 //AMD_F0_SUPPORT
 static inline int is_cpu_pre_f0(void)
 {

Modified: trunk/coreboot-v2/src/include/device/pci_ops.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ops.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/device/pci_ops.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -12,7 +12,7 @@
 void pci_write_config16(device_t dev, unsigned where, uint16_t val);
 void pci_write_config32(device_t dev, unsigned where, uint32_t val);
 
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 uint8_t  pci_mmio_read_config8(device_t dev, unsigned where);
 uint16_t pci_mmio_read_config16(device_t dev, unsigned where);
 uint32_t pci_mmio_read_config32(device_t dev, unsigned where);

Modified: trunk/coreboot-v2/src/include/part/fallback_boot.h
===================================================================
--- trunk/coreboot-v2/src/include/part/fallback_boot.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/part/fallback_boot.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -3,7 +3,7 @@
 
 #ifndef ASSEMBLY
 
-#if HAVE_FALLBACK_BOOT == 1
+#if CONFIG_HAVE_FALLBACK_BOOT == 1
 void set_boot_successful(void);
 #else
 #define set_boot_successful()

Modified: trunk/coreboot-v2/src/include/part/hard_reset.h
===================================================================
--- trunk/coreboot-v2/src/include/part/hard_reset.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/part/hard_reset.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
 #ifndef PART_HARD_RESET_H
 #define PART_HARD_RESET_H
 
-#if HAVE_HARD_RESET == 1
+#if CONFIG_HAVE_HARD_RESET == 1
 void hard_reset(void);
 #else
 #define hard_reset() do {} while(0)

Modified: trunk/coreboot-v2/src/include/part/init_timer.h
===================================================================
--- trunk/coreboot-v2/src/include/part/init_timer.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/part/init_timer.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
 #ifndef PART_INIT_TIMER_H
 #define PART_DELAY_H
 
-#if HAVE_INIT_TIMER == 1
+#if CONFIG_HAVE_INIT_TIMER == 1
 void init_timer(void);
 #else
 #define init_timer() do{} while(0)

Modified: trunk/coreboot-v2/src/include/part/watchdog.h
===================================================================
--- trunk/coreboot-v2/src/include/part/watchdog.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/part/watchdog.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
 #ifndef PART_WATCHDOG_H
 #define PART_WATCHDOG_H
 
-#if USE_WATCHDOG_ON_BOOT == 1
+#if CONFIG_USE_WATCHDOG_ON_BOOT == 1
 void watchdog_off(void);
 #else
 #define watchdog_off()

Modified: trunk/coreboot-v2/src/include/pc80/mc146818rtc.h
===================================================================
--- trunk/coreboot-v2/src/include/pc80/mc146818rtc.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/pc80/mc146818rtc.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -82,19 +82,19 @@
 #define PC_CKS_LOC		46
 
 /* Linux bios checksum is built only over bytes 49..125 */
-#ifndef LB_CKS_RANGE_START
-#define LB_CKS_RANGE_START	49
+#ifndef CONFIG_LB_CKS_RANGE_START
+#define CONFIG_LB_CKS_RANGE_START	49
 #endif
-#ifndef LB_CKS_RANGE_END
-#define LB_CKS_RANGE_END	125
+#ifndef CONFIG_LB_CKS_RANGE_END
+#define CONFIG_LB_CKS_RANGE_END	125
 #endif
-#ifndef LB_CKS_LOC
-#define LB_CKS_LOC		126
+#ifndef CONFIG_LB_CKS_LOC
+#define CONFIG_LB_CKS_LOC		126
 #endif
 
 #if !defined(ASSEMBLY)
 void rtc_init(int invalid);
-#if USE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE == 1
 int get_option(void *dest, char *name);
 #else
 static inline int get_option(void *dest, char *name) { return -2; }

Modified: trunk/coreboot-v2/src/include/x86emu/fpu_regs.h
===================================================================
--- trunk/coreboot-v2/src/include/x86emu/fpu_regs.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/x86emu/fpu_regs.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -40,8 +40,8 @@
 #define __X86EMU_FPU_REGS_H
 
 
-#if defined(DEBUG) && (DEBUG == 0)
-#undef DEBUG
+#if defined(CONFIG_DEBUG) && (DEBUG == 0)
+#undef CONFIG_DEBUG
 #endif
 
 #ifdef X86_FPU_SUPPORT
@@ -107,7 +107,7 @@
 
 #endif /* X86_FPU_SUPPORT */
 
-#ifdef DEBUG
+#ifdef CONFIG_DEBUG
 # define DECODE_PRINTINSTR32(t,mod,rh,rl)     	\
 	DECODE_PRINTF(t[(mod<<3)+(rh)]);
 # define DECODE_PRINTINSTR256(t,mod,rh,rl)    	\

Modified: trunk/coreboot-v2/src/include/x86emu/regs.h
===================================================================
--- trunk/coreboot-v2/src/include/x86emu/regs.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/x86emu/regs.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -40,8 +40,8 @@
 #ifndef __X86EMU_REGS_H
 #define __X86EMU_REGS_H
 
-#if defined(DEBUG) && (DEBUG == 0)
-#undef DEBUG
+#if defined(CONFIG_DEBUG) && (CONFIG_DEBUG == 0)
+#undef CONFIG_DEBUG
 #endif
 
 /*---------------------- Macros and type definitions ----------------------*/
@@ -283,7 +283,7 @@
     u32                         mode;
     volatile int                intr;   /* mask of pending interrupts */
     volatile int                         debug;
-#ifdef DEBUG
+#ifdef CONFIG_DEBUG
     int                         check;
     u16                         saved_ip;
     u16                         saved_cs;

Modified: trunk/coreboot-v2/src/include/x86emu/x86emu.h
===================================================================
--- trunk/coreboot-v2/src/include/x86emu/x86emu.h	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/include/x86emu/x86emu.h	2009-06-30 15:17:49 UTC (rev 4381)
@@ -42,8 +42,8 @@
 #ifndef __X86EMU_X86EMU_H
 #define __X86EMU_X86EMU_H
 
-#if defined(DEBUG) && (DEBUG == 0)
-#undef DEBUG
+#if defined(CONFIG_DEBUG) && (CONFIG_DEBUG == 0)
+#undef CONFIG_DEBUG
 #endif
 
 /* FIXME: undefine printk for the moment */
@@ -165,7 +165,7 @@
 void 	X86EMU_exec(void);
 void 	X86EMU_halt_sys(void);
 
-#ifdef	DEBUG
+#ifdef	CONFIG_DEBUG
 #define	HALT_SYS()	\
     	printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__);	\
 	X86EMU_halt_sys();

Modified: trunk/coreboot-v2/src/lib/fallback_boot.c
===================================================================
--- trunk/coreboot-v2/src/lib/fallback_boot.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/lib/fallback_boot.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -5,7 +5,7 @@
 #include <arch/io.h>
 
 
-#if HAVE_FALLBACK_BOOT == 1
+#if CONFIG_HAVE_FALLBACK_BOOT == 1
 void set_boot_successful(void)
 {
 	/* Remember I succesfully booted by setting

Modified: trunk/coreboot-v2/src/lib/uart8250.c
===================================================================
--- trunk/coreboot-v2/src/lib/uart8250.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/lib/uart8250.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -80,7 +80,7 @@
 	int lcs;
 	divisor = 115200/(uart->baud ? uart->baud: 1);
 	lcs = 3;
-	if (base_port == TTYS0_BASE) {
+	if (base_port == CONFIG_TTYS0_BASE) {
 		/* Don't reinitialize the console serial port,
 		 * This is espeically nasty in SMP.
 		 */

Modified: trunk/coreboot-v2/src/lib/version.c
===================================================================
--- trunk/coreboot-v2/src/lib/version.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/lib/version.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,10 +1,10 @@
 #include <version.h>
 
-#ifndef MAINBOARD_VENDOR
-#error MAINBOARD_VENDOR not defined
+#ifndef CONFIG_MAINBOARD_VENDOR
+#error CONFIG_MAINBOARD_VENDOR not defined
 #endif
-#ifndef MAINBOARD_PART_NUMBER
-#error  MAINBOARD_PART_NUMBER not defined
+#ifndef CONFIG_MAINBOARD_PART_NUMBER
+#error  CONFIG_MAINBOARD_PART_NUMBER not defined
 #endif
 
 #ifndef COREBOOT_VERSION
@@ -39,8 +39,8 @@
 #define COREBOOT_EXTRA_VERSION ""
 #endif
 
-const char mainboard_vendor[] = MAINBOARD_VENDOR;
-const char mainboard_part_number[] = MAINBOARD_PART_NUMBER;
+const char mainboard_vendor[] = CONFIG_MAINBOARD_VENDOR;
+const char mainboard_part_number[] = CONFIG_MAINBOARD_PART_NUMBER;
 
 const char coreboot_version[] = COREBOOT_VERSION;
 const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION;

Modified: trunk/coreboot-v2/src/lib/xmodem.c
===================================================================
--- trunk/coreboot-v2/src/lib/xmodem.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/lib/xmodem.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -26,17 +26,17 @@
 
 static int _inbyte(int msec)
 {
-	while (!uart8250_can_rx_byte(TTYS0_BASE)) {
+	while (!uart8250_can_rx_byte(CONFIG_TTYS0_BASE)) {
 		udelay(1000);
 		if (msec-- <= 0)
 			return -1;
 	}
-	return uart8250_rx_byte(TTYS0_BASE);
+	return uart8250_rx_byte(CONFIG_TTYS0_BASE);
 }
 
 static void _outbyte(unsigned char c)
 {
-	uart8250_tx_byte(TTYS0_BASE, c);
+	uart8250_tx_byte(CONFIG_TTYS0_BASE, c);
 }
 
 static unsigned short crc16_ccitt(const unsigned char *buf, int sz)

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -54,7 +54,7 @@
 	if (bist == 0)
 		early_mtrr_init();
 
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x07 << 3) | 0x0,	/* Interrupt router device */
 	0x600,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -54,7 +54,7 @@
 	if (bist == 0)
 		early_mtrr_init();
 
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x07 << 3) | 0x0,	/* Interrupt router device */
 	0xc20,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,83 +18,83 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024		# Override this in targets/*/Config.lb.
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024		# Override this in targets/*/Config.lb.
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
 default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
 default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
 

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 		early_mtrr_init();
 
 	/* FIXME: It's a Winbond W83977EF, actually. */
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x07 << 3) | 0x0,	/* Interrupt router device */
 	0x1c20,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,45 +18,45 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
@@ -64,7 +64,7 @@
 uses CONFIG_SPLASH_GRAPHIC
 uses CONFIG_GX1_VIDEO
 uses CONFIG_GX1_VIDEOMODE
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
 ## Enable VGA with a splash screen (only 640x480 to run on most monitors).
 ## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
@@ -74,34 +74,34 @@
 default CONFIG_SPLASH_GRAPHIC = 1
 default CONFIG_VIDEO_MB = 2
 
-default ROM_SIZE = 256 * 1024
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default PIRQ_ROUTE = 1
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_PIRQ_ROUTE = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_OPTION_TABLE = 0
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc "
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3		# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3		# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -36,7 +36,7 @@
 
 static void main(unsigned long bist)
 {
-	w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x12 << 3) | 0x0,	/* Interrupt router device */
 	0xc00,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,14 +14,14 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
 	#compile cache_as_ram.c to auto.inc
 	makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
@@ -37,7 +37,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 #	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,59 +1,59 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -65,17 +65,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -85,58 +85,58 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=4
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=4
+default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
 default CONFIG_USE_PRINTK_IN_CAR=1
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -146,21 +146,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -172,13 +172,13 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 
 #

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -113,7 +113,7 @@
 	/* Note: must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	mb_gpio_init();
 	uart_init();
 	console_init();

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -44,7 +44,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * IRQ_SLOT_COUNT,	/* there can be total 6 devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* there can be total 6 devices on the bus */
 	0x00,			/* Where the interrupt router lies (bus) */
 	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */
@@ -54,7 +54,7 @@
 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
 	0x00,			/*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-	 /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
 	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,8 +19,8 @@
 ##
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
@@ -33,18 +33,18 @@
 
 #dir /drivers/si/3114
 
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE
 	object get_bus_conf.o
 	object irq_tables.o
 end
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	object acpi_tables.o
 	object fadt.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
+		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
+		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
 		action  "mv dsdt.hex dsdt.c"
 	end
 	object ./dsdt.o
@@ -55,15 +55,15 @@
 	if CONFIG_USE_INIT
 
 		makerule ./cache_as_ram_auto.o
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else
 
 		makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
@@ -87,7 +87,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -111,7 +111,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,133 +19,133 @@
 ##
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 uses CONFIG_USE_PRINTK_IN_CAR
 
 uses CONFIG_VIDEO_MB
 uses CONFIG_GFXUMA
-uses HAVE_MAINBOARD_RESOURCES
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
 
 ###
 ### Build options
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=131072
 #256K
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -158,7 +158,7 @@
 default CONFIG_LOGICAL_CPUS=1
 
 #1G memory hole
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -166,23 +166,23 @@
 
 # BTDC: Only one HT device on Herring.
 #HT Unit ID offset
-#default HT_CHAIN_UNITID_BASE=0x6
-default HT_CHAIN_UNITID_BASE=0x0
+#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_UNITID_BASE=0x0
 
 
 #real SB Unit ID
-default HT_CHAIN_END_UNITID_BASE=0x1
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
 
 #make the SB HT chain on bus 0
-default SB_HT_CHAIN_ON_BUS0=1
+default CONFIG_SB_HT_CHAIN_ON_BUS0=1
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x8000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 ##
@@ -193,39 +193,39 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="dbm690t"
-default MAINBOARD_VENDOR="amd"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
+default CONFIG_MAINBOARD_PART_NUMBER="dbm690t"
+default CONFIG_MAINBOARD_VENDOR="amd"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
 
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
 ##
 ## coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -239,8 +239,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -258,21 +258,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -284,21 +284,21 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 default CONFIG_VIDEO_MB=1
 default CONFIG_GFXUMA=1
-default HAVE_MAINBOARD_RESOURCES=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -59,7 +59,7 @@
 
 extern u8 AmlCode[];
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 extern u8 AmlCode_ssdt2[];
 extern u8 AmlCode_ssdt3[];
 extern u8 AmlCode_ssdt4[];
@@ -201,7 +201,7 @@
 	current += ssdt->length;
 	acpi_add_table(rsdt, ssdt);
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
 	/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -100,7 +100,7 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -139,14 +139,14 @@
 fallback_image:
 	post_code(0x25);
 }
-#endif				/* USE_FALLBACK_IMAGE == 1 */
+#endif				/* CONFIG_USE_FALLBACK_IMAGE == 1 */
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
 #endif
 	real_main(bist, cpu_init_detectedx);
@@ -159,7 +159,7 @@
 	u32 bsp_apicid = 0;
 	msr_t msr;
 	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 
 	if (bist == 0) {
@@ -170,7 +170,7 @@
 	sb600_lpc_init();
 
 	/* it8712f_enable_serial does not use its 1st parameter. */
-	it8712f_enable_serial(0, TTYS0_BASE);
+	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -142,7 +142,7 @@
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if HAVE_ACPI_TABLES == 0
+#if CONFIG_HAVE_ACPI_TABLES == 0
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
 #else

Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,7 +14,7 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
@@ -22,8 +22,8 @@
 
 	#compile cache_as_ram.c to auto.inc
 	makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
@@ -39,7 +39,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -61,7 +61,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 #	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,59 +1,59 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -65,17 +65,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -85,58 +85,58 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=6
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=6
+default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
 default CONFIG_USE_PRINTK_IN_CAR=1
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -146,21 +146,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -172,13 +172,13 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 
 #

Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -44,7 +44,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * IRQ_SLOT_COUNT,	/* there can be total 6 devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* there can be total 6 devices on the bus */
 	0x00,			/* Where the interrupt router lies (bus) */
 	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */
@@ -54,7 +54,7 @@
 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
 	0x00,			/*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-	 /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
 	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,8 +19,8 @@
 ##
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
@@ -33,18 +33,18 @@
 
 #dir /drivers/si/3114
 
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE
 	object get_bus_conf.o
 	object irq_tables.o
 end
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	object acpi_tables.o
 	object fadt.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
+		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
+		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
 		action  "mv dsdt.hex dsdt.c"
 	end
 	object ./dsdt.o
@@ -55,15 +55,15 @@
 	if CONFIG_USE_INIT
 
 		makerule ./cache_as_ram_auto.o
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else
 
 		makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
@@ -87,7 +87,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -111,7 +111,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,133 +19,133 @@
 ##
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 uses CONFIG_USE_PRINTK_IN_CAR
 
 uses CONFIG_VIDEO_MB
 uses CONFIG_GFXUMA
-uses HAVE_MAINBOARD_RESOURCES
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
 
 ###
 ### Build options
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=131072
 #256K
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -158,7 +158,7 @@
 default CONFIG_LOGICAL_CPUS=1
 
 #1G memory hole
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -166,23 +166,23 @@
 
 # BTDC: Only one HT device on Herring.
 #HT Unit ID offset
-#default HT_CHAIN_UNITID_BASE=0x6
-default HT_CHAIN_UNITID_BASE=0x0
+#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_UNITID_BASE=0x0
 
 
 #real SB Unit ID
-default HT_CHAIN_END_UNITID_BASE=0x1
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
 
 #make the SB HT chain on bus 0
-default SB_HT_CHAIN_ON_BUS0=1
+default CONFIG_SB_HT_CHAIN_ON_BUS0=1
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x8000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 ##
@@ -193,39 +193,39 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="pistachio"
-default MAINBOARD_VENDOR="amd"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
+default CONFIG_MAINBOARD_PART_NUMBER="pistachio"
+default CONFIG_MAINBOARD_VENDOR="amd"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
 
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
 ##
 ## coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -239,8 +239,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -258,21 +258,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -284,21 +284,21 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 default CONFIG_VIDEO_MB=1
 default CONFIG_GFXUMA=1
-default HAVE_MAINBOARD_RESOURCES=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -59,7 +59,7 @@
 
 extern u8 AmlCode[];
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 extern u8 AmlCode_ssdt2[];
 extern u8 AmlCode_ssdt3[];
 extern u8 AmlCode_ssdt4[];
@@ -201,7 +201,7 @@
 	current += ssdt->length;
 	acpi_add_table(rsdt, ssdt);
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
 	/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
 

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -94,7 +94,7 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -133,14 +133,14 @@
       fallback_image:
 	post_code(0x02);
 }
-#endif				/* USE_FALLBACK_IMAGE == 1 */
+#endif				/* CONFIG_USE_FALLBACK_IMAGE == 1 */
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
 #endif
 	real_main(bist, cpu_init_detectedx);
@@ -154,8 +154,8 @@
 	msr_t msr;
 	struct cpuid_result cpuid1;
 	struct sys_info *sysinfo =
-	    (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
-				DCACHE_RAM_GLOBAL_VAR_SIZE);
+	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
+				CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mptable.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/mptable.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mptable.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -142,7 +142,7 @@
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if HAVE_ACPI_TABLES == 0
+#if CONFIG_HAVE_ACPI_TABLES == 0
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
 #else

Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,29 +14,29 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -50,7 +50,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -72,7 +72,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,50 +1,50 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -53,17 +53,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -73,49 +73,49 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=2
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=2
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -125,21 +125,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -151,13 +151,13 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 
 #

Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -127,7 +127,7 @@
 	SystemPreInit();
 	
 
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
 arch i386 end 
@@ -15,25 +15,25 @@
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE 
+if CONFIG_HAVE_MP_TABLE 
 	object mptable.o 
 end
 
-if HAVE_PIRQ_TABLE 
+if CONFIG_HAVE_PIRQ_TABLE 
 	object irq_tables.o 
 end
 
-#if HAVE_ACPI_TABLES
+#if CONFIG_HAVE_ACPI_TABLES
 #       object acpi_tables.o
 #       object fadt.o
-#       if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_SB_HT_CHAIN_ON_BUS0
 #               object dsdt_bus0.o
 #       else
 #               object dsdt.o
 #       end
 #       object ssdt.o
-#       if ACPI_SSDTX_NUM
-#                if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_ACPI_SSDTX_NUM
+#                if CONFIG_SB_HT_CHAIN_ON_BUS0
 #                 object ssdt2_bus0.o
 #                else
 #                 object ssdt2.o
@@ -41,36 +41,36 @@
 #       end
 #end
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
         object acpi_tables.o
         object fadt.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
+		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
 		action  "mv dsdt_lb.hex dsdt.c"
 	end
         object ./dsdt.o
 
 	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
 	
-        if ACPI_SSDTX_NUM
+        if CONFIG_ACPI_SSDTX_NUM
             makerule ssdt2.c
-                        depends "$(MAINBOARD)/dx/pci2.asl"
-                        action  "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
+                        action  "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
                         action  "mv pci2.hex ssdt2.c"
             end
             object ./ssdt2.o
             makerule ssdt3.c
-                        depends "$(MAINBOARD)/dx/pci3.asl"
-                        action  "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
+                        action  "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
                         action  "mv pci3.hex ssdt3.c"
             end
             object ./ssdt3.o
             makerule ssdt4.c
-                        depends "$(MAINBOARD)/dx/pci4.asl"
-                        action  "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
+                        action  "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
                         action  "mv pci4.hex ssdt4.c"
             end
@@ -81,26 +81,26 @@
 	if CONFIG_USE_INIT
 		# compile cache_as_ram.c to auto.o
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else   
 		#compile cache_as_ram.c to auto.inc 
 		makerule ./cache_as_ram_auto.inc
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 	end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
 	makerule ./apc_auto.o
-		depends "$(MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
 	end
 	ldscript /arch/i386/init/ldscript_apc.lb
     end
@@ -110,13 +110,13 @@
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
@@ -134,8 +134,8 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -143,7 +143,7 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
     end
 else
-    if USE_FALLBACK_IMAGE 
+    if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -168,12 +168,12 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 		ldscript /arch/i386/lib/failover_failover.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
     end
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,85 +1,85 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
 
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
 
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
@@ -87,9 +87,9 @@
 
 uses CONFIG_AP_CODE_IN_CAR
 
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
 
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -98,20 +98,20 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
 
 #FALLBACK: 256K-4K
-default FALLBACK_SIZE=0x3f000
+default CONFIG_FALLBACK_SIZE=0x3f000
 #FAILOVER: 4K
-default FAILOVER_SIZE=0x01000
+default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -119,42 +119,42 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 ## extra SSDT num
-default ACPI_SSDTX_NUM=1
+default CONFIG_ACPI_SSDTX_NUM=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -165,41 +165,41 @@
 default CONFIG_MAX_PHYSICAL_CPUS=4
 default CONFIG_LOGICAL_CPUS=1
 
-default SERIAL_CPU_INIT=0
+default CONFIG_SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x8
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x8
+default CONFIG_LIFT_BSP_APIC_ID=1
 
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
 #1G
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 #512M
-#default HW_MEM_HOLE_SIZEK=0x80000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
 
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
 
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
 
 #HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0xa
+default CONFIG_HT_CHAIN_UNITID_BASE=0xa
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
-default HT_CHAIN_END_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
 
 #make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
 
 #only offset for SB chain?, default is yes(1)
-#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 
 #allow capable device use that above 4G
 #default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -207,10 +207,10 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 
@@ -218,8 +218,8 @@
 ## for rev F training on AP purpose
 ##
 default CONFIG_AP_CODE_IN_CAR=1
-default MEM_TRAIN_SEQ=1
-default WAIT_BEFORE_CPUS_INIT=1
+default CONFIG_MEM_TRAIN_SEQ=1
+default CONFIG_WAIT_BEFORE_CPUS_INIT=1
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -229,37 +229,37 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="serengeti_cheetah"
-default MAINBOARD_VENDOR="AMD"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah"
+default CONFIG_MAINBOARD_VENDOR="AMD"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Load the payload from the ROM
@@ -273,8 +273,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -290,21 +290,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -316,17 +316,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -39,7 +39,7 @@
 #endif
 
 extern unsigned char AmlCode[];
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 extern unsigned char AmlCode_ssdt2[];
 extern unsigned char AmlCode_ssdt3[];
 extern unsigned char AmlCode_ssdt4[];
@@ -263,7 +263,7 @@
 	current += ssdt->length;
 	acpi_add_table(rsdt, ssdt);
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
         //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -74,8 +74,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,7 +19,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -45,7 +45,7 @@
 #endif
 }
 #endif
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
@@ -59,7 +59,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -156,7 +156,7 @@
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -201,7 +201,7 @@
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -215,21 +215,21 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -253,7 +253,7 @@
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
@@ -265,11 +265,11 @@
 
 //	post_code(0x32);
 
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
-//	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 	
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
@@ -284,7 +284,7 @@
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
 #endif
 	setup_coherent_ht_domain(); // routing table and start other core0

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -109,7 +109,7 @@
         dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
         if (dev) {
                 m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
 //		printk_debug("bus_isa=%d\n",bus_isa);
@@ -132,7 +132,7 @@
         dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
         if (dev) {
                 m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
 //              printk_debug("bus_isa=%d\n",bus_isa);

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,8 +17,8 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
 arch i386 end
@@ -33,51 +33,51 @@
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE
+if CONFIG_HAVE_MP_TABLE
 	object mptable.o
 end
 
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	 object acpi_tables.o
 	 object fadt.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
-		action	"iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
+		action	"iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
 		action	"mv dsdt_lb.hex dsdt.c"
 	end
 	 object ./dsdt.o
 
 	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
 
-	if ACPI_SSDTX_NUM
+	if CONFIG_ACPI_SSDTX_NUM
 	makerule ssdt2.c
-		depends "$(MAINBOARD)/dx/pci2.asl"
-		action	"iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
+		depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
+		action	"iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
 		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
 		action	"mv pci2.hex ssdt2.c"
 	end
 	object ./ssdt2.o
 	makerule ssdt3.c
-		depends "$(MAINBOARD)/dx/pci3.asl"
-		action	"iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
+		depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
+		action	"iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
 		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
 		action	"mv pci3.hex ssdt3.c"
 	end
 	object ./ssdt3.o
 	makerule ssdt4.c
-		depends "$(MAINBOARD)/dx/pci4.asl"
-		action	"iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
+		depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
+		action	"iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
 		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
 		action	"mv pci4.hex ssdt4.c"
 	end
 	object ./ssdt4.o
 	makerule ssdt5.c
-		depends "$(MAINBOARD)/dx/pci5.asl"
-		action	"iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
+		depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
+		action	"iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
 		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
 		action	"mv pci5.hex ssdt5.c"
 	end
@@ -88,27 +88,27 @@
 	if CONFIG_USE_INIT
 		# compile cache_as_ram.c to auto.o
 		makerule ./cache_as_ram_auto.o
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else
 		#compile cache_as_ram.c to auto.inc
 		makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 
 	end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
 	 makerule ./apc_auto.o
-		 depends "$(MAINBOARD)/apc_auto.c option_table.h"
-		 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+		 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+		 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
 	 end
 	 ldscript /arch/i386/init/ldscript_apc.lb
     end
@@ -118,13 +118,13 @@
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
@@ -142,8 +142,8 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
     else
@@ -151,7 +151,7 @@
 	ldscript /cpu/x86/32bit/reset32.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
     else
@@ -177,12 +177,12 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 		ldscript /arch/i386/lib/failover_failover.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
     end
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,126 +17,126 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
 
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
 
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
 uses CONFIG_LB_MEM_TOPK
 
-uses PCI_BUS_SEGN_BITS
+uses CONFIG_PCI_BUS_SEGN_BITS
 
 uses CONFIG_AP_CODE_IN_CAR
 
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
 
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
-uses CAR_FAM10
-uses AMD_UCODE_PATCH_FILE
+uses CONFIG_CAR_FAM10
+uses CONFIG_AMD_UCODE_PATCH_FILE
 
 ###
 ### Build options
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=1024*1024
+default CONFIG_ROM_SIZE=1024*1024
 
 ##
 ##
 #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
 
 #FALLBACK: 1024K - 8K
-default FALLBACK_SIZE=0xFE000
+default CONFIG_FALLBACK_SIZE=0xFE000
 #FAILOVER: 8k
-default FAILOVER_SIZE=0x02000
+default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
 #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
@@ -145,42 +145,42 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 ## extra SSDT num
-default ACPI_SSDTX_NUM=31
+default CONFIG_ACPI_SSDTX_NUM=31
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -190,58 +190,58 @@
 default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
 default CONFIG_LOGICAL_CPUS=1
 
-#default SERIAL_CPU_INIT=0
+#default CONFIG_SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=1
-default APIC_ID_OFFSET=0x00
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=1
+default CONFIG_APIC_ID_OFFSET=0x00
+default CONFIG_LIFT_BSP_APIC_ID=1
 
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
 #1G
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 #512M
-#default HW_MEM_HOLE_SIZEK=0x80000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
 
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
 
 #HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0xa
+default CONFIG_HT_CHAIN_UNITID_BASE=0xa
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
-default HT_CHAIN_END_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
 
 #make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
 
 #only offset for SB chain?, default is yes(1)
-#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 
 #allow capable device use that above 4G
 #default CONFIG_PCI_64BIT_PREF_MEM=1
 
 #it only be 0, 1, 2, 3, 4 and default is 0
-#default PCI_BUS_SEGN_BITS=3
+#default CONFIG_PCI_BUS_SEGN_BITS=3
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc4000
-default DCACHE_RAM_SIZE=0x0c000
-#default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc4000
+default CONFIG_DCACHE_RAM_SIZE=0x0c000
+#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
 default CONFIG_USE_INIT=0
 
 #default CONFIG_AP_CODE_IN_CAR=1
-default MEM_TRAIN_SEQ=2
-default WAIT_BEFORE_CPUS_INIT=0
+default CONFIG_MEM_TRAIN_SEQ=2
+default CONFIG_WAIT_BEFORE_CPUS_INIT=0
 
 default CONFIG_AMDMCT = 1
 
@@ -253,10 +253,10 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="Cheetah Fam10"
-default MAINBOARD_VENDOR="AMD"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10"
+default CONFIG_MAINBOARD_VENDOR="AMD"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ##
 ## Set microcode patch file name
@@ -266,34 +266,34 @@
 ##	Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
 ##	Shanghai rev DA-C2: "mc_patch_0100009f.h"
 ##
-default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
+default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 768k heap
 ##
-default HEAP_SIZE=0xc0000
+default CONFIG_HEAP_SIZE=0xc0000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00200000
+default CONFIG_RAMBASE=0x00200000
 
 ##
 ## Load the payload from the ROM
@@ -307,8 +307,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -325,21 +325,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -351,17 +351,17 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -49,7 +49,7 @@
 extern u8 AmlCode[];
 extern u8 AmlCode_ssdt[];
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 extern u8 AmlCode_ssdt2[];
 extern u8 AmlCode_ssdt3[];
 extern u8 AmlCode_ssdt4[];
@@ -276,7 +276,7 @@
 	printk_debug("ACPI:    * SSDT for PState at %lx\n", current);
 	current = acpi_add_ssdt_pstates(rsdt, current);
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
 	/* same htio, but different possition? We may have to copy,
 	change HCIN, and recalculate the checknum and add_table */

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -50,9 +50,9 @@
 #include "lib/delay.c"
 
 #if NODE_NUMS == 64
-	 #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CBB,CDB+x,fn):PCI_DEV(CBB-1, CDB+x-32, fn))
+	 #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn):PCI_DEV(CONFIG_CBB-1, CONFIG_CDB+x-32, fn))
 #else
-	 #define NODE_PCI(x, fn) PCI_DEV(CBB,CDB+x,fn)
+	 #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn)
 #endif
 
 //#include "cpu/x86/lapic/boot_cpu.c"
@@ -73,8 +73,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -60,7 +60,7 @@
 	outb(value, 0x80);
 }
 
-#if (USE_FAILOVER_IMAGE == 0)
+#if (CONFIG_USE_FAILOVER_IMAGE == 0)
 #include "arch/i386/lib/console.c"
 #include "pc80/serial.c"
 #include "ram/ramtest.c"
@@ -80,7 +80,7 @@
 #include "cpu/x86/bist.h"
 
 
-#if (USE_FAILOVER_IMAGE == 0)
+#if (CONFIG_USE_FAILOVER_IMAGE == 0)
 
 #include "northbridge/amd/amdfam10/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -142,10 +142,10 @@
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif /* (USE_FAILOVER_IMAGE == 0) */
+#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
 
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -190,7 +190,7 @@
 		);
 
 fallback_image:
- #if HAVE_FAILOVER_BOOT==1
+ #if CONFIG_HAVE_FAILOVER_BOOT==1
 	__asm__ volatile ("jmp __fallback_image"
 		 : /* outputs */
 		 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -198,22 +198,22 @@
  #endif
 	;
 }
-#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) */
+#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */
 
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a USE_FAILOVER_IMAGE=0.
-#if HAVE_FAILOVER_BOOT==1
- #if USE_FAILOVER_IMAGE==1
+//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0.
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+ #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);
  #else
 	real_main(bist, cpu_init_detectedx);
  #endif
 #else
- #if USE_FALLBACK_IMAGE == 1
+ #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
  #endif
 	real_main(bist, cpu_init_detectedx);
@@ -221,7 +221,7 @@
 }
 
 
-#if (USE_FAILOVER_IMAGE==0)
+#if (CONFIG_USE_FAILOVER_IMAGE==0)
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -229,7 +229,7 @@
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-	struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	u32 bsp_apicid = 0;
 	u32 val;
 	msr_t msr;
@@ -243,12 +243,12 @@
 
 	post_code(0x32);
 
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	printk_debug("\n");
 
-//	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
@@ -380,4 +380,4 @@
 }
 
 
-#endif /* USE_FAILOVER_IMAGE==0 */
+#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -116,11 +116,11 @@
 
 	}
 
-#if CBB
-	write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+#if CONFIG_CBB
+	write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
 	if(sysconf.nodes>32) {
-		write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+		write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 		pirq_info++; slot_num++;
 	}
 #endif

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -49,14 +49,14 @@
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-//		PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10
-		PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
 		 * F1:0x48 i = 1
@@ -87,14 +87,14 @@
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-//		PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR_FAM10
-		PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -128,14 +128,14 @@
 		 *	   This field defines the upp adddress bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000,
-//		PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -163,14 +163,14 @@
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-//		PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -197,10 +197,10 @@
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
-		PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -227,10 +227,10 @@
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
-		PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -268,10 +268,10 @@
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration regin i
 		 */
-//		PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
-		PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
 
 	int max;

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,21 +13,21 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 end
 
 else    
                 
 makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -37,7 +37,7 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
         ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -55,7 +55,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -79,7 +79,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,61 +1,61 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_LOGICAL_CPUS
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -69,48 +69,48 @@
 default CONFIG_LOGICAL_CPUS=1
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -128,9 +128,9 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
  
 #VGA
@@ -140,38 +140,38 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="HDAMA"
-default MAINBOARD_VENDOR="ARIMA"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
+default CONFIG_MAINBOARD_VENDOR="ARIMA"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -185,8 +185,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -203,21 +203,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -229,17 +229,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -96,7 +96,7 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -148,7 +148,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         failover_process(bist, cpu_init_detectedx);
 #endif
         real_main(bist, cpu_init_detectedx);
@@ -186,7 +186,7 @@
 		init_cpus(cpu_init_detectedx);
         }
 
-	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,7 +18,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,           /* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT table entries */
+	32+16*CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
 	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
 	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,13 +14,13 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 	#compile cache_as_ram.c to auto.inc
 	makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
@@ -36,7 +36,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -58,7 +58,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 #	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,59 +1,59 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -65,17 +65,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -85,58 +85,58 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=3
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=3
+default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
 default CONFIG_USE_PRINTK_IN_CAR=1
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -146,21 +146,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -172,13 +172,13 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 
 #

Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -44,7 +44,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * IRQ_SLOT_COUNT,	/* there can be total 6 devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* there can be total 6 devices on the bus */
 	0x00,			/* Where the interrupt router lies (bus) */
 	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */
@@ -54,7 +54,7 @@
 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
 	0x00,			/*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-	 /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
 	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,45 +18,45 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
@@ -64,7 +64,7 @@
 uses CONFIG_SPLASH_GRAPHIC
 uses CONFIG_GX1_VIDEO
 uses CONFIG_GX1_VIDEOMODE
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
 ## Enable VGA with a splash screen (only 640x480 to run on most monitors).
 ## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
@@ -74,34 +74,34 @@
 default CONFIG_SPLASH_GRAPHIC = 1
 default CONFIG_VIDEO_MB = 2
 
-default ROM_SIZE = 256 * 1024
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default PIRQ_ROUTE = 1
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_PIRQ_ROUTE = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_OPTION_TABLE = 0
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc "
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3		# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3		# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -36,7 +36,7 @@
 
 static void main(unsigned long bist)
 {
-	pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x12 << 3) | 0x0,	/* Interrupt router device */
 	0x8800,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,7 +14,7 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
@@ -22,22 +22,22 @@
 ## Romcc output
 ##
 # makerule ./failover.E
-# 	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-# 	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+# 	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+# 	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 # end
 # 
 # makerule ./failover.inc
-# 	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-# 	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+# 	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+# 	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 # end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -51,7 +51,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -73,7 +73,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-# if USE_FALLBACK_IMAGE
+# if CONFIG_USE_FALLBACK_IMAGE
 # 	ldscript /arch/i386/lib/failover.lds 
 # 	mainboardinit ./failover.inc
 # end

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,52 +1,52 @@
-uses HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_CBFS
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 # uses CONFIG_CONSOLE_VGA
 # uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 256 * 1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE = 256 * 1024
 
 ###
 ### Build options
@@ -55,12 +55,12 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -70,49 +70,49 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5        # TODO?
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=5        # TODO?
+default CONFIG_PIRQ_ROUTE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-# default HAVE_OPTION_TABLE=0
+# default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-# default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+# default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -122,21 +122,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -148,13 +148,13 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=9
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
 ## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 
 # VGA Console
 # default CONFIG_CONSOLE_VGA=1

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -38,7 +38,7 @@
 static void main(unsigned long bist)
 {
 	/* Initialize the serial console. */
-	pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -21,36 +21,36 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
 arch i386 end
 driver mainboard.o
 # Needed by irq_tables and mptable and acpi_tables.
 object get_bus_conf.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 	if CONFIG_USE_INIT
 		makerule ./auto.o
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 	else
 		makerule ./auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 	end
-if HAVE_FAILOVER_BOOT
-	if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
 		mainboardinit cpu/x86/16bit/entry16.inc
 		ldscript /cpu/x86/16bit/entry16.lds
 	end
 else
-	if USE_FALLBACK_IMAGE
+	if CONFIG_USE_FALLBACK_IMAGE
 		mainboardinit cpu/x86/16bit/entry16.inc
 		ldscript /cpu/x86/16bit/entry16.lds
 	end
@@ -60,8 +60,8 @@
 		ldscript /cpu/x86/32bit/entry32.lds
 		ldscript /cpu/amd/car/cache_as_ram.lds
 	end
-if HAVE_FAILOVER_BOOT
-	if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
 		mainboardinit cpu/x86/16bit/reset16.inc
 		ldscript /cpu/x86/16bit/reset16.lds
 	else
@@ -69,7 +69,7 @@
 		ldscript /cpu/x86/32bit/reset32.lds
 	end
 else
-	if USE_FALLBACK_IMAGE
+	if CONFIG_USE_FALLBACK_IMAGE
 		mainboardinit cpu/x86/16bit/reset16.inc
 		ldscript /cpu/x86/16bit/reset16.lds
 	else
@@ -81,24 +81,24 @@
 mainboardinit southbridge/nvidia/ck804/id.inc
 ldscript /southbridge/nvidia/ck804/id.lds
 # ROMSTRAP table for CK804.
-if HAVE_FAILOVER_BOOT
-	if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
 		mainboardinit southbridge/nvidia/ck804/romstrap.inc
 		ldscript /southbridge/nvidia/ck804/romstrap.lds
 	end
 else
-	if USE_FALLBACK_IMAGE
+	if CONFIG_USE_FALLBACK_IMAGE
 		mainboardinit southbridge/nvidia/ck804/romstrap.inc
 		ldscript /southbridge/nvidia/ck804/romstrap.lds
 	end
 end
 	mainboardinit cpu/amd/car/cache_as_ram.inc
-if HAVE_FAILOVER_BOOT
-	if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+	if CONFIG_USE_FAILOVER_IMAGE
 			ldscript /arch/i386/lib/failover_failover.lds
 	end
 else
-	if USE_FALLBACK_IMAGE
+	if CONFIG_USE_FALLBACK_IMAGE
 			ldscript /arch/i386/lib/failover.lds
 	end
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,153 +19,153 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
+uses CONFIG_RAMBASE
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_CONSOLE_BTEXT
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_AP_CODE_IN_CAR
-uses MEM_TRAIN_SEQ
-uses WAIT_BEFORE_CPUS_INIT
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_MEM_TRAIN_SEQ
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 uses CONFIG_PCI_64BIT_PREF_MEM
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 uses CONFIG_LB_MEM_TOPK
 uses CONFIG_USE_PRINTK_IN_CAR
 
-default ROM_SIZE = 512 * 1024
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 252 * 1024
-default FAILOVER_SIZE = 4 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_FAILOVER_BOOT = 1
-default HAVE_HARD_RESET = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 13
-default HAVE_MP_TABLE = 1
-default HAVE_OPTION_TABLE = 1
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 252 * 1024
+default CONFIG_FAILOVER_SIZE = 4 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_FAILOVER_BOOT = 1
+default CONFIG_HAVE_HARD_RESET = 1
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 13
+default CONFIG_HAVE_MP_TABLE = 1
+default CONFIG_HAVE_OPTION_TABLE = 1
 # Move the default coreboot CMOS range off of AMD RTC registers.
-default LB_CKS_RANGE_START = 49
-default LB_CKS_RANGE_END = 122
-default LB_CKS_LOC = 123
+default CONFIG_LB_CKS_RANGE_START = 49
+default CONFIG_LB_CKS_RANGE_END = 122
+default CONFIG_LB_CKS_LOC = 123
 # SMP support (only worry about 2 micro processors).
 default CONFIG_SMP = 1
 default CONFIG_MAX_CPUS = 2
 default CONFIG_MAX_PHYSICAL_CPUS = 1
 default CONFIG_LOGICAL_CPUS = 1
 # 1G memory hole.
-default HW_MEM_HOLE_SIZEK = 0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
 # HT Unit ID offset, default is 1, the typical one.
-default HT_CHAIN_UNITID_BASE = 0
+default CONFIG_HT_CHAIN_UNITID_BASE = 0
 # Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default HT_CHAIN_END_UNITID_BASE = 0x10
+# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10
 # Make the SB HT chain on bus 0, default is not (0).
-default SB_HT_CHAIN_ON_BUS0 = 2
+default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
 # Only offset for SB chain?, default is yes(1).
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
 # default CONFIG_CONSOLE_BTEXT = 1		# BTEXT console
 default CONFIG_CONSOLE_VGA = 1			# For VGA console
 default CONFIG_PCI_ROM_RUN = 1			# For VGA console
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xc8000
-default DCACHE_RAM_SIZE = 32 * 1024
-default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xc8000
+default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024
 default CONFIG_USE_INIT = 0
 default CONFIG_AP_CODE_IN_CAR = 0
-default MEM_TRAIN_SEQ = 2
-default WAIT_BEFORE_CPUS_INIT = 0
-# default ENABLE_APIC_EXT_ID = 0
-# default APIC_ID_OFFSET = 0x10
-# default LIFT_BSP_APIC_ID = 0
+default CONFIG_MEM_TRAIN_SEQ = 2
+default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
+# default CONFIG_ENABLE_APIC_EXT_ID = 0
+# default CONFIG_APIC_ID_OFFSET = 0x10
+# default CONFIG_LIFT_BSP_APIC_ID = 0
 # default CONFIG_PCI_64BIT_PREF_MEM = 1
 default CONFIG_IOAPIC = 1
-default MAINBOARD_PART_NUMBER = "A8N-E"
-default MAINBOARD_VENDOR = "ASUS"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
+default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E"
+default CONFIG_MAINBOARD_VENDOR = "ASUS"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
 # Only use the option table in a normal image.
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE)
-default _RAMBASE = 0x00004000
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_GDB_STUB = 0
 default CONFIG_USE_PRINTK_IN_CAR=1
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3
-default DEFAULT_CONSOLE_LOGLEVEL = 8
-default MAXIMUM_CONSOLE_LOGLEVEL = 8
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -50,7 +50,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 
 /* Used by ck894_early_setup(). */
 #define CK804_NUM 1
@@ -99,10 +99,10 @@
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#endif	/* USE_FAILOVER_IMAGE */
+#endif	/* CONFIG_USE_FAILOVER_IMAGE */
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \
-	|| ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \
+	|| ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -166,7 +166,7 @@
 
 fallback_image:
 
-#if HAVE_FAILOVER_BOOT == 1
+#if CONFIG_HAVE_FAILOVER_BOOT == 1
 	__asm__ volatile ("jmp __fallback_image"
 		:					/* outputs */
 		:"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
@@ -175,27 +175,27 @@
 	;
 }
 
-#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */
+#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT == 1
-#if USE_FAILOVER_IMAGE == 1
+#if CONFIG_HAVE_FAILOVER_BOOT == 1
+#if CONFIG_USE_FAILOVER_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
 #else
 	real_main(bist, cpu_init_detectedx);
 #endif
 #else
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
 #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -215,7 +215,7 @@
 		bsp_apicid = init_cpus(cpu_init_detectedx);
 
 	it8712f_24mhz_clkin();
-	it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 
@@ -266,4 +266,4 @@
 
 	post_cache_as_ram();
 }
-#endif /* USE_FAILOVER_IMAGE */
+#endif /* CONFIG_USE_FAILOVER_IMAGE */

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -20,42 +20,42 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ## 
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 default CONFIG_ROM_PAYLOAD = 1
 
 arch i386 end 
 
 driver mainboard.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
   object acpi_tables.o
   makerule dsdt.c
-    depends "$(MAINBOARD)/dsdt.asl"
-    action  "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
+    depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+    action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
     action  "mv dsdt.hex dsdt.c"
   end
   object ./dsdt.o
 end
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 # object reset.o
 
   if CONFIG_USE_INIT
     makerule ./cache_as_ram_auto.o
-      depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
     end
   else
     makerule ./cache_as_ram_auto.inc
-      depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
     end
   end
 
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
   mainboardinit cpu/x86/16bit/entry16.inc
   ldscript /cpu/x86/16bit/entry16.lds
   mainboardinit southbridge/via/k8t890/romstrap.inc
@@ -71,7 +71,7 @@
     ldscript /cpu/amd/car/cache_as_ram.lds
   end
 
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
   mainboardinit cpu/x86/16bit/reset16.inc
   ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -81,7 +81,7 @@
 
   mainboardinit cpu/amd/car/cache_as_ram.inc
 
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
     ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,156 +17,156 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-# uses USE_OPTION_TABLE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+# uses CONFIG_USE_OPTION_TABLE
 # uses CONFIG_LB_MEM_TOPK
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
+uses CONFIG_RAMBASE
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 # bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses K8_HT_FREQ_1G_SUPPORT
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
 # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 # bx_b005+
-uses SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_USE_PRINTK_IN_CAR
 
-default ROM_SIZE = 512 * 1024
-default FALLBACK_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_HARD_RESET = 0
-default HAVE_PIRQ_TABLE = 0
-default IRQ_SLOT_COUNT = 11	# FIXME?
-default HAVE_MP_TABLE = 1
-default HAVE_OPTION_TABLE = 0	# FIXME
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_FALLBACK_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_HAVE_PIRQ_TABLE = 0
+default CONFIG_IRQ_SLOT_COUNT = 11	# FIXME?
+default CONFIG_HAVE_MP_TABLE = 1
+default CONFIG_HAVE_OPTION_TABLE = 0	# FIXME
 # Move the default coreboot CMOS range off of AMD RTC registers.
-default LB_CKS_RANGE_START = 49
-default LB_CKS_RANGE_END = 122
-default LB_CKS_LOC = 123
+default CONFIG_LB_CKS_RANGE_START = 49
+default CONFIG_LB_CKS_RANGE_END = 122
+default CONFIG_LB_CKS_LOC = 123
 default CONFIG_SMP = 1
 default CONFIG_MAX_CPUS = 2
 default CONFIG_MAX_PHYSICAL_CPUS = 1
 default CONFIG_LOGICAL_CPUS = 1
-default HAVE_ACPI_TABLES = 1
+default CONFIG_HAVE_ACPI_TABLES = 1
 
 # 1G memory hole
 # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
 
 # Opteron K8 1G HT support
-default K8_HT_FREQ_1G_SUPPORT = 1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
 
 # HT Unit ID offset, default is 1, the typical one.
-default HT_CHAIN_UNITID_BASE = 0x0
+default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
 
 # Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default HT_CHAIN_END_UNITID_BASE = 0x0
+# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
 
 # Make the SB HT chain on bus 0, default is not (0).
 # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
 
 # bx_b005+ make the SB HT chain on bus 0.
-default SB_HT_CHAIN_ON_BUS0 = 1
+default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
 
 # Only offset for SB chain?, default is yes(1).
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
 
 default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
 default CONFIG_PCI_ROM_RUN = 1		# Needed for VGA.
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xcc000
-default DCACHE_RAM_SIZE = 0x4000
-default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xcc000
+default CONFIG_DCACHE_RAM_SIZE = 0x4000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
 default CONFIG_USE_INIT = 0
-default ENABLE_APIC_EXT_ID = 0
-default APIC_ID_OFFSET = 0x10
-default LIFT_BSP_APIC_ID = 0
+default CONFIG_ENABLE_APIC_EXT_ID = 0
+default CONFIG_APIC_ID_OFFSET = 0x10
+default CONFIG_LIFT_BSP_APIC_ID = 0
 default CONFIG_IOAPIC = 1
-default MAINBOARD_VENDOR = "ASUS"
-default MAINBOARD_PART_NUMBER = "A8V-E SE"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
-default ROM_IMAGE_SIZE = 64 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 256 * 1024
+default CONFIG_MAINBOARD_VENDOR = "ASUS"
+default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
+# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 256 * 1024
 # More 1M for pgtbl.
 # default CONFIG_LB_MEM_TOPK = 2048
-default _RAMBASE = 0x00004000
-# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_RAMBASE = 0x00004000
+# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_GDB_STUB = 0
 default CONFIG_USE_PRINTK_IN_CAR = 1
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3		# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 8
-default MAXIMUM_CONSOLE_LOGLEVEL = 8
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3		# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 #
 # CBFS
 #

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -178,7 +178,7 @@
 	pnp_exit_ext_func_mode(GPIO_DEV);
 }
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -187,7 +187,7 @@
 	unsigned last_boot_normal_x = 1;
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	enable_rom_decode();
@@ -232,7 +232,7 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
 #endif
 	real_main(bist, cpu_init_detectedx);
@@ -251,11 +251,11 @@
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
 	struct sys_info *sysinfo =
-	    (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	char *p;
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	enable_rom_decode();

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -20,18 +20,18 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ## 
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end 
 
 driver mainboard.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
   object acpi_tables.o
   makerule dsdt.c
-    depends "$(MAINBOARD)/dsdt.asl"
-    action  "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
+    depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+    action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
     action  "mv dsdt.hex dsdt.c"
   end
   object ./dsdt.o
@@ -39,19 +39,19 @@
 
   if CONFIG_USE_INIT
     makerule ./cache_as_ram_auto.o
-      depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
     end
   else
     makerule ./cache_as_ram_auto.inc
-      depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
     end
   end
 
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
   mainboardinit cpu/x86/16bit/entry16.inc
   ldscript /cpu/x86/16bit/entry16.lds
   mainboardinit southbridge/via/k8t890/romstrap.inc
@@ -67,7 +67,7 @@
     ldscript /cpu/amd/car/cache_as_ram.lds
   end
 
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
   mainboardinit cpu/x86/16bit/reset16.inc
   ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -77,7 +77,7 @@
 
   mainboardinit cpu/amd/car/cache_as_ram.inc
 
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
     ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,159 +17,159 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-# uses USE_OPTION_TABLE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+# uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_LB_MEM_TOPK
-uses HAVE_ACPI_TABLES
-uses HAVE_MAINBOARD_RESOURCES
-uses HAVE_ACPI_RESUME
-uses HAVE_LOW_TABLES
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_HAVE_LOW_TABLES
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
+uses CONFIG_RAMBASE
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 # bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses K8_HT_FREQ_1G_SUPPORT
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
 # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 # bx_b005+
-uses SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_USE_PRINTK_IN_CAR
 
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_HARD_RESET = 1
-default HAVE_PIRQ_TABLE = 0
-default IRQ_SLOT_COUNT = 11	# FIXME?
-default HAVE_MP_TABLE = 0
-default HAVE_OPTION_TABLE = 0	# FIXME
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_HARD_RESET = 1
+default CONFIG_HAVE_PIRQ_TABLE = 0
+default CONFIG_IRQ_SLOT_COUNT = 11	# FIXME?
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0	# FIXME
 # Move the default coreboot CMOS range off of AMD RTC registers.
-default LB_CKS_RANGE_START = 49
-default LB_CKS_RANGE_END = 122
-default LB_CKS_LOC = 123
+default CONFIG_LB_CKS_RANGE_START = 49
+default CONFIG_LB_CKS_RANGE_END = 122
+default CONFIG_LB_CKS_LOC = 123
 default CONFIG_SMP = 1
 default CONFIG_MAX_CPUS = 2
 default CONFIG_MAX_PHYSICAL_CPUS = 1
 default CONFIG_LOGICAL_CPUS = 1
-default HAVE_ACPI_TABLES = 1
-default HAVE_MAINBOARD_RESOURCES = 1
-default HAVE_LOW_TABLES = 0
-default HAVE_ACPI_RESUME = 1
+default CONFIG_HAVE_ACPI_TABLES = 1
+default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
+default CONFIG_HAVE_LOW_TABLES = 0
+default CONFIG_HAVE_ACPI_RESUME = 1
 
 # 1G memory hole
 # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
 
 # Opteron K8 1G HT support
-default K8_HT_FREQ_1G_SUPPORT = 1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
 
 # HT Unit ID offset, default is 1, the typical one.
-default HT_CHAIN_UNITID_BASE = 0x0
+default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
 
 # Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default HT_CHAIN_END_UNITID_BASE = 0x0
+# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
 
 # Make the SB HT chain on bus 0, default is not (0).
 # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
 
 # bx_b005+ make the SB HT chain on bus 0.
-default SB_HT_CHAIN_ON_BUS0 = 1
+default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
 
 # Only offset for SB chain?, default is yes(1).
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
 
 default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
 default CONFIG_PCI_ROM_RUN = 0		# Needed for VGA.
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xcc000
-default DCACHE_RAM_SIZE = 0x4000
-default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xcc000
+default CONFIG_DCACHE_RAM_SIZE = 0x4000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
 default CONFIG_USE_INIT = 0
-default ENABLE_APIC_EXT_ID = 0
-default APIC_ID_OFFSET = 0x10
-default LIFT_BSP_APIC_ID = 0
+default CONFIG_ENABLE_APIC_EXT_ID = 0
+default CONFIG_APIC_ID_OFFSET = 0x10
+default CONFIG_LIFT_BSP_APIC_ID = 0
 default CONFIG_IOAPIC = 1
-default MAINBOARD_VENDOR = "ASUS"
-default MAINBOARD_PART_NUMBER = "M2V-MX SE"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 256 * 1024
+default CONFIG_MAINBOARD_VENDOR = "ASUS"
+default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
+# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 256 * 1024
 # More 1M for pgtbl.
 default CONFIG_LB_MEM_TOPK = 32768
 # to 1MB
-default _RAMBASE = 0x1F00000
-# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_RAMBASE = 0x1F00000
+# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_GDB_STUB = 0
 default CONFIG_USE_PRINTK_IN_CAR=1
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3		# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3		# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 #
 # CBFS
 #

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -40,7 +40,7 @@
 /* If we want to wait for core1 done before DQS training, set it to 0. */
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -183,12 +183,12 @@
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
 	struct sys_info *sysinfo =
-	    (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	char *p;
 	u8 reg;
 
 	sio_init();
-	it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 	it8712f_enable_3vsbsw();
 	uart_init();

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -25,11 +25,11 @@
 
 int add_mainboard_resources(struct lb_memory *mem)
 {
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME == 1
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
-		_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE));
+		CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE));
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
-		DCACHE_RAM_BASE, DCACHE_RAM_SIZE);
+		CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE);
 #endif
 	return 0;
 }

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,40 +18,40 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
 	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	action	"../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
 	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	action	"../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -61,7 +61,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 512 * 1024		# Override this in targets/*/Config.lb.
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 512 * 1024		# Override this in targets/*/Config.lb.
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
 default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
 default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
 

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -54,7 +54,7 @@
 	if (bist == 0)
 		early_mtrr_init();
 
-	smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x1f << 3) | 0x0,	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,29 +14,29 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -50,7 +50,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -72,7 +72,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,50 +1,50 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_IDE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 512*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 512*1024
 
 ###
 ### Build options
@@ -53,28 +53,28 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE = 0
+default CONFIG_HAVE_MP_TABLE = 0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET = 0
+default CONFIG_HAVE_HARD_RESET = 0
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 11
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 11
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
 
 ## IDE Support
 default CONFIG_IDE = 1
@@ -83,36 +83,36 @@
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -122,21 +122,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -148,13 +148,13 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=9
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=9
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 
 default CONFIG_UDELAY_TSC=1
 

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -58,7 +58,7 @@
 	if (bist == 0)
 		early_mtrr_init();
 
-	lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,83 +18,83 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -54,7 +54,7 @@
 	if (bist == 0)
 		early_mtrr_init();
 
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x04 << 3) | 0x0,	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,37 +18,37 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -58,7 +58,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,89 +18,89 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_SMP
 uses CONFIG_MAX_CPUS
 uses CONFIG_IOAPIC
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 1
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 1
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
 default CONFIG_SMP = 1
 default CONFIG_MAX_CPUS = 2
 default CONFIG_IOAPIC = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 default CONFIG_CBFS = 0

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 		enable_lapic();		/* FIXME? */
 	}
 
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x04 << 3) | 0x0,	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,37 +18,37 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -58,7 +58,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,89 +18,89 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_SMP
 uses CONFIG_MAX_CPUS
 uses CONFIG_IOAPIC
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 1
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 1
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
 default CONFIG_SMP = 1
 default CONFIG_MAX_CPUS = 2
 default CONFIG_IOAPIC = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 		enable_lapic();		/* FIXME? */
 	}
 
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x04 << 3) | 0x0,	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 		early_mtrr_init();
 
 	/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x04 << 3) | 0x0,	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 		early_mtrr_init();
 
 	/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x04 << 3) | 0x0,	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,36 +18,36 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -57,7 +57,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,45 +18,45 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
@@ -64,7 +64,7 @@
 uses CONFIG_SPLASH_GRAPHIC
 uses CONFIG_GX1_VIDEO
 uses CONFIG_GX1_VIDEOMODE
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
 ## Enable VGA with a splash screen (only 640x480 to run on most monitors).
 ## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
@@ -74,34 +74,34 @@
 default CONFIG_SPLASH_GRAPHIC = 1
 default CONFIG_VIDEO_MB = 2
 
-default ROM_SIZE = 256 * 1024
-default MAINBOARD_VENDOR = "AXUS"
-default MAINBOARD_PART_NUMBER = "TC320"
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_MAINBOARD_VENDOR = "AXUS"
+default CONFIG_MAINBOARD_PART_NUMBER = "TC320"
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
-default PIRQ_ROUTE = 1
-default HAVE_OPTION_TABLE = 0
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
+default CONFIG_PIRQ_ROUTE = 1
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc "
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3		# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 6
-default MAXIMUM_CONSOLE_LOGLEVEL = 6
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3		# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -37,7 +37,7 @@
 
 static void main(unsigned long bist)
 {
-	pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -66,7 +66,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	.signature = PIRQ_SIGNATURE,	/* PIRQ signature */
 	.version = PIRQ_VERSION,	/* PIRQ version */
-	.size = 32 + 16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */
+	.size = 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */
 	.rtr_bus = 0x00,		/* Interrupt router bus */
 	.rtr_devfn = (0x12 << 3) | 0x0,	/* Interrupt router device */
 	.exclusive_irqs = IRQ_DEVOTED_TO_PCI,	/* IRQs devoted to PCI */

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,37 +18,37 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -58,7 +58,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 		early_mtrr_init();
 
 	/* FIXME: It's a Winbond W83977EF, actually. */
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x07 << 3) | 0x0,	/* Interrupt router device */
 	0xc00,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,45 +18,45 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
@@ -64,7 +64,7 @@
 uses CONFIG_SPLASH_GRAPHIC
 uses CONFIG_GX1_VIDEO
 uses CONFIG_GX1_VIDEOMODE
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
 ## Enable VGA with a splash screen (only 640x480 to run on most monitors).
 ## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
@@ -74,34 +74,34 @@
 default CONFIG_SPLASH_GRAPHIC = 1
 default CONFIG_VIDEO_MB = 2
 
-default ROM_SIZE = 256 * 1024
-default MAINBOARD_VENDOR = "BCOM"
-default MAINBOARD_PART_NUMBER = "WinNET100"
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_MAINBOARD_VENDOR = "BCOM"
+default CONFIG_MAINBOARD_PART_NUMBER = "WinNET100"
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
-default PIRQ_ROUTE = 1
-default HAVE_OPTION_TABLE = 0
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
+default CONFIG_PIRQ_ROUTE = 1
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc "
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3		# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 6
-default MAXIMUM_CONSOLE_LOGLEVEL = 6
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3		# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -38,7 +38,7 @@
 static void main(unsigned long bist)
 {
 	/* Initialize the serial console. */
-	pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -64,7 +64,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	.signature = PIRQ_SIGNATURE,	/* PIRQ signature */
 	.version = PIRQ_VERSION,	/* PIRQ version */
-	.size = 32 +16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */
+	.size = 32 +16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */
 	.rtr_bus = 0x00,		/* Interrupt router bus */
 	.rtr_devfn = (0x12 << 3) | 0x0,	/* Interrupt router device */
 	.exclusive_irqs = IRQ_DEVOTED_TO_PCI,	/* IRQs devoted to PCI */

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,40 +19,40 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_ACPI_TABLES
 	object fadt.o
 	object dsdt.o
 	object acpi_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -62,7 +62,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,46 +19,46 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
@@ -68,33 +68,33 @@
 uses CONFIG_VIDEO_MB
 uses CONFIG_IOAPIC
 
-default ROM_SIZE = 512 * 1024
+default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_IOAPIC = 0
 default CONFIG_VIDEO_MB = 32
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default CONFIG_PCI_ROM_RUN = 0
 default CONFIG_CONSOLE_VGA = 0
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_HARD_RESET = 0
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 10
-default HAVE_ACPI_TABLES = 0
-default HAVE_OPTION_TABLE = 1
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = ROM_SIZE
-default USE_FALLBACK_IMAGE = 1
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 10
+default CONFIG_HAVE_ACPI_TABLES = 0
+default CONFIG_HAVE_OPTION_TABLE = 1
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
+default CONFIG_USE_FALLBACK_IMAGE = 1
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
+default CONFIG_HOSTCC = "gcc"
 
 ##
 ## Set this to the max PCI bus number you would ever use for PCI config I/O.

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -99,7 +99,7 @@
 
 	w83697hf_set_clksel_48(SERIAL_DEV);
 
-	w83697hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -24,7 +24,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x11 << 3) | 0x0,	/* Interrupt router device */
 	0x828,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -54,7 +54,7 @@
 	if (bist == 0)
 		early_mtrr_init();
 
-	smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x07 << 3) | 0x0,	/* Interrupt router device */
 	0xc00,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end 
@@ -12,8 +12,8 @@
 
 #dir /drivers/si/3114
 
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE 
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE 
 	object get_bus_conf.o
 	object irq_tables.o 
 end
@@ -23,15 +23,15 @@
 	if CONFIG_USE_INIT
 
 		makerule ./cache_as_ram_auto.o
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else    
                 
 		makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
@@ -55,7 +55,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -79,7 +79,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	       ldscript /arch/i386/lib/failover.lds
 end
 
@@ -209,14 +209,14 @@
                                         device pci 2.0 on end # USB        0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,),
+                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
                                         chip drivers/pci/onboard
                                               device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
-                                                                    # if HT_CHAIN_END_UNITID_BASE=0, it is 5, if HT_CHAIN_END_UNITID_BASE=1, it is 4
+                                                                    # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
                                               register "rom_address" = "0xfff80000"
                                         end
                                 end
-                                        #when HT_CHAIN_END_UNITID_BASE > HT_CHAIN_UNITID_BASE (6, ,,,,)
+                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
 #                                        chip drivers/pci/onboard
 #                                              device pci 0.0 on end # fake, will be disabled
 #                                        end

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,123 +1,123 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 ###
 ### Build options
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=131072
 #256K
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -129,27 +129,27 @@
 default CONFIG_LOGICAL_CPUS=1
 
 #1G memory hole
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 
 #VGA Console
 #default CONFIG_CONSOLE_VGA=1
 #default CONFIG_PCI_ROM_RUN=1
 
 #HT Unit ID offset
-default HT_CHAIN_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_UNITID_BASE=0x6
 
 #real SB Unit ID
-default HT_CHAIN_END_UNITID_BASE=0x1
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
 
 #make the SB HT chain on bus 0
-default SB_HT_CHAIN_ON_BUS0=1
+default CONFIG_SB_HT_CHAIN_ON_BUS0=1
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
 
 ##
@@ -160,38 +160,38 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="blast"
-default MAINBOARD_VENDOR="Broadcom"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
+default CONFIG_MAINBOARD_PART_NUMBER="blast"
+default CONFIG_MAINBOARD_VENDOR="Broadcom"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
 
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -205,8 +205,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -223,21 +223,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -249,17 +249,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -110,7 +110,7 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -161,14 +161,14 @@
 //        post_code(0x25);
 	;
 }
-#endif /* USE_FALLBACK_IMAGE == 1 */
+#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         failover_process(bist, cpu_init_detectedx);
 #endif
         real_main(bist, cpu_init_detectedx);
@@ -197,7 +197,7 @@
         }
 //	post_code(0x32);
 
-	pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 //	post_code(0x33);
 	
         uart_init();

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/get_bus_conf.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -83,7 +83,7 @@
 		dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d,0));
 		if(dev) {
 			bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
 	                bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 	                bus_isa++;
 //        	        printk_debug("bus_isa=%d\n",bus_isa);
@@ -99,7 +99,7 @@
 	        dev = dev_find_slot(bus_bcm5780[0], PCI_DEVFN(sbdn2 + i - 1,0));
 	        if(dev) {
         	        bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                         bus_isa++;
 //                      printk_debug("bus_isa=%d\n",bus_isa);

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -57,7 +57,7 @@
 		early_mtrr_init();
 
 	/* FIXME: Should be PC97307! */
-	pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x14 << 3) | 0x0,	/* Interrupt router device */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,10 +1,10 @@
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -18,30 +18,30 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+	action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -55,7 +55,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -77,7 +77,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,57 +1,57 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_MAX_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
 uses CONFIG_GDB_STUB
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_BTEXT
 uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
 
 
 ###
@@ -59,14 +59,14 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=1048576
+default CONFIG_ROM_SIZE=1048576
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Delay timer options
@@ -78,31 +78,31 @@
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=16
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=16
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -120,39 +120,39 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="X6DHR"
-default MAINBOARD_VENDOR=     "Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
+default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
+default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -167,8 +167,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -183,21 +183,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -209,17 +209,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ##
 ## Don't enable the btext console

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -103,7 +103,7 @@
 	outb(0x87,0x2e);
 	outb(0x87,0x2e);
 	pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-	w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,29 +13,29 @@
 ##
 
 driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -49,7 +49,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -71,7 +71,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,47 +1,47 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_UDELAY_IO
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-default DEFAULT_CONSOLE_LOGLEVEL=9
-default MAXIMUM_CONSOLE_LOGLEVEL=9
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 1024*1024
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 1024*1024
 
 ###
 ### Build options
@@ -50,17 +50,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## use io based udelay function
@@ -70,48 +70,48 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=5
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -78,7 +78,7 @@
 #endif
 	}
         
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,8 +1,8 @@
-default ROM_SIZE = 512 * 1024 
-default FALLBACK_SIZE = 0x10000
+default CONFIG_ROM_SIZE = 512 * 1024 
+default CONFIG_FALLBACK_SIZE = 0x10000
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 32 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 32 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -16,29 +16,29 @@
 ##
 
 driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 # object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -52,7 +52,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -74,7 +74,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,47 +1,47 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_COMPRESS
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_USE_INIT
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 
 uses CONFIG_CONSOLE_SERIAL8250
 
 
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 
 # VGA support
 uses CONFIG_CONSOLE_VGA
@@ -51,10 +51,10 @@
 
 
 default CONFIG_CONSOLE_SERIAL8250=1
-default DEFAULT_CONSOLE_LOGLEVEL=9
-default MAXIMUM_CONSOLE_LOGLEVEL=9
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -63,63 +63,63 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=7
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=7
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -137,7 +137,7 @@
 	/* hack for IDIOTIC need to fix rom_start */
 	printk_err("Patching rom_start due to sc520 limits\n");
 	rom_start = 0x2000000 + 0x40000;
-	rom_end = rom_start + PAYLOAD_SIZE - 1;
+	rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1;
 
 	
 }

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,14 +14,14 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
 	#compile cache_as_ram.c to auto.inc
 	makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
@@ -37,7 +37,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -59,7 +59,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 #	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,59 +1,59 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -65,17 +65,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -85,58 +85,58 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=6
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=6
+default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
 default CONFIG_USE_PRINTK_IN_CAR=1
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -146,21 +146,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -172,13 +172,13 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 
 #

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -81,7 +81,7 @@
 	 * for cs5536
 	 */
 	cs5536_disable_internal_uart();
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	mb_gpio_init();
 	uart_init();
 	console_init();

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,29 +14,29 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -50,7 +50,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -72,7 +72,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,52 +1,52 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_VIDEO_MB
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -55,17 +55,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -75,50 +75,50 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=2
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=2
+default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -128,21 +128,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -154,13 +154,13 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 default CONFIG_VIDEO_MB = 0
 

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 
 static void main(unsigned long bist)
 {
-	pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,5 +23,5 @@
 ## Build the objects we have code for in this directory.
 ##
 
-addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
 makedefine CFLAGS += -msoft-float

Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -2,25 +2,25 @@
 ## Config file for the Embedded Planet EP405PC Computing Engine
 ##
 
-uses PCIC0_CFGADDR 
+uses CONFIG_PCIC0_CFGADDR 
 uses CONFIG_CBFS
 uses CONFIG_ARCH_X86
-uses PCIC0_CFGDATA 
-uses ISA_IO_BASE 
-uses ISA_MEM_BASE 
-uses TTYS0_BASE 
-uses _IO_BASE 
+uses CONFIG_PCIC0_CFGDATA 
+uses CONFIG_ISA_IO_BASE 
+uses CONFIG_ISA_MEM_BASE 
+uses CONFIG_TTYS0_BASE 
+uses CONFIG_IO_BASE 
 
-uses CPU_OPT
-uses CROSS_COMPILE 
-uses HAVE_OPTION_TABLE
+uses CONFIG_CPU_OPT
+uses CONFIG_CROSS_COMPILE 
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_COMPRESS 
 uses CONFIG_CHIP_CONFIGURE
-uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_USE_INIT
 uses CONFIG_CONSOLE_SERIAL8250 
-uses TTYS0_BAUD TTYS0_DIV
-uses NO_POST
+uses CONFIG_TTYS0_BAUD CONFIG_TTYS0_DIV
+uses CONFIG_NO_POST
 uses CONFIG_IDE
 uses CONFIG_FS_PAYLOAD
 uses CONFIG_FS_EXT2
@@ -28,54 +28,54 @@
 uses CONFIG_FS_FAT
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses AUTOBOOT_CMDLINE
+uses CONFIG_AUTOBOOT_CMDLINE
 uses CONFIG_SYS_CLK_FREQ
-uses IDE_BOOT_DRIVE
-#uses IDE_SWAB
-uses IDE_OFFSET 
-uses ROM_SIZE
-uses ROM_IMAGE_SIZE
-uses _RESET
-uses _EXCEPTION_VECTORS
-uses _ROMBASE
-uses _ROMSTART
-uses _RAMBASE
-#uses _RAMSTART
-uses EMBEDDED_RAM_SIZE
-uses STACK_SIZE HEAP_SIZE
+uses CONFIG_IDE_BOOT_DRIVE
+#uses CONFIG_IDE_SWAB
+uses CONFIG_IDE_OFFSET 
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_RESET
+uses CONFIG_EXCEPTION_VECTORS
+uses CONFIG_ROMBASE
+uses CONFIG_ROMSTART
+uses CONFIG_RAMBASE
+#uses CONFIG_RAMSTART
+uses CONFIG_EMBEDDED_RAM_SIZE
+uses CONFIG_STACK_SIZE CONFIG_HEAP_SIZE
 
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 
 ##
 ## Set PCI configuration register addresses
 ##
-default PCIC0_CFGADDR=0xeec00000
-default PCIC0_CFGDATA=0xeec00004
+default CONFIG_PCIC0_CFGADDR=0xeec00000
+default CONFIG_PCIC0_CFGDATA=0xeec00004
 
 ##
 ## Set PCI/ISA I/O and memory base address
 ##
-default ISA_IO_BASE=0xe8000000
-default ISA_MEM_BASE=0x80000000
-default _IO_BASE=ISA_IO_BASE
+default CONFIG_ISA_IO_BASE=0xe8000000
+default CONFIG_ISA_MEM_BASE=0x80000000
+default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
 
 ##
 ## HACK ALERT: the UART0 registers are not in the PCI I/O address space
 ## but both IDE and UART use the same routines for I/O (inb/outb). To get 
 ## around this we set TTYSO_BASE to the difference between the two.
 ##
-default TTYS0_BASE=0xef600300-ISA_IO_BASE
+default CONFIG_TTYS0_BASE=0xef600300-CONFIG_ISA_IO_BASE
 
 ## Enable PPC405 instructions
-default CPU_OPT="-mcpu=405"
-#default CPU_OPT=""
+default CONFIG_CPU_OPT="-mcpu=405"
+#default CONFIG_CPU_OPT=""
 default CONFIG_ARCH_X86=0
 
 ## Use stage 1 initialization code
@@ -88,14 +88,14 @@
 default CONFIG_COMPRESS=0
 
 ## Turn off POST codes
-default NO_POST=1
+default CONFIG_NO_POST=1
 
 ## Enable serial console
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default CONFIG_CONSOLE_SERIAL8250=1
 # Divisor of 69 == 9600 baud due to weird clocking
-default TTYS0_DIV=69
-default TTYS0_BAUD=9600
+default CONFIG_TTYS0_DIV=69
+default CONFIG_TTYS0_BAUD=9600
 
 ## Boot linux from IDE
 default CONFIG_IDE=1
@@ -103,25 +103,25 @@
 default CONFIG_FS_EXT2=1
 default CONFIG_FS_ISO9660=1
 default CONFIG_FS_FAT=1
-default AUTOBOOT_CMDLINE="hda1:/vmlinuz"
+default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
 
-default ROM_SIZE=1048576
+default CONFIG_ROM_SIZE=1048576
 
 ## Board has fixed size RAM
-default EMBEDDED_RAM_SIZE=64*1024*1024
+default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
 
 ## Coreboot C code runs at this location in RAM
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Use a 64K stack
 ##
-default STACK_SIZE=0x10000
+default CONFIG_STACK_SIZE=0x10000
 
 ##
 ## Use a 64K heap
 ##
-default HEAP_SIZE=0x10000
+default CONFIG_HEAP_SIZE=0x10000
 
 ##
 ## System clock
@@ -129,19 +129,19 @@
 default CONFIG_SYS_CLK_FREQ=33
 
 ##
-default _ROMBASE=0xfff00000
+default CONFIG_ROMBASE=0xfff00000
 
 ## Reset vector address
-default _RESET=0xfffffffc
+default CONFIG_RESET=0xfffffffc
 
 ## Exception vectors
-default _EXCEPTION_VECTORS=_ROMBASE+0x100
+default CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100
 
 ## coreboot ROM start address
-default _ROMSTART=0xfff03000
+default CONFIG_ROMSTART=0xfff03000
 
 ## coreboot C code runs at this location in RAM
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,34 +1,34 @@
-## we don't use USE_DCACHE_RAM by default
-default USE_DCACHE_RAM=0
+## we don't use CONFIG_USE_DCACHE_RAM by default
+default CONFIG_USE_DCACHE_RAM=0
 ##
 ## Compute the location and size of where this firmware image
 ## (coreboot plus bootloader) will live in the boot rom chip.
 ##
-default ROM_SIZE = 256 * 1024 
-default ROM_SECTION_SIZE   = ROM_IMAGE_SIZE
-default ROM_SECTION_OFFSET = 0
+default CONFIG_ROM_SIZE = 256 * 1024 
+default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_ROM_SECTION_OFFSET = 0
 
 ##
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default PAYLOAD_SIZE            = ( ROM_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
 ##
-default XIP_ROM_SIZE=32*1024
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+default CONFIG_XIP_ROM_SIZE=32*1024
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
 
 ##
 ## Set all of the defaults for an x86 architecture
@@ -41,15 +41,15 @@
 ##
 
 driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 
-## ALL dependencies for USE_DCACHE_RAM go here. 
+## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. 
 ## That way, later, we can simply yank them if we wish. 
-## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case. 
+## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. 
 ## we do not use failover yet in this case. This is a work in progress. 
-if USE_DCACHE_RAM
+if CONFIG_USE_DCACHE_RAM
 	##
 	##
 	mainboardinit arch/i386/init/entry.S
@@ -63,22 +63,22 @@
 	## Romcc output
 	##
 	makerule ./failover.E
-		depends "$(MAINBOARD)/failover.c ../romcc" 
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
+		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 	end
 	
 	makerule ./failover.inc
-		depends "$(MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 	end
 	
 	makerule ./auto.E 
-		depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-		action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+		depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+		action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 	end
 	makerule ./auto.inc 
-		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-		action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+		action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 	end
 	
 	##
@@ -112,7 +112,7 @@
 	ldscript /arch/i386/lib/id.lds
 	
 ##
-## end of USE_DCACHE_RAM bits. 
+## end of CONFIG_USE_DCACHE_RAM bits. 
 ##
 end
 

Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,63 +1,63 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses HAVE_HIGH_TABLES
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_HIGH_TABLES
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 
 uses CONFIG_CONSOLE_SERIAL8250
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CBFS
 
 
 default CONFIG_CONSOLE_SERIAL8250=1
-default DEFAULT_CONSOLE_LOGLEVEL=8
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 default CONFIG_CBFS=1
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -66,30 +66,30 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=6
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=6
 
-default HAVE_HIGH_TABLES=1
+default CONFIG_HAVE_HIGH_TABLES=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Option ROM init
@@ -101,40 +101,40 @@
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = ROM_IMAGE_SIZE
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## known-good settings for qemu
-default DCACHE_RAM_BASE=0x8f000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_DCACHE_RAM_BASE=0x8f000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 
-default ROM_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_ROM_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
-default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default HAVE_OPTION_TABLE = 0
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_HAVE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3			# 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3			# 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -54,7 +54,7 @@
 	if (bist == 0)
 		early_mtrr_init();
 
-	it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	report_bist_failure(bist);

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x07 << 3) | 0x0,	/* Interrupt router device */
 	0xc00,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -21,8 +21,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
 arch i386 end
@@ -35,30 +35,30 @@
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 	if CONFIG_USE_INIT
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 	else
 		makerule ./cache_as_ram_auto.inc
-        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CPU_OPT) $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 	end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
         makerule ./apc_auto.o
-                depends "$(MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
         end
         ldscript /arch/i386/init/ldscript_apc.lb
     end
@@ -68,13 +68,13 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
@@ -93,8 +93,8 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
     else
@@ -102,7 +102,7 @@
 	ldscript /cpu/x86/32bit/reset32.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
     else
@@ -120,13 +120,13 @@
 ##
 ## ROMSTRAP table for MCP55
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit southbridge/sis/sis966/romstrap.inc
 	ldscript /southbridge/sis/sis966/romstrap.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit southbridge/sis/sis966/romstrap.inc
 	ldscript /southbridge/sis/sis966/romstrap.lds
     end
@@ -142,12 +142,12 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 		ldscript /arch/i386/lib/failover_failover.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
     end
 end

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -21,90 +21,90 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
 
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
 
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
@@ -112,9 +112,9 @@
 
 uses CONFIG_AP_CODE_IN_CAR
 
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
 
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -123,21 +123,21 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
-#default ROM_SIZE=0x100000
+default CONFIG_ROM_SIZE=524288
+#default CONFIG_ROM_SIZE=0x100000
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
 
 #FALLBACK: 256K-4K
-default FALLBACK_SIZE=0x3f000
+default CONFIG_FALLBACK_SIZE=0x3f000
 #FAILOVER: 4K
-default FAILOVER_SIZE=0x01000
+default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -145,40 +145,40 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=0
+default CONFIG_HAVE_ACPI_TABLES=0
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -189,25 +189,25 @@
 default CONFIG_MAX_PHYSICAL_CPUS=1
 default CONFIG_LOGICAL_CPUS=1
 
-#default SERIAL_CPU_INIT=0
+#default CONFIG_SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x10
+default CONFIG_LIFT_BSP_APIC_ID=1
 
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
 #1G
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 #512M
-#default HW_MEM_HOLE_SIZEK=0x80000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
 
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
 
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -216,16 +216,16 @@
 #default CONFIG_USBDEBUG_DIRECT=0
 
 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default HT_CHAIN_UNITID_BASE=0
+default CONFIG_HT_CHAIN_UNITID_BASE=0
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
-#default HT_CHAIN_END_UNITID_BASE=0x6
+#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
 
 #make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
 
 #only offset for SB chain?, default is yes(1)
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 
 #allow capable device use that above 4G
 #default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -233,15 +233,15 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 default CONFIG_AP_CODE_IN_CAR=0
-default MEM_TRAIN_SEQ=2
-default WAIT_BEFORE_CPUS_INIT=0
+default CONFIG_MEM_TRAIN_SEQ=2
+default CONFIG_WAIT_BEFORE_CPUS_INIT=0
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -251,37 +251,37 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="ga_2761gxdk"
-default MAINBOARD_VENDOR="GIGABYTE"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
+default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk"
+default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Load the payload from the ROM
@@ -297,8 +297,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -314,21 +314,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -340,17 +340,17 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -88,8 +88,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -41,7 +41,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -58,7 +58,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -82,7 +82,7 @@
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 #include "cpu/x86/bist.h"
 
@@ -154,7 +154,7 @@
 
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/sis/sis966/sis966_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -221,7 +221,7 @@
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -234,21 +234,21 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -261,7 +261,7 @@
 #endif
 	};
 
-        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
@@ -272,7 +272,7 @@
 
 	pnp_enter_ext_func_mode(SERIAL_DEV);
         pnp_write_config(SERIAL_DEV, 0x23, 0);
- 	it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
+ 	it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
         setup_mb_resource_map();
@@ -292,7 +292,7 @@
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 #endif
         setup_coherent_ht_domain(); // routing table and start other core0

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,8 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ## 
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
 arch i386 end 
@@ -33,30 +33,30 @@
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 	if CONFIG_USE_INIT	
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 	else
 		makerule ./cache_as_ram_auto.inc
-        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 	end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
         makerule ./apc_auto.o
-                depends "$(MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
         end
         ldscript /arch/i386/init/ldscript_apc.lb
     end
@@ -66,13 +66,13 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
@@ -91,8 +91,8 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -100,7 +100,7 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
     end
 else
-    if USE_FALLBACK_IMAGE 
+    if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -118,13 +118,13 @@
 ##
 ## ROMSTRAP table for MCP55
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE 
 	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 	ldscript /southbridge/nvidia/mcp55/romstrap.lds
     end
 else
-    if USE_FALLBACK_IMAGE 
+    if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 	ldscript /southbridge/nvidia/mcp55/romstrap.lds
     end
@@ -140,17 +140,17 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 		ldscript /arch/i386/lib/failover_failover.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
     end
 end
 
-if HAVE_FANCTL
+if CONFIG_HAVE_FANCTL
 	object fanctl.o
 end
 
@@ -166,11 +166,11 @@
 ##
 ## ACPI Support
 ##
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	object acpi_tables.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dsdt.asl"
-		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
+		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+		action  "iasl -p $(PWD)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
 		action  "mv dsdt.hex dsdt.c"
 	end
 	object ./dsdt.o

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,92 +19,92 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ## 
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
 
-uses HAVE_HIGH_TABLES
+uses CONFIG_HAVE_HIGH_TABLES
 
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
 
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
@@ -112,33 +112,33 @@
 
 uses CONFIG_AP_CODE_IN_CAR
 
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
 
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
-uses HAVE_FANCTL
+uses CONFIG_HAVE_FANCTL
 ###
 ### Build options
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
-#default ROM_SIZE=0x100000
+default CONFIG_ROM_SIZE=524288
+#default CONFIG_ROM_SIZE=0x100000
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
 
 #FALLBACK: 256K-4K
-default FALLBACK_SIZE=0x3f000
+default CONFIG_FALLBACK_SIZE=0x3f000
 #FAILOVER: 4K
-default FAILOVER_SIZE=0x01000
+default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -146,48 +146,48 @@
 ##
 ## Set-up automatic fan control
 ##
-default HAVE_FANCTL=1
+default CONFIG_HAVE_FANCTL=1
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## HIGH tables support
-default HAVE_HIGH_TABLES=1
+default CONFIG_HAVE_HIGH_TABLES=1
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -198,25 +198,25 @@
 default CONFIG_MAX_PHYSICAL_CPUS=1
 default CONFIG_LOGICAL_CPUS=1
 
-#default SERIAL_CPU_INIT=0
+#default CONFIG_SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x10
+default CONFIG_LIFT_BSP_APIC_ID=1
 
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
 #1G
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 #512M
-#default HW_MEM_HOLE_SIZEK=0x80000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
 
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
 
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -225,16 +225,16 @@
 #default CONFIG_USBDEBUG_DIRECT=1
 
 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default HT_CHAIN_UNITID_BASE=0
+default CONFIG_HT_CHAIN_UNITID_BASE=0
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
-#default HT_CHAIN_END_UNITID_BASE=0x6
+#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
 
 #make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
 
 #only offset for SB chain?, default is yes(1)
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 
 #allow capable device use that above 4G
 #default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -242,15 +242,15 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 default CONFIG_AP_CODE_IN_CAR=0
-default MEM_TRAIN_SEQ=2
-default WAIT_BEFORE_CPUS_INIT=0
+default CONFIG_MEM_TRAIN_SEQ=2
+default CONFIG_WAIT_BEFORE_CPUS_INIT=0
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -260,37 +260,37 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="m57sli"
-default MAINBOARD_VENDOR="GIGABYTE"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+default CONFIG_MAINBOARD_PART_NUMBER="m57sli"
+default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Load the payload from the ROM
@@ -306,8 +306,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -323,21 +323,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -349,17 +349,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/apc_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/apc_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/apc_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -86,8 +86,8 @@
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -39,7 +39,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -56,7 +56,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -79,7 +79,7 @@
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 #include "cpu/x86/bist.h"
 
@@ -152,7 +152,7 @@
 
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -219,7 +219,7 @@
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -232,21 +232,21 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -259,7 +259,7 @@
 #endif
 	};
 
-        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
@@ -281,10 +281,10 @@
 		pnp_write_config(GPIO_DEV, 0x64, 0x08);
 		pnp_write_config(GPIO_DEV, 0x65, 0x20);
 		/* We can get away with not resetting the logical device because
-		 * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that.
+		 * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
 		 */
 	}
- 	it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
+ 	it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
         setup_mb_resource_map();
@@ -304,7 +304,7 @@
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 #endif
         setup_coherent_ht_domain(); // routing table and start other core0

Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -25,8 +25,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
@@ -40,18 +40,18 @@
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 
 if CONFIG_USE_INIT
 	makerule ./auto.o
-		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 	end
 else
 	makerule ./auto.inc
-		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
@@ -60,7 +60,7 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -78,7 +78,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -102,7 +102,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -24,84 +24,84 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
 uses CONFIG_CBFS
 
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
 
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
@@ -114,14 +114,14 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -129,37 +129,37 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from linuxBIOS
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=15
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=15
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -170,41 +170,41 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-default SERIAL_CPU_INIT=0
+default CONFIG_SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x8
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x8
+default CONFIG_LIFT_BSP_APIC_ID=1
 
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
 #1G
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 #512M
-#default HW_MEM_HOLE_SIZEK=0x80000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
 
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
 
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=0
 
 #HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0x06
+default CONFIG_HT_CHAIN_UNITID_BASE=0x06
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
-default HT_CHAIN_END_UNITID_BASE=0x01
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
 
 #make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
 
 #only offset for SB chain?, default is yes(1)
-#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 
 #allow capable device use that above 4G
 #default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -212,10 +212,10 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcc000
-default DCACHE_RAM_SIZE=0x04000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcc000
+default CONFIG_DCACHE_RAM_SIZE=0x04000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 ##
@@ -226,37 +226,37 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="DL145 G3"
-default MAINBOARD_VENDOR="HP"
-#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+default CONFIG_MAINBOARD_PART_NUMBER="DL145 G3"
+default CONFIG_MAINBOARD_VENDOR="HP"
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Load the payload from the ROM
@@ -270,8 +270,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -289,21 +289,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -315,17 +315,17 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ##
 ## CBFS

Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -44,7 +44,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -62,7 +62,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -84,7 +84,7 @@
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 #include "cpu/x86/bist.h"
 
@@ -156,7 +156,7 @@
 
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -238,7 +238,7 @@
 		);
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
 	__asm__ volatile ("jmp __fallback_image"
 		: /* outputs */
 		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -253,21 +253,21 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -283,7 +283,7 @@
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	 int needs_reset;
 	 unsigned bsp_apicid = 0;
@@ -293,7 +293,7 @@
 		 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	 }
 
-	pilot_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	//setup_mp_resource_map();
 
@@ -310,7 +310,7 @@
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 #endif
 	setup_coherent_ht_domain();

Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/get_bus_conf.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/get_bus_conf.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -108,7 +108,7 @@
 		printk_debug("now found %s...\n",dev_path(dev));
 		if(dev) {
 			m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
 			m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			m->bus_isa++;
 			printk_debug("bus_isa 1=%d\n",m->bus_isa);
@@ -124,7 +124,7 @@
 		dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
 		if(dev) {
 			m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 			m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			m->bus_isa++;
 			printk_debug("bus_isa 2=%d\n",m->bus_isa);

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,22 +13,22 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 end
 
 else    
                 
 makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -38,7 +38,7 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
         ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -56,7 +56,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -80,7 +80,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,54 +1,54 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -58,48 +58,48 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -117,45 +117,45 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
  
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="E325"
-default MAINBOARD_VENDOR="IBM"
-#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+default CONFIG_MAINBOARD_PART_NUMBER="E325"
+default CONFIG_MAINBOARD_VENDOR="IBM"
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -169,8 +169,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 default CONFIG_USE_PRINTK_IN_CAR=1
 
@@ -182,21 +182,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -208,17 +208,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -93,7 +93,7 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -145,7 +145,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         failover_process(bist, cpu_init_detectedx);
 #endif
         real_main(bist, cpu_init_detectedx);
@@ -183,7 +183,7 @@
 		init_cpus(cpu_init_detectedx);
         }
 
-	pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
 #include <arch/pirq_routing.h>
 #include <device/pci.h>
 
-#define IRQ_SLOT_COUNT 12
+#define CONFIG_IRQ_SLOT_COUNT 12
 #define IRQ_ROUTER_BUS		0
 #define IRQ_ROUTER_DEVFN	PCI_DEVFN(4,3)
 #define IRQ_ROUTER_VENDOR	0x1022
@@ -19,7 +19,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,           /* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT table entries */
+	32+16*CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
 	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
 	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,22 +13,22 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 end
 
 else    
                 
 makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -38,7 +38,7 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
         ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -56,7 +56,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -80,7 +80,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,56 +1,56 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -60,48 +60,48 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -123,45 +123,45 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
  
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="E326"
-default MAINBOARD_VENDOR="IBM"
-#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+default CONFIG_MAINBOARD_PART_NUMBER="E326"
+default CONFIG_MAINBOARD_VENDOR="IBM"
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -175,8 +175,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 default CONFIG_USE_PRINTK_IN_CAR=1
 
@@ -188,21 +188,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -214,17 +214,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -93,7 +93,7 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -145,7 +145,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         failover_process(bist, cpu_init_detectedx);
 #endif
         real_main(bist, cpu_init_detectedx);
@@ -183,7 +183,7 @@
 		init_cpus(cpu_init_detectedx);
         }
 
-	pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,7 +1,7 @@
 #include <arch/pirq_routing.h>
 #include <device/pci.h>
 
-#define IRQ_SLOT_COUNT 12
+#define CONFIG_IRQ_SLOT_COUNT 12
 #define IRQ_ROUTER_BUS		0
 #define IRQ_ROUTER_DEVFN	PCI_DEVFN(4,3)
 #define IRQ_ROUTER_VENDOR	0x1022
@@ -19,7 +19,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,           /* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT table entries */
+	32+16*CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
 	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
 	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -2,31 +2,31 @@
 ## Compute the location and size of where this firmware image
 ## (coreboot plus bootloader) will live in the boot rom chip.
 ##
-default ROM_SIZE = 256 * 1024 
-default ROM_SECTION_SIZE   = ROM_SIZE
-default ROM_SECTION_OFFSET = 0
+default CONFIG_ROM_SIZE = 256 * 1024 
+default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_SIZE
+default CONFIG_ROM_SECTION_OFFSET = 0
 
 ##
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
 ##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+default CONFIG_XIP_ROM_SIZE=65536
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
 
 ##
 ## Set all of the defaults for an x86 architecture
@@ -40,29 +40,29 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##

Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,53 +1,53 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
 uses CONFIG_UDELAY_IO
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_SERIAL8250
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_VIDEO_MB
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -56,57 +56,57 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 default CONFIG_UDELAY_IO=1
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=0
-default IRQ_SLOT_COUNT=2
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=0
+default CONFIG_IRQ_SLOT_COUNT=2
+default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
@@ -116,32 +116,32 @@
 
 # To Enable the Serial Console
 default CONFIG_CONSOLE_SERIAL8250=1
-default DEFAULT_CONSOLE_LOGLEVEL=8
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 default CONFIG_VIDEO_MB = 0
 

Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -40,7 +40,7 @@
 static void main(unsigned long bist)
 {
 	/* Initialize the serial console. */
-	w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,29 +14,29 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -50,7 +50,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -72,7 +72,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,43 +1,43 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
@@ -46,10 +46,10 @@
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_VIDEO_MB
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -62,17 +62,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=0
+default CONFIG_HAVE_FALLBACK_BOOT=0
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -82,50 +82,50 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=7
-default PIRQ_ROUTE=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=7
+default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -135,21 +135,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -161,14 +161,14 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 default CONFIG_VIDEO_MB = 0
 

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -39,7 +39,7 @@
 static void main(unsigned long bist)
 {
 	/* Initialize the serial console. */
-	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -51,7 +51,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	.signature = PIRQ_SIGNATURE,	/* u32 signature */
 	.version = PIRQ_VERSION,	/* u16 version   */
-	.size = 32+16*IRQ_SLOT_COUNT,	/* There can be total 4 devices on the bus */
+	.size = 32+16*CONFIG_IRQ_SLOT_COUNT,	/* There can be total 4 devices on the bus */
 	.rtr_bus = 0x00,		/* Where the interrupt router lies (bus) */
 	.rtr_devfn = (0x12<<3)|0x0,	/* Where the interrupt router lies (dev) */
 	.exclusive_irqs = 0x4C20,	/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,20 +18,20 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 	# Compile cache_as_ram.c to auto.inc.
 	makerule ./cache_as_ram_auto.inc
-			# depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			depends "$(MAINBOARD)/cache_as_ram_auto.c"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+			# depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
@@ -39,7 +39,7 @@
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -48,7 +48,7 @@
 end
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 #	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,93 +18,93 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_IO
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-default ROM_SIZE = 256 * 1024
+default CONFIG_ROM_SIZE = 256 * 1024
 default CONFIG_CONSOLE_VGA = 0
 default CONFIG_VIDEO_MB = 8
 default CONFIG_PCI_ROM_RUN = 0
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
-default HAVE_HARD_RESET = 0
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_UDELAY_IO = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 9
-default PIRQ_ROUTE = 1
-default HAVE_OPTION_TABLE = 0
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xc8000
-default DCACHE_RAM_SIZE = 32 * 1024
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 9
+default CONFIG_PIRQ_ROUTE = 1
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xc8000
+default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
 default CONFIG_USE_PRINTK_IN_CAR=1
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3
-default DEFAULT_CONSOLE_LOGLEVEL=8
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 
 #

Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -118,7 +118,7 @@
 	/* Note: must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	mb_gpio_init();
 	uart_init();
 	console_init();

Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -47,7 +47,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * IRQ_SLOT_COUNT,/* there can be total 6 devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total 6 devices on the bus */
 	0x00,			/* Where the interrupt router lies (bus) */
 	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
 	EXCLUSIVE_PCI_IRQS,	/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,10 +1,10 @@
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -18,30 +18,30 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -55,7 +55,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -77,7 +77,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,59 +1,59 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_MAX_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
 uses CONFIG_GDB_STUB
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_BTEXT
 uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
-uses MAX_REBOOT_CNT
-uses USE_WATCHDOG_ON_BOOT
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
+uses CONFIG_MAX_REBOOT_CNT
+uses CONFIG_USE_WATCHDOG_ON_BOOT
 
 
 ###
@@ -63,23 +63,23 @@
 ##
 ## Because we do the stutter start we need more attempts
 ##
-default MAX_REBOOT_CNT=8
+default CONFIG_MAX_REBOOT_CNT=8
 
 ##
 ## Use the watchdog to break out of a lockup condition
 ##
-default USE_WATCHDOG_ON_BOOT=1
+default CONFIG_USE_WATCHDOG_ON_BOOT=1
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=2097152
+default CONFIG_ROM_SIZE=2097152
 
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Delay timer options
@@ -91,31 +91,31 @@
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -133,40 +133,40 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="SE7520JR22D"
-default MAINBOARD_VENDOR=     "Intel"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
+default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D"
+default CONFIG_MAINBOARD_VENDOR=     "Intel"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -181,8 +181,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -197,21 +197,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -223,17 +223,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ##
 ## Don't enable the btext console

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -81,7 +81,7 @@
 	/* Setup the console */
 	pc87427_disable_dev(CONSOLE_SERIAL_DEV);
 	pc87427_disable_dev(HIDDEN_SERIAL_DEV);
-	pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+	pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
         /* Enable Serial 2 lines instead of GPIO */
         outb(0x2c, 0x2e);
         outb((inb(0x2f) & (~1<<1)), 0x2f);

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,8 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -32,29 +32,29 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c ../romcc"
-        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c ../romcc"
-        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -68,7 +68,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/reset16.inc
         ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -90,7 +90,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         ldscript /arch/i386/lib/failover.lds
         mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,56 +17,56 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_MAX_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
 uses CONFIG_GDB_STUB
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
 
 
 ###
@@ -74,14 +74,14 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE = 2 * 1024 * 1024
+default CONFIG_ROM_SIZE = 2 * 1024 * 1024
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Delay timer options
@@ -93,19 +93,19 @@
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=1
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code for SMP support
@@ -123,39 +123,39 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="Mt. Arvon"
-default MAINBOARD_VENDOR=     "Intel"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
+default CONFIG_MAINBOARD_PART_NUMBER="Mt. Arvon"
+default CONFIG_MAINBOARD_VENDOR=     "Intel"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
 
 ###
 ### Coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
 
 ##
 ## coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -170,8 +170,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -186,21 +186,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -212,17 +212,17 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=5
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=5
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -86,7 +86,7 @@
 	}
 	/* Set up the console */
 	i3100_enable_superio();
-	i3100_enable_serial(0x4e, I3100_SP1, TTYS0_BASE);
+	i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE, /* u32 signature */
 	PIRQ_VERSION,   /* u16 version   */
-	32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
+	32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
 	0x00,       /* u8 Bus 0 */
 	(0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
 	0x0000,     /* u16 reserve IRQ for PCI */

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,8 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -32,29 +32,29 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c ../romcc"
-        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+        action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c ../romcc"
-        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+        action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -68,7 +68,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/reset16.inc
         ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -90,7 +90,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         ldscript /arch/i386/lib/failover.lds
         mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -17,56 +17,56 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_MAX_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
 uses CONFIG_GDB_STUB
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
 
 
 ###
@@ -74,14 +74,14 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE = 2 * 1024 * 1024
+default CONFIG_ROM_SIZE = 2 * 1024 * 1024
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Delay timer options
@@ -93,19 +93,19 @@
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=1
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=1
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code for SMP support
@@ -123,39 +123,39 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="Truxton"
-default MAINBOARD_VENDOR=     "Intel"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
+default CONFIG_MAINBOARD_PART_NUMBER="Truxton"
+default CONFIG_MAINBOARD_VENDOR=     "Intel"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
 
 ###
 ### Coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
 
 ##
 ## coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -170,8 +170,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -186,21 +186,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -212,17 +212,17 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=5
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=5
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -84,7 +84,7 @@
 
 	/* Set up the console */
 	i3100_enable_superio();
-	i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, TTYS0_BASE);
+	i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE, /* u32 signature */
 	PIRQ_VERSION,   /* u16 version   */
-	32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
+	32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
 	0x00,       /* u8 Bus 0 */
 	(0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
 	0x0000,     /* u16 reserve IRQ for PCI */

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end 
@@ -9,9 +9,9 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE 		object mptable.o 	 end
-if HAVE_PIRQ_TABLE 		object irq_tables.o	 end
-if HAVE_ACPI_TABLES 	object acpi_tables.o end
+if CONFIG_HAVE_MP_TABLE 		object mptable.o 	 end
+if CONFIG_HAVE_PIRQ_TABLE 		object irq_tables.o	 end
+if CONFIG_HAVE_ACPI_TABLES 	object acpi_tables.o end
 object reset.o
 
 # Include the VGA option ROM, but only if we're compiled to use it
@@ -29,22 +29,22 @@
 ## Romcc output
 ##
 makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+        action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ../romcc"
-        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+        action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-        action  "../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+        action  "../romcc    -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -58,8 +58,8 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FALLBACK_BOOT
-    if USE_FALLBACK_IMAGE 
+if CONFIG_HAVE_FALLBACK_BOOT
+    if CONFIG_USE_FALLBACK_IMAGE 
 	    mainboardinit cpu/x86/16bit/reset16.inc 
 	    ldscript /cpu/x86/16bit/reset16.lds
     else
@@ -85,7 +85,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,11 +1,11 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses HAVE_PIRQ_TABLE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_OPTION_TABLE
-uses IRQ_SLOT_COUNT
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_IRQ_SLOT_COUNT
 uses CONFIG_MAX_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
@@ -14,72 +14,72 @@
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses DEBUG
-#uses CPU_OPT
+uses CONFIG_DEBUG
+#uses CONFIG_CPU_OPT
 uses CONFIG_IDE
 
 ## The default definitions are used for these
 uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
+uses CONFIG_PAYLOAD_SIZE
 
 ## These are defined in target Config.lb, don't add here
-uses USE_FALLBACK_IMAGE
-uses ROM_SIZE
-uses ROM_IMAGE_SIZE
-uses FALLBACK_SIZE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_FALLBACK_SIZE
 uses COREBOOT_EXTRA_VERSION
 
 ## These are defined in mainboard Config.lb, don't add here
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
 
 ###
 ### Build options
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=2097152
-default ROM_IMAGE_SIZE = 65536
+default CONFIG_ROM_SIZE=2097152
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Build code for the fallback boot?
 ##
-default HAVE_FALLBACK_BOOT=1
-default FALLBACK_SIZE=131072
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_FALLBACK_SIZE=131072
 
 
 ## Delay timer options
@@ -90,28 +90,28 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=12
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=12
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## Build code to export ACPI tables?
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 
 ##
 ## Build code to export a CMOS option table?
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ## CMOS checksum definitions (units == bytes)
 ## These must match the checksum record in cmos.layout
-default LB_CKS_RANGE_START=128
-default LB_CKS_RANGE_END=130
-default LB_CKS_LOC=131
+default CONFIG_LB_CKS_RANGE_START=128
+default CONFIG_LB_CKS_RANGE_END=130
+default CONFIG_LB_CKS_LOC=131
 
 ##
 ## Build code for SMP support
@@ -138,10 +138,10 @@
 ##
 ## Motherboard identification
 ##
-default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
-default MAINBOARD_VENDOR="Intel"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
+default CONFIG_MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
+default CONFIG_MAINBOARD_VENDOR="Intel"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
 
 ###
 ### coreboot layout values
@@ -150,22 +150,22 @@
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## CMOS settings not currently supported due to conflicts with factory BIOS
 ##
-default USE_OPTION_TABLE = 0
+default CONFIG_USE_OPTION_TABLE = 0
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -179,8 +179,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -195,21 +195,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -221,23 +221,23 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ## Things we may not have
 default CONFIG_IDE=1
 
-default DEBUG=1
-# default CPU_OPT="-g"
+default CONFIG_DEBUG=1
+# default CONFIG_CPU_OPT="-g"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -66,7 +66,7 @@
 
 	// Get the serial port running and print a welcome banner
 
-    lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
+    lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
     uart_init();
     console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
 arch i386 end 
@@ -15,25 +15,25 @@
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE 
+if CONFIG_HAVE_MP_TABLE 
 	object mptable.o 
 end
 
-if HAVE_PIRQ_TABLE 
+if CONFIG_HAVE_PIRQ_TABLE 
 	object irq_tables.o 
 end
 
-#if HAVE_ACPI_TABLES
+#if CONFIG_HAVE_ACPI_TABLES
 #       object acpi_tables.o
 #       object fadt.o
-#       if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_SB_HT_CHAIN_ON_BUS0
 #               object dsdt_bus0.o
 #       else
 #               object dsdt.o
 #       end
 #       object ssdt.o
-#       if ACPI_SSDTX_NUM
-#                if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_ACPI_SSDTX_NUM
+#                if CONFIG_SB_HT_CHAIN_ON_BUS0
 #                 object ssdt2_bus0.o
 #                else
 #                 object ssdt2.o
@@ -41,43 +41,43 @@
 #       end
 #end
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
         object acpi_tables.o
         object fadt.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
+		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
 		action  "mv dsdt_lb.hex dsdt.c"
 	end
         object ./dsdt.o
 
 	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
 	
-        if ACPI_SSDTX_NUM
+        if CONFIG_ACPI_SSDTX_NUM
             makerule ssdt2.c
-                        depends "$(MAINBOARD)/dx/pci2.asl"
-                        action  "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
+                        action  "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
                         action  "mv pci2.hex ssdt2.c"
             end
             object ./ssdt2.o
             makerule ssdt3.c
-                        depends "$(MAINBOARD)/dx/pci3.asl"
-                        action  "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
+                        action  "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
                         action  "mv pci3.hex ssdt3.c"
             end
             object ./ssdt3.o
             makerule ssdt4.c
-                        depends "$(MAINBOARD)/dx/pci4.asl"
-                        action  "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
+                        action  "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
                         action  "mv pci4.hex ssdt4.c"
             end
             object ./ssdt4.o
             makerule ssdt5.c
-                        depends "$(MAINBOARD)/dx/pci5.asl"
-                        action  "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
+                        action  "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
                         action  "mv pci5.hex ssdt5.c"
             end
@@ -88,27 +88,27 @@
 	if CONFIG_USE_INIT
 		# compile cache_as_ram.c to auto.o
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else   
 		#compile cache_as_ram.c to auto.inc 
 		makerule ./cache_as_ram_auto.inc
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 
 	end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
 	makerule ./apc_auto.o
-		depends "$(MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
 	end
 	ldscript /arch/i386/init/ldscript_apc.lb
     end
@@ -118,13 +118,13 @@
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
@@ -142,8 +142,8 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -151,7 +151,7 @@
 	ldscript /cpu/x86/32bit/reset32.lds 
     end
 else
-    if USE_FALLBACK_IMAGE 
+    if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -176,12 +176,12 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 		ldscript /arch/i386/lib/failover_failover.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
     end
 end

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,85 +1,85 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
 
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
 
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
@@ -87,9 +87,9 @@
 
 uses CONFIG_AP_CODE_IN_CAR
 
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
 
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -98,20 +98,20 @@
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
 
 #FALLBACK: 256K-8K
-default FALLBACK_SIZE=0x3e000
+default CONFIG_FALLBACK_SIZE=0x3e000
 #FAILOVER: 8K
-default FAILOVER_SIZE=0x02000
+default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -119,42 +119,42 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 ## extra SSDT num
-default ACPI_SSDTX_NUM=3
+default CONFIG_ACPI_SSDTX_NUM=3
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -165,41 +165,41 @@
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-default SERIAL_CPU_INIT=0
+default CONFIG_SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x10
+default CONFIG_LIFT_BSP_APIC_ID=1
 
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
 #1G
-#default HW_MEM_HOLE_SIZEK=0x100000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 #512M
-default HW_MEM_HOLE_SIZEK=0x80000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
 
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
 
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
 
 #HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0xa
+default CONFIG_HT_CHAIN_UNITID_BASE=0xa
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
-default HT_CHAIN_END_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
 
 #make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
 
 #only offset for SB chain?, default is yes(1)
-#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 
 #allow capable device use that above 4G
 #default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -207,18 +207,18 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc4000
-default DCACHE_RAM_SIZE=0x0c000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc4000
+default CONFIG_DCACHE_RAM_SIZE=0x0c000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 ##
 ## for rev F training on AP purpose
 ##
 #default CONFIG_AP_CODE_IN_CAR=1
-#default MEM_TRAIN_SEQ=1
-#default WAIT_BEFORE_CPUS_INIT=1
+#default CONFIG_MEM_TRAIN_SEQ=1
+#default CONFIG_WAIT_BEFORE_CPUS_INIT=1
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -228,37 +228,37 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="dk8_htx"
-default MAINBOARD_VENDOR="IWILL"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+default CONFIG_MAINBOARD_PART_NUMBER="dk8_htx"
+default CONFIG_MAINBOARD_VENDOR="IWILL"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Load the payload from the ROM
@@ -272,8 +272,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -289,21 +289,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -315,17 +315,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/acpi_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/acpi_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -40,7 +40,7 @@
 
 extern unsigned char AmlCode[];
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 extern unsigned char AmlCode_ssdt2[];
 extern unsigned char AmlCode_ssdt3[];
 extern unsigned char AmlCode_ssdt4[];
@@ -266,7 +266,7 @@
 	current += ssdt->length;
 	acpi_add_table(rsdt, ssdt);
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
         //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,7 +19,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -34,7 +34,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
@@ -48,7 +48,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -132,7 +132,7 @@
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -177,7 +177,7 @@
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -191,21 +191,21 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -221,7 +221,7 @@
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
@@ -230,7 +230,7 @@
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -243,7 +243,7 @@
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
 #endif
 	setup_coherent_ht_domain(); // routing table and start other core0

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/get_bus_conf.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -109,7 +109,7 @@
         dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
         if (dev) {
                 m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
 //		printk_debug("bus_isa=%d\n",bus_isa);
@@ -132,7 +132,7 @@
         dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
         if (dev) {
                 m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
 //              printk_debug("bus_isa=%d\n",bus_isa);

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,8 +13,8 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ## ATI Rage XL framebuffering graphics driver
@@ -23,15 +23,15 @@
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 end
 
 else    
                 
 makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -41,7 +41,7 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
         ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -59,7 +59,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -83,7 +83,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,106 +1,106 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE=524288
 
 ###
 ### Build options
 ###
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -118,46 +118,46 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
  
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="HDAMA"
-default MAINBOARD_VENDOR="ARIMA"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
+default CONFIG_MAINBOARD_VENDOR="ARIMA"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -171,8 +171,8 @@
 ##
 ## The default compiler
 ##
-#default CC="$(CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
+#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+#default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -189,21 +189,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -215,17 +215,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,7 +19,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -34,7 +34,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
@@ -48,7 +48,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -132,7 +132,7 @@
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -177,7 +177,7 @@
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -191,21 +191,21 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -221,7 +221,7 @@
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
@@ -230,7 +230,7 @@
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -243,7 +243,7 @@
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
 #endif
 	setup_coherent_ht_domain(); // routing table and start other core0

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,22 +13,22 @@
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 end
 
 else    
                 
 makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -38,7 +38,7 @@
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
         ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -56,7 +56,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -80,7 +80,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,106 +1,106 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE=524288
 
 ###
 ### Build options
 ###
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -118,45 +118,45 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
  
 ##
 ## Clean up the motherboard id strings
 ##
-#default MAINBOARD_PART_NUMBER="HDAMA"
-#default MAINBOARD_VENDOR="ARIMA"
-#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+#default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
+#default CONFIG_MAINBOARD_VENDOR="ARIMA"
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -170,8 +170,8 @@
 ##
 ## The default compiler
 ##
-#default CC="$(CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
+#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+#default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -188,21 +188,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -214,17 +214,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,7 +19,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -34,7 +34,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
@@ -48,7 +48,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -132,7 +132,7 @@
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -177,7 +177,7 @@
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -191,21 +191,21 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -221,7 +221,7 @@
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
@@ -230,7 +230,7 @@
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -243,7 +243,7 @@
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
 #endif
 	setup_coherent_ht_domain(); // routing table and start other core0

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,7 +18,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT 
+	32+16*CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT 
 				 * devices on the bus */
 	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
 	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */

Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,40 +19,40 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_ACPI_TABLES
 	object fadt.o
 	object dsdt.o
 	object acpi_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -62,7 +62,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -19,83 +19,83 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_MAX_PCI_BUSES
-uses TTYS0_BAUD
+uses CONFIG_TTYS0_BAUD
 uses CONFIG_VIDEO_MB
 uses CONFIG_IOAPIC
 
-default ROM_SIZE = 512 * 1024
+default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_IOAPIC = 0
 default CONFIG_VIDEO_MB = 32
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default CONFIG_PCI_ROM_RUN = 0
 default CONFIG_CONSOLE_VGA = 0
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_MP_TABLE = 0
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_MP_TABLE = 0
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default HAVE_HARD_RESET = 0
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 10
-default HAVE_ACPI_TABLES = 0
-default HAVE_OPTION_TABLE = 0
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = ROM_SIZE
-default USE_FALLBACK_IMAGE = 1
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 16 * 1024
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-#default USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 10
+default CONFIG_HAVE_ACPI_TABLES = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
+default CONFIG_USE_FALLBACK_IMAGE = 1
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+#default CONFIG_USE_OPTION_TABLE = 0
+default CONFIG_RAMBASE = 0x00004000
 default CONFIG_ROM_PAYLOAD = 1
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
+default CONFIG_HOSTCC = "gcc"
 
 ##
 ## Set this to the max PCI bus number you would ever use for PCI config I/O.

Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -40,7 +40,7 @@
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
 
-#if TTYS0_BASE == 0x2f8
+#if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
 #else
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
@@ -101,7 +101,7 @@
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
-	f71805f_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -24,7 +24,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x11 << 3) | 0x0,	/* Interrupt router device */
 	0x828,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -26,10 +26,10 @@
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -44,16 +44,16 @@
 
 driver mainboard.o
 driver rtl8168.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
-if HAVE_SMI_HANDLER smmobject mainboard_smi.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
 	object fadt.o
 	object acpi_tables.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dsdt.asl"
-		action  "iasl -p dsdt -tc $(MAINBOARD)/dsdt.asl"
+		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+		action  "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
 		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
 	end
 	object ./dsdt.o
@@ -64,15 +64,15 @@
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-	depends "$(MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 else
 
 makerule ./auto.inc
-	depends "$(MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
 	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -93,7 +93,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
         mainboardinit cpu/x86/16bit/reset16.inc
         ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -118,7 +118,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 end
 

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -20,17 +20,17 @@
 ##
 
 # Tables
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses HAVE_MAINBOARD_RESOURCES
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
 # SMP
 uses CONFIG_SMP
 uses CONFIG_LOGICAL_CPUS
@@ -39,71 +39,71 @@
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 # Image Size
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 # Payload
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
+uses CONFIG_PAYLOAD_SIZE
 # Build Internals
-uses _RAMBASE
-uses _ROMBASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_RAMBASE
+uses CONFIG_ROMBASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
-uses XIP_ROM_BASE
-uses XIP_ROM_SIZE
-uses HAVE_HARD_RESET
-uses HAVE_SMI_HANDLER
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_SMI_HANDLER
 uses CONFIG_PCIE_CONFIGSPACE_HOLE
-uses MMCONF_SUPPORT
-uses MMCONF_BASE_ADDRESS
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_MMCONF_BASE_ADDRESS
 uses CONFIG_GFXUMA
 uses CONFIG_CBFS
 
 #
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 # Timers
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 # Console
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_VGA_ROM_RUN
 uses CONFIG_PCI_ROM_RUN
-uses DEBUG
+uses CONFIG_DEBUG
 # Toolchain
 uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
 # Tweaks
 uses CONFIG_GDB_STUB
-uses MAX_REBOOT_CNT
-uses USE_WATCHDOG_ON_BOOT
+uses CONFIG_MAX_REBOOT_CNT
+uses CONFIG_USE_WATCHDOG_ON_BOOT
 uses COREBOOT_EXTRA_VERSION
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 
 ###
 ### Build options
@@ -111,23 +111,23 @@
 
 ##
 ##
-default MAX_REBOOT_CNT=3
+default CONFIG_MAX_REBOOT_CNT=3
 
 ##
 ## Use the watchdog to break out of a lockup condition
 ##
-default USE_WATCHDOG_ON_BOOT=0
+default CONFIG_USE_WATCHDOG_ON_BOOT=0
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=1024*1024
+default CONFIG_ROM_SIZE=1024*1024
 
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Delay timer options
@@ -139,20 +139,20 @@
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build SMI handler
 ##
-default HAVE_SMI_HANDLER=1
+default CONFIG_HAVE_SMI_HANDLER=1
 
 ##
 ## Leave a hole for mmapped PCIe config space
 ##
 
 default CONFIG_PCIE_CONFIGSPACE_HOLE=1
-default MMCONF_SUPPORT=1
-default MMCONF_BASE_ADDRESS=0xf0000000
+default CONFIG_MMCONF_SUPPORT=1
+default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
 
 ##
 ## UMA
@@ -162,32 +162,32 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=18
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=18
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to provide ACPI support
 ##
-default HAVE_ACPI_TABLES=1
-default HAVE_MAINBOARD_RESOURCES=1
+default CONFIG_HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
@@ -196,7 +196,7 @@
 # for now:
 default CONFIG_VGA_ROM_RUN=1
 default CONFIG_PCI_ROM_RUN=0
-default DEBUG=0
+default CONFIG_DEBUG=0
 
 ##
 ## Build code for SMP support
@@ -211,9 +211,9 @@
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_SIZE=0x8000
-default DCACHE_RAM_BASE=( 0xfff00000 - DCACHE_RAM_SIZE - 1024*1024)
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
 default CONFIG_USE_PRINTK_IN_CAR=1
 
 ##
@@ -224,37 +224,37 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="986LCD-M"
-default MAINBOARD_VENDOR=     "KONTRON"
+default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M"
+default CONFIG_MAINBOARD_VENDOR=     "KONTRON"
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default FALLBACK_SIZE=ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
 
 ##
 ## coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Load the payload from the ROM
@@ -268,8 +268,8 @@
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -284,21 +284,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -310,17 +310,17 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=5
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=9
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -313,7 +313,7 @@
 
 	printk_debug("ACPI:     * DMI (Linux workaround)\n");
 	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if HAVE_HIGH_TABLES == 1
+#if CONFIG_HAVE_HIGH_TABLES == 1
 	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
 	current += DMI_TABLE_SIZE;
 	ALIGN_CURRENT;

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -296,7 +296,7 @@
 	RCBA32(0x2034) = reg32;
 }
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i82801gx/cmos_failover.c"
 #endif
 
@@ -331,7 +331,7 @@
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 	
-#if DEFAULT_CONSOLE_LOGLEVEL > 8
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 	dump_spd_registers();
 #endif
 
@@ -351,7 +351,7 @@
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization();
 
-#if DEFAULT_CONSOLE_LOGLEVEL > 8
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 #if defined(DEBUG_RAM_SETUP)
 	sdram_dump_mchbar_registers();
 #endif

Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -14,29 +14,29 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ##
 ## Romcc output
 ##
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
@@ -50,7 +50,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -72,7 +72,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,50 +1,50 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE  = 256*1024
 
 ###
 ### Build options
@@ -53,17 +53,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
 
 ## Delay timer options
 ##
@@ -73,49 +73,49 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=2
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=2
 #object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## The Serial Console
@@ -125,21 +125,21 @@
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -151,13 +151,13 @@
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 
 #

Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -84,7 +84,7 @@
 	SystemPreInit();
 	msr_init();
 
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -20,8 +20,8 @@
 
 ## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -36,14 +36,14 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
 	# compile cache_as_ram.c to auto.inc
 	makerule ./cache_as_ram_auto.inc
-		depends "$(MAINBOARD)/cache_as_ram_auto.c"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		action "perl -e 's/.rodata/.rom.data/g' -pi $@"
 		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 	end
@@ -59,7 +59,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -81,7 +81,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 #	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -20,69 +20,69 @@
 
 ## Based on Options.lb from AMD's DB800 mainboard.
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_IDE
 uses CONFIG_FS_PAYLOAD
 uses CONFIG_FS_EXT2
-uses AUTOBOOT_DELAY
-uses AUTOBOOT_CMDLINE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_AUTOBOOT_DELAY
+uses CONFIG_AUTOBOOT_CMDLINE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEBUG
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEBUG
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 512 * 1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE = 512 * 1024
 
 ###
 ### Build options
@@ -94,17 +94,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE = 0
+default CONFIG_HAVE_MP_TABLE = 0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET = 0
+default CONFIG_HAVE_HARD_RESET = 0
 
 ## Delay timer options
 ##
@@ -114,57 +114,57 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 7
-default PIRQ_ROUTE = 1
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 7
+default CONFIG_PIRQ_ROUTE = 1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xc8000
-default DCACHE_RAM_SIZE = 0x08000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xc8000
+default CONFIG_DCACHE_RAM_SIZE = 0x08000
 default CONFIG_USE_PRINTK_IN_CAR=1
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE = 8 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE = 16 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 
 ##
 ## The Serial Console
@@ -174,24 +174,24 @@
 default CONFIG_CONSOLE_SERIAL8250 = 1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD = 115200
-#default TTYS0_BAUD = 57600
-#default TTYS0_BAUD = 38400
-#default TTYS0_BAUD = 19200
-#default TTYS0_BAUD = 9600
-#default TTYS0_BAUD = 4800
-#default TTYS0_BAUD = 2400
-#default TTYS0_BAUD = 1200
+default CONFIG_TTYS0_BAUD = 115200
+#default CONFIG_TTYS0_BAUD = 57600
+#default CONFIG_TTYS0_BAUD = 38400
+#default CONFIG_TTYS0_BAUD = 19200
+#default CONFIG_TTYS0_BAUD = 9600
+#default CONFIG_TTYS0_BAUD = 4800
+#default CONFIG_TTYS0_BAUD = 2400
+#default CONFIG_TTYS0_BAUD = 1200
 
 # Select the serial console base port
-default TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_BASE = 0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS = 0x3
+default CONFIG_TTYS0_LCS = 0x3
 
 # Compile extra debugging code
-default DEBUG = 1
+default CONFIG_DEBUG = 1
 
 ##
 ### Select the coreboot loglevel
@@ -203,13 +203,13 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL = 8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL = 8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -103,7 +103,7 @@
 	0x1E2C,		// disable ATXPowerGood - will cause a reboot!
 	0x0423,		// don't delay POWerOK1/2
 	0x9072,		// watchdog triggers POWOK, counts seconds
-#if !USE_WATCHDOG_ON_BOOT
+#if !CONFIG_USE_WATCHDOG_ON_BOOT
 	0x0073, 0x0074,	// disable watchdog by setting timeout to 0
 #endif
 	0xBF25, 0x372A, 0xF326, // select GPIO function for most pins
@@ -149,7 +149,7 @@
 	 * Note: must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter
+	it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
 	mb_gpio_init();
 	uart_init();
 	console_init();

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -47,7 +47,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */
 	0x00,			/* Where the interrupt router lies (bus) */
 	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */
@@ -57,7 +57,7 @@
 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
 	0xE0,			/* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-		/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+		/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
 		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* CPU */
 		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */

Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -20,8 +20,8 @@
 
 ## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -35,14 +35,14 @@
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 
 	# compile cache_as_ram.c to auto.inc
 	makerule ./cache_as_ram_auto.inc
-		depends "$(MAINBOARD)/cache_as_ram_auto.c"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 	end
@@ -58,7 +58,7 @@
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -80,7 +80,7 @@
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 #	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -20,69 +20,69 @@
 
 ## Based on Options.lb from AMD's DB800 mainboard.
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_IDE
 uses CONFIG_FS_PAYLOAD
 uses CONFIG_FS_EXT2
-uses AUTOBOOT_DELAY
-uses AUTOBOOT_CMDLINE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_AUTOBOOT_DELAY
+uses CONFIG_AUTOBOOT_CMDLINE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEBUG
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEBUG
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 512*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE = 512*1024
 
 ###
 ### Build options
@@ -94,17 +94,17 @@
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
 
 ##
 ## no MP table
 ##
-default HAVE_MP_TABLE = 0
+default CONFIG_HAVE_MP_TABLE = 0
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET = 0
+default CONFIG_HAVE_HARD_RESET = 0
 
 ## Delay timer options
 ##
@@ -114,57 +114,57 @@
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 7
-default PIRQ_ROUTE = 1
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 7
+default CONFIG_PIRQ_ROUTE = 1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
 
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xc8000
-default DCACHE_RAM_SIZE = 0x08000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xc8000
+default CONFIG_DCACHE_RAM_SIZE = 0x08000
 default CONFIG_USE_PRINTK_IN_CAR=1
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE = 0x2000
+default CONFIG_STACK_SIZE = 0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE = 0x4000
+default CONFIG_HEAP_SIZE = 0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
 
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
 
 default CONFIG_ROM_PAYLOAD = 1
 
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
 
 ##
 ## The Serial Console
@@ -174,24 +174,24 @@
 default CONFIG_CONSOLE_SERIAL8250 = 1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD = 115200
-#default TTYS0_BAUD = 57600
-#default TTYS0_BAUD = 38400
-#default TTYS0_BAUD = 19200
-#default TTYS0_BAUD = 9600
-#default TTYS0_BAUD = 4800
-#default TTYS0_BAUD = 2400
-#default TTYS0_BAUD = 1200
+default CONFIG_TTYS0_BAUD = 115200
+#default CONFIG_TTYS0_BAUD = 57600
+#default CONFIG_TTYS0_BAUD = 38400
+#default CONFIG_TTYS0_BAUD = 19200
+#default CONFIG_TTYS0_BAUD = 9600
+#default CONFIG_TTYS0_BAUD = 4800
+#default CONFIG_TTYS0_BAUD = 2400
+#default CONFIG_TTYS0_BAUD = 1200
 
 # Select the serial console base port
-default TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_BASE = 0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS = 0x3
+default CONFIG_TTYS0_LCS = 0x3
 
 # Compile extra debugging code
-default DEBUG = 1
+default CONFIG_DEBUG = 1
 
 ##
 ### Select the coreboot loglevel
@@ -203,13 +203,13 @@
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
-## DEBUG      8   debug-level messages
+## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL = 8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL = 8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 
 #
 # CBFS

Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -89,7 +89,7 @@
 	if (device != DIMM0)
 		return 0xFF;	/* No DIMM1, don't even try. */
 
-#if DEBUG
+#if CONFIG_DEBUG
 	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
 		print_err("ERROR: spd_read_byte(DIMM0, 0x");
 		print_err_hex8(address);
@@ -165,7 +165,7 @@
 	0x1E2C,		// disable ATXPowerGood
 	0x0423,		// don't delay POWerOK1/2
 	0x9072,		// watchdog triggers POWOK, counts seconds
-#if !USE_WATCHDOG_ON_BOOT
+#if !CONFIG_USE_WATCHDOG_ON_BOOT
 	0x0073, 0x0074,	// disable watchdog by setting timeout to 0
 #endif
 	0xBF25, 0x172A, 0xF326,	// select GPIO function for most pins
@@ -211,7 +211,7 @@
 	 * Note: Must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter
+	it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
 	mb_gpio_init();
 	uart_init();
 	console_init();

Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/irq_tables.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/irq_tables.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -47,7 +47,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */
 	0x00,			/* Where the interrupt router lies (bus) */
 	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */
@@ -57,7 +57,7 @@
 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
 	0xE0,			/* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-		/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+		/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
 		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* CPU */
 		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */

Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -15,7 +15,7 @@
 object clock.o
 
 ##
-## Set our ARCH
+## Set our CONFIG_ARCH
 ##
 arch ppc end
 
@@ -26,5 +26,5 @@
 dir nvram
 dir flash
 
-addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
 makedefine CFLAGS += -g

Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -5,70 +5,70 @@
 uses CONFIG_SANDPOINT_UNITY
 uses CONFIG_SANDPOINT_VALIS
 uses CONFIG_SANDPOINT_GYRUS
-uses ISA_IO_BASE
-uses ISA_MEM_BASE
-uses PCIC0_CFGADDR
-uses PCIC0_CFGDATA
-uses PNP_CFGADDR
-uses PNP_CFGDATA
-uses _IO_BASE
+uses CONFIG_ISA_IO_BASE
+uses CONFIG_ISA_MEM_BASE
+uses CONFIG_PCIC0_CFGADDR
+uses CONFIG_PCIC0_CFGDATA
+uses CONFIG_PNP_CFGADDR
+uses CONFIG_PNP_CFGDATA
+uses CONFIG_IO_BASE
 
-uses CROSS_COMPILE 
-uses HAVE_OPTION_TABLE
+uses CONFIG_CROSS_COMPILE 
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_SANDPOINT_ALTIMUS 
 uses CONFIG_COMPRESS 
-uses DEFAULT_CONSOLE_LOGLEVEL 
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 uses CONFIG_USE_INIT
 uses CONFIG_CHIP_CONFIGURE
-uses NO_POST
+uses CONFIG_NO_POST
 uses CONFIG_CONSOLE_SERIAL8250 
-uses TTYS0_BASE 
+uses CONFIG_TTYS0_BASE 
 uses CONFIG_IDE
 uses CONFIG_FS_PAYLOAD 
 uses CONFIG_FS_EXT2
 uses CONFIG_FS_ISO9660
 uses CONFIG_FS_FAT
-uses AUTOBOOT_CMDLINE
-uses PAYLOAD_SIZE
-uses ROM_SIZE
-uses ROM_IMAGE_SIZE
-uses _RESET
-uses _EXCEPTION_VECTORS
-uses _ROMBASE
-uses _ROMSTART
-uses _RAMBASE
-uses _RAMSTART
-uses STACK_SIZE
-uses HEAP_SIZE
+uses CONFIG_AUTOBOOT_CMDLINE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_RESET
+uses CONFIG_EXCEPTION_VECTORS
+uses CONFIG_ROMBASE
+uses CONFIG_ROMSTART
+uses CONFIG_RAMBASE
+uses CONFIG_RAMSTART
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
 
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 
 ##
 ## Set memory map
 ##
-default ISA_IO_BASE=0xfe000000
-default ISA_MEM_BASE=0xfd000000
-default PCIC0_CFGADDR=0xfec00000
-default PCIC0_CFGDATA=0xfee00000
-default PNP_CFGADDR=0x15c
-default PNP_CFGDATA=0x15d
-default _IO_BASE=ISA_IO_BASE
+default CONFIG_ISA_IO_BASE=0xfe000000
+default CONFIG_ISA_MEM_BASE=0xfd000000
+default CONFIG_PCIC0_CFGADDR=0xfec00000
+default CONFIG_PCIC0_CFGDATA=0xfee00000
+default CONFIG_PNP_CFGADDR=0x15c
+default CONFIG_PNP_CFGDATA=0x15d
+default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
 
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc"
+default CONFIG_HOSTCC="gcc"
 ## use a cross compiler
-#default CROSS_COMPILE="powerpc-eabi-"
-#default CROSS_COMPILE="ppc_74xx-"
+#default CONFIG_CROSS_COMPILE="powerpc-eabi-"
+#default CONFIG_CROSS_COMPILE="ppc_74xx-"
 default CONFIG_ARCH_X86=0
 
 ## Use stage 1 initialization code
@@ -81,12 +81,12 @@
 default CONFIG_COMPRESS=0
 
 ## Turn off POST codes
-default NO_POST=1
+default CONFIG_NO_POST=1
 
 ## Enable serial console
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default CONFIG_CONSOLE_SERIAL8250=1
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 ## Load payload using filo
 default CONFIG_IDE=1
@@ -94,34 +94,34 @@
 default CONFIG_FS_EXT2=1
 default CONFIG_FS_ISO9660=1
 default CONFIG_FS_FAT=1
-default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
+default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
 
 # coreboot must fit into 128KB
-default ROM_IMAGE_SIZE=131072
-default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
-default PAYLOAD_SIZE=262144
+default CONFIG_ROM_IMAGE_SIZE=131072
+default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE}
+default CONFIG_PAYLOAD_SIZE=262144
 
 # Set stack and heap sizes (stage 2)
-default STACK_SIZE=0x10000
-default HEAP_SIZE=0x10000
+default CONFIG_STACK_SIZE=0x10000
+default CONFIG_HEAP_SIZE=0x10000
 
 # Sandpoint Demo Board
 ## Base of ROM
-default _ROMBASE=0xfff00000
+default CONFIG_ROMBASE=0xfff00000
 
 ## Sandpoint reset vector
-default _RESET=_ROMBASE+0x100
+default CONFIG_RESET=CONFIG_ROMBASE+0x100
 
 ## Exception vectors (other than reset vector)
-default _EXCEPTION_VECTORS=_RESET+0x100
+default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
 
 ## Start of coreboot in the boot rom
-## = _RESET + exeception vector table size
-default _ROMSTART=_RESET+0x3100
+## = CONFIG_RESET + exeception vector table size
+default CONFIG_ROMSTART=CONFIG_RESET+0x3100
 
 ## Coreboot C code runs at this location in RAM
-default _RAMBASE=0x00100000
-default _RAMSTART=0x00100000
+default CONFIG_RAMBASE=0x00100000
+default CONFIG_RAMSTART=0x00100000
 
 default CONFIG_SANDPOINT_ALTIMUS=1
 

Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/init.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/init.c	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/init.c	2009-06-30 15:17:49 UTC (rev 4381)
@@ -38,8 +38,8 @@
 
 void pnp_output(char address, char data)
 {
-	outb(address, PNP_CFGADDR);
-	outb(data, PNP_CFGDATA);
+	outb(address, CONFIG_PNP_CFGADDR);
+	outb(data, CONFIG_PNP_CFGDATA);
 }
 
 void
@@ -55,10 +55,10 @@
 	 */
 	pnp_output(0x07, 6); /* LD 6 = UART0 */
 	pnp_output(0x30, 0); /* Dectivate */
-	pnp_output(0x60, TTYS0_BASE >> 8); /* IO Base */
-	pnp_output(0x61, TTYS0_BASE & 0xFF); /* IO Base */
+	pnp_output(0x60, CONFIG_TTYS0_BASE >> 8); /* IO Base */
+	pnp_output(0x61, CONFIG_TTYS0_BASE & 0xFF); /* IO Base */
 	pnp_output(0x30, 1); /* Activate */
-	uart8250_init(TTYS0_BASE, 115200/TTYS0_BAUD, TTYS0_LCS);
+	uart8250_init(CONFIG_TTYS0_BASE, 115200/CONFIG_TTYS0_BAUD, CONFIG_TTYS0_LCS);
 }
 
 void

Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -1,22 +1,22 @@
-uses ISA_IO_BASE
+uses CONFIG_ISA_IO_BASE
 uses CONFIG_CBFS
-uses ISA_MEM_BASE
-uses PCIC0_CFGADDR
-uses PCIC0_CFGDATA
-uses PNP_CFGADDR
-uses PNP_CFGDATA
-uses _IO_BASE
+uses CONFIG_ISA_MEM_BASE
+uses CONFIG_PCIC0_CFGADDR
+uses CONFIG_PCIC0_CFGDATA
+uses CONFIG_PNP_CFGADDR
+uses CONFIG_PNP_CFGDATA
+uses CONFIG_IO_BASE
 
-uses CROSS_COMPILE 
-uses HAVE_OPTION_TABLE
+uses CONFIG_CROSS_COMPILE 
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_SANDPOINT_ALTIMUS 
 uses CONFIG_COMPRESS 
-uses DEFAULT_CONSOLE_LOGLEVEL 
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
 uses CONFIG_USE_INIT
 uses CONFIG_CHIP_CONFIGURE
-uses NO_POST
+uses CONFIG_NO_POST
 uses CONFIG_CONSOLE_SERIAL8250 
-uses TTYS0_BASE 
+uses CONFIG_TTYS0_BASE 
 uses CONFIG_IDE
 uses CONFIG_FS_PAYLOAD 
 uses CONFIG_FS_EXT2
@@ -24,47 +24,47 @@
 uses CONFIG_FS_FAT
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses AUTOBOOT_CMDLINE
-uses PAYLOAD_SIZE
-uses ROM_SIZE
-uses ROM_IMAGE_SIZE
-uses _RESET
-uses _EXCEPTION_VECTORS
-uses _ROMBASE
-uses _ROMSTART
-uses _RAMBASE
-uses _RAMSTART
-uses STACK_SIZE
-uses HEAP_SIZE
+uses CONFIG_AUTOBOOT_CMDLINE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_RESET
+uses CONFIG_EXCEPTION_VECTORS
+uses CONFIG_ROMBASE
+uses CONFIG_ROMSTART
+uses CONFIG_RAMBASE
+uses CONFIG_RAMSTART
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
 
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 
 ##
 ## Set memory map
 ##
-default ISA_IO_BASE=0xfe000000
-default ISA_MEM_BASE=0xfd000000
-default PCIC0_CFGADDR=0xfec00000
-default PCIC0_CFGDATA=0xfee00000
-default PNP_CFGADDR=0x15c
-default PNP_CFGDATA=0x15d
-default _IO_BASE=ISA_IO_BASE
+default CONFIG_ISA_IO_BASE=0xfe000000
+default CONFIG_ISA_MEM_BASE=0xfd000000
+default CONFIG_PCIC0_CFGADDR=0xfec00000
+default CONFIG_PCIC0_CFGDATA=0xfee00000
+default CONFIG_PNP_CFGADDR=0x15c
+default CONFIG_PNP_CFGDATA=0x15d
+default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
 
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc"
+default CONFIG_HOSTCC="gcc"
 ## use a cross compiler
-#default CROSS_COMPILE="powerpc-eabi-"
-#default CROSS_COMPILE="ppc_74xx-"
+#default CONFIG_CROSS_COMPILE="powerpc-eabi-"
+#default CONFIG_CROSS_COMPILE="ppc_74xx-"
 
 ## Use stage 1 initialization code
 default CONFIG_USE_INIT=1
@@ -76,12 +76,12 @@
 default CONFIG_COMPRESS=0
 
 ## Turn off POST codes
-default NO_POST=1
+default CONFIG_NO_POST=1
 
 ## Enable serial console
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default CONFIG_CONSOLE_SERIAL8250=1
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 ## Load payload using filo
 default CONFIG_IDE=1
@@ -89,34 +89,34 @@
 default CONFIG_FS_EXT2=1
 default CONFIG_FS_ISO9660=1
 default CONFIG_FS_FAT=1
-default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
+default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
 
 # coreboot must fit into 128KB
-default ROM_IMAGE_SIZE=131072
-default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
-default PAYLOAD_SIZE=262144
+default CONFIG_ROM_IMAGE_SIZE=131072
+default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE}
+default CONFIG_PAYLOAD_SIZE=262144
 
 # Set stack and heap sizes (stage 2)
-default STACK_SIZE=0x10000
-default HEAP_SIZE=0x10000
+default CONFIG_STACK_SIZE=0x10000
+default CONFIG_HEAP_SIZE=0x10000
 
 # Sandpoint Demo Board
 ## Base of ROM
-default _ROMBASE=0xfff00000
+default CONFIG_ROMBASE=0xfff00000
 
 ## Sandpoint reset vector
-default _RESET=_ROMBASE+0x100
+default CONFIG_RESET=CONFIG_ROMBASE+0x100
 
 ## Exception vectors (other than reset vector)
-default _EXCEPTION_VECTORS=_RESET+0x100
+default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
 
 ## Start of coreboot in the boot rom
-## = _RESET + exeception vector table size
-default _ROMSTART=_RESET+0x3100
+## = CONFIG_RESET + exeception vector table size
+default CONFIG_ROMSTART=CONFIG_RESET+0x3100
 
 ## Coreboot C code runs at this location in RAM
-default _RAMBASE=0x00100000
-default _RAMSTART=0x00100000
+default CONFIG_RAMBASE=0x00100000
+default CONFIG_RAMSTART=0x00100000
 
 ### End Options.lb
 #

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,38 +18,38 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
 driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
 	object irq_tables.o
 end
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./auto.E
-	# depends	"$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc
-	# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/reset16.inc
 	ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -59,7 +59,7 @@
 mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds
 	mainboardinit ./failover.inc
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb	2009-06-30 14:11:42 UTC (rev 4380)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb	2009-06-30 15:17:49 UTC (rev 4381)
@@ -18,82 +18,82 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FA