From kevin at koconnor.net Sun Mar 1 00:41:28 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Sat, 28 Feb 2009 18:41:28 -0500 Subject: [coreboot] MPTable can not be high-memory on Linux In-Reply-To: <49A23EE0.8000102@kernel.org> References: <499DB40C.1060205@coresystems.de> <499DCE79.8020809@coresystems.de> <20090222152530.GA30576@morn.localdomain> <200902221806.55429.rjw@sisk.pl> <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> Message-ID: <20090228234127.GA29964@morn.localdomain> On Sun, Feb 22, 2009 at 10:14:56PM -0800, Yinghai Lu wrote: > please check > > [PATCH] x86: check physptr with max_low_pfn on 32bit Thanks for looking at this issue. Unfortunately, the kernel still does not work with the applied patch. Neither 32bit nor 64bit kernels boot. (Note, I applied the patch to Linus' git, and I had to replace mpf->physptr with mpf->mpf_physptr.) The error messages from before and after patching appear to be the same. In order to aid in testing, I modified SeaBIOS to force the mptable into high memory even in qemu mode. A modified bios.bin file can be found at: http://linuxtogo.org/~kevin/SeaBIOS/bios.bin-high-mptable To use it with qemu, the steps are roughly: mkdir testbios cp /usr/share/qemu/*.bin testbios/ cp bios.bin-high-mptable testbios/bios.bin qemu -L testbios/ -hda mytestlinux.img -serial file:mylog The modified bios.bin can also be built manually by running: git clone git://linuxtogo.org/home/kevin/seabios.git cd seabios patch -p1 < patch-from-below make cp out/bios.bin ../bios.bin-high-mptable -Kevin diff --git a/src/config.h b/src/config.h index 56e5302..1ecc86f 100644 --- a/src/config.h +++ b/src/config.h @@ -21,7 +21,7 @@ #define CONFIG_DEBUG_LEVEL 1 // Send debugging information to serial port -#define CONFIG_DEBUG_SERIAL 0 +#define CONFIG_DEBUG_SERIAL 1 // Support for int13 floppy drive access #define CONFIG_FLOPPY_SUPPORT 1 @@ -77,7 +77,7 @@ // Support finding a UUID (for smbios) via "magic" outl sequence. #define CONFIG_UUID_BACKDOOR 1 // Support generation of ACPI tables (for emulators) -#define CONFIG_ACPI 1 +#define CONFIG_ACPI 0 // Support bios callbacks specific to via vgabios. #define CONFIG_VGAHOOKS 0 // Support S3 resume handler. diff --git a/src/mptable.c b/src/mptable.c index 9e030fe..79cc7ba 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -19,7 +19,7 @@ mptable_init(void) dprintf(3, "init MPTable\n"); int smp_cpus = smp_probe(); - if (smp_cpus <= 1) + if (0 && smp_cpus <= 1) // Building an mptable on uniprocessor machines confuses some OSes. return; @@ -39,7 +39,9 @@ mptable_init(void) /* floating pointer structure */ struct mptable_floating_s *floating = (void*)start; memset(floating, 0, sizeof(*floating)); - struct mptable_config_s *config = (void*)&floating[1]; +// struct mptable_config_s *config = (void*)&floating[1]; + struct mptable_config_s *config = (void*)(RamSize - 64*1024); + add_e820((u32)config, 64*1024, E820_RESERVED); floating->signature = MPTABLE_SIGNATURE; floating->physaddr = (u32)config; floating->length = 1; From joe at settoplinux.org Sun Mar 1 00:59:21 2009 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 28 Feb 2009 18:59:21 -0500 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <49A86EB2.7030405@gmx.net> References: <49A86EB2.7030405@gmx.net> Message-ID: <9f7bd297fb5011335f199b07ecbb279c@imap.1and1.com> On Fri, 27 Feb 2009 23:52:34 +0100, Carl-Daniel Hailfinger wrote: > Hi all, > > GSoC 2009 is approaching and although the number of total slots has been > reduced, there is a chance we might get some slots for coreboot and/or > flashrom. We might want to apply separately for coreboot and flashrom, > maybe also for buildrom or libpayload because they are essentially > separate projects. I don't know if SeaBIOS would benefit from GSoC > because it seems rather complete to me. > > Deadline for organizational applications: March 13, 2009 noon. > No application possible before March 9, 2009 noon. > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_org_apply_4694175091022641 > > Full timeline: > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_timeline_5354032302481437_ > Any ideas for projects? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From peter at stuge.se Sun Mar 1 01:10:04 2009 From: peter at stuge.se (Peter Stuge) Date: Sun, 1 Mar 2009 01:10:04 +0100 Subject: [coreboot] [Etherboot-discuss] Etherboot kernel help.. In-Reply-To: <1235826405.7367.0.camel@DAJ3W> References: <1235826405.7367.0.camel@DAJ3W> Message-ID: <20090301001004.14577.qmail@stuge.se> Joshua McDowell wrote: > > Why not come on into IRC on Freenode and join the #etherboot > > channel for some more lively help? > > What IRC services do you use? I would love to do that! Says right there. irc.freenode.net #etherboot and there is also #coreboot where some of the coreboot folks like to hang out. //Peter From stepan at coresystems.de Sun Mar 1 02:34:52 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 01 Mar 2009 02:34:52 +0100 Subject: [coreboot] [PATCH] port yabel and vm86 to v2. Message-ID: <49A9E63C.7090106@coresystems.de> These patches replace the v2 bios emulator by the version from coreboot v3, including yabel and vm86. Other actions required: svn propset "x86emu svn://coreboot.org/repository/coreboot-v3/util/x86emu" util svn rm src/devices/emulator Best regards, Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- A non-text attachment was scrubbed... Name: yabel-prereq.diff Type: text/x-patch Size: 5248 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: yabel-v2.diff Type: text/x-patch Size: 15654 bytes Desc: not available URL: From joe at settoplinux.org Sun Mar 1 03:38:13 2009 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 28 Feb 2009 21:38:13 -0500 Subject: [coreboot] [PATCH] port yabel and vm86 to v2. In-Reply-To: <49A9E63C.7090106@coresystems.de> References: <49A9E63C.7090106@coresystems.de> Message-ID: <8699662a32b6f434a8a67e3fb184215d@imap.1and1.com> On Sun, 01 Mar 2009 02:34:52 +0100, Stefan Reinauer wrote: > These patches replace the v2 bios emulator by the version from coreboot v3, > including yabel and vm86. > > Other actions required: > > svn propset "x86emu > svn://coreboot.org/repository/coreboot-v3/util/x86emu" util > svn rm src/devices/emulator > I like it! You have my ACK :-) Acked-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From yinghai at kernel.org Sun Mar 1 04:10:18 2009 From: yinghai at kernel.org (Yinghai Lu) Date: Sat, 28 Feb 2009 19:10:18 -0800 Subject: [coreboot] MPTable can not be high-memory on Linux In-Reply-To: <20090228234127.GA29964@morn.localdomain> References: <499DB40C.1060205@coresystems.de> <499DCE79.8020809@coresystems.de> <20090222152530.GA30576@morn.localdomain> <200902221806.55429.rjw@sisk.pl> <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> Message-ID: <49A9FC9A.2030707@kernel.org> Kevin O'Connor wrote: > On Sun, Feb 22, 2009 at 10:14:56PM -0800, Yinghai Lu wrote: >> please check >> >> [PATCH] x86: check physptr with max_low_pfn on 32bit > > Thanks for looking at this issue. > > Unfortunately, the kernel still does not work with the applied patch. > Neither 32bit nor 64bit kernels boot. (Note, I applied the patch to > Linus' git, and I had to replace mpf->physptr with mpf->mpf_physptr.) > > The error messages from before and after patching appear to be the > same. > > please add this patch too [PATCH] x86: ioremap mptable Impact: fix boot with mptable above max_low_mapped try to use early_ioremap it. Signed-off-by: Yinghai Lu --- arch/x86/kernel/mpparse.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) Index: linux-2.6/arch/x86/kernel/mpparse.c =================================================================== --- linux-2.6.orig/arch/x86/kernel/mpparse.c +++ linux-2.6/arch/x86/kernel/mpparse.c @@ -611,12 +611,20 @@ static void __init __get_smp_config(unsi construct_default_ISA_mptable(mpf->feature1); } else if (mpf->physptr) { + struct mpc_table *mpc; + unsigned int length; + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); + length = mpc->length; + apic_printk(APIC_VERBOSE, " mpc: %x-%x\n", mpf->physptr, + mpf->physptr + length); + early_iounmap(mpc, PAGE_SIZE); + mpc = early_ioremap(mpf->physptr, length); /* * Read the physical hardware table. Anything here will * override the defaults. */ - if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { + if (!smp_read_mpc(mpc, early)) { #ifdef CONFIG_X86_LOCAL_APIC smp_found_config = 0; #endif @@ -624,9 +632,12 @@ static void __init __get_smp_config(unsi "BIOS bug, MP table errors detected!...\n"); printk(KERN_ERR "... disabling SMP support. " "(tell your hw vendor)\n"); + early_iounmap(mpc, length); return; } + early_iounmap(mpc, length); + if (early) return; #ifdef CONFIG_X86_IO_APIC From stepan at coresystems.de Sun Mar 1 11:04:07 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 01 Mar 2009 11:04:07 +0100 Subject: [coreboot] [PATCH] v2: drop path type union name In-Reply-To: <49A99574.2030202@gmx.net> References: <49A97CD5.3020604@coresystems.de> <49A99574.2030202@gmx.net> Message-ID: <49AA5D97.6060607@coresystems.de> On 28.02.2009 20:50 Uhr, Carl-Daniel Hailfinger wrote: > On 28.02.2009 19:05, Stefan Reinauer wrote: > >> coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3 >> a long time ago. This will make it easier to port v2 boards forward to v3 at >> some point (and other things) >> >> Signed-off-by: Stefan Reinauer >> > > Thanks for doing this! > > If it survives abuild, it is > Acked-by: Carl-Daniel Hailfinger > Thanks, r3964 Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From svn at coreboot.org Sun Mar 1 11:08:06 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Sun, 1 Mar 2009 11:08:06 +0100 Subject: [coreboot] r1141 - in coreboot-v3/util/x86emu: . pcbios x86emu yabel yabel/compat Message-ID: Author: stepan Date: 2009-03-01 11:08:06 +0100 (Sun, 01 Mar 2009) New Revision: 1141 Added: coreboot-v3/util/x86emu/Config.lb coreboot-v3/util/x86emu/pcbios/Config.lb coreboot-v3/util/x86emu/x86emu/Config.lb coreboot-v3/util/x86emu/yabel/Config.lb coreboot-v3/util/x86emu/yabel/compat/Config.lb Modified: coreboot-v3/util/x86emu/biosemu.c coreboot-v3/util/x86emu/pcbios/pcibios.c coreboot-v3/util/x86emu/vm86.c coreboot-v3/util/x86emu/vm86_gdt.c coreboot-v3/util/x86emu/x86emu/sys.c coreboot-v3/util/x86emu/yabel/biosemu.c coreboot-v3/util/x86emu/yabel/compat/functions.c coreboot-v3/util/x86emu/yabel/debug.c coreboot-v3/util/x86emu/yabel/debug.h coreboot-v3/util/x86emu/yabel/device.c coreboot-v3/util/x86emu/yabel/device.h coreboot-v3/util/x86emu/yabel/interrupt.c coreboot-v3/util/x86emu/yabel/io.c coreboot-v3/util/x86emu/yabel/mem.c coreboot-v3/util/x86emu/yabel/pmm.c coreboot-v3/util/x86emu/yabel/vbe.c Log: This patch contains the necessary changes to util/x86emu of the v3 tree to use it in the v2 tree as well. Requires the yabel-prereq.diff patch in order to work in v2. Signed-off-by: Stefan Reinauer Acked-by: Joseph Smith Added: coreboot-v3/util/x86emu/Config.lb =================================================================== --- coreboot-v3/util/x86emu/Config.lb (rev 0) +++ coreboot-v3/util/x86emu/Config.lb 2009-03-01 10:08:06 UTC (rev 1141) @@ -0,0 +1,17 @@ +uses CONFIG_PCI_OPTION_ROM_RUN_YABEL +uses CONFIG_PCI_OPTION_ROM_RUN_VM86 + +if CONFIG_PCI_OPTION_ROM_RUN_YABEL + dir yabel + dir x86emu +else + if CONFIG_PCI_OPTION_ROM_RUN_VM86 + object vm86.o + object vm86_gdt.o + else + object biosemu.o + dir pcbios + dir x86emu + end +end + Modified: coreboot-v3/util/x86emu/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/biosemu.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/biosemu.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -20,6 +20,7 @@ * This file is part of the coreboot project. * * (c) Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL + * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,8 +36,13 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if COREBOOT_V2 +#include +#include +#else #include #include +#endif #include #include #include @@ -96,9 +102,10 @@ u8 val; val = inb(port); - +#ifdef DEBUG if (port != 0x40) printk("inb(0x%04x) = 0x%02x\n", port, val); +#endif return val; } @@ -109,7 +116,9 @@ val = inw(port); +#ifdef DEBUG printk("inw(0x%04x) = 0x%04x\n", port, val); +#endif return val; } @@ -119,26 +128,34 @@ val = inl(port); +#ifdef DEBUG printk("inl(0x%04x) = 0x%08x\n", port, val); +#endif return val; } void x_outb(u16 port, u8 val) { +#ifdef DEBUG if (port != 0x43) printk("outb(0x%02x, 0x%04x)\n", val, port); +#endif outb(val, port); } void x_outw(u16 port, u16 val) { +#ifdef DEBUG printk("outw(0x%04x, 0x%04x)\n", val, port); +#endif outw(val, port); } void x_outl(u16 port, u32 val) { +#ifdef DEBUG printk("outl(0x%08x, 0x%04x)\n", val, port); +#endif outl(val, port); } @@ -324,6 +341,7 @@ unsigned short initialcs = (addr & 0xF0000) >> 4; unsigned short initialip = (addr + 3) & 0xFFFF; unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn; + X86EMU_intrFuncs intFuncs[256]; X86EMU_setMemBase(0, 0x100000); Added: coreboot-v3/util/x86emu/pcbios/Config.lb =================================================================== --- coreboot-v3/util/x86emu/pcbios/Config.lb (rev 0) +++ coreboot-v3/util/x86emu/pcbios/Config.lb 2009-03-01 10:08:06 UTC (rev 1141) @@ -0,0 +1 @@ +object pcibios.o \ No newline at end of file Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c =================================================================== --- coreboot-v3/util/x86emu/pcbios/pcibios.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/pcbios/pcibios.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -35,7 +35,11 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if COREBOOT_V2 +#include +#else #include +#endif #include #include #include @@ -61,7 +65,11 @@ break; case FIND_PCI_DEVICE: /* FixME: support SI != 0 */ +#if COREBOOT_V2 + dev = dev_find_device(X86_DX, X86_CX, dev); +#else dev = dev_find_pci_device(X86_DX, X86_CX, dev); +#endif if (dev != 0) { X86_BH = dev->bus->secondary; X86_BL = dev->path.pci.devfn; Modified: coreboot-v3/util/x86emu/vm86.c =================================================================== --- coreboot-v3/util/x86emu/vm86.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/vm86.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -4,7 +4,7 @@ * Copyright (C) 2000 Scyld Computing Corporation * Copyright (C) 2001 University of California. LA-CC Number 01-67. * Copyright (C) 2005 Nick.Barker9 at btinternet.com - * Copyright (C) 2007 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,9 +25,15 @@ #include #include #include +#include +#if COREBOOT_V2 +#include +#include +#define printk(lvl, x...) printk_debug(x) +#else #include -#include #include +#endif /* The address arguments to this function are PHYSICAL ADDRESSES */ static void real_mode_switch_call_vga(unsigned long devfn) @@ -539,7 +545,6 @@ *(unsigned char *) i = 0; } setup_realmode_idt(); - real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn); } @@ -586,7 +591,11 @@ vendorid = *pedx; devindex = *pesi; dev = 0; +#if COREBOOT_V2 + while ((dev = dev_find_device(vendorid, devid, dev))) { +#else while ((dev = dev_find_pci_device(vendorid, devid, dev))) { +#endif if (devindex <= 0) break; devindex--; Modified: coreboot-v3/util/x86emu/vm86_gdt.c =================================================================== --- coreboot-v3/util/x86emu/vm86_gdt.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/vm86_gdt.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -33,7 +33,11 @@ " .globl gdtarg\n" "gdtarg: \n" " .word gdt_limit \n" +#if COREBOOT_V2 + " .long gdt \n" +#else " .long gdtptr \n" +#endif /* compute the table limit */ "__mygdt_limit = __mygdt_end - __mygdt - 1 \n" @@ -74,6 +78,7 @@ "__mygdt_end: \n" +#if !COREBOOT_V2 /* FIXME: This does probably not belong here */ " .globl idtarg\n" "idtarg:\n" @@ -83,6 +88,7 @@ "_idt:\n" " .fill 20, 8, 0\n" // # idt is unitiailzed "_idt_end:\n" +#endif /* Declare a pointer to where our idt is going to be i.e. at mem zero */ " .globl __myidt\n" Added: coreboot-v3/util/x86emu/x86emu/Config.lb =================================================================== --- coreboot-v3/util/x86emu/x86emu/Config.lb (rev 0) +++ coreboot-v3/util/x86emu/x86emu/Config.lb 2009-03-01 10:08:06 UTC (rev 1141) @@ -0,0 +1,7 @@ +object debug.o +object decode.o +object fpu.o +object ops.o +object ops2.o +object prim_ops.o +object sys.o Modified: coreboot-v3/util/x86emu/x86emu/sys.c =================================================================== --- coreboot-v3/util/x86emu/x86emu/sys.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/x86emu/sys.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -46,7 +46,11 @@ #include "debug.h" #include "prim_ops.h" #if 1 /* Coreboot needs to map prinkf to printk. */ +#if COREBOOT_V2 +#include "arch/io.h" +#else #include "io.h" +#endif #else #include #endif Added: coreboot-v3/util/x86emu/yabel/Config.lb =================================================================== --- coreboot-v3/util/x86emu/yabel/Config.lb (rev 0) +++ coreboot-v3/util/x86emu/yabel/Config.lb 2009-03-01 10:08:06 UTC (rev 1141) @@ -0,0 +1,9 @@ +object biosemu.o +object debug.o +object device.o +object interrupt.o +object io.o +object mem.o +object pmm.o +object vbe.o +dir compat Modified: coreboot-v3/util/x86emu/yabel/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/yabel/biosemu.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/biosemu.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -13,13 +13,19 @@ #include #include +#if !COREBOOT_V2 #include +#endif #include "debug.h" #include #include +#if COREBOOT_V2 +#include "../x86emu/prim_ops.h" +#else #include // for push_word +#endif #include "biosemu.h" #include "io.h" @@ -28,7 +34,11 @@ #include "device.h" #include "pmm.h" +#if COREBOOT_V2 +#include "compat/rtas.h" +#else #include +#endif #include Added: coreboot-v3/util/x86emu/yabel/compat/Config.lb =================================================================== --- coreboot-v3/util/x86emu/yabel/compat/Config.lb (rev 0) +++ coreboot-v3/util/x86emu/yabel/compat/Config.lb 2009-03-01 10:08:06 UTC (rev 1141) @@ -0,0 +1 @@ +object functions.o Modified: coreboot-v3/util/x86emu/yabel/compat/functions.c =================================================================== --- coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -14,8 +14,10 @@ */ #include +#if !COREBOOT_V2 +#include +#endif #include -#include #define VMEM_SIZE 1024 *1024 /* 1 MB */ Modified: coreboot-v3/util/x86emu/yabel/debug.c =================================================================== --- coreboot-v3/util/x86emu/yabel/debug.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/debug.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -10,7 +10,9 @@ * IBM Corporation - initial implementation *****************************************************************************/ +#if !COREBOOT_V2 #include +#endif #include "debug.h" Modified: coreboot-v3/util/x86emu/yabel/debug.h =================================================================== --- coreboot-v3/util/x86emu/yabel/debug.h 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/debug.h 2009-03-01 10:08:06 UTC (rev 1141) @@ -19,7 +19,11 @@ extern void x86emu_dump_xregs(void); /* printf is not available in coreboot... use printk */ +#if COREBOOT_V2 +#include +#else #include +#endif /* uurgs... yuck... x86emu/x86emu.h is redefining printk... we include it here * and use its redefinition of printk * TODO: FIX!!!! */ Modified: coreboot-v3/util/x86emu/yabel/device.c =================================================================== --- coreboot-v3/util/x86emu/yabel/device.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/device.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -12,13 +12,17 @@ #include "device.h" +#if COREBOOT_V2 +#include "compat/rtas.h" +#else #include "rtas.h" +#endif #include #include "debug.h" #include +#include #include -#include #include /* the device we are working with... */ @@ -47,6 +51,10 @@ struct resource *r; u8 bus = bios_device.dev->bus->link; u16 devfn = bios_device.dev->path.pci.devfn; + + bios_device.bus = bus; + bios_device.devfn = devfn; + DEBUG_PRINTF("bus: %x, devfn: %x\n", bus, devfn); for (i = 0; i < bios_device.dev->resources; i++) { r = &bios_device.dev->resource[i]; @@ -388,7 +396,11 @@ { u8 rval = 0; //init bios_device struct +#if COREBOOT_V2 + DEBUG_PRINTF("%s\n", __func__); +#else DEBUG_PRINTF("%s(%s)\n", __func__, device->dtsname); +#endif memset(&bios_device, 0, sizeof(bios_device)); #ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL Modified: coreboot-v3/util/x86emu/yabel/device.h =================================================================== --- coreboot-v3/util/x86emu/yabel/device.h 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/device.h 2009-03-01 10:08:06 UTC (rev 1141) @@ -14,11 +14,16 @@ #define DEVICE_LIB_H #include +#if COREBOOT_V2 +#include +#include "compat/of.h" +#else #include +#include #include "of.h" +#endif #include "debug.h" -#include // a Expansion Header Struct as defined in Plug and Play BIOS Spec 1.0a Chapter 3.2 typedef struct { Modified: coreboot-v3/util/x86emu/yabel/interrupt.c =================================================================== --- coreboot-v3/util/x86emu/yabel/interrupt.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/interrupt.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -10,7 +10,11 @@ * IBM Corporation - initial implementation *****************************************************************************/ +#if COREBOOT_V2 +#include "compat/rtas.h" +#else #include +#endif #include "biosemu.h" #include "mem.h" @@ -19,9 +23,14 @@ #include "pmm.h" #include +#if COREBOOT_V2 +#include "../x86emu/prim_ops.h" +#else #include +#endif #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include #include #endif Modified: coreboot-v3/util/x86emu/yabel/io.c =================================================================== --- coreboot-v3/util/x86emu/yabel/io.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/io.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -10,16 +10,21 @@ * IBM Corporation - initial implementation *****************************************************************************/ +#include +#if COREBOOT_V2 +#include "compat/rtas.h" +#include "compat/time.h" +#else #include +#include "rtas.h" +#include +#endif #include "device.h" -#include "rtas.h" #include "debug.h" -#include "device.h" -#include #include -#include #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include #include #endif @@ -359,10 +364,15 @@ || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... printf - ("Config access invalid! bus: %x, devfn: %x, offs: %x\n", - bus, devfn, offs); + ("Config read access invalid! PCI device %x:%x.%x, offs: %x\n", + bus, devfn >> 3, devfn & 7, offs); +#ifdef CONFIG_YABEL_NO_ILLEGAL_ACCESS HALT_SYS(); } else { +#else + } + { +#endif #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL switch (size) { case 1: @@ -410,8 +420,8 @@ || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... printf - ("Config access invalid! bus: %x, devfn: %x, offs: %x\n", - bus, devfn, offs); + ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", + bus, devfn >> 3, devfn & 7, offs); HALT_SYS(); } else { #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL Modified: coreboot-v3/util/x86emu/yabel/mem.c =================================================================== --- coreboot-v3/util/x86emu/yabel/mem.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/mem.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -11,12 +11,18 @@ *****************************************************************************/ #include +#if !COREBOOT_V2 #include +#endif #include "debug.h" #include "device.h" #include "x86emu/x86emu.h" #include "biosemu.h" +#if COREBOOT_V2 +#include "compat/time.h" +#else #include +#endif // define a check for access to certain (virtual) memory regions (interrupt handlers, BIOS Data Area, ...) #ifdef DEBUG Modified: coreboot-v3/util/x86emu/yabel/pmm.c =================================================================== --- coreboot-v3/util/x86emu/yabel/pmm.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/pmm.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -10,7 +10,11 @@ ****************************************************************************/ #include +#if COREBOOT_V2 +#include "../x86emu/prim_ops.h" +#else #include +#endif #include #include "biosemu.h" Modified: coreboot-v3/util/x86emu/yabel/vbe.c =================================================================== --- coreboot-v3/util/x86emu/yabel/vbe.c 2009-02-25 17:50:38 UTC (rev 1140) +++ coreboot-v3/util/x86emu/yabel/vbe.c 2009-03-01 10:08:06 UTC (rev 1141) @@ -11,15 +11,20 @@ *****************************************************************************/ #include - #include +#if !COREBOOT_V2 #include +#endif #include "debug.h" #include #include +#if COREBOOT_V2 +#include "../x86emu/prim_ops.h" +#else #include // for push_word +#endif #include "biosemu.h" #include "io.h" From svn at coreboot.org Sun Mar 1 11:16:01 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Sun, 1 Mar 2009 11:16:01 +0100 Subject: [coreboot] r3965 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/include/arch src/config src/devices src/include src/include/cpu/x86 util Message-ID: Author: stepan Date: 2009-03-01 11:16:01 +0100 (Sun, 01 Mar 2009) New Revision: 3965 Added: trunk/coreboot-v2/src/include/types.h Removed: trunk/coreboot-v2/src/devices/emulator/ Modified: trunk/coreboot-v2/src/arch/i386/boot/multiboot.c trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h trunk/coreboot-v2/src/arch/i386/include/stdint.h trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/devices/Config.lb trunk/coreboot-v2/src/include/cpu/x86/smm.h trunk/coreboot-v2/src/include/string.h trunk/coreboot-v2/util/ Log: Some changes required to get yabel working on v2 (and they generally make sense, too). Have one u64 instead of three. In order to use the old bios emulator, you have to do nothing. (Default, if CONFIG_PCI_ROM_RUN is enabled) In order to use yabel in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_YABEL default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 In order to use vm86 in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_VM86 default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 Note: vm86 only works on platforms with _RAMBASE in the lower megabyte. Signed-off-by: Stefan Reinauer Acked-by: Joseph Smith Modified: trunk/coreboot-v2/src/arch/i386/boot/multiboot.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-02-28 20:10:20 UTC (rev 3964) +++ trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-03-01 10:16:01 UTC (rev 3965) @@ -23,8 +23,6 @@ #include #include -typedef unsigned long long u64; - static struct multiboot_mmap_entry *mb_mem; struct multiboot_info *mbi; Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-02-28 20:10:20 UTC (rev 3964) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-03-01 10:16:01 UTC (rev 3965) @@ -18,7 +18,6 @@ #if HAVE_ACPI_TABLES==1 #include -typedef unsigned long long u64; #define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ #define RSDP_NAME "RSDP" Modified: trunk/coreboot-v2/src/arch/i386/include/stdint.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/stdint.h 2009-02-28 20:10:20 UTC (rev 3964) +++ trunk/coreboot-v2/src/arch/i386/include/stdint.h 2009-03-01 10:16:01 UTC (rev 3965) @@ -65,11 +65,13 @@ typedef unsigned long int uintmax_t; #endif -#undef __HAVE_LONG_LONG__ - typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; +#if __HAVE_LONG_LONG__ +typedef uint64_t u64; +#endif +#undef __HAVE_LONG_LONG__ #endif /* I386_STDINT_H */ Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-02-28 20:10:20 UTC (rev 3964) +++ trunk/coreboot-v2/src/config/Options.lb 2009-03-01 10:16:01 UTC (rev 3965) @@ -168,6 +168,12 @@ comment "Use stage 1 initialization code" end +define COREBOOT_V2 + default 1 + export always + comment "This is used by code to determine v2 vs v3" +end + ############################################### # ROM image options ############################################### @@ -1068,6 +1074,18 @@ comment "Init x86 ROMs on all PCI devices" end +define CONFIG_PCI_OPTION_ROM_RUN_YABEL + default 0 + export used + comment "Use Yabel instead of old bios emulator" +end + +define CONFIG_PCI_OPTION_ROM_RUN_VM86 + default 0 + export used + comment "Use Yabel instead of old bios emulator" +end + define CONFIG_PCI_64BIT_PREF_MEM default 0 export always Modified: trunk/coreboot-v2/src/devices/Config.lb =================================================================== --- trunk/coreboot-v2/src/devices/Config.lb 2009-02-28 20:10:20 UTC (rev 3964) +++ trunk/coreboot-v2/src/devices/Config.lb 2009-03-01 10:16:01 UTC (rev 3965) @@ -1,5 +1,6 @@ uses CONFIG_PCI_ROM_RUN uses CONFIG_VGA_ROM_RUN + object device.o object root_device.o object device_util.o @@ -15,10 +16,10 @@ if CONFIG_PCI_ROM_RUN object pci_rom.o - dir emulator + dir ../../util/x86emu else if CONFIG_VGA_ROM_RUN object pci_rom.o - dir emulator + dir ../../util/x86emu end end Modified: trunk/coreboot-v2/src/include/cpu/x86/smm.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/x86/smm.h 2009-02-28 20:10:20 UTC (rev 3964) +++ trunk/coreboot-v2/src/include/cpu/x86/smm.h 2009-03-01 10:16:01 UTC (rev 3965) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 coresystems GmbH + * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,8 +18,6 @@ */ -typedef uint64_t u64; - /* AMD64 SMM State-Save Area * starts @ 0x7e00 */ Modified: trunk/coreboot-v2/src/include/string.h =================================================================== --- trunk/coreboot-v2/src/include/string.h 2009-02-28 20:10:20 UTC (rev 3964) +++ trunk/coreboot-v2/src/include/string.h 2009-03-01 10:16:01 UTC (rev 3965) @@ -81,6 +81,18 @@ return r; } +static inline int strncmp(const char *s1, const char *s2, int maxlen) +{ + int i; + + for (i = 0; i < maxlen; i++) { + if (s1[i] != s2[i]) + return s1[i] - s2[i]; + } + + return 0; +} + static inline int isspace(int c) { switch (c) { Added: trunk/coreboot-v2/src/include/types.h =================================================================== --- trunk/coreboot-v2/src/include/types.h (rev 0) +++ trunk/coreboot-v2/src/include/types.h 2009-03-01 10:16:01 UTC (rev 3965) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __TYPES_H +#define __TYPES_H +#include +#include +#endif + Property changes on: trunk/coreboot-v2/util ___________________________________________________________________ Modified: svn:externals - flashrom svn://coreboot.org/repos/trunk/util/flashrom nvramtool svn://coreboot.org/repos/trunk/util/nvramtool superiotool svn://coreboot.org/repos/trunk/util/superiotool getpir svn://coreboot.org/repos/trunk/util/getpir mptable svn://coreboot.org/repos/trunk/util/mptable inteltool svn://coreboot.org/repos/trunk/util/inteltool + x86emu svn://coreboot.org/repository/coreboot-v3/util/x86emu From svn at coreboot.org Sun Mar 1 11:19:51 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Sun, 1 Mar 2009 11:19:51 +0100 Subject: [coreboot] r3966 - trunk/coreboot-v2/util Message-ID: Author: stepan Date: 2009-03-01 11:19:50 +0100 (Sun, 01 Mar 2009) New Revision: 3966 Modified: trunk/coreboot-v2/util/ Log: oops, got to be careful with svn:externals: Adding back all the other externals. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Property changes on: trunk/coreboot-v2/util ___________________________________________________________________ Modified: svn:externals - x86emu svn://coreboot.org/repository/coreboot-v3/util/x86emu + flashrom svn://coreboot.org/repos/trunk/util/flashrom nvramtool svn://coreboot.org/repos/trunk/util/nvramtool superiotool svn://coreboot.org/repos/trunk/util/superiotool getpir svn://coreboot.org/repos/trunk/util/getpir mptable svn://coreboot.org/repos/trunk/util/mptable inteltool svn://coreboot.org/repos/trunk/util/inteltool x86emu svn://coreboot.org/repository/coreboot-v3/util/x86emu From stepan at coresystems.de Sun Mar 1 11:22:10 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 01 Mar 2009 11:22:10 +0100 Subject: [coreboot] [PATCH] port yabel and vm86 to v2. In-Reply-To: <8699662a32b6f434a8a67e3fb184215d@imap.1and1.com> References: <49A9E63C.7090106@coresystems.de> <8699662a32b6f434a8a67e3fb184215d@imap.1and1.com> Message-ID: <49AA61D2.4020108@coresystems.de> On 01.03.2009 3:38 Uhr, Joseph Smith wrote: > > On Sun, 01 Mar 2009 02:34:52 +0100, Stefan Reinauer > wrote: > >> These patches replace the v2 bios emulator by the version from coreboot >> > v3, > >> including yabel and vm86. >> >> Other actions required: >> >> svn propset "x86emu >> svn://coreboot.org/repository/coreboot-v3/util/x86emu" util >> svn rm src/devices/emulator >> >> > I like it! > You have my ACK :-) > > Acked-by: Joseph Smith > Thanks, r1141 in v3, and r3965 and r3966 in v2. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From ronald at zonnet.nl Sun Mar 1 12:38:19 2009 From: ronald at zonnet.nl (Ronald Hoogenboom) Date: Sun, 01 Mar 2009 12:38:19 +0100 Subject: [coreboot] [v3] rev 1141 COREBOOT_V2 is not defined In-Reply-To: References: Message-ID: <1235907499.3398.3.camel@amd-x2.grundel> Hi, Trivial patch to make v3 compile too. Signed off by: Ronald Hoogenboom -------------- next part -------------- A non-text attachment was scrubbed... Name: vm86.diff Type: text/x-patch Size: 640 bytes Desc: not available URL: From ronald at zonnet.nl Sun Mar 1 12:41:43 2009 From: ronald at zonnet.nl (Ronald Hoogenboom) Date: Sun, 01 Mar 2009 12:41:43 +0100 Subject: [coreboot] [v3] rev 1141 COREBOOT_V2 is not defined In-Reply-To: <1235907499.3398.3.camel@amd-x2.grundel> References: <1235907499.3398.3.camel@amd-x2.grundel> Message-ID: <1235907703.3398.4.camel@amd-x2.grundel> Sorry, in another file too... On Sun, 2009-03-01 at 12:38 +0100, Ronald Hoogenboom wrote: > Hi, > > Trivial patch to make v3 compile too. > > Signed off by: Ronald Hoogenboom > > -------------- next part -------------- A non-text attachment was scrubbed... Name: vm86.diff Type: text/x-patch Size: 1175 bytes Desc: not available URL: From kevin at koconnor.net Sun Mar 1 19:04:20 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Sun, 1 Mar 2009 13:04:20 -0500 Subject: [coreboot] MPTable can not be high-memory on Linux In-Reply-To: <49A9FC9A.2030707@kernel.org> References: <499DB40C.1060205@coresystems.de> <499DCE79.8020809@coresystems.de> <20090222152530.GA30576@morn.localdomain> <200902221806.55429.rjw@sisk.pl> <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> Message-ID: <20090301180420.GA27040@morn.localdomain> On Sat, Feb 28, 2009 at 07:10:18PM -0800, Yinghai Lu wrote: > Kevin O'Connor wrote: > > On Sun, Feb 22, 2009 at 10:14:56PM -0800, Yinghai Lu wrote: > >> please check > >> > >> [PATCH] x86: check physptr with max_low_pfn on 32bit > > > > Thanks for looking at this issue. > > > > Unfortunately, the kernel still does not work with the applied patch. > > Neither 32bit nor 64bit kernels boot. (Note, I applied the patch to > > Linus' git, and I had to replace mpf->physptr with mpf->mpf_physptr.) > > please add this patch too > > [PATCH] x86: ioremap mptable Thanks. Both 32bit and 64bit kernels are working now. -Kevin From svn at coreboot.org Sun Mar 1 19:05:25 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Sun, 1 Mar 2009 19:05:25 +0100 Subject: [coreboot] r3967 - trunk/coreboot-v2/src/northbridge/amd/amdk8 Message-ID: Author: ruik Date: 2009-03-01 19:05:25 +0100 (Sun, 01 Mar 2009) New Revision: 3967 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c Log: (Trivial) Add missing header file. Signed-off-by: Rudolf Marek Acked-by: Rudolf Marek Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-03-01 10:19:50 UTC (rev 3966) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-03-01 18:05:25 UTC (rev 3967) @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include From c-d.hailfinger.devel.2006 at gmx.net Sun Mar 1 19:44:55 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sun, 01 Mar 2009 19:44:55 +0100 Subject: [coreboot] [PATCH] Fix printk format warning Message-ID: <49AAD7A7.8040308@gmx.net> Fix printk format warning in amdk8_acpi.c. Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c (Revision 3967) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c (Arbeitskopie) @@ -128,7 +128,7 @@ basek = resk(res->base); sizek = resk(res->size); - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", + printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", dev_path(dev), res->index, basek, sizek); /* * 0-640K must be on node 0 -- http://www.hailfinger.org/ From svn at coreboot.org Sun Mar 1 20:23:02 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Sun, 1 Mar 2009 20:23:02 +0100 Subject: [coreboot] r1142 - in coreboot-v3/util/x86emu: . pcbios x86emu yabel yabel/compat Message-ID: Author: stepan Date: 2009-03-01 20:23:02 +0100 (Sun, 01 Mar 2009) New Revision: 1142 Modified: coreboot-v3/util/x86emu/biosemu.c coreboot-v3/util/x86emu/pcbios/pcibios.c coreboot-v3/util/x86emu/vm86.c coreboot-v3/util/x86emu/vm86_gdt.c coreboot-v3/util/x86emu/x86emu/sys.c coreboot-v3/util/x86emu/yabel/biosemu.c coreboot-v3/util/x86emu/yabel/compat/functions.c coreboot-v3/util/x86emu/yabel/debug.c coreboot-v3/util/x86emu/yabel/debug.h coreboot-v3/util/x86emu/yabel/device.c coreboot-v3/util/x86emu/yabel/device.h coreboot-v3/util/x86emu/yabel/interrupt.c coreboot-v3/util/x86emu/yabel/io.c coreboot-v3/util/x86emu/yabel/mem.c coreboot-v3/util/x86emu/yabel/pmm.c coreboot-v3/util/x86emu/yabel/vbe.c Log: Trivial patch to make v3 compile too. Signed-off-by: Ronald Hoogenboom Acked-by: Stefan Reinauer Modified: coreboot-v3/util/x86emu/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/biosemu.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/biosemu.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -36,7 +36,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include #include #else Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c =================================================================== --- coreboot-v3/util/x86emu/pcbios/pcibios.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/pcbios/pcibios.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -35,7 +35,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include #else #include @@ -65,7 +65,7 @@ break; case FIND_PCI_DEVICE: /* FixME: support SI != 0 */ -#if COREBOOT_V2 +#ifdef COREBOOT_V2 dev = dev_find_device(X86_DX, X86_CX, dev); #else dev = dev_find_pci_device(X86_DX, X86_CX, dev); Modified: coreboot-v3/util/x86emu/vm86.c =================================================================== --- coreboot-v3/util/x86emu/vm86.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/vm86.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -26,7 +26,7 @@ #include #include #include -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include #include #define printk(lvl, x...) printk_debug(x) @@ -591,7 +591,7 @@ vendorid = *pedx; devindex = *pesi; dev = 0; -#if COREBOOT_V2 +#ifdef COREBOOT_V2 while ((dev = dev_find_device(vendorid, devid, dev))) { #else while ((dev = dev_find_pci_device(vendorid, devid, dev))) { Modified: coreboot-v3/util/x86emu/vm86_gdt.c =================================================================== --- coreboot-v3/util/x86emu/vm86_gdt.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/vm86_gdt.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -33,7 +33,7 @@ " .globl gdtarg\n" "gdtarg: \n" " .word gdt_limit \n" -#if COREBOOT_V2 +#ifdef COREBOOT_V2 " .long gdt \n" #else " .long gdtptr \n" @@ -78,7 +78,7 @@ "__mygdt_end: \n" -#if !COREBOOT_V2 +#ifndef COREBOOT_V2 /* FIXME: This does probably not belong here */ " .globl idtarg\n" "idtarg:\n" Modified: coreboot-v3/util/x86emu/x86emu/sys.c =================================================================== --- coreboot-v3/util/x86emu/x86emu/sys.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/x86emu/sys.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -46,7 +46,7 @@ #include "debug.h" #include "prim_ops.h" #if 1 /* Coreboot needs to map prinkf to printk. */ -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "arch/io.h" #else #include "io.h" Modified: coreboot-v3/util/x86emu/yabel/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/yabel/biosemu.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/biosemu.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -13,7 +13,7 @@ #include #include -#if !COREBOOT_V2 +#ifndef COREBOOT_V2 #include #endif @@ -21,7 +21,7 @@ #include #include -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include // for push_word @@ -34,7 +34,7 @@ #include "device.h" #include "pmm.h" -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "compat/rtas.h" #else #include Modified: coreboot-v3/util/x86emu/yabel/compat/functions.c =================================================================== --- coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/compat/functions.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -14,7 +14,7 @@ */ #include -#if !COREBOOT_V2 +#ifndef COREBOOT_V2 #include #endif #include Modified: coreboot-v3/util/x86emu/yabel/debug.c =================================================================== --- coreboot-v3/util/x86emu/yabel/debug.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/debug.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -10,7 +10,7 @@ * IBM Corporation - initial implementation *****************************************************************************/ -#if !COREBOOT_V2 +#ifndef COREBOOT_V2 #include #endif Modified: coreboot-v3/util/x86emu/yabel/debug.h =================================================================== --- coreboot-v3/util/x86emu/yabel/debug.h 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/debug.h 2009-03-01 19:23:02 UTC (rev 1142) @@ -19,7 +19,7 @@ extern void x86emu_dump_xregs(void); /* printf is not available in coreboot... use printk */ -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include #else #include Modified: coreboot-v3/util/x86emu/yabel/device.c =================================================================== --- coreboot-v3/util/x86emu/yabel/device.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/device.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -12,7 +12,7 @@ #include "device.h" -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "compat/rtas.h" #else #include "rtas.h" @@ -396,7 +396,7 @@ { u8 rval = 0; //init bios_device struct -#if COREBOOT_V2 +#ifdef COREBOOT_V2 DEBUG_PRINTF("%s\n", __func__); #else DEBUG_PRINTF("%s(%s)\n", __func__, device->dtsname); Modified: coreboot-v3/util/x86emu/yabel/device.h =================================================================== --- coreboot-v3/util/x86emu/yabel/device.h 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/device.h 2009-03-01 19:23:02 UTC (rev 1142) @@ -14,7 +14,7 @@ #define DEVICE_LIB_H #include -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include #include "compat/of.h" #else Modified: coreboot-v3/util/x86emu/yabel/interrupt.c =================================================================== --- coreboot-v3/util/x86emu/yabel/interrupt.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/interrupt.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -10,7 +10,7 @@ * IBM Corporation - initial implementation *****************************************************************************/ -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "compat/rtas.h" #else #include @@ -23,7 +23,7 @@ #include "pmm.h" #include -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include Modified: coreboot-v3/util/x86emu/yabel/io.c =================================================================== --- coreboot-v3/util/x86emu/yabel/io.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/io.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -11,7 +11,7 @@ *****************************************************************************/ #include -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "compat/rtas.h" #include "compat/time.h" #else Modified: coreboot-v3/util/x86emu/yabel/mem.c =================================================================== --- coreboot-v3/util/x86emu/yabel/mem.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/mem.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -11,14 +11,14 @@ *****************************************************************************/ #include -#if !COREBOOT_V2 +#ifndef COREBOOT_V2 #include #endif #include "debug.h" #include "device.h" #include "x86emu/x86emu.h" #include "biosemu.h" -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "compat/time.h" #else #include Modified: coreboot-v3/util/x86emu/yabel/pmm.c =================================================================== --- coreboot-v3/util/x86emu/yabel/pmm.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/pmm.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -10,7 +10,7 @@ ****************************************************************************/ #include -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include Modified: coreboot-v3/util/x86emu/yabel/vbe.c =================================================================== --- coreboot-v3/util/x86emu/yabel/vbe.c 2009-03-01 10:08:06 UTC (rev 1141) +++ coreboot-v3/util/x86emu/yabel/vbe.c 2009-03-01 19:23:02 UTC (rev 1142) @@ -12,7 +12,7 @@ #include #include -#if !COREBOOT_V2 +#ifndef COREBOOT_V2 #include #endif @@ -20,7 +20,7 @@ #include #include -#if COREBOOT_V2 +#ifdef COREBOOT_V2 #include "../x86emu/prim_ops.h" #else #include // for push_word From stepan at coresystems.de Sun Mar 1 20:23:46 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 01 Mar 2009 20:23:46 +0100 Subject: [coreboot] [v3] rev 1141 COREBOOT_V2 is not defined In-Reply-To: <1235907703.3398.4.camel@amd-x2.grundel> References: <1235907499.3398.3.camel@amd-x2.grundel> <1235907703.3398.4.camel@amd-x2.grundel> Message-ID: <49AAE0C2.1090301@coresystems.de> On 01.03.2009 12:41 Uhr, Ronald Hoogenboom wrote: > Sorry, in another file too... > > On Sun, 2009-03-01 at 12:38 +0100, Ronald Hoogenboom wrote: > >> Hi, >> >> Trivial patch to make v3 compile too. >> >> Signed off by: Ronald Hoogenboom >> >> Thanks! r1142 -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From stepan at coresystems.de Sun Mar 1 20:24:33 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Sun, 01 Mar 2009 20:24:33 +0100 Subject: [coreboot] [PATCH] Fix printk format warning In-Reply-To: <49AAD7A7.8040308@gmx.net> References: <49AAD7A7.8040308@gmx.net> Message-ID: <49AAE0F1.9060609@coresystems.de> On 01.03.2009 19:44 Uhr, Carl-Daniel Hailfinger wrote: > Fix printk format warning in amdk8_acpi.c. > > Signed-off-by: Carl-Daniel Hailfinger > > > Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c > Are you sure this is a current tree? > =================================================================== > --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c (Revision 3967) > +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c (Arbeitskopie) > @@ -128,7 +128,7 @@ > basek = resk(res->base); > sizek = resk(res->size); > > - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", > + printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", > dev_path(dev), res->index, basek, sizek); > /* > * 0-640K must be on node 0 > > Acked-by: Stefan Reinauer -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From c-d.hailfinger.devel.2006 at gmx.net Mon Mar 2 02:32:54 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 02 Mar 2009 02:32:54 +0100 Subject: [coreboot] [PATCH] Fix printk format warning In-Reply-To: <49AAE0F1.9060609@coresystems.de> References: <49AAD7A7.8040308@gmx.net> <49AAE0F1.9060609@coresystems.de> Message-ID: <49AB3746.1030403@gmx.net> On 01.03.2009 20:24, Stefan Reinauer wrote: > On 01.03.2009 19:44 Uhr, Carl-Daniel Hailfinger wrote: > >> Fix printk format warning in amdk8_acpi.c. >> >> Signed-off-by: Carl-Daniel Hailfinger >> >> >> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c >> >> > Are you sure this is a current tree? > Yes. For easier tab completion, the v2 trees on my disk are named LinuxBIOSv2-* and the v3 trees are named corebootv3-* > Acked-by: Stefan Reinauer > Thanks! I just went on a bugfix frenzy and fixed all printk format warnings triggered by the AMD 690/SB600 targets and would prefer to commit them in one go. This new patch includes the small patch you already acked. Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c (working copy) @@ -129,7 +129,7 @@ device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c (working copy) @@ -203,7 +203,7 @@ device_t sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); + printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); /* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c (working copy) @@ -121,7 +121,7 @@ device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); - printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, + printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, nb_dev); /* set APERTURE_SIZE, 128M. */ @@ -417,7 +417,7 @@ struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", + printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* step 0, REFCLK_SEL, skip A11 revision */ Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c (working copy) @@ -96,7 +96,7 @@ printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ + printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c (working copy) @@ -94,7 +94,7 @@ /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%x\n", usb2_bar0); + printk_info("usb2_bar0=%p\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c (working copy) @@ -302,7 +302,7 @@ return; base = (u8 *) ((u32)res->base); - printk_debug("base = %08x\n", base); + printk_debug("base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { Index: LinuxBIOSv2-printkformatwarnings/src/devices/device.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/devices/device.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/devices/device.c (working copy) @@ -358,7 +358,7 @@ base += size; printk_spew( - "%s %02x * [0x%08Lx - 0x%08Lx] %s\n", + "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", dev_path(dev), resource->index, resource->base, Index: LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c (working copy) @@ -357,7 +357,7 @@ #endif } /* Allocate an msr */ - printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek); + printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); state->range_startk = basek; state->range_sizek = sizek; } Index: LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c (working copy) @@ -136,7 +136,7 @@ maxlvt = 4; for (j = 1; j <= num_starts; j++) { - printk_spew("Sending STARTUP #%d to %u.\n", j, apicid); + printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid); lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); lapic_read(LAPIC_ESR); @@ -239,7 +239,7 @@ #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" #endif if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { - printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10); + printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); die("Can not go on\n"); } stack_end -= sizeof(struct cpu_info); Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c (working copy) @@ -73,7 +73,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (u8 *) (addr); Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c (working copy) @@ -255,7 +255,7 @@ ((acpi_header_t *) AmlCode)->length); current += dsdt->length; - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); /* FADT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c (working copy) @@ -61,7 +61,7 @@ { u8 byte; - printk_info("enable_onboard_nic.\n"); + printk_info("%s.\n", __func__); /* enable GPM8 output */ byte = pm_ioread(0x95); @@ -274,7 +274,7 @@ struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev); + printk_info("Mainboard Pistachio Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -308,7 +308,7 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ @@ -328,7 +328,7 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c (working copy) @@ -73,7 +73,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (u8 *) (addr); Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c (working copy) @@ -254,7 +254,7 @@ memcpy((void *)dsdt, (void *)AmlCode, ((acpi_header_t *) AmlCode)->length); current += dsdt->length; - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); /* FADT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c (working copy) @@ -61,7 +61,7 @@ { u8 byte; - printk_info("enable_onboard_nic.\n"); + printk_info("%s.\n", __func__); /* set index register 0C50h to 13h (miscellaneous control) */ outb(0x13, 0xC50); /* CMIndex */ @@ -202,7 +202,7 @@ struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); + printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -236,7 +236,7 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ @@ -256,7 +256,7 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); Index: LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c (working copy) @@ -27,7 +27,7 @@ { void *p; - MALLOCDBG(("%s Enter, size %d, free_mem_ptr %p\n", __func__, size, free_mem_ptr)); + MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr)); if (size < 0) die("Error! malloc: Size < 0"); if (free_mem_ptr <= 0) Index: LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c (working copy) @@ -128,7 +128,7 @@ basek = resk(res->base); sizek = resk(res->size); - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", + printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", dev_path(dev), res->index, basek, sizek); /* * 0-640K must be on node 0 Index: LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c (revision 3967) +++ LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c (working copy) @@ -473,7 +473,7 @@ limit |= (nodeid & 7); if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", + printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", __func__, dev_path(dev), link); base |= PCI_IO_BASE_VGA_EN; } -- http://www.hailfinger.org/ From joe at settoplinux.org Mon Mar 2 03:51:23 2009 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 01 Mar 2009 21:51:23 -0500 Subject: [coreboot] r3965 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/include/arch src/config src/devices src/include src/include/cpu/x86 util In-Reply-To: <0MKojg-1LdiiY12Ia-000Shx@mx.perfora.net> References: <0MKojg-1LdiiY12Ia-000Shx@mx.perfora.net> Message-ID: > In order to use the old bios emulator, you have to do nothing. (Default, > if > CONFIG_PCI_ROM_RUN is enabled) > > In order to use yabel in your target, you need to add the following lines > to > your config: > uses CONFIG_PCI_OPTION_ROM_RUN_YABEL > default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 > > In order to use vm86 in your target, you need to add the following lines > to > your config: > uses CONFIG_PCI_OPTION_ROM_RUN_VM86 > default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 > Note: vm86 only works on platforms with _RAMBASE in the lower megabyte. > Can we get this added to the wiki somewhere? Maybe http://www.coreboot.org/Coreboot_Options ? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From yinghai at kernel.org Mon Mar 2 04:23:10 2009 From: yinghai at kernel.org (Yinghai Lu) Date: Sun, 01 Mar 2009 19:23:10 -0800 Subject: [coreboot] [PATCH] x86: ioremap mptable -v2 In-Reply-To: <20090301180420.GA27040@morn.localdomain> References: <499DB40C.1060205@coresystems.de> <499DCE79.8020809@coresystems.de> <20090222152530.GA30576@morn.localdomain> <200902221806.55429.rjw@sisk.pl> <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> <20090301180420.GA27040@morn.localdomain> Message-ID: <49AB511E.9010507@kernel.org> Impact: fix boot with mptable above max_low_mapped try to use early_ioremap it. v2: also get the exact size for reserve_bootmem in case we got big size than 4k Signed-off-by: Yinghai Lu Reported-and-tested-by: Kevin O'Connor --- arch/x86/kernel/mpparse.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) Index: linux-2.6/arch/x86/kernel/mpparse.c =================================================================== --- linux-2.6.orig/arch/x86/kernel/mpparse.c +++ linux-2.6/arch/x86/kernel/mpparse.c @@ -611,12 +611,20 @@ static void __init __get_smp_config(unsi construct_default_ISA_mptable(mpf->feature1); } else if (mpf->physptr) { + struct mpc_table *mpc; + unsigned long size; + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); + size = mpc->length; + apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", (unsigned long)mpf->physptr, + mpf->physptr + size); + early_iounmap(mpc, PAGE_SIZE); + mpc = early_ioremap(mpf->physptr, size); /* * Read the physical hardware table. Anything here will * override the defaults. */ - if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { + if (!smp_read_mpc(mpc, early)) { #ifdef CONFIG_X86_LOCAL_APIC smp_found_config = 0; #endif @@ -624,9 +632,12 @@ static void __init __get_smp_config(unsi "BIOS bug, MP table errors detected!...\n"); printk(KERN_ERR "... disabling SMP support. " "(tell your hw vendor)\n"); + early_iounmap(mpc, size); return; } + early_iounmap(mpc, size); + if (early) return; #ifdef CONFIG_X86_IO_APIC @@ -700,7 +711,12 @@ static int __init smp_scan_config(unsign reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE, BOOTMEM_DEFAULT); if (mpf->physptr) { - unsigned long size = PAGE_SIZE; + struct mpc_table *mpc; + unsigned long size; + + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); + size = mpc->length; + early_iounmap(mpc, PAGE_SIZE); #ifdef CONFIG_X86_32 /* * We cannot access to MPC table to compute[PATCH] x86: ioremap mptable -v2 Impact: fix boot with mptable above max_low_mapped try to use early_ioremap it. v2: also get the exact size for reserve_bootmem in case we got big size than 4k Signed-off-by: Yinghai Lu Reported-and-tested-by: Kevin O'Connor --- arch/x86/kernel/mpparse.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) Index: linux-2.6/arch/x86/kernel/mpparse.c =================================================================== --- linux-2.6.orig/arch/x86/kernel/mpparse.c +++ linux-2.6/arch/x86/kernel/mpparse.c @@ -611,12 +611,20 @@ static void __init __get_smp_config(unsi construct_default_ISA_mptable(mpf->feature1); } else if (mpf->physptr) { + struct mpc_table *mpc; + unsigned long size; + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); + size = mpc->length; + apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", (unsigned long)mpf->physptr, + mpf->physptr + size); + early_iounmap(mpc, PAGE_SIZE); + mpc = early_ioremap(mpf->physptr, size); /* * Read the physical hardware table. Anything here will * override the defaults. */ - if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { + if (!smp_read_mpc(mpc, early)) { #ifdef CONFIG_X86_LOCAL_APIC smp_found_config = 0; #endif @@ -624,9 +632,12 @@ static void __init __get_smp_config(unsi "BIOS bug, MP table errors detected!...\n"); printk(KERN_ERR "... disabling SMP support. " "(tell your hw vendor)\n"); + early_iounmap(mpc, size); return; } + early_iounmap(mpc, size); + if (early) return; #ifdef CONFIG_X86_IO_APIC @@ -700,7 +711,12 @@ static int __init smp_scan_config(unsign reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE, BOOTMEM_DEFAULT); if (mpf->physptr) { - unsigned long size = PAGE_SIZE; + struct mpc_table *mpc; + unsigned long size; + + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); + size = mpc->length; + early_iounmap(mpc, PAGE_SIZE); #ifdef CONFIG_X86_32 /* * We cannot access to MPC table to compute From mingo at elte.hu Mon Mar 2 11:18:23 2009 From: mingo at elte.hu (Ingo Molnar) Date: Mon, 2 Mar 2009 11:18:23 +0100 Subject: [coreboot] [PATCH] x86: ioremap mptable -v2 In-Reply-To: <49AB511E.9010507@kernel.org> References: <20090222152530.GA30576@morn.localdomain> <200902221806.55429.rjw@sisk.pl> <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> <20090301180420.GA27040@morn.localdomain> <49AB511E.9010507@kernel.org> Message-ID: <20090302101823.GJ20897@elte.hu> * Yinghai Lu wrote: > Impact: fix boot with mptable above max_low_mapped > > try to use early_ioremap it. > > v2: also get the exact size for reserve_bootmem in case we got big size than 4k > > Signed-off-by: Yinghai Lu > Reported-and-tested-by: Kevin O'Connor > > --- > arch/x86/kernel/mpparse.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > Index: linux-2.6/arch/x86/kernel/mpparse.c > =================================================================== > --- linux-2.6.orig/arch/x86/kernel/mpparse.c > +++ linux-2.6/arch/x86/kernel/mpparse.c > @@ -611,12 +611,20 @@ static void __init __get_smp_config(unsi > construct_default_ISA_mptable(mpf->feature1); > > } else if (mpf->physptr) { > + struct mpc_table *mpc; > + unsigned long size; > > + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); > + size = mpc->length; > + apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", (unsigned long)mpf->physptr, > + mpf->physptr + size); > + early_iounmap(mpc, PAGE_SIZE); > + mpc = early_ioremap(mpf->physptr, size); no objections, but this bit of __get_smp_config() needs to be done cleaner - the whole mpf->physptr != 0 bit should probably go into a helper function. Ingo From mingo at elte.hu Mon Mar 2 11:19:18 2009 From: mingo at elte.hu (Ingo Molnar) Date: Mon, 2 Mar 2009 11:19:18 +0100 Subject: [coreboot] [PATCH] x86: ioremap mptable -v2 In-Reply-To: <20090302101823.GJ20897@elte.hu> References: <200902221806.55429.rjw@sisk.pl> <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> <20090301180420.GA27040@morn.localdomain> <49AB511E.9010507@kernel.org> <20090302101823.GJ20897@elte.hu> Message-ID: <20090302101918.GA6705@elte.hu> * Ingo Molnar wrote: > > } else if (mpf->physptr) { > > + struct mpc_table *mpc; > > + unsigned long size; > > > > + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); > > + size = mpc->length; > > + apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", (unsigned long)mpf->physptr, > > + mpf->physptr + size); > > + early_iounmap(mpc, PAGE_SIZE); > > + mpc = early_ioremap(mpf->physptr, size); > > no objections, but this bit of __get_smp_config() needs to be > done cleaner - the whole mpf->physptr != 0 bit should probably > go into a helper function. and if you do that it should be done via two patches, in two steps: first patch is a pure cleanup that moves this bit of __get_smp_config() into a helper function. The second patch then adds the early_ioremap(). Ingo From svn at coreboot.org Mon Mar 2 11:36:02 2009 From: svn at coreboot.org (coreboot) Date: Mon, 02 Mar 2009 10:36:02 -0000 Subject: [coreboot] #42: Disable SMM on K8 platforms In-Reply-To: <042.41495118e7095f3b73b30580e95f5486@coreboot.org> References: <042.41495118e7095f3b73b30580e95f5486@coreboot.org> Message-ID: <051.9685ea7eb98204d0f4eedd572bd3ce7a@coreboot.org> #42: Disable SMM on K8 platforms ----------------------------------+----------------------------------------- Reporter: stepan | Owner: stepan Type: defect | Status: assigned Priority: major | Milestone: Going mainstream Component: coreboot | Version: v2 Keywords: SMM, security | Dependencies: Patchstatus: patch needs review | ----------------------------------+----------------------------------------- Comment(by hailfinger): What's the status of this patch? -- Ticket URL: coreboot From svn at coreboot.org Mon Mar 2 11:44:07 2009 From: svn at coreboot.org (coreboot) Date: Mon, 02 Mar 2009 10:44:07 -0000 Subject: [coreboot] #122: Add links to logs of successful builds on the QA pages Message-ID: <046.8698c73b9cbdb016161fcf0ea1ff3e47@coreboot.org> #122: Add links to logs of successful builds on the QA pages ------------------------------------+--------------------------------------- Reporter: hailfinger | Owner: stepan Type: enhancement | Status: new Priority: major | Milestone: Component: wiki/website/tracker | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- http://qa.coreboot.org/log_buildrev.php?revision=3962 and other build status pages contain only links to failing builds. Please add links to successful logs as well. Benefits: * easier comparisons between failing and successful builds * the ability to look for warnings in the compiler output -- Ticket URL: coreboot From svn at coreboot.org Mon Mar 2 11:51:56 2009 From: svn at coreboot.org (coreboot) Date: Mon, 02 Mar 2009 10:51:56 -0000 Subject: [coreboot] #122: Add links to logs of successful builds on the QA pages In-Reply-To: <046.8698c73b9cbdb016161fcf0ea1ff3e47@coreboot.org> References: <046.8698c73b9cbdb016161fcf0ea1ff3e47@coreboot.org> Message-ID: <055.d7fa2ef3e751c728b1f524a5b9bd44c8@coreboot.org> #122: Add links to logs of successful builds on the QA pages ------------------------------------+--------------------------------------- Reporter: hailfinger | Owner: stepan Type: enhancement | Status: assigned Priority: major | Milestone: Component: wiki/website/tracker | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- Changes (by stepan): * status: new => assigned -- Ticket URL: coreboot From phueper at hueper.net Mon Mar 2 13:46:21 2009 From: phueper at hueper.net (Pattrick Hueper) Date: Mon, 2 Mar 2009 13:46:21 +0100 Subject: [coreboot] [PATCH] port yabel and vm86 to v2. In-Reply-To: <49A9E63C.7090106@coresystems.de> References: <49A9E63C.7090106@coresystems.de> Message-ID: Iknow it's already too late... but still: Acked-by: Pattrick Hueper Patty On Sun, Mar 1, 2009 at 2:34 AM, Stefan Reinauer wrote: > These patches replace the v2 bios emulator by the version from coreboot v3, > including yabel and vm86. > > Other actions required: > > svn propset "x86emu > svn://coreboot.org/repository/coreboot-v3/util/x86emu" util > svn rm src/devices/emulator > > Best regards, > Stefan > > -- > coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. > ? ? ?Tel.: +49 761 7668825 ? Fax: +49 761 7664613 > Email: info at coresystems.de ?? http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg ? HRB 7656 > Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 > > From oli at rhce.servebbs.net Mon Mar 2 15:46:36 2009 From: oli at rhce.servebbs.net (Oliver Niesner) Date: Mon, 02 Mar 2009 15:46:36 +0100 Subject: [coreboot] A8N-SLI-Deluxe_support In-Reply-To: <49A2B28A.8050103@rhce.servebbs.net> References: <49A2B28A.8050103@rhce.servebbs.net> Message-ID: <49ABF14C.7060906@rhce.servebbs.net> Oliver Niesner wrote: > Hi, all > > I'am very new to all the coreboot stuff and i need some info - > hope someone can help. > > I have an ASUS A8N-SLI-Deluxe mainboard. > According to the list on coreboot.org the A8V-E Deluxe is supported, but > i found nothing about A8N-SLI-Deluxe. > Has somebody info about the support for that mainboard? > > Thanks, > > Oliver > Sorry for my blindness, i overlooked it!! Will be more careful in the future. Oliver From c-d.hailfinger.devel.2006 at gmx.net Mon Mar 2 15:57:44 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 02 Mar 2009 15:57:44 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c Message-ID: <49ABF3E8.6070109@gmx.net> Hi, Using pci_read_config8() inside mainboard.c causes a crash on the AMD DBM690T and Pistachio targets. AMD developers are seeing the crash as well and use pci_cf8_conf1.read8() instead which works fine. Since I won't have access to my Asus M2A-VM board in the next two weeks, I'd appreciate if someone could test the patch below on a M2A-VM. I expect it to hang somewhere along these messages: [...] enable_onboard_nic. enable_onboard_nic done. get_ide_dma66. get_ide_dma66 dev_find_slot(0:14.0) returned .... If you can't recover from a non-booting image, DO NOT USE! Signed-off-by: Carl-Daniel Hailfinger Index: src/southbridge/amd/rs690/rs690.c =================================================================== --- src/southbridge/amd/rs690/rs690.c (Revision 3967) +++ src/southbridge/amd/rs690/rs690.c (Arbeitskopie) @@ -129,7 +129,7 @@ device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { Index: src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- src/southbridge/amd/rs690/rs690_pcie.c (Revision 3967) +++ src/southbridge/amd/rs690/rs690_pcie.c (Arbeitskopie) @@ -203,7 +203,7 @@ device_t sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); + printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); /* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, Index: src/southbridge/amd/rs690/rs690_gfx.c =================================================================== --- src/southbridge/amd/rs690/rs690_gfx.c (Revision 3967) +++ src/southbridge/amd/rs690/rs690_gfx.c (Arbeitskopie) @@ -121,7 +121,7 @@ device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); - printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, + printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, nb_dev); /* set APERTURE_SIZE, 128M. */ @@ -417,7 +417,7 @@ struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", + printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* step 0, REFCLK_SEL, skip A11 revision */ Index: src/southbridge/amd/sb600/sb600_sata.c =================================================================== --- src/southbridge/amd/sb600/sb600_sata.c (Revision 3967) +++ src/southbridge/amd/sb600/sb600_sata.c (Arbeitskopie) @@ -96,7 +96,7 @@ printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ + printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; Index: src/southbridge/amd/sb600/sb600_usb.c =================================================================== --- src/southbridge/amd/sb600/sb600_usb.c (Revision 3967) +++ src/southbridge/amd/sb600/sb600_usb.c (Arbeitskopie) @@ -94,7 +94,7 @@ /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%x\n", usb2_bar0); + printk_info("usb2_bar0=%p\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; Index: src/southbridge/amd/sb600/sb600_hda.c =================================================================== --- src/southbridge/amd/sb600/sb600_hda.c (Revision 3967) +++ src/southbridge/amd/sb600/sb600_hda.c (Arbeitskopie) @@ -302,7 +302,7 @@ return; base = (u8 *) ((u32)res->base); - printk_debug("base = %08x\n", base); + printk_debug("base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { Index: src/devices/device.c =================================================================== --- src/devices/device.c (Revision 3967) +++ src/devices/device.c (Arbeitskopie) @@ -358,7 +358,7 @@ base += size; printk_spew( - "%s %02x * [0x%08Lx - 0x%08Lx] %s\n", + "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", dev_path(dev), resource->index, resource->base, Index: src/devices/pci_ops.c =================================================================== --- src/devices/pci_ops.c (Revision 3967) +++ src/devices/pci_ops.c (Arbeitskopie) @@ -24,7 +24,7 @@ #include #include -static struct bus *get_pbus(device_t dev) +struct bus *get_pbus(device_t dev) { struct bus *pbus = dev->bus; while(pbus && pbus->dev && !ops_pci_bus(pbus)) { Index: src/include/device/pci.h =================================================================== --- src/include/device/pci.h (Revision 3967) +++ src/include/device/pci.h (Arbeitskopie) @@ -99,5 +99,6 @@ } return bops; } +struct bus *get_pbus(device_t dev); #endif /* PCI_H */ Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (Revision 3967) +++ src/cpu/x86/mtrr/mtrr.c (Arbeitskopie) @@ -357,7 +357,7 @@ #endif } /* Allocate an msr */ - printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek); + printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); state->range_startk = basek; state->range_sizek = sizek; } Index: src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- src/cpu/x86/lapic/lapic_cpu_init.c (Revision 3967) +++ src/cpu/x86/lapic/lapic_cpu_init.c (Arbeitskopie) @@ -136,7 +136,7 @@ maxlvt = 4; for (j = 1; j <= num_starts; j++) { - printk_spew("Sending STARTUP #%d to %u.\n", j, apicid); + printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid); lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); lapic_read(LAPIC_ESR); @@ -239,7 +239,7 @@ #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" #endif if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { - printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10); + printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); die("Can not go on\n"); } stack_end -= sizeof(struct cpu_info); Index: src/mainboard/amd/pistachio/resourcemap.c =================================================================== --- src/mainboard/amd/pistachio/resourcemap.c (Revision 3967) +++ src/mainboard/amd/pistachio/resourcemap.c (Arbeitskopie) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void setup_pistachio_resource_map(void) +static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ Index: src/mainboard/amd/pistachio/chip.h =================================================================== --- src/mainboard/amd/pistachio/chip.h (Revision 3967) +++ src/mainboard/amd/pistachio/chip.h (Arbeitskopie) @@ -21,6 +21,6 @@ struct mainboard_config { - unsigned long uma_size; /* How many UMA should be used in memory for TOP. */ + u32 uma_size; /* How many UMA should be used in memory for TOP. */ }; Index: src/mainboard/amd/pistachio/acpi/dsdt.asl =================================================================== --- src/mainboard/amd/pistachio/acpi/dsdt.asl (Revision 3967) +++ src/mainboard/amd/pistachio/acpi/dsdt.asl (Arbeitskopie) @@ -21,7 +21,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x01, /* DSDT Revision */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ "PISTACHI", /* TABLE ID */ 0x00010001 /* OEM Revision */ @@ -32,7 +32,6 @@ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ /* Memory related values */ - Name(TOM2, 0x0) /* Top of RAM memory above 4GB (>> 16) */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ @@ -1129,6 +1128,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) + External (TOM2) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ Index: src/mainboard/amd/pistachio/mainboard.c =================================================================== --- src/mainboard/amd/pistachio/mainboard.c (Revision 3967) +++ src/mainboard/amd/pistachio/mainboard.c (Arbeitskopie) @@ -83,7 +83,6 @@ u16 word; u32 dword; device_t sm_dev; - struct bus pbus; /* set adt7475 */ ADT7475_write_byte(0x40, 0x04); @@ -116,11 +115,11 @@ /* remote 2 therm temp limit (95C) */ ADT7475_write_byte(0x6c, 0x9f); - /* PWM 1 minimum duty cycle (37%) */ + /* PWM 1 minimum duty cycle (37.6%) */ ADT7475_write_byte(0x64, 0x60); /* PWM 1 Maximum duty cycle (100%) */ ADT7475_write_byte(0x38, 0xff); - /* PWM 3 minimum duty cycle (37%) */ + /* PWM 3 minimum duty cycle (37.6%) */ ADT7475_write_byte(0x66, 0x60); /* PWM 3 Maximum Duty Cycle (100%) */ ADT7475_write_byte(0x3a, 0xff); @@ -167,28 +166,19 @@ /* GPM5 as GPIO not USB OC */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - dword = - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x64); + dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 19; - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x64, dword); + pci_write_config32(sm_dev, 0x64, dword); /* Enable Client Management Index/Data registers */ - dword = - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x78); + dword = pci_read_config32(sm_dev, 0x78); dword |= 1 << 11; /* Cms_enable */ - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x78, dword); + pci_write_config32(sm_dev, 0x78, dword); /* MiscfuncEnable */ - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x41); + byte = pci_read_config8(sm_dev, 0x41); byte |= (1 << 5); - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x41, byte); + pci_write_config8(sm_dev, 0x41, byte); /* set GPM5 as input */ /* set index register 0C50h to 13h (miscellaneous control) */ @@ -228,12 +218,9 @@ pm2_iowrite(0x42, byte); /* set GPIO 64 to input */ - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); @@ -269,12 +256,12 @@ * enable the dedicated function in pistachio board. * This function called early than rs690_enable. *************************************************/ -void pistachio_enable(device_t dev) +void mb_enable(device_t dev) { struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev); + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=0x%x\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -339,6 +326,6 @@ * CONFIG_CHIP_NAME defined in Option.lb. */ struct chip_operations mainboard_ops = { - CHIP_NAME("AMD Pistachio Mainboard") - .enable_dev = pistachio_enable, + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = mb_enable, }; Index: src/mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- src/mainboard/amd/pistachio/cache_as_ram_auto.c (Revision 3967) +++ src/mainboard/amd/pistachio/cache_as_ram_auto.c (Arbeitskopie) @@ -156,9 +156,8 @@ u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = - (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -178,7 +177,7 @@ report_bist_failure(bist); printk_debug("bsp_apicid=0x%x\n", bsp_apicid); - setup_pistachio_resource_map(); + setup_mb_resource_map(); setup_coherent_ht_domain(); Index: src/mainboard/amd/dbm690t/Config.lb =================================================================== --- src/mainboard/amd/dbm690t/Config.lb (Revision 3967) +++ src/mainboard/amd/dbm690t/Config.lb (Arbeitskopie) @@ -197,7 +197,7 @@ #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on - chip cpu/amd/socket_S1G1 + chip cpu/amd/socket_AM2 device apic 0 on end end end @@ -213,7 +213,7 @@ end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b + #device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 4.0 on end # PCIE P2P bridge 0x7914 device pci 5.0 on end # PCIE P2P bridge 0x7915 device pci 6.0 on end # PCIE P2P bridge 0x7916 @@ -257,9 +257,9 @@ device pci 14.3 on # LPC 0x438d chip superio/ite/it8712f device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + #io 0x60 = 0x3f0 + #irq 0x70 = 6 + #drq 0x74 = 2 end device pnp 2e.1 on # Com1 io 0x60 = 0x3f8 Index: src/mainboard/amd/dbm690t/irq_tables.c =================================================================== --- src/mainboard/amd/dbm690t/irq_tables.c (Revision 3967) +++ src/mainboard/amd/dbm690t/irq_tables.c (Arbeitskopie) @@ -54,7 +54,7 @@ extern u8 bus_isa; extern u8 bus_rs690[8]; extern u8 bus_sb600[2]; -extern unsigned long sbdn_sb600; +extern u32 sbdn_sb600; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -73,7 +73,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (u8 *) (addr); Index: src/mainboard/amd/dbm690t/resourcemap.c =================================================================== --- src/mainboard/amd/dbm690t/resourcemap.c (Revision 3967) +++ src/mainboard/amd/dbm690t/resourcemap.c (Arbeitskopie) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void setup_dbm690t_resource_map(void) +static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ Index: src/mainboard/amd/dbm690t/acpi_tables.c =================================================================== --- src/mainboard/amd/dbm690t/acpi_tables.c (Revision 3967) +++ src/mainboard/amd/dbm690t/acpi_tables.c (Arbeitskopie) @@ -254,7 +254,7 @@ memcpy((void *)dsdt, (void *)AmlCode, ((acpi_header_t *) AmlCode)->length); current += dsdt->length; - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); /* FADT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Index: src/mainboard/amd/dbm690t/acpi/dsdt.asl =================================================================== --- src/mainboard/amd/dbm690t/acpi/dsdt.asl (Revision 3967) +++ src/mainboard/amd/dbm690t/acpi/dsdt.asl (Arbeitskopie) @@ -19,12 +19,12 @@ /* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x01, /* DSDT Revision */ - "AMD ", /* OEMID */ - "DBM690T ", /* TABLE ID */ - 0x00010001 /* OEM Revision */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "DBM690T ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ /* Include ("debug.asl") */ /* Include global debug methods if needed */ @@ -32,7 +32,6 @@ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ /* Memory related values */ - Name(TOM2, 0x0) /* Top of RAM memory above 4GB (>> 16) */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ @@ -1130,6 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) + External (TOM2) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1476,7 +1476,7 @@ 0x0000, /* range minimum */ 0x0CF7, /* range maximum */ 0x0000, /* translation */ - 0x0CF8 /* Resource source index */ + 0x0CF8 /* length */ ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, @@ -1554,12 +1554,10 @@ /* Set size of memory from 1MB to TopMem */ Subtract(TOM1, 0x100000, DMLL) - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ + If(LNotEqual(TOM2, 0x00000000)){ + Store(0x100000000,DMHB) /* DRAM from 4GB to TopMem2 */ + Subtract(TOM2, 0x100000000, DMHL) + } /* If there is no memory above 4GB, put the BIOS just below 4GB */ If(LEqual(TOM2, 0x00000000)){ Index: src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- src/mainboard/amd/dbm690t/mainboard.c (Revision 3967) +++ src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -61,7 +61,7 @@ { u8 byte; - printk_info("enable_onboard_nic.\n"); + printk_info("%s.\n", __func__); /* set index register 0C50h to 13h (miscellaneous control) */ outb(0x13, 0xC50); /* CMIndex */ @@ -87,6 +87,7 @@ byte = inb(0xC52); byte &= ~0x8; outb(byte, 0xC52); + printk_info("%s done.\n", __func__); } /******************************************************** @@ -97,32 +98,36 @@ static void get_ide_dma66() { u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - struct bus pbus; + struct device *sm_dev; + struct device *ide_dev; + struct bus *pbus; + printk_info("%s.\n", __func__); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + printk_info("%s dev_find_slot(0:14.0) returned sm_dev=%p, sm_dev->bus=%p.\n", __func__, sm_dev, sm_dev->bus); - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9); + printk_info("%s running get_pbus(sm_dev)\n", __func__); + pbus = get_pbus(sm_dev); + printk_info("%s pbus=%p, ops_pci_bus(pbus)=%p, &pci_cf8_conf1=%p.\n", __func__, pbus, ops_pci_bus(pbus), &pci_cf8_conf1); + if (ops_pci_bus(pbus) != &pci_cf8_conf1) + printk_info("%s ops_pci_bus(pbus) and &pci_cf8_conf1 do NOT match! Die?\n", __func__); + //byte = ops_pci_bus(pbus)->read8(pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA9); + //byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA9); + byte = pci_read_config8(sm_dev, 0xA9); + printk_info("%s survived first pci_read_config8\n", __func__); byte |= (1 << 5); /* Set Gpio9 as input */ - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9, byte); + pci_write_config8(sm_dev, 0xA9, byte); + printk_info("%s survived first pci_write_config8\n", __func__); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56); + byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 5) & pci_cf8_conf1. - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, - 0xAA)) + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56, byte); + pci_write_config8(ide_dev, 0x56, byte); + printk_info("%s done.\n", __func__); } /* @@ -133,7 +138,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -156,12 +160,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); @@ -197,12 +198,12 @@ * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -void dbm690t_enable(device_t dev) +void mb_enable(device_t dev) { struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -236,7 +237,7 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ @@ -256,7 +257,7 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); @@ -267,6 +268,6 @@ * CONFIG_CHIP_NAME defined in Option.lb. */ struct chip_operations mainboard_ops = { - CHIP_NAME("AMD DBM690T Mainboard") - .enable_dev = dbm690t_enable, + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = mb_enable, }; Index: src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3967) +++ src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie) @@ -32,6 +32,8 @@ #define DIMM0 0x50 #define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 #define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 @@ -137,7 +139,7 @@ normal_image: post_code(0x23); __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); + :"a" (bist), "b"(cpu_init_detectedx)); /* inputs */ fallback_image: post_code(0x25); @@ -157,14 +159,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; + static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); - if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } @@ -181,7 +183,7 @@ report_bist_failure(bist); printk_debug("bsp_apicid=0x%x\n", bsp_apicid); - setup_dbm690t_resource_map(); + setup_mb_resource_map(); setup_coherent_ht_domain(); Index: src/lib/malloc.c =================================================================== --- src/lib/malloc.c (Revision 3967) +++ src/lib/malloc.c (Arbeitskopie) @@ -27,7 +27,7 @@ { void *p; - MALLOCDBG(("%s Enter, size %d, free_mem_ptr %p\n", __func__, size, free_mem_ptr)); + MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr)); if (size < 0) die("Error! malloc: Size < 0"); if (free_mem_ptr <= 0) Index: src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- src/northbridge/amd/amdk8/amdk8_acpi.c (Revision 3967) +++ src/northbridge/amd/amdk8/amdk8_acpi.c (Arbeitskopie) @@ -128,7 +128,7 @@ basek = resk(res->base); sizek = resk(res->size); - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", + printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", dev_path(dev), res->index, basek, sizek); /* * 0-640K must be on node 0 Index: src/northbridge/amd/amdk8/raminit.c =================================================================== --- src/northbridge/amd/amdk8/raminit.c (Revision 3967) +++ src/northbridge/amd/amdk8/raminit.c (Arbeitskopie) @@ -1420,9 +1420,6 @@ die("min_cycle_time to low"); } print_spew(param->name); -#ifdef DRAM_MIN_CYCLE_TIME - print_debug(param->name); -#endif return param; } Index: src/northbridge/amd/amdk8/northbridge.c =================================================================== --- src/northbridge/amd/amdk8/northbridge.c (Revision 3967) +++ src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -473,7 +473,7 @@ limit |= (nodeid & 7); if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", + printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", __func__, dev_path(dev), link); base |= PCI_IO_BASE_VGA_EN; } Index: src/northbridge/amd/amdk8/raminit_f.c =================================================================== Index: src/arch/i386/include/arch/smp/mpspec.h =================================================================== --- src/arch/i386/include/arch/smp/mpspec.h (Revision 3967) +++ src/arch/i386/include/arch/smp/mpspec.h (Arbeitskopie) @@ -1,6 +1,8 @@ #ifndef __ASM_MPSPEC_H #define __ASM_MPSPEC_H +#include + #if HAVE_MP_TABLE==1 /* Index: targets/amd/dbm690t/Config-abuild.lb =================================================================== --- targets/amd/dbm690t/Config-abuild.lb (Revision 3967) +++ targets/amd/dbm690t/Config-abuild.lb (Arbeitskopie) @@ -7,9 +7,12 @@ option CROSS_COMPILE="CROSS_PREFIX" option HOSTCC="CROSS_HOSTCC" +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + __COMPRESSION__ -option ROM_SIZE=1024*1024 +option ROM_SIZE = 1024*1024 - 54784 romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 -- http://www.hailfinger.org/ From rminnich at gmail.com Mon Mar 2 16:17:12 2009 From: rminnich at gmail.com (ron minnich) Date: Mon, 2 Mar 2009 07:17:12 -0800 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49ABF3E8.6070109@gmx.net> References: <49ABF3E8.6070109@gmx.net> Message-ID: <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> On Mon, Mar 2, 2009 at 6:57 AM, Carl-Daniel Hailfinger wrote: > Hi, > > Using pci_read_config8() inside mainboard.c causes a crash on the AMD > DBM690T and Pistachio targets. AMD developers are seeing the crash as > well and use pci_cf8_conf1.read8() instead which works fine. Did this just start? ron From c-d.hailfinger.devel.2006 at gmx.net Mon Mar 2 16:30:41 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 02 Mar 2009 16:30:41 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> Message-ID: <49ABFBA1.80709@gmx.net> On 02.03.2009 16:17, ron minnich wrote: > On Mon, Mar 2, 2009 at 6:57 AM, Carl-Daniel Hailfinger > wrote: > >> Hi, >> >> Using pci_read_config8() inside mainboard.c causes a crash on the AMD >> DBM690T and Pistachio targets. AMD developers are seeing the crash as >> well and use pci_cf8_conf1.read8() instead which works fine. >> > > Did this just start? > AFAIK it has been the case at least since AMD published their 690G/SB600 port, maybe even before that. For a fun time, grep over the tree for pci_cf8_conf1 and you'll see it is not constrained to mainboard code. Regards, Carl-Daniel -- http://www.hailfinger.org/ From rminnich at gmail.com Mon Mar 2 16:33:49 2009 From: rminnich at gmail.com (ron minnich) Date: Mon, 2 Mar 2009 07:33:49 -0800 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49ABFBA1.80709@gmx.net> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> Message-ID: <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> On Mon, Mar 2, 2009 at 7:30 AM, Carl-Daniel Hailfinger wrote: > AFAIK it has been the case at least since AMD published their 690G/SB600 > port, maybe even before that. For a fun time, grep over the tree for > pci_cf8_conf1 and you'll see it is not constrained to mainboard code. ok, has anyone checked to see if it's the code that determines type 1/type 2 access going wrong somehow? If so, there's an easy fix :-) thanks ron From lists at r000n.net Mon Mar 2 16:34:03 2009 From: lists at r000n.net (Roman Mindalev) Date: Mon, 02 Mar 2009 15:34:03 +0000 Subject: [coreboot] GA-P31-ES3G motherboard support Message-ID: <49ABFC6B.9020407@r000n.net> Hi! Recently I'm get this PC: Intel E2200 Dual Core processor Gigabyte GA-P31-ES3G motherboard (P31 northbridge, ICH7 southbridge) flashrom r3844 with PAT disabled successfully made BIOS backup: Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found chip "Macronix MX25L4005" (512 KB) at physical address 0xfff80000 lspci output: 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller (rev 10) 00:01.0 PCI bridge: Intel Corporation 82G33/G31/P35/P31 Express PCI Express Root Port (rev 10) 00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition Audio Controller (rev 01) 00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 (rev 01) 00:1c.1 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 2 (rev 01) 00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 01) 00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 01) 00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 01) 00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 01) 00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 01) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1) 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge (rev 01) 00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE Controller (rev 01) 00:1f.2 IDE interface: Intel Corporation 82801GB/GR/GH (ICH7 Family) SATA IDE Controller (rev 01) 00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 01) 01:00.0 VGA compatible controller: nVidia Corporation GeForce 8400 GS (rev a1) 03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 02) Any chance for this hardware to be supported by coreboot? From c-d.hailfinger.devel.2006 at gmx.net Mon Mar 2 16:40:45 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 02 Mar 2009 16:40:45 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> Message-ID: <49ABFDFD.7080807@gmx.net> On 02.03.2009 16:33, ron minnich wrote: > On Mon, Mar 2, 2009 at 7:30 AM, Carl-Daniel Hailfinger > wrote: > > >> AFAIK it has been the case at least since AMD published their 690G/SB600 >> port, maybe even before that. For a fun time, grep over the tree for >> pci_cf8_conf1 and you'll see it is not constrained to mainboard code. >> > > > ok, has anyone checked to see if it's the code that determines type > 1/type 2 access going wrong somehow? > Maybe. pci_set_method() is not called on any K8 platform. AFAICS type 1 is hardcoded there, so pci_set_method should not be necessary in theory. I don't know whether setting the access method happens early enough for the mainboard code. > If so, there's an easy fix :-) > Hopefully. Once Ward boots tomorrow with my debug patch, we'll know where exactly it hangs and probably also why. Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Mon Mar 2 16:56:56 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 2 Mar 2009 08:56:56 -0700 Subject: [coreboot] slow load times In-Reply-To: <20090228173937.GA1885@morn.localdomain> References: <20090219044044.GA27902@morn.localdomain> <9C3A56E6AD3A4AFBA2DD1BFACFB5BA53@chimp> <20090219133543.GA32116@morn.localdomain> <229C9C3CE1FE4A5687A7D88B3DE84CF9@chimp> <2831fecf0902231300i72e23e79v164c717843007488@mail.gmail.com> <20090228013547.GA25923@morn.localdomain> <20090228173937.GA1885@morn.localdomain> Message-ID: <2831fecf0903020756m5c5a5c1s954487f83624f8c3@mail.gmail.com> On Sat, Feb 28, 2009 at 10:39 AM, Kevin O'Connor wrote: > On Sat, Feb 28, 2009 at 08:58:30AM -0700, Myles Watson wrote: >> > I'm okay with commiting this to SeaBIOS as long as it is disabled by >> > default. ?Is it okay if I commit this? >> Sure. ?It's been working for me so far :) > > I committed a patch based on your work. ?(I did make a few changes.) > Let me know if it works on your machine. Good idea to make it a bus number instead of a BDF. It still works. Thanks, Myles From marcj303 at gmail.com Mon Mar 2 17:02:59 2009 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 2 Mar 2009 09:02:59 -0700 Subject: [coreboot] #42: Disable SMM on K8 platforms In-Reply-To: <051.9685ea7eb98204d0f4eedd572bd3ce7a@coreboot.org> References: <042.41495118e7095f3b73b30580e95f5486@coreboot.org> <051.9685ea7eb98204d0f4eedd572bd3ce7a@coreboot.org> Message-ID: <534e5dc20903020802u7fc6f74exf482e29fa3521efe@mail.gmail.com> On Mon, Mar 2, 2009 at 3:36 AM, coreboot wrote: > #42: Disable SMM on K8 platforms > ----------------------------------+----------------------------------------- > ? Reporter: ?stepan ? ? ? ? ? ? ?| ? ? ? ? ?Owner: ?stepan > ? ? ? Type: ?defect ? ? ? ? ? ? ?| ? ? ? ? Status: ?assigned > ? Priority: ?major ? ? ? ? ? ? ? | ? ? ?Milestone: ?Going mainstream > ?Component: ?coreboot ? ? ? ? ? ?| ? ? ? ?Version: ?v2 > ? Keywords: ?SMM, security ? ? ? | ? Dependencies: > Patchstatus: ?patch needs review ?| > ----------------------------------+----------------------------------------- > > Comment(by hailfinger): > > ?What's the status of this patch? > This has been in the code for a long time. I think that is all that needs to be done. coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); Marc From yinghai at kernel.org Mon Mar 2 21:07:40 2009 From: yinghai at kernel.org (Yinghai Lu) Date: Mon, 02 Mar 2009 12:07:40 -0800 Subject: [coreboot] [PATCH] x86: ioremap mptable -v2 In-Reply-To: <20090302101823.GJ20897@elte.hu> References: <20090222152530.GA30576@morn.localdomain> <200902221806.55429.rjw@sisk.pl> <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> <20090301180420.GA27040@morn.localdomain> <49AB511E.9010507@kernel.org> <20090302101823.GJ20897@elte.hu> Message-ID: <49AC3C8C.8070702@kernel.org> Ingo Molnar wrote: > * Yinghai Lu wrote: > >> Impact: fix boot with mptable above max_low_mapped >> >> try to use early_ioremap it. >> >> v2: also get the exact size for reserve_bootmem in case we got big size than 4k >> >> Signed-off-by: Yinghai Lu >> Reported-and-tested-by: Kevin O'Connor >> >> --- >> arch/x86/kernel/mpparse.c | 20 ++++++++++++++++++-- >> 1 file changed, 18 insertions(+), 2 deletions(-) >> >> Index: linux-2.6/arch/x86/kernel/mpparse.c >> =================================================================== >> --- linux-2.6.orig/arch/x86/kernel/mpparse.c >> +++ linux-2.6/arch/x86/kernel/mpparse.c >> @@ -611,12 +611,20 @@ static void __init __get_smp_config(unsi >> construct_default_ISA_mptable(mpf->feature1); >> >> } else if (mpf->physptr) { >> + struct mpc_table *mpc; >> + unsigned long size; >> >> + mpc = early_ioremap(mpf->physptr, PAGE_SIZE); >> + size = mpc->length; >> + apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", (unsigned long)mpf->physptr, >> + mpf->physptr + size); >> + early_iounmap(mpc, PAGE_SIZE); >> + mpc = early_ioremap(mpf->physptr, size); > > no objections, but this bit of __get_smp_config() needs to be > done cleaner - the whole mpf->physptr != 0 bit should probably > go into a helper function. > please check [PATCH] x86: ioremap mptable -v3 Impact: fix boot with mptable above max_low_mapped try to use early_ioremap it. v2: also get the exact size for reserve_bootmem in case we got big size than 4k V3: according to Ingo, seperate get_mpc_size() Signed-off-by: Yinghai Lu Reported-and-tested-by: Kevin O'Connor --- arch/x86/kernel/mpparse.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) Index: linux-2.6/arch/x86/kernel/mpparse.c =================================================================== --- linux-2.6.orig/arch/x86/kernel/mpparse.c +++ linux-2.6/arch/x86/kernel/mpparse.c @@ -558,6 +558,19 @@ static inline void __init construct_defa static struct mpf_intel *mpf_found; +static unsigned long __init get_mpc_size(unsigned long physptr) +{ + struct mpc_table *mpc; + unsigned long size; + + mpc = early_ioremap(physptr, PAGE_SIZE); + size = mpc->length; + early_iounmap(mpc, PAGE_SIZE); + apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); + + return size; +} + /* * Scan the memory blocks for an SMP configuration block. */ @@ -611,12 +624,16 @@ static void __init __get_smp_config(unsi construct_default_ISA_mptable(mpf->feature1); } else if (mpf->physptr) { + struct mpc_table *mpc; + unsigned long size; + size = get_mpc_size(mpf->physptr); + mpc = early_ioremap(mpf->physptr, size); /* * Read the physical hardware table. Anything here will * override the defaults. */ - if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { + if (!smp_read_mpc(mpc, early)) { #ifdef CONFIG_X86_LOCAL_APIC smp_found_config = 0; #endif @@ -624,9 +641,12 @@ static void __init __get_smp_config(unsi "BIOS bug, MP table errors detected!...\n"); printk(KERN_ERR "... disabling SMP support. " "(tell your hw vendor)\n"); + early_iounmap(mpc, size); return; } + early_iounmap(mpc, size); + if (early) return; #ifdef CONFIG_X86_IO_APIC @@ -700,7 +720,7 @@ static int __init smp_scan_config(unsign reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE, BOOTMEM_DEFAULT); if (mpf->physptr) { - unsigned long size = PAGE_SIZE; + unsigned long size = get_mpc_size(mpf->physptr); #ifdef CONFIG_X86_32 /* * We cannot access to MPC table to compute From mingo at elte.hu Mon Mar 2 21:29:18 2009 From: mingo at elte.hu (Ingo Molnar) Date: Mon, 2 Mar 2009 21:29:18 +0100 Subject: [coreboot] [PATCH] x86: ioremap mptable -v2 In-Reply-To: <49AC3C8C.8070702@kernel.org> References: <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> <20090301180420.GA27040@morn.localdomain> <49AB511E.9010507@kernel.org> <20090302101823.GJ20897@elte.hu> <49AC3C8C.8070702@kernel.org> Message-ID: <20090302202918.GA14471@elte.hu> * Yinghai Lu wrote: > V3: according to Ingo, seperate get_mpc_size() No, that was not my suggestion. My suggestion was to separate this whole 'else if' branch: > } else if (mpf->physptr) { > + struct mpc_table *mpc; > + unsigned long size; > > + size = get_mpc_size(mpf->physptr); > + mpc = early_ioremap(mpf->physptr, size); > /* > * Read the physical hardware table. Anything here will > * override the defaults. > */ > - if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { > + if (!smp_read_mpc(mpc, early)) { > #ifdef CONFIG_X86_LOCAL_APIC > smp_found_config = 0; > #endif ... into a helper function - if that improves the code. Your patch does early_ioremap, iounmap then ioremap and iounmap - quite pointlessly. You should resist cleanup suggestions that make the code worse, even if it comes from a maintainer :-) Ingo From yinghai at kernel.org Mon Mar 2 21:46:23 2009 From: yinghai at kernel.org (Yinghai Lu) Date: Mon, 02 Mar 2009 12:46:23 -0800 Subject: [coreboot] [PATCH] x86: ioremap mptable -v2 In-Reply-To: <20090302202918.GA14471@elte.hu> References: <49A1C4AF.9000009@kernel.org> <20090222223226.GA3346@morn.localdomain> <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> <20090301180420.GA27040@morn.localdomain> <49AB511E.9010507@kernel.org> <20090302101823.GJ20897@elte.hu> <49AC3C8C.8070702@kernel.org> <20090302202918.GA14471@elte.hu> Message-ID: <49AC459F.10606@kernel.org> Ingo Molnar wrote: > * Yinghai Lu wrote: > >> V3: according to Ingo, seperate get_mpc_size() > > No, that was not my suggestion. My suggestion was to separate > this whole 'else if' branch: > >> } else if (mpf->physptr) { >> + struct mpc_table *mpc; >> + unsigned long size; >> >> + size = get_mpc_size(mpf->physptr); >> + mpc = early_ioremap(mpf->physptr, size); >> /* >> * Read the physical hardware table. Anything here will >> * override the defaults. >> */ >> - if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { >> + if (!smp_read_mpc(mpc, early)) { >> #ifdef CONFIG_X86_LOCAL_APIC >> smp_found_config = 0; >> #endif > > ... into a helper function - if that improves the code. oh, i missed it > Your patch does early_ioremap, iounmap then ioremap and iounmap - > quite pointlessly. try to get exact mpc size. > > You should resist cleanup suggestions that make the code worse, > even if it comes from a maintainer :-) we could do that later. to make __get_smp_config smaller and readable. YH From mingo at elte.hu Mon Mar 2 21:57:27 2009 From: mingo at elte.hu (Ingo Molnar) Date: Mon, 2 Mar 2009 21:57:27 +0100 Subject: [coreboot] [PATCH] x86: ioremap mptable -v2 In-Reply-To: <49AC459F.10606@kernel.org> References: <20090222225847.GB1649@elte.hu> <49A23EE0.8000102@kernel.org> <20090228234127.GA29964@morn.localdomain> <49A9FC9A.2030707@kernel.org> <20090301180420.GA27040@morn.localdomain> <49AB511E.9010507@kernel.org> <20090302101823.GJ20897@elte.hu> <49AC3C8C.8070702@kernel.org> <20090302202918.GA14471@elte.hu> <49AC459F.10606@kernel.org> Message-ID: <20090302205727.GA20228@elte.hu> * Yinghai Lu wrote: > Ingo Molnar wrote: > > * Yinghai Lu wrote: > > > >> V3: according to Ingo, seperate get_mpc_size() > > > > No, that was not my suggestion. My suggestion was to separate > > this whole 'else if' branch: > > > >> } else if (mpf->physptr) { > >> + struct mpc_table *mpc; > >> + unsigned long size; > >> > >> + size = get_mpc_size(mpf->physptr); > >> + mpc = early_ioremap(mpf->physptr, size); > >> /* > >> * Read the physical hardware table. Anything here will > >> * override the defaults. > >> */ > >> - if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { > >> + if (!smp_read_mpc(mpc, early)) { > >> #ifdef CONFIG_X86_LOCAL_APIC > >> smp_found_config = 0; > >> #endif > > > > ... into a helper function - if that improves the code. > oh, i missed it > > Your patch does early_ioremap, iounmap then ioremap and iounmap - > > quite pointlessly. > try to get exact mpc size. > > > > You should resist cleanup suggestions that make the code worse, > > even if it comes from a maintainer :-) > > we could do that later. to make __get_smp_config smaller and readable. No, do it in two separate patches please: _first_ do the whole cleanup of these functions - on the assumption and expectation that it wont break anything. Then add the early_ioremap() change in a second patch - on top of the cleanup patch. If we do a cleanup _after_ a functional change then we make the feature patch harder to revert and harder to fix as well. We'd always have to 'see through' the cleanup patch when considering breakages caused by the functional patch. Like i suggested in my first reply ;-) Ingo From ronald at zonnet.nl Mon Mar 2 22:36:13 2009 From: ronald at zonnet.nl (Ronald Hoogenboom) Date: Mon, 02 Mar 2009 22:36:13 +0100 Subject: [coreboot] [PATCH] port yabel and vm86 to v2. In-Reply-To: References: Message-ID: <1236029773.2851.8.camel@amd-x2.grundel> Hi, So with this patch, it should be /easy/ to select vm86 instead of emu86 to boot my vga board on my gigabyte m57sli, like it is in v3. What I did: add the line +uses CONFIG_PCI_OPTION_ROM_RUN_VM86 to src/mainboard/gigabyte/m57sli/Options.lb and add the line +option CONFIG_PCI_OPTION_ROM_RUN_VM86=1 to targets/gigabyte/m57sli/Config.lb do a './buildtarget gigabyte/m57sli/Config.lb' and 'make' in targets/gigabyte/m57sli/m57sli. But: gcc -m32 -nostdlib -nostartfiles -static -o coreboot_ram -T /home/ronald/coreboot/src/config/coreboot_ram.ld coreboot_ram.o coreboot_ram.o: In function `__vga_ec_16bit': vm86.c:(.text+0x9eb1): relocation truncated to fit: R_386_16 against `.text' coreboot_ram.o: In function `__vga_ec_real': vm86.c:(.text+0x9ece): relocation truncated to fit: R_386_16 against symbol `__myidt' defined in .text section in coreboot_ram.o coreboot_ram.o: In function `idthandle': vm86.c:(.text+0x9f2d): relocation truncated to fit: R_386_16 against `.text' coreboot_ram.o: In function `__rms_16bit2': vm86.c:(.text+0x9f9c): relocation truncated to fit: R_386_16 against `.text' coreboot_ram.o: In function `__rms_real2': vm86.c:(.text+0x9fb0): relocation truncated to fit: R_386_16 against symbol `__myidt' defined in .text section in coreboot_ram.o coreboot_ram.o: In function `__rms_16bit': vm86.c:(.text+0xa31f): relocation truncated to fit: R_386_16 against `.text' coreboot_ram.o: In function `__rms_real': vm86.c:(.text+0xa338): relocation truncated to fit: R_386_16 against symbol `__myidt' defined in .text section in coreboot_ram.o collect2: ld returned 1 exit status make[1]: *** [coreboot_ram] Error 1 What is still missing here?? Ronald. From mylesgw at gmail.com Mon Mar 2 23:32:24 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 2 Mar 2009 15:32:24 -0700 Subject: [coreboot] SSDT _PPC return outside method body Message-ID: <2831fecf0903021432la2ac505xd4f1121141db91f@mail.gmail.com> Rudolf, In acpigen.c the code that should generate the _PPC method generates code that when disassembled places the return outside the block. Method (_PPC, 0, NotSerialized) { } Return (0x00) I played with it a little, but the best I could get was: Method (_PPC, 0, NotSerialized) { Return (0x00) } Zero Note the extra zero after the block. I think there's an error with the length calculation (the argument to acpigen_patch_len() or the return value of acpigen_write_PPC), but I'm not sure how to fix it. Thanks, Myles From phueper at hueper.net Mon Mar 2 23:34:31 2009 From: phueper at hueper.net (Pattrick Hueper) Date: Mon, 2 Mar 2009 23:34:31 +0100 Subject: [coreboot] r3965 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/include/arch src/config src/devices src/include src/include/cpu/x86 util In-Reply-To: <49aa6081.041abc0a.2c67.ffffd19dSMTPIN_ADDED@mx.google.com> References: <49aa6081.041abc0a.2c67.ffffd19dSMTPIN_ADDED@mx.google.com> Message-ID: Hi, On Sun, Mar 1, 2009 at 11:16 AM, wrote: ... > > +define CONFIG_PCI_OPTION_ROM_RUN_YABEL > + ? ? ? default 0 > + ? ? ? export used > + ? ? ? comment "Use Yabel instead of old bios emulator" > +end > + > +define CONFIG_PCI_OPTION_ROM_RUN_VM86 > + ? ? ? default 0 > + ? ? ? export used > + ? ? ? comment "Use Yabel instead of old bios emulator" > +end > + I just noticed... the second comment should be "Use vm86 instead of old bios emulator", shouldnt it? Patty From r.marek at assembler.cz Mon Mar 2 23:42:02 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 02 Mar 2009 23:42:02 +0100 Subject: [coreboot] SSDT _PPC return outside method body In-Reply-To: <2831fecf0903021432la2ac505xd4f1121141db91f@mail.gmail.com> References: <2831fecf0903021432la2ac505xd4f1121141db91f@mail.gmail.com> Message-ID: <49AC60BA.9090106@assembler.cz> hi, Are you using latest version? I think I fixed that. Oh and it seems I forgot to commit the fix: [coreboot] [PATCH] fix the _PPC method generation Rudolf From svn at coreboot.org Mon Mar 2 23:45:31 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Mon, 2 Mar 2009 23:45:31 +0100 Subject: [coreboot] r3968 - trunk/coreboot-v2/src/arch/i386/boot Message-ID: Author: ruik Date: 2009-03-02 23:45:31 +0100 (Mon, 02 Mar 2009) New Revision: 3968 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpigen.c Log: Small bug somehow slipped there. The method body length is incorrectly computed. The attached patch fixes this. I did not spotted that because the return arg is moved just outside of method and I have overseen the closing } Signed-off-by: Rudolf Marek Acked-by: Peter Stuge Modified: trunk/coreboot-v2/src/arch/i386/boot/acpigen.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpigen.c 2009-03-01 18:05:25 UTC (rev 3967) +++ trunk/coreboot-v2/src/arch/i386/boot/acpigen.c 2009-03-02 22:45:31 UTC (rev 3968) @@ -239,8 +239,10 @@ acpigen_emit_byte(0xa4); /* arg */ len += acpigen_write_byte(nr); + /* add all single bytes */ + len += 3; acpigen_patch_len(len - 1); - return len + 3; + return len; } int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, From r.marek at assembler.cz Mon Mar 2 23:46:58 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 02 Mar 2009 23:46:58 +0100 Subject: [coreboot] SSDT _PPC return outside method body In-Reply-To: <49AC60BA.9090106@assembler.cz> References: <2831fecf0903021432la2ac505xd4f1121141db91f@mail.gmail.com> <49AC60BA.9090106@assembler.cz> Message-ID: <49AC61E2.6080909@assembler.cz> Hi all, Its fixed, Committed revision 3968. I may have more time tomorrow. (to answer the more CPUs PSS states email) Rudolf From r.marek at assembler.cz Mon Mar 2 23:50:15 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 02 Mar 2009 23:50:15 +0100 Subject: [coreboot] [PATCH 2/2] AMD boards to use new Power Now infrastructure In-Reply-To: <2831fecf0902250900yd566b40s1b7f081ef8f1e449@mail.gmail.com> References: <4996C49E.8070303@assembler.cz> <499CD145.3000907@gmx.net> <499D1ACE.5070609@assembler.cz> <2831fecf0902250900yd566b40s1b7f081ef8f1e449@mail.gmail.com> Message-ID: <49AC62A7.1000903@assembler.cz> Myles Watson napsal(a): > On Thu, Feb 19, 2009 at 1:39 AM, Rudolf Marek wrote: >>> And your code shows one processor, the original code shows four >>> processors (I have one single-core CPU). >> I choose to generate the code just for cores which exists. > > I have two dual-core CPUs, and code is only generated for two of them. > I see the for loop with write_pstates_for_core in powernow_acpi.c. > Should there be another loop for packages? Yes but it needs to read new data from the AP CPU (the MSRs and CPUIDs) Dont know if we have funcs like cpuid_on_cpu and msr_on_cpu. > I guess I'm not sure which > two cores are being found by your algorithm. Just BSP processor. It needs to be thought how to do that for more CPUs, perhaps using funcs like above. Rudolf From mylesgw at gmail.com Mon Mar 2 23:52:58 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 2 Mar 2009 15:52:58 -0700 Subject: [coreboot] SSDT _PPC return outside method body In-Reply-To: <49AC61E2.6080909@assembler.cz> References: <2831fecf0903021432la2ac505xd4f1121141db91f@mail.gmail.com> <49AC60BA.9090106@assembler.cz> <49AC61E2.6080909@assembler.cz> Message-ID: <2831fecf0903021452y352d3b60of1f159e66c4bf177@mail.gmail.com> On Mon, Mar 2, 2009 at 3:46 PM, Rudolf Marek wrote: > Hi all, > > Its fixed, > > Committed revision 3968. Thanks Rudolf. Sorry I didn't see the fix earlier. Myles From mylesgw at gmail.com Mon Mar 2 23:57:18 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 2 Mar 2009 15:57:18 -0700 Subject: [coreboot] [PATCH 2/2] AMD boards to use new Power Now infrastructure In-Reply-To: <49AC62A7.1000903@assembler.cz> References: <4996C49E.8070303@assembler.cz> <499CD145.3000907@gmx.net> <499D1ACE.5070609@assembler.cz> <2831fecf0902250900yd566b40s1b7f081ef8f1e449@mail.gmail.com> <49AC62A7.1000903@assembler.cz> Message-ID: <2831fecf0903021457r59f0392dk16f83e3ff7ed9ff0@mail.gmail.com> On Mon, Mar 2, 2009 at 3:50 PM, Rudolf Marek wrote: > Myles Watson napsal(a): >> >> On Thu, Feb 19, 2009 at 1:39 AM, Rudolf Marek >> wrote: >>>> >>>> And your code shows one processor, the original code shows four >>>> processors (I have one single-core CPU). >>> >>> I choose to generate the code just for cores which exists. >> >> I have two dual-core CPUs, and code is only generated for two of them. >> ?I see the for loop with write_pstates_for_core in powernow_acpi.c. >> Should there be another loop for packages? > > Yes but it needs to read new data from the AP CPU (the MSRs and CPUIDs) > Dont know if we have funcs like cpuid_on_cpu and msr_on_cpu. > > >> I guess I'm not sure which >> two cores are being found by your algorithm. > > Just BSP processor. It needs to be thought how to do that for more CPUs, > perhaps using funcs like above. I guess the alternative is to force users to use matched CPUs. Do we already force that for microcode patches? Thanks, Myles From w.de.groot at ai.rug.nl Tue Mar 3 17:18:57 2009 From: w.de.groot at ai.rug.nl (Wouter de Groot) Date: Tue, 03 Mar 2009 17:18:57 +0100 Subject: [coreboot] coreboot on MSI K9AGM3-F Message-ID: <1236097137.6243.44.camel@wouter-laptop> I spoke with carldani in #coreboot about running coreboot on my MSI K9AGM3-F. Details below. The first problem is that the BIOS is soldered to the board. However, there is SPI access[1][2]. I understand the code is not perfect, but should be usable. I'm no expert, but where I can I'd like to help. Page [2] builds an external programmer using a parallel port. Unfortunately, I do not have such a port sitting around. I do have a serial port. I'd be very pleased if someone could help me build a programmer for it. I can't make schematics, but I can solder. At the end of the day, my board needs to be usable. It's not doing anything mission-critical, but I can't make this an eternal project, either. I am willing to invest time and effort, perform tests where I can, provide feedback, that sort of thing. Board details: CPU: AMD Athlon(tm) X2 Dual Core Processor BE-2300 NB: AMD 960V SB: ATI SB600 MB: MSI K9AGM3-F lspci: 00:00.0 Host bridge: ATI Technologies Inc RS690 Host Bridge 00:01.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx) 00:07.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 3) 00:12.0 SATA controller: ATI Technologies Inc SB600 Non-Raid-5 SATA 00:13.0 USB Controller: ATI Technologies Inc SB600 USB (OHCI0) 00:13.1 USB Controller: ATI Technologies Inc SB600 USB (OHCI1) 00:13.2 USB Controller: ATI Technologies Inc SB600 USB (OHCI2) 00:13.3 USB Controller: ATI Technologies Inc SB600 USB (OHCI3) 00:13.4 USB Controller: ATI Technologies Inc SB600 USB (OHCI4) 00:13.5 USB Controller: ATI Technologies Inc SB600 USB Controller (EHCI) 00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 14) 00:14.1 IDE interface: ATI Technologies Inc SB600 IDE 00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia 00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:05.0 VGA compatible controller: ATI Technologies Inc RS690 [Radeon X1200 Series] 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01) 03:02.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) end lspci Super IO: Fintek F71882FG BIOS chip type: SOIC8 (also see [1]) URL: http://global.msi.com.tw/index.php?func=proddesc&prod_no=1346&maincat_no=1 [1] http://img48.imageshack.us/img48/9302/dsc00351lo.jpg [2] http://www.fccps.cz/download/adv/frr/spi/msi_spi.html -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part URL: From c-d.hailfinger.devel.2006 at gmx.net Tue Mar 3 17:37:13 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 03 Mar 2009 17:37:13 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49ABFDFD.7080807@gmx.net> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> Message-ID: <49AD5CB9.1040701@gmx.net> On 02.03.2009 16:40, Carl-Daniel Hailfinger wrote: > On 02.03.2009 16:33, ron minnich wrote: > >> On Mon, Mar 2, 2009 at 7:30 AM, Carl-Daniel Hailfinger >> wrote: >> >> >> >>> AFAIK it has been the case at least since AMD published their 690G/SB600 >>> port, maybe even before that. For a fun time, grep over the tree for >>> pci_cf8_conf1 and you'll see it is not constrained to mainboard code. >>> >>> >> ok, has anyone checked to see if it's the code that determines type >> 1/type 2 access going wrong somehow? >> >> > > Maybe. pci_set_method() is not called on any K8 platform. AFAICS type 1 > is hardcoded there, so pci_set_method should not be necessary in theory. > I don't know whether setting the access method happens early enough for > the mainboard code. > > > >> If so, there's an easy fix :-) >> >> > > Hopefully. Once Ward boots tomorrow with my debug patch, we'll know > where exactly it hangs and probably also why. > http://ward.vandewege.net/coreboot/m2a-vm/m2a-vm-with-fix-printk-format-warning-patch.log Ouch. We hang inside get_pbus. Ward, can you revert src/devices/pci_ops.c and apply this patch? Index: src/devices/pci_ops.c =================================================================== --- src/devices/pci_ops.c (Revision 3967) +++ src/devices/pci_ops.c (Arbeitskopie) @@ -24,11 +24,15 @@ #include #include -static struct bus *get_pbus(device_t dev) +struct bus *get_pbus(device_t dev) { + printk_spew("%s entered\n", __func__); struct bus *pbus = dev->bus; + printk_spew("%s before loop, pbus=%p, pbus->dev=%p, pbus->dev->ops=%p, pbus->children=%p\n", __func__, pbus, pbus ? pbus->dev : 0xdeadbeef, (pbus && pbus->dev) ? pbus->dev->ops : 0xdeadbeef, pbus ? pbus->children: 0xdeadbeef); while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + printk_spew("%s inside loop begin, pbus=%p, pbus->dev=%p, pbus->dev->ops=%p, pbus->children=%p\n", __func__, pbus, pbus ? pbus->dev : 0xdeadbeef, (pbus && pbus->dev) ? pbus->dev->ops : 0xdeadbeef, pbus ? pbus->children: 0xdeadbeef); pbus = pbus->dev->bus; + printk_spew("%s inside loop end, pbus=%p, pbus->dev=%p, pbus->dev->ops=%p, pbus->children=%p\n", __func__, pbus, pbus ? pbus->dev : 0xdeadbeef, (pbus && pbus->dev) ? pbus->dev->ops : 0xdeadbeef, pbus ? pbus->children: 0xdeadbeef); } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { printk_alert("%s Cannot find pci bus operations", dev_path(dev)); Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Tue Mar 3 18:03:27 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 3 Mar 2009 10:03:27 -0700 Subject: [coreboot] [PATCH] filesystem hierarchy in v2 buildsystem In-Reply-To: <49A891DF.2030605@coresystems.de> References: <49A891DF.2030605@coresystems.de> Message-ID: <2831fecf0903030903p3fd1cd79i63a0112f781f8dc8@mail.gmail.com> 2009/2/27 Stefan Reinauer : > See patch. This fixes a very ugly issue in v2. I think we should update make clean to do rm -f $(OBJECTS) or something like that. Right now it doesn't do much since the .o files are in directories. What's the best way? Thanks, Myles From c-d.hailfinger.devel.2006 at gmx.net Tue Mar 3 18:13:16 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 03 Mar 2009 18:13:16 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49AD5CB9.1040701@gmx.net> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> Message-ID: <49AD652C.7070909@gmx.net> On 03.03.2009 17:37, Carl-Daniel Hailfinger wrote: > On 02.03.2009 16:40, Carl-Daniel Hailfinger wrote: > >> On 02.03.2009 16:33, ron minnich wrote: >> >> >>> On Mon, Mar 2, 2009 at 7:30 AM, Carl-Daniel Hailfinger >>> wrote: >>> >>> >>> >>> >>>> AFAIK it has been the case at least since AMD published their 690G/SB600 >>>> port, maybe even before that. For a fun time, grep over the tree for >>>> pci_cf8_conf1 and you'll see it is not constrained to mainboard code. >>>> >>>> >>>> >>> ok, has anyone checked to see if it's the code that determines type >>> 1/type 2 access going wrong somehow? >>> >>> >>> >> Maybe. pci_set_method() is not called on any K8 platform. AFAICS type 1 >> is hardcoded there, so pci_set_method should not be necessary in theory. >> I don't know whether setting the access method happens early enough for >> the mainboard code. >> >> >> >> >>> If so, there's an easy fix :-) >>> >>> >>> >> Hopefully. Once Ward boots tomorrow with my debug patch, we'll know >> where exactly it hangs and probably also why. >> >> > > http://ward.vandewege.net/coreboot/m2a-vm/m2a-vm-with-fix-printk-format-warning-patch.log > > Ouch. We hang inside get_pbus. > Ward, can you revert src/devices/pci_ops.c again and apply this patch? Index: src/devices/pci_ops.c =================================================================== --- src/devices/pci_ops.c (Revision 3967) +++ src/devices/pci_ops.c (Arbeitskopie) @@ -24,11 +24,19 @@ #include #include -static struct bus *get_pbus(device_t dev) +struct bus *get_pbus(device_t dev) { + printk_spew("%s entered\n", __func__); struct bus *pbus = dev->bus; + printk_spew("%s before loop, pbus=%p, pbus->dev=%p, pbus->dev->ops=%p, pbus->children=%p\n", __func__, pbus, pbus ? pbus->dev : 0xdeadbeef, (pbus && pbus->dev) ? pbus->dev->ops : 0xdeadbeef, pbus ? pbus->children: 0xdeadbeef); while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + printk_spew("%s inside loop begin, pbus=%p, pbus->dev=%p, pbus->dev->ops=%p, pbus->children=%p\n", __func__, pbus, pbus ? pbus->dev : 0xdeadbeef, (pbus && pbus->dev) ? pbus->dev->ops : 0xdeadbeef, pbus ? pbus->children: 0xdeadbeef); + if (pbus == pbus->dev->bus) { + printk_alert("%s stuck in endless loop for %s, breaking out\n", __func__, dev_path(dev)); + break; + } pbus = pbus->dev->bus; + printk_spew("%s inside loop end, pbus=%p, pbus->dev=%p, pbus->dev->ops=%p, pbus->children=%p\n", __func__, pbus, pbus ? pbus->dev : 0xdeadbeef, (pbus && pbus->dev) ? pbus->dev->ops : 0xdeadbeef, pbus ? pbus->children: 0xdeadbeef); } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { printk_alert("%s Cannot find pci bus operations", dev_path(dev)); Regards, Carl-Daniel -- http://www.hailfinger.org/ From marcj303 at gmail.com Tue Mar 3 19:22:15 2009 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 3 Mar 2009 11:22:15 -0700 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49AD652C.7070909@gmx.net> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> Message-ID: <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> I think I see the problem. The mainboard.c code is called during the chip_operations enable_dev stage very early before the static tree is setup with the device function pointers. The reason for this is to do chip device setup before the devices are scanned. For example the device may need to be enabled in the southbridge before it will be found in the normal scan or it may need to be hidden etc. If you look at static.c you will see that the .ops = 0 for all the devices. That field gets updated in set_pci_ops() (or other device ops setup functions) which happens later in the device scan, after the chip enable_dev. That is why we need to use the direct access pci functions and not the static tree pointer functions. I think that the fix is to add a comment explaining why you need to use the direct access functions at in the enable_dev function. I hope that was clear. It is a bit easier to understand in V3 where the stages/phases are numbered. Marc From c-d.hailfinger.devel.2006 at gmx.net Tue Mar 3 23:29:25 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 03 Mar 2009 23:29:25 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> Message-ID: <49ADAF45.5050801@gmx.net> On 03.03.2009 19:22, Marc Jones wrote: > I think I see the problem. The mainboard.c code is called during the > chip_operations enable_dev stage very early before the static tree is > setup with the device function pointers. The reason for this is to do > chip device setup before the devices are scanned. For example the > device may need to be enabled in the southbridge before it will be > found in the normal scan or it may need to be hidden etc. > > If you look at static.c you will see that the .ops = 0 for all the > devices. That field gets updated in set_pci_ops() (or other device ops > setup functions) which happens later in the device scan, after the > chip enable_dev. > > That is why we need to use the direct access pci functions and not the > static tree pointer functions. I think that the fix is to add a > comment explaining why you need to use the direct access functions at > in the enable_dev function. > > I hope that was clear. It is a bit easier to understand in V3 where > the stages/phases are numbered. > Thanks. I still want to work around this. Ward, can you please revert src/mainboard/amd/dbm690t/mainboard.c and try this? Index: src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- src/mainboard/amd/dbm690t/mainboard.c (Revision 3967) +++ src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -61,7 +61,7 @@ { u8 byte; - printk_info("enable_onboard_nic.\n"); + printk_info("%s.\n", __func__); /* set index register 0C50h to 13h (miscellaneous control) */ outb(0x13, 0xC50); /* CMIndex */ @@ -87,6 +87,7 @@ byte = inb(0xC52); byte &= ~0x8; outb(byte, 0xC52); + printk_info("%s done.\n", __func__); } /******************************************************** @@ -97,32 +98,47 @@ static void get_ide_dma66() { u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - struct bus pbus; + struct device *sm_dev; + struct device *ide_dev; + struct bus *pbus; + printk_info("%s.\n", __func__); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + printk_info("%s dev_find_slot(0:14.0) returned sm_dev=%p, sm_dev->bus=%p.\n", __func__, sm_dev, sm_dev->bus); - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9); + pbus = dev->bus; + while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + if (pbus == pbus->dev->bus) + break; + pbus = pbus->dev->bus; + } + if (pbus && pbus->dev && pbus->dev->ops) { + printk_info("%s fixing up root bus pci ops\n"); + bus->dev->ops->ops_pci_bus = &pci_cf8_conf1; + } + + printk_info("%s running get_pbus(sm_dev)\n", __func__); + pbus = get_pbus(sm_dev); + printk_info("%s pbus=%p, ops_pci_bus(pbus)=%p, &pci_cf8_conf1=%p.\n", __func__, pbus, ops_pci_bus(pbus), &pci_cf8_conf1); + if (ops_pci_bus(pbus) != &pci_cf8_conf1) + printk_info("%s ops_pci_bus(pbus) and &pci_cf8_conf1 do NOT match! Die?\n", __func__); + //byte = ops_pci_bus(pbus)->read8(pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA9); + //byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA9); + byte = pci_read_config8(sm_dev, 0xA9); + printk_info("%s survived first pci_read_config8\n", __func__); byte |= (1 << 5); /* Set Gpio9 as input */ - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9, byte); + pci_write_config8(sm_dev, 0xA9, byte); + printk_info("%s survived first pci_write_config8\n", __func__); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56); + byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 5) & pci_cf8_conf1. - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, - 0xAA)) + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56, byte); + pci_write_config8(ide_dev, 0x56, byte); + printk_info("%s done.\n", __func__); } /* @@ -133,7 +149,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -156,12 +171,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); @@ -197,12 +209,12 @@ * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -void dbm690t_enable(device_t dev) +void mb_enable(device_t dev) { struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -236,7 +248,7 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ @@ -256,7 +268,7 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); @@ -267,6 +279,6 @@ * CONFIG_CHIP_NAME defined in Option.lb. */ struct chip_operations mainboard_ops = { - CHIP_NAME("AMD DBM690T Mainboard") - .enable_dev = dbm690t_enable, + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = mb_enable, }; Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Tue Mar 3 23:33:54 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 03 Mar 2009 23:33:54 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49ADAF45.5050801@gmx.net> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> <49ADAF45.5050801@gmx.net> Message-ID: <49ADB052.2030405@gmx.net> On 03.03.2009 23:29, Carl-Daniel Hailfinger wrote: > On 03.03.2009 19:22, Marc Jones wrote: > >> I think I see the problem. The mainboard.c code is called during the >> chip_operations enable_dev stage very early before the static tree is >> setup with the device function pointers. The reason for this is to do >> chip device setup before the devices are scanned. For example the >> device may need to be enabled in the southbridge before it will be >> found in the normal scan or it may need to be hidden etc. >> >> If you look at static.c you will see that the .ops = 0 for all the >> devices. That field gets updated in set_pci_ops() (or other device ops >> setup functions) which happens later in the device scan, after the >> chip enable_dev. >> >> That is why we need to use the direct access pci functions and not the >> static tree pointer functions. I think that the fix is to add a >> comment explaining why you need to use the direct access functions at >> in the enable_dev function. >> >> I hope that was clear. It is a bit easier to understand in V3 where >> the stages/phases are numbered. >> >> > > Thanks. I still want to work around this. > > Ward, can you please revert src/mainboard/amd/dbm690t/mainboard.c and > try this? > Argh. I sent the patch too early. Index: src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- src/mainboard/amd/dbm690t/mainboard.c (Revision 3967) +++ src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -61,7 +61,7 @@ { u8 byte; - printk_info("enable_onboard_nic.\n"); + printk_info("%s.\n", __func__); /* set index register 0C50h to 13h (miscellaneous control) */ outb(0x13, 0xC50); /* CMIndex */ @@ -87,6 +87,7 @@ byte = inb(0xC52); byte &= ~0x8; outb(byte, 0xC52); + printk_info("%s done.\n", __func__); } /******************************************************** @@ -97,32 +98,47 @@ static void get_ide_dma66() { u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - struct bus pbus; + struct device *sm_dev; + struct device *ide_dev; + struct bus *pbus; + printk_info("%s.\n", __func__); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + printk_info("%s dev_find_slot(0:14.0) returned sm_dev=%p, sm_dev->bus=%p.\n", __func__, sm_dev, sm_dev->bus); - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9); + pbus = sm_dev->bus; + while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + if (pbus == pbus->dev->bus) + break; + pbus = pbus->dev->bus; + } + if (pbus && pbus->dev && pbus->dev->ops) { + printk_info("%s fixing up root bus pci ops\n", __func__); + pbus->dev->ops->ops_pci_bus = &pci_cf8_conf1; + } + + printk_info("%s running get_pbus(sm_dev)\n", __func__); + pbus = get_pbus(sm_dev); + printk_info("%s pbus=%p, ops_pci_bus(pbus)=%p, &pci_cf8_conf1=%p.\n", __func__, pbus, ops_pci_bus(pbus), &pci_cf8_conf1); + if (ops_pci_bus(pbus) != &pci_cf8_conf1) + printk_info("%s ops_pci_bus(pbus) and &pci_cf8_conf1 do NOT match! Die?\n", __func__); + //byte = ops_pci_bus(pbus)->read8(pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA9); + //byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA9); + byte = pci_read_config8(sm_dev, 0xA9); + printk_info("%s survived first pci_read_config8\n", __func__); byte |= (1 << 5); /* Set Gpio9 as input */ - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9, byte); + pci_write_config8(sm_dev, 0xA9, byte); + printk_info("%s survived first pci_write_config8\n", __func__); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56); + byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 5) & pci_cf8_conf1. - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, - 0xAA)) + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56, byte); + pci_write_config8(ide_dev, 0x56, byte); + printk_info("%s done.\n", __func__); } /* @@ -133,7 +149,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -156,12 +171,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); @@ -197,12 +209,12 @@ * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -void dbm690t_enable(device_t dev) +void mb_enable(device_t dev) { struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -236,7 +248,7 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ @@ -256,7 +268,7 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); @@ -267,6 +279,6 @@ * CONFIG_CHIP_NAME defined in Option.lb. */ struct chip_operations mainboard_ops = { - CHIP_NAME("AMD DBM690T Mainboard") - .enable_dev = dbm690t_enable, + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = mb_enable, }; -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Wed Mar 4 00:36:16 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 04 Mar 2009 00:36:16 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49ADB052.2030405@gmx.net> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> <49ADAF45.5050801@gmx.net> <49ADB052.2030405@gmx.net> Message-ID: <49ADBEF0.1090609@gmx.net> On 03.03.2009 23:33, Carl-Daniel Hailfinger wrote: > On 03.03.2009 23:29, Carl-Daniel Hailfinger wrote: > >> On 03.03.2009 19:22, Marc Jones wrote: >> >> >>> I think I see the problem. The mainboard.c code is called during the >>> chip_operations enable_dev stage very early before the static tree is >>> setup with the device function pointers. The reason for this is to do >>> chip device setup before the devices are scanned. For example the >>> device may need to be enabled in the southbridge before it will be >>> found in the normal scan or it may need to be hidden etc. >>> >>> If you look at static.c you will see that the .ops = 0 for all the >>> devices. That field gets updated in set_pci_ops() (or other device ops >>> setup functions) which happens later in the device scan, after the >>> chip enable_dev. >>> >>> That is why we need to use the direct access pci functions and not the >>> static tree pointer functions. I think that the fix is to add a >>> comment explaining why you need to use the direct access functions at >>> in the enable_dev function. >>> >>> I hope that was clear. It is a bit easier to understand in V3 where >>> the stages/phases are numbered. >>> >>> >>> >> Thanks. I still want to work around this. >> >> Ward, can you please revert src/mainboard/amd/dbm690t/mainboard.c and >> try this? >> >> > > Index: src/mainboard/amd/dbm690t/mainboard.c > =================================================================== > --- src/mainboard/amd/dbm690t/mainboard.c (Revision 3967) > +++ src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) > Ward managed to boot his M2A-VM with this patch. Thanks for your patience, Ward! Boot log is here: http://ward.vandewege.net/coreboot/m2a-vm/m2a-vm-with-fix-printk-format-warning-patch5.log Separate patches will follow. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Wed Mar 4 00:48:35 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 04 Mar 2009 00:48:35 +0100 Subject: [coreboot] [PATCH] Don't loop endlessly in get_pbus Message-ID: <49ADC1D3.4060808@gmx.net> If get_pbus() is called for a device which has no parent/ancestor bus with nonzero PCI bus operations, get_pbus() will get stuck in a silent endless loop. Detect the endless loop and break out with an error message. Such a situation can happen if the device tree is not yet initialized/walked completely. This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was used in early mainboard code for the AMD DBM690T. Instead, the code will now die() with a meaningful error message. Thanks to Ward Vandewege for testing my patches to track down that bug. Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c (Revision 3967) +++ LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c (Arbeitskopie) @@ -28,6 +28,12 @@ { struct bus *pbus = dev->bus; while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + if (pbus == pbus->dev->bus) { + printk_alert("%s in endless loop looking for a parent " + "bus with ops_pci_bus for %s, breaking out\n", + __func__, dev_path(dev)); + break; + } pbus = pbus->dev->bus; } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: linuxbios_get_pbus_fix_silent_hang.diff URL: From svn at coreboot.org Wed Mar 4 01:25:44 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 4 Mar 2009 01:25:44 +0100 Subject: [coreboot] r3969 - trunk/coreboot-v2/src/config Message-ID: Author: stepan Date: 2009-03-04 01:25:44 +0100 (Wed, 04 Mar 2009) New Revision: 3969 Modified: trunk/coreboot-v2/src/config/Config.lb Log: fix make clean as suggested by Myles Watson. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-03-02 22:45:31 UTC (rev 3968) +++ trunk/coreboot-v2/src/config/Config.lb 2009-03-04 00:25:44 UTC (rev 3969) @@ -196,6 +196,8 @@ end makerule clean + action "rm -f $(OBJECTS)" + action "rm -f $(DRIVER)" action "rm -f coreboot.* *~" action "rm -f coreboot" action "rm -f ldscript.ld" From kevin at koconnor.net Wed Mar 4 01:26:42 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Tue, 3 Mar 2009 19:26:42 -0500 Subject: [coreboot] coreboot+seabios+gpxe In-Reply-To: <49ADBB5C.6070302@julianfamily.org> References: <49ADBB5C.6070302@julianfamily.org> Message-ID: <20090304002642.GA32511@morn.localdomain> Hi Joe, I'm CC'ing the coreboot mailing list. On Tue, Mar 03, 2009 at 03:21:00PM -0800, Joe Julian wrote: > I'm attempting to duplicate your results and was wondering about the > OPTIONROM defines you mentioned on the coreboot mailing list: > > #define OPTIONROM_BDF_1 0x0100 > #define OPTIONROM_MEM_1 0xfffc0000 > #define OPTIONROM_BDF_2 0x0048 > #define OPTIONROM_MEM_2 0xfffcf800 > > Where do those addresses come from? The values are where the rom can be found in physical memory, and which PCI device they correspond to. It's now possible to use a helper function when setting the BDF values, so an equivalent of the above is: #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) #define OPTIONROM_MEM_1 0xfffc0000 #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0) #define OPTIONROM_MEM_2 0xfffcf800 To find the PCI addresses, look at the lspci and find the device ids. On my machine they are from: 01:00.0 VGA compatible controller: VIA Technologies, Inc... 00:09.0 Ethernet controller: Realtek Semiconductor Co... For the memory addresses, I have a 256KiB chip, and the first rom is located at the start of the chip - so it is 0x100000000 - 0x40000 = 0xfffc0000. > Do you still load the video bios in coreboot? No - I have SeaBIOS load and execute all the roms. -Kevin From c-d.hailfinger.devel.2006 at gmx.net Wed Mar 4 01:46:53 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 04 Mar 2009 01:46:53 +0100 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> Message-ID: <49ADCF7D.6060700@gmx.net> On 03.03.2009 19:22, Marc Jones wrote: > I think I see the problem. The mainboard.c code is called during the > chip_operations enable_dev stage very early before the static tree is > setup with the device function pointers. The reason for this is to do > chip device setup before the devices are scanned. For example the > device may need to be enabled in the southbridge before it will be > found in the normal scan or it may need to be hidden etc. > > If you look at static.c you will see that the .ops = 0 for all the > devices. That field gets updated in set_pci_ops() (or other device ops > setup functions) which happens later in the device scan, after the > chip enable_dev. > > That is why we need to use the direct access pci functions and not the > static tree pointer functions. I think that the fix is to add a > comment explaining why you need to use the direct access functions at > in the enable_dev function. > To be honest, I prefer a fix which is not an easily overlooked "don't do this" comment. > I hope that was clear. It is a bit easier to understand in V3 where > the stages/phases are numbered. > Thanks for your explanation. A lot (all?) of the DBM690T mainboard setup code does not muck with device visibility or bus setup and could easily be called at a time when the static device tree has been prepared sufficiently well. Until someone can tell me how to call the mainboard specific setup code at a more opportune time, the following bandaid works well enough to boot without problems. Signed-off-by: Carl-Daniel Hailfinger Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Revision 3967) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -89,6 +89,31 @@ outb(byte, 0xC52); } +/* + * This is a totally gross hack to be able to use pci_{read,write}_config* + * early during boot when the device tree is not yet set up completely. + */ +void devicetree_early_fixup(struct device *dev) +{ + struct bus *pbus = dev->bus; + while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + if (pbus == pbus->dev->bus) + break; + pbus = pbus->dev->bus; + } + if (ops_pci_bus(pbus)) { + printk_info("%s not needed\n", __func__); + return; + } + if (pbus && pbus->dev && pbus->dev->ops) { + printk_info("%s fixing up root bus pci ops\n", __func__); + pbus->dev->ops->ops_pci_bus = &pci_cf8_conf1; + return; + } + printk_info("%s failed\n", __func__); + return; +} + /******************************************************** * dbm690t uses SB600 GPIO9 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to @@ -97,32 +122,25 @@ static void get_ide_dma66() { u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - struct bus pbus; + struct device *sm_dev; + struct device *ide_dev; + printk_info("%s.\n", __func__); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + devicetree_early_fixup(sm_dev); - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9); + byte = pci_read_config8(sm_dev, 0xA9); byte |= (1 << 5); /* Set Gpio9 as input */ - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9, byte); + pci_write_config8(sm_dev, 0xA9, byte); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56); + byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 5) & pci_cf8_conf1. - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, - 0xAA)) + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56, byte); + pci_write_config8(ide_dev, 0x56, byte); } /* @@ -133,7 +151,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -156,12 +173,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: linuxbios_asus_m2a-vm_workaround_early_pci.diff URL: From c-d.hailfinger.devel.2006 at gmx.net Wed Mar 4 01:50:25 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 04 Mar 2009 01:50:25 +0100 Subject: [coreboot] [PATCH] Fix printk format warning In-Reply-To: <49AB3746.1030403@gmx.net> References: <49AAD7A7.8040308@gmx.net> <49AAE0F1.9060609@coresystems.de> <49AB3746.1030403@gmx.net> Message-ID: <49ADD051.6000308@gmx.net> On 02.03.2009 02:32, Carl-Daniel Hailfinger wrote: > On 01.03.2009 20:24, Stefan Reinauer wrote: > >> On 01.03.2009 19:44 Uhr, Carl-Daniel Hailfinger wrote: >> >>> Fix printk format warning in amdk8_acpi.c. >>> >>> Signed-off-by: Carl-Daniel Hailfinger >>> >>> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c >>> >>> >> Are you sure this is a current tree? >> > > Yes. For easier tab completion, the v2 trees on my disk are named > LinuxBIOSv2-* and the v3 trees are named corebootv3-* > > >> Acked-by: Stefan Reinauer >> >> > > Thanks! > > I just went on a bugfix frenzy and fixed all printk format warnings > triggered by the AMD 690/SB600 targets and would prefer to commit them > in one go. > This new patch includes the small patch you already acked. > > Signed-off-by: Carl-Daniel Hailfinger > Any reviews? With this patch, the DBM690T and the Pistachio have no more printk format warnings. Regards, Carl-Daniel > Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c (working copy) > @@ -129,7 +129,7 @@ > device_t nb_dev = 0, sb_dev = 0; > int dev_ind; > > - printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); > + printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); > > nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); > if (!nb_dev) { > Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c (working copy) > @@ -203,7 +203,7 @@ > device_t sb_dev; > struct southbridge_amd_rs690_config *cfg = > (struct southbridge_amd_rs690_config *)nb_dev->chip_info; > - printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); > + printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); > > /* init GPP core */ > set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, > Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c (working copy) > @@ -121,7 +121,7 @@ > device_t k8_f0 = 0, k8_f2 = 0; > device_t nb_dev = dev_find_slot(0, 0); > > - printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, > + printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, > nb_dev); > > /* set APERTURE_SIZE, 128M. */ > @@ -417,7 +417,7 @@ > struct southbridge_amd_rs690_config *cfg = > (struct southbridge_amd_rs690_config *)nb_dev->chip_info; > > - printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", > + printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", > nb_dev, dev, port); > > /* step 0, REFCLK_SEL, skip A11 revision */ > Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c (working copy) > @@ -96,7 +96,7 @@ > printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ > printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ > printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ > - printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ > + printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ > > /* Program the 2C to 0x43801002 */ > dword = 0x43801002; > Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c (working copy) > @@ -94,7 +94,7 @@ > /* pci_write_config32(dev, 0xf8, dword); */ > > usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); > - printk_info("usb2_bar0=%x\n", usb2_bar0); > + printk_info("usb2_bar0=%p\n", usb2_bar0); > > /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ > dword = 0x00020F00; > Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c (working copy) > @@ -302,7 +302,7 @@ > return; > > base = (u8 *) ((u32)res->base); > - printk_debug("base = %08x\n", base); > + printk_debug("base = %p\n", base); > codec_mask = codec_detect(base); > > if (codec_mask) { > Index: LinuxBIOSv2-printkformatwarnings/src/devices/device.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/devices/device.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/devices/device.c (working copy) > @@ -358,7 +358,7 @@ > base += size; > > printk_spew( > - "%s %02x * [0x%08Lx - 0x%08Lx] %s\n", > + "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", > dev_path(dev), > resource->index, > resource->base, > Index: LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c (working copy) > @@ -357,7 +357,7 @@ > #endif > } > /* Allocate an msr */ > - printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek); > + printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); > state->range_startk = basek; > state->range_sizek = sizek; > } > Index: LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c (working copy) > @@ -136,7 +136,7 @@ > maxlvt = 4; > > for (j = 1; j <= num_starts; j++) { > - printk_spew("Sending STARTUP #%d to %u.\n", j, apicid); > + printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid); > lapic_read_around(LAPIC_SPIV); > lapic_write(LAPIC_ESR, 0); > lapic_read(LAPIC_ESR); > @@ -239,7 +239,7 @@ > #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" > #endif > if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { > - printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10); > + printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); > die("Can not go on\n"); > } > stack_end -= sizeof(struct cpu_info); > Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c (working copy) > @@ -73,7 +73,7 @@ > addr &= ~15; > > /* This table must be betweeen 0xf0000 & 0x100000 */ > - printk_info("Writing IRQ routing tables to 0x%x...", addr); > + printk_info("Writing IRQ routing tables to 0x%lx...", addr); > > pirq = (void *)(addr); > v = (u8 *) (addr); > Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c (working copy) > @@ -255,7 +255,7 @@ > ((acpi_header_t *) AmlCode)->length); > > current += dsdt->length; > - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); > + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); > /* FADT */ > printk_debug("ACPI: * FADT\n"); > fadt = (acpi_fadt_t *) current; > Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c (working copy) > @@ -61,7 +61,7 @@ > { > u8 byte; > > - printk_info("enable_onboard_nic.\n"); > + printk_info("%s.\n", __func__); > > /* enable GPM8 output */ > byte = pm_ioread(0x95); > @@ -274,7 +274,7 @@ > struct mainboard_config *mainboard = > (struct mainboard_config *)dev->chip_info; > > - printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev); > + printk_info("Mainboard Pistachio Enable. dev=0x%p\n", dev); > > #if (CONFIG_GFXUMA == 1) > msr_t msr, msr2; > @@ -308,7 +308,7 @@ > } > > uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ > - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", > + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", > __func__, uma_memory_size, uma_memory_base); > > /* TODO: TOP_MEM2 */ > @@ -328,7 +328,7 @@ > * in some circumstances we want the memory mentioned as reserved. > */ > #if (CONFIG_GFXUMA == 1) > - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", > + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", > uma_memory_base, uma_memory_size); > lb_add_memory_range(mem, LB_MEM_RESERVED, > uma_memory_base, uma_memory_size); > Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c (working copy) > @@ -73,7 +73,7 @@ > addr &= ~15; > > /* This table must be betweeen 0xf0000 & 0x100000 */ > - printk_info("Writing IRQ routing tables to 0x%x...", addr); > + printk_info("Writing IRQ routing tables to 0x%lx...", addr); > > pirq = (void *)(addr); > v = (u8 *) (addr); > Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c (working copy) > @@ -254,7 +254,7 @@ > memcpy((void *)dsdt, (void *)AmlCode, > ((acpi_header_t *) AmlCode)->length); > current += dsdt->length; > - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); > + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); > /* FADT */ > printk_debug("ACPI: * FADT\n"); > fadt = (acpi_fadt_t *) current; > Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c (working copy) > @@ -61,7 +61,7 @@ > { > u8 byte; > > - printk_info("enable_onboard_nic.\n"); > + printk_info("%s.\n", __func__); > > /* set index register 0C50h to 13h (miscellaneous control) */ > outb(0x13, 0xC50); /* CMIndex */ > @@ -202,7 +202,7 @@ > struct mainboard_config *mainboard = > (struct mainboard_config *)dev->chip_info; > > - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); > + printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev); > > #if (CONFIG_GFXUMA == 1) > msr_t msr, msr2; > @@ -236,7 +236,7 @@ > } > > uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ > - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", > + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", > __func__, uma_memory_size, uma_memory_base); > > /* TODO: TOP_MEM2 */ > @@ -256,7 +256,7 @@ > * in some circumstances we want the memory mentioned as reserved. > */ > #if (CONFIG_GFXUMA == 1) > - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", > + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", > uma_memory_base, uma_memory_size); > lb_add_memory_range(mem, LB_MEM_RESERVED, > uma_memory_base, uma_memory_size); > Index: LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c (working copy) > @@ -27,7 +27,7 @@ > { > void *p; > > - MALLOCDBG(("%s Enter, size %d, free_mem_ptr %p\n", __func__, size, free_mem_ptr)); > + MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr)); > if (size < 0) > die("Error! malloc: Size < 0"); > if (free_mem_ptr <= 0) > Index: LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c (working copy) > @@ -128,7 +128,7 @@ > basek = resk(res->base); > sizek = resk(res->size); > > - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", > + printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", > dev_path(dev), res->index, basek, sizek); > /* > * 0-640K must be on node 0 > Index: LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c > =================================================================== > --- LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c (revision 3967) > +++ LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c (working copy) > @@ -473,7 +473,7 @@ > limit |= (nodeid & 7); > > if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { > - printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", > + printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", > __func__, dev_path(dev), link); > base |= PCI_IO_BASE_VGA_EN; > } > > > -- http://www.hailfinger.org/ From stepan at coresystems.de Wed Mar 4 01:52:15 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 04 Mar 2009 01:52:15 +0100 Subject: [coreboot] coreboot+seabios+gpxe In-Reply-To: <20090304002642.GA32511@morn.localdomain> References: <49ADBB5C.6070302@julianfamily.org> <20090304002642.GA32511@morn.localdomain> Message-ID: <49ADD0BF.6030502@coresystems.de> Kevin O'Connor wrote: > #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) > #define OPTIONROM_MEM_1 0xfffc0000 > #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0) > #define OPTIONROM_MEM_2 0xfffcf800 > Hi, Kevin, the bdf notion for matching option roms might be critical, as on k8 bus numbers can vary a lot. Could we instead just keep a list of addresses and have SeaBIOS match the vendor IDs from PCI devices with those in the Option ROMs? That way we wouldn't have to worry. I'll gladly send a patch if you see no obstacles in changing the behavior. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From stepan at coresystems.de Wed Mar 4 01:54:03 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 04 Mar 2009 01:54:03 +0100 Subject: [coreboot] [PATCH] Fix printk format warning In-Reply-To: <49ADD051.6000308@gmx.net> References: <49AAD7A7.8040308@gmx.net> <49AAE0F1.9060609@coresystems.de> <49AB3746.1030403@gmx.net> <49ADD051.6000308@gmx.net> Message-ID: <49ADD12B.1040600@coresystems.de> Carl-Daniel Hailfinger wrote: > On 02.03.2009 02:32, Carl-Daniel Hailfinger wrote: > >> On 01.03.2009 20:24, Stefan Reinauer wrote: >> >> >>> On 01.03.2009 19:44 Uhr, Carl-Daniel Hailfinger wrote: >>> >>> >>>> Fix printk format warning in amdk8_acpi.c. >>>> >>>> Signed-off-by: Carl-Daniel Hailfinger >>>> >>>> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c >>>> >>>> >>>> >>> Are you sure this is a current tree? >>> >>> >> Yes. For easier tab completion, the v2 trees on my disk are named >> LinuxBIOSv2-* and the v3 trees are named corebootv3-* >> >> >> >>> Acked-by: Stefan Reinauer >>> >>> >>> >> Thanks! >> >> I just went on a bugfix frenzy and fixed all printk format warnings >> triggered by the AMD 690/SB600 targets and would prefer to commit them >> in one go. >> This new patch includes the small patch you already acked. >> >> Signed-off-by: Carl-Daniel Hailfinger >> >> > > Any reviews? > With this patch, the DBM690T and the Pistachio have no more printk > format warnings. Sure, go ahead. Acked-by: Stefan Reinauer >> Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690.c (working copy) >> @@ -129,7 +129,7 @@ >> device_t nb_dev = 0, sb_dev = 0; >> int dev_ind; >> >> - printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); >> + printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); >> >> nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); >> if (!nb_dev) { >> Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_pcie.c (working copy) >> @@ -203,7 +203,7 @@ >> device_t sb_dev; >> struct southbridge_amd_rs690_config *cfg = >> (struct southbridge_amd_rs690_config *)nb_dev->chip_info; >> - printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); >> + printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); >> >> /* init GPP core */ >> set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, >> Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/rs690/rs690_gfx.c (working copy) >> @@ -121,7 +121,7 @@ >> device_t k8_f0 = 0, k8_f2 = 0; >> device_t nb_dev = dev_find_slot(0, 0); >> >> - printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, >> + printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, >> nb_dev); >> >> /* set APERTURE_SIZE, 128M. */ >> @@ -417,7 +417,7 @@ >> struct southbridge_amd_rs690_config *cfg = >> (struct southbridge_amd_rs690_config *)nb_dev->chip_info; >> >> - printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", >> + printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", >> nb_dev, dev, port); >> >> /* step 0, REFCLK_SEL, skip A11 revision */ >> Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_sata.c (working copy) >> @@ -96,7 +96,7 @@ >> printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ >> printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ >> printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ >> - printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ >> + printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ >> >> /* Program the 2C to 0x43801002 */ >> dword = 0x43801002; >> Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_usb.c (working copy) >> @@ -94,7 +94,7 @@ >> /* pci_write_config32(dev, 0xf8, dword); */ >> >> usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); >> - printk_info("usb2_bar0=%x\n", usb2_bar0); >> + printk_info("usb2_bar0=%p\n", usb2_bar0); >> >> /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ >> dword = 0x00020F00; >> Index: LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/southbridge/amd/sb600/sb600_hda.c (working copy) >> @@ -302,7 +302,7 @@ >> return; >> >> base = (u8 *) ((u32)res->base); >> - printk_debug("base = %08x\n", base); >> + printk_debug("base = %p\n", base); >> codec_mask = codec_detect(base); >> >> if (codec_mask) { >> Index: LinuxBIOSv2-printkformatwarnings/src/devices/device.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/devices/device.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/devices/device.c (working copy) >> @@ -358,7 +358,7 @@ >> base += size; >> >> printk_spew( >> - "%s %02x * [0x%08Lx - 0x%08Lx] %s\n", >> + "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", >> dev_path(dev), >> resource->index, >> resource->base, >> Index: LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/cpu/x86/mtrr/mtrr.c (working copy) >> @@ -357,7 +357,7 @@ >> #endif >> } >> /* Allocate an msr */ >> - printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek); >> + printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); >> state->range_startk = basek; >> state->range_sizek = sizek; >> } >> Index: LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/cpu/x86/lapic/lapic_cpu_init.c (working copy) >> @@ -136,7 +136,7 @@ >> maxlvt = 4; >> >> for (j = 1; j <= num_starts; j++) { >> - printk_spew("Sending STARTUP #%d to %u.\n", j, apicid); >> + printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid); >> lapic_read_around(LAPIC_SPIV); >> lapic_write(LAPIC_ESR, 0); >> lapic_read(LAPIC_ESR); >> @@ -239,7 +239,7 @@ >> #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" >> #endif >> if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { >> - printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10); >> + printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); >> die("Can not go on\n"); >> } >> stack_end -= sizeof(struct cpu_info); >> Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/irq_tables.c (working copy) >> @@ -73,7 +73,7 @@ >> addr &= ~15; >> >> /* This table must be betweeen 0xf0000 & 0x100000 */ >> - printk_info("Writing IRQ routing tables to 0x%x...", addr); >> + printk_info("Writing IRQ routing tables to 0x%lx...", addr); >> >> pirq = (void *)(addr); >> v = (u8 *) (addr); >> Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/acpi_tables.c (working copy) >> @@ -255,7 +255,7 @@ >> ((acpi_header_t *) AmlCode)->length); >> >> current += dsdt->length; >> - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); >> + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); >> /* FADT */ >> printk_debug("ACPI: * FADT\n"); >> fadt = (acpi_fadt_t *) current; >> Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/pistachio/mainboard.c (working copy) >> @@ -61,7 +61,7 @@ >> { >> u8 byte; >> >> - printk_info("enable_onboard_nic.\n"); >> + printk_info("%s.\n", __func__); >> >> /* enable GPM8 output */ >> byte = pm_ioread(0x95); >> @@ -274,7 +274,7 @@ >> struct mainboard_config *mainboard = >> (struct mainboard_config *)dev->chip_info; >> >> - printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev); >> + printk_info("Mainboard Pistachio Enable. dev=0x%p\n", dev); >> >> #if (CONFIG_GFXUMA == 1) >> msr_t msr, msr2; >> @@ -308,7 +308,7 @@ >> } >> >> uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ >> - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", >> + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", >> __func__, uma_memory_size, uma_memory_base); >> >> /* TODO: TOP_MEM2 */ >> @@ -328,7 +328,7 @@ >> * in some circumstances we want the memory mentioned as reserved. >> */ >> #if (CONFIG_GFXUMA == 1) >> - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", >> + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", >> uma_memory_base, uma_memory_size); >> lb_add_memory_range(mem, LB_MEM_RESERVED, >> uma_memory_base, uma_memory_size); >> Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/irq_tables.c (working copy) >> @@ -73,7 +73,7 @@ >> addr &= ~15; >> >> /* This table must be betweeen 0xf0000 & 0x100000 */ >> - printk_info("Writing IRQ routing tables to 0x%x...", addr); >> + printk_info("Writing IRQ routing tables to 0x%lx...", addr); >> >> pirq = (void *)(addr); >> v = (u8 *) (addr); >> Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/acpi_tables.c (working copy) >> @@ -254,7 +254,7 @@ >> memcpy((void *)dsdt, (void *)AmlCode, >> ((acpi_header_t *) AmlCode)->length); >> current += dsdt->length; >> - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); >> + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); >> /* FADT */ >> printk_debug("ACPI: * FADT\n"); >> fadt = (acpi_fadt_t *) current; >> Index: LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/mainboard/amd/dbm690t/mainboard.c (working copy) >> @@ -61,7 +61,7 @@ >> { >> u8 byte; >> >> - printk_info("enable_onboard_nic.\n"); >> + printk_info("%s.\n", __func__); >> >> /* set index register 0C50h to 13h (miscellaneous control) */ >> outb(0x13, 0xC50); /* CMIndex */ >> @@ -202,7 +202,7 @@ >> struct mainboard_config *mainboard = >> (struct mainboard_config *)dev->chip_info; >> >> - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); >> + printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev); >> >> #if (CONFIG_GFXUMA == 1) >> msr_t msr, msr2; >> @@ -236,7 +236,7 @@ >> } >> >> uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ >> - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", >> + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", >> __func__, uma_memory_size, uma_memory_base); >> >> /* TODO: TOP_MEM2 */ >> @@ -256,7 +256,7 @@ >> * in some circumstances we want the memory mentioned as reserved. >> */ >> #if (CONFIG_GFXUMA == 1) >> - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", >> + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", >> uma_memory_base, uma_memory_size); >> lb_add_memory_range(mem, LB_MEM_RESERVED, >> uma_memory_base, uma_memory_size); >> Index: LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/lib/malloc.c (working copy) >> @@ -27,7 +27,7 @@ >> { >> void *p; >> >> - MALLOCDBG(("%s Enter, size %d, free_mem_ptr %p\n", __func__, size, free_mem_ptr)); >> + MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr)); >> if (size < 0) >> die("Error! malloc: Size < 0"); >> if (free_mem_ptr <= 0) >> Index: LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/amdk8_acpi.c (working copy) >> @@ -128,7 +128,7 @@ >> basek = resk(res->base); >> sizek = resk(res->size); >> >> - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", >> + printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", >> dev_path(dev), res->index, basek, sizek); >> /* >> * 0-640K must be on node 0 >> Index: LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c >> =================================================================== >> --- LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c (revision 3967) >> +++ LinuxBIOSv2-printkformatwarnings/src/northbridge/amd/amdk8/northbridge.c (working copy) >> @@ -473,7 +473,7 @@ >> limit |= (nodeid & 7); >> >> if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { >> - printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", >> + printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", >> __func__, dev_path(dev), link); >> base |= PCI_IO_BASE_VGA_EN; >> } >> >> >> >> > > > -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 249 bytes Desc: OpenPGP digital signature URL: From rminnich at gmail.com Wed Mar 4 01:57:53 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 3 Mar 2009 16:57:53 -0800 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <49ADCF7D.6060700@gmx.net> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> <49ADCF7D.6060700@gmx.net> Message-ID: <13426df10903031657p4986d276o4c518e6e2861a342@mail.gmail.com> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Revision 3967) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -89,6 +89,31 @@ outb(byte, 0xC52); } +/* + * This is a totally gross hack to be able to use pci_{read,write}_config* + * early during boot when the device tree is not yet set up completely. + */ +void devicetree_early_fixup(struct device *dev) +{ + struct bus *pbus = dev->bus; + while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + if (pbus == pbus->dev->bus) + break; + pbus = pbus->dev->bus; + } + if (ops_pci_bus(pbus)) { + printk_info("%s not needed\n", __func__); + return; + } + if (pbus && pbus->dev && pbus->dev->ops) { + printk_info("%s fixing up root bus pci ops\n", __func__); + pbus->dev->ops->ops_pci_bus = &pci_cf8_conf1; + return; + } + printk_info("%s failed\n", __func__); + return; +} There has to be a better way to do this than a per-mainboard fix. ron From svn at coreboot.org Wed Mar 4 02:06:41 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 4 Mar 2009 02:06:41 +0100 Subject: [coreboot] r3970 - in trunk/coreboot-v2/src: cpu/x86/lapic cpu/x86/mtrr devices lib mainboard/amd/dbm690t mainboard/amd/pistachio northbridge/amd/amdk8 southbridge/amd/rs690 southbridge/amd/sb600 Message-ID: Author: hailfinger Date: 2009-03-04 02:06:41 +0100 (Wed, 04 Mar 2009) New Revision: 3970 Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c trunk/coreboot-v2/src/devices/device.c trunk/coreboot-v2/src/lib/malloc.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c trunk/coreboot-v2/src/mainboard/amd/pistachio/irq_tables.c trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_usb.c Log: I just went on a bugfix frenzy and fixed all printk format warnings triggered by the AMD 690/SB600 targets. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -136,7 +136,7 @@ maxlvt = 4; for (j = 1; j <= num_starts; j++) { - printk_spew("Sending STARTUP #%d to %u.\n", j, apicid); + printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid); lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); lapic_read(LAPIC_ESR); @@ -239,7 +239,7 @@ #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" #endif if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { - printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10); + printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); die("Can not go on\n"); } stack_end -= sizeof(struct cpu_info); Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -357,7 +357,7 @@ #endif } /* Allocate an msr */ - printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek); + printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); state->range_startk = basek; state->range_sizek = sizek; } Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/devices/device.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -358,7 +358,7 @@ base += size; printk_spew( - "%s %02x * [0x%08Lx - 0x%08Lx] %s\n", + "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", dev_path(dev), resource->index, resource->base, Modified: trunk/coreboot-v2/src/lib/malloc.c =================================================================== --- trunk/coreboot-v2/src/lib/malloc.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/lib/malloc.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -27,7 +27,7 @@ { void *p; - MALLOCDBG(("%s Enter, size %d, free_mem_ptr %p\n", __func__, size, free_mem_ptr)); + MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr)); if (size < 0) die("Error! malloc: Size < 0"); if (free_mem_ptr <= 0) Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -254,7 +254,7 @@ memcpy((void *)dsdt, (void *)AmlCode, ((acpi_header_t *) AmlCode)->length); current += dsdt->length; - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); /* FADT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -73,7 +73,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (u8 *) (addr); Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -61,7 +61,7 @@ { u8 byte; - printk_info("enable_onboard_nic.\n"); + printk_info("%s.\n", __func__); /* set index register 0C50h to 13h (miscellaneous control) */ outb(0x13, 0xC50); /* CMIndex */ @@ -202,7 +202,7 @@ struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); + printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -236,7 +236,7 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ @@ -256,7 +256,7 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -255,7 +255,7 @@ ((acpi_header_t *) AmlCode)->length); current += dsdt->length; - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); /* FADT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/irq_tables.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/irq_tables.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -73,7 +73,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (u8 *) (addr); Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -61,7 +61,7 @@ { u8 byte; - printk_info("enable_onboard_nic.\n"); + printk_info("%s.\n", __func__); /* enable GPM8 output */ byte = pm_ioread(0x95); @@ -274,7 +274,7 @@ struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev); + printk_info("Mainboard Pistachio Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -308,7 +308,7 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ @@ -328,7 +328,7 @@ * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -128,7 +128,7 @@ basek = resk(res->base); sizek = resk(res->size); - printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", + printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", dev_path(dev), res->index, basek, sizek); /* * 0-640K must be on node 0 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -473,7 +473,7 @@ limit |= (nodeid & 7); if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", + printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", __func__, dev_path(dev), link); base |= PCI_IO_BASE_VGA_EN; } Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -129,7 +129,7 @@ device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -121,7 +121,7 @@ device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); - printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, + printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, nb_dev); /* set APERTURE_SIZE, 128M. */ @@ -417,7 +417,7 @@ struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", + printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* step 0, REFCLK_SEL, skip A11 revision */ Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -203,7 +203,7 @@ device_t sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); + printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); /* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_hda.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -302,7 +302,7 @@ return; base = (u8 *) ((u32)res->base); - printk_debug("base = %08x\n", base); + printk_debug("base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sata.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -96,7 +96,7 @@ printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ + printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_usb.c 2009-03-04 00:25:44 UTC (rev 3969) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_usb.c 2009-03-04 01:06:41 UTC (rev 3970) @@ -94,7 +94,7 @@ /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%x\n", usb2_bar0); + printk_info("usb2_bar0=%p\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; From c-d.hailfinger.devel.2006 at gmx.net Wed Mar 4 02:08:07 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 04 Mar 2009 02:08:07 +0100 Subject: [coreboot] [PATCH] Fix printk format warning In-Reply-To: <49ADD12B.1040600@coresystems.de> References: <49AAD7A7.8040308@gmx.net> <49AAE0F1.9060609@coresystems.de> <49AB3746.1030403@gmx.net> <49ADD051.6000308@gmx.net> <49ADD12B.1040600@coresystems.de> Message-ID: <49ADD477.5080907@gmx.net> On 04.03.2009 01:54, Stefan Reinauer wrote: > Carl-Daniel Hailfinger wrote: > >> On 02.03.2009 02:32, Carl-Daniel Hailfinger wrote: >> >> >>> On 01.03.2009 20:24, Stefan Reinauer wrote: >>> >>> >>> >>>> On 01.03.2009 19:44 Uhr, Carl-Daniel Hailfinger wrote: >>>> >>>> >>>> >>>>> Fix printk format warning in amdk8_acpi.c. >>>>> >>>>> Signed-off-by: Carl-Daniel Hailfinger >>>>> >>>>> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/amdk8_acpi.c >>>>> >>>>> >>>>> >>>>> >>>> Are you sure this is a current tree? >>>> >>>> >>>> >>> Yes. For easier tab completion, the v2 trees on my disk are named >>> LinuxBIOSv2-* and the v3 trees are named corebootv3-* >>> >>> >>> >>> >>>> Acked-by: Stefan Reinauer >>>> >>>> >>>> >>>> >>> Thanks! >>> >>> I just went on a bugfix frenzy and fixed all printk format warnings >>> triggered by the AMD 690/SB600 targets and would prefer to commit them >>> in one go. >>> This new patch includes the small patch you already acked. >>> >>> Signed-off-by: Carl-Daniel Hailfinger >>> >>> >>> >> Any reviews? >> With this patch, the DBM690T and the Pistachio have no more printk >> format warnings. >> > > Sure, go ahead. > > Acked-by: Stefan Reinauer > Thanks, committed in r3970. Regards, Carl-Daniel -- http://www.hailfinger.org/ From kevin at koconnor.net Wed Mar 4 02:22:45 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Tue, 3 Mar 2009 20:22:45 -0500 Subject: [coreboot] coreboot+seabios+gpxe In-Reply-To: <49ADD0BF.6030502@coresystems.de> References: <49ADBB5C.6070302@julianfamily.org> <20090304002642.GA32511@morn.localdomain> <49ADD0BF.6030502@coresystems.de> Message-ID: <20090304012245.GA3883@morn.localdomain> Hi Stefan, On Wed, Mar 04, 2009 at 01:52:15AM +0100, Stefan Reinauer wrote: > Kevin O'Connor wrote: > > #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) > > #define OPTIONROM_MEM_1 0xfffc0000 > > #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0) > > #define OPTIONROM_MEM_2 0xfffcf800 > > > Hi, Kevin, > > the bdf notion for matching option roms might be critical, as on k8 bus > numbers can vary a lot. > Could we instead just keep a list of addresses and have SeaBIOS match > the vendor IDs from PCI devices with those in the Option ROMs? That way > we wouldn't have to worry. I'll gladly send a patch if you see no > obstacles in changing the behavior. Are you suggesting that we define OPTIONROM_DEVID_1 (ie, vendor/device id) instead of OPTIONROM_BDF_1? Or, are you suggesting that SeaBIOS scan the option rom in memory and attempt to locate the PCI ids it supports? The latter seems interesting, but I think it may be difficult to implement efficiently. Otherwise, I don't have any objections. -Kevin From lostdays_15 at hotmail.com Wed Mar 4 11:04:58 2009 From: lostdays_15 at hotmail.com (wei yang) Date: Wed, 4 Mar 2009 10:04:58 +0000 Subject: [coreboot] The VGA rom doesn't work correctly on the coreboot-V2 version for Intel/Truxton platform. Message-ID: I have a intel/Truxtion board and would like to try the coreboot on it. By now, I have successfully built the coreboot for Truxtion with filo payload. without VGA, it can work through the serial port. However, when I used the add-on VGA card, it firstly hang in the VGA Option ROM. After hard debug( the emulator debug is really hard for me, since I can't directly track the OptionROM code I running now), I found the issue. The OptionROM will check the System Mode Flag(0xffffe), if it is not the 0xfc, it will hang. However, the coreboot doesn't touch the 0xffffe address. May it is a bug of coreboot. after fix this issue, the screen can be turn on, but unfortunately, the screen is chaotic. I changed another add-on card and got the same result. Any idea on it? by the way, the add-on VGA card I used is Matorx G550. Thanks _________________________________________________________________ More than messages?check out the rest of the Windows Live?. http://www.microsoft.com/windows/windowslive/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From lostdays_15 at hotmail.com Wed Mar 4 11:15:21 2009 From: lostdays_15 at hotmail.com (wei yang) Date: Wed, 4 Mar 2009 10:15:21 +0000 Subject: [coreboot] the seabios reboot in the post process Message-ID: When I use the seabios as the payload, I got a strange issue. In the seabios flow: Post->timer_setup->rtc_updating->inb_cmos function when run the inb_cmos, it will reboot on the inb operation. inb_cmos disassemables to fllowing: out 0x70, value in value, 0x71. ----> run here to make the reboot happen. 0x70 is the CMOS index port, 0x71 is the CMOS data port. I suspect the "in value, 0x71" operation causes a exception and the seabios doesn't have real IDT, so it then make the reboot. but why it cause the exception is a question for me? since IO port 0x70 also reponsible for the NMI enble/disable, is it caused the error? any one has some comments? thanks _________________________________________________________________ News, entertainment and everything you care about at Live.com. Get it now! http://www.live.com/getstarted.aspx -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Wed Mar 4 11:54:42 2009 From: svn at coreboot.org (coreboot) Date: Wed, 04 Mar 2009 10:54:42 -0000 Subject: [coreboot] #123: layout file Message-ID: <051.68f0f66a0b6d32d616e7c9eb7def71b5@coreboot.org> #123: layout file -------------------------------------+-------------------------------------- Reporter: vivanov@? | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: v2 Keywords: layout address offset | Dependencies: Patchstatus: there is no patch | -------------------------------------+-------------------------------------- Hello, I am trying to update the BIOS "ST M50FW080" and get the following incomprehensibility - layout file works in a strange way 1) saved the current BIOS {{{ $ flashrom --read flash18_saved.rom }}} 2) then I filled first 512K of this file with zeros (it is needed because new BIOS will have 512K size) 3) then I created rom.layout file to use the normal image only: {{{ 00000000:0007ffff stuff 00080000:000fffff normal }}} 4) and started to upgrade BIOS {{{ $ flashrom --write --layout rom.layout --image flash18_saved.rom }}} And get the following: {{{ Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom at coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED '''0007 at address: 0x00070000DONE BLOCK 0x70000''' 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED }}} '''Next''' I changed the rom.layout file like follows: {{{ # cat rom.layout 00000000:00080000 stuff 00080000:000fffff normal }}} and get the '''right''' behaviour: {{{ # flashrom --write --layout rom.layout --image normal --verify flash18_saved.rom Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom at coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED 0007 at address: 0x00070000SKIPPED 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED Verifying flash... VERIFIED. }}} Please explain me which rom layout I should use to update the last 512K of 1M BIOS? -- Ticket URL: coreboot From joe at settoplinux.org Wed Mar 4 13:35:20 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 07:35:20 -0500 Subject: [coreboot] #123: layout file In-Reply-To: <051.68f0f66a0b6d32d616e7c9eb7def71b5@coreboot.org> References: <051.68f0f66a0b6d32d616e7c9eb7def71b5@coreboot.org> Message-ID: <6692b7be58562e5e48100a4f0f2c3306@imap.1and1.com> On Wed, 04 Mar 2009 10:54:42 -0000, "coreboot" wrote: > #123: layout file > -------------------------------------+-------------------------------------- > Reporter: vivanov@? | Owner: somebody > Type: defect | Status: new > Priority: major | Milestone: flashrom v1.0 > Component: flashrom | Version: v2 > Keywords: layout address offset | Dependencies: > Patchstatus: there is no patch | > -------------------------------------+-------------------------------------- > Hello, > > I am trying to update the BIOS "ST M50FW080" and get the following > incomprehensibility - layout file works in a strange way > 1) saved the current BIOS > > {{{ > $ flashrom --read flash18_saved.rom > }}} > > 2) then I filled first 512K of this file with zeros (it is needed > because > new BIOS will have 512K size) > 3) then I created rom.layout file to use the normal image only: > > {{{ > 00000000:0007ffff stuff > 00080000:000fffff normal > }}} > > 4) and started to upgrade BIOS > > {{{ > $ flashrom --write --layout rom.layout --image flash18_saved.rom > }}} > > And get the following: > > {{{ > Looking for "normal"... found. > Calibrating delay loop... OK. > No coreboot table found. > Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. > Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. > === > This flash part has status UNTESTED for operations: PROBE READ ERASE > WRITE > Please email a report to flashrom at coreboot.org if any of the above > operations > work correctly for you with this flash part. Please include the full > output > from the program, including chipset found. Thank you for your help! > === > Flash image seems to be a legacy BIOS. Disabling checks. > Programming page: > 0000 at address: 0x00000000SKIPPED > 0001 at address: 0x00010000SKIPPED > 0002 at address: 0x00020000SKIPPED > 0003 at address: 0x00030000SKIPPED > 0004 at address: 0x00040000SKIPPED > 0005 at address: 0x00050000SKIPPED > 0006 at address: 0x00060000SKIPPED > '''0007 at address: 0x00070000DONE BLOCK 0x70000''' > 0008 at address: 0x00080000SKIPPED > 0009 at address: 0x00090000SKIPPED > 0010 at address: 0x000a0000SKIPPED > 0011 at address: 0x000b0000SKIPPED > 0012 at address: 0x000c0000SKIPPED > 0013 at address: 0x000d0000SKIPPED > 0014 at address: 0x000e0000SKIPPED > 0015 at address: 0x000f0000SKIPPED > }}} > > '''Next''' > > I changed the rom.layout file like follows: > > {{{ > # cat rom.layout > 00000000:00080000 stuff > 00080000:000fffff normal > }}} > > and get the '''right''' behaviour: > > {{{ > # flashrom --write --layout rom.layout --image normal --verify > flash18_saved.rom > Looking for "normal"... found. > Calibrating delay loop... OK. > No coreboot table found. > Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. > Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. > === > This flash part has status UNTESTED for operations: PROBE READ ERASE > WRITE > Please email a report to flashrom at coreboot.org if any of the above > operations > work correctly for you with this flash part. Please include the full > output > from the program, including chipset found. Thank you for your help! > === > Flash image seems to be a legacy BIOS. Disabling checks. > Programming page: > 0000 at address: 0x00000000SKIPPED > 0001 at address: 0x00010000SKIPPED > 0002 at address: 0x00020000SKIPPED > 0003 at address: 0x00030000SKIPPED > 0004 at address: 0x00040000SKIPPED > 0005 at address: 0x00050000SKIPPED > 0006 at address: 0x00060000SKIPPED > 0007 at address: 0x00070000SKIPPED > 0008 at address: 0x00080000SKIPPED > 0009 at address: 0x00090000SKIPPED > 0010 at address: 0x000a0000SKIPPED > 0011 at address: 0x000b0000SKIPPED > 0012 at address: 0x000c0000SKIPPED > 0013 at address: 0x000d0000SKIPPED > 0014 at address: 0x000e0000SKIPPED > 0015 at address: 0x000f0000SKIPPED > > Verifying flash... VERIFIED. > }}} > > Please explain me which rom layout I should use to update the last 512K > of > 1M BIOS? > I don't get it? The M50FW080 is a 1024k chip? Why just flash the last 512k? If your trying to flash a 512k image to a 1024k chip just make your image 1024k by "cat 512k.bin 512k.bin > 1024k.bin". Start with a fresh flash by erasing your chip first, then flash it. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From mylesgw at gmail.com Wed Mar 4 18:09:27 2009 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 4 Mar 2009 10:09:27 -0700 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <8C585EA3396447C4973D331C5A116681@chimp> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49A8914C.9060001@gmx.net> <8C585EA3396447C4973D331C5A116681@chimp> Message-ID: <2831fecf0903040909p48f318e9m37ae0fe1551b409f@mail.gmail.com> I refactored the patches to simplify reviewing. In a coming patch there are some bugfixes in amdk8_util.asl, so this will help with maintenance. changes by file: src/arch/i386/boot/acpi.c: Be Paranoid and set srat_lapic table to zero before filling it. Enable SLIT filling if acpi_create_slit gets called. src/northbridge/amd/amdk8/amdk8_util.asl: Put this file here instead of every board having a personal copy. src/northbridge/amd/amdfam10/amdfam10_util.asl: Put this file here instead of every board having a personal copy. src/mainboard/.../dsdt.dsl: Change the path to amd*_util.asl src/arch/i386/include/arch/acpi.h: Add slit prototype and minor whitespace. This patch is abuild tested. Signed-off-by: Myles Watson >> I didn't see the deletion of the per-board copies. Did subversion forget >> to include them in the diff? I will follow the patch with svn rm src/mainboard/iwill/dk8_htx/dx/amdk8_util.asl svn rm src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl svn rm src/mainboard/amd/serengeti_cheetah_fam10/dx/amdfam10_util.asl svn rm src/mainboard/asus/m2v-mx_se/amdk8_util.asl >> Besides that, moving the related fam10 file as well would be nice. Done. >> Maybe >> also a splitout of the K8 util ACPI code from the DBM690T and Pistachio >> code, but that seems to be more work. The ACPI code is totally different for those boards. It doesn't even use the same functions. The util files for those boards could be moved somewhere central, but I think it's best left for another patch. Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: amdk8_util.diff Type: text/x-patch Size: 24797 bytes Desc: not available URL: From mylesgw at gmail.com Wed Mar 4 18:59:10 2009 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 4 Mar 2009 10:59:10 -0700 Subject: [coreboot] amdk8_util.asl fixes, documentation, and ACPI question Message-ID: <2831fecf0903040959q273772ccw336873bacd463a8f@mail.gmail.com> This patch mostly documents the functionality of amdk8_util.asl. It also fixes a couple of logical errors that were corrupting the resources returned from _CRS. Fixes: 1. When adding a MMIO region to the southbridge, the previous region was corrupted. - Save previous region before checking if you're handling the southbridge. - Make sure you're on node 0 before adding the TOM region. - Add in a MMAX value of 0xFFDFFFFF (See the ACPI question at the end.) - Store resulting region with the saved region. - Move increment of Local 4 so it's more obvious what it refers to. Before: [TOM - 0xBFFFF] added to every node with Link 0 enabled After: [0xA0000-0xBFFFF] and [TOM-0xFFDFFFFF] only once 2. Missing RTAG call corrupted return value when there was no resource for the link - Add RTAG (BUF0) Signed-off-by: Myles Watson But the question is: Why is this logic here? Why do you want a region from TOM-(4G-2M)* when you explicitly have all the regions that are reachable from the HT links in other resources? * I got 4G-2M from the ACPI FAQ. Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: amdk8_util_fix.diff Type: text/x-patch Size: 6008 bytes Desc: not available URL: From corey.osgood at gmail.com Wed Mar 4 19:43:09 2009 From: corey.osgood at gmail.com (Corey Osgood) Date: Wed, 4 Mar 2009 13:43:09 -0500 Subject: [coreboot] r3965 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/include/arch src/config src/devices src/include src/include/cpu/x86 util In-Reply-To: References: <0MKojg-1LdiiY12Ia-000Shx@mx.perfora.net> Message-ID: On Sun, Mar 1, 2009 at 9:51 PM, Joseph Smith wrote: > > > > In order to use the old bios emulator, you have to do nothing. (Default, > > if > > CONFIG_PCI_ROM_RUN is enabled) > > > > In order to use yabel in your target, you need to add the following lines > > to > > your config: > > uses CONFIG_PCI_OPTION_ROM_RUN_YABEL > > default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 > > > > In order to use vm86 in your target, you need to add the following lines > > to > > your config: > > uses CONFIG_PCI_OPTION_ROM_RUN_VM86 > > default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 > > Note: vm86 only works on platforms with _RAMBASE in the lower megabyte. > > > Can we get this added to the wiki somewhere? Maybe > http://www.coreboot.org/Coreboot_Options ? IIRC, that page should update automatically sometime in the next few revisions. -Corey -------------- next part -------------- An HTML attachment was scrubbed... URL: From joe at settoplinux.org Wed Mar 4 20:32:15 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 14:32:15 -0500 Subject: [coreboot] r3965 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/include/arch src/config src/devices src/include src/include/cpu/x86 util In-Reply-To: References: <0MKojg-1LdiiY12Ia-000Shx@mx.perfora.net> Message-ID: <0b5a93cbbc3c3799c8152a6a6e0f3bdd@imap.1and1.com> On Wed, 4 Mar 2009 13:43:09 -0500, Corey Osgood wrote: > On Sun, Mar 1, 2009 at 9:51 PM, Joseph Smith wrote: > >> >> >> > In order to use the old bios emulator, you have to do nothing. > (Default, >> > if >> > CONFIG_PCI_ROM_RUN is enabled) >> > >> > In order to use yabel in your target, you need to add the following > lines >> > to >> > your config: >> > uses CONFIG_PCI_OPTION_ROM_RUN_YABEL >> > default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 >> > >> > In order to use vm86 in your target, you need to add the following > lines >> > to >> > your config: >> > uses CONFIG_PCI_OPTION_ROM_RUN_VM86 >> > default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 >> > Note: vm86 only works on platforms with _RAMBASE in the lower > megabyte. >> > >> Can we get this added to the wiki somewhere? Maybe >> http://www.coreboot.org/Coreboot_Options ? > > > IIRC, that page should update automatically sometime in the next few > revisions. > Great:-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Wed Mar 4 22:48:36 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 16:48:36 -0500 Subject: [coreboot] =?utf-8?q?10!_on_Wiki_Home_page=3F=3F=3F?= Message-ID: <1c58c64fac54d02af4b4060a18974a82@imap.1and1.com> Anyone know why there is a big "10!" on the Wiki homepage??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Wed Mar 4 22:50:27 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 16:50:27 -0500 Subject: [coreboot] =?utf-8?q?10!_on_Wiki_Home_page=3F=3F=3F?= In-Reply-To: <1c58c64fac54d02af4b4060a18974a82@imap.1and1.com> References: <1c58c64fac54d02af4b4060a18974a82@imap.1and1.com> Message-ID: On Wed, 04 Mar 2009 16:48:36 -0500, Joseph Smith wrote: > > Anyone know why there is a big "10!" on the Wiki homepage??? > Oh, is that to signify 10 years in the making? It just threw me off a bit... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From patrick at georgi-clan.de Wed Mar 4 22:51:11 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 04 Mar 2009 22:51:11 +0100 Subject: [coreboot] 10! on Wiki Home page??? In-Reply-To: <1c58c64fac54d02af4b4060a18974a82@imap.1and1.com> References: <1c58c64fac54d02af4b4060a18974a82@imap.1and1.com> Message-ID: <49AEF7CF.7060609@georgi-clan.de> Am 04.03.2009 22:48, schrieb Joseph Smith: > Anyone know why there is a big "10!" on the Wiki homepage??? > coreboot is 10! From phueper at hueper.net Wed Mar 4 23:09:07 2009 From: phueper at hueper.net (Pattrick Hueper) Date: Wed, 4 Mar 2009 23:09:07 +0100 Subject: [coreboot] [PATCH] YABEL: fix 32 bit IO accesses Message-ID: Hi, i just found that 32 bit PCI Accesses thru ports 0xCF8/0xCFC will not work in YABEL. This fixes it: Signed-off-by: Pattrick Hueper --- util/x86emu/yabel/io.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/x86emu/yabel/io.c b/util/x86emu/yabel/io.c index a69e5e6..6f481a7 100644 --- a/util/x86emu/yabel/io.c +++ b/util/x86emu/yabel/io.c @@ -348,7 +348,7 @@ u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size) { u32 rval = 0xFFFFFFFF; - if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) { + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { // PCI Configuration Mechanism 1 step 1 // write to 0xCF8, sets bus, device, function and Config Space offset // later read from 0xCFC-0xCFF returns the value... @@ -404,7 +404,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) { - if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) { + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { // PCI Configuration Mechanism 1 step 1 // write to 0xCF8, sets bus, device, function and Config Space offset // later write to 0xCFC-0xCFF sets the value... -- 1.6.1.2 From joe at settoplinux.org Wed Mar 4 23:23:43 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 17:23:43 -0500 Subject: [coreboot] Trace MMIO Read/Write Message-ID: Hello, Is there anyway to trace (capture) reads and writes to a mmio space in Linux? A utility program maybe? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From c-d.hailfinger.devel.2006 at gmx.net Wed Mar 4 23:25:03 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 04 Mar 2009 23:25:03 +0100 Subject: [coreboot] [PATCH] YABEL: fix 32 bit IO accesses In-Reply-To: References: Message-ID: <49AEFFBF.4000703@gmx.net> On 04.03.2009 23:09, Pattrick Hueper wrote: > Hi, > > i just found that 32 bit PCI Accesses thru ports 0xCF8/0xCFC will not > work in YABEL. This fixes it: > > Signed-off-by: Pattrick Hueper > Acked-by: Carl-Daniel Hailfinger Do you have commit privileges? Regards, Carl-Daniel -- http://www.hailfinger.org/ From rminnich at gmail.com Wed Mar 4 23:25:03 2009 From: rminnich at gmail.com (ron minnich) Date: Wed, 4 Mar 2009 14:25:03 -0800 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: References: Message-ID: <13426df10903041425n750652b8le8286ca8e4ac54bb@mail.gmail.com> On Wed, Mar 4, 2009 at 2:23 PM, Joseph Smith wrote: > > Hello, > Is there anyway to trace (capture) reads and writes to a mmio space in > Linux? A utility program maybe? > tell me more. what is the program, can you run it under ptrace, etc. What's it do? ron From patrick at georgi-clan.de Wed Mar 4 23:27:07 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 04 Mar 2009 23:27:07 +0100 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: References: Message-ID: <49AF003B.4000301@georgi-clan.de> Am 04.03.2009 23:23, schrieb Joseph Smith: > Hello, > Is there anyway to trace (capture) reads and writes to a mmio space in > Linux? A utility program maybe? > I think that's what the renouveau project does, so they should have a tool for that. It should work by mapping the mmio area away, then catching all accesses before passing them trough. Regards, Patrick Georgi From joe at settoplinux.org Wed Mar 4 23:36:04 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 17:36:04 -0500 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: <13426df10903041425n750652b8le8286ca8e4ac54bb@mail.gmail.com> References: <13426df10903041425n750652b8le8286ca8e4ac54bb@mail.gmail.com> Message-ID: <892d25980ab2672f2676e61a977e7b41@imap.1and1.com> On Wed, 4 Mar 2009 14:25:03 -0800, ron minnich wrote: > On Wed, Mar 4, 2009 at 2:23 PM, Joseph Smith wrote: >> >> Hello, >> Is there anyway to trace (capture) reads and writes to a mmio space in >> Linux? A utility program maybe? >> > > tell me more. what is the program, can you run it under ptrace, etc. > What's it do? > I more specifically, I can dump the mmio space before and after a driver is implimented, but there are certian registers that get programmed in a specific order to give the end result. I need to know what registers get programmed in what order, does that make sense? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Wed Mar 4 23:37:50 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 17:37:50 -0500 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: <49AF003B.4000301@georgi-clan.de> References: <49AF003B.4000301@georgi-clan.de> Message-ID: <2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> On Wed, 04 Mar 2009 23:27:07 +0100, Patrick Georgi wrote: > Am 04.03.2009 23:23, schrieb Joseph Smith: >> Hello, >> Is there anyway to trace (capture) reads and writes to a mmio space in >> Linux? A utility program maybe? >> > I think that's what the renouveau project does, so they should have a > tool for that. > It should work by mapping the mmio area away, then catching all accesses > before passing them trough. > > Thanks Patrick, I will check it out. Does it catch reads as well as writes? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Wed Mar 4 23:48:55 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 17:48:55 -0500 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: <2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> References: <49AF003B.4000301@georgi-clan.de> <2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> Message-ID: On Wed, 04 Mar 2009 17:37:50 -0500, Joseph Smith wrote: > > > > On Wed, 04 Mar 2009 23:27:07 +0100, Patrick Georgi > > wrote: >> Am 04.03.2009 23:23, schrieb Joseph Smith: >>> Hello, >>> Is there anyway to trace (capture) reads and writes to a mmio space in >>> Linux? A utility program maybe? >>> >> I think that's what the renouveau project does, so they should have a >> tool for that. >> It should work by mapping the mmio area away, then catching all accesses >> before passing them trough. >> >> > Thanks Patrick, I will check it out. Does it catch reads as well as > writes? > Ahhh, thanks again Patrick! http://nouveau.freedesktop.org/wiki/MmioTrace This will do exactly what I want it to :-) Yahoo, this is going to crack the mystery wide open!!! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From kevin at koconnor.net Thu Mar 5 01:32:06 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Wed, 4 Mar 2009 19:32:06 -0500 Subject: [coreboot] the seabios reboot in the post process In-Reply-To: References: Message-ID: <20090305003206.GA16862@morn.localdomain> On Wed, Mar 04, 2009 at 10:15:21AM +0000, wei yang wrote: > When I use the seabios as the payload, I got a strange issue. > In the seabios flow: > > Post->timer_setup->rtc_updating->inb_cmos function > > when run the inb_cmos, it will reboot on the inb operation. > > inb_cmos disassemables to fllowing: > out 0x70, value > in value, 0x71. ----> run here to make the reboot happen. > > 0x70 is the CMOS index port, 0x71 is the CMOS data port. > > I suspect the "in value, 0x71" operation causes a exception and the > seabios doesn't have real IDT, so it then make the reboot. > > but why it cause the exception is a question for me? > > since IO port 0x70 also reponsible for the NMI enble/disable, is it > caused the error? I haven't seen this before. It would be odd for port 0x70 to control NMI, because it is usually used for rtc access. -Kevin From joe at settoplinux.org Thu Mar 5 02:12:39 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 20:12:39 -0500 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: References: <49AF003B.4000301@georgi-clan.de> <2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> Message-ID: <2a8e793e201030ae643e7c2d48e3f368@imap.1and1.com> On Wed, 04 Mar 2009 17:48:55 -0500, Joseph Smith wrote: > > > > On Wed, 04 Mar 2009 17:37:50 -0500, Joseph Smith > wrote: >> >> >> >> On Wed, 04 Mar 2009 23:27:07 +0100, Patrick Georgi >> >> wrote: >>> Am 04.03.2009 23:23, schrieb Joseph Smith: >>>> Hello, >>>> Is there anyway to trace (capture) reads and writes to a mmio space in >>>> Linux? A utility program maybe? >>>> >>> I think that's what the renouveau project does, so they should have a >>> tool for that. >>> It should work by mapping the mmio area away, then catching all > accesses >>> before passing them trough. >>> >>> >> Thanks Patrick, I will check it out. Does it catch reads as well as >> writes? >> > Ahhh, thanks again Patrick! > > http://nouveau.freedesktop.org/wiki/MmioTrace > hmmm :-( I need to do this on a older kernel 2.6.10 and mmiotrace does not support older kernels.... Any other suggestions? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From mylesgw at gmail.com Thu Mar 5 04:44:38 2009 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 4 Mar 2009 20:44:38 -0700 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: <2a8e793e201030ae643e7c2d48e3f368@imap.1and1.com> References: <49AF003B.4000301@georgi-clan.de><2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> <2a8e793e201030ae643e7c2d48e3f368@imap.1and1.com> Message-ID: <2B342F75EAF54624A540516883CCB16D@chimp> > -----Original Message----- > From: coreboot-bounces+mylesgw=gmail.com at coreboot.org [mailto:coreboot- > bounces+mylesgw=gmail.com at coreboot.org] On Behalf Of Joseph Smith > Sent: Wednesday, March 04, 2009 6:13 PM > To: Patrick Georgi; coreboot > Subject: Re: [coreboot] Trace MMIO Read/Write > > > > > On Wed, 04 Mar 2009 17:48:55 -0500, Joseph Smith > wrote: > > > > > > > > On Wed, 04 Mar 2009 17:37:50 -0500, Joseph Smith > > wrote: > >> > >> > >> > >> On Wed, 04 Mar 2009 23:27:07 +0100, Patrick Georgi > >> > >> wrote: > >>> Am 04.03.2009 23:23, schrieb Joseph Smith: > >>>> Hello, > >>>> Is there anyway to trace (capture) reads and writes to a mmio space > in > >>>> Linux? A utility program maybe? > >>>> > >>> I think that's what the renouveau project does, so they should have a > >>> tool for that. > >>> It should work by mapping the mmio area away, then catching all > > accesses > >>> before passing them trough. > >>> > >>> > >> Thanks Patrick, I will check it out. Does it catch reads as well as > >> writes? > >> > > Ahhh, thanks again Patrick! > > > > http://nouveau.freedesktop.org/wiki/MmioTrace > > > hmmm :-( > I need to do this on a older kernel 2.6.10 and mmiotrace does not support > older kernels.... > > Any other suggestions? Does it run in a simulator or an emulator? SimNow or Qemu could log them for you. Myles From joe at settoplinux.org Thu Mar 5 05:13:58 2009 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 04 Mar 2009 23:13:58 -0500 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: <2B342F75EAF54624A540516883CCB16D@chimp> References: <49AF003B.4000301@georgi-clan.de><2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> <2a8e793e201030ae643e7c2d48e3f368@imap.1and1.com> <2B342F75EAF54624A540516883CCB16D@chimp> Message-ID: <6dc38880e508b9b36c2d6906157b4a06@imap.1and1.com> On Wed, 4 Mar 2009 20:44:38 -0700, "Myles Watson" wrote: > > >> -----Original Message----- >> From: coreboot-bounces+mylesgw=gmail.com at coreboot.org [mailto:coreboot- >> bounces+mylesgw=gmail.com at coreboot.org] On Behalf Of Joseph Smith >> Sent: Wednesday, March 04, 2009 6:13 PM >> To: Patrick Georgi; coreboot >> Subject: Re: [coreboot] Trace MMIO Read/Write >> >> >> >> >> On Wed, 04 Mar 2009 17:48:55 -0500, Joseph Smith >> wrote: >> > >> > >> > >> > On Wed, 04 Mar 2009 17:37:50 -0500, Joseph Smith >> > wrote: >> >> >> >> >> >> >> >> On Wed, 04 Mar 2009 23:27:07 +0100, Patrick Georgi >> >> >> >> wrote: >> >>> Am 04.03.2009 23:23, schrieb Joseph Smith: >> >>>> Hello, >> >>>> Is there anyway to trace (capture) reads and writes to a mmio space >> in >> >>>> Linux? A utility program maybe? >> >>>> >> >>> I think that's what the renouveau project does, so they should have > a >> >>> tool for that. >> >>> It should work by mapping the mmio area away, then catching all >> > accesses >> >>> before passing them trough. >> >>> >> >>> >> >> Thanks Patrick, I will check it out. Does it catch reads as well as >> >> writes? >> >> >> > Ahhh, thanks again Patrick! >> > >> > http://nouveau.freedesktop.org/wiki/MmioTrace >> > >> hmmm :-( >> I need to do this on a older kernel 2.6.10 and mmiotrace does not > support >> older kernels.... >> >> Any other suggestions? > > Does it run in a simulator or an emulator? SimNow or Qemu could log them > for you. > Can they simulate a Intel onboard graphics adapter? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From svn at coreboot.org Thu Mar 5 06:48:43 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 5 Mar 2009 06:48:43 +0100 Subject: [coreboot] r1143 - coreboot-v3/arch/x86 Message-ID: Author: rminnich Date: 2009-03-05 06:48:43 +0100 (Thu, 05 Mar 2009) New Revision: 1143 Modified: coreboot-v3/arch/x86/secondary.S Log: This is working up to the ljmpl to protected mode. It has all the debugging in, using locations 0 and _secondary_start as POST. Calling from initram did not work out, as we have to disable_car in initram to make such a call work (on core2). For now, I am calling this from stage1_phase 3, before stage2 is called. But that has increased the code size of stage1, which is not a great idea. What I am thinking we ought to do: call this from stage2, before phase 1, so that CPUs are nice and set up and quiet. Provide phase2 with an SMP-safe printk. This is here so others may see it and correct my work. The good news is that SMP startup on core2 on v3 is now starting to go. But the better news is that the way this is working is pretty generic and ought to apply to much more than just core2. To really look at object you might want to get ndisasm. Signed-off-by: Ronald G. Minnich Acked-by: Ronald G. Minnich Modified: coreboot-v3/arch/x86/secondary.S =================================================================== --- coreboot-v3/arch/x86/secondary.S 2009-03-01 19:23:02 UTC (rev 1142) +++ coreboot-v3/arch/x86/secondary.S 2009-03-05 05:48:43 UTC (rev 1143) @@ -28,28 +28,52 @@ .code16 .balign 4096 cli - movl $1b, %ebx + movw $0xdead, 0 + movw $0xbeef, 2 xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ /* On hyper threaded cpus, invalidating the cache here is * very very bad. Don't. */ + movw $0, 0 + movl $1b, %ebx + movw $1, 0 + movw $2, 0 /* setup the data segment */ movw %cs, %ax + movw %ax, 2 + movw $3, 0 movw %ax, %ds + movw $4, 0 + /* past this point, "0" means ds:0, i.e. cs:0, or the + * segment part of the address. + */ data32 lgdt gdtaddr - _secondary_start +// data32 lgdt %cs:gdtptr + movw $5, 0 movl %cr0, %eax + movw $6, 0 andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + movw $7, 0 orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movw $8, 0 movl %eax, %cr0 + movw $9, 0 + hlt + /* tested to this point but not past it */ - ljmpl $0x10, $1f + /* I am pretty sure this just jumps back into + * ROM; it's an abs jump + */ + data32 ljmp $0x10, $secondary32 + movw $0xa, 0 1: .code32 secondary32: + hlt movw $0x18, %ax movw %ax, %ds movw %ax, %es From andrew.goodbody at tadpole.com Thu Mar 5 11:12:58 2009 From: andrew.goodbody at tadpole.com (Andrew Goodbody) Date: Thu, 05 Mar 2009 10:12:58 +0000 Subject: [coreboot] the seabios reboot in the post process In-Reply-To: <20090305003206.GA16862@morn.localdomain> References: <20090305003206.GA16862@morn.localdomain> Message-ID: <49AFA5AA.5000303@tadpole.com> Kevin O'Connor wrote: > On Wed, Mar 04, 2009 at 10:15:21AM +0000, wei yang wrote: >> When I use the seabios as the payload, I got a strange issue. >> In the seabios flow: >> >> Post->timer_setup->rtc_updating->inb_cmos function >> >> when run the inb_cmos, it will reboot on the inb operation. >> >> inb_cmos disassemables to fllowing: >> out 0x70, value >> in value, 0x71. ----> run here to make the reboot happen. >> >> 0x70 is the CMOS index port, 0x71 is the CMOS data port. >> >> I suspect the "in value, 0x71" operation causes a exception and the >> seabios doesn't have real IDT, so it then make the reboot. >> >> but why it cause the exception is a question for me? >> >> since IO port 0x70 also reponsible for the NMI enble/disable, is it >> caused the error? > > I haven't seen this before. It would be odd for port 0x70 to control > NMI, because it is usually used for rtc access. It's been this way since the IBM PC AT. If you write to 0x70 with bit 7 reset then you risk releasing any pending NMI. If the interrupt vectors are not initialised then you always need to set bit 7 when writing to 0x70. Andrew From Qingpei.Wang at amd.com Thu Mar 5 12:49:52 2009 From: Qingpei.Wang at amd.com (Wang, Qingpei) Date: Thu, 5 Mar 2009 19:49:52 +0800 Subject: [coreboot] Problems about booting windows xp In-Reply-To: <4999E1E1.8050307@assembler.cz> References: <20090118021006.GA14386@morn.localdomain> <49759968.8040907@assembler.cz> <49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz> Message-ID: Hi Rudolf, I changed the dsdt.asl which take M2V-MX as an example. Now it stopped rebooting, but after the window xp scroll bar it hangs up, which supposed to show the log in screen. I am wondering if there is any another places should be fixed. And also in /src/arch/i386/boot/tables.c( function: write_tables line92) I changed rom_table_start=((512-64)*1024*1024)-64*1024 followed by an patch, May be it is wrong ,which address should I changed in this places? Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD) -----Original Message----- From: Rudolf Marek [mailto:r.marek at assembler.cz] Sent: Tuesday, February 17, 2009 6:00 AM To: Wang, Qingpei Cc: Carl-Daniel Hailfinger; Coreboot; Perley, Tim Subject: Re: [coreboot] Problems about booting windows xp -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I ran also acpiexec util on it, here is what I found. First I will present how PCI0 _CRS method looks on MINE Asus M2V-MX SE, this works with windows... [00] 16-Bit WORD Address Space Resource Resource Type : Bus Number Range Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 0000 Address Minimum : 0000 Address Maximum : 0005 Translation Offset : 0000 Address Length : 0006 Resource Source Index : 00 Resource Source : [Not Specified] [01] 32-Bit DWORD Address Space Resource Resource Type : I/O Range Range Type : EntireRange Translation : TypeStatic Translation Type : DenseTranslation Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000 Address Minimum : 000003B0 Address Maximum : 000003DF Translation Offset : 00000000 Address Length : 00000030 Resource Source Index : 00 Resource Source : [Not Specified] [02] 32-Bit DWORD Address Space Resource Resource Type : I/O Range Range Type : EntireRange Translation : TypeStatic Translation Type : DenseTranslation Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000 Address Minimum : 00000D00 Address Maximum : 00001FFF Translation Offset : 00000000 Address Length : 00001300 Resource Source Index : 00 Resource Source : [Not Specified] [03] 32-Bit DWORD Address Space Resource Resource Type : Memory Range Write Protect : ReadWrite Caching : NonCacheable Range Type : AddressRangeMemory Translation : TypeStatic Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000 Address Minimum : C0000000 Address Maximum : DFFFFFFF Translation Offset : 00000000 Address Length : 20000000 Resource Source Index : 00 Resource Source : [Not Specified] [04] 32-Bit DWORD Address Space Resource Resource Type : Memory Range Write Protect : ReadWrite Caching : NonCacheable Range Type : AddressRangeMemory Translation : TypeStatic Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000 Address Minimum : E0000000 Address Maximum : F12FFFFF Translation Offset : 00000000 Address Length : 11300000 Resource Source Index : 00 Resource Source : [Not Specified] [05] 32-Bit DWORD Address Space Resource Resource Type : Memory Range Write Protect : ReadWrite Caching : NonCacheable Range Type : AddressRangeMemory Translation : TypeStatic Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000 Address Minimum : 000A0000 Address Maximum : 000BFFFF Translation Offset : 00000000 Address Length : 00020000 Resource Source Index : 00 Resource Source : [Not Specified] [06] I/O Resource Address Decoding : Decode16 Address Minimum : 0CF8 Address Maximum : 0CF8 Alignment : 01 Address Length : 08 [07] 16-Bit WORD Address Space Resource Resource Type : I/O Range Range Type : EntireRange Translation : TypeStatic Translation Type : DenseTranslation Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 0000 Address Minimum : 0000 Address Maximum : 0CF7 Translation Offset : 0000 Address Length : 0CF8 Resource Source Index : 00 Resource Source : [Not Specified] [08] EndTag Resource See, there is no RAM mentioned at all. Just PCI decode ranges from CPU as well the PCI IO ranges. Also please note that: LEN = MAX - MIN + 1 This is needed for Windows. And here what you have for your board: acpixtract -a data.txt ./acpiexec ./DSDT.dat - - resources \_SB_.PCI0 [00] I/O Resource Address Decoding : Decode16 Address Minimum : 0CF8 Address Maximum : 0CF8 Alignment : 01 Address Length : 08 [01] 16-Bit WORD Address Space Resource Resource Type : I/O Range Range Type : EntireRange Translation : TypeStatic Translation Type : DenseTranslation Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 0000 Address Minimum : 0000 Address Maximum : 0CF7 Translation Offset : 0000 Address Length : 0CF8 Resource Source Index : 00 Resource Source : [Not Specified] [02] 16-Bit WORD Address Space Resource Resource Type : I/O Range Range Type : EntireRange Translation : TypeStatic Translation Type : DenseTranslation Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 0000 Address Minimum : 0D00 Address Maximum : FFFF Translation Offset : 0000 Address Length : F300 Resource Source Index : 00 Resource Source : [Not Specified] [03] 32-Bit Fixed Memory Range Resource Write Protect : ReadWrite Address : 00000000 Address Length : 000A0000 [04] 32-Bit Fixed Memory Range Resource Write Protect : ReadOnly Address : 000A0000 Address Length : 00020000 [05] 32-Bit Fixed Memory Range Resource Write Protect : ReadOnly Address : 000C0000 Address Length : 00020000 [06] 32-Bit Fixed Memory Range Resource Write Protect : ReadOnly Address : 000E0000 Address Length : 00020000 [07] 32-Bit Fixed Memory Range Resource Write Protect : ReadWrite Address : 00100000 Address Length : 3FF00000 I think this does not agree the e820 map here, because of the ACPI tables. Also both below are empty. No good? [08] 32-Bit DWORD Address Space Resource Resource Type : Memory Range Write Protect : ReadWrite Caching : Cacheable Range Type : AddressRangeMemory Translation : TypeStatic Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000 Address Minimum : 00000000 Address Maximum : 00000000 Translation Offset : 00000000 Address Length : 00000000 Resource Source Index : 00 Resource Source : [Not Specified] [09] 64-Bit QWORD Address Space Resource Resource Type : Memory Range Write Protect : ReadWrite Caching : Cacheable Range Type : AddressRangeMemory Translation : TypeStatic Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000FFFFFFFF Address Minimum : 0000000000000000 Address Maximum : 0000000000000000 Translation Offset : 0000000000000000 Address Length : 0000000000000000 Resource Source Index : 00 Resource Source : [Not Specified] [0A] 64-Bit QWORD Address Space Resource Resource Type : Memory Range Write Protect : ReadWrite Caching : Cacheable Range Type : AddressRangeMemory Translation : TypeStatic Consumer/Producer : ResourceProducer Address Decode : PosDecode Min Relocatability : MinFixed Max Relocatability : MaxFixed Granularity : 00000000FFFFFFFF Address Minimum : 0000000000000000 Address Maximum : 0000000000000000 Translation Offset : 0000000000000000 Address Length : 0000000000000000 Resource Source Index : 00 Resource Source : [Not Specified] I would suggest just to start with totally artificial and static _CRS returned object, similar what is in QEMU: http://bochs.sourceforge.net/cgi-bin/lxr/source/bios/acpi-dsdt.dsl Just grab it and fill all resources manually. (edit the MEMP so all fields are valid for your HW, then just put into _CRS Return (MEMP), without any computations). Then try to boot windows. Once it works you can play with the generic runtime adjustments. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkmZ4d8ACgkQ3J9wPJqZRNVKUACgn4rbrxdPEzEFE5zjdit1cbFB 4QgAn3U/bM2FOs+Vg91AD48jEMxZ4odF =+C4j -----END PGP SIGNATURE----- From c-d.hailfinger.devel.2006 at gmx.net Thu Mar 5 14:16:08 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 05 Mar 2009 14:16:08 +0100 Subject: [coreboot] [PATCH] flashrom: Use helper functions to access flash chips Message-ID: <49AFD098.9000708@gmx.net> flashrom: Use helper functions to access flash chips. Right now we perform direct pointer manipulation without any abstraction to read from and write to memory mapped flash chips. That makes it impossible to drive any flasher which does not mmap the whole chip. Using helper functions readb() and writeb() allows a driver for external flash programmers like Paraflasher to replace readb and writeb with calls to its own chip access routines. This patch has the additional advantage of removing lots of unnecessary casts to volatile uint8_t * and now-superfluous parentheses which caused poor readability. Please note that this patch works, but the conversion is not complete yet (reads outside assignments are not converted). I used the semantic patcher Coccinelle to create this patch. The semantic patch follows: @@ expression a; typedef uint8_t; volatile uint8_t *b; @@ - *b = a; + writeb(a, b); @@ expression a; volatile uint8_t *b; @@ - a = *b; + a = readb(b); @@ type T; T b; expression a; @@ writeb(a, -(T) b); @@ type T; T b; expression a; @@ a = readb( -(T) b); @@ expression a, b; @@ writeb(a, -( b -) ); @@ expression a, b; @@ a = readb( -( b -) ); Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-inband_chipaccess_helper_functions/flash.h =================================================================== --- flashrom-inband_chipaccess_helper_functions/flash.h (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/flash.h (Arbeitskopie) @@ -58,6 +58,36 @@ #define INL inl #endif +static inline void writeb(uint8_t b, volatile void *addr) +{ + *(volatile uint8_t *) addr = b; +} + +static inline void writew(uint16_t b, volatile void *addr) +{ + *(volatile uint16_t *) addr = b; +} + +static inline void writel(uint32_t b, volatile void *addr) +{ + *(volatile uint32_t *) addr = b; +} + +static inline uint8_t readb(const volatile void *addr) +{ + return *(volatile uint8_t *) addr; +} + +static inline uint16_t readw(const volatile void *addr) +{ + return *(volatile uint16_t *) addr; +} + +static inline uint32_t readl(const volatile void *addr) +{ + return *(volatile uint32_t *) addr; +} + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { Index: flashrom-inband_chipaccess_helper_functions/pm49fl00x.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/pm49fl00x.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/pm49fl00x.c (Arbeitskopie) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - *(bios + (i * block_size) + 2) = bits; + writeb(bits, bios + (i * block_size) + 2); } } Index: flashrom-inband_chipaccess_helper_functions/en29f002a.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/en29f002a.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/en29f002a.c (Arbeitskopie) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = *(volatile uint8_t *)(bios + 0x100); - id2 = *(volatile uint8_t *)(bios + 0x101); + id1 = readb(bios + 0x100); + id2 = readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xF0; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0xAAA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0xAAA); + writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = *(volatile uint8_t *)(bios + 0x100); - id2 = *(volatile uint8_t *)(bios + 0x101); + id1 = readb(bios + 0x100); + id2 = readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0xAAA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xF0; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0xAAA); + writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0xA0; - *dst++ = *buf++; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); + writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Index: flashrom-inband_chipaccess_helper_functions/jedec.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/jedec.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/jedec.c (Arbeitskopie) @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x80; - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x20; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x80, bios + 0x5555); + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = *(volatile uint8_t *)(bios + 0x100); + id1 = readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = *(volatile uint8_t *)(bios + 0x101); + id2 = readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + page) = 0x30; + writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + block) = 0x50; + writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x10; + writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - *dst = *src; + writeb(*src, dst); dst++; src++; } @@ -269,12 +269,12 @@ retry: /* Issue JEDEC Byte Program command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - *dst = *src; + writeb(*src, dst); toggle_ready_jedec(bios); if (*dst != *src && tried++ < MAX_REFLASH_TRIES) { Index: flashrom-inband_chipaccess_helper_functions/w29ee011.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w29ee011.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/w29ee011.c (Arbeitskopie) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x60; + writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Index: flashrom-inband_chipaccess_helper_functions/sst49lfxxxc.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst49lfxxxc.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sst49lfxxxc.c (Arbeitskopie) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - *(bios + (i * 65536) + 2) = bits; + writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - *bios = SECTOR_ERASE; - *(bios + address) = ERASE; + writeb(SECTOR_ERASE, bios); + writeb(ERASE, bios + address); do { - status = *bios; + status = readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - *bios = AUTO_PGRM; - *dst++ = *src++; + writeb(AUTO_PGRM, bios); + writeb(*src++, dst++); do { - status = *bios; + status = readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - *bios = RESET; + writeb(RESET, bios); - *bios = READ_ID; - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + writeb(READ_ID, bios); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = RESET; + writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - *bios = RESET; + writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - *bios = RESET; + writeb(RESET, bios); return 0; } Index: flashrom-inband_chipaccess_helper_functions/sharplhf00l04.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sharplhf00l04.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sharplhf00l04.c (Arbeitskopie) @@ -46,18 +46,18 @@ *(volatile uint8_t *)(bios + 0x5555) = 0x90; #endif - *bios = 0xff; + writeb(0xff, bios); myusec_delay(10); - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Leave ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - *bios = 0x70; + writeb(0x70, bios); if ((*bios & 0x80) == 0) { // it's busy while ((*bios & 0x80) == 0) ; } - status = *bios; + status = readb(bios); // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - *bios = 0x50; + writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); printf("write protect is 0x%x\n", *(wrprotect)); - *(wrprotect) = 0; + writeb(0, wrprotect); printf("write protect is 0x%x\n", *(wrprotect)); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_lhf00l04(bios); } } Index: flashrom-inband_chipaccess_helper_functions/m29f002.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/m29f002.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/m29f002.c (Arbeitskopie) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x80; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x10; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x80, bios + 0x555); + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x80; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *dst = 0x30; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x80, bios + 0x555); + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xa0; - *dst = *src; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0xa0, bios + 0x555); + writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Index: flashrom-inband_chipaccess_helper_functions/w39v040c.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v040c.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/w39v040c.c (Arbeitskopie) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 1); - lock = *(volatile uint8_t *)(bios + 0xfff2); + id1 = readb(bios); + id2 = readb(bios + 1); + lock = readb(bios + 0xfff2); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Index: flashrom-inband_chipaccess_helper_functions/sst28sf040.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst28sf040.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sst28sf040.c (Arbeitskopie) @@ -35,13 +35,13 @@ /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = *(volatile uint8_t *)(bios + 0x1823); - tmp = *(volatile uint8_t *)(bios + 0x1820); - tmp = *(volatile uint8_t *)(bios + 0x1822); - tmp = *(volatile uint8_t *)(bios + 0x0418); - tmp = *(volatile uint8_t *)(bios + 0x041B); - tmp = *(volatile uint8_t *)(bios + 0x0419); - tmp = *(volatile uint8_t *)(bios + 0x040A); + tmp = readb(bios + 0x1823); + tmp = readb(bios + 0x1820); + tmp = readb(bios + 0x1822); + tmp = readb(bios + 0x0418); + tmp = readb(bios + 0x041B); + tmp = readb(bios + 0x0419); + tmp = readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) @@ -49,20 +49,20 @@ /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = *(volatile uint8_t *)(bios + 0x1823); - tmp = *(volatile uint8_t *)(bios + 0x1820); - tmp = *(volatile uint8_t *)(bios + 0x1822); - tmp = *(volatile uint8_t *)(bios + 0x0418); - tmp = *(volatile uint8_t *)(bios + 0x041B); - tmp = *(volatile uint8_t *)(bios + 0x0419); - tmp = *(volatile uint8_t *)(bios + 0x041A); + tmp = readb(bios + 0x1823); + tmp = readb(bios + 0x1820); + tmp = readb(bios + 0x1822); + tmp = readb(bios + 0x0418); + tmp = readb(bios + 0x041B); + tmp = readb(bios + 0x0419); + tmp = readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - *bios = AUTO_PG_ERASE1; - *(bios + address) = AUTO_PG_ERASE2; + writeb(AUTO_PG_ERASE1, bios); + writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -85,8 +85,8 @@ continue; } /*issue AUTO PROGRAM command */ - *dst = AUTO_PGRM; - *dst++ = *src++; + writeb(AUTO_PGRM, dst); + writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -100,16 +100,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *bios = RESET; + writeb(RESET, bios); myusec_delay(10); - *bios = READ_ID; + writeb(READ_ID, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); myusec_delay(10); - id2 = *(volatile uint8_t *)(bios + 0x01); + id2 = readb(bios + 0x01); - *bios = RESET; + writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -124,8 +124,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - *bios = CHIP_ERASE; - *bios = CHIP_ERASE; + writeb(CHIP_ERASE, bios); + writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Index: flashrom-inband_chipaccess_helper_functions/stm50flw0x0x.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/stm50flw0x0x.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/stm50flw0x0x.c (Arbeitskopie) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = *(volatile uint8_t *)(bios + 0x100); + id1 = readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = *(volatile uint8_t *)(bios + 0x101); + id2 = readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - *bios = 0x70; + writeb(0x70, bios); if ((*bios & 0x80) == 0) { // it's busy while ((*bios & 0x80) == 0) ; } // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); } /* @@ -142,7 +142,7 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - *(flash_addr + offset + j) = unlock_sector; + writeb(unlock_sector, flash_addr + offset + j); if (*(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); @@ -151,7 +151,7 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - *(flash_addr + offset) = unlock_sector; + writeb(unlock_sector, flash_addr + offset); if (*(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; @@ -167,11 +167,11 @@ int j; // clear status register - *bios = 0x50; + writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_stm50flw0x0x(bios); } Index: flashrom-inband_chipaccess_helper_functions/am29f040b.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/am29f040b.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/am29f040b.c (Arbeitskopie) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + address) = 0x30; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0xA0; - *dst++ = *src++; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0xA0, bios + 0x555); + writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x90, bios + 0x555); - id1 = *bios; - id2 = *(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x10; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-inband_chipaccess_helper_functions/sst_fwhub.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Arbeitskopie) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - *(wrprotect) = 0; + writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Index: flashrom-inband_chipaccess_helper_functions/w39v080fa.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Arbeitskopie) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = *(volatile uint8_t *)bios; - did = *(volatile uint8_t *)(bios + 0x01); + vid = readb(bios); + did = readb(bios + 0x01); /* Product Identifixation Exit */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -60,14 +60,14 @@ printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, *wrprotect); - locking = *wrprotect; + locking = readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = *(volatile uint8_t *)(bios + 0xffff2); + locking = readb(bios + 0xffff2); /* Product Identification Exit */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x80, bios + 0x5555); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + sector) = 0x30; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); Index: flashrom-inband_chipaccess_helper_functions/82802ab.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/82802ab.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/82802ab.c (Arbeitskopie) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); #endif - *bios = 0xff; + writeb(0xff, bios); myusec_delay(10); - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Leave ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - *bios = 0x70; + writeb(0x70, bios); if ((*bios & 0x80) == 0) { // it's busy while ((*bios & 0x80) == 0) ; } - status = *bios; + status = readb(bios); // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); return status; } @@ -115,17 +115,17 @@ uint8_t status; // clear status register - *bios = 0x50; + writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - *(wrprotect) = 0; + writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_82802ab(bios); } } Index: flashrom-inband_chipaccess_helper_functions/m29f400bt.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/m29f400bt.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/m29f400bt.c (Arbeitskopie) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xA0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,12 +35,12 @@ int i; for (i = 0; i < page_size; i++) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xA0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - *dst = *src; + writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x90; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = *(volatile uint8_t *)(bios + 0x02); + id2 = readb(bios + 0x02); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xF0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x80; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x80, bios + 0xAAA); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x10; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x80; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x80, bios + 0xAAA); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - *dst = 0x30; + writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-inband_chipaccess_helper_functions/mx29f002.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/mx29f002.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/mx29f002.c (Arbeitskopie) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(bios + 0x555) = 0xF0; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x10; + writeb(0xF0, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0xA0; - *dst++ = *buf++; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); + writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom-inband_chipaccess_helper_functions.diff URL: From kevin at koconnor.net Thu Mar 5 14:37:29 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Thu, 5 Mar 2009 08:37:29 -0500 Subject: [coreboot] the seabios reboot in the post process In-Reply-To: <49AFA5AA.5000303@tadpole.com> References: <20090305003206.GA16862@morn.localdomain> <49AFA5AA.5000303@tadpole.com> Message-ID: <20090305133729.GA22747@morn.localdomain> On Thu, Mar 05, 2009 at 10:12:58AM +0000, Andrew Goodbody wrote: > Kevin O'Connor wrote: >> On Wed, Mar 04, 2009 at 10:15:21AM +0000, wei yang wrote: >>> since IO port 0x70 also reponsible for the NMI enble/disable, is it >>> caused the error? >> >> I haven't seen this before. It would be odd for port 0x70 to control >> NMI, because it is usually used for rtc access. > > It's been this way since the IBM PC AT. If you write to 0x70 with bit 7 > reset then you risk releasing any pending NMI. If the interrupt vectors > are not initialised then you always need to set bit 7 when writing to > 0x70. Does the patch below stop the crash? -Kevin --- a/src/cmos.h +++ b/src/cmos.h @@ -56,14 +56,14 @@ static inline u8 inb_cmos(u8 reg) { - outb(reg, PORT_CMOS_INDEX); + outb(reg | 0x80, PORT_CMOS_INDEX); return inb(PORT_CMOS_DATA); } static inline void outb_cmos(u8 val, u8 reg) { - outb(reg, PORT_CMOS_INDEX); + outb(reg | 0x80, PORT_CMOS_INDEX); outb(val, PORT_CMOS_DATA); } From mylesgw at gmail.com Thu Mar 5 15:09:47 2009 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 5 Mar 2009 07:09:47 -0700 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: <6dc38880e508b9b36c2d6906157b4a06@imap.1and1.com> References: <49AF003B.4000301@georgi-clan.de><2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> <2a8e793e201030ae643e7c2d48e3f368@imap.1and1.com> <2B342F75EAF54624A540516883CCB16D@chimp> <6dc38880e508b9b36c2d6906157b4a06@imap.1and1.com> Message-ID: <2A5F7B5367844CD2BFA54F09D89824B8@chimp> > -----Original Message----- > From: Joseph Smith [mailto:joe at settoplinux.org] > Sent: Wednesday, March 04, 2009 9:14 PM > To: Myles Watson > Cc: coreboot > Subject: RE: [coreboot] Trace MMIO Read/Write > > > > > On Wed, 4 Mar 2009 20:44:38 -0700, "Myles Watson" > wrote: > > > > > >> -----Original Message----- > >> From: coreboot-bounces+mylesgw=gmail.com at coreboot.org [mailto:coreboot- > >> bounces+mylesgw=gmail.com at coreboot.org] On Behalf Of Joseph Smith > >> Sent: Wednesday, March 04, 2009 6:13 PM > >> To: Patrick Georgi; coreboot > >> Subject: Re: [coreboot] Trace MMIO Read/Write > >> > >> > >> > >> > >> On Wed, 04 Mar 2009 17:48:55 -0500, Joseph Smith > >> wrote: > >> > > >> > > >> > > >> > On Wed, 04 Mar 2009 17:37:50 -0500, Joseph Smith > > >> > wrote: > >> >> > >> >> > >> >> > >> >> On Wed, 04 Mar 2009 23:27:07 +0100, Patrick Georgi > >> >> > >> >> wrote: > >> >>> Am 04.03.2009 23:23, schrieb Joseph Smith: > >> >>>> Hello, > >> >>>> Is there anyway to trace (capture) reads and writes to a mmio > space > >> in > >> >>>> Linux? A utility program maybe? > >> >>>> > >> >>> I think that's what the renouveau project does, so they should have > > a > >> >>> tool for that. > >> >>> It should work by mapping the mmio area away, then catching all > >> > accesses > >> >>> before passing them trough. > >> >>> > >> >>> > >> >> Thanks Patrick, I will check it out. Does it catch reads as well as > >> >> writes? > >> >> > >> > Ahhh, thanks again Patrick! > >> > > >> > http://nouveau.freedesktop.org/wiki/MmioTrace > >> > > >> hmmm :-( > >> I need to do this on a older kernel 2.6.10 and mmiotrace does not > > support > >> older kernels.... > >> > >> Any other suggestions? > > > > Does it run in a simulator or an emulator? SimNow or Qemu could log > them > > for you. > > > Can they simulate a Intel onboard graphics adapter? Probably not easily. Is the driver not open-source? I'm wondering why you couldn't recompile it for the newer kernel if you really want to use MmioTrace. Thanks, Myles From joe at settoplinux.org Thu Mar 5 15:27:02 2009 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 05 Mar 2009 09:27:02 -0500 Subject: [coreboot] Trace MMIO Read/Write In-Reply-To: <2A5F7B5367844CD2BFA54F09D89824B8@chimp> References: <49AF003B.4000301@georgi-clan.de><2f1292b507d7d4b7645ede741a42c6a0@imap.1and1.com> <2a8e793e201030ae643e7c2d48e3f368@imap.1and1.com> <2B342F75EAF54624A540516883CCB16D@chimp> <6dc38880e508b9b36c2d6906157b4a06@imap.1and1.com> <2A5F7B5367844CD2BFA54F09D89824B8@chimp> Message-ID: <5574060ce9fa6c638c8ed67cf89af18c@imap.1and1.com> >> >> I need to do this on a older kernel 2.6.10 and mmiotrace does not >> > support >> >> older kernels.... >> >> >> >> Any other suggestions? >> > >> > Does it run in a simulator or an emulator? SimNow or Qemu could log >> them >> > for you. >> > >> Can they simulate a Intel onboard graphics adapter? > > Probably not easily. Is the driver not open-source? I'm wondering why > you > couldn't recompile it for the newer kernel if you really want to use > MmioTrace. > That is were the problem lies. It is a prebuilt kernel module (*.ko) for 2.6.10... The source is not available. That is why I need to do a mmio trace to find out exactly what it is doing. If I had the source I would not need the trace. I wonder if I could backwards hack MmioTrace to work with the 2.6.10 kernel? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From p.brostovski at levigo.de Thu Mar 5 15:41:49 2009 From: p.brostovski at levigo.de (Piotr Brostovski) Date: Thu, 05 Mar 2009 15:41:49 +0100 Subject: [coreboot] coreboot+seabios+gpxe In-Reply-To: <20090304002642.GA32511@morn.localdomain> References: <49ADBB5C.6070302@julianfamily.org> <20090304002642.GA32511@morn.localdomain> Message-ID: <49AFE4AD.6070405@levigo.de> Hello, i tried recently also to combine coreboot+seabios+gpxe. Sadly it didn't work. Are my addresses correct? 0000:00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 78) 0000:01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3344 (rev 01) #define OPTIONROM_BDF_1 0x0100 #define OPTIONROM_MEM_1 0x1FF80000 #define OPTIONROM_BDF_2 0x0060 #define OPTIONROM_MEM_2 0x1FF70000 i have a 512KB rom. i put the vga rom in first place, then the gpxe rom and after them the coreboot rom. (cat video.rom gpxe-via.rom coreboot.rom > cb_seagpxe.rom) 64k video.rom bios and 64k gpxe-via.rom -- Piotr Kevin O'Connor schrieb: > Hi Joe, > > I'm CC'ing the coreboot mailing list. > >> #define OPTIONROM_BDF_1 0x0100 >> #define OPTIONROM_MEM_1 0xfffc0000 >> #define OPTIONROM_BDF_2 0x0048 >> #define OPTIONROM_MEM_2 0xfffcf800 >> >> Where do those addresses come from? > > The values are where the rom can be found in physical memory, and > which PCI device they correspond to. > > It's now possible to use a helper function when setting the BDF > values, so an equivalent of the above is: > > #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) > #define OPTIONROM_MEM_1 0xfffc0000 > #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0) > #define OPTIONROM_MEM_2 0xfffcf800 > > To find the PCI addresses, look at the lspci and find the device ids. > On my machine they are from: > > > For the memory addresses, I have a 256KiB chip, and the first rom is > located at the start of the chip - so it is 0x100000000 - 0x40000 = > 0xfffc0000. > From fengyuning1984 at gmail.com Thu Mar 5 15:45:05 2009 From: fengyuning1984 at gmail.com (FENG Yu Ning) Date: Thu, 5 Mar 2009 22:45:05 +0800 Subject: [coreboot] [PATCH] flashrom: Use helper functions to access flash chips In-Reply-To: <49AFD098.9000708@gmx.net> References: <49AFD098.9000708@gmx.net> Message-ID: Carl-Daniel Hailfinger wrote: > This patch has the additional advantage of removing lots of unnecessary > casts to volatile uint8_t * and now-superfluous parentheses which caused > poor readability. Generally, patched code looks much nicer. As a trade-off, some code loses symmetry, e.g. > - ? ? ? ? ? ? ? ? ? ? ? *dst = *src; > + ? ? ? ? ? ? ? ? ? ? ? writeb(*src, dst); > I used the semantic patcher Coccinelle to create this patch. That is interesting. I have a new tool to learn. The patch is Acked-by: FENG Yu Ning From mylesgw at gmail.com Thu Mar 5 16:01:22 2009 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 5 Mar 2009 08:01:22 -0700 Subject: [coreboot] coreboot+seabios+gpxe In-Reply-To: <49AFE4AD.6070405@levigo.de> References: <49ADBB5C.6070302@julianfamily.org> <20090304002642.GA32511@morn.localdomain> <49AFE4AD.6070405@levigo.de> Message-ID: <2831fecf0903050701t2d3459c5u8e55ccb104985e7e@mail.gmail.com> On Thu, Mar 5, 2009 at 7:41 AM, Piotr Brostovski wrote: > Hello, > > > i tried recently also to combine coreboot+seabios+gpxe. > Sadly it didn't work. > > Are my addresses correct? > > 0000:00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 78) > 0000:01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3344 (rev 01) > > #define OPTIONROM_BDF_1 0x0100 > #define OPTIONROM_MEM_1 0x1FF80000 > #define OPTIONROM_BDF_2 0x0060 > #define OPTIONROM_MEM_2 0x1FF70000 > > i have a 512KB rom. > i put the vga rom in first place, then the gpxe rom and after them the coreboot rom. > (cat video.rom ?gpxe-via.rom coreboot.rom > cb_seagpxe.rom) > 64k video.rom bios and 64k gpxe-via.rom They look wrong to me. Using the example below as a guide, I would have expected you to have: #define OPTIONROM_BDF_1 0x0100 #define OPTIONROM_MEM_1 0xFFF80000 #define OPTIONROM_BDF_2 0x0060 #define OPTIONROM_MEM_2 0xFFF80000 + 64*1024 or #define OPTIONROM_MEM_2 0xFFF90000 >> It's now possible to use a helper function when setting the BDF >> values, so an equivalent of the above is: >> >> #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) >> #define OPTIONROM_MEM_1 0xfffc0000 >> #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0) >> #define OPTIONROM_MEM_2 0xfffcf800 >> >> To find the PCI addresses, look at the lspci and find the device ids. >> On my machine they are from: >> >> >> For the memory addresses, I have a 256KiB chip, and the first rom is >> located at the start of the chip - so it is 0x100000000 - 0x40000 = >> 0xfffc0000. Thanks, Myles From marcj303 at gmail.com Thu Mar 5 16:31:21 2009 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 5 Mar 2009 08:31:21 -0700 Subject: [coreboot] [PATCH] Don't loop endlessly in get_pbus In-Reply-To: <49ADC1D3.4060808@gmx.net> References: <49ADC1D3.4060808@gmx.net> Message-ID: <534e5dc20903050731o2d39f94ci5af2b04dc4df2038@mail.gmail.com> On Tue, Mar 3, 2009 at 4:48 PM, Carl-Daniel Hailfinger wrote: > If get_pbus() is called for a device which has no parent/ancestor bus > with nonzero PCI bus operations, get_pbus() will get stuck in a silent > endless loop. > Detect the endless loop and break out with an error message. > > Such a situation can happen if the device tree is not yet > initialized/walked completely. > > This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was > used in early mainboard code for the AMD DBM690T. Instead, the code will > now die() with a meaningful error message. > > Thanks to Ward Vandewege for testing my patches to track down that bug. > > Signed-off-by: Carl-Daniel Hailfinger > > Index: LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c > =================================================================== > --- LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c ? ? ? (Revision 3967) > +++ LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c ? ? ? (Arbeitskopie) > @@ -28,6 +28,12 @@ > ?{ > ? ? ? ?struct bus *pbus = dev->bus; > ? ? ? ?while(pbus && pbus->dev && !ops_pci_bus(pbus)) { > + ? ? ? ? ? ? ? if (pbus == pbus->dev->bus) { > + ? ? ? ? ? ? ? ? ? ? ? printk_alert("%s in endless loop looking for a parent " > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "bus with ops_pci_bus for %s, breaking out\n", > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?__func__, dev_path(dev)); > + ? ? ? ? ? ? ? ? ? ? ? break; > + ? ? ? ? ? ? ? } > ? ? ? ? ? ? ? ?pbus = pbus->dev->bus; > ? ? ? ?} > ? ? ? ?if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { > > > -- > http://www.hailfinger.org/ Acked-by: Marc Jones From marcj303 at gmail.com Thu Mar 5 16:32:58 2009 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 5 Mar 2009 08:32:58 -0700 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <13426df10903031657p4986d276o4c518e6e2861a342@mail.gmail.com> References: <49ABF3E8.6070109@gmx.net> <13426df10903020717l79d946e1o4ee9411369cd3a08@mail.gmail.com> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> <49ADCF7D.6060700@gmx.net> <13426df10903031657p4986d276o4c518e6e2861a342@mail.gmail.com> Message-ID: <534e5dc20903050732j764a09eco3fe43100dd8e9ef9@mail.gmail.com> I like the pbus fail nicely patch but I don't think that this device tree change in the mainboard code is a good idea. Mainboard specific configuration is one area that coreboot doesn't handle very well. I think that the UMA setup is the only part that needs to be done before pci discovery. It would be ideal if we had a mainboard hook after discovery and before setup and enable. That probably isn't viable for v2. Maybe we should look at adding a mainboard device instead of chip to v3. Marc From p.brostovski at levigo.de Thu Mar 5 16:50:22 2009 From: p.brostovski at levigo.de (Piotr Brostovski) Date: Thu, 05 Mar 2009 16:50:22 +0100 Subject: [coreboot] coreboot+seabios+gpxe In-Reply-To: <2831fecf0903050701t2d3459c5u8e55ccb104985e7e@mail.gmail.com> References: <49ADBB5C.6070302@julianfamily.org> <20090304002642.GA32511@morn.localdomain> <49AFE4AD.6070405@levigo.de> <2831fecf0903050701t2d3459c5u8e55ccb104985e7e@mail.gmail.com> Message-ID: <49AFF4BE.8080205@levigo.de> Hi, ups, yes, thx! But something seem to be still wrong: Initializing VGA INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3344 rom base, size: fff80000 bus/devfn = 0x100 biosint: INT# 0xd biosint: eax 0x5f0b ebx 0x10100 ecx 0x44 edx 0x110 biosint: ebp 0x1df44 esp 0xfbe edi 0x44 esi 0x9bd7 biosint: ip 0xffff cs 0xf000 flags 0x16 biosint: Oops, exception 13 Stack contents: 0xffff 0xf000 0x0016 0xb9c2 0xc000 0x0006 0x0142 0xbee0 0x0142 0x0044 0x0044 0x9bd7 0xdf44 0x0fe2 0x0100 0x0110 0x0044 0 biosint: Bailing out .... elfboot: Attempting to load payload. rom_stream: 0xfffa0000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000 (cleaned up) New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000 Payload is overwriting Coreboot tables. Dropping non PT_LOAD segment Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x0000000000010000 Jumping to boot code at 0xfe2a7 Start bios CPU Mhz=798 bios_table_addr: 0x000f7950 end=0x000f8150 SMBIOS table addr=0x000f7950 Ram Size=0x1e000000 ... Scan for option roms Found option rom with bad checksum: loc=000c0000 len=55808 sum=000000e4 Changing serial settings was 00000003/00000002 now 00000003/00000000 enter handle_19: NULL -- Piotr Myles Watson schrieb: > On Thu, Mar 5, 2009 at 7:41 AM, Piotr Brostovski wrote: >> Hello, >> >> >> i tried recently also to combine coreboot+seabios+gpxe. >> Sadly it didn't work. >> >> Are my addresses correct? >> >> 0000:00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 78) >> 0000:01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3344 (rev 01) >> >> #define OPTIONROM_BDF_1 0x0100 >> #define OPTIONROM_MEM_1 0x1FF80000 >> #define OPTIONROM_BDF_2 0x0060 >> #define OPTIONROM_MEM_2 0x1FF70000 >> >> i have a 512KB rom. >> i put the vga rom in first place, then the gpxe rom and after them the coreboot rom. >> (cat video.rom gpxe-via.rom coreboot.rom > cb_seagpxe.rom) >> 64k video.rom bios and 64k gpxe-via.rom > > They look wrong to me. Using the example below as a guide, I would > have expected you to have: > #define OPTIONROM_BDF_1 0x0100 > #define OPTIONROM_MEM_1 0xFFF80000 > #define OPTIONROM_BDF_2 0x0060 > #define OPTIONROM_MEM_2 0xFFF80000 + 64*1024 > or > #define OPTIONROM_MEM_2 0xFFF90000 > > >>> It's now possible to use a helper function when setting the BDF >>> values, so an equivalent of the above is: >>> >>> #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) >>> #define OPTIONROM_MEM_1 0xfffc0000 >>> #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0) >>> #define OPTIONROM_MEM_2 0xfffcf800 >>> >>> To find the PCI addresses, look at the lspci and find the device ids. >>> On my machine they are from: >>> >>> >>> For the memory addresses, I have a 256KiB chip, and the first rom is >>> located at the start of the chip - so it is 0x100000000 - 0x40000 = >>> 0xfffc0000. > > Thanks, > Myles > From rminnich at gmail.com Thu Mar 5 17:49:44 2009 From: rminnich at gmail.com (ron minnich) Date: Thu, 5 Mar 2009 08:49:44 -0800 Subject: [coreboot] pci_read_config8 crash in mainboard.c In-Reply-To: <534e5dc20903050732j764a09eco3fe43100dd8e9ef9@mail.gmail.com> References: <49ABF3E8.6070109@gmx.net> <49ABFBA1.80709@gmx.net> <13426df10903020733j17f0414ewbbb66d5aa4fcb4ff@mail.gmail.com> <49ABFDFD.7080807@gmx.net> <49AD5CB9.1040701@gmx.net> <49AD652C.7070909@gmx.net> <534e5dc20903031022x3fe7faa9j26a1909c421949d@mail.gmail.com> <49ADCF7D.6060700@gmx.net> <13426df10903031657p4986d276o4c518e6e2861a342@mail.gmail.com> <534e5dc20903050732j764a09eco3fe43100dd8e9ef9@mail.gmail.com> Message-ID: <13426df10903050849m659f56dtb53500c1268f0b1c@mail.gmail.com> On Thu, Mar 5, 2009 at 7:32 AM, Marc Jones wrote: > Mainboard specific configuration is one area that coreboot doesn't > handle very well. I think that the UMA setup is the only part that > needs to be done before pci discovery. It would be ideal if we had a > mainboard hook after discovery and before setup and enable. That > probably isn't viable for v2. Maybe we should look at adding a > mainboard device instead of chip to v3. > good idea, not sure what it would look like, but I'd love to see a suggestion. ron From mylesgw at gmail.com Thu Mar 5 18:28:44 2009 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 5 Mar 2009 10:28:44 -0700 Subject: [coreboot] Coreboot patches for v2 with SeaBIOS In-Reply-To: <2831fecf0902271332u3ff15812m1943ca2bdfb85662@mail.gmail.com> References: <2831fecf0901201003p47a1a94cq407c22f552cc4ce4@mail.gmail.com> <2831fecf0901201055r9392a8frbce3b0a30e730446@mail.gmail.com> <49765989.4060203@coresystems.de> <2831fecf0902270942t316d4b42t5d07b890bfe80c4c@mail.gmail.com> <534e5dc20902270950tc7eb5e4o41629f64d07d4578@mail.gmail.com> <534e5dc20902271210g21751bfeoee14dafba87c5ecf@mail.gmail.com> <2831fecf0902271310t1d9c9f2fxf7597c30f45b046a@mail.gmail.com> <534e5dc20902271325s46294104jd7a2752d1452658c@mail.gmail.com> <2831fecf0902271332u3ff15812m1943ca2bdfb85662@mail.gmail.com> Message-ID: <2831fecf0903050928w408d4338rb6f0461f2c37b3a9@mail.gmail.com> On Fri, Feb 27, 2009 at 2:32 PM, Myles Watson wrote: > - Show quoted text - > On Fri, Feb 27, 2009 at 2:25 PM, Marc Jones wrote: >> On Fri, Feb 27, 2009 at 2:10 PM, Myles Watson wrote: >>> On Fri, Feb 27, 2009 at 1:10 PM, Marc Jones wrote: >>>> On Fri, Feb 27, 2009 at 12:40 PM, Myles Watson wrote: >>>>> >>>>> >>>>>> -----Original Message----- >>>>>> From: Marc Jones [mailto:marcj303 at gmail.com] >>>>>> Sent: Friday, February 27, 2009 10:51 AM >>>>>> To: Myles Watson >>>>>> Cc: Stefan Reinauer; Coreboot >>>>>> Subject: Re: [coreboot] Coreboot patches for v2 with SeaBIOS >>>>>> >>>>>> On Fri, Feb 27, 2009 at 10:42 AM, Myles Watson wrote: >>>>>> >>>>>> > Does this work for you with 4G of RAM? ?I don't have a Kontron board, >>>>>> > but I copied the implementation to the amdk8 northbridge code. ?It >>>>>> > works for me when I have the RAM "boosted" and it works when I boot >>>>>> > with less than 4G, but if I boot with 4G it tries to put the high >>>>>> > tables in the PCI decode space since they overlap. >>>>>> > >>>>>> > Besides that the patch is working well for me, and I'd like to see it >>>>>> merged. >>>>>> > >>>>>> > If it works in the 4G case and I just didn't implement it right for K8: >>>>>> > >>>>>> > Acked-by: Myles Watson >>>>>> > >>>>>> >>>>>> Do you have an off by 1 problem? That would cause the problem @ 4GB as >>>>>> you described. >>>>> >>>>> I'm confused ( again :) ) >>>>> >>>>> I'm not sure where the off by one problem would be. >>>>> >>>>> I thought the problem was that when you have the top of RAM at 0x100000000 >>>>> and then subtract some small number from it you end up at 0xffff0000, which >>>>> isn't where you should be accessing normal RAM, or reserving it for ACPI. >>>> >>>> I guess I didn't understand what you were saying. I assumed it was a >>>> problem with a size calculation at 4GB. If you have 4GB of memory it >>>> should hoist (boost) some portion of it. 512MB or 1GB typically. Is >>>> there a bug in the memory hoist code? Can you check what the tomk is >>>> with 4GB >>> >>> Sorry that took a while. ?Here are snippets of the output (full output attached) >>> >>> //4 GB getting cleared: >>> Setting up local apic... apic_id: 0x00 done. >>> Clearing memory 2048K - 4194304K: >>> --------------------------------------------------------------- done >>> CPU #0 initialized >>> ... >>> //This is from northbridge.c where I grabbed the space for the high tables: >>> 0: mmio_basek=003e0000, basek=003e0000, limitk=00400000 >> >> It looks like CONFIG_HW_MEM_HOLE_SIZEK might not be set. I don't think >> that you are getting any memory hoisted. You're right. > I guess I'll have to look into it more. > CONFIG_HW_MEM_HOLE_SIZEK = 1048576 > CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC = 0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... pci_domain_set_resources: HOLE_SIZEK=00100000, mmio_basek=003e0000 before hole check node 0 : mmio_basek=003e0000, basek=00000000, limitk=00400000 node 0 : mmio_basek=003e0000, basek=00000300, limitk=00400000 split needed: basek=00000300, limitk=00400000 first region of split: basek=00000300, pre_sizek=003dfd00 size left: sizek=00020000 node 0 at 30 basek=003e0000, sizek=00000000 0: mmio_basek=003e0000, basek=003e0000, limitk=00400000 40K table at =f7ff0000 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device It looks like it's using mmio_basek instead of limitk-HOLE_SIZEK for the first region. Then it doesn't do the second region. Thanks, Myles From c-d.hailfinger.devel.2006 at gmx.net Thu Mar 5 19:07:19 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 05 Mar 2009 19:07:19 +0100 Subject: [coreboot] [PATCH] flashrom: Use helper functions to access flash chips In-Reply-To: References: <49AFD098.9000708@gmx.net> Message-ID: <49B014D7.2040408@gmx.net> On 05.03.2009 15:45, FENG Yu Ning wrote: > Carl-Daniel Hailfinger wrote: > > >> This patch has the additional advantage of removing lots of unnecessary >> casts to volatile uint8_t * and now-superfluous parentheses which caused >> poor readability. >> > > Generally, patched code looks much nicer. As a trade-off, some code loses > symmetry, e.g. > > >> - *dst = *src; >> + writeb(*src, dst); >> True. >> I used the semantic patcher Coccinelle to create this patch. >> > > That is interesting. I have a new tool to learn. > > The patch is > > Acked-by: FENG Yu Ning > Thanks! I'll commit shortly. Below is the updated patch which performs the conversion completely. And the semantic patch shrunk quite a bit. @@ expression a; typedef uint8_t; volatile uint8_t *b; @@ - *(b) = (a); + writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + readb(b) @@ type T; T b; @@ ( readb | writeb ) (..., - (T) - (b) + b ) In contrast to a sed script, the semantic patch performs type checking before converting anything. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-inband_chipaccess_helper_functions/flash.h =================================================================== --- flashrom-inband_chipaccess_helper_functions/flash.h (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/flash.h (Arbeitskopie) @@ -58,6 +58,36 @@ #define INL inl #endif +static inline void writeb(uint8_t b, volatile void *addr) +{ + *(volatile uint8_t *) addr = b; +} + +static inline void writew(uint16_t b, volatile void *addr) +{ + *(volatile uint16_t *) addr = b; +} + +static inline void writel(uint32_t b, volatile void *addr) +{ + *(volatile uint32_t *) addr = b; +} + +static inline uint8_t readb(const volatile void *addr) +{ + return *(volatile uint8_t *) addr; +} + +static inline uint16_t readw(const volatile void *addr) +{ + return *(volatile uint16_t *) addr; +} + +static inline uint32_t readl(const volatile void *addr) +{ + return *(volatile uint32_t *) addr; +} + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { Index: flashrom-inband_chipaccess_helper_functions/pm49fl00x.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/pm49fl00x.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/pm49fl00x.c (Arbeitskopie) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - *(bios + (i * block_size) + 2) = bits; + writeb(bits, bios + (i * block_size) + 2); } } Index: flashrom-inband_chipaccess_helper_functions/en29f002a.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/en29f002a.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/en29f002a.c (Arbeitskopie) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = *(volatile uint8_t *)(bios + 0x100); - id2 = *(volatile uint8_t *)(bios + 0x101); + id1 = readb(bios + 0x100); + id2 = readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xF0; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0xAAA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0xAAA); + writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = *(volatile uint8_t *)(bios + 0x100); - id2 = *(volatile uint8_t *)(bios + 0x101); + id1 = readb(bios + 0x100); + id2 = readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0xAAA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xF0; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0xAAA); + writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0xA0; - *dst++ = *buf++; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); + writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Index: flashrom-inband_chipaccess_helper_functions/jedec.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/jedec.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/jedec.c (Arbeitskopie) @@ -40,10 +40,10 @@ unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = *dst & 0x40; + tmp1 = readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { - tmp2 = *dst & 0x40; + tmp2 = readb(dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -59,7 +59,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = *dst & 0x80; + tmp = readb(dst) & 0x80; if (tmp == data) { break; } @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x80; - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x20; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x80, bios + 0x5555); + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = *(volatile uint8_t *)(bios + 0x100); + id1 = readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = *(volatile uint8_t *)(bios + 0x101); + id2 = readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + page) = 0x30; + writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + block) = 0x50; + writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x10; + writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - *dst = *src; + writeb(*src, dst); dst++; src++; } @@ -238,7 +238,7 @@ src = s; ok = 1; for (i = 0; i < page_size; i++) { - if (*dst != *src) { + if (readb(dst) != *src) { ok = 0; break; } @@ -269,15 +269,15 @@ retry: /* Issue JEDEC Byte Program command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - *dst = *src; + writeb(*src, dst); toggle_ready_jedec(bios); - if (*dst != *src && tried++ < MAX_REFLASH_TRIES) { + if (readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } Index: flashrom-inband_chipaccess_helper_functions/w29ee011.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w29ee011.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/w29ee011.c (Arbeitskopie) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x60; + writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Index: flashrom-inband_chipaccess_helper_functions/sst49lfxxxc.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst49lfxxxc.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sst49lfxxxc.c (Arbeitskopie) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - *(bios + (i * 65536) + 2) = bits; + writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - *bios = SECTOR_ERASE; - *(bios + address) = ERASE; + writeb(SECTOR_ERASE, bios); + writeb(ERASE, bios + address); do { - status = *bios; + status = readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - *bios = AUTO_PGRM; - *dst++ = *src++; + writeb(AUTO_PGRM, bios); + writeb(*src++, dst++); do { - status = *bios; + status = readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - *bios = RESET; + writeb(RESET, bios); - *bios = READ_ID; - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + writeb(READ_ID, bios); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = RESET; + writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - *bios = RESET; + writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - *bios = RESET; + writeb(RESET, bios); return 0; } Index: flashrom-inband_chipaccess_helper_functions/sharplhf00l04.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sharplhf00l04.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sharplhf00l04.c (Arbeitskopie) @@ -41,23 +41,23 @@ #if 0 /* Enter ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); #endif - *bios = 0xff; + writeb(0xff, bios); myusec_delay(10); - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Leave ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - *bios = 0x70; - if ((*bios & 0x80) == 0) { // it's busy - while ((*bios & 0x80) == 0) ; + writeb(0x70, bios); + if ((readb(bios) & 0x80) == 0) { // it's busy + while ((readb(bios) & 0x80) == 0) ; } - status = *bios; + status = readb(bios); // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - *bios = 0x50; + writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); - printf("write protect is 0x%x\n", *(wrprotect)); - *(wrprotect) = 0; - printf("write protect is 0x%x\n", *(wrprotect)); + printf("write protect is 0x%x\n", readb(wrprotect)); + writeb(0, wrprotect); + printf("write protect is 0x%x\n", readb(wrprotect)); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_lhf00l04(bios); } } @@ -163,7 +163,7 @@ volatile uint8_t *bios = flash->virtual_memory; erase_lhf00l04(flash); - if (*bios != 0xff) { + if (readb(bios) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Index: flashrom-inband_chipaccess_helper_functions/w39v040c.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v040c.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/w39v040c.c (Arbeitskopie) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 1); - lock = *(volatile uint8_t *)(bios + 0xfff2); + id1 = readb(bios); + id2 = readb(bios + 1); + lock = readb(bios + 0xfff2); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Index: flashrom-inband_chipaccess_helper_functions/m29f002.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/m29f002.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/m29f002.c (Arbeitskopie) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x80; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x10; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x80, bios + 0x555); + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x80; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *dst = 0x30; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x80, bios + 0x555); + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xa0; - *dst = *src; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0xa0, bios + 0x555); + writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Index: flashrom-inband_chipaccess_helper_functions/sst28sf040.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst28sf040.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sst28sf040.c (Arbeitskopie) @@ -35,13 +35,13 @@ /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = *(volatile uint8_t *)(bios + 0x1823); - tmp = *(volatile uint8_t *)(bios + 0x1820); - tmp = *(volatile uint8_t *)(bios + 0x1822); - tmp = *(volatile uint8_t *)(bios + 0x0418); - tmp = *(volatile uint8_t *)(bios + 0x041B); - tmp = *(volatile uint8_t *)(bios + 0x0419); - tmp = *(volatile uint8_t *)(bios + 0x040A); + tmp = readb(bios + 0x1823); + tmp = readb(bios + 0x1820); + tmp = readb(bios + 0x1822); + tmp = readb(bios + 0x0418); + tmp = readb(bios + 0x041B); + tmp = readb(bios + 0x0419); + tmp = readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) @@ -49,20 +49,20 @@ /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = *(volatile uint8_t *)(bios + 0x1823); - tmp = *(volatile uint8_t *)(bios + 0x1820); - tmp = *(volatile uint8_t *)(bios + 0x1822); - tmp = *(volatile uint8_t *)(bios + 0x0418); - tmp = *(volatile uint8_t *)(bios + 0x041B); - tmp = *(volatile uint8_t *)(bios + 0x0419); - tmp = *(volatile uint8_t *)(bios + 0x041A); + tmp = readb(bios + 0x1823); + tmp = readb(bios + 0x1820); + tmp = readb(bios + 0x1822); + tmp = readb(bios + 0x0418); + tmp = readb(bios + 0x041B); + tmp = readb(bios + 0x0419); + tmp = readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - *bios = AUTO_PG_ERASE1; - *(bios + address) = AUTO_PG_ERASE2; + writeb(AUTO_PG_ERASE1, bios); + writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -85,8 +85,8 @@ continue; } /*issue AUTO PROGRAM command */ - *dst = AUTO_PGRM; - *dst++ = *src++; + writeb(AUTO_PGRM, dst); + writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -100,16 +100,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *bios = RESET; + writeb(RESET, bios); myusec_delay(10); - *bios = READ_ID; + writeb(READ_ID, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); myusec_delay(10); - id2 = *(volatile uint8_t *)(bios + 0x01); + id2 = readb(bios + 0x01); - *bios = RESET; + writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -124,8 +124,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - *bios = CHIP_ERASE; - *bios = CHIP_ERASE; + writeb(CHIP_ERASE, bios); + writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Index: flashrom-inband_chipaccess_helper_functions/stm50flw0x0x.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/stm50flw0x0x.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/stm50flw0x0x.c (Arbeitskopie) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = *(volatile uint8_t *)(bios + 0x100); + id1 = readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = *(volatile uint8_t *)(bios + 0x101); + id2 = readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - *bios = 0x70; - if ((*bios & 0x80) == 0) { // it's busy - while ((*bios & 0x80) == 0) ; + writeb(0x70, bios); + if ((readb(bios) & 0x80) == 0) { // it's busy + while ((readb(bios) & 0x80) == 0) ; } // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); } /* @@ -142,8 +142,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - *(flash_addr + offset + j) = unlock_sector; - if (*(flash_addr + offset + j) != unlock_sector) { + writeb(unlock_sector, flash_addr + offset + j); + if (readb(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -151,8 +151,8 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - *(flash_addr + offset) = unlock_sector; - if (*(flash_addr + offset) != unlock_sector) { + writeb(unlock_sector, flash_addr + offset); + if (readb(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -167,17 +167,17 @@ int j; // clear status register - *bios = 0x50; + writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); for (j = 0; j < flash->page_size; j++) { - if (*(bios + j) != 0xFF) { + if (readb(bios + j) != 0xFF) { printf("Erase failed at 0x%x\n", offset + j); return -1; } @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_stm50flw0x0x(bios); } @@ -210,7 +210,7 @@ dst = d; src = s; for (i = 0; i < page_size; i++) { - if (*dst != *src) { + if (readb(dst) != *src) { rc = -1; break; } Index: flashrom-inband_chipaccess_helper_functions/sst_fwhub.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Arbeitskopie) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - *(wrprotect) = 0; + writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Index: flashrom-inband_chipaccess_helper_functions/am29f040b.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/am29f040b.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/am29f040b.c (Arbeitskopie) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + address) = 0x30; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0xA0; - *dst++ = *src++; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0xA0, bios + 0x555); + writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x90, bios + 0x555); - id1 = *bios; - id2 = *(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x10; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-inband_chipaccess_helper_functions/w39v080fa.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Arbeitskopie) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = *(volatile uint8_t *)bios; - did = *(volatile uint8_t *)(bios + 0x01); + vid = readb(bios); + did = readb(bios + 0x01); /* Product Identifixation Exit */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -58,16 +58,16 @@ uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, - *wrprotect); + readb(wrprotect)); - locking = *wrprotect; + locking = readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = *(volatile uint8_t *)(bios + 0xffff2); + locking = readb(bios + 0xffff2); /* Product Identification Exit */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x80, bios + 0x5555); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + sector) = 0x30; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); Index: flashrom-inband_chipaccess_helper_functions/82802ab.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/82802ab.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/82802ab.c (Arbeitskopie) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); #endif - *bios = 0xff; + writeb(0xff, bios); myusec_delay(10); - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Leave ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - *bios = 0x70; - if ((*bios & 0x80) == 0) { // it's busy - while ((*bios & 0x80) == 0) ; + writeb(0x70, bios); + if ((readb(bios) & 0x80) == 0) { // it's busy + while ((readb(bios) & 0x80) == 0) ; } - status = *bios; + status = readb(bios); // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); return status; } @@ -115,23 +115,23 @@ uint8_t status; // clear status register - *bios = 0x50; + writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - *(wrprotect) = 0; + writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); for (j = 0; j < flash->page_size; j++) { - if (*(bios + j) != 0xFF) { + if (readb(bios + j) != 0xFF) { printf("BLOCK ERASE failed at 0x%x\n", offset); return -1; } @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_82802ab(bios); } } Index: flashrom-inband_chipaccess_helper_functions/m29f400bt.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/m29f400bt.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/m29f400bt.c (Arbeitskopie) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xA0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,18 +35,18 @@ int i; for (i = 0; i < page_size; i++) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xA0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - *dst = *src; + writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); printf ("Value in the flash at address %p = %#x, want %#x\n", - (uint8_t *) (dst - bios), *dst, *src); + (uint8_t *) (dst - bios), readb(dst), *src); dst++; src++; } @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x90; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = *(volatile uint8_t *)(bios + 0x02); + id2 = readb(bios + 0x02); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xF0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x80; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x80, bios + 0xAAA); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x10; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x80; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x80, bios + 0xAAA); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - *dst = 0x30; + writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-inband_chipaccess_helper_functions/mx29f002.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/mx29f002.c (Revision 3970) +++ flashrom-inband_chipaccess_helper_functions/mx29f002.c (Arbeitskopie) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(bios + 0x555) = 0xF0; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x10; + writeb(0xF0, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -65,12 +65,12 @@ #if 0 toggle_ready_jedec(bios); - *(bios + 0x0ffff) = 0x30; - *(bios + 0x1ffff) = 0x30; - *(bios + 0x2ffff) = 0x30; - *(bios + 0x37fff) = 0x30; - *(bios + 0x39fff) = 0x30; - *(bios + 0x3bfff) = 0x30; + writeb(0x30, bios + 0x0ffff); + writeb(0x30, bios + 0x1ffff); + writeb(0x30, bios + 0x2ffff); + writeb(0x30, bios + 0x37fff); + writeb(0x30, bios + 0x39fff); + writeb(0x30, bios + 0x3bfff); #endif return 0; @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0xA0; - *dst++ = *buf++; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); + writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_inband_chipaccess_helper_functions02.diff URL: From harald.gutmann at gmx.net Thu Mar 5 20:14:36 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Thu, 5 Mar 2009 20:14:36 +0100 Subject: [coreboot] ACPI/APIC related questions in coreboot. Message-ID: <200903052014.42570.harald.gutmann@gmx.net> Hello, at the moment i try to get acpi support running with the gigabyte m57sli mainboard. a few things are allready done (fill fadt, dsdt.asl and a pretty "raw" acpi_tables.c). Now my problem is, that i can't figure out the right values to set up the madt and mcfg acpi tables. On the coreboot wiki page according to acpi it's listed to check the source of asus/m2v-mx_se how to fill/create the madt tables. My problem for now is just, where do i find the right values to fill that table correctly? The values which are used in the example are alled #defined somewhere, but for mcp55 i couldn't find values which are defined somewhere and named the same style like those for via. Trying to set up the mcfg table i tried to "guess" the right value for finding the right "dev" to set it up at the correct address base. Here is my guessed suggest for the right values: dev = dev_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_PCI, 0); //or is PCI_DEVICE_ID_NVIDIA_MCP55_LPC correct if (!dev) return current; res = find_resource(dev, K8T890_MMCONFIG_MBAR); /*where to find the right value for mcp55 instead of k8t890? (guessing is not a really good idea, coreboot fails on bootup if that value doesn't exist.*/ if (res) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, res->base, 0x0, 0x0, 0xff); } What does work until now, nothing "great" but it seems that fadt is filled correctly and that the dsdt.asl file is also fine, but it's hard to verify when linux hangs after wring an error message that no lapic entries are present and that mmconfig has no entries. I'd be really glad to get some hints how/where i could find out the needed values. Kind regards, Harald Gutmann -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From svn at coreboot.org Thu Mar 5 20:24:22 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 5 Mar 2009 20:24:22 +0100 Subject: [coreboot] r3971 - trunk/util/flashrom Message-ID: Author: hailfinger Date: 2009-03-05 20:24:22 +0100 (Thu, 05 Mar 2009) New Revision: 3971 Modified: trunk/util/flashrom/82802ab.c trunk/util/flashrom/am29f040b.c trunk/util/flashrom/en29f002a.c trunk/util/flashrom/flash.h trunk/util/flashrom/jedec.c trunk/util/flashrom/m29f002.c trunk/util/flashrom/m29f400bt.c trunk/util/flashrom/mx29f002.c trunk/util/flashrom/pm49fl00x.c trunk/util/flashrom/sharplhf00l04.c trunk/util/flashrom/sst28sf040.c trunk/util/flashrom/sst49lfxxxc.c trunk/util/flashrom/sst_fwhub.c trunk/util/flashrom/stm50flw0x0x.c trunk/util/flashrom/w29ee011.c trunk/util/flashrom/w39v040c.c trunk/util/flashrom/w39v080fa.c Log: flashrom: Use helper functions to access flash chips. Right now we perform direct pointer manipulation without any abstraction to read from and write to memory mapped flash chips. That makes it impossible to drive any flasher which does not mmap the whole chip. Using helper functions readb() and writeb() allows a driver for external flash programmers like Paraflasher to replace readb and writeb with calls to its own chip access routines. This patch has the additional advantage of removing lots of unnecessary casts to volatile uint8_t * and now-superfluous parentheses which caused poor readability. I used the semantic patcher Coccinelle to create this patch. The semantic patch follows: @@ expression a; typedef uint8_t; volatile uint8_t *b; @@ - *(b) = (a); + writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + readb(b) @@ type T; T b; @@ ( readb | writeb ) (..., - (T) - (b) + b ) In contrast to a sed script, the semantic patch performs type checking before converting anything. Signed-off-by: Carl-Daniel Hailfinger Acked-by: FENG Yu Ning Tested-by: Joe Julian Modified: trunk/util/flashrom/82802ab.c =================================================================== --- trunk/util/flashrom/82802ab.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/82802ab.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); #endif - *bios = 0xff; + writeb(0xff, bios); myusec_delay(10); - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Leave ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - *bios = 0x70; - if ((*bios & 0x80) == 0) { // it's busy - while ((*bios & 0x80) == 0) ; + writeb(0x70, bios); + if ((readb(bios) & 0x80) == 0) { // it's busy + while ((readb(bios) & 0x80) == 0) ; } - status = *bios; + status = readb(bios); // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); return status; } @@ -115,23 +115,23 @@ uint8_t status; // clear status register - *bios = 0x50; + writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - *(wrprotect) = 0; + writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); for (j = 0; j < flash->page_size; j++) { - if (*(bios + j) != 0xFF) { + if (readb(bios + j) != 0xFF) { printf("BLOCK ERASE failed at 0x%x\n", offset); return -1; } @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_82802ab(bios); } } Modified: trunk/util/flashrom/am29f040b.c =================================================================== --- trunk/util/flashrom/am29f040b.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/am29f040b.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + address) = 0x30; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0xA0; - *dst++ = *src++; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0xA0, bios + 0x555); + writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x90, bios + 0x555); - id1 = *bios; - id2 = *(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x10; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Modified: trunk/util/flashrom/en29f002a.c =================================================================== --- trunk/util/flashrom/en29f002a.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/en29f002a.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = *(volatile uint8_t *)(bios + 0x100); - id2 = *(volatile uint8_t *)(bios + 0x101); + id1 = readb(bios + 0x100); + id2 = readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xF0; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0xAAA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x90; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0xAAA); + writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = *(volatile uint8_t *)(bios + 0x100); - id2 = *(volatile uint8_t *)(bios + 0x101); + id1 = readb(bios + 0x100); + id2 = readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - *(volatile uint8_t *)(bios + 0x555) = 0xAA; - *(volatile uint8_t *)(bios + 0xAAA) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xF0; + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0xAAA); + writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0xA0; - *dst++ = *buf++; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); + writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/flash.h 2009-03-05 19:24:22 UTC (rev 3971) @@ -58,6 +58,36 @@ #define INL inl #endif +static inline void writeb(uint8_t b, volatile void *addr) +{ + *(volatile uint8_t *) addr = b; +} + +static inline void writew(uint16_t b, volatile void *addr) +{ + *(volatile uint16_t *) addr = b; +} + +static inline void writel(uint32_t b, volatile void *addr) +{ + *(volatile uint32_t *) addr = b; +} + +static inline uint8_t readb(const volatile void *addr) +{ + return *(volatile uint8_t *) addr; +} + +static inline uint16_t readw(const volatile void *addr) +{ + return *(volatile uint16_t *) addr; +} + +static inline uint32_t readl(const volatile void *addr) +{ + return *(volatile uint32_t *) addr; +} + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { Modified: trunk/util/flashrom/jedec.c =================================================================== --- trunk/util/flashrom/jedec.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/jedec.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -40,10 +40,10 @@ unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = *dst & 0x40; + tmp1 = readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { - tmp2 = *dst & 0x40; + tmp2 = readb(dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -59,7 +59,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = *dst & 0x80; + tmp = readb(dst) & 0x80; if (tmp == data) { break; } @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x80; - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x20; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x80, bios + 0x5555); + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = *(volatile uint8_t *)(bios + 0x100); + id1 = readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = *(volatile uint8_t *)(bios + 0x101); + id2 = readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + page) = 0x30; + writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + block) = 0x50; + writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x10; + writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - *dst = *src; + writeb(*src, dst); dst++; src++; } @@ -238,7 +238,7 @@ src = s; ok = 1; for (i = 0; i < page_size; i++) { - if (*dst != *src) { + if (readb(dst) != *src) { ok = 0; break; } @@ -269,15 +269,15 @@ retry: /* Issue JEDEC Byte Program command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - *dst = *src; + writeb(*src, dst); toggle_ready_jedec(bios); - if (*dst != *src && tried++ < MAX_REFLASH_TRIES) { + if (readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } Modified: trunk/util/flashrom/m29f002.c =================================================================== --- trunk/util/flashrom/m29f002.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/m29f002.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x80; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x10; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x80, bios + 0x555); + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0x80; - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *dst = 0x30; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x80, bios + 0x555); + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - *(volatile uint8_t *)(bios + 0x555) = 0xaa; - *(volatile uint8_t *)(bios + 0xaaa) = 0x55; - *(volatile uint8_t *)(bios + 0x555) = 0xa0; - *dst = *src; + writeb(0xaa, bios + 0x555); + writeb(0x55, bios + 0xaaa); + writeb(0xa0, bios + 0x555); + writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Modified: trunk/util/flashrom/m29f400bt.c =================================================================== --- trunk/util/flashrom/m29f400bt.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/m29f400bt.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xA0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,18 +35,18 @@ int i; for (i = 0; i < page_size; i++) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xA0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - *dst = *src; + writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); printf ("Value in the flash at address %p = %#x, want %#x\n", - (uint8_t *) (dst - bios), *dst, *src); + (uint8_t *) (dst - bios), readb(dst), *src); dst++; src++; } @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x90; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = *(volatile uint8_t *)(bios + 0x02); + id2 = readb(bios + 0x02); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0xF0; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x80; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x80, bios + 0xAAA); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x10; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; - *(volatile uint8_t *)(bios + 0xAAA) = 0x80; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); + writeb(0x80, bios + 0xAAA); - *(volatile uint8_t *)(bios + 0xAAA) = 0xAA; - *(volatile uint8_t *)(bios + 0x555) = 0x55; + writeb(0xAA, bios + 0xAAA); + writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - *dst = 0x30; + writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Modified: trunk/util/flashrom/mx29f002.c =================================================================== --- trunk/util/flashrom/mx29f002.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/mx29f002.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - *(bios + 0x555) = 0xF0; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x80; - *(bios + 0x555) = 0xAA; - *(bios + 0x2AA) = 0x55; - *(bios + 0x555) = 0x10; + writeb(0xF0, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x80, bios + 0x555); + writeb(0xAA, bios + 0x555); + writeb(0x55, bios + 0x2AA); + writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -65,12 +65,12 @@ #if 0 toggle_ready_jedec(bios); - *(bios + 0x0ffff) = 0x30; - *(bios + 0x1ffff) = 0x30; - *(bios + 0x2ffff) = 0x30; - *(bios + 0x37fff) = 0x30; - *(bios + 0x39fff) = 0x30; - *(bios + 0x3bfff) = 0x30; + writeb(0x30, bios + 0x0ffff); + writeb(0x30, bios + 0x1ffff); + writeb(0x30, bios + 0x2ffff); + writeb(0x30, bios + 0x37fff); + writeb(0x30, bios + 0x39fff); + writeb(0x30, bios + 0x3bfff); #endif return 0; @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - *bios = 0xF0; + writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - *(bios + 0x5555) = 0xAA; - *(bios + 0x2AAA) = 0x55; - *(bios + 0x5555) = 0xA0; - *dst++ = *buf++; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); + writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Modified: trunk/util/flashrom/pm49fl00x.c =================================================================== --- trunk/util/flashrom/pm49fl00x.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/pm49fl00x.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - *(bios + (i * block_size) + 2) = bits; + writeb(bits, bios + (i * block_size) + 2); } } Modified: trunk/util/flashrom/sharplhf00l04.c =================================================================== --- trunk/util/flashrom/sharplhf00l04.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/sharplhf00l04.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -41,23 +41,23 @@ #if 0 /* Enter ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); #endif - *bios = 0xff; + writeb(0xff, bios); myusec_delay(10); - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Leave ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - *bios = 0x70; - if ((*bios & 0x80) == 0) { // it's busy - while ((*bios & 0x80) == 0) ; + writeb(0x70, bios); + if ((readb(bios) & 0x80) == 0) { // it's busy + while ((readb(bios) & 0x80) == 0) ; } - status = *bios; + status = readb(bios); // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - *bios = 0x50; + writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); - printf("write protect is 0x%x\n", *(wrprotect)); - *(wrprotect) = 0; - printf("write protect is 0x%x\n", *(wrprotect)); + printf("write protect is 0x%x\n", readb(wrprotect)); + writeb(0, wrprotect); + printf("write protect is 0x%x\n", readb(wrprotect)); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_lhf00l04(bios); } } @@ -163,7 +163,7 @@ volatile uint8_t *bios = flash->virtual_memory; erase_lhf00l04(flash); - if (*bios != 0xff) { + if (readb(bios) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Modified: trunk/util/flashrom/sst28sf040.c =================================================================== --- trunk/util/flashrom/sst28sf040.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/sst28sf040.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -35,13 +35,13 @@ /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = *(volatile uint8_t *)(bios + 0x1823); - tmp = *(volatile uint8_t *)(bios + 0x1820); - tmp = *(volatile uint8_t *)(bios + 0x1822); - tmp = *(volatile uint8_t *)(bios + 0x0418); - tmp = *(volatile uint8_t *)(bios + 0x041B); - tmp = *(volatile uint8_t *)(bios + 0x0419); - tmp = *(volatile uint8_t *)(bios + 0x040A); + tmp = readb(bios + 0x1823); + tmp = readb(bios + 0x1820); + tmp = readb(bios + 0x1822); + tmp = readb(bios + 0x0418); + tmp = readb(bios + 0x041B); + tmp = readb(bios + 0x0419); + tmp = readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) @@ -49,20 +49,20 @@ /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = *(volatile uint8_t *)(bios + 0x1823); - tmp = *(volatile uint8_t *)(bios + 0x1820); - tmp = *(volatile uint8_t *)(bios + 0x1822); - tmp = *(volatile uint8_t *)(bios + 0x0418); - tmp = *(volatile uint8_t *)(bios + 0x041B); - tmp = *(volatile uint8_t *)(bios + 0x0419); - tmp = *(volatile uint8_t *)(bios + 0x041A); + tmp = readb(bios + 0x1823); + tmp = readb(bios + 0x1820); + tmp = readb(bios + 0x1822); + tmp = readb(bios + 0x0418); + tmp = readb(bios + 0x041B); + tmp = readb(bios + 0x0419); + tmp = readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - *bios = AUTO_PG_ERASE1; - *(bios + address) = AUTO_PG_ERASE2; + writeb(AUTO_PG_ERASE1, bios); + writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -85,8 +85,8 @@ continue; } /*issue AUTO PROGRAM command */ - *dst = AUTO_PGRM; - *dst++ = *src++; + writeb(AUTO_PGRM, dst); + writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -100,16 +100,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - *bios = RESET; + writeb(RESET, bios); myusec_delay(10); - *bios = READ_ID; + writeb(READ_ID, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); myusec_delay(10); - id2 = *(volatile uint8_t *)(bios + 0x01); + id2 = readb(bios + 0x01); - *bios = RESET; + writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -124,8 +124,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - *bios = CHIP_ERASE; - *bios = CHIP_ERASE; + writeb(CHIP_ERASE, bios); + writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Modified: trunk/util/flashrom/sst49lfxxxc.c =================================================================== --- trunk/util/flashrom/sst49lfxxxc.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/sst49lfxxxc.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - *(bios + (i * 65536) + 2) = bits; + writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - *(bios + address + 2) = bits; + writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - *bios = SECTOR_ERASE; - *(bios + address) = ERASE; + writeb(SECTOR_ERASE, bios); + writeb(ERASE, bios + address); do { - status = *bios; + status = readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - *bios = AUTO_PGRM; - *dst++ = *src++; + writeb(AUTO_PGRM, bios); + writeb(*src++, dst++); do { - status = *bios; + status = readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - *bios = CLEAR_STATUS; + writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - *bios = RESET; + writeb(RESET, bios); - *bios = READ_ID; - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + writeb(READ_ID, bios); + id1 = readb(bios); + id2 = readb(bios + 0x01); - *bios = RESET; + writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - *bios = RESET; + writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - *bios = RESET; + writeb(RESET, bios); return 0; } Modified: trunk/util/flashrom/sst_fwhub.c =================================================================== --- trunk/util/flashrom/sst_fwhub.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/sst_fwhub.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - *(wrprotect) = 0; + writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Modified: trunk/util/flashrom/stm50flw0x0x.c =================================================================== --- trunk/util/flashrom/stm50flw0x0x.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/stm50flw0x0x.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xA0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = *(volatile uint8_t *)(bios + 0x100); + id1 = readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = *(volatile uint8_t *)(bios + 0x101); + id2 = readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - *bios = 0x70; - if ((*bios & 0x80) == 0) { // it's busy - while ((*bios & 0x80) == 0) ; + writeb(0x70, bios); + if ((readb(bios) & 0x80) == 0) { // it's busy + while ((readb(bios) & 0x80) == 0) ; } // put another command to get out of status register mode - *bios = 0x90; + writeb(0x90, bios); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; + id1 = readb(bios); // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); } /* @@ -142,8 +142,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - *(flash_addr + offset + j) = unlock_sector; - if (*(flash_addr + offset + j) != unlock_sector) { + writeb(unlock_sector, flash_addr + offset + j); + if (readb(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -151,8 +151,8 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - *(flash_addr + offset) = unlock_sector; - if (*(flash_addr + offset) != unlock_sector) { + writeb(unlock_sector, flash_addr + offset); + if (readb(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -167,17 +167,17 @@ int j; // clear status register - *bios = 0x50; + writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; + writeb(0x20, bios); + writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); for (j = 0; j < flash->page_size; j++) { - if (*(bios + j) != 0xFF) { + if (readb(bios + j) != 0xFF) { printf("Erase failed at 0x%x\n", offset + j); return -1; } @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - *dst = 0x40; - *dst++ = *src++; + writeb(0x40, dst); + writeb(*src++, dst++); wait_stm50flw0x0x(bios); } @@ -210,7 +210,7 @@ dst = d; src = s; for (i = 0; i < page_size; i++) { - if (*dst != *src) { + if (readb(dst) != *src) { rc = -1; break; } Modified: trunk/util/flashrom/w29ee011.c =================================================================== --- trunk/util/flashrom/w29ee011.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/w29ee011.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0x80, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x60; + writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); + id1 = readb(bios); + id2 = readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Modified: trunk/util/flashrom/w39v040c.c =================================================================== --- trunk/util/flashrom/w39v040c.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/w39v040c.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 1); - lock = *(volatile uint8_t *)(bios + 0xfff2); + id1 = readb(bios); + id2 = readb(bios + 1); + lock = readb(bios + 0xfff2); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + writeb(0xAA, bios + 0x5555); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + writeb(0x55, bios + 0x2AAA); myusec_delay(10); - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Modified: trunk/util/flashrom/w39v080fa.c =================================================================== --- trunk/util/flashrom/w39v080fa.c 2009-03-04 01:06:41 UTC (rev 3970) +++ trunk/util/flashrom/w39v080fa.c 2009-03-05 19:24:22 UTC (rev 3971) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = *(volatile uint8_t *)bios; - did = *(volatile uint8_t *)(bios + 0x01); + vid = readb(bios); + did = readb(bios + 0x01); /* Product Identifixation Exit */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -58,16 +58,16 @@ uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, - *wrprotect); + readb(wrprotect)); - locking = *wrprotect; + locking = readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - *wrprotect = 0; + writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = *(volatile uint8_t *)(bios + 0xffff2); + locking = readb(bios + 0xffff2); /* Product Identification Exit */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x80; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x80, bios + 0x5555); - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + sector) = 0x30; + writeb(0xAA, bios + 0x5555); + writeb(0x55, bios + 0x2AAA); + writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); From c-d.hailfinger.devel.2006 at gmx.net Thu Mar 5 20:26:20 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 05 Mar 2009 20:26:20 +0100 Subject: [coreboot] [PATCH] flashrom: Use helper functions to access flash chips In-Reply-To: <49B014D7.2040408@gmx.net> References: <49AFD098.9000708@gmx.net> <49B014D7.2040408@gmx.net> Message-ID: <49B0275C.3020807@gmx.net> On 05.03.2009 19:07, Carl-Daniel Hailfinger wrote: > On 05.03.2009 15:45, FENG Yu Ning wrote: > >> Carl-Daniel Hailfinger wrote: >> >> >>> I used the semantic patcher Coccinelle to create this patch. >>> >>> >> Acked-by: FENG Yu Ning >> >> > > Thanks! > > I'll commit shortly. Below is the updated patch which performs the > conversion completely. And the semantic patch shrunk quite a bit. > @@ > expression a; > typedef uint8_t; > volatile uint8_t *b; > @@ > - *(b) = (a); > + writeb(a, b); > @@ > volatile uint8_t *b; > @@ > - *(b) > + readb(b) > @@ > type T; > T b; > @@ > ( > readb > | > writeb > ) > (..., > - (T) > - (b) > + b > ) > > In contrast to a sed script, the semantic patch performs type checking > before converting anything. > > Signed-off-by: Carl-Daniel Hailfinger > Committed in r3971. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Thu Mar 5 20:33:12 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 5 Mar 2009 20:33:12 +0100 Subject: [coreboot] r3972 - trunk/coreboot-v2/src/devices Message-ID: Author: hailfinger Date: 2009-03-05 20:33:12 +0100 (Thu, 05 Mar 2009) New Revision: 3972 Modified: trunk/coreboot-v2/src/devices/pci_ops.c Log: If get_pbus() is called for a device which has no parent/ancestor bus with nonzero PCI bus operations, get_pbus() will get stuck in a silent endless loop. Detect the endless loop and break out with an error message. Such a situation can happen if the device tree is not yet initialized/walked completely. This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was used in early mainboard code for the AMD DBM690T. Instead, the code will now die() with a meaningful error message. Thanks to Ward Vandewege for testing my patches to track down that bug. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Marc Jones Modified: trunk/coreboot-v2/src/devices/pci_ops.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-05 19:24:22 UTC (rev 3971) +++ trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-05 19:33:12 UTC (rev 3972) @@ -28,6 +28,12 @@ { struct bus *pbus = dev->bus; while(pbus && pbus->dev && !ops_pci_bus(pbus)) { + if (pbus == pbus->dev->bus) { + printk_alert("%s in endless loop looking for a parent " + "bus with ops_pci_bus for %s, breaking out\n", + __func__, dev_path(dev)); + break; + } pbus = pbus->dev->bus; } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { From c-d.hailfinger.devel.2006 at gmx.net Thu Mar 5 20:34:04 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 05 Mar 2009 20:34:04 +0100 Subject: [coreboot] [PATCH] Don't loop endlessly in get_pbus In-Reply-To: <534e5dc20903050731o2d39f94ci5af2b04dc4df2038@mail.gmail.com> References: <49ADC1D3.4060808@gmx.net> <534e5dc20903050731o2d39f94ci5af2b04dc4df2038@mail.gmail.com> Message-ID: <49B0292C.9060905@gmx.net> On 05.03.2009 16:31, Marc Jones wrote: > On Tue, Mar 3, 2009 at 4:48 PM, Carl-Daniel Hailfinger > wrote: > >> If get_pbus() is called for a device which has no parent/ancestor bus >> with nonzero PCI bus operations, get_pbus() will get stuck in a silent >> endless loop. >> Detect the endless loop and break out with an error message. >> >> Such a situation can happen if the device tree is not yet >> initialized/walked completely. >> >> This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was >> used in early mainboard code for the AMD DBM690T. Instead, the code will >> now die() with a meaningful error message. >> >> Thanks to Ward Vandewege for testing my patches to track down that bug. >> >> Signed-off-by: Carl-Daniel Hailfinger >> >> > Acked-by: Marc Jones > Thanks, r3972. Regards, Carl-Daniel -- http://www.hailfinger.org/ From heiko at fedev.eu Wed Mar 4 18:30:01 2009 From: heiko at fedev.eu (heiko at fedev.eu) Date: Wed, 4 Mar 2009 18:30:01 +0100 Subject: [coreboot] VIA PC2500e-like board from ECS doesn't boot up In-Reply-To: <49A4A682.9020801@onelabs.com> References: <20090225013000.GM27618@lagrange.wgio.eu> <49A4A682.9020801@onelabs.com> Message-ID: <20090304173001.GB1959@mail.fedev.eu> On Tue, Feb 24, 2009 at 08:01:38PM -0600, bari wrote: > Heiko Weinen wrote: >> Hi everyone! >> >> I'm trying to make an Elitegroup (ECS) board run coreboot. Model >> specifics are ECS C7VCM2 rev.1.0 with: [..] > I have a couple of these. I'll take a look when I get a chance and let > you know what I find. The factory BIOS is one of the slowest booting I > have seen in >10 years. Thats exactly the reason why i'm trying to run coreboot on them. A boot takes ages with the original bios. Any news on the matter? Cheers, Heiko From mylesgw at gmail.com Thu Mar 5 21:38:24 2009 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 5 Mar 2009 13:38:24 -0700 Subject: [coreboot] ACPI/APIC related questions in coreboot. In-Reply-To: <200903052014.42570.harald.gutmann@gmx.net> References: <200903052014.42570.harald.gutmann@gmx.net> Message-ID: <2831fecf0903051238x1c67ae75vac895dacb49e1f4c@mail.gmail.com> On Thu, Mar 5, 2009 at 12:14 PM, Harald Gutmann wrote: > Hello, > > at the moment i try to get acpi support running with the gigabyte m57sli > mainboard. > a few things are allready done (fill fadt, dsdt.asl and a pretty "raw" > acpi_tables.c). > > Now my problem is, that i can't figure out the right values to set up the madt > and mcfg acpi tables. This might help: http://www.coreboot.org/pipermail/coreboot/2009-February/044809.html You actually don't need MCFG to boot Linux. > On the coreboot wiki page according to acpi it's listed to check the source of > asus/m2v-mx_se how to fill/create the madt tables. > > My problem for now is just, where do i find the right values to fill that table > correctly? The values which are used in the example are alled #defined > somewhere, but for mcp55 i couldn't find values which are defined somewhere and > named the same style like those for via. > > Trying to set up the mcfg table i tried to "guess" the right value for finding > the right "dev" to set it up at the correct address base. > Here is my guessed suggest for the right values: > > dev = dev_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_PCI, 0); > //or is PCI_DEVICE_ID_NVIDIA_MCP55_LPC correct > ? ? ? ?if (!dev) > ? ? ? ? ? ? ? ?return current; > > ? ? ? ?res = find_resource(dev, K8T890_MMCONFIG_MBAR); /*where to find the > right value for mcp55 instead of k8t890? (guessing is not a really good idea, > coreboot fails on bootup if that value doesn't exist.*/ > ? ? ? ?if (res) { > ? ? ? ? ? ? ? ?current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?current, res->base, 0x0, 0x0, 0xff); > ? ? ? ?} > > What does work until now, nothing "great" but it seems that fadt is filled > correctly and that the dsdt.asl file is also fine, but it's hard to verify when > linux hangs after wring an error message that no lapic entries are present and > that mmconfig has no entries. > I'd be really glad to get some hints how/where i could find out the needed > values. You could take a look at the patches I sent for the Tyan s2895, s2891, & s2892. http://www.coreboot.org/pipermail/coreboot/2009-February/045201.html I generated the dsdt from mptables.c, so it might be easier to see how to do that. I'm not booting Windows yet, but Linux is working flawlessly so far. Thanks, Myles From marcj303 at gmail.com Thu Mar 5 21:57:35 2009 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 5 Mar 2009 13:57:35 -0700 Subject: [coreboot] [patch][msrtool] Add K8 MSRs Message-ID: <534e5dc20903051257l7fc4a133j1fe7ebe78cfb0858@mail.gmail.com> Add K8 support for some of the more important MSRs. Signed-off-by: Marc Jones -------------- next part -------------- A non-text attachment was scrubbed... Name: k8.patch Type: application/octet-stream Size: 15124 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Thu Mar 5 22:22:52 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 05 Mar 2009 22:22:52 +0100 Subject: [coreboot] [patch][msrtool] Add K8 MSRs In-Reply-To: <534e5dc20903051257l7fc4a133j1fe7ebe78cfb0858@mail.gmail.com> References: <534e5dc20903051257l7fc4a133j1fe7ebe78cfb0858@mail.gmail.com> Message-ID: <49B042AC.6030909@gmx.net> On 05.03.2009 21:57, Marc Jones wrote: > Add K8 support for some of the more important MSRs. > > Signed-off-by: Marc Jones > If you fix the one bug mentioned below and can provide explanations/answers for my other questions, this is Acked-by: Carl-Daniel Hailfinger > + { 0xC001001A, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM Register", "This register indicates the first byte of I/O above DRAM", { > + { 63, 24, RESERVED }, > + { 39, 8, "TOM 16-9", "", PRESENT_HEX, { > I find the bit numbering in the description string here to be rather unintuitive. IIRC these bits here are not shifted, so "TOM 29-32" would be the correct name. > + { BITVAL_EOT } > + }}, > + { 31, 9, "TOM 8-0", "", PRESENT_HEX, { > Same here. > + { BITVAL_EOT } > + }}, > + { 22, 23, RESERVED }, > + { BITS_EOT } > + }}, > Can TOP_MEM really be larger than 4 GB? > + > + { 0xC001001D, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM2 Register", "This register indicates the Top of Memory above 4GB", { > + { 63, 24, RESERVED }, > + { 39, 8, "TOM2 16-9", "", PRESENT_HEX, { > Bit numbering. > + { BITVAL_EOT } > + }}, > + { 31, 9, "TOM2 8-0", "", PRESENT_HEX, { > Same here. > + { BITVAL_EOT } > + }}, > + { 22, 23, RESERVED }, > + { BITS_EOT } > + }}, > I thought newer AMD processors have more than 40 bit addressable memory. > + { 0xC0010019, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask0", "This register holds the mask of the variable I/O range", { > Should be IORRMask1. > + { 63, 24, RESERVED }, > + { 39, 8, "MASK 27-20", "", PRESENT_HEX, { > + { BITVAL_EOT } > + }}, > + { 31, 20, "MASK 20-0", "", PRESENT_HEX, { > + { BITVAL_EOT } > + }}, > + { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC, { > + { MSR1(0), "V I/O range disabled" }, > + { MSR1(1), "V I/O range enabled" }, > + { BITVAL_EOT } > + }}, > + { 10, 11, RESERVED }, > + { BITS_EOT } > + }}, > + > > Index: msrtool/msrutils.c > =================================================================== > --- msrtool.orig/msrutils.c 2009-03-05 11:58:19.000000000 -0700 > +++ msrtool/msrutils.c 2009-03-02 15:40:13.000000000 -0700 > @@ -137,7 +137,7 @@ > return NULL; > } > > -const uint32_t msraddrbyname(const char *name) { > +uint32_t msraddrbyname(const char *name) { > Any reason for the const removal? The changelog doesn't say anything about it. > uint8_t t; > const uint32_t addr = strtoul(name, NULL, 16); > const struct msrdef *m; > Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Thu Mar 5 22:28:56 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Thu, 5 Mar 2009 22:28:56 +0100 Subject: [coreboot] r1144 - coreboot-v3/util/x86emu/yabel Message-ID: Author: phueper Date: 2009-03-05 22:28:56 +0100 (Thu, 05 Mar 2009) New Revision: 1144 Modified: coreboot-v3/util/x86emu/yabel/io.c Log: YABEL: fix 32bit cf8/cfc PCI Config accesses Signed-off-by: Pattrick Hueper Acked-by: Carl-Daniel Hailfinger Modified: coreboot-v3/util/x86emu/yabel/io.c =================================================================== --- coreboot-v3/util/x86emu/yabel/io.c 2009-03-05 05:48:43 UTC (rev 1143) +++ coreboot-v3/util/x86emu/yabel/io.c 2009-03-05 21:28:56 UTC (rev 1144) @@ -348,7 +348,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) { u32 rval = 0xFFFFFFFF; - if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) { + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { // PCI Configuration Mechanism 1 step 1 // write to 0xCF8, sets bus, device, function and Config Space offset // later read from 0xCFC-0xCFF returns the value... @@ -404,7 +404,7 @@ void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) { - if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) { + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { // PCI Configuration Mechanism 1 step 1 // write to 0xCF8, sets bus, device, function and Config Space offset // later write to 0xCFC-0xCFF sets the value... From joe at settoplinux.org Thu Mar 5 22:49:19 2009 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 05 Mar 2009 16:49:19 -0500 Subject: [coreboot] [PATCH] flashrom: Use helper functions to access flash chips In-Reply-To: <49AFD098.9000708@gmx.net> References: <49AFD098.9000708@gmx.net> Message-ID: On Thu, 05 Mar 2009 14:16:08 +0100, Carl-Daniel Hailfinger wrote: > flashrom: Use helper functions to access flash chips. > > Right now we perform direct pointer manipulation without any abstraction > to read from and write to memory mapped flash chips. That makes it > impossible to drive any flasher which does not mmap the whole chip. > > Using helper functions readb() and writeb() allows a driver for external > flash programmers like Paraflasher to replace readb and writeb with > calls to its own chip access routines. > > This patch has the additional advantage of removing lots of unnecessary > casts to volatile uint8_t * and now-superfluous parentheses which caused > poor readability. > > Please note that this patch works, but the conversion is not complete > yet (reads outside assignments are not converted). > Sweet! Thanks for laying down the foundation for Paraflasher Carl-Daniel :-) I can't wait to get started. I just have to finish something else I am working on then it will be go time. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From marcj303 at gmail.com Thu Mar 5 23:57:59 2009 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 5 Mar 2009 15:57:59 -0700 Subject: [coreboot] [patch][msrtool] Add K8 MSRs In-Reply-To: <49B042AC.6030909@gmx.net> References: <534e5dc20903051257l7fc4a133j1fe7ebe78cfb0858@mail.gmail.com> <49B042AC.6030909@gmx.net> Message-ID: <534e5dc20903051457u54e5caf4m38565d4c244191fe@mail.gmail.com> On Thu, Mar 5, 2009 at 2:22 PM, Carl-Daniel Hailfinger wrote: > On 05.03.2009 21:57, Marc Jones wrote: >> Add K8 support for some of the more important MSRs. >> >> Signed-off-by: Marc Jones >> > > If you fix the one bug mentioned below and can provide > explanations/answers for my other questions, this is > Acked-by: Carl-Daniel Hailfinger > > >> + ? ? { 0xC001001A, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM Register", "This register indicates the first byte of I/O above DRAM", { >> + ? ? ? ? ? ? { 63, 24, RESERVED }, >> + ? ? ? ? ? ? { 39, 8, "TOM 16-9", "", PRESENT_HEX, { >> > > I find the bit numbering in the description string here to be rather > unintuitive. IIRC these bits here are not shifted, so "TOM 29-32" would > be the correct name. > Ok, changed. > Can TOP_MEM really be larger than 4 GB? I have never seen it but it seems so from the BKDG. You wouldn't be able to hoist them memory in the MMIO hole if you did it this way. > I thought newer AMD processors have more than 40 bit addressable memory. Fam10 does. > > >> + ? ? { 0xC0010019, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask0", "This register holds the mask of the variable I/O range", { >> > > Should be IORRMask1. > Fixed. >> -const uint32_t msraddrbyname(const char *name) { >> +uint32_t msraddrbyname(const char *name) { > > Any reason for the const removal? The changelog doesn't say anything > about it. > That was to get it to compile with -Werror which is on by default. It didn't look like that really needed to be a const. Marc From stepan at coresystems.de Fri Mar 6 00:09:09 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 00:09:09 +0100 Subject: [coreboot] [patch][msrtool] Add K8 MSRs In-Reply-To: <534e5dc20903051457u54e5caf4m38565d4c244191fe@mail.gmail.com> References: <534e5dc20903051257l7fc4a133j1fe7ebe78cfb0858@mail.gmail.com> <49B042AC.6030909@gmx.net> <534e5dc20903051457u54e5caf4m38565d4c244191fe@mail.gmail.com> Message-ID: <49B05B95.2070303@coresystems.de> Marc Jones wrote: >>> -const uint32_t msraddrbyname(const char *name) { >>> +uint32_t msraddrbyname(const char *name) { >>> >> Any reason for the const removal? The changelog doesn't say anything >> about it > > That was to get it to compile with -Werror which is on by default. It > didn't look like that really needed to be a const. > > Does the const make sense at all? It seems odd to define the variable integer return value of a function const. What's that supposed to be good for? Stefan -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 249 bytes Desc: OpenPGP digital signature URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Mar 6 00:23:45 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Mar 2009 00:23:45 +0100 Subject: [coreboot] [PATCH] flashrom: Remove superfluous volatile Message-ID: <49B05F01.2070406@gmx.net> During the conversion of flash chip accesses to helper functions, I spotted assignments to volatile variables which were neither placed inside the mmapped ROM area nor were they counters. Due to the use of accessor functions, volatile usage can be reduced significantly because the accessor functions take care of actually performing the reads/writes correctly. The following semantic patch spotted them: r exists@ expression b; typedef uint8_t; volatile uint8_t a; position p1; @@ a at p1 = readb(b); @script:python@ p1 << r.p1; a << r.a; b << r.b; @@ print "* file: %s line %s has assignment to unnecessarily volatile variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b) Result was: HANDLING: sst28sf040.c * file: sst28sf040.c line 44 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 43 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 42 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 41 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 40 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 39 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 38 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 58 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 57 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 56 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 55 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 54 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 53 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 52 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); From joe at settoplinux.org Fri Mar 6 00:59:07 2009 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 05 Mar 2009 18:59:07 -0500 Subject: [coreboot] [PATCH] flashrom: Remove superfluous volatile In-Reply-To: <49B05F01.2070406@gmx.net> References: <49B05F01.2070406@gmx.net> Message-ID: <80c0c058656cc28ba60698c721739a29@imap.1and1.com> On Fri, 06 Mar 2009 00:23:45 +0100, Carl-Daniel Hailfinger wrote: > During the conversion of flash chip accesses to helper functions, I > spotted assignments to volatile variables which were neither placed > inside the mmapped ROM area nor were they counters. > Due to the use of accessor functions, volatile usage can be reduced > significantly because the accessor functions take care of actually > performing the reads/writes correctly. > > The following semantic patch spotted them: > r exists@ > expression b; > typedef uint8_t; > volatile uint8_t a; > position p1; > @@ > a at p1 = readb(b); > > @script:python@ > p1 << r.p1; > a << r.a; > b << r.b; > @@ > print "* file: %s line %s has assignment to unnecessarily volatile > variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b) > > Result was: > HANDLING: sst28sf040.c > * file: sst28sf040.c line 44 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 43 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 42 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 41 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 40 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 39 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 38 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 58 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 57 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 56 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 55 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 54 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 53 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > * file: sst28sf040.c line 52 has assignment to unnecessarily volatile > variable: tmp = readb(TODO: Binary); > > From that result, the fix was obvious: > > Signed-off-by: Carl-Daniel Hailfinger Acked-by: Joseph Smith Good find. Looks like your having fun with the semantic patching :-) > > Index: flashrom-unneeded_volatile/sst28sf040.c > =================================================================== > --- flashrom-unneeded_volatile/sst28sf040.c (Revision 3971) > +++ flashrom-unneeded_volatile/sst28sf040.c (Arbeitskopie) > @@ -32,8 +32,7 @@ > > static __inline__ void protect_28sf040(volatile uint8_t *bios) > { > - /* ask compiler not to optimize this */ > - volatile uint8_t tmp; > + uint8_t tmp; > > tmp = readb(bios + 0x1823); > tmp = readb(bios + 0x1820); > @@ -46,8 +45,7 @@ > > static __inline__ void unprotect_28sf040(volatile uint8_t *bios) > { > - /* ask compiler not to optimize this */ > - volatile uint8_t tmp; > + uint8_t tmp; > > tmp = readb(bios + 0x1823); > tmp = readb(bios + 0x1820); > > > -- > http://www.hailfinger.org/ -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From svn at coreboot.org Fri Mar 6 01:40:25 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 01:40:25 +0100 Subject: [coreboot] r3973 - trunk/util/flashrom Message-ID: Author: hailfinger Date: 2009-03-06 01:40:25 +0100 (Fri, 06 Mar 2009) New Revision: 3973 Modified: trunk/util/flashrom/sst28sf040.c Log: During the conversion of flash chip accesses to helper functions, I spotted assignments to volatile variables which were neither placed inside the mmapped ROM area nor were they counters. Due to the use of accessor functions, volatile usage can be reduced significantly because the accessor functions take care of actually performing the reads/writes correctly. The following semantic patch spotted them (linebreak in python string for readability reasons, please remove before usage): @r exists@ expression b; typedef uint8_t; volatile uint8_t a; position p1; @@ a at p1 = readb(b); @script:python@ p1 << r.p1; a << r.a; b << r.b; @@ print "* file: %s line %s has assignment to unnecessarily volatile variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b) Result was: HANDLING: sst28sf040.c * file: sst28sf040.c line 44 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 43 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 42 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 41 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 40 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 39 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 38 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 58 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 57 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 56 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 55 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 54 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 53 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 52 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); The following semantic patch uses the spatch builtin match printing functionality by prepending a "*" to the line with the pattern: @@ expression b; typedef uint8_t; volatile uint8_t a; @@ * a = readb(b); Result is: HANDLING: sst28sf040.c diff = --- sst28sf040.c 2009-03-06 01:04:49.000000000 +0100 @@ -35,13 +35,6 @@ static __inline__ void protect_28sf040(v /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) @@ -49,13 +42,6 @@ static __inline__ void unprotect_28sf040 /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, It's arguably a bit easier to read if you get used to the leading "-" for matching lines. This patch was enabled by Coccinelle: http://www.emn.fr/x-info/coccinelle/ Signed-off-by: Carl-Daniel Hailfinger Acked-by: Joseph Smith -- http://www.hailfinger.org/ Modified: trunk/util/flashrom/sst28sf040.c =================================================================== --- trunk/util/flashrom/sst28sf040.c 2009-03-05 19:33:12 UTC (rev 3972) +++ trunk/util/flashrom/sst28sf040.c 2009-03-06 00:40:25 UTC (rev 3973) @@ -32,8 +32,7 @@ static __inline__ void protect_28sf040(volatile uint8_t *bios) { - /* ask compiler not to optimize this */ - volatile uint8_t tmp; + uint8_t tmp; tmp = readb(bios + 0x1823); tmp = readb(bios + 0x1820); @@ -46,8 +45,7 @@ static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { - /* ask compiler not to optimize this */ - volatile uint8_t tmp; + uint8_t tmp; tmp = readb(bios + 0x1823); tmp = readb(bios + 0x1820); From c-d.hailfinger.devel.2006 at gmx.net Fri Mar 6 01:41:20 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Mar 2009 01:41:20 +0100 Subject: [coreboot] [PATCH] flashrom: Remove superfluous volatile In-Reply-To: <80c0c058656cc28ba60698c721739a29@imap.1and1.com> References: <49B05F01.2070406@gmx.net> <80c0c058656cc28ba60698c721739a29@imap.1and1.com> Message-ID: <49B07130.5080004@gmx.net> On 06.03.2009 00:59, Joseph Smith wrote: > On Fri, 06 Mar 2009 00:23:45 +0100, Carl-Daniel Hailfinger > wrote: > >> During the conversion of flash chip accesses to helper functions, I >> spotted assignments to volatile variables which were neither placed >> inside the mmapped ROM area nor were they counters. >> Due to the use of accessor functions, volatile usage can be reduced >> significantly because the accessor functions take care of actually >> performing the reads/writes correctly. >> >> The following semantic patch spotted them: >> r exists@ >> expression b; >> typedef uint8_t; >> volatile uint8_t a; >> position p1; >> @@ >> a at p1 = readb(b); >> >> @script:python@ >> p1 << r.p1; >> a << r.a; >> b << r.b; >> @@ >> print "* file: %s line %s has assignment to unnecessarily volatile >> variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b) >> >> Result was: >> HANDLING: sst28sf040.c >> * file: sst28sf040.c line 44 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 43 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 42 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 41 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 40 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 39 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 38 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 58 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 57 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 56 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 55 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 54 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 53 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> * file: sst28sf040.c line 52 has assignment to unnecessarily volatile >> variable: tmp = readb(TODO: Binary); >> >> From that result, the fix was obvious: >> >> Signed-off-by: Carl-Daniel Hailfinger >> > Acked-by: Joseph Smith > > Good find. Looks like your having fun with the semantic patching :-) > Thanks. By the way, the following semantic patch uses the builtin match printing functionality by prepending a "*" to the line with the pattern: @@ expression b; typedef uint8_t; volatile uint8_t a; @@ * a = readb(b); Result is: HANDLING: sst28sf040.c diff = --- sst28sf040.c 2009-03-06 01:04:49.000000000 +0100 @@ -35,13 +35,6 @@ static __inline__ void protect_28sf040(v /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) @@ -49,13 +42,6 @@ static __inline__ void unprotect_28sf040 /* ask compiler not to optimize this */ volatile uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, It's arguably a bit easier to read if you get used to the leading "-" for matching lines. This patch was enabled by Coccinelle: http://www.emn.fr/x-info/coccinelle/ Committed in r3973. Regards, Carl-Daniel -- http://www.hailfinger.org/ From kevin at koconnor.net Fri Mar 6 01:59:30 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Thu, 5 Mar 2009 19:59:30 -0500 Subject: [coreboot] coreboot+seabios+gpxe In-Reply-To: <49AFF4BE.8080205@levigo.de> References: <49ADBB5C.6070302@julianfamily.org> <20090304002642.GA32511@morn.localdomain> <49AFE4AD.6070405@levigo.de> <2831fecf0903050701t2d3459c5u8e55ccb104985e7e@mail.gmail.com> <49AFF4BE.8080205@levigo.de> Message-ID: <20090306005930.GA28268@morn.localdomain> On Thu, Mar 05, 2009 at 04:50:22PM +0100, Piotr Brostovski wrote: > Hi, > ups, yes, thx! > > > But something seem to be still wrong: > > Initializing VGA > INSTALL REAL-MODE IDT > DO THE VGA BIOS > found VGA: vid=1106, did=3344 > rom base, size: fff80000 > bus/devfn = 0x100 > biosint: INT# 0xd > biosint: eax 0x5f0b ebx 0x10100 ecx 0x44 edx 0x110 > biosint: ebp 0x1df44 esp 0xfbe edi 0x44 esi 0x9bd7 > biosint: ip 0xffff cs 0xf000 flags 0x16 > biosint: Oops, exception 13 You should disable coreboot from running the vga rom. Only SeaBIOS should launch it. [...] > Scan for option roms > Found option rom with bad checksum: loc=000c0000 len=55808 sum=000000e4 > Changing serial settings was 00000003/00000002 now 00000003/00000000 > enter handle_19: > NULL Make sure CONFIG_OPTIONROMS_DEPLOYED is 0 in src/config.h [...] > >> 0000:00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 78) > >> 0000:01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3344 (rev 01) > >> > >> #define OPTIONROM_BDF_1 0x0100 > >> #define OPTIONROM_MEM_1 0x1FF80000 > >> #define OPTIONROM_BDF_2 0x0060 > >> #define OPTIONROM_MEM_2 0x1FF70000 This looks wrong - please use: #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) #define OPTIONROM_MEM_1 0xFFF80000 #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x12, 0) #define OPTIONROM_MEM_2 (0xFFF80000 + 64*1024) -Kevin From r.marek at assembler.cz Fri Mar 6 10:08:03 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 06 Mar 2009 10:08:03 +0100 Subject: [coreboot] Problems about booting windows xp In-Reply-To: References: <20090118021006.GA14386@morn.localdomain> <49759968.8040907@assembler.cz> <49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz> Message-ID: <49B0E7F3.2070505@assembler.cz> Hi, > I changed the dsdt.asl which take M2V-MX as an example. > Now it stopped rebooting, but after the window xp scroll bar it > hangs up, which supposed to show the log in screen. I am wondering > if there is any another places should be fixed. Huh did not experienced such hang, try booting with VGA failsafe. > And also in /src/arch/i386/boot/tables.c( function: write_tables line92) > I changed rom_table_start=((512-64)*1024*1024)-64*1024 followed by an > patch, > May be it is wrong ,which address should I changed in this places? it means put table on last 64kb on adderess 512MB-64MB. The -64MB is there because of integrated framebuffer. If you are not using it, you can put it anywhere in the memory >>1MB Does linux still work with all that changes? Thanks, Rudolf From Qingpei.Wang at amd.com Fri Mar 6 10:43:48 2009 From: Qingpei.Wang at amd.com (Wang, Qingpei) Date: Fri, 6 Mar 2009 17:43:48 +0800 Subject: [coreboot] Problems about booting windows xp In-Reply-To: <49B0E7F3.2070505@assembler.cz> References: <20090118021006.GA14386@morn.localdomain> <49759968.8040907@assembler.cz> <49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz> <49B0E7F3.2070505@assembler.cz> Message-ID: Hi, Today I tried to install a pure new windows xp which seabios in dbm690t it Hand off as show figure. I also put my dmes.txt here and e820 map also data.txt from acpidump. It all works fine with linux. As my dbm690t has 1G Ram, so I Take (1024-128)*1024*1024-64)1024. By the way, is there anybody who know how to use acpiexec? I can not use it smoothly. Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD) -----Original Message----- From: Rudolf Marek [mailto:r.marek at assembler.cz] Sent: Friday, March 06, 2009 5:08 PM To: Wang, Qingpei Cc: Coreboot; Perley, Tim Subject: Re: [coreboot] Problems about booting windows xp Hi, > I changed the dsdt.asl which take M2V-MX as an example. > Now it stopped rebooting, but after the window xp scroll bar it > hangs up, which supposed to show the log in screen. I am wondering > if there is any another places should be fixed. Huh did not experienced such hang, try booting with VGA failsafe. > And also in /src/arch/i386/boot/tables.c( function: write_tables line92) > I changed rom_table_start=((512-64)*1024*1024)-64*1024 followed by an > patch, > May be it is wrong ,which address should I changed in this places? it means put table on last 64kb on adderess 512MB-64MB. The -64MB is there because of integrated framebuffer. If you are not using it, you can put it anywhere in the memory >>1MB Does linux still work with all that changes? Thanks, Rudolf -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: data-linux.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: dmseg.txt URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: e820.txt URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Picture 002.jpg Type: image/jpeg Size: 23872 bytes Desc: Picture 002.jpg URL: From c-d.hailfinger.devel.2006 at gmx.net Fri Mar 6 15:08:45 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Mar 2009 15:08:45 +0100 Subject: [coreboot] [PATCH] flashrom: Rename chip accessor functions Message-ID: <49B12E6D.6070906@gmx.net> FreeBSD definitions of (read|write)[bwl] collide with our own. Before we attempt trickery, we can simply rename the accessor functions. Signed-off-by: Carl-Daniel Hailfinger Index: flashrom-rename_chip_accessors/flash.h =================================================================== --- flashrom-rename_chip_accessors/flash.h (Revision 3973) +++ flashrom-rename_chip_accessors/flash.h (Arbeitskopie) @@ -58,32 +58,32 @@ #define INL inl #endif -static inline void writeb(uint8_t b, volatile void *addr) +static inline void chip_writeb(uint8_t b, volatile void *addr) { *(volatile uint8_t *) addr = b; } -static inline void writew(uint16_t b, volatile void *addr) +static inline void chip_writew(uint16_t b, volatile void *addr) { *(volatile uint16_t *) addr = b; } -static inline void writel(uint32_t b, volatile void *addr) +static inline void chip_writel(uint32_t b, volatile void *addr) { *(volatile uint32_t *) addr = b; } -static inline uint8_t readb(const volatile void *addr) +static inline uint8_t chip_readb(const volatile void *addr) { return *(volatile uint8_t *) addr; } -static inline uint16_t readw(const volatile void *addr) +static inline uint16_t chip_readw(const volatile void *addr) { return *(volatile uint16_t *) addr; } -static inline uint32_t readl(const volatile void *addr) +static inline uint32_t chip_readl(const volatile void *addr) { return *(volatile uint32_t *) addr; } Index: flashrom-rename_chip_accessors/pm49fl00x.c =================================================================== --- flashrom-rename_chip_accessors/pm49fl00x.c (Revision 3973) +++ flashrom-rename_chip_accessors/pm49fl00x.c (Arbeitskopie) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - writeb(bits, bios + (i * block_size) + 2); + chip_writeb(bits, bios + (i * block_size) + 2); } } Index: flashrom-rename_chip_accessors/en29f002a.c =================================================================== --- flashrom-rename_chip_accessors/en29f002a.c (Revision 3973) +++ flashrom-rename_chip_accessors/en29f002a.c (Arbeitskopie) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Index: flashrom-rename_chip_accessors/jedec.c =================================================================== --- flashrom-rename_chip_accessors/jedec.c (Revision 3973) +++ flashrom-rename_chip_accessors/jedec.c (Arbeitskopie) @@ -40,10 +40,10 @@ unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = readb(dst) & 0x40; + tmp1 = chip_readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { - tmp2 = readb(dst) & 0x40; + tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -59,7 +59,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = readb(dst) & 0x80; + tmp = chip_readb(dst) & 0x80; if (tmp == data) { break; } @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x20, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x30, bios + page); + chip_writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x50, bios + block); + chip_writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x10, bios + 0x5555); + chip_writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - writeb(*src, dst); + chip_writeb(*src, dst); dst++; src++; } @@ -238,7 +238,7 @@ src = s; ok = 1; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { ok = 0; break; } @@ -269,15 +269,15 @@ retry: /* Issue JEDEC Byte Program command */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); toggle_ready_jedec(bios); - if (readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { + if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } Index: flashrom-rename_chip_accessors/w29ee011.c =================================================================== --- flashrom-rename_chip_accessors/w29ee011.c (Revision 3973) +++ flashrom-rename_chip_accessors/w29ee011.c (Arbeitskopie) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x60, bios + 0x5555); + chip_writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Index: flashrom-rename_chip_accessors/sst49lfxxxc.c =================================================================== --- flashrom-rename_chip_accessors/sst49lfxxxc.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst49lfxxxc.c (Arbeitskopie) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - writeb(bits, bios + (i * 65536) + 2); + chip_writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - writeb(SECTOR_ERASE, bios); - writeb(ERASE, bios + address); + chip_writeb(SECTOR_ERASE, bios); + chip_writeb(ERASE, bios + address); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, bios); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, bios); + chip_writeb(*src++, dst++); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); - writeb(READ_ID, bios); - id1 = readb(bios); - id2 = readb(bios + 0x01); + chip_writeb(READ_ID, bios); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } Index: flashrom-rename_chip_accessors/sharplhf00l04.c =================================================================== --- flashrom-rename_chip_accessors/sharplhf00l04.c (Revision 3973) +++ flashrom-rename_chip_accessors/sharplhf00l04.c (Arbeitskopie) @@ -41,23 +41,23 @@ #if 0 /* Enter ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); - printf("write protect is 0x%x\n", readb(wrprotect)); - writeb(0, wrprotect); - printf("write protect is 0x%x\n", readb(wrprotect)); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); + chip_writeb(0, wrprotect); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_lhf00l04(bios); } } @@ -163,7 +163,7 @@ volatile uint8_t *bios = flash->virtual_memory; erase_lhf00l04(flash); - if (readb(bios) != 0xff) { + if (chip_readb(bios) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Index: flashrom-rename_chip_accessors/m29f002.c =================================================================== --- flashrom-rename_chip_accessors/m29f002.c (Revision 3973) +++ flashrom-rename_chip_accessors/m29f002.c (Arbeitskopie) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x10, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x30, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0xa0, bios + 0x555); - writeb(*src, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0xa0, bios + 0x555); + chip_writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Index: flashrom-rename_chip_accessors/w39v040c.c =================================================================== --- flashrom-rename_chip_accessors/w39v040c.c (Revision 3973) +++ flashrom-rename_chip_accessors/w39v040c.c (Arbeitskopie) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 1); - lock = readb(bios + 0xfff2); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 1); + lock = chip_readb(bios + 0xfff2); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Index: flashrom-rename_chip_accessors/sst28sf040.c =================================================================== --- flashrom-rename_chip_accessors/sst28sf040.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst28sf040.c (Arbeitskopie) @@ -34,33 +34,33 @@ { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x040A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x041A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - writeb(AUTO_PG_ERASE1, bios); - writeb(AUTO_PG_ERASE2, bios + address); + chip_writeb(AUTO_PG_ERASE1, bios); + chip_writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -83,8 +83,8 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, dst); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, dst); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -98,16 +98,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); - writeb(READ_ID, bios); + chip_writeb(READ_ID, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); myusec_delay(10); - id2 = readb(bios + 0x01); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -122,8 +122,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - writeb(CHIP_ERASE, bios); - writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Index: flashrom-rename_chip_accessors/stm50flw0x0x.c =================================================================== --- flashrom-rename_chip_accessors/stm50flw0x0x.c (Revision 3973) +++ flashrom-rename_chip_accessors/stm50flw0x0x.c (Arbeitskopie) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); } /* @@ -142,8 +142,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - writeb(unlock_sector, flash_addr + offset + j); - if (readb(flash_addr + offset + j) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset + j); + if (chip_readb(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -151,8 +151,8 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - writeb(unlock_sector, flash_addr + offset); - if (readb(flash_addr + offset) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset); + if (chip_readb(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -167,17 +167,17 @@ int j; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("Erase failed at 0x%x\n", offset + j); return -1; } @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_stm50flw0x0x(bios); } @@ -210,7 +210,7 @@ dst = d; src = s; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { rc = -1; break; } Index: flashrom-rename_chip_accessors/am29f040b.c =================================================================== --- flashrom-rename_chip_accessors/am29f040b.c (Revision 3973) +++ flashrom-rename_chip_accessors/am29f040b.c (Arbeitskopie) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x30, bios + address); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xA0, bios + 0x555); - writeb(*src++, dst++); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xA0, bios + 0x555); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/sst_fwhub.c =================================================================== --- flashrom-rename_chip_accessors/sst_fwhub.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst_fwhub.c (Arbeitskopie) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - writeb(0, wrprotect); + chip_writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Index: flashrom-rename_chip_accessors/w39v080fa.c =================================================================== --- flashrom-rename_chip_accessors/w39v080fa.c (Revision 3973) +++ flashrom-rename_chip_accessors/w39v080fa.c (Arbeitskopie) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = readb(bios); - did = readb(bios + 0x01); + vid = chip_readb(bios); + did = chip_readb(bios + 0x01); /* Product Identifixation Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -58,16 +58,16 @@ uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, - readb(wrprotect)); + chip_readb(wrprotect)); - locking = readb(wrprotect); + locking = chip_readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = readb(bios + 0xffff2); + locking = chip_readb(bios + 0xffff2); /* Product Identification Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x30, bios + sector); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/82802ab.c =================================================================== --- flashrom-rename_chip_accessors/82802ab.c (Revision 3973) +++ flashrom-rename_chip_accessors/82802ab.c (Arbeitskopie) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -115,23 +115,23 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("BLOCK ERASE failed at 0x%x\n", offset); return -1; } @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_82802ab(bios); } } Index: flashrom-rename_chip_accessors/m29f400bt.c =================================================================== --- flashrom-rename_chip_accessors/m29f400bt.c (Revision 3973) +++ flashrom-rename_chip_accessors/m29f400bt.c (Arbeitskopie) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,18 +35,18 @@ int i; for (i = 0; i < page_size; i++) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); printf ("Value in the flash at address %p = %#x, want %#x\n", - (uint8_t *) (dst - bios), readb(dst), *src); + (uint8_t *) (dst - bios), chip_readb(dst), *src); dst++; src++; } @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x90, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = readb(bios + 0x02); + id2 = chip_readb(bios + 0x02); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xF0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x10, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - writeb(0x30, dst); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/mx29f002.c =================================================================== --- flashrom-rename_chip_accessors/mx29f002.c (Revision 3973) +++ flashrom-rename_chip_accessors/mx29f002.c (Arbeitskopie) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xF0, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -65,12 +65,12 @@ #if 0 toggle_ready_jedec(bios); - writeb(0x30, bios + 0x0ffff); - writeb(0x30, bios + 0x1ffff); - writeb(0x30, bios + 0x2ffff); - writeb(0x30, bios + 0x37fff); - writeb(0x30, bios + 0x39fff); - writeb(0x30, bios + 0x3bfff); + chip_writeb(0x30, bios + 0x0ffff); + chip_writeb(0x30, bios + 0x1ffff); + chip_writeb(0x30, bios + 0x2ffff); + chip_writeb(0x30, bios + 0x37fff); + chip_writeb(0x30, bios + 0x39fff); + chip_writeb(0x30, bios + 0x3bfff); #endif return 0; @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); -- http://www.hailfinger.org/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: flashrom_rename_chip_accessors.diff URL: From mylesgw at gmail.com Fri Mar 6 15:11:59 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 6 Mar 2009 07:11:59 -0700 Subject: [coreboot] Problems about booting windows xp In-Reply-To: References: <20090118021006.GA14386@morn.localdomain> <49759968.8040907@assembler.cz><49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz><49B0E7F3.2070505@assembler.cz> Message-ID: > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Wang, Qingpei > Sent: Friday, March 06, 2009 2:44 AM > To: Rudolf Marek > Cc: Bao, Zheng; Xie, Michael; Perley, Tim; Coreboot > Subject: Re: [coreboot] Problems about booting windows xp > > Hi, > Today I tried to install a pure new windows xp which seabios in > dbm690t it > Hand off as show figure. I also put my dmes.txt here and e820 map also > data.txt from acpidump. It all works fine with linux. As my dbm690t has > 1G Ram, so I Take (1024-128)*1024*1024-64)1024. It looks like you have DMI enabled. Is that from SeaBIOS? I turned it in config.h since it looks emulator specific. Kevin or Rudolf, do you use it when you boot XP? > By the way, is there anybody who know how to use acpiexec? I can not use > it smoothly. I've been muddling through. I found that the history command has been useful to save some typing and frustration when I have typing errors. The other commands I've used: resources execute namespace help It turns out that you can't load multiple tables into acpiexec, which can be a pain. I patched the source and replaced one table, then I can load the other. Myles From patrick at georgi-clan.de Fri Mar 6 15:23:55 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Fri, 06 Mar 2009 15:23:55 +0100 Subject: [coreboot] [PATCH] flashrom: Rename chip accessor functions In-Reply-To: <49B12E6D.6070906@gmx.net> References: <49B12E6D.6070906@gmx.net> Message-ID: <49B131FB.8070002@georgi-clan.de> Am 06.03.2009 15:08, schrieb Carl-Daniel Hailfinger: > FreeBSD definitions of (read|write)[bwl] collide with our own. Before we > attempt trickery, we can simply rename the accessor functions. > > Signed-off-by: Carl-Daniel Hailfinger > Acked-by: Patrick Georgi Idwer acknowledged that the patch works on IRC, but has mail routing problems right now. As the patch isn't very complicated either, here's my ACK. Regards, Patrick From phueper at hueper.net Fri Mar 6 15:26:23 2009 From: phueper at hueper.net (Pattrick Hueper) Date: Fri, 6 Mar 2009 15:26:23 +0100 Subject: [coreboot] v2 + qemu + yabel Message-ID: Hi, i am trying to get Stefans merged yabel working with v2 under qemu... but it doesnt work. i set CONFIG_PCI_ROM_RUN and CONFIG_PCI_OPTION_ROM_RUN_YABEL As far as i see, the VGA device is not assigned a ROM address and thus run_bios is never called... i dont quite understand why this happens. I also tried to use pci_dev_init instead of vga_init as the init function, but it still wont work :-( Anybody any idea, what i am doing wrong? Regards, Patty From mylesgw at gmail.com Fri Mar 6 15:40:25 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 6 Mar 2009 07:40:25 -0700 Subject: [coreboot] v2 + qemu + yabel In-Reply-To: References: Message-ID: <2831fecf0903060640ydf59bd2q23bf9f4613099db1@mail.gmail.com> On Fri, Mar 6, 2009 at 7:26 AM, Pattrick Hueper wrote: > Hi, > > i am trying to get Stefans merged yabel working with v2 under qemu... > but it doesnt work. > > i set CONFIG_PCI_ROM_RUN and CONFIG_PCI_OPTION_ROM_RUN_YABEL > > As far as i see, the VGA device is not assigned a ROM address and thus > run_bios is never called... i dont quite understand why this happens. > > I also tried to use pci_dev_init instead of vga_init as the init > function, but it still wont work :-( > > Anybody any idea, what i am doing wrong? Look in /emulation/qemu-x86/mainboard.c and /emulation/qemu-x86/vgabios.c In v2 qemu has its own VGA init code. I'd bet you need to bypass that. Thanks, Myles From vincent.lim at amd.com Fri Mar 6 18:12:41 2009 From: vincent.lim at amd.com (Lim, Vincent) Date: Fri, 6 Mar 2009 11:12:41 -0600 Subject: [coreboot] Source Discrepancy Between QA Version and Snapshot Version Message-ID: <8ACC5F4627569841AF9B0331E5EDBF96DDEB50@sausexmb5.amd.com> Hi All: From svn at coreboot.org Fri Mar 6 18:20:18 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 18:20:18 +0100 Subject: [coreboot] r3974 - trunk/coreboot-v2/src/config Message-ID: Author: stepan Date: 2009-03-06 18:20:17 +0100 (Fri, 06 Mar 2009) New Revision: 3974 Modified: trunk/coreboot-v2/src/config/Config.lb Log: really clean out all compile time generated files (trivial) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-03-06 00:40:25 UTC (rev 3973) +++ trunk/coreboot-v2/src/config/Config.lb 2009-03-06 17:20:17 UTC (rev 3974) @@ -204,7 +204,10 @@ action "rm -f a.out *.s *.l *.o *.E *.inc" action "rm -f TAGS tags romcc*" action "rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*" - action "rm -f build_opt_tbl* nrv2b* option_table.c crt0.S" + action "rm -f build_opt_tbl* nrv2b* option_table.c option_table.h crt0.S crt0.disasm" + action "rm -f smm smm.elf smm.map smm_bin.c" + action "rm -f dsdt.aml dsdt.c" + action "rm -f payload" end # do standard config files that the user need not specify From svn at coreboot.org Fri Mar 6 18:21:24 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 18:21:24 +0100 Subject: [coreboot] r3975 - trunk/coreboot-v2/src/lib Message-ID: Author: stepan Date: 2009-03-06 18:21:23 +0100 (Fri, 06 Mar 2009) New Revision: 3975 Modified: trunk/coreboot-v2/src/lib/usbdebug_direct.c Log: use inb instead of outb for delays in usb debug code (trivial) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/lib/usbdebug_direct.c =================================================================== --- trunk/coreboot-v2/src/lib/usbdebug_direct.c 2009-03-06 17:20:17 UTC (rev 3974) +++ trunk/coreboot-v2/src/lib/usbdebug_direct.c 2009-03-06 17:21:23 UTC (rev 3975) @@ -92,7 +92,7 @@ int i; while (ms--) { for (i = 0; i < 1000; i++) - outb(0x1, 0x80); + inb(0x80); } } From svn at coreboot.org Fri Mar 6 18:22:35 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 18:22:35 +0100 Subject: [coreboot] r3976 - trunk/coreboot-v2/src/lib Message-ID: Author: stepan Date: 2009-03-06 18:22:35 +0100 (Fri, 06 Mar 2009) New Revision: 3976 Modified: trunk/coreboot-v2/src/lib/malloc.c Log: use pointers instead of size_t when dealing with pointers. Also fix a few warnings (trivial) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/lib/malloc.c =================================================================== --- trunk/coreboot-v2/src/lib/malloc.c 2009-03-06 17:21:23 UTC (rev 3975) +++ trunk/coreboot-v2/src/lib/malloc.c 2009-03-06 17:22:35 UTC (rev 3976) @@ -4,36 +4,36 @@ #if 0 #define MALLOCDBG(x) #else -#define MALLOCDBG(x) printk_spew x +#define MALLOCDBG(x...) printk_spew(x) #endif extern unsigned char _heap, _eheap; -static size_t free_mem_ptr = (size_t)&_heap; /* Start of heap */ -static size_t free_mem_end_ptr = (size_t)&_eheap; /* End of heap */ +static void *free_mem_ptr = &_heap; /* Start of heap */ +static void *free_mem_end_ptr = &_eheap; /* End of heap */ void malloc_mark(malloc_mark_t *place) { - *place = free_mem_ptr; - printk_spew("malloc_mark 0x%08lx\n", (unsigned long)free_mem_ptr); + *place = (malloc_mark_t)free_mem_ptr; + printk_spew("malloc_mark %p\n", free_mem_ptr); } void malloc_release(malloc_mark_t *ptr) { - free_mem_ptr = *ptr; - printk_spew("malloc_release 0x%08lx\n", (unsigned long)free_mem_ptr); + free_mem_ptr = (void *)*ptr; + printk_spew("malloc_release %p\n", free_mem_ptr); } void *malloc(size_t size) { void *p; - MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr)); + MALLOCDBG("%s Enter, size %ld, free_mem_ptr %p\n", __func__, size, free_mem_ptr); if (size < 0) die("Error! malloc: Size < 0"); if (free_mem_ptr <= 0) die("Error! malloc: Free_mem_ptr <= 0"); - free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */ + free_mem_ptr = (void *)(((unsigned long)free_mem_ptr + 3) & ~3); /* Align */ p = (void *) free_mem_ptr; free_mem_ptr += size; @@ -41,7 +41,7 @@ if (free_mem_ptr >= free_mem_end_ptr) die("Error! malloc: free_mem_ptr >= free_mem_end_ptr"); - MALLOCDBG(("malloc 0x%08lx\n", (unsigned long)p)); + MALLOCDBG("malloc %p\n", p); return p; } From svn at coreboot.org Fri Mar 6 18:24:29 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 18:24:29 +0100 Subject: [coreboot] r3977 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/smp cpu/x86/lapic cpu/x86/tsc devices Message-ID: Author: stepan Date: 2009-03-06 18:24:29 +0100 (Fri, 06 Mar 2009) New Revision: 3977 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/boot/multiboot.c trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/smp/ioapic.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c trunk/coreboot-v2/src/devices/device.c Log: fix a bunch of cast and type warnings and don't call the apic "nvram", that doesn't make no sense. (trivial) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -202,7 +202,7 @@ ssdt->asl_compiler_revision = 42; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((unsigned char *) current); + acpigen_set_current((char *) current); current = acpi_fill_ssdt_generator(current, oem_table_id); /* recalculate length */ Modified: trunk/coreboot-v2/src/arch/i386/boot/multiboot.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -72,7 +72,7 @@ build_mb_mem_range_nooverlap(res->base, res->size); } -#define ROUND(_r,_a) ((_r) + (((_a) - 1)) & ~((_a) - 1)) +#define ROUND(_r,_a) (((_r) + (((_a) - 1))) & ~((_a) - 1)) unsigned long write_multiboot_info( unsigned long low_table_start, unsigned long low_table_end, @@ -81,12 +81,12 @@ struct multiboot_info *mbi; int i; - mbi = rom_table_end; + mbi = (struct multiboot_info *)rom_table_end; memset(mbi, 0, sizeof(*mbi)); rom_table_end += sizeof(*mbi); mbi->mmap_addr = (u32) rom_table_end; - mb_mem = rom_table_end; + mb_mem = (struct multiboot_mmap_entry *)rom_table_end; /* reserved regions */ reserved_mem[0].addr = low_table_start; @@ -111,5 +111,5 @@ printk_info("Multiboot Information structure has been written.\n"); - return mb_mem; + return (unsigned long)mb_mem; } Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -182,7 +182,7 @@ #if CONFIG_MULTIBOOT /* The Multiboot information structure */ - mbi = rom_table_end; + mbi = (struct multiboot_info *)rom_table_end; rom_table_end = write_multiboot_info( low_table_start, low_table_end, rom_table_start, rom_table_end); Modified: trunk/coreboot-v2/src/arch/i386/smp/ioapic.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/smp/ioapic.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/smp/ioapic.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -55,11 +55,11 @@ { int i; unsigned long value_low, value_high; - unsigned long nvram = 0xfec00000; + unsigned long ioapicaddr = 0xfec00000; volatile unsigned long *l; struct ioapicreg *a = ioapicregvalues; - l = (unsigned long *) nvram; + l = (unsigned long *) ioapicaddr; #if defined(i786) /* For the pentium 4 and above apic deliver their interrupts * on the front side bus, enable that. Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -295,7 +295,7 @@ lapicid = lapic_read(LAPIC_ID) >> 24; - printk_debug("CPU %d going down...\n", lapicid); + printk_debug("CPU %ld going down...\n", lapicid); /* send an LAPIC INIT to myself */ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid)); Modified: trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -104,6 +104,7 @@ unsigned long long start, end, delta; unsigned long result, count; + printk_spew("Calibrating delay loop...\n"); start = rdtscll(); // no udivdi3, dammit. // so we count to 1<< 20 and then right shift 20 @@ -127,10 +128,10 @@ delta >>= 20; // save this for microsecond timing. result = delta; - printk_spew("end %x, start %x\n", end, start); - printk_spew("32-bit delta %d\n", (unsigned long) delta); + printk_spew("end %llx, start %llx\n", end, start); + printk_spew("32-bit delta %ld\n", (unsigned long) delta); - printk_spew("%s 32-bit result is %d\n", + printk_spew("%s 32-bit result is %ld\n", __func__, result); return delta; @@ -143,7 +144,7 @@ { if (!clocks_per_usec) { clocks_per_usec = calibrate_tsc(); - printk_info("clocks_per_usec: %u\n", clocks_per_usec); + printk_info("clocks_per_usec: %lu\n", clocks_per_usec); } } Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/devices/device.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -357,8 +357,7 @@ resource->flags &= ~IORESOURCE_STORED; base += size; - printk_spew( - "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", + printk_spew("%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", dev_path(dev), resource->index, resource->base, From svn at coreboot.org Fri Mar 6 18:43:20 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 18:43:20 +0100 Subject: [coreboot] r3978 - trunk/payloads/libpayload/libc Message-ID: Author: stepan Date: 2009-03-06 18:43:20 +0100 (Fri, 06 Mar 2009) New Revision: 3978 Modified: trunk/payloads/libpayload/libc/string.c Log: fix strstr. Seems the function never worked before, except the searched substring is at the end. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/payloads/libpayload/libc/string.c =================================================================== --- trunk/payloads/libpayload/libc/string.c 2009-03-06 17:24:29 UTC (rev 3977) +++ trunk/payloads/libpayload/libc/string.c 2009-03-06 17:43:20 UTC (rev 3978) @@ -234,7 +234,7 @@ int i; for (i = 0; i <= hn - nn; i++) - if (!strcmp(&h[i], n)) + if (!memcmp(&h[i], n, nn)) return (char *)&h[i]; return NULL; From stepan at coresystems.de Fri Mar 6 19:07:01 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 19:07:01 +0100 Subject: [coreboot] [PATCH] v2: fix PCIe/MMCONF config space access Message-ID: <49B16645.8040009@coresystems.de> See patch -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: mmconf.diff URL: From mylesgw at gmail.com Fri Mar 6 19:20:25 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 6 Mar 2009 11:20:25 -0700 Subject: [coreboot] [PATCH] v2: fix PCIe/MMCONF config space access In-Reply-To: <49B16645.8040009@coresystems.de> References: <49B16645.8040009@coresystems.de> Message-ID: <2831fecf0903061020k63c0c96dw1cb18d1674901311@mail.gmail.com> It seems like these two snippets should be related in some way. Do you have to set them equal? Index: src/config/Options.lb =================================================================== --- src/config/Options.lb (.../branches/upstream/coreboot-v2) +++ src/config/Options.lb (.../trunk/coreboot-v2) @@ -983,6 +983,13 @@ comment "enable mmconfig for pci conf" end +define MMCONF_BASE_ADDRESS + default none + format "0x%x" + export used + comment "enable mmconfig base address" +end + from /src/northbridge/intel/i945/northbridge.c: /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ resource = new_resource(dev, 0xcf); resource->base = DEFAULT_PCIEXBAR; resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n", resource->base, (resource->base + resource->size)); I didn't see anywhere that you enabled the PCI decode space in the fam10 code. Is it fixed? How does resource allocation avoid it? Thanks, Myles From c-d.hailfinger.devel.2006 at gmx.net Fri Mar 6 19:36:14 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Mar 2009 19:36:14 +0100 Subject: [coreboot] r3977 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/smp cpu/x86/lapic cpu/x86/tsc devices In-Reply-To: <20090306172501.9772gmx1@mx043.gmx.net> References: <20090306172501.9772gmx1@mx043.gmx.net> Message-ID: <49B16D1E.4040600@gmx.net> On 06.03.2009 18:24, svn at coreboot.org wrote: > Author: stepan > Date: 2009-03-06 18:24:29 +0100 (Fri, 06 Mar 2009) > New Revision: 3977 > > fix a bunch of cast and type warnings and don't call the apic "nvram", that > doesn't make no sense. (trivial) > The change to the ROUND macro is rather non-trivial. It changes the formula. If the new formula is indeed what you want, one parenthesis can be removed: #define ROUND(_r,_a) (((_r) + ((_a) - 1)) & ~((_a) - 1)) Regards, Carl-Daniel > Signed-off-by: Stefan Reinauer > Acked-by: Stefan Reinauer > > Modified: trunk/coreboot-v2/src/arch/i386/boot/multiboot.c > =================================================================== > --- trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-03-06 17:22:35 UTC (rev 3976) > +++ trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-03-06 17:24:29 UTC (rev 3977) > @@ -72,7 +72,7 @@ > build_mb_mem_range_nooverlap(res->base, res->size); > } > > -#define ROUND(_r,_a) ((_r) + (((_a) - 1)) & ~((_a) - 1)) > +#define ROUND(_r,_a) (((_r) + (((_a) - 1))) & ~((_a) - 1)) > > unsigned long write_multiboot_info( > unsigned long low_table_start, unsigned long low_table_end, > -- http://www.hailfinger.org/ From svn at coreboot.org Fri Mar 6 19:38:28 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 19:38:28 +0100 Subject: [coreboot] r3979 - in trunk/coreboot-v2: src/mainboard/emulation/qemu-x86 targets/emulation/qemu-x86 Message-ID: Author: stepan Date: 2009-03-06 19:38:28 +0100 (Fri, 06 Mar 2009) New Revision: 3979 Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb Log: clean up qemu target config (trivial) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-03-06 17:43:20 UTC (rev 3978) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-03-06 18:38:28 UTC (rev 3979) @@ -70,9 +70,8 @@ ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=0 -default IRQ_SLOT_COUNT=5 -#object irq_tables.o +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=6 ## ## Build code to export a CMOS option table Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb 2009-03-06 17:43:20 UTC (rev 3978) +++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb 2009-03-06 18:38:28 UTC (rev 3979) @@ -1,22 +1,20 @@ -# This will make a target directory of ./emulation_qemu-x86 +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD -target emulation_qemu-x86 -mainboard emulation/qemu-x86 +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" __COMPRESSION__ option ROM_SIZE=256*1024 -option CC="gcc -m32" - -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=6 - -romimage "image" +romimage "fallback" + option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option COREBOOT_EXTRA_VERSION="-OpenBIOS" + option COREBOOT_EXTRA_VERSION=".0" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom ROM_SIZE "fallback" From c-d.hailfinger.devel.2006 at gmx.net Fri Mar 6 19:39:26 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Mar 2009 19:39:26 +0100 Subject: [coreboot] [PATCH] v2: fix PCIe/MMCONF config space access In-Reply-To: <49B16645.8040009@coresystems.de> References: <49B16645.8040009@coresystems.de> Message-ID: <49B16DDE.5090700@gmx.net> On 06.03.2009 19:07, Stefan Reinauer wrote: > Fix mmconf (PCIe memory mapped config space access) support in v2. It was > horribly broken and thus never used by any platform. This needs to get > straightened out so current chipsets drivers can use the full feature set. > > Create wrapper functions similar to the io pci config space ones. > > Signed-off-by: Stefan Reinauer > IIRC the AMD DBM690T code uses mmconf accesses for PCIe. Then again, maybe it was only in the ACPI code. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Fri Mar 6 19:39:54 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 19:39:54 +0100 Subject: [coreboot] r3980 - in trunk/coreboot-v2/src/southbridge: amd/cs5536 via/vt8235 via/vt8237r Message-ID: Author: stepan Date: 2009-03-06 19:39:54 +0100 (Fri, 06 Mar 2009) New Revision: 3980 Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: use include file for i8259 where appropriate (trivial) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2009-03-06 18:38:28 UTC (rev 3979) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2009-03-06 18:39:54 UTC (rev 3980) @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -33,8 +34,6 @@ #include "chip.h" #include "cs5536.h" -extern void setup_i8259(void); - struct msrinit { uint32_t msrnum; msr_t msr; Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c 2009-03-06 18:38:28 UTC (rev 3979) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c 2009-03-06 18:39:54 UTC (rev 3980) @@ -4,6 +4,7 @@ #include #include #include +#include #include "vt8235.h" #include "chip.h" Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-03-06 18:38:28 UTC (rev 3979) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-03-06 18:39:54 UTC (rev 3980) @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "vt8237r.h" #include "chip.h" @@ -47,7 +48,6 @@ #define INT (1 << 8) extern void dump_south(device_t dev); -extern void setup_i8259(void); static struct ioapicreg { u32 reg; From stepan at coresystems.de Fri Mar 6 19:45:57 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 19:45:57 +0100 Subject: [coreboot] [PATCH] v2: fix PCIe/MMCONF config space access In-Reply-To: <2831fecf0903061020k63c0c96dw1cb18d1674901311@mail.gmail.com> References: <49B16645.8040009@coresystems.de> <2831fecf0903061020k63c0c96dw1cb18d1674901311@mail.gmail.com> Message-ID: <49B16F65.3000606@coresystems.de> On 06.03.2009 19:20 Uhr, Myles Watson wrote: > It seems like these two snippets should be related in some way. Do > you have to set them equal? > Yes, the two are related. They're not yet unified - there will be more patches coming to clean things up, but I need to get my patch queue smaller in order to not drift away from the public tree. > Index: src/config/Options.lb > =================================================================== > --- src/config/Options.lb (.../branches/upstream/coreboot-v2) > +++ src/config/Options.lb (.../trunk/coreboot-v2) > @@ -983,6 +983,13 @@ > comment "enable mmconfig for pci conf" > end > > +define MMCONF_BASE_ADDRESS > + default none > + format "0x%x" > + export used > + comment "enable mmconfig base address" > +end > + > > from /src/northbridge/intel/i945/northbridge.c: > > /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ > resource = new_resource(dev, 0xcf); > resource->base = DEFAULT_PCIEXBAR; > resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ > resource->flags = > IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | > IORESOURCE_ASSIGNED; > printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n", > resource->base, (resource->base + resource->size)); > > > I didn't see anywhere that you enabled the PCI decode space in the > fam10 code. Is it fixed? How does resource allocation avoid it? > I didn't touch any of the fam10 code, except the obvious MMCONF -> MMCONF_DEFAULT, because that's what the the code that is there really is supposed to do. Hopefully someone can jump in on fam10 and help getting that part straight. At the moment, I'm focussed on getting it right for the Intel code and try to fix up some of the AMD parts as far as I can be sure not to break anything there or make it worse. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From stepan at coresystems.de Fri Mar 6 19:47:04 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 19:47:04 +0100 Subject: [coreboot] [PATCH] v2: fix PCIe/MMCONF config space access In-Reply-To: <49B16DDE.5090700@gmx.net> References: <49B16645.8040009@coresystems.de> <49B16DDE.5090700@gmx.net> Message-ID: <49B16FA8.1040902@coresystems.de> On 06.03.2009 19:39 Uhr, Carl-Daniel Hailfinger wrote: > On 06.03.2009 19:07, Stefan Reinauer wrote: > >> Fix mmconf (PCIe memory mapped config space access) support in v2. It was >> horribly broken and thus never used by any platform. This needs to get >> straightened out so current chipsets drivers can use the full feature set. >> >> Create wrapper functions similar to the io pci config space ones. >> >> Signed-off-by: Stefan Reinauer >> >> > > IIRC the AMD DBM690T code uses mmconf accesses for PCIe. No, it does not. MMCONF is unused. I am absolutely certain that it never worked. (As you can be, when you look at my patch) -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mylesgw at gmail.com Fri Mar 6 19:52:04 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 6 Mar 2009 11:52:04 -0700 Subject: [coreboot] [PATCH] v2: fix PCIe/MMCONF config space access In-Reply-To: <49B16F65.3000606@coresystems.de> References: <49B16645.8040009@coresystems.de> <2831fecf0903061020k63c0c96dw1cb18d1674901311@mail.gmail.com> <49B16F65.3000606@coresystems.de> Message-ID: <2831fecf0903061052k41cfc07buaf6bef8821d95f28@mail.gmail.com> On Fri, Mar 6, 2009 at 11:45 AM, Stefan Reinauer wrote: > On 06.03.2009 19:20 Uhr, Myles Watson wrote: >> It seems like these two snippets should be related in some way. ?Do >> you have to set them equal? >> > > Yes, the two are related. They're not yet unified - there will be more > patches coming to clean things up, but I need to get my patch queue > smaller in order to not drift away from the public tree. Sure. I just wanted to make sure that was the direction we're heading in. Acked-by: Myles Watson Thanks, Myles From mylesgw at gmail.com Fri Mar 6 19:57:13 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 6 Mar 2009 11:57:13 -0700 Subject: [coreboot] r3977 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/smp cpu/x86/lapic cpu/x86/tsc devices In-Reply-To: <49B16D1E.4040600@gmx.net> References: <20090306172501.9772gmx1@mx043.gmx.net> <49B16D1E.4040600@gmx.net> Message-ID: <2831fecf0903061057s3e44bbd0sa3995f648a3f8ad3@mail.gmail.com> On Fri, Mar 6, 2009 at 11:36 AM, Carl-Daniel Hailfinger wrote: > On 06.03.2009 18:24, svn at coreboot.org wrote: >> Author: stepan >> Date: 2009-03-06 18:24:29 +0100 (Fri, 06 Mar 2009) >> New Revision: 3977 >> >> fix a bunch of cast and type warnings and don't call the apic "nvram", that >> doesn't make no sense. (trivial) >> > > The change to the ROUND macro is rather non-trivial. It changes the > formula. If the new formula is indeed what you want, one parenthesis can > be removed: > > #define ROUND(_r,_a) (((_r) + ((_a) - 1)) & ~((_a) - 1)) I agree that a parenthesis can be removed, but since + has precedence over & I don't see how the formula was changed. Thanks, Myles From stepan at coresystems.de Fri Mar 6 20:04:02 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 20:04:02 +0100 Subject: [coreboot] r3977 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/smp cpu/x86/lapic cpu/x86/tsc devices In-Reply-To: <2831fecf0903061057s3e44bbd0sa3995f648a3f8ad3@mail.gmail.com> References: <20090306172501.9772gmx1@mx043.gmx.net> <49B16D1E.4040600@gmx.net> <2831fecf0903061057s3e44bbd0sa3995f648a3f8ad3@mail.gmail.com> Message-ID: <49B173A2.4040002@coresystems.de> On 06.03.2009 19:57 Uhr, Myles Watson wrote: > On Fri, Mar 6, 2009 at 11:36 AM, Carl-Daniel Hailfinger > wrote: > >> On 06.03.2009 18:24, svn at coreboot.org wrote: >> >>> Author: stepan >>> Date: 2009-03-06 18:24:29 +0100 (Fri, 06 Mar 2009) >>> New Revision: 3977 >>> >>> fix a bunch of cast and type warnings and don't call the apic "nvram", that >>> doesn't make no sense. (trivial) >>> >>> >> The change to the ROUND macro is rather non-trivial. It changes the >> formula. If the new formula is indeed what you want, one parenthesis can >> be removed: >> >> #define ROUND(_r,_a) (((_r) + ((_a) - 1)) & ~((_a) - 1)) >> > > I agree that a parenthesis can be removed, but since + has precedence > over & I don't see how the formula was changed. > gcc was complaining about missing paranthesis, so I figured I'd try to make clear what it's supopsed to do. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From stepan at coresystems.de Fri Mar 6 20:04:49 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 20:04:49 +0100 Subject: [coreboot] [PATCH] v2: intel core solo / core duo / core 2 solo / core 2 duo cpu update Message-ID: <49B173D1.1030304@coresystems.de> See patch -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: core-cpus.diff URL: From stepan at coresystems.de Fri Mar 6 20:10:35 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 20:10:35 +0100 Subject: [coreboot] [PATCH] v2: add support for mainboard specific SMM code Message-ID: <49B1752B.3050409@coresystems.de> See patch -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: smm.diff URL: From svn at coreboot.org Fri Mar 6 20:11:52 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 20:11:52 +0100 Subject: [coreboot] r3981 - in trunk/coreboot-v2/src: arch/i386/include/arch arch/i386/lib config devices include/device northbridge/amd/amdfam10 northbridge/intel/i945 Message-ID: Author: stepan Date: 2009-03-06 20:11:52 +0100 (Fri, 06 Mar 2009) New Revision: 3981 Modified: trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/devices/pci_ops.c trunk/coreboot-v2/src/include/device/pci_ops.h trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c Log: Fix mmconf (PCIe memory mapped config space access) support in v2. It was horribly broken and thus never used by any platform. This needs to get straightened out so current chipsets drivers can use the full feature set. Create wrapper functions similar to the io pci config space ones. Signed-off-by: Stefan Reinauer Acked-by: Myles Watson Modified: trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h 2009-03-06 18:39:54 UTC (rev 3980) +++ trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h 2009-03-06 19:11:52 UTC (rev 3981) @@ -105,13 +105,13 @@ static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) { unsigned addr; - addr = dev | where; + addr = MMCONF_BASE_ADDRESS | dev | where; return read8x(addr); } #endif static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) { -#if MMCONF_SUPPORT +#if MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config8(dev, where); #else return pci_io_read_config8(dev, where); @@ -134,14 +134,14 @@ static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) { unsigned addr; - addr = dev | where; + addr = MMCONF_BASE_ADDRESS | dev | where; return read16x(addr); } #endif static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) { -#if MMCONF_SUPPORT +#if MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config16(dev, where); #else return pci_io_read_config16(dev, where); @@ -165,14 +165,14 @@ static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) { unsigned addr; - addr = dev | where; + addr = MMCONF_BASE_ADDRESS | dev | where; return read32x(addr); } #endif static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) { -#if MMCONF_SUPPORT +#if MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config32(dev, where); #else return pci_io_read_config32(dev, where); @@ -195,14 +195,14 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) { unsigned addr; - addr = dev | where; + addr = MMCONF_BASE_ADDRESS | dev | where; write8x(addr, value); } #endif static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) { -#if MMCONF_SUPPORT +#if MMCONF_SUPPORT_DEFAULT pci_mmio_write_config8(dev, where, value); #else pci_io_write_config8(dev, where, value); @@ -226,14 +226,14 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; - addr = dev | where; + addr = MMCONF_BASE_ADDRESS | dev | where; write16x(addr, value); } #endif static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) { -#if MMCONF_SUPPORT +#if MMCONF_SUPPORT_DEFAULT pci_mmio_write_config16(dev, where, value); #else pci_io_write_config16(dev, where, value); @@ -257,14 +257,14 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; - addr = dev | where; + addr = MMCONF_BASE_ADDRESS | dev | where; write32x(addr, value); } #endif static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) { -#if MMCONF_SUPPORT +#if MMCONF_SUPPORT_DEFAULT pci_mmio_write_config32(dev, where, value); #else pci_io_write_config32(dev, where, value); Modified: trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c 2009-03-06 18:39:54 UTC (rev 3980) +++ trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c 2009-03-06 19:11:52 UTC (rev 3981) @@ -13,6 +13,7 @@ */ #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \ + MMCONF_BASE_ADDRESS | \ (((SEGBUS) & 0xFFF) << 20) | \ (((DEVFN) & 0xFF) << 12) | \ ((WHERE) & 0xFFF)) Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-03-06 18:39:54 UTC (rev 3980) +++ trunk/coreboot-v2/src/config/Options.lb 2009-03-06 19:11:52 UTC (rev 3981) @@ -983,6 +983,13 @@ comment "enable mmconfig for pci conf" end +define MMCONF_BASE_ADDRESS + default none + format "0x%x" + export used + comment "enable mmconfig base address" +end + define HW_MEM_HOLE_SIZEK default 0 export always Modified: trunk/coreboot-v2/src/devices/pci_ops.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-06 18:39:54 UTC (rev 3980) +++ trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-06 19:11:52 UTC (rev 3981) @@ -3,6 +3,7 @@ * * Copyright (C) 2004 Linux Networx * (Written by Eric Biederman for Linux Networx) + * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,3 +80,41 @@ struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } + +#if MMCONF_SUPPORT +uint8_t pci_mmio_read_config8(device_t dev, unsigned where) +{ + struct bus *pbus = get_pbus(dev); + return pci_ops_mmconf.read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where); +} + +uint16_t pci_mmio_read_config16(device_t dev, unsigned where) +{ + struct bus *pbus = get_pbus(dev); + return pci_ops_mmconf.read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where); +} + +uint32_t pci_mmio_read_config32(device_t dev, unsigned where) +{ + struct bus *pbus = get_pbus(dev); + return pci_ops_mmconf.read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where); +} + +void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val) +{ + struct bus *pbus = get_pbus(dev); + pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); +} + +void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val) +{ + struct bus *pbus = get_pbus(dev); + pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); +} + +void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val) +{ + struct bus *pbus = get_pbus(dev); + pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); +} +#endif Modified: trunk/coreboot-v2/src/include/device/pci_ops.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci_ops.h 2009-03-06 18:39:54 UTC (rev 3980) +++ trunk/coreboot-v2/src/include/device/pci_ops.h 2009-03-06 19:11:52 UTC (rev 3981) @@ -12,4 +12,13 @@ void pci_write_config16(device_t dev, unsigned where, uint16_t val); void pci_write_config32(device_t dev, unsigned where, uint32_t val); +#if MMCONF_SUPPORT +uint8_t pci_mmio_read_config8(device_t dev, unsigned where); +uint16_t pci_mmio_read_config16(device_t dev, unsigned where); +uint32_t pci_mmio_read_config32(device_t dev, unsigned where); +void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val); +void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val); +void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val); +#endif + #endif /* PCI_OPS_H */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-03-06 18:39:54 UTC (rev 3980) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-03-06 19:11:52 UTC (rev 3981) @@ -1176,7 +1176,7 @@ .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -#if MMCONF_SUPPORT +#if MMCONF_SUPPORT_DEFAULT .ops_pci_bus = &pci_ops_mmconf, #else .ops_pci_bus = &pci_cf8_conf1, Modified: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-03-06 18:39:54 UTC (rev 3980) +++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-03-06 19:11:52 UTC (rev 3981) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -199,7 +199,11 @@ .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ +#if MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif }; static void mc_read_resources(device_t dev) From harald.gutmann at gmx.net Fri Mar 6 20:34:10 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Fri, 6 Mar 2009 20:34:10 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI Message-ID: <200903062034.17928.harald.gutmann@gmx.net> Hello, the result of the past two/three days work/interest on coreboot is a big part of ACPI support on M57SLI which works on my revision (v2). Soft-Power-Off works, and that's what i missed really hard in coreboot for m57sli. The other parts of ACPI support should work (mostly) also fine. (except setting up MMCONFIG in acpi_fill_mcfg, and the powernow features which hopefully can be done with the recently commited patch "AMD boards to use new Power Now infrastructure" from Rudolf Marek). I think i'll get the time this weekend or at the beginning of the next week to address those remaining problems. In the mean time i hope that someone can test the code which i didn't originally write, but modified, to work at M57SLI. For myself I own an M57SLI with hardware rev.2, maybe Ward can test if that code will work on v1 too. One other "problem" with the actual code is, that most of the interesting parts are hardcoded (numbers where variables should be/could be). The attached patch is quite complete, except the problems mentioned above and the copyright informations are missing in the patch. This one is just for testing, and i'll try to get the remaining problems fixed, and i also will add copyright information when the work is finally done. I think it's not the time to add this patch into svn because of the above mentioned missing parts. But it's a great time to test and enjoy this patch. Kind regards, Harald Gutmann -------------- next part -------------- A non-text attachment was scrubbed... Name: acpi_patch_m57sli.diff Type: text/x-patch Size: 195724 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: acpi_patch_m57sli.diff.gpg Type: application/pgp-encrypted Size: 17419 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From peter at stuge.se Fri Mar 6 20:41:49 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 20:41:49 +0100 Subject: [coreboot] [PATCH] v2: intel core solo / core duo / core 2 solo / core 2 duo cpu update In-Reply-To: <49B173D1.1030304@coresystems.de> References: <49B173D1.1030304@coresystems.de> Message-ID: <20090306194149.11958.qmail@stuge.se> Stefan Reinauer wrote: > Some updates for core/core duo/core2/core2 duo cpus. > > The microcode is from Intel's Linux microcode file, so it's unproblematic. > > Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge From peter at stuge.se Fri Mar 6 20:42:54 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 20:42:54 +0100 Subject: [coreboot] [PATCH] v2: add support for mainboard specific SMM code In-Reply-To: <49B1752B.3050409@coresystems.de> References: <49B1752B.3050409@coresystems.de> Message-ID: <20090306194254.12255.qmail@stuge.se> Stefan Reinauer wrote: > * fix a minor power state issue in the ich7 smm handler > * move mainboard dependent code into a mainboard SMI handler. > > Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge From peter at stuge.se Fri Mar 6 20:45:33 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 20:45:33 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <200903062034.17928.harald.gutmann@gmx.net> References: <200903062034.17928.harald.gutmann@gmx.net> Message-ID: <20090306194533.12943.qmail@stuge.se> Harald Gutmann wrote: > the result of the past two/three days work/interest on coreboot is > a big part of ACPI support on M57SLI which works on my revision > (v2). > > Soft-Power-Off works, and that's what i missed really hard in > coreboot for m57sli. Good work getting that going! I don't know if we want to take in the factory DSDT though.. //Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: From harald.gutmann at gmx.net Fri Mar 6 20:49:30 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Fri, 6 Mar 2009 20:49:30 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <200903062034.17928.harald.gutmann@gmx.net> References: <200903062034.17928.harald.gutmann@gmx.net> Message-ID: <200903062049.31020.harald.gutmann@gmx.net> Hello once again, as i love it that much to talk with myself, i was wondering while working/creating ACPI stuff, why HPTE support is turned off in mcp55_lpc.c with using #if 0. Has maybe someone of you an idea why that was done? (HPTE is also in context with ACPI) Here there is the code snippet i refer to: #if 0 static void enable_hpet(struct device *dev) { unsigned long hpet_address; pci_write_config32(dev,0x44, 0xfed00001); hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; printk_debug("enabling HPET @0x%x\n", hpet_address); } #endif Ideas? Kind Regards, Harald Gutmann PS: This was not mentioned in the first post on the list, but HPTE support should be also included into ACPI to get it full working. I just missed it in the first post. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From mylesgw at gmail.com Fri Mar 6 20:50:03 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 6 Mar 2009 12:50:03 -0700 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <200903062049.31020.harald.gutmann@gmx.net> References: <200903062034.17928.harald.gutmann@gmx.net> <200903062049.31020.harald.gutmann@gmx.net> Message-ID: <5C9E8024680E4034B04EFE3E6A3D62BE@chimp> > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Harald Gutmann > Sent: Friday, March 06, 2009 12:50 PM > To: coreboot at coreboot.org > Subject: Re: [coreboot] [patch] ACPI support on M57SLI > > Hello once again, > > as i love it that much to talk with myself, i was wondering while > working/creating ACPI stuff, why HPTE support is turned off in mcp55_lpc.c > with > using #if 0. > > Has maybe someone of you an idea why that was done? (HPTE is also in > context > with ACPI) I don't know why HPET is disabled in mcp55. It was also disabled in ck804_lpc.c. It worked fine when I enabled it. Thanks, Myles From svn at coreboot.org Fri Mar 6 20:52:36 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 20:52:36 +0100 Subject: [coreboot] r3982 - in trunk/coreboot-v2/src: cpu/x86/smm include/cpu/x86 mainboard/kontron/986lcd-m southbridge/intel/i82801gx Message-ID: Author: stepan Date: 2009-03-06 20:52:36 +0100 (Fri, 06 Mar 2009) New Revision: 3982 Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c Modified: trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c trunk/coreboot-v2/src/include/cpu/x86/smm.h trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c Log: * fix a minor power state issue in the ich7 smm handler * move mainboard dependent code into a mainboard SMI handler. Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge Modified: trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c 2009-03-06 19:11:52 UTC (rev 3981) +++ trunk/coreboot-v2/src/cpu/x86/smm/smihandler.c 2009-03-06 19:52:36 UTC (rev 3982) @@ -129,7 +129,18 @@ void io_trap_handler(int smif) { - southbridge_io_trap_handler(smif); + /* If a handler function handled a given IO trap, it + * shall return a non-zero value + */ + printk_debug("SMI function trap 0x%x: ", smif); + + if (southbridge_io_trap_handler(smif)) + return; + + if (mainboard_io_trap_handler(smif)) + return; + + printk_debug("Unknown function\n"); } /** Modified: trunk/coreboot-v2/src/include/cpu/x86/smm.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/x86/smm.h 2009-03-06 19:11:52 UTC (rev 3981) +++ trunk/coreboot-v2/src/include/cpu/x86/smm.h 2009-03-06 19:52:36 UTC (rev 3982) @@ -249,3 +249,8 @@ }; } smm_state_save_area_t; + +/* SMI handler function prototypes */ +int southbridge_io_trap_handler(int smif); +int mainboard_io_trap_handler(int smif); + Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb 2009-03-06 19:11:52 UTC (rev 3981) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb 2009-03-06 19:52:36 UTC (rev 3982) @@ -76,6 +76,7 @@ driver rtl8168.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +if HAVE_SMI_HANDLER smmobject mainboard_smi.o end if HAVE_ACPI_TABLES object fadt.o Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c 2009-03-06 19:52:36 UTC (rev 3982) @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" + +int mainboard_io_trap_handler(int smif) +{ + global_nvs_t *gnvs = (global_nvs_t *)0xc00; + + switch (smif) { + case 0x99: + printk_debug("Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + + Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c 2009-03-06 19:11:52 UTC (rev 3981) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c 2009-03-06 19:52:36 UTC (rev 3982) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 coresystems GmbH + * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c 2009-03-06 19:11:52 UTC (rev 3981) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c 2009-03-06 19:52:36 UTC (rev 3982) @@ -31,10 +31,11 @@ #define DEBUG_SMI -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 +#define APM_CNT 0xb2 +#define APM_STS 0xb3 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 - /* I945 */ #define SMRAM 0x9d #define D_OPEN (1 << 6) @@ -241,37 +242,18 @@ */ #include "../../../northbridge/intel/i945/pcie_config.c" -void southbridge_io_trap_handler(int smif) +int southbridge_io_trap_handler(int smif) { - u8 reg8; global_nvs_t *gnvs = (global_nvs_t *)0xc00; - printk_debug("SMI function trap 0x%x: ", smif); - switch (smif) { case 0x32: printk_debug("OS Init\n"); //gnvs->smif = 0; break; - case 0xd5: - printk_debug("Set Brightness\n"); - reg8 = gnvs->brtl; - printk_debug("brtl: %x\n", reg8); - outb(0x17, 0x66); - outb(reg8, 0x62); - //gnvs->smif = 0; - break; - case 0xd6: - printk_debug("Get Brightness\n"); - outb(0x17, 0x66); - reg8 = inb(0x62); - printk_debug("brtl: %x\n", reg8); - gnvs->brtl = reg8; - //gnvs->smif = 0; - break; default: - printk_debug("Unknown function\n"); - break; + /* Not handled */ + return 0; } /* On success, the IO Trap Handler returns 0 @@ -281,6 +263,7 @@ * see what's going on. */ //gnvs->smif = 0; + return 1; /* IO trap handled */ } /** @@ -423,12 +406,13 @@ */ /* Write back to the SLP register to cause the - * originally intended event again. + * originally intended event again. We need to set BIT13 + * (SLP_EN) though to make the sleep happen. */ reg32 = inl(pmbase + 0x04); - printk_debug("SMI#: SLP = 0x%08x\n"); + printk_debug("SMI#: SLP = 0x%08x\n", reg32); printk_debug("SMI#: Powering off.\n"); - outl(reg32, pmbase + 0x04); + outl(reg32 | (1 << 13), pmbase + 0x04); } } From stepan at coresystems.de Fri Mar 6 20:52:54 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 20:52:54 +0100 Subject: [coreboot] [PATCH] v2: intel core solo / core duo / core 2 solo / core 2 duo cpu update In-Reply-To: <20090306194149.11958.qmail@stuge.se> References: <49B173D1.1030304@coresystems.de> <20090306194149.11958.qmail@stuge.se> Message-ID: <49B17F16.7020603@coresystems.de> On 06.03.2009 20:41 Uhr, Peter Stuge wrote: > Acked-by: Peter Stuge Thanks, r3982 -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From harald.gutmann at gmx.net Fri Mar 6 20:56:42 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Fri, 6 Mar 2009 20:56:42 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <20090306194533.12943.qmail@stuge.se> References: <200903062034.17928.harald.gutmann@gmx.net> <20090306194533.12943.qmail@stuge.se> Message-ID: <200903062056.42199.harald.gutmann@gmx.net> On Friday 06 March 2009 20:45:33 Peter Stuge wrote: > Harald Gutmann wrote: > > the result of the past two/three days work/interest on coreboot is > > a big part of ACPI support on M57SLI which works on my revision > > (v2). > > > > Soft-Power-Off works, and that's what i missed really hard in > > coreboot for m57sli. > > Good work getting that going! > > I don't know if we want to take in the factory DSDT though.. As you've seen correctly it's the factory DSDT which i created using acpidump, acpixtract and iasl. I don't know if it would be a license problem to take that in, but it works, and as told above this patch shouldn't be committed right now. > > //Peter Harald -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From svn at coreboot.org Fri Mar 6 20:54:15 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 20:54:15 +0100 Subject: [coreboot] r3983 - in trunk/coreboot-v2/src/cpu/intel: model_6ex model_6fx Message-ID: Author: stepan Date: 2009-03-06 20:54:15 +0100 (Fri, 06 Mar 2009) New Revision: 3983 Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f257.h trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f6c7.h Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c Log: Some updates for core/core duo/core2/core2 duo cpus. The microcode is from Intel's Linux microcode file, so it's unproblematic. Signed-off-by: Stefan Reinauer Acked-by: Peter Stuge Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c 2009-03-06 19:52:36 UTC (rev 3982) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c 2009-03-06 19:54:15 UTC (rev 3983) @@ -52,6 +52,76 @@ strcpy(processor_name, processor_name_start); } +#define IA32_FEATURE_CONTROL 0x003a + +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + regs = cpuid(1); + if (regs.ecx & CPUID_VMX) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + +#define PMG_CST_CONFIG_CONTROL 0xe2 +static void configure_c_states(void) +{ + msr_t msr; + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + + // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(PMG_CST_CONFIG_CONTROL, msr); +} + +#define IA32_MISC_ENABLE 0x1a0 +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 13); /* TM2 enable */ + msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + + msr.lo |= (1 << 10); /* FERR# multiplexing */ + + // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + + // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(IA32_MISC_ENABLE, msr); + + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + +#if CONFIG_USBDEBUG_DIRECT +static unsigned ehci_debug_addr; +#endif + static void model_6ex_init(device_t cpu) { char processor_name[49]; @@ -66,13 +136,35 @@ fill_processor_name(processor_name); printk_info("CPU: %s.\n", processor_name); +#if CONFIG_USBDEBUG_DIRECT + // Is this caution really needed? + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + /* Setup MTRRs */ x86_setup_mtrrs(36); x86_mtrr_check(); - + +#if CONFIG_USBDEBUG_DIRECT + set_ehci_debug(ehci_debug_addr); +#endif + /* Enable the local cpu apics */ setup_lapic(); + /* Enable virtualization */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* TODO: PIC thermal sensor control */ + /* Start up my cpu siblings */ intel_sibling_init(cpu); } Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f257.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f257.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f257.h 2009-03-06 19:54:15 UTC (rev 3983) @@ -0,0 +1,291 @@ +//+++ +// Copyright (c) <1995-2008>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Wed Sep 10 11:53:28 CST 2008 */ +/* 2129-m206f257.inc */ +0x00000001, 0x00000057, 0x03152007, 0x000006f2, +0x07e77759, 0x00000001, 0x00000020, 0x00000fd0, +0x00001000, 0x00000000, 0x00000000, 0x00000000, +0xf0aefac0, 0x7c38e188, 0xba5a013f, 0xdfb167bf, +0x3c3fed5c, 0x9a7527d0, 0x7f3ae5a3, 0x8ab688d1, +0x348436ab, 0xdc4756d5, 0xfc2a0a22, 0x9f11b7bf, +0xa47e1335, 0xc1e04f7c, 0xdaaf86cf, 0xa870c161, +0x072e2279, 0x87ee60b8, 0x3e4b0622, 0x326b4d89, +0x0652f8e1, 0x2ea0c801, 0xbeaa5953, 0xdc1b6573, +0x701f392e, 0xed0630f9, 0xbc9b3dfa, 0x1640fe65, +0x571a23c1, 0x9d913021, 0x895d7d30, 0xd2d2d7d4, +0xd605ed58, 0x254a7575, 0x0cac66a8, 0xcfe8bbe5, +0xcdd30390, 0xbb2236d2, 0x4c5c5bee, 0x5aee0bec, +0xc7ccb2ce, 0x02e4a983, 0xc5920bf7, 0x4ce10d1f, +0x3fc17820, 0xda1b4e54, 0x3de20b4d, 0x5ff322d2, +0xd6de8959, 0xe35d9fbb, 0x7b450c74, 0xcdc09449, +0x25bb7745, 0x056e0ec0, 0x05c27088, 0xeece366b, +0xd99a08bd, 0xbf7aa5ff, 0xb99fb54a, 0x1e620294, +0x5498c8b6, 0x7e9feeb8, 0x0bd593db, 0x9ae9d723, +0xaf9ef586, 0xcf6b95a7, 0x8eb34bd2, 0x378c817a, +0xc0a0b5a8, 0xd92c8ec3, 0x756277de, 0x6c023ab6, +0x982be06c, 0xb8a70610, 0x7f5a8718, 0xa677cfa8, +0x2e7ade57, 0x3978eec5, 0xc34a97d1, 0x37733521, +0x5692ce95, 0x7b9fc090, 0x0d111e36, 0x6d9fb551, +0xc48f3b9e, 0x6a1b2dfc, 0x8ba4b179, 0xb00f6962, +0xfa149366, 0xbb1dc1b3, 0x23a921c0, 0xb96d73b7, +0xcd4dc6da, 0xfc5e8abb, 0xdb5fe0f2, 0xcb33f9dc, +0xaf75f866, 0x3dfd2478, 0xe7a5b475, 0x54a611b2, +0x73994c7d, 0x161b27bc, 0x7f810ba5, 0x8dd5733c, +0x72fe4c72, 0x2e76dbe3, 0x9f9f0c64, 0x0e21bdbd, +0x4331bf86, 0x879b1ddc, 0x40c84fce, 0x7c5d11c0, +0x3faf10ab, 0x3550eae6, 0x26996e67, 0x00ef27d2, +0xccda83ed, 0x11030e92, 0x757074d7, 0xc5a517dd, +0xfc3e7fd4, 0xc16d81ed, 0x9044cd87, 0x2d099580, +0xb25b9d47, 0x5b610359, 0x0e59eeb5, 0x7d19f029, +0x4cf9706f, 0x0f5c8597, 0xecf7aedb, 0x86d1ee8b, +0x2c85f041, 0x3015ac75, 0xa0db24d8, 0xa9f07271, +0xb78ec67e, 0xeca00670, 0xf7d05fe5, 0xdff30312, +0x6ae19969, 0x63375a04, 0x466a01f5, 0xc171c0da, +0x93ce8528, 0x703c1aed, 0xcd42cced, 0x32819c8d, +0xeb642286, 0x72723b25, 0x86c46d68, 0xb64d3c67, +0x3d3bb64c, 0x60eaf2be, 0x924b7f3d, 0x0bb38768, +0xaf2deef9, 0x2fa43b64, 0xdb0823ee, 0x7ddb339c, +0xea1cbf8a, 0xb19895d0, 0x1d6fd197, 0xb9a9343e, +0x31ce5f2e, 0x9399fc36, 0x14d6f1dd, 0xdd6ed0ac, +0xd9e8f45a, 0x56dba12c, 0xf5ef138a, 0x981a6eaf, +0x74fe5839, 0x370aab6a, 0x717df9f6, 0xa4dbc8d1, +0x3c665e8a, 0x07711522, 0x58911dfd, 0x9276384e, +0x70dd2327, 0x2613f4ad, 0x67043d57, 0x085bc73e, +0x13399b60, 0x28b0d7e3, 0xc7101b20, 0xa29550aa, +0x8177a1dc, 0x5bcc83b2, 0x1cf50fbc, 0x448c109a, +0x09288db1, 0x1700bdcf, 0xa119bf8e, 0xdaeb3c27, +0xf21a1004, 0x3490c7e4, 0x6562906d, 0x732225be, +0x4ca41b48, 0x9807ec37, 0x82c2c81a, 0x182ae052, +0x337f2a6c, 0x177a866f, 0xb0397a1e, 0x8aa9e3d2, +0xb596cae5, 0x52630925, 0x069e969f, 0xb8a6cf5d, +0xe206c823, 0x95768639, 0xeb9ef6c1, 0xdc879822, +0x805b7540, 0xdbdca41e, 0x92daf8aa, 0x2855131d, +0x98537e07, 0xf9f437ff, 0x4fd88be0, 0x07cadd26, +0x61c5f34a, 0xbb6a19cd, 0xc113d97e, 0xc2097fa8, +0x93df4c5c, 0x71f49496, 0xeeb280b9, 0xd8b31a12, +0x8c68fe2a, 0x6c85e6c5, 0x665d8833, 0xbf7ca2d8, +0x8ec9d5fb, 0x2d8ada4b, 0x1112da86, 0x1eadb344, +0x72bb72b4, 0x1146c42e, 0x9c4a1796, 0x103a8aa2, +0x4e22694d, 0xdabb9fb9, 0xa643d98b, 0xa1e82adb, +0x5e1f20ec, 0xc1179fc2, 0xdf5791d1, 0x1071ced5, +0x940a595b, 0x9d575c0c, 0x572a6eb6, 0x68866e0b, +0x2cc54642, 0xa0b47fe9, 0xd53f7591, 0x40c57980, +0x7e927dfc, 0xad644a5e, 0x2f6b3a0a, 0xb4c788d4, +0x59131505, 0xdf982aa7, 0x7eed9890, 0xc7a79316, +0xa390c1e8, 0xb6a81315, 0x8b6ecc2f, 0xa18d162e, +0xa96a54a1, 0xf9801a9e, 0x763aa20d, 0xfcba9e42, +0x1d8f9e51, 0xb63608fe, 0xd0bca8d5, 0xc05b6fc3, +0x1dabad44, 0x864011c5, 0x92a94ac3, 0x7e2bdb44, +0xf1e0e0a4, 0x4e988af4, 0x51934b03, 0xc2eb8a5d, +0xf58b0dfe, 0x88c9c264, 0xe81e0809, 0xb3087c8c, +0x1f0cdd31, 0xcab43925, 0x02120053, 0xd4d308cb, +0x5727a77a, 0xc0a58a07, 0x45b8004e, 0x4b887559, +0xd5a6cfbd, 0x096d6b43, 0x8f7c3cf9, 0x10a9f009, +0x8b55e8c8, 0x286cd461, 0x5d340d0f, 0x2e071f42, +0x3c156062, 0x4a2ba5ed, 0x466f979d, 0x36ad6534, +0x432a28d6, 0x23dd3681, 0xb782ecfd, 0x4ac65284, +0x190c3fe3, 0x32371293, 0x1b4a968c, 0x4d140c3b, +0xe9602892, 0xaa61bb7f, 0x87d82028, 0x833b076d, +0xf5dfc16a, 0xe7e7e8cc, 0x9b9b123d, 0xe55f7f06, +0x019ca425, 0x8c2ad978, 0x6e53312e, 0x4c68cc59, +0x1505573b, 0xe50246c3, 0xe13f8925, 0xb40d8c6a, +0x6df7688e, 0x64ddc299, 0xfa2de5ee, 0x8e22c09b, +0xfc43e080, 0x27bdf731, 0xbd811f19, 0x50eb4114, +0x33aefa80, 0x0dd5a922, 0xcb087d89, 0xf594aaaf, +0x469590d5, 0xc2610f7e, 0x357f27f1, 0xe30b5697, +0x744a47d4, 0x18703bcc, 0xbd00cbb4, 0x859b13b1, +0x83259929, 0x71700966, 0xa6586c05, 0x70a61cb9, +0x67af2d49, 0xbc1a3e58, 0xf6f3b5c7, 0x916983f3, +0x3b99438f, 0x993ea084, 0xd2e842ab, 0xaae24c93, +0x38902c9c, 0xcdcaa742, 0x1407900f, 0x4fa9a83f, +0x0d87845e, 0x3dab31dc, 0xd1f773ee, 0x0b5181b9, +0x0dd327f1, 0x9de29e99, 0x11d78ea2, 0xc66b0639, +0xc97fae80, 0xd352bbe1, 0xfc19afbc, 0x713381a9, +0x51b9502a, 0x355de567, 0x040ee678, 0xf4085bdf, +0xc8b52da4, 0x7b851dfd, 0x94f53879, 0x936c3596, +0x005b0eda, 0xb17d6d52, 0xf576900a, 0x99234c3d, +0xdd2388f3, 0x3920a2eb, 0xce320776, 0xbaa6bb20, +0x82ccef09, 0x15f3fa80, 0x30e218d5, 0x9f7c35f6, +0xfc422ad6, 0x697ba237, 0xe9bd989a, 0x20573da5, +0x526140be, 0x54023897, 0xd9ff4fbe, 0xee0c4495, +0xe62410a3, 0x5150c878, 0x9a2c671c, 0xf76de5ad, +0xd3eb74b4, 0x0688ec67, 0x7d4f12b3, 0x4fcbeb96, +0x81b9489b, 0x257b67a2, 0x0538b984, 0x4aeb1a19, +0xb3632b9f, 0x42148957, 0x71801f3e, 0x3ed494f4, +0xe1591118, 0xa4542eeb, 0xca3d0445, 0x03b948a9, +0x767a31b4, 0x090f62e1, 0x701890e7, 0x1cdf23f4, +0xaba00984, 0x1b42b0e0, 0xb5369d19, 0x0e582a3d, +0x079fc09d, 0x0a6b1256, 0x166e21c0, 0x4dfbf861, +0x68d90df7, 0x1392544f, 0x52e420f2, 0xaa437eb1, +0x355fe827, 0x5e5a497f, 0xb06b9003, 0x118c85ed, +0x7c8b1f9b, 0x710f30bf, 0xf42ad4e0, 0x70a17971, +0x3321840d, 0xebf2f3ca, 0x6820d080, 0xe5987997, +0xf1bcc9b5, 0x9357765e, 0x317884cf, 0x3449efff, +0x641d249c, 0x8dae0eec, 0xa5db1774, 0x1c06f4c6, +0x0dbd7c38, 0x18dd265a, 0x206eed23, 0x1b1f3780, +0x4e6b063c, 0x07169a13, 0x1b16ed6e, 0x87de6f65, +0xfe05eeca, 0xd3e6958f, 0xef53638e, 0xb8fa5b3a, +0xed4aa69c, 0xf229c96b, 0x922efea9, 0xf2e9f8d6, +0x7626207d, 0xac94bddd, 0xa055f4d1, 0x7cf49e93, +0xb68191fd, 0x5d1e0522, 0xb778bc1a, 0x667773ab, +0x0547d582, 0xb990ca6f, 0xae44199e, 0x090f8cbb, +0x66909346, 0x990b0a60, 0x866f804e, 0xafb29f1d, +0x85635204, 0x5531bc16, 0x766099af, 0x3128bdc5, +0x564838ac, 0x0f6a5d39, 0xc560f67b, 0xc7820c23, +0x05bb1328, 0x6f9484ee, 0x319809ab, 0xc0dead11, +0x30928a58, 0xcea6f365, 0xae4c63e2, 0x375bb2f5, +0x0d7b1cdb, 0x6777d042, 0x70d56f28, 0xa67ebccb, +0x1f02a61b, 0x148f5044, 0xa2ff3cd5, 0xdacfcf0e, +0xcec94c27, 0xee4af516, 0x0cddc248, 0x018cda30, +0x9d70143d, 0x197a6a8e, 0x6f651d33, 0x6faa4e8e, +0x8ebf8215, 0xead609df, 0xfd2f388b, 0xccb70ecc, +0x4a670925, 0xdd621f46, 0xb9e0bae9, 0xc9937471, +0x0a4232eb, 0xc7ba26cb, 0x8c3a7e17, 0xcef032c2, +0x73b75440, 0xcca87896, 0xb544c0d8, 0xcadfa89e, +0x3392961d, 0x5d99f95a, 0x00974612, 0xc5b871c6, +0x9336a0b2, 0x9dc01d28, 0xcf6f39e6, 0x847c7351, +0x0b990971, 0x70184dd8, 0xe5257c82, 0x721e7ef4, +0x8922a618, 0xacc61d52, 0xa31cb090, 0xec6e46bf, +0x0e22d152, 0x88c3a2f8, 0xd4cb10f6, 0x1e2bd43f, +0x67d26f37, 0xf6a2b4d3, 0xd4229cef, 0x89626856, +0x81400377, 0xa80b84d0, 0x1f5b6e64, 0xb5def54f, +0x8db7711e, 0x69b7f916, 0x1d3dda64, 0xe5c6d920, +0x6b3459ab, 0x5dc96ae2, 0x083308d7, 0xfa84b8a6, +0xb8f0a688, 0xa806c32f, 0x04d3a1a8, 0x58f5f04c, +0xf0233835, 0x7f5cb42f, 0x5eceef54, 0x577374c5, +0x51aa783b, 0x8ffe6da8, 0xc118f745, 0xe881675f, +0xb1e02bf3, 0x63db76ef, 0x8b0848ac, 0x0e0573ec, +0x1d4fc251, 0xf430354c, 0x38b5b60e, 0x0c942f9c, +0x67f1905c, 0x7428f8b0, 0x79297d7e, 0xa93f388c, +0x051e8616, 0x48e03984, 0x04d97406, 0x7413b6d4, +0x6a3f6f8d, 0xfaed5a44, 0xdc89c0a1, 0x1b2611d1, +0x21ca7dd6, 0x9c9d1448, 0xab3687c2, 0xc275130d, +0xbeec53d3, 0x93e05b62, 0xd164a9d6, 0x1418ada5, +0xcbb235da, 0x01cde834, 0x16d895fb, 0x5d916eeb, +0x2f8a4045, 0x671dd425, 0xab40ec3b, 0xed3eefda, +0xc1a93fd2, 0x348066fe, 0x538e9697, 0x3a73512a, +0x0eded14d, 0x7cc7085a, 0x1a769924, 0x8e11533c, +0xb961df1e, 0x73db50a8, 0xfe625496, 0x79b0bef6, +0x712f024b, 0x997a8bd8, 0x3009ce33, 0x38a922fa, +0x2f1b74d9, 0x70342c80, 0x587b1639, 0x9f02fd01, +0x5c8c4977, 0x6b0d1be1, 0xed9fb8fe, 0x0d1c9fa4, +0x3e51d08a, 0x2ecdd796, 0x71768e1b, 0x803c8b2d, +0xc009ac20, 0x242dc6ee, 0x6c9cfe25, 0x8cd3dbc4, +0xb35832db, 0x4613ba88, 0xab1274dd, 0xda19e833, +0x49c0fb40, 0xeb37ba33, 0xdf06e975, 0x90ad6d1b, +0x8aef380d, 0xa4cfb894, 0x107819ab, 0x01f89df1, +0x1ea242cc, 0x17626b76, 0x9568d1a8, 0x3e584238, +0x9c0ba10f, 0x3de6d8b8, 0xbcff277e, 0x94ba4d60, +0x24f88a80, 0x7d336afe, 0x04f4af38, 0xa435ae27, +0x82c5de40, 0x28b78b43, 0x5f4f3836, 0x809d1a13, +0xdb95ee3a, 0xacc8e9b4, 0xd0d6cf98, 0x9ba813cc, +0x6e89a462, 0x2afbe3c3, 0x5d662eef, 0x5365d477, +0x98bd0b86, 0x81c1601f, 0x15cd7693, 0x8b3d7ef9, +0xaf25331e, 0x49c24e40, 0xe6e8a26c, 0x0f083b65, +0xdcaa15a9, 0x26101687, 0x9dd1cad9, 0x80a9b15b, +0xac16e5e1, 0xb85861bd, 0x78c59bbe, 0x284648f0, +0x1f1af2cf, 0xbb834fbf, 0xd7d71460, 0xcf44c671, +0x573bd611, 0x76e94cde, 0x17c03286, 0x02621543, +0x705d0c85, 0x2b6d6b0f, 0xa8f17a22, 0xbde3ed1e, +0x09afd9cc, 0xf84955f8, 0xa7d1dabb, 0x82343b59, +0xa3fbc5f1, 0xfcdce701, 0xd600158c, 0x71262e33, +0xcb257268, 0xf3f17de9, 0x257ec37e, 0x366552f6, +0xd39c706d, 0x1372a7ef, 0x84fb48ea, 0xf1c4776a, +0x182f548f, 0xa5499971, 0x488e7904, 0x4167ba8d, +0x796aa238, 0x41eedf0e, 0xe65e7ffc, 0x7352ab66, +0x7ea8d981, 0x93c717f5, 0xc8124404, 0xa7447a65, +0x231dd863, 0x17581b25, 0xd10a9250, 0x5807994a, +0x12b18ae5, 0x80d03bbb, 0x7595c1b1, 0x6e878a42, +0xbc2db045, 0xde5c7e5d, 0x8f096855, 0x82dc150c, +0x7afd3dca, 0xf274e65a, 0x2abbe67f, 0x0145568c, +0x014dba37, 0x9a182028, 0xd71618ac, 0xc87934bd, +0xe96101d1, 0x55d1976c, 0x471c8505, 0x7a36d839, +0x5d62a9ee, 0xf3c54a8a, 0xa2be15d9, 0x244087c9, +0x042c8037, 0x23224689, 0x281c5d73, 0x2139ecfc, +0xffb8bc8a, 0x834fdd11, 0x9cd5a5bd, 0xa3368319, +0x7e5bef0c, 0x4ae2dbda, 0x86d90089, 0x6675dfce, +0x48876262, 0xcec72538, 0x11dc5c80, 0x86a730f9, +0x313565c9, 0xe3e5be11, 0x106d7cce, 0x752b8be2, +0x3d00a5bc, 0xe6f70e95, 0x44447ac8, 0x600df30c, +0x8335ac3b, 0x8816ddee, 0x700982fe, 0xee495741, +0x48c7e81c, 0xa3d55da2, 0xb0172982, 0x70ab2158, +0xd4460621, 0x3a9e528b, 0x59b18a7b, 0xf4dabc4c, +0xa8454763, 0x70877bb6, 0x66005c97, 0xaf292c06, +0x7b843db1, 0xf343b59b, 0x25cdc7b5, 0xa41da617, +0x9e9d895e, 0xc936f475, 0x7270925a, 0x30024230, +0x8e72f53d, 0x2b6c1b6f, 0x1a69732c, 0x7ed5aff5, +0xfc18a2a3, 0xaf377cc1, 0xbff09a78, 0x4b4e0814, +0x95a0b2c1, 0x270398de, 0x201fca94, 0x2a032a4f, +0x131542b4, 0x0d7306da, 0x2d1c3496, 0xcc3c6d8d, +0xa814ddc9, 0xa3b3a991, 0x17ee60c2, 0x852c0b8d, +0x11e5853a, 0x762002a7, 0x92c5311d, 0x0d4bf7e1, +0xfffec870, 0xe3d35e5b, 0xff6ecfb9, 0xdedae6ff, +0x0111a772, 0x9808e780, 0x29c336e8, 0xe9bc05df, +0x5bedde11, 0x945565af, 0xaff808fe, 0x87e3423d, +0x4de6f98f, 0x93b4adef, 0xbf704fa4, 0x09120e91, +0xd54f3692, 0xdf8eab1e, 0xfabbf59c, 0xe74318be, +0xaab87ffc, 0x29fa791c, 0xe3915552, 0xa652cb9b, +0xa1252e74, 0xb35b723b, 0x542aa28b, 0x12fcc5b0, +0x3941f962, 0x82bcc6cc, 0x47b11974, 0xb821611f, +0x78b34250, 0xf1be5659, 0x561b9e61, 0x6f3bd501, +0x584e6f5c, 0xd54ed547, 0xacebcd21, 0x7b5ff816, +0xb64ad233, 0x9f2f330d, 0x69fb1ece, 0xac8710dd, +0x58dc6c60, 0x9bee6139, 0xbb10ad0e, 0xbd8cd5dd, +0xebc0ce9d, 0xa733274f, 0x884d9b55, 0x42b08b63, +0xafa54a74, 0x1c7ccf64, 0x93a20191, 0xaaa3132e, +0xc69831d1, 0x54634889, 0xfbfe3efc, 0xd3cf68d4, +0x302e3117, 0xf5693131, 0xc3ce8c6c, 0x1f03cd89, +0x6243334c, 0xf16bc80f, 0xdca5f130, 0xcb2cd956, +0x4c1bb421, 0xe8de533c, 0x7f86703a, 0x29aa897e, +0xdd54acad, 0x76b2f2ae, 0x7ef82b71, 0x2e30970b, +0xba402597, 0x9a653ab4, 0xd68fcf53, 0x2d9f0d15, +0x7f9efd1c, 0x2363d147, 0x5327289a, 0xe89229f3, +0xd63a535c, 0x7efe9273, 0x64f2e3a3, 0x9bdf65a7, +0x26b6edfb, 0x1b9c7bfe, 0x5d14b3de, 0x54d575fb, +0x6d65db4c, 0x95648b7f, 0xa8a3b8f0, 0x7cc7ad46, +0xe20e6dbb, 0x8488a45f, 0x8ebc2932, 0xd4767316, +0x3e8c4b8a, 0xbab7402c, 0xfc1e217e, 0xe5c5bf82, +0x6928fe2e, 0xc88528e9, 0x4b2e4e8f, 0xdd938b86, +0x0c964f98, 0xfc88d480, 0x35fcaf9e, 0xdd7bbe9d, +0x197d005a, 0x4d40b3b3, 0xcf203155, 0x0d2fa621, +0x752d2c58, 0xb12bac12, 0x1e7e8c23, 0x94215d54, +0x9854a71c, 0x4de63c64, 0x7a012529, 0x9c171f8d, +0x9e71def7, 0x3bd17d50, 0x11f175d9, 0xec78abf3, +0x7b529eee, 0xd3a69fc3, 0x5b718676, 0x58214d29, +0xa8bd2c34, 0x41ea00ab, 0xa03f64d6, 0x4ee342b0, +0x32b1e444, 0x1c1801a4, 0xc8424702, 0x334a7e35, +0x50cf1543, 0x3b22b495, 0x88683776, 0x8e2e0154, +0x6155c033, 0x4e2fa6ac, 0x42ace700, 0x8d64f97c, +0xaf9ced17, 0xb2a5cb92, 0xa558582d, 0x88705de7, +0x9e528d59, 0x84bd45e4, 0x5cb680c0, 0xcd48fa5c, Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f6c7.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f6c7.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/microcode_m206f6c7.h 2009-03-06 19:54:15 UTC (rev 3983) @@ -0,0 +1,291 @@ +//+++ +// Copyright (c) <1995-2008>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Wed Sep 10 11:53:28 CST 2008 */ +/* 2127-m206f6c7.inc */ +0x00000001, 0x000000c7, 0x03152007, 0x000006f6, +0xd863aca5, 0x00000001, 0x00000020, 0x00000fd0, +0x00001000, 0x00000000, 0x00000000, 0x00000000, +0xf135893c, 0x4c42e3f3, 0xb73a55b6, 0x351ee5de, +0xb62b15d8, 0xa4b7a683, 0x15e59363, 0xb5a88344, +0x83cb3484, 0x27b18c8d, 0x94d04ac1, 0x8f1f77db, +0x13b4b7fe, 0xa649fe2c, 0xb24e07e8, 0x1599f3a0, +0xb3769963, 0xa12ac372, 0x250722b3, 0x9d15fb7d, +0x9813a1b2, 0x117335fd, 0x8c1230f9, 0x81968e27, +0x05a86156, 0x9b82a393, 0x9169c94d, 0x31b89d77, +0x973c1fb2, 0x8f75d325, 0x6386e9f8, 0xa8df1a90, +0xea70b02b, 0x5eb51ed7, 0x8c97f33c, 0xf9c1b8a6, +0x5eb80126, 0xbec523d7, 0xb974f767, 0x73b44b82, +0xf832f648, 0x8d196107, 0x7c0879bf, 0xcd6d630c, +0x22466897, 0x4816ea2d, 0x6efda835, 0x25832e9b, +0x7898d668, 0x59131743, 0x0f5c9772, 0x6f5a9ec7, +0xbe40da64, 0x2d376de9, 0x85fdddd4, 0x9721c351, +0x12a9d1de, 0xbfb37d7c, 0xb21a779f, 0x2593f254, +0xa1737d77, 0x9aa94919, 0x314de914, 0xb56a3111, +0x82a98637, 0x15fcc11e, 0x882e1550, 0x9dc71080, +0x2effb94c, 0xaca5f479, 0xaa2db04b, 0x2ec75a37, +0x80c324c1, 0xb387798a, 0x092e24c6, 0x82f54f78, +0x2799d295, 0x010b6198, 0x38d497ab, 0x255044a9, +0x28f09f9f, 0x12e3669b, 0x2937f975, 0x21332882, +0x2a0c3de4, 0x127b6e06, 0x196c4c4a, 0x339de5f3, +0x2d1952eb, 0x11b661e9, 0x38c5a4d9, 0x08d02b39, +0x07714640, 0x14394d59, 0x3e2f5bbd, 0x0898e888, +0x3ebde0c8, 0x11078f3c, 0x32e047cd, 0x3b8a1671, +0x3d5400a2, 0x1ee97d92, 0x057760c9, 0x31ddc483, +0x6b672bb1, 0x0239c65b, 0x5168de3c, 0x57da3987, +0x0a411c03, 0x6ac8c9c3, 0x38c1814d, 0x138ae982, +0x17fe9610, 0x22c1b2c2, 0x0f64d62b, 0x292f29a6, +0x172bd3a3, 0x2660983f, 0x3f34706f, 0x17ddc325, +0x3be7c056, 0x24297b2c, 0x0d7b4a97, 0x1ccace5e, +0x362c300c, 0x2d8a24c7, 0x40a8b209, 0x27e2b212, +0x51f58204, 0x47291d65, 0x049de5d0, 0x620f697e, +0x4a407809, 0x2c8afcc9, 0x3adb22f4, 0x4dec3b92, +0x46981a3b, 0x379b774c, 0x7f3ab853, 0x7d8d941d, +0x35d5717b, 0x4865f240, 0x657ae90a, 0x38db767f, +0x5ba5af85, 0x624bde90, 0x27ca5b94, 0x7d6de192, +0x74752869, 0x1aa685e2, 0x626ac31b, 0x78db6d6c, +0x10924be8, 0x7f5fa69a, 0x70b7ba13, 0x35ea4627, +0x6e8d8ce0, 0x5a36f924, 0x368ab401, 0x7271a3bb, +0x5a552eaa, 0x32d42181, 0x6db87723, 0x6459b69e, +0x3b7f2229, 0x516935fe, 0x7af35a05, 0x34d6f025, +0x4fb65637, 0x7f9446c9, 0x29279aae, 0x630458d9, +0x7d91017f, 0x12138189, 0x670175f5, 0x79410f28, +0x10096979, 0x6c00509a, 0x65007291, 0x231b6f99, +0x6c086043, 0x4bb85e3c, 0x2a14b537, 0x75ac8df6, +0x50f5171f, 0x3872a743, 0x624efe16, 0x654ede16, +0x388a9b3a, 0x52e4d776, 0x7875c3b4, 0x2487fd53, +0x468cd150, 0x6d323e69, 0x2ce7e3c2, 0x695c3c62, +0x77e824a3, 0x11756de6, 0x7bf7c901, 0x74e5c26d, +0x1afa9675, 0x69b9df37, 0x73b86637, 0x24e87f5d, +0x7c0e8526, 0x4901376c, 0x31fb6e1b, 0x660dbe1a, +0x53170be5, 0x21c35688, 0x73503139, 0x6064b5df, +0x29ba71f5, 0x53bdb0d1, 0x6536739e, 0x3a25f143, +0x443e2b84, 0x73bb1a43, 0x3711fbe7, 0x7c6e4a38, +0x7780f574, 0x16901e72, 0x69e9671d, 0x60ec9c20, +0x06890195, 0x7bb14d4b, 0x6292324e, 0x32c9abed, +0x799488db, 0x50b9af33, 0x299b8a16, 0x7209f8e0, +0x5add0439, 0x28f8fc56, 0x7f63fe6b, 0x71275304, +0x20b6a475, 0x4c9bdbbe, 0x662f84b0, 0x3d6cc2d1, +0x47d6afa4, 0x7ad1c011, 0x2ead22c5, 0x7d908a65, +0x6e6ccec4, 0x1d7689f7, 0x6ee48904, 0x733ccb6f, +0x1da0fb77, 0x7bb09d43, 0x7321dd51, 0x2701892c, +0x7d84793d, 0x4d6492cc, 0x2fa9a321, 0x76b7e6e2, +0x465dbd1c, 0x33b7fe03, 0x6282c0fc, 0x6301d671, +0x08afdd4b, 0x521c30f9, 0x165202e8, 0x0401a7ed, +0x32d4bdcd, 0x37002f6e, 0x29e0b079, 0x3b8f70e6, +0x1f32ea74, 0x17ca355f, 0x19c8eceb, 0x109551cd, +0x046136e7, 0x0d1b04c2, 0x3599e1f5, 0x3abb8250, +0x1bfa131d, 0x12193715, 0x77cdde86, 0x065f6895, +0x51718435, 0x4731e28b, 0x285fdb8c, 0x4fa6e3cc, +0x6aa41e77, 0x18cc12b7, 0x3d9bd449, 0x68254258, +0x41e7cb3e, 0x25b2eb61, 0x42133e78, 0x64f82d73, +0x112e4c48, 0x798379b6, 0x5f33622d, 0x14d4b234, +0x6325e99e, 0x524dd17f, 0x04ecf1c3, 0x49e60429, +0x7065602d, 0x2b0d9ae7, 0x5e7c9b5a, 0x780d283b, +0x0c835bcc, 0x6721511f, 0x75b36f07, 0x134145d7, +0x0e814738, 0x4e0aa44d, 0x51a96127, 0x188d63ea, +0x463147c0, 0x7477864c, 0x220d2e93, 0x4eca7e2f, +0xc1de753e, 0x078e240c, 0x80b8951a, 0xcd8c655b, +0x6157aed4, 0xbf7a4cbb, 0xeedfff8d, 0x6b6efec2, +0x3918ac62, 0xd2154ed5, 0x9d7ef787, 0x3cd4ca4d, +0x83cfb39b, 0xb2e41461, 0x177ed847, 0x979b8263, +0x063e5288, 0x25686303, 0x6ac4c002, 0x1daaee7b, +0x44a872f5, 0x6920fad9, 0x1615e22f, 0x7ee6b668, +0x46a20eca, 0x3f70299f, 0x6804ec4f, 0x438f3d2b, +0x21981b39, 0x56c56c26, 0x790e53f9, 0x3d075619, +0x73ec2706, 0x461887a3, 0x3289a477, 0x6dc41ff3, +0x7f5575d9, 0x15c41603, 0x5b529716, 0x75fe042a, +0x1ad545a3, 0x6c3bda68, 0x63a22b88, 0x0c762a66, +0x6414a225, 0x4211a57d, 0x3ee18677, 0x70672a56, +0x2263d25f, 0x147a0102, 0x2abb0809, 0x36d405a0, +0x370f7ebd, 0x3a633ec6, 0x21f35ed3, 0x0eaa0a9c, +0x18776376, 0x0d7cb3ae, 0x0c317ba7, 0x0e7f0abc, +0x04259abe, 0x02f52088, 0x030df095, 0x20c29d81, +0x882c52ea, 0x2d580ecc, 0xa92564dc, 0x802796ac, +0x3219a158, 0x9f257e87, 0x9cc10ff5, 0x34274f65, +0x83ee1c46, 0xa0220012, 0x1dde176a, 0x8bfbd3cf, +0xc1205b06, 0x3bd2cafc, 0xfb023b16, 0xca0dfb9b, +0x0a339312, 0xce3891c9, 0xd5f95269, 0x01011bc3, +0xda50d4a6, 0xe4bb68a0, 0x38a2d750, 0xcfea1bc8, +0x8f5e797c, 0x013aadfa, 0xf591d8c8, 0x8ee4aa28, +0x7355b612, 0xee0428b4, 0x9ae443a0, 0x6feac10a, +0xfd4339ca, 0x846da8fc, 0x0502cee5, 0xf4257dfc, +0xc9da3d3e, 0x3b300835, 0xde8627da, 0xcd8bea50, +0x1c8e4efc, 0xeb473eae, 0xe55d5e4b, 0x1627425e, +0xc596048d, 0xc625faa2, 0x1320a228, 0xc49aec7f, +0xeec906ce, 0x353f3489, 0xdfc5495e, 0xefa721f4, +0x35be9794, 0xe644add2, 0xd48800ba, 0x26d27892, +0xfac89ec0, 0xf876f427, 0x06861fa0, 0xe89c1407, +0xad86305a, 0x0031d329, 0xaec58f29, 0x9ded7311, +0x0f535848, 0x89751f81, 0x9453a5bd, 0x0593b715, +0x9cfb5340, 0x8f8cc387, 0x0ba81c6b, 0xab249d09, +0x47b98128, 0x3a59a622, 0x6bcc7e6d, 0x490d3f9e, +0x194d7172, 0x43bc0d54, 0x476d5302, 0x0e79ab9d, +0x043a2e4e, 0x6e23d982, 0x4f9275a2, 0x13482aaf, +0x4cd88767, 0x417af7bf, 0x2670b7b6, 0x6e3159e1, +0x7ee5fb88, 0x1690d436, 0x7c204b0c, 0x7f7bd21e, +0x1c44e6bd, 0x72aa216e, 0x762740e1, 0x3195f0af, +0x68f7a632, 0x405a48de, 0x4f47cf2b, 0x74802579, +0x306f294c, 0x5c40b9a2, 0x44882623, 0x1bc24415, +0x57479859, 0x77f1f9b6, 0x75e1d617, 0x5c0f58e0, +0x09ea315f, 0x439d0666, 0x7c896e85, 0x02a7bb07, +0x6faf5510, 0x4d84a791, 0x27fe2b91, 0x68aa7491, +0x52973597, 0x0222a1a1, 0x621446c4, 0x4e8a2246, +0x018f0189, 0x52fe91c5, 0x5c1dc78b, 0x0f3df43e, +0x46b83eca, 0x5ec0e882, 0x0794307d, 0x6fc5de80, +0x49d5654e, 0x354ee67c, 0x710ff7c0, 0x4ea654ae, +0x1c6b7d3b, 0x6e8a2a53, 0x77a83c55, 0x3876439d, +0x6c9b745e, 0x6caf0739, 0x5cdbcbb5, 0x2476ae0e, +0x0bb3d90e, 0xa6bfe765, 0x5ea2df7b, 0xf0787223, +0xce1d2f30, 0xe3f585a9, 0x862936aa, 0x760f8e61, +0xbe83028a, 0xe8b5836a, 0x3f511b31, 0xc14765f3, +0xcb58aca3, 0xcba6b2cd, 0xe4663a5d, 0x306d3a63, +0x9f92084b, 0x9ede4973, 0x782c5d7e, 0xff753f56, +0xe863b9fe, 0xb48dae56, 0x926718e6, 0x3f2df5a7, +0xb96e9045, 0xa7ffe8e3, 0x3d712112, 0x96a37460, +0xcf6d2da6, 0xb453af2f, 0xe2738a18, 0x46eab1c6, +0xb33f26c8, 0xacfaa37e, 0x5545aef9, 0xf6ee57bc, +0x9ab32696, 0x60f08210, 0xc6a68785, 0xbe0f8a26, +0x6ec47920, 0x6fd6f0d2, 0xbe21a54b, 0xc1ed9f13, +0x779b8ab2, 0x601e0135, 0xd707f98a, 0xbe8ba28c, +0x490cf7d2, 0xdabad447, 0x8e0447e3, 0x5aa97c13, +0xe0fa4ffc, 0x87c56421, 0x744c8d5d, 0xff38fc68, +0xeeb31201, 0x5183cc8b, 0x8cf20994, 0xd8043432, +0x5d9fe6c1, 0x5e1874f0, 0xc2955a2f, 0x84390ab0, +0x3ef119f8, 0x84f1a150, 0xedfd1684, 0x6b244bce, +0xef6b8b37, 0xd2b4b735, 0x0aabcb89, 0xc50ab6b6, +0xe99f0600, 0x016503fb, 0xeac92d6b, 0xe17828bb, +0x6f54ab62, 0xe442ad55, 0x8ac94c9c, 0x7fbd6462, +0x95fbbc51, 0x4312f35f, 0x15f95b03, 0x4b376589, +0x30054b1f, 0x4f93b30f, 0x3f893784, 0x7b1fe40d, +0x302a042a, 0xa7b52297, 0x1baf4c24, 0xb2d8045d, +0xc59c87e5, 0x6182bfae, 0xc0177c03, 0xa07f2b7d, +0x6d3c9042, 0xe119b6c0, 0xb95000e4, 0x5ef06018, +0xe329fddd, 0xb6c351e9, 0x561a9f22, 0x0e3d0ee5, +0xb1d82fa7, 0x24e5a591, 0x0f877f43, 0xc7fbf6dd, +0x2bd640c4, 0xac411744, 0xc0572fb3, 0x814e269f, +0xbff658b7, 0xa6fb6709, 0x8eb94c8a, 0xdd59b669, +0xaec2ec83, 0x0f975d58, 0xc007e63e, 0x34f1ef97, +0x1093e9ae, 0xf10306c2, 0x371d2ba6, 0x06d529e5, +0xcc5ba006, 0x62720191, 0x2760d5d9, 0xbcf9f2ef, +0x6cf26009, 0x3cc648ba, 0xad069852, 0x79d86abd, +0x2bd13a45, 0x6c59ab96, 0x7fe93fa9, 0xf4f9c8c4, +0x6659306e, 0x4ceb3f8e, 0xf8f3b54f, 0x22d47284, +0x25f00ac3, 0xdf42abde, 0x48232afe, 0x6b12c85a, +0xd3689402, 0x439533cc, 0x699ed29c, 0xc8579683, +0x4083f273, 0xc0133829, 0xcb4319da, 0xef666889, +0xdd90130f, 0xd6b42043, 0xfea82ce5, 0xc974a1c8, +0xc16fa70d, 0xf704cc46, 0xdde80293, 0xd19e56a5, +0xe92cc8b6, 0x50e56bf3, 0xc7c8b490, 0x7824c8ac, +0x49e11bfd, 0x5b430d40, 0x73b0ca71, 0x24d265ae, +0xab0c7b5b, 0x26f970b0, 0xc6ef1791, 0xe04eb2a0, +0x85f9948b, 0xde0bf679, 0x4a7dfccb, 0x93201bf0, +0x8a5898ba, 0xa2c8afb0, 0xdc169dda, 0x62eaa056, +0xbee610e4, 0xcfe62b41, 0x683c035e, 0xb154a8ff, +0x5bc3c6e1, 0x7f72f3f8, 0x2634ae89, 0x4dfab058, +0x0ecbcc90, 0x73948eaf, 0x2002cc46, 0x402c28ea, +0x316ee39e, 0x3491bc24, 0x05f329d3, 0x3e1b39ed, +0x8f939791, 0x3e8081e0, 0x9e3471fc, 0xb768956e, +0xf5001d85, 0xdd6a5d5f, 0x72f9ac8b, 0xa39e90b7, +0xda690817, 0x699362ea, 0xb1611e17, 0xd44046c6, +0x33771d3e, 0xe884be2f, 0x8c7a72d7, 0x7e51529d, +0xe1807e89, 0xa07cdfde, 0x64e8c668, 0xd3774939, +0xe8261a25, 0x430c6240, 0x991408e5, 0xd01517e0, +0xacfe1fbb, 0xd7aeeb57, 0x22ccc0c2, 0xfd449c99, +0x2d3f390f, 0x30f54c8c, 0x0dde0c1d, 0x3cb3c009, +0x5729d223, 0x6a25e468, 0x44eb6c4e, 0x3e5863e9, +0xa9639ce4, 0x096bf738, 0xea20cefb, 0xe187f5c8, +0x418ccab3, 0x4bc370ca, 0xa1200b64, 0xebcfc110, +0xeb942278, 0x4ba5d196, 0x48a7b4d0, 0x07aeaf38, +0xb7b71ee5, 0x59184abf, 0xfa2b23bc, 0xbcc9da17, +0xd846d1fc, 0x214f1278, 0x2bf7e99f, 0x1a04261a, +0xd7f6e905, 0x86ea57d7, 0xd71618ac, 0xc87934bd, +0xe96101d1, 0x55d1976c, 0x471c8505, 0x7a36d839, +0x5d62a9ee, 0xf3c54a8a, 0xa2be15d9, 0x244087c9, +0x042c8037, 0x23224689, 0x281c5d73, 0x2139ecfc, +0xffb8bc8a, 0x834fdd11, 0x9cd5a5bd, 0xa3368319, +0x7e5bef0c, 0x4ae2dbda, 0x86d90089, 0x6675dfce, +0x48876262, 0xcec72538, 0x11dc5c80, 0x86a730f9, +0x313565c9, 0xe3e5be11, 0x106d7cce, 0x752b8be2, +0x3d00a5bc, 0xe6f70e95, 0x44447ac8, 0x600df30c, +0x8335ac3b, 0x8816ddee, 0x700982fe, 0xee495741, +0x48c7e81c, 0xa3d55da2, 0xb0172982, 0x70ab2158, +0xd4460621, 0x3a9e528b, 0x59b18a7b, 0xf4dabc4c, +0xa8454763, 0x70877bb6, 0x66005c97, 0xaf292c06, +0x7b843db1, 0xf343b59b, 0x25cdc7b5, 0xa41da617, +0x9e9d895e, 0xc936f475, 0x7270925a, 0x30024230, +0x8e72f53d, 0x2b6c1b6f, 0x1a69732c, 0x7ed5aff5, +0xfc18a2a3, 0xaf377cc1, 0xbff09a78, 0x4b4e0814, +0x95a0b2c1, 0x270398de, 0x201fca94, 0x2a032a4f, +0x131542b4, 0x0d7306da, 0x2d1c3496, 0xcc3c6d8d, +0xa814ddc9, 0xa3b3a991, 0x17ee60c2, 0x852c0b8d, +0x11e5853a, 0x762002a7, 0x92c5311d, 0x0d4bf7e1, +0xfffec870, 0xe3d35e5b, 0xff6ecfb9, 0xdedae6ff, +0x0111a772, 0x9808e780, 0x29c336e8, 0xe9bc05df, +0x5bedde11, 0x945565af, 0xaff808fe, 0x87e3423d, +0x4de6f98f, 0x93b4adef, 0xbf704fa4, 0x09120e91, +0xd54f3692, 0xdf8eab1e, 0xfabbf59c, 0xe74318be, +0xaab87ffc, 0x29fa791c, 0xe3915552, 0xa652cb9b, +0xa1252e74, 0xb35b723b, 0x542aa28b, 0x12fcc5b0, +0x3941f962, 0x82bcc6cc, 0x47b11974, 0xb821611f, +0x78b34250, 0xf1be5659, 0x561b9e61, 0x6f3bd501, +0x584e6f5c, 0xd54ed547, 0xacebcd21, 0x7b5ff816, +0xb64ad233, 0x9f2f330d, 0x69fb1ece, 0xac8710dd, +0x58dc6c60, 0x9bee6139, 0xbb10ad0e, 0xbd8cd5dd, +0xebc0ce9d, 0xa733274f, 0x884d9b55, 0x42b08b63, +0xafa54a74, 0x1c7ccf64, 0x93a20191, 0xaaa3132e, +0xc69831d1, 0x54634889, 0xfbfe3efc, 0xd3cf68d4, +0x302e3117, 0xf5693131, 0xc3ce8c6c, 0x1f03cd89, +0x6243334c, 0xf16bc80f, 0xdca5f130, 0xcb2cd956, +0x4c1bb421, 0xe8de533c, 0x7f86703a, 0x29aa897e, +0xdd54acad, 0x76b2f2ae, 0x7ef82b71, 0x2e30970b, +0xba402597, 0x9a653ab4, 0xd68fcf53, 0x2d9f0d15, +0x7f9efd1c, 0x2363d147, 0x5327289a, 0xe89229f3, +0xd63a535c, 0x7efe9273, 0x64f2e3a3, 0x9bdf65a7, +0x26b6edfb, 0x1b9c7bfe, 0x5d14b3de, 0x54d575fb, +0x6d65db4c, 0x95648b7f, 0xa8a3b8f0, 0x7cc7ad46, +0xe20e6dbb, 0x8488a45f, 0x8ebc2932, 0xd4767316, +0x3e8c4b8a, 0xbab7402c, 0xfc1e217e, 0xe5c5bf82, +0x6928fe2e, 0xc88528e9, 0x4b2e4e8f, 0xdd938b86, +0x0c964f98, 0xfc88d480, 0x35fcaf9e, 0xdd7bbe9d, +0x197d005a, 0x4d40b3b3, 0xcf203155, 0x0d2fa621, +0x752d2c58, 0xb12bac12, 0x1e7e8c23, 0x94215d54, +0x9854a71c, 0x4de63c64, 0x7a012529, 0x9c171f8d, +0x9e71def7, 0x3bd17d50, 0x11f175d9, 0xec78abf3, +0x7b529eee, 0xd3a69fc3, 0x5b718676, 0x58214d29, +0xa8bd2c34, 0x41ea00ab, 0xa03f64d6, 0x4ee342b0, +0x32b1e444, 0x1c1801a4, 0xc8424702, 0x334a7e35, +0x50cf1543, 0x3b22b495, 0x88683776, 0x8e2e0154, +0x6155c033, 0x4e2fa6ac, 0x42ace700, 0x8d64f97c, +0xaf9ced17, 0xb2a5cb92, 0xa558582d, 0x88705de7, +0x9e528d59, 0x84bd45e4, 0x5cb680c0, 0xcd48fa5c, Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c 2009-03-06 19:52:36 UTC (rev 3982) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c 2009-03-06 19:54:15 UTC (rev 3983) @@ -12,7 +12,8 @@ #include static const uint32_t microcode_updates[] = { - // #include "microcode_m206e839.h" + #include "microcode_m206f257.h" + #include "microcode_m206f6c7.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -52,8 +53,122 @@ strcpy(processor_name, processor_name_start); } -static void model_6ex_init(device_t cpu) +#define IA32_FEATURE_CONTROL 0x003a + +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +static void enable_vmx(void) { + struct cpuid_result regs; + msr_t msr; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + regs = cpuid(1); + if (regs.ecx & CPUID_VMX) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + +#define PMG_CST_CONFIG_CONTROL 0xe2 +#define PMG_IO_BASE_ADDR 0xe3 +#define PMG_IO_CAPTURE_ADDR 0xe4 + +#define PMB0_BASE 0x580 +#define PMB1_BASE 0x800 +#define CST_RANGE 2 +static void configure_c_states(void) +{ + msr_t msr; + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + + msr.lo |= (1 << 15); // config lock until next reset + msr.lo |= (1 << 14); // Deeper Sleep + msr.lo |= (1 << 10); // Enable IO MWAIT redirection + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo |= (1 << 3); // Dynamic L2 + + wrmsr(PMG_CST_CONFIG_CONTROL, msr); + + /* Set Processor MWAIT IO BASE */ + msr.hi = 0; + msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); + wrmsr(PMG_IO_BASE_ADDR, msr); + + /* Set IO Capture Address */ + msr.hi = 0; + msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16); + wrmsr(PMG_IO_CAPTURE_ADDR, msr); +} + +#define IA32_MISC_ENABLE 0x1a0 +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 13); /* TM2 enable */ + msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + + msr.lo |= (1 << 10); /* FERR# multiplexing */ + + // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + + /* Enable C2E */ + msr.lo |= (1 << 26); + + /* Enable C4E */ + /* TODO This should only be done on mobile CPUs, see cpuid 5 */ + msr.hi |= (1 << (32 - 32)); // C4E + msr.hi |= (1 << (33 - 32)); // Hard C4E + + /* Enable EMTTM. */ + /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */ + msr.hi |= (1 << (36 - 32)); + + wrmsr(IA32_MISC_ENABLE, msr); + + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + +#define PIC_SENS_CFG 0x1aa +static void configure_pic_thermal_sensors(void) +{ + msr_t msr; + + msr = rdmsr(PIC_SENS_CFG); + + msr.lo |= (1 << 21); // inter-core lock TM1 + msr.lo |= (1 << 4); // Enable bypass filter + + wrmsr(PIC_SENS_CFG, msr); +} + +#if CONFIG_USBDEBUG_DIRECT +static unsigned ehci_debug_addr; +#endif + +static void model_6fx_init(device_t cpu) +{ char processor_name[49]; /* Turn on caching if we haven't already */ @@ -66,19 +181,42 @@ fill_processor_name(processor_name); printk_info("CPU: %s.\n", processor_name); +#if CONFIG_USBDEBUG_DIRECT + // Is this caution really needed? + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + /* Setup MTRRs */ x86_setup_mtrrs(36); x86_mtrr_check(); - + +#if CONFIG_USBDEBUG_DIRECT + set_ehci_debug(ehci_debug_addr); +#endif + /* Enable the local cpu apics */ setup_lapic(); + /* Enable virtualization */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* PIC thermal sensor control */ + configure_pic_thermal_sensors(); + /* Start up my cpu siblings */ intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { - .init = model_6ex_init, + .init = model_6fx_init, }; static struct cpu_device_id cpu_table[] = { From stepan at coresystems.de Fri Mar 6 20:54:44 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Fri, 06 Mar 2009 20:54:44 +0100 Subject: [coreboot] [PATCH] v2: add support for mainboard specific SMM code In-Reply-To: <20090306194254.12255.qmail@stuge.se> References: <49B1752B.3050409@coresystems.de> <20090306194254.12255.qmail@stuge.se> Message-ID: <49B17F84.8010308@coresystems.de> On 06.03.2009 20:42 Uhr, Peter Stuge wrote: > Stefan Reinauer wrote: > >> * fix a minor power state issue in the ich7 smm handler >> * move mainboard dependent code into a mainboard SMI handler. >> >> Signed-off-by: Stefan Reinauer >> > > Acked-by: Peter Stuge oops, sorry, this one is r3982 -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From harald.gutmann at gmx.net Fri Mar 6 20:59:03 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Fri, 6 Mar 2009 20:59:03 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <5C9E8024680E4034B04EFE3E6A3D62BE@chimp> References: <200903062034.17928.harald.gutmann@gmx.net> <200903062049.31020.harald.gutmann@gmx.net> <5C9E8024680E4034B04EFE3E6A3D62BE@chimp> Message-ID: <200903062059.03569.harald.gutmann@gmx.net> On Friday 06 March 2009 20:50:03 Myles Watson wrote: > > -----Original Message----- > > From: coreboot-bounces at coreboot.org > > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Harald Gutmann > > Sent: Friday, March 06, 2009 12:50 PM > > To: coreboot at coreboot.org > > Subject: Re: [coreboot] [patch] ACPI support on M57SLI > > > > Hello once again, > > > > as i love it that much to talk with myself, i was wondering while > > working/creating ACPI stuff, why HPTE support is turned off in > > mcp55_lpc.c with > > using #if 0. > > > > Has maybe someone of you an idea why that was done? (HPTE is also in > > context > > with ACPI) > > I don't know why HPET is disabled in mcp55. It was also disabled in > ck804_lpc.c. It worked fine when I enabled it. Until now i didn't try to activate HPTE in mcp55 because HPTE was not necessary to get ACPI running, but i was wondering why it's disabled. Thanks for sharing your experience on ck804, i'll just try to enable it. > Thanks, > Myles Kind regards, Harald -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From peter at stuge.se Fri Mar 6 20:56:16 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 20:56:16 +0100 Subject: [coreboot] GA-P31-ES3G motherboard support In-Reply-To: <49ABFC6B.9020407@r000n.net> References: <49ABFC6B.9020407@r000n.net> Message-ID: <20090306195616.16075.qmail@stuge.se> Hi Roman, Roman Mindalev wrote: > Gigabyte GA-P31-ES3G motherboard (P31 northbridge, ICH7 southbridge) > Any chance for this hardware to be supported by coreboot? Short answer: No. The southbridge is supported, but the northbridge would need a lot of work, and access to orange cover (2nd level NDA) documentation from Intel. I don't believe anyone is planning on implementing this support. Sorry. :\ //Peter From harald.gutmann at gmx.net Fri Mar 6 21:02:37 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Fri, 6 Mar 2009 21:02:37 +0100 Subject: [coreboot] ACPI/APIC related questions in coreboot. In-Reply-To: <2831fecf0903051238x1c67ae75vac895dacb49e1f4c@mail.gmail.com> References: <200903052014.42570.harald.gutmann@gmx.net> <2831fecf0903051238x1c67ae75vac895dacb49e1f4c@mail.gmail.com> Message-ID: <200903062102.37840.harald.gutmann@gmx.net> Myles, as you could read in another topic on the ml, i was able to get the "basic" ACPI functions working on my mainboard with coreboot. Your links were really helpful to get that done, and also the coreboot wiki page on acpi support (http://www.coreboot.org/ACPI_in_coreboot). I didn't respond until now to your mail because i directly started to get it working and compare with your code Thanks for your help, regards Harald On Thursday 05 March 2009 21:38:24 Myles Watson wrote: > On Thu, Mar 5, 2009 at 12:14 PM, Harald Gutmann wrote: > > Hello, > > > > at the moment i try to get acpi support running with the gigabyte m57sli > > mainboard. > > a few things are allready done (fill fadt, dsdt.asl and a pretty "raw" > > acpi_tables.c). > > > > Now my problem is, that i can't figure out the right values to set up the > > madt and mcfg acpi tables. > > This might help: > http://www.coreboot.org/pipermail/coreboot/2009-February/044809.html > > You actually don't need MCFG to boot Linux. > > You could take a look at the patches I sent for the Tyan s2895, s2891, & > s2892. http://www.coreboot.org/pipermail/coreboot/2009-February/045201.html > > I generated the dsdt from mptables.c, so it might be easier to see how > to do that. I'm not booting Windows yet, but Linux is working > flawlessly so far. > > Thanks, > Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From rminnich at gmail.com Fri Mar 6 21:05:24 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 12:05:24 -0800 Subject: [coreboot] proposed cpu startup change Message-ID: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> This is a proposal for cpu startup on v3. It is motivated by the needs of SMP. The idea is that we introduce cpu phases to parallel the device phases. Because, on modern CPUs, we can dynamically probe pretty much everything, we don't use the device tree for CPUs; that was always a point of confusion on v2 anyway. Rather, in this example, we define cpu_phase1 and cpu_phase 6 (for example) and define weak symbols for them. These functions can be over-ridden by platform or cpu functions. Here's the patch. Comments welcome. ron Index: lib/stage2.c =================================================================== --- lib/stage2.c (revision 1143) +++ lib/stage2.c (working copy) @@ -28,6 +28,18 @@ #include #include +void __attribute__((weak)) unsigned int cpu_phase1(unsigned int coldboot, + struct sys_info *sysinfo) +{ + printk(BIOS_SPEW, "cpu_phase1: nothing to do\n"); +} + +void __attribute__((weak)) unsigned int cpu_phase6(unsigned int coldboot, + struct sys_info *sysinfo) +{ + printk(BIOS_SPEW, "cpu_phase6: nothing to do\n"); +} + /** * Main function of the DRAM part of coreboot. * @@ -44,8 +56,10 @@ void *stage2(void) { void *mbi; + struct sys_info *sysinfo = &(global_vars()->sys_info); post_code(POST_STAGE2_BEGIN); + cpu_phase1(is_coldboot(), sysinfo); dev_init(); /* Phase 1 was console init and making printk work. Both functions are @@ -85,6 +99,11 @@ dev_phase6(); show_all_devs(BIOS_DEBUG, "After phase 6."); + /* final cleanup: do any remaining CPU setup. This can include memory + * init, or not, depending on the CPU; it may have been done in phase 1. + */ + cpu_phase6(is_coldboot(), sysinfo); + /* Write tables to pass information to the payloads. */ post_code(POST_STAGE2_WRITE_TABLES); mbi = write_tables(); From peter at stuge.se Fri Mar 6 21:08:06 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 21:08:06 +0100 Subject: [coreboot] coreboot on MSI K9AGM3-F In-Reply-To: <1236097137.6243.44.camel@wouter-laptop> References: <1236097137.6243.44.camel@wouter-laptop> Message-ID: <20090306200806.19505.qmail@stuge.se> Wouter de Groot wrote: > SPI access[1][2] .. > I'd be very pleased if someone could help me build a programmer for > it. I can't make schematics, but I can solder. > > At the end of the day, my board needs to be usable. Suggest that you buy/make a USB->SPI bridge. FTDI modules can do this. They can then be programmed from Linux or Windows. See thread at http://www.coreboot.org/pipermail/coreboot/2008-December/043511.html When someone has/makes their own programmer we will support it in flashrom through a simple plugin scheme yet TBD. But it will be fleshed out quickly because it is very simple. //Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: From rminnich at gmail.com Fri Mar 6 21:09:42 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 12:09:42 -0800 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <20090306194533.12943.qmail@stuge.se> References: <200903062034.17928.harald.gutmann@gmx.net> <20090306194533.12943.qmail@stuge.se> Message-ID: <13426df10903061209v1494daf5rc516340e66a01a48@mail.gmail.com> On Fri, Mar 6, 2009 at 11:45 AM, Peter Stuge wrote: > > I don't know if we want to take in the factory DSDT though.. I did not read the patch. Factory DSDT is in it? ron From c-d.hailfinger.devel.2006 at gmx.net Fri Mar 6 21:19:18 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Mar 2009 21:19:18 +0100 Subject: [coreboot] coreboot on MSI K9AGM3-F In-Reply-To: <20090306200806.19505.qmail@stuge.se> References: <1236097137.6243.44.camel@wouter-laptop> <20090306200806.19505.qmail@stuge.se> Message-ID: <49B18546.3040900@gmx.net> On 06.03.2009 21:08, Peter Stuge wrote: > Wouter de Groot wrote: > >> SPI access[1][2] >> > .. > >> I'd be very pleased if someone could help me build a programmer for >> it. I can't make schematics, but I can solder. >> >> At the end of the day, my board needs to be usable. >> > > Suggest that you buy/make a USB->SPI bridge. FTDI modules can do > this. They can then be programmed from Linux or Windows. > > See thread at > http://www.coreboot.org/pipermail/coreboot/2008-December/043511.html > > When someone has/makes their own programmer we will support it in > flashrom through a simple plugin scheme yet TBD. But it will be > fleshed out quickly because it is very simple. > Actually, the first half of plugin support in flashrom has already been merged. SPI is already completely plugin-ready. A plugin for an external flasher simply registers as SPI chipset driver. No further changes needed. LPC/FWH/Parallel is mostly done. The mmap operations need to be abstracted out, the driver for the external flasher has to register its own version of chip_readb/chip_writeb and you're done except for cosmetic changes. Regards, Carl-Daniel -- http://www.hailfinger.org/ From harald.gutmann at gmx.net Fri Mar 6 21:24:31 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Fri, 6 Mar 2009 21:24:31 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <13426df10903061209v1494daf5rc516340e66a01a48@mail.gmail.com> References: <200903062034.17928.harald.gutmann@gmx.net> <20090306194533.12943.qmail@stuge.se> <13426df10903061209v1494daf5rc516340e66a01a48@mail.gmail.com> Message-ID: <200903062124.31244.harald.gutmann@gmx.net> On Friday 06 March 2009 21:09:42 ron minnich wrote: > On Fri, Mar 6, 2009 at 11:45 AM, Peter Stuge wrote: > > I don't know if we want to take in the factory DSDT though.. > > I did not read the patch. Factory DSDT is in it? yes, it's in it. created with acpidump and acpixtract. the file, which factory bios gives with that tools was directly used in the patch. like said before, i don't know if this is a licensing problem or not. and also like stated before, this patch is not suggested for commiting. It works, and it shouldn't be much work to get the rest of the missing acpi features done. (until now, i didn't really care about dsdt.dsl, but i tried to get acpi_tables.c and fadt.c working.) > ron regards Harald -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From echelon at free.fr Fri Mar 6 21:28:23 2009 From: echelon at free.fr (Florentin Demetrescu) Date: Fri, 06 Mar 2009 21:28:23 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <200903062124.31244.harald.gutmann@gmx.net> References: <200903062034.17928.harald.gutmann@gmx.net> <20090306194533.12943.qmail@stuge.se> <13426df10903061209v1494daf5rc516340e66a01a48@mail.gmail.com> <200903062124.31244.harald.gutmann@gmx.net> Message-ID: <1236371303.49b1876784899@webmail.free.fr> Hi Harold, Great work! I will try to test your patch on my board this WE. I will keep you informed about the results Florentin Quoting Harald Gutmann : > On Friday 06 March 2009 21:09:42 ron minnich wrote: > > On Fri, Mar 6, 2009 at 11:45 AM, Peter Stuge wrote: > > > I don't know if we want to take in the factory DSDT though.. > > > > I did not read the patch. Factory DSDT is in it? > yes, it's in it. created with acpidump and acpixtract. > the file, which factory bios gives with that tools was directly used in the > patch. > like said before, i don't know if this is a licensing problem or not. and > also > like stated before, this patch is not suggested for commiting. > It works, and it shouldn't be much work to get the rest of the missing acpi > features done. (until now, i didn't really care about dsdt.dsl, but i tried > to > get acpi_tables.c and fadt.c working.) > > > ron > regards Harald > > From peter at stuge.se Fri Mar 6 21:31:15 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 21:31:15 +0100 Subject: [coreboot] [PATCH] YABEL: fix 32 bit IO accesses In-Reply-To: <49AEFFBF.4000703@gmx.net> References: <49AEFFBF.4000703@gmx.net> Message-ID: <20090306203115.26275.qmail@stuge.se> Carl-Daniel Hailfinger wrote: > > i just found that 32 bit PCI Accesses thru ports 0xCF8/0xCFC will not > > work in YABEL. This fixes it: > > > > Signed-off-by: Pattrick Hueper > > Acked-by: Carl-Daniel Hailfinger This is r1144. Please remember to note the commit rev in the patch thread, it is very helpful since we are managing all patches on the mailing list. Or you can use trac of course. :) //Peter From joe at julianfamily.org Fri Mar 6 21:39:55 2009 From: joe at julianfamily.org (Joe Julian) Date: Fri, 06 Mar 2009 12:39:55 -0800 Subject: [coreboot] Need HAVE_HIGH_TABLES for the Tyan S2916_fam10 Message-ID: <49B18A1B.6060602@julianfamily.org> I need to implement the HAVE_HIGH_TABLES patch. I've implemented the following changes, but I can't decipher how to implement the change to northbridge/amd/amdfam10/northbridge.c and I don't have a mainboard acpi_tables.c --- mainboard.c (revision 3981) +++ mainboard.c (working copy) @@ -24,6 +24,7 @@ #include #include #include +#include #include "chip.h" #if CONFIG_CHIP_NAME == 1 @@ -31,3 +32,15 @@ CHIP_NAME("Tyan S2912 Mainboard (Family 10)") }; #endif +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif +return 0; +} --- Options.lb (revision 3981) +++ Options.lb (working copy) @@ -22,6 +22,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES uses ACPI_SSDTX_NUM uses USE_FALLBACK_IMAGE uses USE_FAILOVER_IMAGE @@ -166,6 +168,8 @@ ## ACPI tables will be included default HAVE_ACPI_TABLES=0 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=1 ## extra SSDT num default ACPI_SSDTX_NUM=31 From peter at stuge.se Fri Mar 6 21:41:42 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 21:41:42 +0100 Subject: [coreboot] proposed cpu startup change In-Reply-To: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> References: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> Message-ID: <20090306204142.29459.qmail@stuge.se> ron minnich wrote: > cpu_phase1 and cpu_phase 6 (for example) Please call it cpu_phase2 instead. Then: Acked-by: Peter Stuge From peter at stuge.se Fri Mar 6 21:44:12 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 21:44:12 +0100 Subject: [coreboot] coreboot on MSI K9AGM3-F In-Reply-To: <49B18546.3040900@gmx.net> References: <1236097137.6243.44.camel@wouter-laptop> <20090306200806.19505.qmail@stuge.se> <49B18546.3040900@gmx.net> Message-ID: <20090306204412.30254.qmail@stuge.se> Carl-Daniel Hailfinger wrote: > .. While some changes were made in the plugin direction, there is still work to do. As I wrote, it will be finished quickly when there is motivation, but there is still work to be done. //Peter From peter at stuge.se Fri Mar 6 21:46:08 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 21:46:08 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <200903062124.31244.harald.gutmann@gmx.net> References: <200903062034.17928.harald.gutmann@gmx.net> <20090306194533.12943.qmail@stuge.se> <13426df10903061209v1494daf5rc516340e66a01a48@mail.gmail.com> <200903062124.31244.harald.gutmann@gmx.net> Message-ID: <20090306204608.30957.qmail@stuge.se> Harald Gutmann wrote: > > > I don't know if we want to take in the factory DSDT though.. > > > > I did not read the patch. Factory DSDT is in it? > > yes, it's in it. created with acpidump and acpixtract. > the file, which factory bios gives with that tools was directly > used in the patch. > like said before, i don't know if this is a licensing problem or > not. We want to avoid the issue by not including factory parts without express permission, though. > and also like stated before, this patch is not suggested for > commiting. Yup. I'm looking forward to more test results in any case! :) //Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: From phueper at hueper.net Fri Mar 6 21:51:07 2009 From: phueper at hueper.net (Pattrick Hueper) Date: Fri, 6 Mar 2009 21:51:07 +0100 Subject: [coreboot] [PATCH] YABEL: fix 32 bit IO accesses In-Reply-To: <20090306203115.26275.qmail@stuge.se> References: <49AEFFBF.4000703@gmx.net> <20090306203115.26275.qmail@stuge.se> Message-ID: uups... sorry, i did reply to Carl-Daniels Ack with the revision.... but only to Carl-Daniel, sorry! Pattrick On Fri, Mar 6, 2009 at 9:31 PM, Peter Stuge wrote: > Carl-Daniel Hailfinger wrote: >> > i just found that 32 bit PCI Accesses thru ports 0xCF8/0xCFC will not >> > work in YABEL. This fixes it: >> > >> > Signed-off-by: Pattrick Hueper >> >> Acked-by: Carl-Daniel Hailfinger > > This is r1144. Please remember to note the commit rev in the patch > thread, it is very helpful since we are managing all patches on the > mailing list. > > Or you can use trac of course. :) > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From peter at stuge.se Fri Mar 6 22:01:09 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 22:01:09 +0100 Subject: [coreboot] [PATCH] YABEL: fix 32 bit IO accesses In-Reply-To: References: <49AEFFBF.4000703@gmx.net> <20090306203115.26275.qmail@stuge.se> Message-ID: <20090306210109.3853.qmail@stuge.se> Pattrick Hueper wrote: > uups... sorry, i did reply to Carl-Daniels Ack with the revision.... > but only to Carl-Daniel, sorry! Too bad Gmail doesn't have list-reply. Try nagging them about it maybe. //Peter From peter at stuge.se Fri Mar 6 22:15:03 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 22:15:03 +0100 Subject: [coreboot] [patch][msrtool] Add K8 MSRs In-Reply-To: <49B05B95.2070303@coresystems.de> References: <534e5dc20903051257l7fc4a133j1fe7ebe78cfb0858@mail.gmail.com> <49B042AC.6030909@gmx.net> <534e5dc20903051457u54e5caf4m38565d4c244191fe@mail.gmail.com> <49B05B95.2070303@coresystems.de> Message-ID: <20090306211503.7716.qmail@stuge.se> Stefan Reinauer wrote: > >>> -const uint32_t msraddrbyname(const char *name) { > > > > That was to get it to compile with -Werror which is on by > > default. It didn't look like that really needed to be a const. > > Does the const make sense at all? It seems odd to define the > variable integer return value of a function const. What's that > supposed to be good for? The value returned in the function is const. Is it OK to still have the function return non-const? msrtool.h: struct msrdef { const uint32_t addr; msrutils.c: if (addr == m->addr) return m->addr; if (!strcasecmp(name, m->symbol)) return m->addr; If I just made a too conservative assumption about types, I am all for! Acked-by: Peter Stuge -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: not available URL: From rminnich at gmail.com Fri Mar 6 22:25:47 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 13:25:47 -0800 Subject: [coreboot] proposed cpu startup change In-Reply-To: <20090306204142.29459.qmail@stuge.se> References: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> <20090306204142.29459.qmail@stuge.se> Message-ID: <13426df10903061325i430b33adqda1cb7eaa7569ed5@mail.gmail.com> On Fri, Mar 6, 2009 at 12:41 PM, Peter Stuge wrote: > ron minnich wrote: >> cpu_phase1 and cpu_phase 6 (for example) > > Please call it cpu_phase2 instead. Then: are you sure? this is cpu code in stage2, phase1. Why phase2? ron From peter at stuge.se Fri Mar 6 22:40:28 2009 From: peter at stuge.se (Peter Stuge) Date: Fri, 6 Mar 2009 22:40:28 +0100 Subject: [coreboot] proposed cpu startup change In-Reply-To: <13426df10903061325i430b33adqda1cb7eaa7569ed5@mail.gmail.com> References: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> <20090306204142.29459.qmail@stuge.se> <13426df10903061325i430b33adqda1cb7eaa7569ed5@mail.gmail.com> Message-ID: <20090306214028.14410.qmail@stuge.se> ron minnich wrote: > On Fri, Mar 6, 2009 at 12:41 PM, Peter Stuge wrote: > > ron minnich wrote: > >> cpu_phase1 and cpu_phase 6 (for example) > > > > Please call it cpu_phase2 instead. Then: > > are you sure? this is cpu code in stage2, phase1. Why phase2? cpu_phase1 and cpu_phase2 was my idea. If they are indeed running completely independent of other stage2_phases. Maybe I misunderstood? //Peter From ward at gnu.org Fri Mar 6 22:42:54 2009 From: ward at gnu.org (Ward Vandewege) Date: Fri, 6 Mar 2009 16:42:54 -0500 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <200903062034.17928.harald.gutmann@gmx.net> References: <200903062034.17928.harald.gutmann@gmx.net> Message-ID: <20090306214254.GA12496@localdomain> Hi Harald, Awesome! Great work. I tested on an m57sli v1. Boot log: http://ward.vandewege.net/coreboot/m57sli/m57sli-hargut-acpi.log ACPI is detected, etc, but soft power off does not work - the machine almost powers off, but then immediately resets. Thanks, Ward. -- Ward Vandewege Free Software Foundation - Senior Systems Administrator From rminnich at gmail.com Fri Mar 6 22:55:09 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 13:55:09 -0800 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <200903062124.31244.harald.gutmann@gmx.net> References: <200903062034.17928.harald.gutmann@gmx.net> <20090306194533.12943.qmail@stuge.se> <13426df10903061209v1494daf5rc516340e66a01a48@mail.gmail.com> <200903062124.31244.harald.gutmann@gmx.net> Message-ID: <13426df10903061355n4a2670e9ocd5098f3f4b31b25@mail.gmail.com> On Fri, Mar 6, 2009 at 12:24 PM, Harald Gutmann wrote: > like said before, i don't know if this is a licensing problem or not. and also > like stated before, this patch is not suggested for commiting. Understand. Yes, we certainly don't want to put a copy of factory ACPI in our SVN UNLESS: someone wants to contact the manufacturer and gets permission. If they do get permission, I suggest that a copy of the email granting permission be dropped in the mainboard directory. I have had experience with the following: 1. Vendor: please do this port. 2. We do the port. (years pass) (people move around) 3. Vendor: WHY IS OUR MAINBOARD IN YOUR SOURCE TREE? PLEASE REMOVE! (we didn't :-) So you have to be careful once you get the ok ... either get ACPI with a GPL-from-vendor note in it or leave a nice audit trail, preferably with a copy of the email in comments. AMD, as always, is one example of how to get this done correctly. ron From rminnich at gmail.com Fri Mar 6 22:56:19 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 13:56:19 -0800 Subject: [coreboot] proposed cpu startup change In-Reply-To: <20090306204142.29459.qmail@stuge.se> References: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> <20090306204142.29459.qmail@stuge.se> Message-ID: <13426df10903061356r35780bc0i104d2ef230c1b4c6@mail.gmail.com> On Fri, Mar 6, 2009 at 12:41 PM, Peter Stuge wrote: > ron minnich wrote: >> cpu_phase1 and cpu_phase 6 (for example) > > Please call it cpu_phase2 instead. Then: now I see. You want cpu_phase6 to be called cpu_phase2? Here is why I did not. I want to leave open the possibility that hardware creates a need for other phases. However, I'm not picky on this. ron From harald.gutmann at gmx.net Fri Mar 6 23:00:54 2009 From: harald.gutmann at gmx.net (Harald Gutmann) Date: Fri, 6 Mar 2009 23:00:54 +0100 Subject: [coreboot] [patch] ACPI support on M57SLI In-Reply-To: <20090306214254.GA12496@localdomain> References: <200903062034.17928.harald.gutmann@gmx.net> <20090306214254.GA12496@localdomain> Message-ID: <200903062301.24124.harald.gutmann@gmx.net> On Friday 06 March 2009 22:42:54 Ward Vandewege wrote: > Hi Harald, Hello Ward, please try to post the following outputs/files: acpidump from original bios. acpidump from coreboot with my patches. As mentioned some posts before all values of my patch are hardcoded, therefore it can easily be it won't work on v1. With the informations of the acpidump files of original and coreboot for v1, it might be easier for me to create the code so that it's not hard-coded any more. On irc you mentioned that you have both versions of m57sli, please be so kindly and test this patch on v2 too. (and if possible send acpidump from proprietary bios and coreboot too.) > Awesome! Great work. > > I tested on an m57sli v1. > > Boot log: > > http://ward.vandewege.net/coreboot/m57sli/m57sli-hargut-acpi.log thanks for the boot-log, but the problem for me to verify that boot-log is, that i can't check out my own boot-log atm, because if've no hardware to do that. > ACPI is detected, etc, but soft power off does not work - the machine > almost powers off, but then immediately resets. Immediately resets, strange but it could maybe fixed easily with knowing the differences between your original bios acpi-tables and coreboot-acpi tables on hardware rev.1. > Thanks, > Ward. Regards, Harald -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 197 bytes Desc: This is a digitally signed message part. URL: From svn at coreboot.org Fri Mar 6 23:26:01 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Fri, 6 Mar 2009 23:26:01 +0100 Subject: [coreboot] r3984 - trunk/util/flashrom Message-ID: Author: hailfinger Date: 2009-03-06 23:26:00 +0100 (Fri, 06 Mar 2009) New Revision: 3984 Modified: trunk/util/flashrom/82802ab.c trunk/util/flashrom/am29f040b.c trunk/util/flashrom/en29f002a.c trunk/util/flashrom/flash.h trunk/util/flashrom/jedec.c trunk/util/flashrom/m29f002.c trunk/util/flashrom/m29f400bt.c trunk/util/flashrom/mx29f002.c trunk/util/flashrom/pm49fl00x.c trunk/util/flashrom/sharplhf00l04.c trunk/util/flashrom/sst28sf040.c trunk/util/flashrom/sst49lfxxxc.c trunk/util/flashrom/sst_fwhub.c trunk/util/flashrom/stm50flw0x0x.c trunk/util/flashrom/w29ee011.c trunk/util/flashrom/w39v040c.c trunk/util/flashrom/w39v080fa.c Log: FreeBSD definitions of (read|write)[bwl] collide with our own. Before we attempt trickery, we can simply rename the accessor functions. Patch created with the help of Coccinelle. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Idwer Vollering Acked-by: Patrick Georgi Modified: trunk/util/flashrom/82802ab.c =================================================================== --- trunk/util/flashrom/82802ab.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/82802ab.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -115,23 +115,23 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("BLOCK ERASE failed at 0x%x\n", offset); return -1; } @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_82802ab(bios); } } Modified: trunk/util/flashrom/am29f040b.c =================================================================== --- trunk/util/flashrom/am29f040b.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/am29f040b.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x30, bios + address); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xA0, bios + 0x555); - writeb(*src++, dst++); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xA0, bios + 0x555); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Modified: trunk/util/flashrom/en29f002a.c =================================================================== --- trunk/util/flashrom/en29f002a.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/en29f002a.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/flash.h 2009-03-06 22:26:00 UTC (rev 3984) @@ -58,32 +58,32 @@ #define INL inl #endif -static inline void writeb(uint8_t b, volatile void *addr) +static inline void chip_writeb(uint8_t b, volatile void *addr) { *(volatile uint8_t *) addr = b; } -static inline void writew(uint16_t b, volatile void *addr) +static inline void chip_writew(uint16_t b, volatile void *addr) { *(volatile uint16_t *) addr = b; } -static inline void writel(uint32_t b, volatile void *addr) +static inline void chip_writel(uint32_t b, volatile void *addr) { *(volatile uint32_t *) addr = b; } -static inline uint8_t readb(const volatile void *addr) +static inline uint8_t chip_readb(const volatile void *addr) { return *(volatile uint8_t *) addr; } -static inline uint16_t readw(const volatile void *addr) +static inline uint16_t chip_readw(const volatile void *addr) { return *(volatile uint16_t *) addr; } -static inline uint32_t readl(const volatile void *addr) +static inline uint32_t chip_readl(const volatile void *addr) { return *(volatile uint32_t *) addr; } Modified: trunk/util/flashrom/jedec.c =================================================================== --- trunk/util/flashrom/jedec.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/jedec.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -40,10 +40,10 @@ unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = readb(dst) & 0x40; + tmp1 = chip_readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { - tmp2 = readb(dst) & 0x40; + tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -59,7 +59,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = readb(dst) & 0x80; + tmp = chip_readb(dst) & 0x80; if (tmp == data) { break; } @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x20, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x30, bios + page); + chip_writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x50, bios + block); + chip_writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x10, bios + 0x5555); + chip_writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - writeb(*src, dst); + chip_writeb(*src, dst); dst++; src++; } @@ -238,7 +238,7 @@ src = s; ok = 1; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { ok = 0; break; } @@ -269,15 +269,15 @@ retry: /* Issue JEDEC Byte Program command */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); toggle_ready_jedec(bios); - if (readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { + if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } Modified: trunk/util/flashrom/m29f002.c =================================================================== --- trunk/util/flashrom/m29f002.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/m29f002.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x10, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x30, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0xa0, bios + 0x555); - writeb(*src, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0xa0, bios + 0x555); + chip_writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Modified: trunk/util/flashrom/m29f400bt.c =================================================================== --- trunk/util/flashrom/m29f400bt.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/m29f400bt.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,18 +35,18 @@ int i; for (i = 0; i < page_size; i++) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); printf ("Value in the flash at address %p = %#x, want %#x\n", - (uint8_t *) (dst - bios), readb(dst), *src); + (uint8_t *) (dst - bios), chip_readb(dst), *src); dst++; src++; } @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x90, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = readb(bios + 0x02); + id2 = chip_readb(bios + 0x02); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xF0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x10, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - writeb(0x30, dst); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Modified: trunk/util/flashrom/mx29f002.c =================================================================== --- trunk/util/flashrom/mx29f002.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/mx29f002.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xF0, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -65,12 +65,12 @@ #if 0 toggle_ready_jedec(bios); - writeb(0x30, bios + 0x0ffff); - writeb(0x30, bios + 0x1ffff); - writeb(0x30, bios + 0x2ffff); - writeb(0x30, bios + 0x37fff); - writeb(0x30, bios + 0x39fff); - writeb(0x30, bios + 0x3bfff); + chip_writeb(0x30, bios + 0x0ffff); + chip_writeb(0x30, bios + 0x1ffff); + chip_writeb(0x30, bios + 0x2ffff); + chip_writeb(0x30, bios + 0x37fff); + chip_writeb(0x30, bios + 0x39fff); + chip_writeb(0x30, bios + 0x3bfff); #endif return 0; @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Modified: trunk/util/flashrom/pm49fl00x.c =================================================================== --- trunk/util/flashrom/pm49fl00x.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/pm49fl00x.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - writeb(bits, bios + (i * block_size) + 2); + chip_writeb(bits, bios + (i * block_size) + 2); } } Modified: trunk/util/flashrom/sharplhf00l04.c =================================================================== --- trunk/util/flashrom/sharplhf00l04.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sharplhf00l04.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -41,23 +41,23 @@ #if 0 /* Enter ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); - printf("write protect is 0x%x\n", readb(wrprotect)); - writeb(0, wrprotect); - printf("write protect is 0x%x\n", readb(wrprotect)); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); + chip_writeb(0, wrprotect); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_lhf00l04(bios); } } @@ -163,7 +163,7 @@ volatile uint8_t *bios = flash->virtual_memory; erase_lhf00l04(flash); - if (readb(bios) != 0xff) { + if (chip_readb(bios) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Modified: trunk/util/flashrom/sst28sf040.c =================================================================== --- trunk/util/flashrom/sst28sf040.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sst28sf040.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -34,33 +34,33 @@ { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x040A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x041A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - writeb(AUTO_PG_ERASE1, bios); - writeb(AUTO_PG_ERASE2, bios + address); + chip_writeb(AUTO_PG_ERASE1, bios); + chip_writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -83,8 +83,8 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, dst); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, dst); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -98,16 +98,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); - writeb(READ_ID, bios); + chip_writeb(READ_ID, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); myusec_delay(10); - id2 = readb(bios + 0x01); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -122,8 +122,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - writeb(CHIP_ERASE, bios); - writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Modified: trunk/util/flashrom/sst49lfxxxc.c =================================================================== --- trunk/util/flashrom/sst49lfxxxc.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sst49lfxxxc.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - writeb(bits, bios + (i * 65536) + 2); + chip_writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - writeb(SECTOR_ERASE, bios); - writeb(ERASE, bios + address); + chip_writeb(SECTOR_ERASE, bios); + chip_writeb(ERASE, bios + address); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, bios); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, bios); + chip_writeb(*src++, dst++); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); - writeb(READ_ID, bios); - id1 = readb(bios); - id2 = readb(bios + 0x01); + chip_writeb(READ_ID, bios); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } Modified: trunk/util/flashrom/sst_fwhub.c =================================================================== --- trunk/util/flashrom/sst_fwhub.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sst_fwhub.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - writeb(0, wrprotect); + chip_writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Modified: trunk/util/flashrom/stm50flw0x0x.c =================================================================== --- trunk/util/flashrom/stm50flw0x0x.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/stm50flw0x0x.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); } /* @@ -142,8 +142,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - writeb(unlock_sector, flash_addr + offset + j); - if (readb(flash_addr + offset + j) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset + j); + if (chip_readb(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -151,8 +151,8 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - writeb(unlock_sector, flash_addr + offset); - if (readb(flash_addr + offset) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset); + if (chip_readb(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -167,17 +167,17 @@ int j; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("Erase failed at 0x%x\n", offset + j); return -1; } @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_stm50flw0x0x(bios); } @@ -210,7 +210,7 @@ dst = d; src = s; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { rc = -1; break; } Modified: trunk/util/flashrom/w29ee011.c =================================================================== --- trunk/util/flashrom/w29ee011.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/w29ee011.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x60, bios + 0x5555); + chip_writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Modified: trunk/util/flashrom/w39v040c.c =================================================================== --- trunk/util/flashrom/w39v040c.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/w39v040c.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 1); - lock = readb(bios + 0xfff2); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 1); + lock = chip_readb(bios + 0xfff2); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Modified: trunk/util/flashrom/w39v080fa.c =================================================================== --- trunk/util/flashrom/w39v080fa.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/w39v080fa.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = readb(bios); - did = readb(bios + 0x01); + vid = chip_readb(bios); + did = chip_readb(bios + 0x01); /* Product Identifixation Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -58,16 +58,16 @@ uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, - readb(wrprotect)); + chip_readb(wrprotect)); - locking = readb(wrprotect); + locking = chip_readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = readb(bios + 0xffff2); + locking = chip_readb(bios + 0xffff2); /* Product Identification Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x30, bios + sector); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); From c-d.hailfinger.devel.2006 at gmx.net Fri Mar 6 23:26:23 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 06 Mar 2009 23:26:23 +0100 Subject: [coreboot] [PATCH] flashrom: Rename chip accessor functions In-Reply-To: <49B131FB.8070002@georgi-clan.de> References: <49B12E6D.6070906@gmx.net> <49B131FB.8070002@georgi-clan.de> Message-ID: <49B1A30F.10805@gmx.net> On 06.03.2009 15:23, Patrick Georgi wrote: > Am 06.03.2009 15:08, schrieb Carl-Daniel Hailfinger: > >> FreeBSD definitions of (read|write)[bwl] collide with our own. Before we >> attempt trickery, we can simply rename the accessor functions. >> >> Signed-off-by: Carl-Daniel Hailfinger >> >> > Acked-by: Patrick Georgi > Idwer acknowledged that the patch works on IRC, but has mail routing > problems right now. As the patch isn't very complicated either, here's > my ACK. > Thanks, committed in r3984. By the way, this was done with Coccinelle as well. Regards, Carl-Daniel -- http://www.hailfinger.org/ From peter at stuge.se Sat Mar 7 00:29:07 2009 From: peter at stuge.se (Peter Stuge) Date: Sat, 7 Mar 2009 00:29:07 +0100 Subject: [coreboot] proposed cpu startup change In-Reply-To: <13426df10903061356r35780bc0i104d2ef230c1b4c6@mail.gmail.com> References: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> <20090306204142.29459.qmail@stuge.se> <13426df10903061356r35780bc0i104d2ef230c1b4c6@mail.gmail.com> Message-ID: <20090306232907.11977.qmail@stuge.se> ron minnich wrote: > >> cpu_phase1 and cpu_phase 6 (for example) > > > > Please call it cpu_phase2 instead. Then: > > now I see. You want cpu_phase6 to be called cpu_phase2? Yes, exactly! :) > Here is why I did not. I want to leave open the possibility that > hardware creates a need for other phases. However, I'm not picky > on this. While it is nice to plan ahead a little I would prefer if we just changed the numbering. This needs to be done for some non-CPU stages/phases too. I think we should just do it. //Peter From joe at julianfamily.org Sat Mar 7 00:33:03 2009 From: joe at julianfamily.org (Joe Julian) Date: Fri, 06 Mar 2009 15:33:03 -0800 Subject: [coreboot] seaBIOS config options "for emulators" Message-ID: <49B1B2AF.8040501@julianfamily.org> Hello Kevin, You suggested, on the coreboot IRC channel, that I enable smbios in seabios to solve the missing mptable and RSDP problem. The reason those are turned off is because the comments for CONFIG_PIRTABLE, CONFIG_MPTABLE, COMFIG_SMBIOS, and CONFIG_ACPI all state, "for emulators". Since this is a bare metal install, wouldn't it be correct to have those options disabled since we need the real data rather than simulated data? Thanks, Joe From rminnich at gmail.com Sat Mar 7 00:54:32 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 15:54:32 -0800 Subject: [coreboot] proposed cpu startup change In-Reply-To: <20090306232907.11977.qmail@stuge.se> References: <13426df10903061205i74ac4e3br156cbd7de67c0029@mail.gmail.com> <20090306204142.29459.qmail@stuge.se> <13426df10903061356r35780bc0i104d2ef230c1b4c6@mail.gmail.com> <20090306232907.11977.qmail@stuge.se> Message-ID: <13426df10903061554n53e1d98dtf9b37e58750a25ac@mail.gmail.com> On Fri, Mar 6, 2009 at 3:29 PM, Peter Stuge wrote: > ron minnich wrote: >> >> cpu_phase1 and cpu_phase 6 (for example) >> > >> > Please call it cpu_phase2 instead. Then: >> >> now I see. You want cpu_phase6 to be called cpu_phase2? > > Yes, exactly! :) OK, I will test this change tonight and if it all works I will be posting final diffs this weekend. With any luck by "final diffs" I will mean "first working real SMP hardware in v3". We'll see. ron From mylesgw at gmail.com Sat Mar 7 00:57:10 2009 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 6 Mar 2009 16:57:10 -0700 Subject: [coreboot] ACPI/APIC related questions in coreboot. In-Reply-To: <200903062102.37840.harald.gutmann@gmx.net> References: <200903052014.42570.harald.gutmann@gmx.net> <2831fecf0903051238x1c67ae75vac895dacb49e1f4c@mail.gmail.com> <200903062102.37840.harald.gutmann@gmx.net> Message-ID: <2831fecf0903061557g65eed3e3j3487a4474125d8cf@mail.gmail.com> On Fri, Mar 6, 2009 at 1:02 PM, Harald Gutmann wrote: > Myles, as you could read in another topic on the ml, i was able to get the > "basic" ACPI functions working on my mainboard with coreboot. > > Your links were really helpful to get that done, and also the coreboot wiki > page on acpi support (http://www.coreboot.org/ACPI_in_coreboot). > > I didn't respond until now to your mail because i directly started to get it > working and compare with your code No problem. I'm glad it's working for you. I hope that soon enough people will have done it that we can start cleaning it up and making it easier for others. Thanks, Myles From kevin at koconnor.net Sat Mar 7 01:08:49 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Fri, 6 Mar 2009 19:08:49 -0500 Subject: [coreboot] seaBIOS config options "for emulators" In-Reply-To: <49B1B2AF.8040501@julianfamily.org> References: <49B1B2AF.8040501@julianfamily.org> Message-ID: <20090307000849.GB6309@morn.localdomain> On Fri, Mar 06, 2009 at 03:33:03PM -0800, Joe Julian wrote: > You suggested, on the coreboot IRC channel, that I enable smbios in > seabios to solve the missing mptable and RSDP problem. The reason those > are turned off is because the comments for CONFIG_PIRTABLE, > CONFIG_MPTABLE, COMFIG_SMBIOS, and CONFIG_ACPI all state, "for > emulators". Since this is a bare metal install, wouldn't it be correct > to have those options disabled since we need the real data rather than > simulated data? Linux, by default, wont use the acpi tables unless there is an smbios table. The current coreboot targets don't support building an smbios table. So, I programmed SeaBIOS to build a dummy smbios table when it is used with coreboot. It's safe to leave all of: #define CONFIG_PIRTABLE 1 #define CONFIG_MPTABLE 1 #define CONFIG_SMBIOS 1 #define CONFIG_ACPI 1 enabled. The SMBIOS helps convince Linux to use acpi, and the other three (mptable, pirtable, acpi) are automatically disabled when in coreboot mode. -Kevin From joe at julianfamily.org Sat Mar 7 06:46:01 2009 From: joe at julianfamily.org (Joe Julian) Date: Fri, 06 Mar 2009 21:46:01 -0800 Subject: [coreboot] seaBIOS config options "for emulators" In-Reply-To: <20090307041604.GA8232@morn.localdomain> References: <49B1B2AF.8040501@julianfamily.org> <20090307000849.GB6309@morn.localdomain> <49B1C0F9.5040202@julianfamily.org> <20090307005941.GA6916@morn.localdomain> <49B1CB57.6030105@julianfamily.org> <20090307041604.GA8232@morn.localdomain> Message-ID: <49B20A19.6090809@julianfamily.org> Kevin O'Connor wrote: > On Fri, Mar 06, 2009 at 05:18:15PM -0800, Joe Julian wrote: > >> I find this patch >> http://www.coreboot.org/pipermail/coreboot/2009-February/045068.html >> > > Yes. You need to apply that patch. (Please confirm your machine has > at least 1GiB of memory.) > > The next thing you need to do is setup your SeaBIOS src/config.h. It > should have CONFIG_COREBOOT set, CONFIG_DEBUG_SERIAL set, > CONFIG_OPTIONROMS_DEPLOYED unset, and OPTIONROM_BDF/MEM_* set. I > think you've already done this. > > Then, one compiles the above, and flashes the chip. > > If you're not seeing the correct output, something must be wrong. > You'll need to capture the serial output and send the log. With the > log, we'll be able to figure out what went wrong. > Thanks for your help. I can't directly apply that patch because it's been superseded by this one http://tracker.coreboot.org/trac/coreboot/changeset/3960 which works for me so far, with the following changes. There's a little bit of workaround there, as I don't know how to patch the HAVE_HIGH_TABLES into src/northbridge/amd/amdfam10/northbridge.c Here's a link to my log: http://www.privatepaste.com/04ilD2DoPH And yes, the machine has more than 1Gb. It has 8. --- src/arch/i386/boot/tables.c (revision 3981) +++ src/arch/i386/boot/tables.c (working copy) @@ -58,7 +58,7 @@ } #if HAVE_HIGH_TABLES == 1 -uint64_t high_tables_base = 0; +uint64_t high_tables_base = 0x3dff0000; uint64_t high_tables_size; #endif @@ -188,11 +187,12 @@ rom_table_start, rom_table_end); #endif +#if 0 /* The coreboot table must be in 0-4K or 960K-1M */ write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); -#if 0 && HAVE_HIGH_TABLES == 1 +#else // HAVE_HIGH_TABLES == 1 /* This is currently broken and should be severely refactored. Ideally * we only have a pointer to the coreboot table in the low memory, so * anyone can find the real position. @@ -205,8 +205,8 @@ * corrupted */ if (high_tables_base) { - write_coreboot_table(high_table_start, high_table_end, - high_table_start, high_table_end); + write_coreboot_table(low_table_start, low_table_end, + high_table_start, high_table_end); } #endif --- src/mainboard/tyan/s2912_fam10/mainboard.c (revision 3981) +++ src/mainboard/tyan/s2912_fam10/mainboard.c (working copy) @@ -24,6 +24,7 @@ #include #include #include +#include #include "chip.h" #if CONFIG_CHIP_NAME == 1 @@ -31,3 +32,15 @@ CHIP_NAME("Tyan S2912 Mainboard (Family 10)") }; #endif +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif +return 0; +} Index: src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- src/mainboard/tyan/s2912_fam10/Options.lb (revision 3981) +++ src/mainboard/tyan/s2912_fam10/Options.lb (working copy) @@ -22,6 +22,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES uses ACPI_SSDTX_NUM uses USE_FALLBACK_IMAGE uses USE_FAILOVER_IMAGE @@ -166,6 +168,8 @@ ## ACPI tables will be included default HAVE_ACPI_TABLES=0 +default HAVE_MAINBOARD_RESOURCES=0 +default HAVE_HIGH_TABLES=1 ## extra SSDT num default ACPI_SSDTX_NUM=31 @@ -211,8 +215,8 @@ #default HW_MEM_HOLE_SIZE_AUTO_INC=1 #VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 +default CONFIG_CONSOLE_VGA=0 +default CONFIG_PCI_ROM_RUN=0 #default CONFIG_USBDEBUG_DIRECT=1 -------------- next part -------------- An HTML attachment was scrubbed... URL: From rminnich at gmail.com Sat Mar 7 07:05:43 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 22:05:43 -0800 Subject: [coreboot] patch: working SMP startup for kontron/core2 Message-ID: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> comments welcome. Please see notes in the patch. ron -------------- next part -------------- A non-text attachment was scrubbed... Name: core2smp.diff Type: text/x-patch Size: 8458 bytes Desc: not available URL: From rminnich at gmail.com Sat Mar 7 08:40:09 2009 From: rminnich at gmail.com (ron minnich) Date: Fri, 6 Mar 2009 23:40:09 -0800 Subject: [coreboot] FILO failure Message-ID: <13426df10903062340j7be0f313ha0ed7d38eb762db8@mail.gmail.com> This is on the kontron with a USB drive. It's very consistent. We might need a slightly more informative error message than "panic". thanks ron FILO version 0.6.0rc1 (rminnich at xcpu2.sandia.gov) Fri Mar 6 23:31:02 PST 2009 00:1d.0 27c8:8086.0 UHCI controller fullspeed device maxPacketSize0: 40 device version: 2.0 device has 1 configurations device has 1 interfaces #0 has 2 endpoints, interface 8:6, protocol 50 #1: Endpoint 1 (in), max packet size 40, type bulk #2: Endpoint 2 (out), max packet size 40, type bulk device of class 8 found MSC found it uses SCSI transparent command set it uses Bulk-Only Transport protocol using endpoint 81 as in, 2 as out has 1 luns Waiting for device to become ready... .........timeout. Device not ready. Sti. spin up. OK. has 3963904 blocks sized 512b 00:1d.1 27c9:8086.1 UHCI controller warning: device 0 reassigned? 00:1d.2 27ca:8086.2 UHCI controller 00:1d.3 27cb:8086.3 UHCI controller memory allocator panic. From peter at stuge.se Sat Mar 7 11:05:33 2009 From: peter at stuge.se (Peter Stuge) Date: Sat, 7 Mar 2009 11:05:33 +0100 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> Message-ID: <20090307100533.9043.qmail@stuge.se> ron minnich wrote: > comments welcome. Please see notes in the patch. Short version: Very nice! > I am not as interested in comments on this specific code (it needs > cleanup) as I am in two questions: I'll mention a few things that I would like to be included in that cleanup. > 1. can artec please test the current svn to make sure there is > nothing I have broken Good point. Could be tested also on ALIX. > 2. Are the changes to lib/stage2.c ok I think so. > Anyway, take a look. With luck, we have SMP on the kontron within > the week; SMI follows, then ACPI, then maybe we can make v3 the > preferred kontron software base. It would be awesome! > +++ lib/stage2.c (working copy) .. > @@ -85,6 +104,11 @@ > dev_phase6(); > show_all_devs(BIOS_DEBUG, "After phase 6."); > > + /* final cleanup: do any remaining CPU setup. This can include memory > + * init, or not, depending on the CPU; it may have been done in phase 1. > + */ > + cpu_phase2(is_coldboot(), sysinfo); > + The comment mentions phase 1 - but which phase 1 is that? Would help if it said cpu_phase1() or stage2_phase1() instead. > + movw $0x11, 0 Just curious, what do these movws to 0 do? > +++ arch/x86/intel/core2/init_cpus.c (working copy) .. > @@ -73,6 +72,7 @@ > int nodes, siblings; > result = cpuid(1); > /* See how many sibling cpus we have */ > + printk(BIOS_DEBUG, "cpuid(1) %x\n", result.ebx); Please make this debug output say ebx=%08x because even if that is redundant for the people looking at it right now, output like this can linger and anyone else may be confused. > @@ -377,18 +384,25 @@ > stackmem->stacks[index].post = 0; > stackmem->stacks[index].active_cpus = active_cpus; > stackmem->stacks[index].start_cpu_lock = start_cpu_lock; > + printk(BIOS_SPEW, "stack[index, apicid, post, active_cpus, start_cpu_lock = [%lx, %x, %d, %p, %p]\n", index, apicid, 0, active_cpus, start_cpu_lock); I guess this is missing ] after start_cpu_lock. Overall great improvements! //Peter From peter at stuge.se Sat Mar 7 12:27:09 2009 From: peter at stuge.se (Peter Stuge) Date: Sat, 7 Mar 2009 12:27:09 +0100 Subject: [coreboot] 965/ICH8 ? Message-ID: <20090307112709.451.qmail@stuge.se> How different are they from 945/ICH7? Target: http://www.commell.com.tw/Product/SBC/LV-679.HTM Am thinking to try the Kontron port to see what happens. Hobby project though. //Peter From joe at settoplinux.org Sat Mar 7 16:04:59 2009 From: joe at settoplinux.org (Joseph Smith) Date: Sat, 07 Mar 2009 10:04:59 -0500 Subject: [coreboot] =?utf-8?q?965/ICH8_=3F?= In-Reply-To: <20090307112709.451.qmail@stuge.se> References: <20090307112709.451.qmail@stuge.se> Message-ID: <9c2b8af188823510bae7c4124bbb55a9@imap.1and1.com> On Sat, 7 Mar 2009 12:27:09 +0100, Peter Stuge wrote: > How different are they from 945/ICH7? > > Target: http://www.commell.com.tw/Product/SBC/LV-679.HTM > > Am thinking to try the Kontron port to see what happens. Hobby > project though. > > Go for it :-) Would the 3100 be a better choice? The graphics are 3100. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From rminnich at gmail.com Sat Mar 7 16:37:25 2009 From: rminnich at gmail.com (ron minnich) Date: Sat, 7 Mar 2009 07:37:25 -0800 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <20090307100533.9043.qmail@stuge.se> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> <20090307100533.9043.qmail@stuge.se> Message-ID: <13426df10903070737h46982b9dy57b559bb0f067cca@mail.gmail.com> On Sat, Mar 7, 2009 at 2:05 AM, Peter Stuge wrote: >> + ? ? movw ? ?$0x11, 0 > > Just curious, what do these movws to 0 do? > Glad you asked! These are how I got it debugged. Since we have another CPU (BSP) I had the BSP wait and print out the values. These are POST codes for AP startup! So BSP can now monitor AP progress with variables -- no more "worked"/"did not work" but "here's how far it got". The BSP has far more knowledge than in v2 of how far things got. They movw to 0 going to be removed, I think; we can depend on secondary.S. Or should we? Should I leave them in? > Overall great improvements! Thanks for the comments, I'm hoping you found the code understandable -- I am guessing you did? Thanks for reading it! ron From kevin at koconnor.net Sat Mar 7 18:17:18 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Sat, 7 Mar 2009 12:17:18 -0500 Subject: [coreboot] seaBIOS config options "for emulators" In-Reply-To: <49B20A19.6090809@julianfamily.org> References: <49B1B2AF.8040501@julianfamily.org> <20090307000849.GB6309@morn.localdomain> <49B1C0F9.5040202@julianfamily.org> <20090307005941.GA6916@morn.localdomain> <49B1CB57.6030105@julianfamily.org> <20090307041604.GA8232@morn.localdomain> <49B20A19.6090809@julianfamily.org> Message-ID: <20090307171718.GA15652@morn.localdomain> On Fri, Mar 06, 2009 at 09:46:01PM -0800, Joe Julian wrote: > Kevin O'Connor wrote: >> If you're not seeing the correct output, something must be wrong. >> You'll need to capture the serial output and send the log. With the >> log, we'll be able to figure out what went wrong. > > Thanks for your help. I can't directly apply that patch because it's > been superseded by this one > http://tracker.coreboot.org/trac/coreboot/changeset/3960 > which works for me so far, with the following changes. There's a little > bit of workaround there, as I don't know how to patch the > HAVE_HIGH_TABLES into src/northbridge/amd/amdfam10/northbridge.c > > Here's a link to my log: > http://www.privatepaste.com/04ilD2DoPH Okay. Looks like your tables are being relocated and SeaBIOS is finding them properly. It also looks like gPXE is succesfully running. Unfortunately, your coreboot mainboard doesn't have any ACPI definitions. (So, the problem isn't SeaBIOS not finding it - instead coreboot is not providing it.) Extending coreboot to provide acpi definitions is a bit out of my expertise. Someone from the list should be able to suggest a starting point. You are getting very close though. -Kevin From lists at r000n.net Sat Mar 7 19:12:04 2009 From: lists at r000n.net (Roman Mindalev) Date: Sat, 07 Mar 2009 21:12:04 +0300 Subject: [coreboot] GA-P31-ES3G motherboard support In-Reply-To: <20090306195616.16075.qmail@stuge.se> References: <49ABFC6B.9020407@r000n.net> <20090306195616.16075.qmail@stuge.se> Message-ID: <49B2B8F4.3080700@r000n.net> Peter Stuge wrote: > Hi Roman, > > Roman Mindalev wrote: >> Gigabyte GA-P31-ES3G motherboard (P31 northbridge, ICH7 southbridge) > >> Any chance for this hardware to be supported by coreboot? > > Short answer: No. > > The southbridge is supported, but the northbridge would need a lot of > work, and access to orange cover (2nd level NDA) documentation from > Intel. Ok. Anyway, thanks for answer, Peter From svn at coreboot.org Sun Mar 8 05:37:39 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Sun, 8 Mar 2009 05:37:39 +0100 Subject: [coreboot] r3985 - trunk/util/msrtool Message-ID: Author: mjones Date: 2009-03-08 05:37:39 +0100 (Sun, 08 Mar 2009) New Revision: 3985 Added: trunk/util/msrtool/k8.c Modified: trunk/util/msrtool/Makefile.in trunk/util/msrtool/configure trunk/util/msrtool/msrtool.c trunk/util/msrtool/msrtool.h trunk/util/msrtool/msrutils.c Log: Add some basic K8 MSRs. Fix bash script type. Removed const return type on msraddrbyname() to fix gcc warning/error. Signed-off-by: Marc Jones Acked-by: Carl-Daniel Hailfinger Acked-by: Peter Stuge Modified: trunk/util/msrtool/Makefile.in =================================================================== --- trunk/util/msrtool/Makefile.in 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/Makefile.in 2009-03-08 04:37:39 UTC (rev 3985) @@ -26,7 +26,7 @@ CFLAGS = @CFLAGS@ LDFLAGS = @LDFLAGS@ -TARGETS = geodelx.o cs5536.o +TARGETS = geodelx.o cs5536.o k8.o SYSTEMS = linux.o OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS) Modified: trunk/util/msrtool/configure =================================================================== --- trunk/util/msrtool/configure 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/configure 2009-03-08 04:37:39 UTC (rev 3985) @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # # This file is part of msrtool. # Added: trunk/util/msrtool/k8.c =================================================================== --- trunk/util/msrtool/k8.c (rev 0) +++ trunk/util/msrtool/k8.c 2009-03-08 04:37:39 UTC (rev 3985) @@ -0,0 +1,366 @@ +/* + * This file is part of msrtool. + * + * Copyright (c) 2009 Marc Jones + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int k8_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return 0xF == id->family; +} + +/* + * AMD BKDG Publication # 32559 Revision: 3.08 Issue Date: July 2007 + */ +const struct msrdef k8_msrs[] = { + { 0xC0000080, MSRTYPE_RDWR, MSR2(0, 0), "EFER Register", "Extended Feature Enable Register", { + { 63, 32, RESERVED }, + { 31, 18, RESERVED }, + { 14, 1, "FFXSR:", "Fast FXSAVE/FRSTOR Enable", PRESENT_DEC, { + { MSR1(0), "FXSAVE/FRSTOR disabled" }, + { MSR1(1), "FXSAVE/FRSTOR enabled" }, + { BITVAL_EOT } + }}, + { 13, 1, "LMSLE:", "Long Mode Segment Limit Enable", PRESENT_DEC, { + { MSR1(0), "Long mode segment limit check disabled" }, + { MSR1(1), "Long mode segment limit check enalbed" }, + { BITVAL_EOT } + }}, + { 12, 1, "SVME:", "SVM Enable", PRESENT_DEC, { + { MSR1(0), "SVM features disabled" }, + { MSR1(1), "SVM features enabled" }, + { BITVAL_EOT } + }}, + { 11, 1, "NXE:", "No-Execute Page Enable", PRESENT_DEC, { + { MSR1(0), "NXE features disabled" }, + { MSR1(1), "NXE features enabled" }, + { BITVAL_EOT } + }}, + { 10, 1, "LMA:", "Long Mode Active", PRESENT_DEC, { + { MSR1(0), "Long Mode feature not active" }, + { MSR1(1), "Long Mode feature active" }, + { BITVAL_EOT } + }}, + { 9, 1, RESERVED }, + { 8, 1, "LME:", "Long Mode Enable", PRESENT_DEC, { + { MSR1(0), "Long Mode feature disabled" }, + { MSR1(1), "Long Mode feature enabled" }, + { BITVAL_EOT } + }}, + { 7, 7, RESERVED }, + { 0, 1, "SYSCALL:", "System Call Extension Enable", PRESENT_DEC, { + { MSR1(0), "System Call feature disabled" }, + { MSR1(1), "System Call feature enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010010, MSRTYPE_RDWR, MSR2(0, 0), "SYSCFG Register", "This register controls the system configuration", { + { 63, 32, RESERVED }, + { 31, 9, RESERVED }, + { 22, 1, "Tom2ForceMemTypeWB:", "Top of Memory 2 Memory Type Write Back", PRESENT_DEC, { + { MSR1(0), "Tom2ForceMemTypeWB disabled" }, + { MSR1(1), "Tom2ForceMemTypeWB enabled" }, + { BITVAL_EOT } + }}, + { 21, 1, "MtrrTom2En:", "Top of Memory Address Register 2 Enable", PRESENT_DEC, { + { MSR1(0), "MtrrTom2En disabled" }, + { MSR1(1), "MtrrTom2En enabled" }, + { BITVAL_EOT } + }}, + { 20, 1, "MtrrVarDramEn:", "Top of Memory Address Register and I/O Range Register Enable", PRESENT_DEC, { + { MSR1(0), "MtrrVarDramEn disabled" }, + { MSR1(1), "MtrrVarDramEn enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "MtrrFixDramModEn:", "RdDram and WrDram Bits Modification Enable", PRESENT_DEC, { + { MSR1(0), "MtrrFixDramModEn disabled" }, + { MSR1(1), "MtrrFixDramModEn enabled" }, + { BITVAL_EOT } + }}, + { 18, 1, "MtrrFixDramEn:", "Fixed RdDram and WrDram Attributes Enable", PRESENT_DEC, { + { MSR1(0), "MtrrFixDramEn disabled" }, + { MSR1(1), "MtrrFixDramEn enabled" }, + { BITVAL_EOT } + }}, + { 17, 1, "SysUcLockEn:", "System Interface Lock Command Enable", PRESENT_DEC, { + { MSR1(0), "SysUcLockEn disabled" }, + { MSR1(1), "SysUcLockEn enabled" }, + { BITVAL_EOT } + }}, + { 16, 1, "ChxToDirtyDis:", "Change to Dirty Command Disable", PRESENT_DEC, { + { MSR1(0), "ChxToDirtyDis disabled" }, + { MSR1(1), "ChxToDirtyDis enabled" }, + { BITVAL_EOT } + }}, + { 15, 5, RESERVED }, + { 10, 1, "SetDirtyEnO:", "SharedToDirty Command for O->M State Transition Enable", PRESENT_DEC, { + { MSR1(0), "SetDirtyEnO disabled" }, + { MSR1(1), "SetDirtyEnO enabled" }, + { BITVAL_EOT } + }}, + { 9, 1, "SetDirtyEnS:", "SharedToDirty Command for S->M State Transition Enable", PRESENT_DEC, { + { MSR1(0), "SetDirtyEnS disabled" }, + { MSR1(1), "SetDirtyEnS enabled" }, + { BITVAL_EOT } + }}, + { 8, 1, "SetDirtyEnE:", "CleanToDirty Command for E->M State Transition Enable", PRESENT_DEC, { + { MSR1(0), "SetDirtyEnE disabled" }, + { MSR1(1), "SetDirtyEnE enabled" }, + { BITVAL_EOT } + }}, + { 7, 3, "SysVicLimit:", "Outstanding Victim Bus Command Limit", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 4, 5, "SysAckLimit:", "Outstanding Bus Command Limit", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010015, MSRTYPE_RDWR, MSR2(0, 0), "HWCR Register", "This register controls the harware configuration", { + { 63, 32, RESERVED }, + { 31, 2, RESERVED }, + { 29, 6, "START_FID:", "Status of the startup FID", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 5, RESERVED }, + { 18, 1, "MCi_STATUS_WREN:", "MCi Status Write Enable", PRESENT_DEC, { + { MSR1(0), "MCi_STATUS_WREN disabled" }, + { MSR1(1), "MCi_STATUS_WREN enabled" }, + { BITVAL_EOT } + }}, + { 17, 1, "WRAP32DIS:", "32-bit Address Wrap Disable", PRESENT_DEC, { + { MSR1(0), "WRAP32DIS clear" }, + { MSR1(1), "WRAP32DIS set" }, + { BITVAL_EOT } + }}, + { 16, 1, RESERVED }, + { 15, 1, "SSEDIS:", "SSE Instructions Disable", PRESENT_DEC, { + { MSR1(0), "SSEDIS clear" }, + { MSR1(1), "SSEDIS set" }, + { BITVAL_EOT } + }}, + { 14, 1, "RSMSPCYCDIS:", "Special Bus Cycle On RSM Disable", PRESENT_DEC, { + { MSR1(0), "RSMSPCYCDIS clear" }, + { MSR1(1), "RSMSPCYCDIS set" }, + { BITVAL_EOT } + }}, + { 13, 1, "SMISPCYCDIS:", "Special Bus Cycle On SMI Disable", PRESENT_DEC, { + { MSR1(0), "SMISPCYCDIS clear" }, + { MSR1(1), "SMISPCYCDIS set" }, + { BITVAL_EOT } + }}, + { 12, 1, "HLTXSPCYCEN:", "Enable Special Bus Cycle On Exit From HLT", PRESENT_DEC, { + { MSR1(0), "HLTXSPCYCEN disabled" }, + { MSR1(1), "HLTXSPCYCEN enabled" }, + { BITVAL_EOT } + }}, + { 11, 4, RESERVED }, + { 8, 1, "IGNNE_EM:", "IGNNE Port Emulation Enable", PRESENT_DEC, { + { MSR1(0), "IGNNE_EM disabled" }, + { MSR1(1), "IGNNE_EM enabled" }, + { BITVAL_EOT } + }}, + { 7, 1, "DISLOCK:", "Disable x86 LOCK prefix functionality", PRESENT_DEC, { + { MSR1(0), "DISLOCK clear" }, + { MSR1(1), "DISLOCK set" }, + { BITVAL_EOT } + }}, + { 6, 1, "FFDIS:", "TLB Flush Filter Disable", PRESENT_DEC, { + { MSR1(0), "FFDIS clear" }, + { MSR1(1), "FFDIS set" }, + { BITVAL_EOT } + }}, + { 5, 1, RESERVED }, + { 4, 1, "INVD_WBINVD:", "INVD to WBINVD Conversion", PRESENT_DEC, { + { MSR1(0), "INVD_WBINVD disabled" }, + { MSR1(1), "INVD_WBINVD enabled" }, + { BITVAL_EOT } + }}, + { 3, 1, "TLBCACHEDIS:", "TLB Cacheable Memory Disable", PRESENT_DEC, { + { MSR1(0), "TLBCACHEDIS clear" }, + { MSR1(1), "TLBCACHEDIS set" }, + { BITVAL_EOT } + }}, + { 2, 1, RESERVED }, + { 1, 1, "SLOWFENCE:", "Slow SFENCE Enable", PRESENT_DEC, { + { MSR1(0), "SLOWFENCE disabled" }, + { MSR1(1), "SLOWFENCE enabled" }, + { BITVAL_EOT } + }}, + { 0, 1, "SMMLOCK:", "SMM Configuration Lock", PRESENT_DEC, { + { MSR1(0), "SMMLOCK disabled" }, + { MSR1(1), "SMMLOCK enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC001001F, MSRTYPE_RDWR, MSR2(0, 0), "NB_CFG Register", "", { + { 63, 9, RESERVED }, + { 54, 1, "InitApicIdCpuIdLo:", "CpuId and NodeId[2:0] bit field positions are swapped in the APICID", PRESENT_DEC, { + { MSR1(0), "CpuId and NodeId not swapped" }, + { MSR1(1), "CpuId and NodeId swapped" }, + { BITVAL_EOT } + }}, + { 53, 8, RESERVED }, + { 45, 1, "DisUsSysMgtRqToNLdt:", "Disable Upstream System Management Rebroadcast", PRESENT_DEC, { + { MSR1(0), "Upstream Rebroadcast disabled" }, + { MSR1(1), "Upstream Rebroadcast enabled" }, + { BITVAL_EOT } + }}, + { 44, 1, RESERVED }, + { 43, 1, "DisThmlPfMonSmiInt:", "Disable Performance Monitor SMI", PRESENT_DEC, { + { MSR1(0), "Performance Monitor SMI enabled" }, + { MSR1(1), "Performance Monitor SMI disabled" }, + { BITVAL_EOT } + }}, + { 42, 6, RESERVED }, + { 36, 1, "DisDatMsk:", "Disables DRAM data masking function", PRESENT_DEC, { + { MSR1(0), "DRAM data masking enabled" }, + { MSR1(1), "DRAM data masking disabled" }, + { BITVAL_EOT } + }}, + { 35, 4, RESERVED }, + { 31, 1, "DisCohLdtCfg:", "Disable Coherent HyperTransport Configuration Accesses", PRESENT_DEC, { + { MSR1(0), "Coherent HyperTransport Configuration enabled" }, + { MSR1(1), "Coherent HyperTransport Configuration disabled" }, + { BITVAL_EOT } + }}, + { 30, 21, RESERVED }, + { 9, 1, "DisRefUseFreeBuf:", "Disable Display Refresh from Using Free List Buffers", PRESENT_DEC, { + { MSR1(0), "Display refresh requests enabled" }, + { MSR1(1), "Display refresh requests disabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC001001A, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM Register", "This register indicates the first byte of I/O above DRAM", { + { 63, 24, RESERVED }, + { 39, 8, "TOM 39-32", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 9, "TOM 31-23", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 22, 23, RESERVED }, + { BITS_EOT } + }}, + + { 0xC001001D, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM2 Register", "This register indicates the Top of Memory above 4GB", { + { 63, 24, RESERVED }, + { 39, 8, "TOM2 39-32", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 9, "TOM2 31-23", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 22, 23, RESERVED }, + { BITS_EOT } + }}, + + { 0xC0010016, MSRTYPE_RDWR, MSR2(0, 0), "IORRBase0", "This register holds the base of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "BASE 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "BASE 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 6, RESERVED }, + { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC, { + { MSR1(0), "RdDram disabled" }, + { MSR1(1), "RdDram enabled" }, + { BITVAL_EOT } + }}, + { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC, { + { MSR1(0), "WrDram disabled" }, + { MSR1(1), "WrDram enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010017, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask0", "This register holds the mask of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "MASK 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "MASK 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC, { + { MSR1(0), "V I/O range disabled" }, + { MSR1(1), "V I/O range enabled" }, + { BITVAL_EOT } + }}, + { 10, 11, RESERVED }, + { BITS_EOT } + }}, + + { 0xC0010018, MSRTYPE_RDWR, MSR2(0, 0), "IORRBase1", "This register holds the base of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "BASE 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "BASE 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 6, RESERVED }, + { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC, { + { MSR1(0), "RdDram disabled" }, + { MSR1(1), "RdDram enabled" }, + { BITVAL_EOT } + }}, + { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC, { + { MSR1(0), "WrDram disabled" }, + { MSR1(1), "WrDram enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010019, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask1", "This register holds the mask of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "MASK 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "MASK 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC, { + { MSR1(0), "V I/O range disabled" }, + { MSR1(1), "V I/O range enabled" }, + { BITVAL_EOT } + }}, + { 10, 11, RESERVED }, + { BITS_EOT } + }}, + +/* + { 0, MSRTYPE_RDONLY, MSR2(0, 0), "TEMPLATE", "Template MSR", { + { 63, 64, RESERVED }, + { BITS_EOT } + }}, +*/ + + { MSR_EOT } +}; Modified: trunk/util/msrtool/msrtool.c =================================================================== --- trunk/util/msrtool/msrtool.c 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/msrtool.c 2009-03-08 04:37:39 UTC (rev 3985) @@ -42,6 +42,7 @@ static struct targetdef alltargets[] = { { "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs }, { "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs }, + { "K8", "AMD K8 Family", k8_probe, k8_msrs }, { TARGET_EOT } }; Modified: trunk/util/msrtool/msrtool.h =================================================================== --- trunk/util/msrtool/msrtool.h 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/msrtool.h 2009-03-08 04:37:39 UTC (rev 3985) @@ -157,7 +157,7 @@ struct msr msr_shr(const struct msr a, const uint8_t bits); void msr_and(struct msr *a, const struct msr b); const struct msrdef *findmsrdef(const uint32_t addr); -const uint32_t msraddrbyname(const char *name); +uint32_t msraddrbyname(const char *name); void dumpmsrdefs(const struct targetdef *t); int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu); uint8_t str2msr(char *str, struct msr *msr); @@ -185,4 +185,8 @@ extern int cs5536_probe(const struct targetdef *t); extern const struct msrdef cs5536_msrs[]; +/* k8.c */ +extern int k8_probe(const struct targetdef *t); +extern const struct msrdef k8_msrs[]; + #endif /* MSRTOOL_H */ Modified: trunk/util/msrtool/msrutils.c =================================================================== --- trunk/util/msrtool/msrutils.c 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/msrutils.c 2009-03-08 04:37:39 UTC (rev 3985) @@ -137,7 +137,7 @@ return NULL; } -const uint32_t msraddrbyname(const char *name) { +uint32_t msraddrbyname(const char *name) { uint8_t t; const uint32_t addr = strtoul(name, NULL, 16); const struct msrdef *m; From marcj303 at gmail.com Sun Mar 8 05:38:08 2009 From: marcj303 at gmail.com (Marc Jones) Date: Sat, 7 Mar 2009 21:38:08 -0700 Subject: [coreboot] [patch][msrtool] Add K8 MSRs In-Reply-To: <20090306211503.7716.qmail@stuge.se> References: <534e5dc20903051257l7fc4a133j1fe7ebe78cfb0858@mail.gmail.com> <49B042AC.6030909@gmx.net> <534e5dc20903051457u54e5caf4m38565d4c244191fe@mail.gmail.com> <49B05B95.2070303@coresystems.de> <20090306211503.7716.qmail@stuge.se> Message-ID: <534e5dc20903072038p78921563o5ae91e622881e8f7@mail.gmail.com> On Fri, Mar 6, 2009 at 2:15 PM, Peter Stuge wrote: > Stefan Reinauer wrote: >> >>> -const uint32_t msraddrbyname(const char *name) { >> > >> > That was to get it to compile with -Werror which is on by >> > default. It didn't look like that really needed to be a const. >> >> Does the const make sense at all? It seems odd to define the >> variable integer return value of a function const. What's that >> supposed to be good for? > > The value returned in the function is const. Is it OK to still have > the function return non-const? > > msrtool.h: > > struct msrdef { > ? ? ? ?const uint32_t addr; > > > msrutils.c: > > if (addr == m->addr) > ? ? ? ?return m->addr; > if (!strcasecmp(name, m->symbol)) > ? ? ? ?return m->addr; > > > If I just made a too conservative assumption about types, I am all > for! > > Acked-by: Peter Stuge Yes, That doesn't seem to bother the type checking but having the return type not match the variable causes an error (warning). r3985 Thanks, Marc From peter at stuge.se Sun Mar 8 11:54:12 2009 From: peter at stuge.se (Peter Stuge) Date: Sun, 8 Mar 2009 11:54:12 +0100 Subject: [coreboot] r3985 - trunk/util/msrtool Message-ID: <20090308105412.11987.qmail@stuge.se> Cool! svn at coreboot.org wrote: > + { 0xC0000080, MSRTYPE_RDWR, MSR2(0, 0), "EFER Register", "Extended Feature Enable Register", { Would you mind if I changed that first string to read just "EFER" ? > + { 14, 1, "FFXSR:", "Fast FXSAVE/FRSTOR Enable", PRESENT_DEC, { And if I removed the trailing : in these value names? Sorry - should have mentioned these sooner. //Peter From peter at stuge.se Sun Mar 8 22:21:37 2009 From: peter at stuge.se (Peter Stuge) Date: Sun, 8 Mar 2009 22:21:37 +0100 Subject: [coreboot] Expo report from embedded world 2009 Message-ID: <20090308212137.19404.qmail@stuge.se> Hi all! Myself, Stefan Reinauer and Rudolf Marek made a visit at embedded world 2009 in N?rnberg this week and I would like to tell you a little about what we did there. http://www.embedded-world.de/ As always it was nice to meet in person, especially Rudolf whom neither me nor Stefan had met before, although he has been quite active in the project for several years. Overall I consider the visit quite successful. Perhaps even more successful than if coreboot would have been an exhibitor, because we would not have been able to move around so much if we had a booth to attend to. A great number of interesting companies both for hardware and software were represented at the expo and some of the ones we spoke with were IEI, AXIOMTEK, MSC, Advantech, congatec, LIPPERT, Toradex, MSI, DIGITAL-LOGIC, VIA, JET-WAY, MEN, Radisys, Denx, QNX and Microsoft. I would estimate that 85% of the displayed boards used Atom. There were also Geode LX, C7/Nano and some Core2 boards, but for every one non-Atom I still saw two or three Atoms. I quickly learned one thing which was maybe not so surprising, the asian hardware companies do all BIOS development at headquarters. Axiomtek, MSI, JET-WAY and VIA did have representatives from HQ at the expo, but no engineers and no firmware experts. We still tried to establish as many contacts as possible, and everyone we met was quite helpful and promised to forward information and contacts to the appropriate people within their organizations. Some highlights: * Discussing firmware with Mr. Lippert himself * Ad-hoc coreboot demo, twice!, at the SYSGO (Rudolf's job) booth party * VIA 855 chipset - H.264 playback and die still at 45 C with no cooling! * Free beer at the Microsoft booth talking to the owner of XP Embedded * Learning that the QNX bootloader is a clean 32-bit ELF built with gcc Earlier this year Konsult Stuge and coresystems GmbH joined an industry consortium which has already established the next generation CPU module standard. The other members are mostly companies in the hardware sector so we gave a short coreboot presentation at the consortium meeting during the expo in order to shine a light on the benefits and possibilities which coreboot brings to the embedded segment. For me as an open source enthousiast and evangelist it was really a great pleasure to attend the consortium meeting. Attitude and proceedings were much like in any open source project - with the small difference that just about everyone in the room wore suit and tie and was a heavyweight industry representative! I have never seen anything like it but I believe the modus operandi is completely unbeatable. We are very happy and proud to parttake in this venture! The response was quite positive, as always the demo is highly appreciated, and we are happy to bridge the two communities. I believe there will be very valuable discussion on both sides, and that everyone will see good things come out of this! Back at the expo QNX presented a nice fast boot demo on Atom. From reset to GL graphics in under two seconds. They have developed their own fastboot code (maybe using some reference code from Intel) but right now it is available only for Atom. Of course they were excited to learn that coreboot allows them to achieve the same performance on a large number of other platforms. We can use the bootloader (startup module in QNX terms) directly as a payload. Startup module + QNX kernel + QNX libc slimmed down is 400-600KB and a full version is 1.2MB. Doable on any board today. Pretty exciting! And QNX is freely available. From r.marek at assembler.cz Sun Mar 8 22:30:25 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Sun, 08 Mar 2009 22:30:25 +0100 Subject: [coreboot] [PATCH] wip - suspend/resume for AMD famF revF CPUs (socket AM2) Message-ID: <49B438F1.20802@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, This patch is a WIP patch to get working S3 on AM2 boards. Currently it works on M2V-MX SE. The resume code does only the ram init right. No code which saves/restores mem is there. It is not yet usable. I needed to implement DQS timming save restore. I use NVRAM in K8M890 for this. The SB600 has also such NVRAM. There is quite strange errata for mine CPU, so the exit self refresh code is strange. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm0OO4ACgkQ3J9wPJqZRNX+6wCg1SMFCEW8IDccBBJWcRV9KtaL jU4An2rIGM5/nU6j/0AErME5oVSdPtSO =SoLP -----END PGP SIGNATURE----- -------------- next part -------------- A non-text attachment was scrubbed... Name: ram_resume.patch Type: text/x-diff Size: 19482 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: ram_resume.patch.sig Type: application/octet-stream Size: 72 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Mon Mar 9 03:04:58 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 09 Mar 2009 03:04:58 +0100 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> Message-ID: <49B4794A.5090003@gmx.net> On 07.03.2009 07:05, ron minnich wrote: > Index: lib/stage2.c > =================================================================== > --- lib/stage2.c (revision 1143) > +++ lib/stage2.c (working copy) > @@ -27,7 +27,22 @@ > #include > #include > #include > +#include > > +unsigned int __attribute__((weak)) cpu_phase1(unsigned int coldboot, > + struct sys_info *sysinfo) > +{ > + printk(BIOS_SPEW, "cpu_phase1: nothing to do\n"); > You may want to print the content of the coldboot param here. > + return 0; > +} > + > +unsigned int __attribute__((weak)) cpu_phase2(unsigned int coldboot, > + struct sys_info *sysinfo) > +{ > + printk(BIOS_SPEW, "cpu_phase2: nothing to do\n"); > Dito. > + return 0; > +} > + > /** > * Main function of the DRAM part of coreboot. > * > @@ -44,8 +59,12 @@ > void *stage2(void) > { > void *mbi; > - > + struct sys_info *sysinfo; > + int is_coldboot(void); > This prototype should live in a header file. > + struct global_vars *global_vars(void); > This prototype is in globalvars.h IIRC, so it can be removed here. > post_code(POST_STAGE2_BEGIN); > + sysinfo = &(global_vars()->sys_info); > + cpu_phase1(is_coldboot(), sysinfo); > dev_init(); > > /* Phase 1 was console init and making printk work. Both functions are > @@ -85,6 +104,11 @@ > dev_phase6(); > show_all_devs(BIOS_DEBUG, "After phase 6."); > > + /* final cleanup: do any remaining CPU setup. This can include memory > + * init, or not, depending on the CPU; it may have been done in phase 1. > + */ > + cpu_phase2(is_coldboot(), sysinfo); > + > /* Write tables to pass information to the payloads. */ > post_code(POST_STAGE2_WRITE_TABLES); > mbi = write_tables(); > > Index: arch/x86/secondary.S > =================================================================== > --- arch/x86/secondary.S (revision 1143) > +++ arch/x86/secondary.S (working copy) > @@ -62,24 +62,28 @@ > movw $8, 0 > movl %eax, %cr0 > movw $9, 0 > - hlt > - /* tested to this point but not past it */ > > /* I am pretty sure this just jumps back into > * ROM; it's an abs jump > */ > - data32 ljmp $0x10, $secondary32 > + data32 ljmp $0x8, $secondary32 > The code line above is a bit confusing and the comment does not really explain what happens. > movw $0xa, 0 > 1: > .code32 > secondary32: > - hlt > - movw $0x18, %ax > + movw $0x11, 0 > + movw $0x10, %ax > +// movw $0x12, 0 > movw %ax, %ds > + movw $0x13, 0 > movw %ax, %es > +// movw $0x14, 0 > movw %ax, %ss > +// movw $0x15, 0 > movw %ax, %fs > +// movw $0x16, 0 > movw %ax, %gs > + movw $0x17, 0 > Can you either activate all movw $something, 0 or deactivate all of them? > > /* Load the Interrupt descriptor table */ > lidt idtarg > @@ -87,6 +91,8 @@ > /* Set the stack pointer */ > movl -4(%ebx),%esp > movl $0, -4(%ebx) > call secondary_cpu_init > 1: hlt > @@ -108,14 +114,6 @@ > /* selgdt 0x10, flat data segment */ > .word 0xffff, 0x0000 > .byte 0x00, 0x93, 0xcf, 0x00 > - > - /* selgdt 0x18, flat code segment for CAR */ > - .word 0xffff, 0x0000 > - .byte 0x00, 0x9b, 0xcf, 0x00 > - > - /* selgdt 0x20, flat data segment for CAR */ > - .word 0xffff, 0x0000 > - .byte 0x00, 0x93, 0xcf, 0x00 > gdt_end: > > > Index: arch/x86/intel/core2/init_cpus.c > =================================================================== > --- arch/x86/intel/core2/init_cpus.c (revision 1143) > +++ arch/x86/intel/core2/init_cpus.c (working copy) > @@ -21,7 +21,6 @@ > * along with this program; if not, write to the Free Software > * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > */ > -#include > #include > #include > #include > @@ -73,6 +72,7 @@ > int nodes, siblings; > result = cpuid(1); > /* See how many sibling cpus we have */ > + printk(BIOS_DEBUG, "cpuid(1) %x\n", result.ebx); > Maybe mention that you're printing ebx. > siblings = (result.ebx >> 16) & 0xff; > if (siblings < 1) { > siblings = 1; > @@ -204,6 +204,9 @@ > * Starting actual IPI sequence... > */ > > + printk(BIOS_SPEW, "Before Startup.apicid %ld\n", apicid); > + printk(BIOS_SPEW, "Before Startup.sb[0] %p @0 %p\n", > + (void *) secondary_base[0], (void *) *(u32 *) 0); > I'm not sure why you're casting *(u32 *)0 to (void *) here. If you change the printk format to %08lx, you can avoid the cast and improve readability. Like this: printk(BIOS_SPEW, "Before Startup.sb[0] %p @0 %08lx\n", (void *) secondary_base[0], *(u32 *) 0); > printk(BIOS_SPEW, "Asserting INIT.\n"); > > /* > @@ -321,7 +324,11 @@ > if (send_status || accept_status) > break; > } > + printk(BIOS_SPEW, "udelay(1000000)\n"); > + udelay(1000000); > printk(BIOS_SPEW, "After Startup.sb[-1] %p\n", (void *) secondary_base[-1]); > No offense, but doesn't gcc scream warnings all over the place here? Do you really want the memory contents of secondary_base[-1] or do you want &secondary_base[-1] instead? Hm. Looking at the code again, the -1 seems to be OK, but negative array indices are somewhere between clever and scary. > + printk(BIOS_SPEW, "After Startup.sb[0] %p @0 %p\n", > + (void *) secondary_base[0], (void *) *(u32 *) 0); > Second cast of the contents of the zero address to void * is unneeded. > if (send_status) > printk(BIOS_WARNING, "APIC never delivered???\n"); > if (accept_status) > @@ -377,18 +384,25 @@ > stackmem->stacks[index].post = 0; > stackmem->stacks[index].active_cpus = active_cpus; > stackmem->stacks[index].start_cpu_lock = start_cpu_lock; > + printk(BIOS_SPEW, "stack[index, apicid, post, active_cpus, start_cpu_lock = [%lx, %x, %d, %p, %p]\n", index, apicid, 0, active_cpus, start_cpu_lock); > /* Advertise the new stack to start_cpu */ > printk(BIOS_SPEW, "Set stack @ %p to %p\n", &secondary_base[-1], (void *)stack_end); > secondary_base[-1] = stack_end; > > /* Start the cpu */ > result = lapic_start_cpu(apicid, secondary_base); > + printk(BIOS_SPEW, "we think we started it. The stack value is 0x%p (should be 0)\n", (void *)secondary_base[-1]); > > if (result) { > + printk(BIOS_SPEW, "Spinning on post which is now 0x%x\n", > + stackmem->stacks[index].post); > result = 0; > /* Wait 1s or until the new the new cpu calls in */ > - for(count = 0; count < 100000 ; count++) { > - if (stackmem->stacks[index].post) { > + for(count = 0; count < 1000000 ; count++) { > + printk(BIOS_SPEW, > + "BSP post 0x%x\n", > + stackmem->stacks[index].post); > + if (stackmem->stacks[index].post >= AP_STOP_OK) { > result = 1; > break; > } > @@ -476,9 +490,12 @@ > struct atomic *active_cpus, > struct spinlock *start_cpu_lock) > { > +printk(BIOS_SPEW, "secondary start\n"); > post = AP_START; > +printk(BIOS_SPEW, "secondary post %d\n", post); > atomic_inc(active_cpus); > post = AP_ACTIVEUP; > +printk(BIOS_SPEW, "secondary post %d\n", post); > if (SERIAL_CPU_INIT && (CONFIG_MAX_PHYSICAL_CPUS > 2)) > spin_lock(start_cpu_lock); > post = AP_LOCKED; > @@ -559,7 +576,7 @@ > * @param sysinfo The sys_info pointer > * @returns the BSP APIC ID > */ > -unsigned int init_cpus(unsigned cpu_init_detectedx, > +unsigned int cpu_phase1(unsigned cpu_init_detectedx, > struct sys_info *sysinfo) > { > /* Number of cpus that are currently running in coreboot */ > There is something about stack setup which smells just wrong. Code excerpts follow. struct stack { u32 post; u32 index; u32 apicid; struct atomic *active_cpus; struct spinlock *start_cpu_lock; u32 callerpc; u32 data[16384/sizeof(u32) - 7]; }; [...] stack_end = (u32)&stackmem->stacks[index].data; stack_end is now the address of where downwards grow of the stack must end, NOT the top of a pristine stack aka initial stack pointer. void __attribute__((regparm(0))) secondary_cpu_init( u32 post, u32 index, u32 apicid, struct atomic *active_cpus, struct spinlock *start_cpu_lock) { [...] I guess the function signature is intended to match struct stack, but if that is the case, you will overflow the stack. The data member of struct stack is at the wrong end of the struct. Regards, Carl-Daniel -- http://www.hailfinger.org/ From c-d.hailfinger.devel.2006 at gmx.net Mon Mar 9 03:07:24 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Mon, 09 Mar 2009 03:07:24 +0100 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <13426df10903070737h46982b9dy57b559bb0f067cca@mail.gmail.com> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> <20090307100533.9043.qmail@stuge.se> <13426df10903070737h46982b9dy57b559bb0f067cca@mail.gmail.com> Message-ID: <49B479DC.90003@gmx.net> On 07.03.2009 16:37, ron minnich wrote: > On Sat, Mar 7, 2009 at 2:05 AM, Peter Stuge wrote: > > >>> + movw $0x11, 0 >>> >> Just curious, what do these movws to 0 do? >> >> > > Glad you asked! These are how I got it debugged. Since we have another > CPU (BSP) I had the BSP wait and print out the values. These are POST > codes for AP startup! So BSP can now monitor AP progress with > variables -- no more "worked"/"did not work" but "here's how far it > got". The BSP has far more knowledge than in v2 of how far things got. > > They movw to 0 going to be removed, I think; we can depend on > secondary.S. Or should we? Should I leave them in? > Please leave them in! More diagnostics are always welcome. If would be nice to be able to determine the AP core ID somehow from the AP POST code. You already use 4 bytes for that purpose. The first 2 bytes have a 0-extended POST code, the second 2 bytes have 0xbeef. Regards, Carl-Daniel -- http://www.hailfinger.org/ From phueper at hueper.net Mon Mar 9 15:19:19 2009 From: phueper at hueper.net (Pattrick Hueper) Date: Mon, 9 Mar 2009 15:19:19 +0100 Subject: [coreboot] v2 + qemu + yabel In-Reply-To: <2831fecf0903060640ydf59bd2q23bf9f4613099db1@mail.gmail.com> References: <2831fecf0903060640ydf59bd2q23bf9f4613099db1@mail.gmail.com> Message-ID: Hi, i debugged into the VGA init code... it seems that the device (PCI: 00:02.0) is not assigned a ROM address. Further debugging into pci_get_rom_resource and pci_moving_config32 shows that pci_read_config32 _always_ reads a 0 from the ROM BAR, even if 0xffffffff is written just before reading... Any ideas? I will try to find out what v3 does for the qemu VGA device... Pattrick On Fri, Mar 6, 2009 at 3:40 PM, Myles Watson wrote: > On Fri, Mar 6, 2009 at 7:26 AM, Pattrick Hueper wrote: >> Hi, >> >> i am trying to get Stefans merged yabel working with v2 under qemu... >> but it doesnt work. >> >> i set CONFIG_PCI_ROM_RUN and CONFIG_PCI_OPTION_ROM_RUN_YABEL >> >> As far as i see, the VGA device is not assigned a ROM address and thus >> run_bios is never called... i dont quite understand why this happens. >> >> I also tried to use pci_dev_init instead of vga_init as the init >> function, but it still wont work :-( >> >> Anybody any idea, what i am doing wrong? > > Look in /emulation/qemu-x86/mainboard.c and /emulation/qemu-x86/vgabios.c > > In v2 qemu has its own VGA init code. ?I'd bet you need to bypass that. > > Thanks, > Myles > From mylesgw at gmail.com Mon Mar 9 16:41:09 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 08:41:09 -0700 Subject: [coreboot] v2 + qemu + yabel In-Reply-To: References: <2831fecf0903060640ydf59bd2q23bf9f4613099db1@mail.gmail.com> Message-ID: <2831fecf0903090841t28118df7o6c6f9c4b6e25a8fb@mail.gmail.com> On Mon, Mar 9, 2009 at 7:19 AM, Pattrick Hueper wrote: > Hi, > > i debugged into the VGA init code... it seems that the device (PCI: > 00:02.0) is not assigned a ROM address. > Further debugging into pci_get_rom_resource and pci_moving_config32 > shows that pci_read_config32 _always_ reads a 0 from the ROM BAR, even > if 0xffffffff is written just before reading... > > Any ideas? I will try to find out what v3 does for the qemu VGA device... In v3 it's hardcoded too. The VGA BIOS is always mapped to 0xc0000 in qemu, so v3 just sets the value. In device/pci_rom.c it checks to see if dev->rom_address is set. In /mainboard/emulation/qemu-x86/vga.c it sets it to 0xc0000. Thanks, Myles From mylesgw at gmail.com Mon Mar 9 17:00:59 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 09:00:59 -0700 Subject: [coreboot] seaBIOS config options "for emulators" In-Reply-To: <20090307000849.GB6309@morn.localdomain> References: <49B1B2AF.8040501@julianfamily.org> <20090307000849.GB6309@morn.localdomain> Message-ID: <2831fecf0903090900n76a89be5xb05ee306581a6cb2@mail.gmail.com> On Fri, Mar 6, 2009 at 5:08 PM, Kevin O'Connor wrote: > On Fri, Mar 06, 2009 at 03:33:03PM -0800, Joe Julian wrote: >> You suggested, on the coreboot IRC channel, that I enable smbios in >> seabios to solve the missing mptable and RSDP problem. The reason those >> are turned off is because the comments for CONFIG_PIRTABLE, >> CONFIG_MPTABLE, COMFIG_SMBIOS, and CONFIG_ACPI all state, "for >> emulators". Since this is a bare metal install, wouldn't it be correct >> to have those options disabled since we need the real data rather than >> simulated data? > > Linux, by default, wont use the acpi tables unless there is an smbios > table. ?The current coreboot targets don't support building an smbios > table. ?So, I programmed SeaBIOS to build a dummy smbios table when it > is used with coreboot. > > It's safe to leave all of: > > #define CONFIG_PIRTABLE 1 > #define CONFIG_MPTABLE 1 > #define CONFIG_SMBIOS 1 > #define CONFIG_ACPI 1 Linux has been happy without these defines for me, except that it says: DMI not present or invalid. //Here's a snippet from the log: Ram Size=0xc0000000 init PNPBIOS table Scan for VGA option rom Attempting to init PCI bdf 00000200 Attempting to map option rom on dev 00000200 Option rom sizing returned f5000000 fffe0000 Inspecting possible rom at f5000000 (vd=014110de bdf=00000200) Copying option rom from f5000000 to 000c0000 Running option rom at 0000c000:00000003 Turning on vga console Starting SeaBIOS init keyboard i8042 ctr old=00000000 new=00000020 ps2_recvbyte timeout i8042 ctr old=00000000 new=00000020 i8042 ctr old=00000000 new=00000020 i8042 ctr old=00000061 new=00000060 keyboard initialized init lpt init serial init mouse e820 map has 7 items: 0: 0000000000000000 - 000000000009fc00 = 1 1: 000000000009fc00 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 000000007fff0000 = 1 4: 000000007fff0000 - 0000000080000000 = 2 5: 0000000080000000 - 00000000c0000000 = 1 6: 0000000100000000 - 0000000140000000 = 1 final bios_table_addr: 0x000faa4c (used 84%) init boot device ordering //This is the log if I enable them: Copying PIR from 7fff0000 to 000fa9a0 Copying ACPI RSDP from 7fff0400 to 000fa9f0 Copying MPTABLE from 7fff1800/7fff1810 to 000faa10 init SMBIOS tables Found 4 cpu(s) SMBIOS table addr=0x000fb060 Ram Size=0xc0000000 init PNPBIOS table Scan for VGA option rom Attempting to init PCI bdf 00000200 Attempting to map option rom on dev 00000200 Option rom sizing returned f5000000 fffe0000 Inspecting possible rom at f5000000 (vd=014110de bdf=00000200) Copying option rom from f5000000 to 000c0000 Running option rom at 0000c000:00000003 Turning on vga console Starting SeaBIOS init keyboard i8042 ctr old=00000000 new=00000020 ps2_recvbyte timeout i8042 ctr old=00000000 new=00000020 i8042 ctr old=00000000 new=00000020 i8042 ctr old=00000061 new=00000060 keyboard initialized init lpt init serial init mouse e820 map has 7 items: 0: 000000000009fc00 - 00000000000a0000 = 2 1: 00000000000f0000 - 0000000000100000 = 2 2: 0f13000031204d4d - 0f1200003120604d = 268435535 3: 0014001314000001 - 0014501313000001 = 18022417 4: 20000b2000000000 - 20000b2000000000 = 294656 5: 000000008000007f - 00000000c000007f = 1 6: 0000000100000000 - 0000000140000000 = 1 final bios_table_addr: 0x000fb1df (used 103%) bios_table_end_addr overflow! Mappings 2 & 3 look pretty bad. Is it because the tables were too big, or are the tables too big because of the broken map? How do I make more room for the tables? Thanks, Myles From stepan at coresystems.de Mon Mar 9 17:21:26 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Mon, 09 Mar 2009 17:21:26 +0100 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <49A86EB2.7030405@gmx.net> References: <49A86EB2.7030405@gmx.net> Message-ID: <49B54206.6080803@coresystems.de> Hi, due to a severe lack of spare time I am not going to set any gsoc effort up this year. If someone wants coreboot to participate, I suggest you stand up now and do it. The deadline for mentoring organizations is coming pretty close. I'll gladly share my experience from previous years with any new mentors/org admins. Best regards, Stefan On 27.02.2009 23:52 Uhr, Carl-Daniel Hailfinger wrote: > Hi all, > > GSoC 2009 is approaching and although the number of total slots has been > reduced, there is a chance we might get some slots for coreboot and/or > flashrom. We might want to apply separately for coreboot and flashrom, > maybe also for buildrom or libpayload because they are essentially > separate projects. I don't know if SeaBIOS would benefit from GSoC > because it seems rather complete to me. > > Deadline for organizational applications: March 13, 2009 noon. > No application possible before March 9, 2009 noon. > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_org_apply_4694175091022641 > > Full timeline: > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_timeline_5354032302481437_ > > Regards, > Carl-Daniel > > -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From phueper at hueper.net Mon Mar 9 18:08:13 2009 From: phueper at hueper.net (Pattrick Hueper) Date: Mon, 9 Mar 2009 18:08:13 +0100 Subject: [coreboot] v2 + qemu + yabel In-Reply-To: <2831fecf0903090841t28118df7o6c6f9c4b6e25a8fb@mail.gmail.com> References: <2831fecf0903060640ydf59bd2q23bf9f4613099db1@mail.gmail.com> <2831fecf0903090841t28118df7o6c6f9c4b6e25a8fb@mail.gmail.com> Message-ID: yiiehaah... thanks, that did it... assigning dev->rom_address= 0xc0000; in emulation/qemu-x86/mainboard.c function vga_init() and then calling pci_dev_init() calls yabel and the qemu screen is initialized. Once i cleaned up the code i will post patches... Thanks Myles! Cheers, Pattrick On Mon, Mar 9, 2009 at 4:41 PM, Myles Watson wrote: > On Mon, Mar 9, 2009 at 7:19 AM, Pattrick Hueper wrote: >> Hi, >> >> i debugged into the VGA init code... it seems that the device (PCI: >> 00:02.0) is not assigned a ROM address. >> Further debugging into pci_get_rom_resource and pci_moving_config32 >> shows that pci_read_config32 _always_ reads a 0 from the ROM BAR, even >> if 0xffffffff is written just before reading... >> >> Any ideas? I will try to find out what v3 does for the qemu VGA device... > > In v3 it's hardcoded too. ?The VGA BIOS is always mapped to 0xc0000 in > qemu, so v3 just sets the value. ?In device/pci_rom.c it checks to see > if dev->rom_address is set. ?In /mainboard/emulation/qemu-x86/vga.c it > sets it to 0xc0000. > > Thanks, > Myles > From mylesgw at gmail.com Mon Mar 9 18:17:16 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 10:17:16 -0700 Subject: [coreboot] seaBIOS config options "for emulators" In-Reply-To: <2831fecf0903090900n76a89be5xb05ee306581a6cb2@mail.gmail.com> References: <49B1B2AF.8040501@julianfamily.org> <20090307000849.GB6309@morn.localdomain> <2831fecf0903090900n76a89be5xb05ee306581a6cb2@mail.gmail.com> Message-ID: <2831fecf0903091017v1bc99f49k7bb472e881d8e6f4@mail.gmail.com> On Mon, Mar 9, 2009 at 9:00 AM, Myles Watson wrote: > On Fri, Mar 6, 2009 at 5:08 PM, Kevin O'Connor wrote: >> On Fri, Mar 06, 2009 at 03:33:03PM -0800, Joe Julian wrote: >>> You suggested, on the coreboot IRC channel, that I enable smbios in >>> seabios to solve the missing mptable and RSDP problem. The reason those >>> are turned off is because the comments for CONFIG_PIRTABLE, >>> CONFIG_MPTABLE, COMFIG_SMBIOS, and CONFIG_ACPI all state, "for >>> emulators". Since this is a bare metal install, wouldn't it be correct >>> to have those options disabled since we need the real data rather than >>> simulated data? >> >> Linux, by default, wont use the acpi tables unless there is an smbios >> table. ?The current coreboot targets don't support building an smbios >> table. ?So, I programmed SeaBIOS to build a dummy smbios table when it >> is used with coreboot. >> >> It's safe to leave all of: >> >> #define CONFIG_PIRTABLE 1 >> #define CONFIG_MPTABLE 1 >> #define CONFIG_SMBIOS 1 >> #define CONFIG_ACPI 1 > > Linux has been happy without these defines for me, except that it says: > > DMI not present or invalid. > > //Here's a snippet from the log: > > Ram Size=0xc0000000 > init PNPBIOS table > Scan for VGA option rom > Attempting to init PCI bdf 00000200 > Attempting to map option rom on dev 00000200 > Option rom sizing returned f5000000 fffe0000 > Inspecting possible rom at f5000000 (vd=014110de bdf=00000200) > Copying option rom from f5000000 to 000c0000 > Running option rom at 0000c000:00000003 > Turning on vga console > Starting SeaBIOS > > init keyboard > i8042 ctr old=00000000 new=00000020 > ps2_recvbyte timeout > i8042 ctr old=00000000 new=00000020 > i8042 ctr old=00000000 new=00000020 > i8042 ctr old=00000061 new=00000060 > keyboard initialized > init lpt > init serial > init mouse > e820 map has 7 items: > ?0: 0000000000000000 - 000000000009fc00 = 1 > ?1: 000000000009fc00 - 00000000000a0000 = 2 > ?2: 00000000000f0000 - 0000000000100000 = 2 > ?3: 0000000000100000 - 000000007fff0000 = 1 > ?4: 000000007fff0000 - 0000000080000000 = 2 > ?5: 0000000080000000 - 00000000c0000000 = 1 > ?6: 0000000100000000 - 0000000140000000 = 1 > final bios_table_addr: 0x000faa4c (used 84%) > init boot device ordering > > > //This is the log if I enable them: > > Copying PIR from 7fff0000 to 000fa9a0 > Copying ACPI RSDP from 7fff0400 to 000fa9f0 > Copying MPTABLE from 7fff1800/7fff1810 to 000faa10 > init SMBIOS tables > Found 4 cpu(s) > SMBIOS table addr=0x000fb060 > Ram Size=0xc0000000 > init PNPBIOS table > Scan for VGA option rom > Attempting to init PCI bdf 00000200 > Attempting to map option rom on dev 00000200 > Option rom sizing returned f5000000 fffe0000 > Inspecting possible rom at f5000000 (vd=014110de bdf=00000200) > Copying option rom from f5000000 to 000c0000 > Running option rom at 0000c000:00000003 > Turning on vga console > Starting SeaBIOS > > init keyboard > i8042 ctr old=00000000 new=00000020 > ps2_recvbyte timeout > i8042 ctr old=00000000 new=00000020 > i8042 ctr old=00000000 new=00000020 > i8042 ctr old=00000061 new=00000060 > keyboard initialized > init lpt > init serial > init mouse > e820 map has 7 items: > ?0: 000000000009fc00 - 00000000000a0000 = 2 > ?1: 00000000000f0000 - 0000000000100000 = 2 > ?2: 0f13000031204d4d - 0f1200003120604d = 268435535 > ?3: 0014001314000001 - 0014501313000001 = 18022417 > ?4: 20000b2000000000 - 20000b2000000000 = 294656 > ?5: 000000008000007f - 00000000c000007f = 1 > ?6: 0000000100000000 - 0000000140000000 = 1 > final bios_table_addr: 0x000fb1df (used 103%) > bios_table_end_addr overflow! > > Mappings 2 & 3 look pretty bad. ?Is it because the tables were too > big, or are the tables too big because of the broken map? Tables were too big. > How do I make more room for the tables? I set CONFIG_MAX_BIOSTABLE to 2048+512 Thanks, Myles From mylesgw at gmail.com Mon Mar 9 18:55:28 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 10:55:28 -0700 Subject: [coreboot] SimNOW and SeaBIOS Message-ID: <2831fecf0903091055w2fac2bb4x1e50271d6265e0d0@mail.gmail.com> SeaBIOS won't work with SimNOW unless you make the error checking in ata.c less strict. This is the message you get: ata_transfer : no sectors left (status 00000008) I reported it to the SimNOW team since it seems like they're not following the spec, but it's been a long time and the bug is still there. To get past it: dprintf(6, "ata_transfer : no sectors left (status %02x)\n", status); + if (status != 0x8) return -7; Thanks, Myles From r.marek at assembler.cz Mon Mar 9 21:36:37 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 09 Mar 2009 21:36:37 +0100 Subject: [coreboot] amdk8_util.asl fixes, documentation, and ACPI question In-Reply-To: <2831fecf0903040959q273772ccw336873bacd463a8f@mail.gmail.com> References: <2831fecf0903040959q273772ccw336873bacd463a8f@mail.gmail.com> Message-ID: <49B57DD5.3080802@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, > Why is this logic here? Why do you want a region from TOM-(4G-2M)* Tha acpi FAQ is just a example imho. I guess we should add only the PCI mem and not the real mem maybe? Please have you checked the m2v-mx version of the k8-util.asl? I fixed there also something. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm1fdMACgkQ3J9wPJqZRNVvIACfY1Nlr0kFzIXALInMCU6l6yPv vEUAnjxS8Gp6hDtzLt4Q549UDCloUoFj =tG/G -----END PGP SIGNATURE----- From r.marek at assembler.cz Mon Mar 9 21:37:38 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 09 Mar 2009 21:37:38 +0100 Subject: [coreboot] [PATCH 2/2] AMD boards to use new Power Now infrastructure In-Reply-To: <2831fecf0903021457r59f0392dk16f83e3ff7ed9ff0@mail.gmail.com> References: <4996C49E.8070303@assembler.cz> <499CD145.3000907@gmx.net> <499D1ACE.5070609@assembler.cz> <2831fecf0902250900yd566b40s1b7f081ef8f1e449@mail.gmail.com> <49AC62A7.1000903@assembler.cz> <2831fecf0903021457r59f0392dk16f83e3ff7ed9ff0@mail.gmail.com> Message-ID: <49B57E12.6060304@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 > I guess the alternative is to force users to use matched CPUs. Do we > already force that for microcode patches? Dont know haven't looked into this yet. For now you could invoke the routines 2 times more I guess. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm1fhIACgkQ3J9wPJqZRNVf7ACfb+e964upDVGt1WZLbSNG/mhz bnwAoI0dSPDxviZb/zeXyprDt5Xn5P1a =13lA -----END PGP SIGNATURE----- From mylesgw at gmail.com Mon Mar 9 21:53:04 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 13:53:04 -0700 Subject: [coreboot] amdk8_util.asl fixes, documentation, and ACPI question In-Reply-To: <49B57DD5.3080802@assembler.cz> References: <2831fecf0903040959q273772ccw336873bacd463a8f@mail.gmail.com> <49B57DD5.3080802@assembler.cz> Message-ID: <2831fecf0903091353u3d86234x4a8ea541d0dcf81b@mail.gmail.com> On Mon, Mar 9, 2009 at 1:36 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > >> Why is this logic here? ?Why do you want a region from TOM-(4G-2M)* > > Tha acpi FAQ is just a example imho. I guess we should add only the PCI mem and > not the real mem maybe? > > Please have you checked the m2v-mx version of the k8-util.asl? I fixed there > also something. It looks like you added the Increment so that sizes end up being round numbers. I found that one too. The strange thing is that SimNOW (serengeti_cheetah) loads Windows fine even with the bugs. It's frustrating because even though I'm making it more compliant, I'm not sure I'm getting closer. Thanks, Myles From mylesgw at gmail.com Mon Mar 9 21:53:43 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 13:53:43 -0700 Subject: [coreboot] [PATCH 2/2] AMD boards to use new Power Now infrastructure In-Reply-To: <49B57E12.6060304@assembler.cz> References: <4996C49E.8070303@assembler.cz> <499CD145.3000907@gmx.net> <499D1ACE.5070609@assembler.cz> <2831fecf0902250900yd566b40s1b7f081ef8f1e449@mail.gmail.com> <49AC62A7.1000903@assembler.cz> <2831fecf0903021457r59f0392dk16f83e3ff7ed9ff0@mail.gmail.com> <49B57E12.6060304@assembler.cz> Message-ID: <2831fecf0903091353q143eb931m73542dfa19a214e5@mail.gmail.com> On Mon, Mar 9, 2009 at 1:37 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > >> I guess the alternative is to force users to use matched CPUs. ?Do we >> already force that for microcode patches? > > Dont know haven't looked into this yet. For now you could invoke the routines 2 > times more I guess. Yes. For now that's what I'm doing. Thanks, Myles From r.marek at assembler.cz Mon Mar 9 22:33:04 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Mon, 09 Mar 2009 22:33:04 +0100 Subject: [coreboot] amdk8_util.asl fixes, documentation, and ACPI question In-Reply-To: <2831fecf0903091353u3d86234x4a8ea541d0dcf81b@mail.gmail.com> References: <2831fecf0903040959q273772ccw336873bacd463a8f@mail.gmail.com> <49B57DD5.3080802@assembler.cz> <2831fecf0903091353u3d86234x4a8ea541d0dcf81b@mail.gmail.com> Message-ID: <49B58B10.9080108@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 > It looks like you added the Increment so that sizes end up being round > numbers. I found that one too. The strange thing is that SimNOW Yes see the ACPI FAQ windows needs it. I'm now reviewing testing your ACPI patches, stay tuned. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm1iw8ACgkQ3J9wPJqZRNU2tgCgspktjzr4bH4MQeW26En7xX67 dWEAnRu5tNANlyr0LRuYYjHjK2QP2jPV =V/d4 -----END PGP SIGNATURE----- From r.marek at assembler.cz Tue Mar 10 00:08:36 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 10 Mar 2009 00:08:36 +0100 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0903040909p48f318e9m37ae0fe1551b409f@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49A8914C.9060001@gmx.net> <8C585EA3396447C4973D331C5A116681@chimp> <2831fecf0903040909p48f318e9m37ae0fe1551b409f@mail.gmail.com> Message-ID: <49B5A174.6010502@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, /* If this is the SouthBridge node and link, add a DRAM region. */ + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (\_SB.PCI0.TOM1, MMIN) + Subtract (MMAX, MMIN, MLEN) + Increment (MLEN) + } + This part cause Windows 7 to BSOD and restart. Did not look at it yet. It starts otherwise. (I added also the another Increment (MLEN), its late for me now to test without that). If you commit it with a proposed I think we can check in the patch. (dont know for fam10 maybe same change is needed). Acked-by: Rudolf Marek Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm1oXMACgkQ3J9wPJqZRNUhHgCeKcCN6jp47OIlQ967pNhsheuo 0VYAnidQifLzUwsd8G6j7z0MPqDBhKdG =QUMG -----END PGP SIGNATURE----- From r.marek at assembler.cz Tue Mar 10 00:15:43 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 10 Mar 2009 00:15:43 +0100 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> Message-ID: <49B5A31F.5080502@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Acked-by: Rudolf Marek If you can explain to me why the superIO changes. Also The SMM does nothing to do with IRQ9. Get rid of SMM for now. The IRQ 9 needs to be setup for ACPI in SB. Thats it (and perhaps it needed also an IRQ override). It looks fine, assuming it works for you then lets put it in. A lot of people is trying to get ACPI working those days. Please note that some changes to second patch needs to be done too. For the global acpik8_util Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm1ox8ACgkQ3J9wPJqZRNVh8wCgh07/lzRaV1OWCEYNOn3FHngi mtUAoKBLcDT6yePbSeeb0bP1JSHoE5fj =2V8O -----END PGP SIGNATURE----- From r.marek at assembler.cz Tue Mar 10 00:24:08 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 10 Mar 2009 00:24:08 +0100 Subject: [coreboot] [PATCH] M2V-MX SE random fixups Message-ID: <49B5A518.8090804@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region. This is last missing bit to make SeaBIOS & Windows happy ;) This patch depends on the small patch adding the HAVE_HIGH_TABLES to K8 NB by Myles. Windows 7 still boots ;) once this is in, we have no need for other patches. Signed-off-by: Rudolf Marek Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm1pRgACgkQ3J9wPJqZRNXOfQCePVAeWWHJBNIf96NseAH+E2HY 9JsAoKuanbUTqaY/1KyhVaTci3PHUvbd =nzql -----END PGP SIGNATURE----- -------------- next part -------------- A non-text attachment was scrubbed... Name: fixes.patch Type: text/x-diff Size: 3919 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: fixes.patch.sig Type: application/octet-stream Size: 72 bytes Desc: not available URL: From kevin at koconnor.net Tue Mar 10 01:05:27 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Mon, 9 Mar 2009 20:05:27 -0400 Subject: [coreboot] SimNOW and SeaBIOS In-Reply-To: <2831fecf0903091055w2fac2bb4x1e50271d6265e0d0@mail.gmail.com> References: <2831fecf0903091055w2fac2bb4x1e50271d6265e0d0@mail.gmail.com> Message-ID: <20090310000527.GB16577@morn.localdomain> On Mon, Mar 09, 2009 at 10:55:28AM -0700, Myles Watson wrote: > SeaBIOS won't work with SimNOW unless you make the error checking in > ata.c less strict. > > This is the message you get: > ata_transfer : no sectors left (status 00000008) > > I reported it to the SimNOW team since it seems like they're not > following the spec, but it's been a long time and the bug is still > there. To get past it: > dprintf(6, "ata_transfer : no sectors left (status %02x)\n", status); > + if (status != 0x8) > return -7; Yeah, I've run into this too. It looks like the SimNOW CDROM doesn't clear the DRQ bit - even though the spec definitely says it must be cleared. I make the same change locally (just warn and not abort the transfer) when I test with SimNOW. -Kevin From kevin at koconnor.net Tue Mar 10 01:07:14 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Mon, 9 Mar 2009 20:07:14 -0400 Subject: [coreboot] seaBIOS config options "for emulators" In-Reply-To: <2831fecf0903091017v1bc99f49k7bb472e881d8e6f4@mail.gmail.com> References: <49B1B2AF.8040501@julianfamily.org> <20090307000849.GB6309@morn.localdomain> <2831fecf0903090900n76a89be5xb05ee306581a6cb2@mail.gmail.com> <2831fecf0903091017v1bc99f49k7bb472e881d8e6f4@mail.gmail.com> Message-ID: <20090310000714.GC16577@morn.localdomain> On Mon, Mar 09, 2009 at 10:17:16AM -0700, Myles Watson wrote: > On Mon, Mar 9, 2009 at 9:00 AM, Myles Watson wrote: > > Mappings 2 & 3 look pretty bad. ?Is it because the tables were too > > big, or are the tables too big because of the broken map? > > Tables were too big. > > > How do I make more room for the tables? > > I set CONFIG_MAX_BIOSTABLE to 2048+512 Yeah - your mptable is surprisingly big (~1600 bytes). I can up the default if needed. BTW, if you do math in a macro, be sure to put parenthesis around it (ie, "(2048+512)"). -Kevin From kevin at koconnor.net Tue Mar 10 01:09:13 2009 From: kevin at koconnor.net (Kevin O'Connor) Date: Mon, 9 Mar 2009 20:09:13 -0400 Subject: [coreboot] the seabios reboot in the post process In-Reply-To: References: <20090305003206.GA16862@morn.localdomain> <49AFA5AA.5000303@tadpole.com> <20090305133729.GA22747@morn.localdomain> Message-ID: <20090310000913.GD16577@morn.localdomain> On Mon, Mar 09, 2009 at 01:54:56AM +0000, wei yang wrote: > > Hi, Kevin: > Your patch does work for my issue. > I think it is a bug in the seabios, since some chipset will use > the bit 7 on the 0x70. But the current Seabios doesn't handle > this scenario. Thanks your response. :). Thanks. The latest SeaBIOS git will keep the high bit set on 0x70 writes. > by they way, here I got another question when seabios tring to boot > through the CDROM. I have connected a SATA DVD device within Fedora > 10 install CD to the board, which can be found when the payload is > FILO. When I use the Seabios, it does invoke the Handle 18 and > return the error code :00000002. The code means "cd rom not found" > after I checked the code in the cdrom.c. I am wandering why it will > happen? do you have some comments? I'll need to see the log. It looks like SeaBIOS didn't find your cdrom. -Kevin From c-d.hailfinger.devel.2006 at gmx.net Tue Mar 10 01:21:29 2009 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Tue, 10 Mar 2009 01:21:29 +0100 Subject: [coreboot] SimNOW and SeaBIOS In-Reply-To: <20090310000527.GB16577@morn.localdomain> References: <2831fecf0903091055w2fac2bb4x1e50271d6265e0d0@mail.gmail.com> <20090310000527.GB16577@morn.localdomain> Message-ID: <49B5B289.9060807@gmx.net> On 10.03.2009 01:05, Kevin O'Connor wrote: > On Mon, Mar 09, 2009 at 10:55:28AM -0700, Myles Watson wrote: > >> SeaBIOS won't work with SimNOW unless you make the error checking in >> ata.c less strict. >> >> This is the message you get: >> ata_transfer : no sectors left (status 00000008) >> >> I reported it to the SimNOW team since it seems like they're not >> following the spec, but it's been a long time and the bug is still >> there. To get past it: >> dprintf(6, "ata_transfer : no sectors left (status %02x)\n", status); >> + if (status != 0x8) >> return -7; >> > > Yeah, I've run into this too. It looks like the SimNOW CDROM doesn't > clear the DRQ bit - even though the spec definitely says it must be > cleared. > > I make the same change locally (just warn and not abort the transfer) > when I test with SimNOW. > Maybe add a conditional message: "Working around SimNow bug" so users and coders know what's happening. Regards, Carl-Daniel -- http://www.hailfinger.org/ From mylesgw at gmail.com Tue Mar 10 04:28:56 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 20:28:56 -0700 Subject: [coreboot] seaBIOS config options "for emulators" In-Reply-To: <20090310000714.GC16577@morn.localdomain> References: <49B1B2AF.8040501@julianfamily.org> <20090307000849.GB6309@morn.localdomain> <2831fecf0903090900n76a89be5xb05ee306581a6cb2@mail.gmail.com> <2831fecf0903091017v1bc99f49k7bb472e881d8e6f4@mail.gmail.com> <20090310000714.GC16577@morn.localdomain> Message-ID: <2831fecf0903092028x3bf82c0bt296de355c6d960b5@mail.gmail.com> On Mon, Mar 9, 2009 at 5:07 PM, Kevin O'Connor wrote: > On Mon, Mar 09, 2009 at 10:17:16AM -0700, Myles Watson wrote: >> On Mon, Mar 9, 2009 at 9:00 AM, Myles Watson wrote: >> > Mappings 2 & 3 look pretty bad. ?Is it because the tables were too >> > big, or are the tables too big because of the broken map? >> >> Tables were too big. >> >> > How do I make more room for the tables? >> >> I set CONFIG_MAX_BIOSTABLE to 2048+512 > > Yeah - your mptable is surprisingly big (~1600 bytes). ?I can up the > default if needed. I would expect this board to be on the upper end of the requirement since it has so many APICs, 3 PCI root busses, etc. Most people probably won't need more space. > BTW, if you do math in a macro, be sure to put parenthesis around it > (ie, "(2048+512)"). Good to remember. I actually put 2560 but wanted it to be more clear why I chose it. Thanks, Myles From mylesgw at gmail.com Tue Mar 10 04:46:25 2009 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 9 Mar 2009 20:46:25 -0700 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B5A31F.5080502@assembler.cz> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> Message-ID: <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> On Mon, Mar 9, 2009 at 4:15 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > Acked-by: Rudolf Marek > > If you can explain to me why the superIO changes. For some reason the SuperIO puts the RTC at 0x400, even though it's usually at 0x70. If I put it at 0x70 the keyboard and mouse don't work :( I put it at 0x90 and corrected the size so that it wouldn't conflict with other devices. That makes Linux happy with it. It still could be a problem for Windows not to have it at 0x70. > Also The SMM does nothing to > do with IRQ9. Get rid of SMM for now. The IRQ 9 needs to be setup for ACPI in > SB. Thats it (and perhaps it needed also an IRQ override). Sorry I must have misunderstood this again. I thought this was why I keep getting : IRQ9 nobody cared messages from Linux. It's the last thing that Linux complains about. I'm not sure what I should do so that somebody cares. > It looks fine, assuming it works for you then lets put it in. A lot of people is > trying to get ACPI working those days. It's mostly working. > > Please note that some changes to second patch needs to be done too. For the > global acpik8_util Yes. I was trying to implement what I thought was the intent of the original. Since then I've taken out the VGA IO port regions and the DRAM region. It's a lot more complicated because I have multiple root buses. As far as I can tell the factory BIOS is also not 100% compliant with the spec, which is making it harder to see what's wrong with mine. My current state is hopefully better than what it was when I first submitted these patches, but the BSOD is the same. Thanks, Myles From Qingpei.Wang at amd.com Tue Mar 10 13:20:53 2009 From: Qingpei.Wang at amd.com (Wang, Qingpei) Date: Tue, 10 Mar 2009 20:20:53 +0800 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <49B54206.6080803@coresystems.de> References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> Message-ID: Hi all It sounds interesting. If there is any proper projects, I would like to join in. Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD) -----Original Message----- From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Stefan Reinauer Sent: Tuesday, March 10, 2009 12:21 AM To: Coreboot Subject: Re: [coreboot] GSoC 2009 deadlines Hi, due to a severe lack of spare time I am not going to set any gsoc effort up this year. If someone wants coreboot to participate, I suggest you stand up now and do it. The deadline for mentoring organizations is coming pretty close. I'll gladly share my experience from previous years with any new mentors/org admins. Best regards, Stefan On 27.02.2009 23:52 Uhr, Carl-Daniel Hailfinger wrote: > Hi all, > > GSoC 2009 is approaching and although the number of total slots has been > reduced, there is a chance we might get some slots for coreboot and/or > flashrom. We might want to apply separately for coreboot and flashrom, > maybe also for buildrom or libpayload because they are essentially > separate projects. I don't know if SeaBIOS would benefit from GSoC > because it seems rather complete to me. > > Deadline for organizational applications: March 13, 2009 noon. > No application possible before March 9, 2009 noon. > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_org_apply_4694175091022641 > > Full timeline: > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_timeline_5354032302481437_ > > Regards, > Carl-Daniel > > -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info at coresystems.de * http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg * HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer * Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot From Qingpei.Wang at amd.com Tue Mar 10 13:25:40 2009 From: Qingpei.Wang at amd.com (Wang, Qingpei) Date: Tue, 10 Mar 2009 20:25:40 +0800 Subject: [coreboot] Problems about booting windows xp In-Reply-To: References: <20090118021006.GA14386@morn.localdomain> <49759968.8040907@assembler.cz><49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz><49B0E7F3.2070505@assembler.cz> Message-ID: Hi -----Original Message----- From: Myles Watson [mailto:mylesgw at gmail.com] Sent: Friday, March 06, 2009 10:12 PM To: Wang, Qingpei; 'Rudolf Marek'; 'Kevin O'Connor' Cc: Bao, Zheng; Xie, Michael; Perley, Tim; 'Coreboot' Subject: RE: [coreboot] Problems about booting windows xp > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Wang, Qingpei > Sent: Friday, March 06, 2009 2:44 AM > To: Rudolf Marek > Cc: Bao, Zheng; Xie, Michael; Perley, Tim; Coreboot > Subject: Re: [coreboot] Problems about booting windows xp > > Hi, > Today I tried to install a pure new windows xp which seabios in > dbm690t it > Hand off as show figure. I also put my dmes.txt here and e820 map also > data.txt from acpidump. It all works fine with linux. As my dbm690t has > 1G Ram, so I Take (1024-128)*1024*1024-64)1024. It looks like you have DMI enabled. Is that from SeaBIOS? I turned it in config.h since it looks emulator specific. Kevin or Rudolf, do you use it when you boot XP? [Jason, Wang] I really have no idea about DMI, and I also checked the SeaBIOS configuration file and gained nothing. Watson, what is the path of the file"config.h"? > By the way, is there anybody who know how to use acpiexec? I can not use > it smoothly. I've been muddling through. I found that the history command has been useful to save some typing and frustration when I have typing errors. The other commands I've used: resources execute namespace help It turns out that you can't load multiple tables into acpiexec, which can be a pain. I patched the source and replaced one table, then I can load the other. [Jason, Wang] how did you do that? Now I really need some tools to debug the acpi. Myles From joe at settoplinux.org Tue Mar 10 13:41:22 2009 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 10 Mar 2009 08:41:22 -0400 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> Message-ID: <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> On Tue, 10 Mar 2009 20:20:53 +0800, "Wang, Qingpei" wrote: > Hi all > It sounds interesting. If there is any proper projects, I would like to > join in. > > Jason Wang > BeiJing Technology Development Center > Advanced Micro Devices (AMD) > > > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Stefan Reinauer > Sent: Tuesday, March 10, 2009 12:21 AM > To: Coreboot > Subject: Re: [coreboot] GSoC 2009 deadlines > > Hi, > > due to a severe lack of spare time I am not going to set any gsoc effort > up this year. If someone wants coreboot to participate, I suggest you > stand up now and do it. The deadline for mentoring organizations is > coming pretty close. I'll gladly share my experience from previous years > with any new mentors/org admins. > > Best regards, > > Stefan > > On 27.02.2009 23:52 Uhr, Carl-Daniel Hailfinger wrote: >> Hi all, >> >> GSoC 2009 is approaching and although the number of total slots has been >> reduced, there is a chance we might get some slots for coreboot and/or >> flashrom. We might want to apply separately for coreboot and flashrom, >> maybe also for buildrom or libpayload because they are essentially >> separate projects. I don't know if SeaBIOS would benefit from GSoC >> because it seems rather complete to me. >> >> Deadline for organizational applications: March 13, 2009 noon. >> No application possible before March 9, 2009 noon. >> > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_org_apply_4694175091022641 >> >> Full timeline: >> > http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_timeline_5354032302481437_ >> I wouldn't mind helping out where I can eithor. The problem is I haven't heard any ideas for projects..... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From stepan at coresystems.de Tue Mar 10 14:52:31 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 10 Mar 2009 14:52:31 +0100 Subject: [coreboot] [PATCH] M2V-MX SE random fixups In-Reply-To: <49B5A518.8090804@assembler.cz> References: <49B5A518.8090804@assembler.cz> Message-ID: <49B6709F.4070909@coresystems.de> On 10.03.2009 0:24 Uhr, Rudolf Marek wrote: > Hello, > > To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves > coreboot to 1MB and tries to cache whole range for XIP. The UMA part > colide a > bit with the HAVE_HIGH_TABLES region. I solved that by relocation of > the region. > > This is last missing bit to make SeaBIOS & Windows happy ;) > > This patch depends on the small patch adding the HAVE_HIGH_TABLES to > K8 NB by Myles. > > Windows 7 still boots ;) once this is in, we have no need for other > patches. > > Signed-off-by: Rudolf Marek Acked-by: Stefan Reinauer -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From r.marek at assembler.cz Tue Mar 10 15:00:33 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 10 Mar 2009 15:00:33 +0100 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> Message-ID: <49B67281.1020606@assembler.cz> >> If you can explain to me why the superIO changes. > For some reason the SuperIO puts the RTC at 0x400, even though it's > usually at 0x70. If I put it at 0x70 the keyboard and mouse don't > work :( I put it at 0x90 and corrected the size so that it wouldn't > conflict with other devices. That makes Linux happy with it. It > still could be a problem for Windows not to have it at 0x70. Well maybe the RTC chip is elsewhere too? >> Also The SMM does nothing to >> do with IRQ9. Get rid of SMM for now. The IRQ 9 needs to be setup for ACPI in >> SB. Thats it (and perhaps it needed also an IRQ override). > Sorry I must have misunderstood this again. I thought this was why I > keep getting : IRQ9 nobody cared messages from Linux. What devices you think you have at IRQ9? Maybe some spurious serial IRQ form superIO? Generally IRQ9 is used as ACPI SCI int. Just pressing the power button generates the IRQ for example. To make it work you need: 1) Set IRQ9 in chipset as ACPI IRQ 2) Set the IRQ 9 override to level/low in MADT 3) Fill the FADT sci int to 9 I think you have 2) 3) I failed to find 1) Please check. Also cat/proc/interrupts should state: ... 7: 0 0 IO-APIC-edge parport0 8: 1 0 IO-APIC-edge rtc0 9: 0 0 IO-APIC-fasteoi acpi 16: 1645904 0 IO-APIC-fasteoi uhci_hcd:usb1, ahci, nvidia 17: 0 0 IO-APIC-fasteoi uhci_hcd:usb2, ide0, ide1 The IRQ9 should be level/low - APIC-fasteoi Please post /proc/interrupts Thanks, Rudolf > > It's the last thing that Linux complains about. I'm not sure what I > should do so that somebody cares. > >> It looks fine, assuming it works for you then lets put it in. A lot of people is >> trying to get ACPI working those days. > It's mostly working. > >> Please note that some changes to second patch needs to be done too. For the >> global acpik8_util > > Yes. I was trying to implement what I thought was the intent of the > original. Since then I've taken out the VGA IO port regions and the > DRAM region. It's a lot more complicated because I have multiple root > buses. As far as I can tell the factory BIOS is also not 100% > compliant with the spec, which is making it harder to see what's wrong > with mine. > > My current state is hopefully better than what it was when I first > submitted these patches, but the BSOD is the same. > > Thanks, > Myles From mylesgw at gmail.com Tue Mar 10 15:09:05 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 07:09:05 -0700 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B67281.1020606@assembler.cz> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> <49B67281.1020606@assembler.cz> Message-ID: <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> On Tue, Mar 10, 2009 at 7:00 AM, Rudolf Marek wrote: >>> If you can explain to me why the superIO changes. >> >> For some reason the SuperIO puts the RTC at 0x400, even though it's >> usually at 0x70. ?If I put it at 0x70 the keyboard and mouse don't >> work :( ?I put it at 0x90 and corrected the size so that it wouldn't >> conflict with other devices. ?That makes Linux happy with it. ?It >> still could be a problem for Windows not to have it at 0x70. > > Well maybe the RTC chip is elsewhere too? > > >>> Also The SMM does nothing to >>> do with IRQ9. Get rid of SMM for now. The IRQ 9 needs to be setup for >>> ACPI in >>> SB. Thats it (and perhaps it needed also an IRQ override). >> >> Sorry I must have misunderstood this again. ?I thought this was why I >> keep getting : IRQ9 nobody cared messages from Linux. > > What devices you think you have at IRQ9? I don't think I have any. > Maybe some spurious serial IRQ form superIO? > > Generally IRQ9 is used as ACPI SCI int. > Just pressing the power button generates the IRQ for example. To make it > work you need: > > 1) Set IRQ9 in chipset as ACPI IRQ I don't know where I would do this. I'm assuming you mean southbridge when you say chipset. > 2) Set the IRQ 9 override to level/low in MADT > 3) Fill the FADT sci int to 9 > > I think you have 2) 3) I failed to find 1) Please check. Also > cat/proc/interrupts should state: > > ... > ?7: ? ? ? ? ?0 ? ? ? ? ?0 ? IO-APIC-edge ? ? ?parport0 > ?8: ? ? ? ? ?1 ? ? ? ? ?0 ? IO-APIC-edge ? ? ?rtc0 > ?9: ? ? ? ? ?0 ? ? ? ? ?0 ? IO-APIC-fasteoi ? acpi > ?16: ? ?1645904 ? ? ? ? ?0 ? IO-APIC-fasteoi ? uhci_hcd:usb1, ahci, nvidia > ?17: ? ? ? ? ?0 ? ? ? ? ?0 ? IO-APIC-fasteoi ? uhci_hcd:usb2, ide0, ide1 > > The IRQ9 should be level/low - APIC-fasteoi > > Please post /proc/interrupts Attached. Thanks, Myles -------------- next part -------------- CPU0 CPU1 CPU2 CPU3 0: 137 0 2 441 IO-APIC-edge timer 1: 0 6 11 9388 IO-APIC-edge i8042 4: 0 0 0 4 IO-APIC-edge 7: 103 0 0 0 IO-APIC-edge parport0 8: 0 1 0 0 IO-APIC-edge rtc0 9: 1 276 15 99709 IO-APIC-fasteoi acpi 12: 8 2253 356 210620 IO-APIC-edge i8042 14: 0 270 472 430834 IO-APIC-edge pata_amd 15: 0 0 0 4 IO-APIC-edge pata_amd 19: 0 0 0 3 IO-APIC-fasteoi ohci1394 20: 0 6 3 1091 IO-APIC-fasteoi ehci_hcd:usb1, NVidia CK804 21: 2 3342 663 7785207 IO-APIC-fasteoi ohci_hcd:usb2, eth0 22: 0 0 0 0 IO-APIC-fasteoi sata_nv 23: 0 0 0 0 IO-APIC-fasteoi sata_nv 50: 0 88 0 1 IO-APIC-fasteoi ahci 51: 0 0 0 0 IO-APIC-fasteoi pata_jmicron 53: 162 7635506 16 416 IO-APIC-fasteoi eth1 NMI: 0 0 0 0 Non-maskable interrupts LOC: 3487248 2729920 1947556 3789444 Local timer interrupts RES: 635666 548595 481475 292570 Rescheduling interrupts CAL: 493 482 469 95 function call interrupts TLB: 3909 4023 2811 39787 TLB shootdowns TRM: 0 0 0 0 Thermal event interrupts THR: 0 0 0 0 Threshold APIC interrupts SPU: 0 0 0 0 Spurious interrupts ERR: 103 From r.marek at assembler.cz Tue Mar 10 15:19:37 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 10 Mar 2009 15:19:37 +0100 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> <49B67281.1020606@assembler.cz> <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> Message-ID: <49B676F9.5020406@assembler.cz> > I don't think I have any. Check if some superIO has not irq9 configured. >> Generally IRQ9 is used as ACPI SCI int. >> Just pressing the power button generates the IRQ for example. To make it >> work you need: >> >> 1) Set IRQ9 in chipset as ACPI IRQ > I don't know where I would do this. I'm assuming you mean southbridge > when you say chipset. Yes. Maybe it is hardcoded in chip (IRQ9). 9: 1 276 15 99709 IO-APIC-fasteoi acpi Huh quite big number. Is it from coreboot or legacy BIOS? Maybe some ACPI GP timer is generating the IRQ9? Rudolf From mylesgw at gmail.com Tue Mar 10 15:27:20 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 07:27:20 -0700 Subject: [coreboot] Problems about booting windows xp In-Reply-To: References: <49759968.8040907@assembler.cz> <49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz> <49B0E7F3.2070505@assembler.cz> Message-ID: <2831fecf0903100727y5b0b1b18o8c7a38f360ad0b67@mail.gmail.com> On Tue, Mar 10, 2009 at 5:25 AM, Wang, Qingpei wrote: > [Jason, Wang] I really have no idea about DMI, and I also checked the > SeaBIOS configuration file and gained nothing. Watson, what is the path > of the file"config.h"? >> By the way, is there anybody who know how to use acpiexec? I can not > use >> it smoothly. > > I've been muddling through. ?I found that the history command has been > useful to save some typing and frustration when I have typing errors. > > The other commands I've used: > > resources > execute > namespace > help > > It turns out that you can't load multiple tables into acpiexec, which > can be > a pain. ?I patched the source and replaced one table, then I can load > the > other. > > [Jason, Wang] how did you do that? Now I really need some tools to debug > the acpi. I've been using Stefan's script to automate table dumping: http://www.coreboot.org/pipermail/coreboot/2009-January/044210.html Then I compile the SSDT table with iasl -tc to make a c source file. You can take the contents of the array and insert it into tools/acpiexec/aeexec.c in the place of the Ssdt1Code[] data. Then when you load your DSDT it can refer to the data in the SSDT. The other way to do it is to disassemble the SSDT and DSDT and combine them into one file. I like putting the SSDT into the executable better. Thanks, Myles From r.marek at assembler.cz Tue Mar 10 15:29:09 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 10 Mar 2009 15:29:09 +0100 Subject: [coreboot] Problems about booting windows xp In-Reply-To: References: <20090118021006.GA14386@morn.localdomain> <49759968.8040907@assembler.cz><49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz><49B0E7F3.2070505@assembler.cz> Message-ID: <49B67935.8010009@assembler.cz> Hi, > [Jason, Wang] I really have no idea about DMI, and I also checked the > SeaBIOS configuration file and gained nothing. Watson, what is the path > of the file"config.h"? it is in src/config.h in SeaBIOS. > [Jason, Wang] how did you do that? Now I really need some tools to debug > the acpi. Just take the ssdt from running system and copy it inside dsdt, then recompile. Rudolf From mylesgw at gmail.com Tue Mar 10 15:35:28 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 07:35:28 -0700 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B676F9.5020406@assembler.cz> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> <49B67281.1020606@assembler.cz> <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> <49B676F9.5020406@assembler.cz> Message-ID: <2831fecf0903100735w90eb109u177ae796d14824ae@mail.gmail.com> On Tue, Mar 10, 2009 at 7:19 AM, Rudolf Marek wrote: >> I don't think I have any. > > Check if some superIO has not irq9 configured. > >>> Generally IRQ9 is used as ACPI SCI int. >>> Just pressing the power button generates the IRQ for example. To make it >>> work you need: >>> >>> 1) Set IRQ9 in chipset as ACPI IRQ > >> I don't know where I would do this. ?I'm assuming you mean southbridge >> when you say chipset. > > Yes. Maybe it is hardcoded in chip (IRQ9). > > ?9: ? ? ? ? ?1 ? ? ? ?276 ? ? ? ? 15 ? ? ?99709 ? IO-APIC-fasteoi ? acpi > > Huh quite big number. Is it from coreboot or legacy BIOS? It's from Coreboot. Here's the same line from the factory BIOS: 9: 0 0 0 0 IO-APIC-fasteoi acpi > Maybe some ACPI GP > timer is generating the IRQ9? I wish I knew more about interrupts. I'm surprised how different the routing is for interrupts between the factory BIOS and Coreboot, but I've been assuming they're routed correctly. I've attached /proc/interrupts from the factory BIOS. Thanks, Myles -------------- next part -------------- CPU0 CPU1 CPU2 CPU3 0: 113 0 0 0 IO-APIC-edge timer 1: 0 0 1 517 IO-APIC-edge i8042 4: 0 0 0 4 IO-APIC-edge 7: 1 0 1 1 IO-APIC-edge parport0 8: 0 0 0 0 IO-APIC-edge rtc0 9: 0 0 0 0 IO-APIC-fasteoi acpi 12: 0 1 4 5452 IO-APIC-edge i8042 14: 0 1 17 10162 IO-APIC-edge pata_amd 15: 0 0 0 11 IO-APIC-edge pata_amd 18: 0 0 0 3 IO-APIC-fasteoi ohci1394, pata_jmicron 19: 0 0 4 17944 IO-APIC-fasteoi ahci, eth1 20: 0 0 0 0 IO-APIC-fasteoi sata_nv 21: 0 0 0 0 IO-APIC-fasteoi sata_nv 22: 0 0 2 1072 IO-APIC-fasteoi ohci_hcd:usb2, NVidia CK804 23: 0 1 12 18819 IO-APIC-fasteoi ehci_hcd:usb1, eth0 NMI: 0 0 0 0 Non-maskable interrupts LOC: 13461 8736 8236 15704 Local timer interrupts RES: 8301 12242 5179 15270 Rescheduling interrupts CAL: 1840 2032 1100 3685 function call interrupts TLB: 306 1075 365 562 TLB shootdowns TRM: 0 0 0 0 Thermal event interrupts THR: 0 0 0 0 Threshold APIC interrupts SPU: 0 0 0 0 Spurious interrupts ERR: 1 From r.marek at assembler.cz Tue Mar 10 15:44:01 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 10 Mar 2009 15:44:01 +0100 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0903100735w90eb109u177ae796d14824ae@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> <49B67281.1020606@assembler.cz> <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> <49B676F9.5020406@assembler.cz> <2831fecf0903100735w90eb109u177ae796d14824ae@mail.gmail.com> Message-ID: <49B67CB1.5000900@assembler.cz> > Here's the same line from the factory BIOS: > > 9: 0 0 0 0 Yes this how it should look like ;) > I wish I knew more about interrupts. I'm surprised how different the > routing is for interrupts between the factory BIOS and Coreboot, but > I've been assuming they're routed correctly. I've attached > /proc/interrupts from the factory BIOS. Hmm perhaps the chipset is setup differently. Question is from where the IRQ9 comes from. Maybe some ACPI timer, but it is hard to tell. Maybe it is HPET? Can you switch off hpet again? Rudolf From rminnich at gmail.com Tue Mar 10 16:02:11 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 10 Mar 2009 08:02:11 -0700 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> Message-ID: <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> The project I'd like to see is AVATT v. 2 -- get it on real hardware. AVATT is a virtual machine in flash. kernel + kvm + coreboot. But, people are good to want to join in, but the hard part is leading it. It's tremendous work. You don't want to start GSOC unless you are sure you can finish it. Stefan, how many hours per week and hours total did you put into GSOC? Did you get any sleep? ron From mylesgw at gmail.com Tue Mar 10 16:09:02 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 08:09:02 -0700 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B67CB1.5000900@assembler.cz> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> <49B67281.1020606@assembler.cz> <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> <49B676F9.5020406@assembler.cz> <2831fecf0903100735w90eb109u177ae796d14824ae@mail.gmail.com> <49B67CB1.5000900@assembler.cz> Message-ID: <2831fecf0903100809x596a6571ge3915d8d2b7dd512@mail.gmail.com> On Tue, Mar 10, 2009 at 7:44 AM, Rudolf Marek wrote: >> Here's the same line from the factory BIOS: >> >> ? ?9: ? ? ? ? ?0 ? ? ? ? ? 0 ? ? ? ? ? ?0 ? ? ? ? ? ? ?0 > > Yes this how it should look like ;) > > >> I wish I knew more about interrupts. ?I'm surprised how different the >> routing is for interrupts between the factory BIOS and Coreboot, but >> I've been assuming they're routed correctly. ?I've attached >> /proc/interrupts from the factory BIOS. > > Hmm perhaps the chipset is setup differently. Question is from where the > IRQ9 comes from. Maybe some ACPI timer, but it is hard to tell. Maybe it is > HPET? > Can you switch off hpet again? I did, but the interrupts are still there. When the HPET is on, I get this in my boot log: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 31 hpet0: 3 32-bit timers, 25000000 Hz At least no mention of IRQ 9 there. Thanks, Myles From mylesgw at gmail.com Tue Mar 10 16:38:40 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 08:38:40 -0700 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0903100809x596a6571ge3915d8d2b7dd512@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> <49B67281.1020606@assembler.cz> <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> <49B676F9.5020406@assembler.cz> <2831fecf0903100735w90eb109u177ae796d14824ae@mail.gmail.com> <49B67CB1.5000900@assembler.cz> <2831fecf0903100809x596a6571ge3915d8d2b7dd512@mail.gmail.com> Message-ID: <2831fecf0903100838k7a39dc1fh414f5c5a96587126@mail.gmail.com> On Tue, Mar 10, 2009 at 8:09 AM, Myles Watson wrote: > On Tue, Mar 10, 2009 at 7:44 AM, Rudolf Marek wrote: >>> Here's the same line from the factory BIOS: >>> >>> ? ?9: ? ? ? ? ?0 ? ? ? ? ? 0 ? ? ? ? ? ?0 ? ? ? ? ? ? ?0 >> >> Yes this how it should look like ;) >> >> >>> I wish I knew more about interrupts. ?I'm surprised how different the >>> routing is for interrupts between the factory BIOS and Coreboot, but >>> I've been assuming they're routed correctly. ?I've attached >>> /proc/interrupts from the factory BIOS. >> >> Hmm perhaps the chipset is setup differently. Question is from where the >> IRQ9 comes from. I think it's interesting that there are no interrupt sources with that many interrupts in the factory BIOS. Maybe that's a hint? Thanks, Myles From rminnich at gmail.com Tue Mar 10 16:57:22 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 10 Mar 2009 08:57:22 -0700 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <49B4794A.5090003@gmx.net> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> <49B4794A.5090003@gmx.net> Message-ID: <13426df10903100857v50cefddqd14352862571d42e@mail.gmail.com> This is in response to the very good comments i got. kontron is booting with this *with VGA*. Weirdly, serial and vga work but not keyboard (!). One issue is that the MTRRs are totally wrong, so that it runs slowly. Three other issues: - stack layout is wrong (see below) - no SMI - no ACPI ron >> ? ? ? printk(BIOS_SPEW, "After Startup.sb[-1] %p\n", (void *) secondary_base[-1]); >> > > No offense, but doesn't gcc scream warnings all over the place here? Do > you really want the memory contents of secondary_base[-1] or do you want > &secondary_base[-1] instead? Hm. Looking at the code again, the -1 seems > to be OK, but negative array indices are somewhere between clever and scary. not at all! It's one of the few useful things you can do in C :-) I'm leaving it in; it's too handy. Negative indices should not be scary. You just have to be careful. gcc should not scream warnings here because this is the kind of thing C was designed for. > > There is something about stack setup which smells just wrong. Code > excerpts follow. > > struct stack { > ? ? ? ?u32 post; > ? ? ? ?u32 index; > ? ? ? ?u32 apicid; > ? ? ? ?struct atomic *active_cpus; > ? ? ? ?struct spinlock *start_cpu_lock; > ? ? ? ?u32 ?callerpc; > ? ? ? ?u32 data[16384/sizeof(u32) - 7]; > }; > [...] > stack_end = (u32)&stackmem->stacks[index].data; > > stack_end is now the address of where downwards grow of the stack must > end, NOT the top of a pristine stack aka initial stack pointer. > > void __attribute__((regparm(0))) secondary_cpu_init( > ? ? ? ?u32 post, > ? ? ? ?u32 index, > ? ? ? ?u32 apicid, > ? ? ? ?struct atomic *active_cpus, > ? ? ? ?struct spinlock *start_cpu_lock) > { > [...] > > I guess the function signature is intended to match struct stack, but if > that is the case, you will overflow the stack. The data member of struct > stack is at the wrong end of the struct. yep, I got it upside down, fix will be in the next rev. I'd like to get it in in this partial state for now. thanks ron From marcj303 at gmail.com Tue Mar 10 17:04:32 2009 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 10 Mar 2009 10:04:32 -0600 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <13426df10903100857v50cefddqd14352862571d42e@mail.gmail.com> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> <49B4794A.5090003@gmx.net> <13426df10903100857v50cefddqd14352862571d42e@mail.gmail.com> Message-ID: <534e5dc20903100904v46fb5a29j40a733148e843366@mail.gmail.com> On Tue, Mar 10, 2009 at 9:57 AM, ron minnich wrote: > This is in response to the very good comments i got. > > kontron is booting with this *with VGA*. Weirdly, serial and vga work > but not keyboard (!). > > One issue is that the MTRRs are totally wrong, so that it runs slowly. Were you going to do MTRRs in phase6? Marc From patrick.georgi at coresystems.de Tue Mar 10 17:08:57 2009 From: patrick.georgi at coresystems.de (Patrick Georgi) Date: Tue, 10 Mar 2009 17:08:57 +0100 Subject: [coreboot] [PATCH]es for v2: build system fixes and changes, and scan-build support Message-ID: <49B69099.5020709@coresystems.de> Hi, scan-build is a part of clang, a C language frontend of llvm. (www.llvm.org, clang.llvm.org). scan-build uses the compiler infrastructure to statically analyze the code, for serious and not-so-serious mistakes. llvm, clang and scan-build are still work in progress, and their results should be used with caution. However, they're quite useful at this time. The attached patches do the following: 20090310-1-paths: The rules changed in this patch originally wanted to write c_start.o into the source tree. That triggered a bug in my other work, and is generally not what we want. 20090310-2-gcc-for-real: Create a variable "GCC", which defaults to the content of CC, but allows the user to provide a gcc to use in this instance, even when normally a different tool is chosen. That helps with scan-build (see next patch), and might help with distcc, ccache etc, too. 20090310-3-scanbuild: Add support for clang's scan-build utility to abuild. scan-build wraps the compiler and runs its own compiler on the same sources to do some static analysis on them. It adds an option "-sb" or "--scan-build" that creates a coreboot-builds/$target-scanbuild directory for every $target, containing the output of scan-build, which is a HTML documentation on its results. Be aware, that scanbuild significantly increases build time: A board that takes 6-7 seconds normally requires 60 seconds with that option enabled on my test system. The patch also moves the stack-protector option down a bit, so it applies to crosscompiled targets, too (which overwrote the compiler settings before) I'm currently doing a full abuild run on a recent tree, with the above changes, and the resulting coreboot-builds directory is public at http://www.coresystems.de/~patrick/coreboot-builds/. Feel free to look for bugs in your favorite board support, and fix them! :-) All of them: Signed-off-by: Patrick Georgi Regards, Patrick Georgi From patrick at georgi-clan.de Tue Mar 10 17:10:24 2009 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 10 Mar 2009 17:10:24 +0100 Subject: [coreboot] [PATCH]es for v2: build system fixes and changes, and scan-build support In-Reply-To: <49B69099.5020709@coresystems.de> References: <49B69099.5020709@coresystems.de> Message-ID: <49B690F0.6000404@georgi-clan.de> And next time, I'll actually add the patches the first time. Patrick -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090310-3-scanbuild URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090310-1-paths URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: 20090310-2-gcc-for-real URL: From mylesgw at gmail.com Tue Mar 10 17:21:42 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 09:21:42 -0700 Subject: [coreboot] [PATCH]es for v2: build system fixes and changes, and scan-build support In-Reply-To: <49B69099.5020709@coresystems.de> References: <49B69099.5020709@coresystems.de> Message-ID: <2831fecf0903100921v4cf9c323k4eb134ecec4ec3c8@mail.gmail.com> On Tue, Mar 10, 2009 at 9:08 AM, Patrick Georgi wrote: > Hi, > > scan-build is a part of clang, a C language frontend of llvm. > (www.llvm.org, clang.llvm.org). scan-build uses the compiler > infrastructure to statically analyze the code, for serious and > not-so-serious mistakes. > llvm, clang and scan-build are still work in progress, and their results > should be used with caution. However, they're quite useful at this time. > > The attached patches do the following: > 20090310-1-paths: > The rules changed in this patch originally wanted to write c_start.o > into the source tree. That triggered a bug in my other work, and is > generally not what we want. > > 20090310-2-gcc-for-real: > Create a variable "GCC", which defaults to the content of CC, but allows > the user to provide a gcc to use in this instance, even when normally a > different tool is chosen. That helps with scan-build (see next patch), > and might help with distcc, ccache etc, too. > > 20090310-3-scanbuild: > Add support for clang's scan-build utility to abuild. scan-build wraps > the compiler and runs its own compiler on the same sources to do some > static analysis on them. It adds an option "-sb" or "--scan-build" that > creates a coreboot-builds/$target-scanbuild directory for every $target, > containing the output of scan-build, which is a HTML documentation on > its results. > Be aware, that scanbuild significantly increases build time: A board > that takes 6-7 seconds normally requires 60 seconds with that option > enabled on my test system. > The patch also moves the stack-protector option down a bit, so it > applies to crosscompiled targets, too (which overwrote the compiler > settings before) > > I'm currently doing a full abuild run on a recent tree, with the above > changes, and the resulting coreboot-builds directory is public at > http://www.coresystems.de/~patrick/coreboot-builds/. Feel free to look > for bugs in your favorite board support, and fix them! :-) It looks like many of the errors are in the util directory (nrv2b, x86emu, etc.) I was interested how many parser errors there are, but I couldn't look at them. I get permission denied with the following link: http://www.coresystems.de/~patrick/coreboot-builds/amd_serengeti_cheetah-scanbuild/failures/clang_parser_rejects_0I4Exi.i Thanks, Myles From patrick.georgi at coresystems.de Tue Mar 10 17:28:30 2009 From: patrick.georgi at coresystems.de (Patrick Georgi) Date: Tue, 10 Mar 2009 17:28:30 +0100 Subject: [coreboot] [PATCH]es for v2: build system fixes and changes, and scan-build support In-Reply-To: <2831fecf0903100921v4cf9c323k4eb134ecec4ec3c8@mail.gmail.com> References: <49B69099.5020709@coresystems.de> <2831fecf0903100921v4cf9c323k4eb134ecec4ec3c8@mail.gmail.com> Message-ID: <49B6952E.9050003@coresystems.de> Am 10.03.2009 17:21, schrieb Myles Watson: > http://www.coresystems.de/~patrick/coreboot-builds/amd_serengeti_cheetah-scanbuild/failures/clang_parser_rejects_0I4Exi.i > Fixed. I'll re-add permissions later again, so if you have problems with other boards, just try again later. That thing is still building Patrick From stepan at coresystems.de Tue Mar 10 17:38:50 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 10 Mar 2009 17:38:50 +0100 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> Message-ID: <49B6979A.6060001@coresystems.de> On 10.03.2009 16:02 Uhr, ron minnich wrote: > The project I'd like to see is AVATT v. 2 -- get it on real hardware. > > AVATT is a virtual machine in flash. kernel + kvm + coreboot. > > But, people are good to want to join in, but the hard part is leading > it. It's tremendous work. You don't want to start GSOC unless you are > sure you can finish it. > > Stefan, how many hours per week and hours total did you put into GSOC? > Did you get any sleep? > It should be 5 hours per week and per student minimum. I think for a good mentoring this might not always be enough, though it's sometimes hard to reach even that. Think I was trying to mentor 7 students in the first year. That said, I filled out a registration form for gsoc 09 after quite some people showed interest in helping out. If we do this, we should make sure the students get a good time and all the help they need to do stuff. Stefan From marcj303 at gmail.com Tue Mar 10 17:57:51 2009 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 10 Mar 2009 10:57:51 -0600 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <49B6979A.6060001@coresystems.de> References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> <49B6979A.6060001@coresystems.de> Message-ID: <534e5dc20903100957s7d3b55aaxc8e891f90eedc6ee@mail.gmail.com> On Tue, Mar 10, 2009 at 10:38 AM, Stefan Reinauer wrote: > On 10.03.2009 16:02 Uhr, ron minnich wrote: >> The project I'd like to see is AVATT v. 2 -- get it on real hardware. >> >> AVATT is a virtual machine in flash. kernel + kvm + coreboot. >> >> But, people are good to want to join in, but the hard part is leading >> it. It's tremendous work. You don't want to start GSOC unless you are >> sure you can finish it. >> >> Stefan, how many hours per week and hours total did you put into GSOC? >> Did you get any sleep? >> > > It should be 5 hours per week and per student minimum. I think for a > good mentoring this might not always be enough, though it's sometimes > hard to reach even that. > Think I was trying to mentor 7 students in the first year. > > That said, I filled out a registration form for gsoc 09 after quite some > people showed interest in helping out. If we do this, we should make > sure the students get a good time and all the help they need to do stuff. I would like to be a mentor for a coreboot GSOC project. Just let me know what project you would like me to help with. Marc From mylesgw at gmail.com Tue Mar 10 18:57:22 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 11:57:22 -0600 Subject: [coreboot] Problems about booting windows xp In-Reply-To: <49B67935.8010009@assembler.cz> References: <49997F9E.1030004@gmx.net> <4999E1E1.8050307@assembler.cz> <49B0E7F3.2070505@assembler.cz> <49B67935.8010009@assembler.cz> Message-ID: <2831fecf0903101057m6b15bd50k595e17ec6aa7b055@mail.gmail.com> On Tue, Mar 10, 2009 at 8:29 AM, Rudolf Marek wrote: > Hi, >> >> [Jason, Wang] I really have no idea about DMI, and I also checked the >> SeaBIOS configuration file and gained nothing. Watson, what is the path >> of the file"config.h"? > > it is in src/config.h in SeaBIOS. Thanks Rudolf. I missed that question. > >> [Jason, Wang] how did you do that? Now I really need some tools to debug >> the acpi. > > Just take the ssdt from running system and copy it inside dsdt, then > recompile. I was having problems with some of the tables not recompiling. That was why I patched acpiexec. If the tables recompile without problems, it probably is easier to combine them. Thanks, Myles From svn at coreboot.org Tue Mar 10 19:06:48 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 10 Mar 2009 19:06:48 +0100 Subject: [coreboot] r3986 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/include/arch mainboard/amd/serengeti_cheetah/dx mainboard/amd/serengeti_cheetah_fam10/dx mainboard/asus/m2v-mx_se mainboard/iwill/dk8_htx/dx northbridge/amd/amdfam10 northbridge/amd/amdk8 Message-ID: Author: myles Date: 2009-03-10 19:06:47 +0100 (Tue, 10 Mar 2009) New Revision: 3986 Added: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_util.asl trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_util.asl Removed: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/amdfam10_util.asl trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/amdk8_util.asl Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/dsdt_lb.dsl trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/dsdt_lb.dsl Log: This patch makes the boards use a single amdk8_util.asl. There are only whitespace differences between this file and the amdk8_util.asl from asus/m2v_mxe. It also enables SLIT filling if you have one, zeroes the unused fields in the srat_lapic structure, and adds some declarations in acpi.h. Signed-off-by: Myles Watson Acked-by: Rudolf Marek Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-03-10 18:06:47 UTC (rev 3986) @@ -212,6 +212,7 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic) { + memset((void *)lapic, 0, sizeof(acpi_srat_lapic_t)); lapic->type=0; lapic->length=sizeof(acpi_srat_lapic_t); lapic->flags=1; @@ -284,7 +285,7 @@ header->length = sizeof(acpi_slit_t); header->revision = 1; -// current = acpi_fill_slit(current); + current = acpi_fill_slit(current); /* recalculate length */ header->length= current - (unsigned long)slit; Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-03-10 18:06:47 UTC (rev 3986) @@ -292,7 +292,8 @@ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_mcfg(unsigned long current); -unsigned long acpi_fill_srat(unsigned long current); +unsigned long acpi_fill_srat(unsigned long current); +unsigned long acpi_fill_slit(unsigned long current); unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id); void acpi_create_ssdt_generator(acpi_header_t *ssdt, char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt); Deleted: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/amdk8_util.asl 2009-03-10 18:06:47 UTC (rev 3986) @@ -1,315 +0,0 @@ -/* - * Copyright 2005 AMD - */ - -//AMD k8 util for BUSB and res range - - Scope (\_SB) - { - - Name (OSTB, Ones) - Method (OSTP, 0, NotSerialized) - { - If (LEqual (^OSTB, Ones)) - { - Store (0x00, ^OSTB) - } - - Return (^OSTB) - } - - Method (SEQL, 2, Serialized) - { - Store (SizeOf (Arg0), Local0) - Store (SizeOf (Arg1), Local1) - If (LNot (LEqual (Local0, Local1))) { Return (Zero) } - - Name (BUF0, Buffer (Local0) {}) - Store (Arg0, BUF0) - Name (BUF1, Buffer (Local0) {}) - Store (Arg1, BUF1) - Store (Zero, Local2) - While (LLess (Local2, Local0)) - { - Store (DerefOf (Index (BUF0, Local2)), Local3) - Store (DerefOf (Index (BUF1, Local2)), Local4) - If (LNot (LEqual (Local3, Local4))) { Return (Zero) } - - Increment (Local2) - } - - Return (One) - } - - - Method (DADD, 2, NotSerialized) - { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) - Return (Local0) - } - - - Method (GHCE, 1, NotSerialized) // check if the HC enabled - { - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } - Else { Return (0x00) } - } - - Method (GHCN, 1, NotSerialized) // get the node num for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) - Return (Local0) - } - - Method (GHCL, 1, NotSerialized) // get the link num on node for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) - Return (Local0) - } - - Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) - Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 - Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) - Return (Local0) - } - - Method (GBUS, 2, NotSerialized) - { - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) - } - } - } - - Increment (Local0) - } - - Return (0x00) - } - - Method (GWBN, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0000, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0000,,,) - }) - CreateWordField (BUF0, 0x08, BMIN) - CreateWordField (BUF0, 0x0A, BMAX) - CreateWordField (BUF0, 0x0E, BLEN) - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) - Store (ShiftRight (Local1, 0x18), BMAX) - Subtract (BMAX, BMIN, BLEN) - Increment (BLEN) - Return (RTAG (BUF0)) - } - } - } - - Increment (Local0) - } - - Return (RTAG (BUF0)) - } - - Method (GMEM, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , AddressRangeMemory, TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, MMIN) - CreateDWordField (BUF0, 0x0E, MMAX) - CreateDWordField (BUF0, 0x16, MLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x10)) - { - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x07))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) - Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) - Or (MMAX, 0xFFFF, MMAX) - Subtract (MMAX, MMIN, MLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (\_SB.PCI0.TOM1, MMIN) - Subtract (MMAX, MMIN, MLEN) - Increment (MLEN) - } - - Store (RTAG (BUF0), Local3) - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (BUF0, Local3) - } - - Return (Local3) - } - - Method (GIOR, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, PMIN) - CreateDWordField (BUF0, 0x0E, PMAX) - CreateDWordField (BUF0, 0x16, PLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x08)) - { - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x07))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - Store (And (Local1, 0x01FFF000), PMIN) - Store (And (Local2, 0x01FFF000), PMAX) - Or (PMAX, 0x0FFF, PMAX) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LGreater (PMAX, PMIN)) - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (0x0D00, PMIN) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - } - - Store (RTAG (BUF0), Local3) - Increment (Local4) - } - - If (And (Local1, 0x10)) - { - Store (0x03B0, PMIN) - Store (0x03DF, PMAX) - Store (0x30, PLEN) - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - } - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - Method (RTAG, 1, NotSerialized) - { - Store (Arg0, Local0) - Store (SizeOf (Local0), Local1) - Subtract (Local1, 0x02, Local1) - Multiply (Local1, 0x08, Local1) - CreateField (Local0, 0x00, Local1, RETB) - Store (RETB, Local2) - Return (Local2) - } - } - Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/dx/dsdt_lb.dsl 2009-03-10 18:06:47 UTC (rev 3986) @@ -206,7 +206,7 @@ Z00A, 8 } - Include ("amdk8_util.asl") + Include ("../../../../../src/northbridge/amd/amdk8/amdk8_util.asl") } Deleted: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/amdfam10_util.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/amdfam10_util.asl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/amdfam10_util.asl 2009-03-10 18:06:47 UTC (rev 3986) @@ -1,329 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -// - -//AMD FAM10 util for BUSB and res range - -Scope (\_SB) -{ - - Name (OSTB, Ones) - Method (OSTP, 0, NotSerialized) - { - If (LEqual (^OSTB, Ones)) - { - Store (0x00, ^OSTB) - } - - Return (^OSTB) - } - - Method (SEQL, 2, Serialized) - { - Store (SizeOf (Arg0), Local0) - Store (SizeOf (Arg1), Local1) - If (LNot (LEqual (Local0, Local1))) { Return (Zero) } - - Name (BUF0, Buffer (Local0) {}) - Store (Arg0, BUF0) - Name (BUF1, Buffer (Local0) {}) - Store (Arg1, BUF1) - Store (Zero, Local2) - While (LLess (Local2, Local0)) - { - Store (DerefOf (Index (BUF0, Local2)), Local3) - Store (DerefOf (Index (BUF1, Local2)), Local4) - If (LNot (LEqual (Local3, Local4))) { Return (Zero) } - - Increment (Local2) - } - - Return (One) - } - - - Method (DADD, 2, NotSerialized) - { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) - Return (Local0) - } - - - Method (GHCE, 1, NotSerialized) // check if the HC enabled - { - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } - Else { Return (0x00) } - } - - Method (GHCN, 1, NotSerialized) // get the node num for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xfc), 0x02), Local0) - Return (Local0) - } - - Method (GHCL, 1, NotSerialized) // get the link num on node for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0x700), 0x08), Local0) - Return (Local0) - } - - Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) - Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 - Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) - Return (Local0) - } - - Method (GBUS, 2, NotSerialized) - { - Store (0x00, Local0) - While (LLess (Local0, 0x20)) // 32 ht links - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) - { - Return (ShiftRight (And (Local1, 0x000FF000), 0x0c)) - } - } - } - - Increment (Local0) - } - - Return (0x00) - } - - Method (GWBN, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0000, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0000,,,) - }) - CreateWordField (BUF0, 0x08, BMIN) - CreateWordField (BUF0, 0x0A, BMAX) - CreateWordField (BUF0, 0x0E, BLEN) - Store (0x00, Local0) - While (LLess (Local0, 0x20)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) - { - Store (ShiftRight (And (Local1, 0x000FF000), 0x0c), BMIN) - Store (ShiftRight (Local1, 0x14), BMAX) - Subtract (BMAX, BMIN, BLEN) - Increment (BLEN) - Return (RTAG (BUF0)) - } - } - } - - Increment (Local0) - } - - Return (RTAG (BUF0)) - } - - Method (GMEM, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , AddressRangeMemory, TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, MMIN) - CreateDWordField (BUF0, 0x0E, MMAX) - CreateDWordField (BUF0, 0x16, MLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem ) *2 ( base, limit ) - { - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x3f))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) - { - Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) - Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) - Or (MMAX, 0xFFFF, MMAX) - Subtract (MMAX, MMIN, MLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (\_SB.PCI0.TOM1, MMIN) - Subtract (MMAX, MMIN, MLEN) - Increment (MLEN) - } - - Store (RTAG (BUF0), Local3) - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (BUF0, Local3) - } - - Return (Local3) - } - - Method (GIOR, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, PMIN) - CreateDWordField (BUF0, 0x0E, PMAX) - CreateDWordField (BUF0, 0x16, PLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x40)) // 0x20 ht links * 2 ( base, limit) - { - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x3f))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) - { - Store (And (Local1, 0x01FFF000), PMIN) - Store (And (Local2, 0x01FFF000), PMAX) - Or (PMAX, 0x0FFF, PMAX) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LGreater (PMAX, PMIN)) - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (0x0D00, PMIN) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - } - - Store (RTAG (BUF0), Local3) - Increment (Local4) - } - - If (And (Local1, 0x10)) - { - Store (0x03B0, PMIN) - Store (0x03DF, PMAX) - Store (0x30, PLEN) - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - } - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - Method (RTAG, 1, NotSerialized) - { - Store (Arg0, Local0) - Store (SizeOf (Local0), Local1) - Subtract (Local1, 0x02, Local1) - Multiply (Local1, 0x08, Local1) - CreateField (Local0, 0x00, Local1, RETB) - Store (RETB, Local2) - Return (Local2) - } -} \ No newline at end of file Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/dsdt_lb.dsl =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/dsdt_lb.dsl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/dx/dsdt_lb.dsl 2009-03-10 18:06:47 UTC (rev 3986) @@ -238,5 +238,5 @@ Z00A, 8 } - Include ("amdfam10_util.asl") -} \ No newline at end of file + Include ("../../../../../src/northbridge/amd/amdfam10/amdfam10_util.asl") +} Deleted: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl 2009-03-10 18:06:47 UTC (rev 3986) @@ -1,307 +0,0 @@ -/* - * Copyright 2005 AMD - */ - -//AMD k8 util for BUSB and res range - - Scope (\_SB) - { - - Name (OSTB, Ones) - Method (OSTP, 0, NotSerialized) - { - If (LEqual (^OSTB, Ones)) - { - Store (0x00, ^OSTB) - } - - Return (^OSTB) - } - - Method (SEQL, 2, Serialized) - { - Store (SizeOf (Arg0), Local0) - Store (SizeOf (Arg1), Local1) - If (LNot (LEqual (Local0, Local1))) { Return (Zero) } - - Name (BUF0, Buffer (Local0) {}) - Store (Arg0, BUF0) - Name (BUF1, Buffer (Local0) {}) - Store (Arg1, BUF1) - Store (Zero, Local2) - While (LLess (Local2, Local0)) - { - Store (DerefOf (Index (BUF0, Local2)), Local3) - Store (DerefOf (Index (BUF1, Local2)), Local4) - If (LNot (LEqual (Local3, Local4))) { Return (Zero) } - - Increment (Local2) - } - - Return (One) - } - - - Method (DADD, 2, NotSerialized) - { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) - Return (Local0) - } - - - Method (GHCE, 1, NotSerialized) // check if the HC enabled - { - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } - Else { Return (0x00) } - } - - Method (GHCN, 1, NotSerialized) // get the node num for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) - Return (Local0) - } - - Method (GHCL, 1, NotSerialized) // get the link num on node for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) - Return (Local0) - } - - Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) - Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 - Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) - Return (Local0) - } - - Method (GBUS, 2, NotSerialized) - { - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) - } - } - } - - Increment (Local0) - } - - Return (0x00) - } - - Method (GWBN, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0000, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0000,,,) - }) - CreateWordField (BUF0, 0x08, BMIN) - CreateWordField (BUF0, 0x0A, BMAX) - CreateWordField (BUF0, 0x0E, BLEN) - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) - Store (ShiftRight (Local1, 0x18), BMAX) - Subtract (BMAX, BMIN, BLEN) - Increment (BLEN) - Return (RTAG (BUF0)) - } - } - } - - Increment (Local0) - } - - Return (RTAG (BUF0)) - } - - Method (GMEM, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , AddressRangeMemory, TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, MMIN) - CreateDWordField (BUF0, 0x0E, MMAX) - CreateDWordField (BUF0, 0x16, MLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x10)) - { - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x07))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) - Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) - Or (MMAX, 0xFFFF, MMAX) - Subtract (MMAX, MMIN, MLEN) - Increment (MLEN) - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (BUF0, Local3) - } - - Return (Local3) - } - - Method (GIOR, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, PMIN) - CreateDWordField (BUF0, 0x0E, PMAX) - CreateDWordField (BUF0, 0x16, PLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x08)) - { - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x07))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - Store (And (Local1, 0x01FFF000), PMIN) - Store (And (Local2, 0x01FFF000), PMAX) - Or (PMAX, 0x0FFF, PMAX) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LGreater (PMAX, PMIN)) - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (0x0D00, PMIN) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - } - Store (RTAG (BUF0), Local3) - Increment (Local4) - } - - If (And (Local1, 0x10)) - { - Store (0x03B0, PMIN) - Store (0x03DF, PMAX) - Store (0x30, PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - } - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - Method (RTAG, 1, NotSerialized) - { - Store (Arg0, Local0) - Store (SizeOf (Local0), Local1) - Subtract (Local1, 0x02, Local1) - Multiply (Local1, 0x08, Local1) - CreateField (Local0, 0x00, Local1, RETB) - Store (RETB, Local2) - Return (Local2) - } - } - Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl 2009-03-10 18:06:47 UTC (rev 3986) @@ -22,7 +22,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { - Include ("amdk8_util.asl") + Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl") /* For now only define 2 power states: * - S0 which is fully on Deleted: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/amdk8_util.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/amdk8_util.asl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/amdk8_util.asl 2009-03-10 18:06:47 UTC (rev 3986) @@ -1,315 +0,0 @@ -/* - * Copyright 2005 AMD - */ - -//AMD k8 util for BUSB and res range - - Scope (\_SB) - { - - Name (OSTB, Ones) - Method (OSTP, 0, NotSerialized) - { - If (LEqual (^OSTB, Ones)) - { - Store (0x00, ^OSTB) - } - - Return (^OSTB) - } - - Method (SEQL, 2, Serialized) - { - Store (SizeOf (Arg0), Local0) - Store (SizeOf (Arg1), Local1) - If (LNot (LEqual (Local0, Local1))) { Return (Zero) } - - Name (BUF0, Buffer (Local0) {}) - Store (Arg0, BUF0) - Name (BUF1, Buffer (Local0) {}) - Store (Arg1, BUF1) - Store (Zero, Local2) - While (LLess (Local2, Local0)) - { - Store (DerefOf (Index (BUF0, Local2)), Local3) - Store (DerefOf (Index (BUF1, Local2)), Local4) - If (LNot (LEqual (Local3, Local4))) { Return (Zero) } - - Increment (Local2) - } - - Return (One) - } - - - Method (DADD, 2, NotSerialized) - { - Store( Arg1, Local0) - Store( Arg0, Local1) - Add( ShiftLeft(Local1,16), Local0, Local0) - Return (Local0) - } - - - Method (GHCE, 1, NotSerialized) // check if the HC enabled - { - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } - Else { Return (0x00) } - } - - Method (GHCN, 1, NotSerialized) // get the node num for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) - Return (Local0) - } - - Method (GHCL, 1, NotSerialized) // get the link num on node for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) - Return (Local0) - } - - Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) - Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 - Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight( Local1, Local2), 0xff), Local0) - Return (Local0) - } - - Method (GBUS, 2, NotSerialized) - { - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) - } - } - } - - Increment (Local0) - } - - Return (0x00) - } - - Method (GWBN, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0000, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0000,,,) - }) - CreateWordField (BUF0, 0x08, BMIN) - CreateWordField (BUF0, 0x0A, BMAX) - CreateWordField (BUF0, 0x0E, BLEN) - Store (0x00, Local0) - While (LLess (Local0, 0x04)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) - { - Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) - Store (ShiftRight (Local1, 0x18), BMAX) - Subtract (BMAX, BMIN, BLEN) - Increment (BLEN) - Return (RTAG (BUF0)) - } - } - } - - Increment (Local0) - } - - Return (RTAG (BUF0)) - } - - Method (GMEM, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , AddressRangeMemory, TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, MMIN) - CreateDWordField (BUF0, 0x0E, MMAX) - CreateDWordField (BUF0, 0x16, MLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x10)) - { - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x07))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) - Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) - Or (MMAX, 0xFFFF, MMAX) - Subtract (MMAX, MMIN, MLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (\_SB.PCI0.TOM1, MMIN) - Subtract (MMAX, MMIN, MLEN) - Increment (MLEN) - } - - Store (RTAG (BUF0), Local3) - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (BUF0, Local3) - } - - Return (Local3) - } - - Method (GIOR, 2, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000000,,, - , TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, PMIN) - CreateDWordField (BUF0, 0x0E, PMAX) - CreateDWordField (BUF0, 0x16, PLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x08)) - { - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x07))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) - { - Store (And (Local1, 0x01FFF000), PMIN) - Store (And (Local2, 0x01FFF000), PMAX) - Or (PMAX, 0x0FFF, PMAX) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LGreater (PMAX, PMIN)) - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (0x0D00, PMIN) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - } - - Store (RTAG (BUF0), Local3) - Increment (Local4) - } - - If (And (Local1, 0x10)) - { - Store (0x03B0, PMIN) - Store (0x03DF, PMAX) - Store (0x30, PLEN) - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - } - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - Method (RTAG, 1, NotSerialized) - { - Store (Arg0, Local0) - Store (SizeOf (Local0), Local1) - Subtract (Local1, 0x02, Local1) - Multiply (Local1, 0x08, Local1) - CreateField (Local0, 0x00, Local1, RETB) - Store (RETB, Local2) - Return (Local2) - } - } - Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/dsdt_lb.dsl =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/dsdt_lb.dsl 2009-03-08 04:37:39 UTC (rev 3985) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/dx/dsdt_lb.dsl 2009-03-10 18:06:47 UTC (rev 3986) @@ -206,7 +206,7 @@ Z00A, 8 } - Include ("amdk8_util.asl") + Include ("../../../../../src/northbridge/amd/amdk8/amdk8_util.asl") } Added: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_util.asl =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_util.asl (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_util.asl 2009-03-10 18:06:47 UTC (rev 3986) @@ -0,0 +1,324 @@ +// +// This file is part of the coreboot project. +// +// Copyright (C) 2007 Advanced Micro Devices, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// + +//AMD FAM10 util for BUSB and res range + +Scope (\_SB) +{ + + Name (OSTB, Ones) + Method (OSTP, 0, NotSerialized) + { + If (LEqual (^OSTB, Ones)) + { + Store (0x00, ^OSTB) + } + + Return (^OSTB) + } + + Method (SEQL, 2, Serialized) + { + Store (SizeOf (Arg0), Local0) + Store (SizeOf (Arg1), Local1) + If (LNot (LEqual (Local0, Local1))) { Return (Zero) } + + Name (BUF0, Buffer (Local0) {}) + Store (Arg0, BUF0) + Name (BUF1, Buffer (Local0) {}) + Store (Arg1, BUF1) + Store (Zero, Local2) + While (LLess (Local2, Local0)) + { + Store (DerefOf (Index (BUF0, Local2)), Local3) + Store (DerefOf (Index (BUF1, Local2)), Local4) + If (LNot (LEqual (Local3, Local4))) { Return (Zero) } + + Increment (Local2) + } + + Return (One) + } + + + Method (DADD, 2, NotSerialized) + { + Store( Arg1, Local0) + Store( Arg0, Local1) + Add( ShiftLeft(Local1,16), Local0, Local0) + Return (Local0) + } + + + Method (GHCE, 1, NotSerialized) // check if the HC enabled + { + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + Else { Return (0x00) } + } + + Method (GHCN, 1, NotSerialized) // get the node num for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xfc), 0x02), Local0) + Return (Local0) + } + + Method (GHCL, 1, NotSerialized) // get the link num on node for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0x700), 0x08), Local0) + Return (Local0) + } + + Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) + Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 + Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 + Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Return (Local0) + } + + Method (GBUS, 2, NotSerialized) + { + Store (0x00, Local0) + While (LLess (Local0, 0x20)) // 32 ht links + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) + { + Return (ShiftRight (And (Local1, 0x000FF000), 0x0c)) + } + } + } + + Increment (Local0) + } + + Return (0x00) + } + + Method (GWBN, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0000, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0000,,,) + }) + CreateWordField (BUF0, 0x08, BMIN) + CreateWordField (BUF0, 0x0A, BMAX) + CreateWordField (BUF0, 0x0E, BLEN) + Store (0x00, Local0) + While (LLess (Local0, 0x20)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) + { + Store (ShiftRight (And (Local1, 0x000FF000), 0x0c), BMIN) + Store (ShiftRight (Local1, 0x14), BMAX) + Subtract (BMAX, BMIN, BLEN) + Increment (BLEN) + Return (RTAG (BUF0)) + } + } + } + + Increment (Local0) + } + + Return (RTAG (BUF0)) + } + + Method (GMEM, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , AddressRangeMemory, TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, MMIN) + CreateDWordField (BUF0, 0x0E, MMAX) + CreateDWordField (BUF0, 0x16, MLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem ) *2 ( base, limit ) + { + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x3f))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) + { + Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) + Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) + Or (MMAX, 0xFFFF, MMAX) + Subtract (MMAX, MMIN, MLEN) + Increment (MLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (BUF0, Local3) + } + + Return (Local3) + } + + Method (GIOR, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, PMIN) + CreateDWordField (BUF0, 0x0E, PMAX) + CreateDWordField (BUF0, 0x16, PLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x40)) // 0x20 ht links * 2 ( base, limit) + { + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x3f))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) + { + Store (And (Local1, 0x01FFF000), PMIN) + Store (And (Local2, 0x01FFF000), PMAX) + Or (PMAX, 0x0FFF, PMAX) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + If (LGreater (PMAX, PMIN)) + { + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (0x0D00, PMIN) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + } + + Store (RTAG (BUF0), Local3) + Increment (Local4) + } + + If (And (Local1, 0x10)) + { + Store (0x03B0, PMIN) + Store (0x03DF, PMAX) + Store (0x30, PLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + } + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (RTAG (BUF0), Local3) + } + + Return (Local3) + } + + Method (RTAG, 1, NotSerialized) + { + Store (Arg0, Local0) + Store (SizeOf (Local0), Local1) + Subtract (Local1, 0x02, Local1) + Multiply (Local1, 0x08, Local1) + CreateField (Local0, 0x00, Local1, RETB) + Store (RETB, Local2) + Return (Local2) + } +} Added: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_util.asl =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_util.asl (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_util.asl 2009-03-10 18:06:47 UTC (rev 3986) @@ -0,0 +1,309 @@ +/* + * Copyright 2005 AMD + */ + +//AMD k8 util for BUSB and res range + +Scope (\_SB) +{ + + Name (OSTB, Ones) + Method (OSTP, 0, NotSerialized) + { + If (LEqual (^OSTB, Ones)) + { + Store (0x00, ^OSTB) + } + + Return (^OSTB) + } + + Method (SEQL, 2, Serialized) + { + Store (SizeOf (Arg0), Local0) + Store (SizeOf (Arg1), Local1) + If (LNot (LEqual (Local0, Local1))) { Return (Zero) } + + Name (BUF0, Buffer (Local0) {}) + Store (Arg0, BUF0) + Name (BUF1, Buffer (Local0) {}) + Store (Arg1, BUF1) + Store (Zero, Local2) + While (LLess (Local2, Local0)) + { + Store (DerefOf (Index (BUF0, Local2)), Local3) + Store (DerefOf (Index (BUF1, Local2)), Local4) + If (LNot (LEqual (Local3, Local4))) { Return (Zero) } + + Increment (Local2) + } + + Return (One) + } + + + Method (DADD, 2, NotSerialized) + { + Store( Arg1, Local0) + Store( Arg0, Local1) + Add( ShiftLeft(Local1,16), Local0, Local0) + Return (Local0) + } + + + Method (GHCE, 1, NotSerialized) // check if the HC enabled + { + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + Else { Return (0x00) } + } + + Method (GHCN, 1, NotSerialized) // get the node num for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) + Return (Local0) + } + + Method (GHCL, 1, NotSerialized) // get the link num on node for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) + Return (Local0) + } + + Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) + Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 + Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 + Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Return (Local0) + } + + Method (GBUS, 2, NotSerialized) + { + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) + } + } + } + + Increment (Local0) + } + + Return (0x00) + } + + Method (GWBN, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0000, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0000,,,) + }) + CreateWordField (BUF0, 0x08, BMIN) + CreateWordField (BUF0, 0x0A, BMAX) + CreateWordField (BUF0, 0x0E, BLEN) + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) + Store (ShiftRight (Local1, 0x18), BMAX) + Subtract (BMAX, BMIN, BLEN) + Increment (BLEN) + Return (RTAG (BUF0)) + } + } + } + + Increment (Local0) + } + + Return (RTAG (BUF0)) + } + + Method (GMEM, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , AddressRangeMemory, TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, MMIN) + CreateDWordField (BUF0, 0x0E, MMAX) + CreateDWordField (BUF0, 0x16, MLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x10)) + { + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) + Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) + Or (MMAX, 0xFFFF, MMAX) + Subtract (MMAX, MMIN, MLEN) + Increment (MLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (BUF0, Local3) + } + + Return (Local3) + } + + Method (GIOR, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, PMIN) + CreateDWordField (BUF0, 0x0E, PMAX) + CreateDWordField (BUF0, 0x16, PLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x08)) + { + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (And (Local1, 0x01FFF000), PMIN) + Store (And (Local2, 0x01FFF000), PMAX) + Or (PMAX, 0x0FFF, PMAX) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + If (LGreater (PMAX, PMIN)) + { + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (0x0D00, PMIN) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + } + + Store (RTAG (BUF0), Local3) + Increment (Local4) + } + + If (And (Local1, 0x10)) + { + Store (0x03B0, PMIN) + Store (0x03DF, PMAX) + Store (0x30, PLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + } + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (RTAG (BUF0), Local3) + } + + Return (Local3) + } + + Method (RTAG, 1, NotSerialized) + { + Store (Arg0, Local0) + Store (SizeOf (Local0), Local1) + Subtract (Local1, 0x02, Local1) + Multiply (Local1, 0x08, Local1) + CreateField (Local0, 0x00, Local1, RETB) + Store (RETB, Local2) + Return (Local2) + } +} From mylesgw at gmail.com Tue Mar 10 19:07:53 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 12:07:53 -0600 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B5A174.6010502@assembler.cz> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49A8914C.9060001@gmx.net> <8C585EA3396447C4973D331C5A116681@chimp> <2831fecf0903040909p48f318e9m37ae0fe1551b409f@mail.gmail.com> <49B5A174.6010502@assembler.cz> Message-ID: <2831fecf0903101107m1095e315n9bc9493c49368ff6@mail.gmail.com> On Mon, Mar 9, 2009 at 5:08 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > ? ? ? ? ? ? ? ? ?/* If this is the SouthBridge node and link, add a DRAM region. */ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual > (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?{ > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Store (\_SB.PCI0.TOM1, MMIN) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Subtract (MMAX, MMIN, MLEN) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Increment (MLEN) > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?} > + > > This part cause Windows 7 to BSOD and restart. Did not look at it yet. It starts > ?otherwise. (I added also the another Increment (MLEN), its late for me now to > test without that). > > If you commit it with a proposed I think we can check in the patch. (dont know > for fam10 ?maybe same change is needed). > > Acked-by: Rudolf Marek Committed Rev 3986. Thanks, Myles From rminnich at gmail.com Tue Mar 10 19:09:16 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 10 Mar 2009 11:09:16 -0700 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <534e5dc20903100904v46fb5a29j40a733148e843366@mail.gmail.com> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> <49B4794A.5090003@gmx.net> <13426df10903100857v50cefddqd14352862571d42e@mail.gmail.com> <534e5dc20903100904v46fb5a29j40a733148e843366@mail.gmail.com> Message-ID: <13426df10903101109j26b9b4a3j2f2f6e12c2ff7ca7@mail.gmail.com> On Tue, Mar 10, 2009 at 9:04 AM, Marc Jones wrote: > On Tue, Mar 10, 2009 at 9:57 AM, ron minnich wrote: >> This is in response to the very good comments i got. >> >> kontron is booting with this *with VGA*. Weirdly, serial and vga work >> but not keyboard (!). >> >> One issue is that the MTRRs are totally wrong, so that it runs slowly. > > Were you going to do MTRRs in phase6? I would like to do them early. I don't see any reason not to do them in initram. That way the memory would run fast. Comments on that idea are welcome. ron From rminnich at gmail.com Tue Mar 10 19:10:39 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 10 Mar 2009 11:10:39 -0700 Subject: [coreboot] [PATCH]es for v2: build system fixes and changes, and scan-build support In-Reply-To: <49B6952E.9050003@coresystems.de> References: <49B69099.5020709@coresystems.de> <2831fecf0903100921v4cf9c323k4eb134ecec4ec3c8@mail.gmail.com> <49B6952E.9050003@coresystems.de> Message-ID: <13426df10903101110y4505f44br4e7a85f2ab7865c7@mail.gmail.com> could you set this up or show me how to set this up for v3? ron From info at coresystems.de Tue Mar 10 19:26:23 2009 From: info at coresystems.de (coreboot information) Date: Tue, 10 Mar 2009 19:26:23 +0100 Subject: [coreboot] r3986 build service Message-ID: Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3986 to the coreboot source repository and caused the following changes: Change Log: This patch makes the boards use a single amdk8_util.asl. There are only whitespace differences between this file and the amdk8_util.asl from asus/m2v_mxe. It also enables SLIT filling if you have one, zeroes the unused fields in the srat_lapic structure, and adds some declarations in acpi.h. Signed-off-by: Myles Watson Acked-by: Rudolf Marek Build Log: Compilation of intel:xe7501devkit has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3986&device=xe7501devkit&vendor=intel Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3986&device=986lcd-m&vendor=kontron Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3986&device=epia-m&vendor=via If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From marcj303 at gmail.com Tue Mar 10 19:38:30 2009 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 10 Mar 2009 12:38:30 -0600 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <13426df10903101109j26b9b4a3j2f2f6e12c2ff7ca7@mail.gmail.com> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> <49B4794A.5090003@gmx.net> <13426df10903100857v50cefddqd14352862571d42e@mail.gmail.com> <534e5dc20903100904v46fb5a29j40a733148e843366@mail.gmail.com> <13426df10903101109j26b9b4a3j2f2f6e12c2ff7ca7@mail.gmail.com> Message-ID: <534e5dc20903101138w3647329ft8c781de1b85a721f@mail.gmail.com> On Tue, Mar 10, 2009 at 12:09 PM, ron minnich wrote: > On Tue, Mar 10, 2009 at 9:04 AM, Marc Jones wrote: >> On Tue, Mar 10, 2009 at 9:57 AM, ron minnich wrote: >>> This is in response to the very good comments i got. >>> >>> kontron is booting with this *with VGA*. Weirdly, serial and vga work >>> but not keyboard (!). >>> >>> One issue is that the MTRRs are totally wrong, so that it runs slowly. >> >> Were you going to do MTRRs in phase6? > > I would like to do them early. I don't see any reason not to do them > in initram. That way the memory would run fast. Comments on that idea > are welcome. Yes, You should set the BSP at initram time. I meant which stage of AP init you would do it in. Marc From svn at coreboot.org Tue Mar 10 19:44:34 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 10 Mar 2009 19:44:34 +0100 Subject: [coreboot] r3987 - in trunk/coreboot-v2/src/mainboard: intel/xe7501devkit kontron/986lcd-m via/epia-m Message-ID: Author: myles Date: 2009-03-10 19:44:34 +0100 (Tue, 10 Mar 2009) New Revision: 3987 Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/acpi_tables.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c trunk/coreboot-v2/src/mainboard/via/epia-m/acpi_tables.c Log: This patch adds empty acpi_fill_slit functions so they build again. Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/acpi_tables.c 2009-03-10 18:06:47 UTC (rev 3986) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/acpi_tables.c 2009-03-10 18:44:34 UTC (rev 3987) @@ -20,6 +20,12 @@ return current; } +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + unsigned long acpi_fill_srat(unsigned long current) { // Not implemented Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-03-10 18:06:47 UTC (rev 3986) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-03-10 18:44:34 UTC (rev 3987) @@ -171,6 +171,12 @@ return current; } +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + unsigned long acpi_fill_srat(unsigned long current) { /* No NUMA, no SRAT */ Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/acpi_tables.c 2009-03-10 18:06:47 UTC (rev 3986) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/acpi_tables.c 2009-03-10 18:44:34 UTC (rev 3987) @@ -19,6 +19,11 @@ return current; } +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} unsigned long acpi_fill_madt(unsigned long current) { From stepan at coresystems.de Tue Mar 10 19:50:34 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 10 Mar 2009 19:50:34 +0100 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> Message-ID: <49B6B67A.2040104@coresystems.de> On 10.03.2009 16:02 Uhr, ron minnich wrote: > The project I'd like to see is AVATT v. 2 -- get it on real hardware. > > AVATT is a virtual machine in flash. kernel + kvm + coreboot. > I have two more ideas: - vga option rom for geode LX (same as last year, didn't get done due too few students assigned to us) - storage option rom for usb boot in seabios. (I started this already, but I am not sure if I can finish it) -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From rminnich at gmail.com Tue Mar 10 19:56:26 2009 From: rminnich at gmail.com (ron minnich) Date: Tue, 10 Mar 2009 11:56:26 -0700 Subject: [coreboot] patch: working SMP startup for kontron/core2 In-Reply-To: <534e5dc20903101138w3647329ft8c781de1b85a721f@mail.gmail.com> References: <13426df10903062205r32b4be1md31c7855695b3598@mail.gmail.com> <49B4794A.5090003@gmx.net> <13426df10903100857v50cefddqd14352862571d42e@mail.gmail.com> <534e5dc20903100904v46fb5a29j40a733148e843366@mail.gmail.com> <13426df10903101109j26b9b4a3j2f2f6e12c2ff7ca7@mail.gmail.com> <534e5dc20903101138w3647329ft8c781de1b85a721f@mail.gmail.com> Message-ID: <13426df10903101156j4fde981g15eef46464fccbd0@mail.gmail.com> On Tue, Mar 10, 2009 at 11:38 AM, Marc Jones wrote: > Yes, You should set the BSP at initram time. I meant which stage of AP > init you would do it in. no idea yet :-) I am leaning toward cpu_phase1 ron From info at coresystems.de Tue Mar 10 20:04:14 2009 From: info at coresystems.de (coreboot information) Date: Tue, 10 Mar 2009 20:04:14 +0100 Subject: [coreboot] r3987 build service Message-ID: Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3987 to the coreboot source repository and caused the following changes: Change Log: This patch adds empty acpi_fill_slit functions so they build again. Signed-off-by: Myles Watson Acked-by: Myles Watson Build Log: Compilation of intel:xe7501devkit has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of via:epia-m has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From joe at settoplinux.org Tue Mar 10 20:16:01 2009 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 10 Mar 2009 15:16:01 -0400 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <49B6B67A.2040104@coresystems.de> References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> <49B6B67A.2040104@coresystems.de> Message-ID: <9b6dbfe3b968be90e3d510b84d7b34ca@imap.1and1.com> On Tue, 10 Mar 2009 19:50:34 +0100, Stefan Reinauer wrote: > On 10.03.2009 16:02 Uhr, ron minnich wrote: >> The project I'd like to see is AVATT v. 2 -- get it on real hardware. >> >> AVATT is a virtual machine in flash. kernel + kvm + coreboot. >> > > I have two more ideas: > > - vga option rom for geode LX (same as last year, didn't get done due > too few students assigned to us) > - storage option rom for usb boot in seabios. (I started this already, > but I am not sure if I can finish it) > I like these :-) What about a filo read/write on-flash file system (1 block would be plenty) to store filo.conf for filo 1.0?? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From mylesgw at gmail.com Tue Mar 10 21:27:01 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 14:27:01 -0600 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B5A31F.5080502@assembler.cz> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> Message-ID: <2831fecf0903101327x16e7d392wb160d5be905c3007@mail.gmail.com> On Mon, Mar 9, 2009 at 5:15 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > Acked-by: Rudolf Marek Here's the updated part of the patch. I think it has changed enough to need a second look. I added a new place for high tables to live, because when you have 4GB of RAM and no hoisting it messed up before. I also disabled an extra ram_resource for the same case. Signed-off-by: Myles Watson Thanks, Myles > If you can explain to me why the superIO changes. Also The SMM does nothing to > do with IRQ9. Get rid of SMM for now. The IRQ 9 needs to be setup for ACPI in > SB. Thats it (and perhaps it needed also an IRQ override). > > It looks fine, assuming it works for you then lets put it in. A lot of people is > trying to get ACPI working those days. > > Please note that some changes to second patch needs to be done too. For the > global acpik8_util > > Rudolf -------------- next part -------------- A non-text attachment was scrubbed... Name: tyan_common_tables.diff Type: text/x-patch Size: 7878 bytes Desc: not available URL: From stepan at coresystems.de Tue Mar 10 21:31:45 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 10 Mar 2009 21:31:45 +0100 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0903101327x16e7d392wb160d5be905c3007@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903101327x16e7d392wb160d5be905c3007@mail.gmail.com> Message-ID: <49B6CE31.3010603@coresystems.de> On 10.03.2009 21:27 Uhr, Myles Watson wrote: > On Mon, Mar 9, 2009 at 5:15 PM, Rudolf Marek wrote: > >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Hi, >> >> Acked-by: Rudolf Marek >> > > Here's the updated part of the patch. I think it has changed enough > to need a second look. I added a new place for high tables to live, > because when you have 4GB of RAM and no hoisting it messed up before. > I also disabled an extra ram_resource for the same case. > > Signed-off-by: Myles Watson > > > Acked-by: Stefan Reinauer > Thanks, > Myles > > >> If you can explain to me why the superIO changes. Also The SMM does nothing to >> do with IRQ9. Get rid of SMM for now. The IRQ 9 needs to be setup for ACPI in >> SB. Thats it (and perhaps it needed also an IRQ override). >> >> It looks fine, assuming it works for you then lets put it in. A lot of people is >> trying to get ACPI working those days. >> >> Please note that some changes to second patch needs to be done too. For the >> global acpik8_util >> >> Rudolf >> >> ------------------------------------------------------------------------ >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mylesgw at gmail.com Tue Mar 10 21:32:41 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 14:32:41 -0600 Subject: [coreboot] IRQ 9 on s2895 and s2892 Message-ID: <2831fecf0903101332k77438458y628a22bd1689cc73@mail.gmail.com> I'm extracting this from a different thread hoping for more help :) Thanks Rudolf for all the help so far. This is the last "funny" snippet from a Linux boot log with ACPI enabled: irq 9: nobody cared (try booting with the "irqpoll" option) Pid: 0, comm: swapper Not tainted 2.6.27-11-generic #1 Call Trace: [] __report_bad_irq+0x2b/0x90 [] note_interrupt+0x137/0x170 [] handle_fasteoi_irq+0xed/0x110 [] do_IRQ+0x86/0x100 [] ret_from_intr+0x0/0x29 [] ? native_safe_halt+0x6/0x10 [] ? atomic_notifier_call_chain+0x1a/0x20 [] ? default_idle+0x55/0x60 [] ? cpu_idle+0x75/0x110 [] ? start_secondary+0x97/0xc2 handlers: [] (acpi_irq+0x0/0x2b) Disabling IRQ #9 Freeing initrd memory: 8460k freed audit: initializing netlink socket (disabled) This IRQ is very active > > 9: 1 276 15 99709 IO-APIC-fasteoi acpi > > Huh quite big number. Is it from coreboot or legacy BIOS? It's from Coreboot. Here's the same line from the factory BIOS: 9: 0 0 0 0 IO-APIC-fasteoi acpi > Maybe some ACPI GP > timer is generating the IRQ9? How do you find an interrupt source that's going crazy like that? When I boot with acpi=off I IRQ9 doesn't even get registered. Thanks, Myles From svn at coreboot.org Tue Mar 10 21:39:28 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 10 Mar 2009 21:39:28 +0100 Subject: [coreboot] r3988 - in trunk/coreboot-v2/src: northbridge/amd/amdk8 southbridge/nvidia/ck804 Message-ID: Author: myles Date: 2009-03-10 21:39:27 +0100 (Tue, 10 Mar 2009) New Revision: 3988 Added: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_fadt.c Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/Config.lb trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c Log: This patch adds common elements for ck804-based boards. changes by file: src/northbridge/amd/amdk8/northbridge.c: Add high tables code ala Stefan's code for the i945. src/southbridge/nvidia/ck804/ck804_lpc.c: Enable High Precision Event Timers. Add pm_base for ACPI. src/southbridge/nvidia/ck804/ck804_fadt.c: Since fadt is only dependent on the Southbridge, add it here. src/southbridge/nvidia/ck804/Config.lb: Compile in ck804_fadt.c Signed-off-by: Myles Watson Acked-by: Stefan Reinauer Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-03-10 18:44:34 UTC (rev 3987) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-03-10 20:39:27 UTC (rev 3988) @@ -896,6 +896,11 @@ } #endif +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM == 1 @@ -1075,6 +1080,15 @@ ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; +#if HAVE_HIGH_TABLES==1 + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_base); + } +#endif } #if HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1094,10 +1108,24 @@ sizek -= (4*1024*1024 - mmio_basek); } } - ram_resource(dev, (idx | i), basek, sizek); + /* If sizek == 0, it was split at mmio_basek without a hole. + * Don't create an empty ram_resource. + */ + if (sizek) + ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; +#if HAVE_HIGH_TABLES==1 + printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", + i, mmio_basek, basek, limitk); + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif } assign_resources(&dev->link[0]); + } static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/Config.lb =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/Config.lb 2009-03-10 18:44:34 UTC (rev 3987) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/Config.lb 2009-03-10 20:39:27 UTC (rev 3988) @@ -1,3 +1,5 @@ +uses HAVE_ACPI_TABLES + config chip.h driver ck804.o driver ck804_usb.o @@ -12,3 +14,7 @@ driver ck804_pcie.o driver ck804_ht.o object ck804_reset.o + +if HAVE_ACPI_TABLES + object ck804_fadt.o +end Added: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_fadt.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_fadt.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_fadt.c 2009-03-10 20:39:27 UTC (rev 3988) @@ -0,0 +1,146 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2005 Stefan Reinauer + */ + +#include +#include +#include + +extern unsigned pm_base; /* pm_base should be set in sb acpi */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk_debug("pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); +#ifdef LONG_FADT + header->length = 244; +#else + header->length = 0x74; +#endif + header->revision = 1; + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "CB-FADT ", 8); + memcpy(header->asl_compiler_id, "IASL", 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + // 3=Workstation,4=Enterprise Server, 7=Performance Server + fadt->preferred_pm_profile = 0; + fadt->sci_int = 9; + // disable system management mode by setting to 0: + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = pm_base; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = pm_base + 0x04; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = pm_base + 0x1c; + fadt->pm_tmr_blk = pm_base + 0x08; + fadt->gpe0_blk = pm_base + 0x20; + fadt->gpe1_blk = 0x0000; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 0xffff; + fadt->p_lvl3_lat = 0xffff; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0; + fadt->flags = 0xa5; + +#ifdef LONG_FADT + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pm_base; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pm_base + 4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pm_base + 0x08; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pm_base + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 64; + fadt->x_gpe1_blk.bit_offset = 16; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = pm_base + 0xb0; + fadt->x_gpe1_blk.addrh = 0x0; +#endif + header->checksum = acpi_checksum((void *)fadt, header->length); +} Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-03-10 18:44:34 UTC (rev 3987) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-03-10 20:39:27 UTC (rev 3988) @@ -165,7 +165,6 @@ pci_write_config8(dev, 0x6d, new); } -#if 0 static void enable_hpet(struct device *dev) { unsigned long hpet_address; @@ -174,8 +173,9 @@ hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; printk_debug("Enabling HPET @0x%x\n", hpet_address); } -#endif +unsigned pm_base=0; + static void lpc_init(device_t dev) { uint8_t byte, byte_old; @@ -183,6 +183,9 @@ lpc_common_init(dev); + pm_base = pci_read_config32(dev, 0x60) & 0xff00; + printk_info("%s: pm_base = %lx \n", __func__, pm_base); + #if CK804_CHIP_REV==1 if (dev->bus->secondary != 1) return; @@ -251,7 +254,7 @@ isa_dma_init(); /* Initialize the High Precision Event Timers (HPET). */ - /* enable_hpet(dev); */ + enable_hpet(dev); rom_dummy_write(dev); } From mylesgw at gmail.com Tue Mar 10 21:40:12 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 14:40:12 -0600 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B6CE31.3010603@coresystems.de> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903101327x16e7d392wb160d5be905c3007@mail.gmail.com> <49B6CE31.3010603@coresystems.de> Message-ID: <2831fecf0903101340m44d31991p5161da7e60fc99fa@mail.gmail.com> On Tue, Mar 10, 2009 at 2:31 PM, Stefan Reinauer wrote: > On 10.03.2009 21:27 Uhr, Myles Watson wrote: > > On Mon, Mar 9, 2009 at 5:15 PM, Rudolf Marek wrote: > > > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > Here's the updated part of the patch. I think it has changed enough > to need a second look. I added a new place for high tables to live, > because when you have 4GB of RAM and no hoisting it messed up before. > I also disabled an extra ram_resource for the same case. > > Signed-off-by: Myles Watson > > > > > Acked-by: Stefan Reinauer Rev 3988. Thanks, Myles From stepan at coresystems.de Tue Mar 10 21:50:26 2009 From: stepan at coresystems.de (Stefan Reinauer) Date: Tue, 10 Mar 2009 21:50:26 +0100 Subject: [coreboot] GSoC 2009 deadlines In-Reply-To: <9b6dbfe3b968be90e3d510b84d7b34ca@imap.1and1.com> References: <49A86EB2.7030405@gmx.net> <49B54206.6080803@coresystems.de> <5e2e217a9ff6b40dd0d4e18abedf3bdb@imap.1and1.com> <13426df10903100802w2beb9e28uedd59b337f8860b9@mail.gmail.com> <49B6B67A.2040104@coresystems.de> <9b6dbfe3b968be90e3d510b84d7b34ca@imap.1and1.com> Message-ID: <49B6D292.9060606@coresystems.de> On 10.03.2009 20:16 Uhr, Joseph Smith wrote: > > On Tue, 10 Mar 2009 19:50:34 +0100, Stefan Reinauer > wrote: > >> On 10.03.2009 16:02 Uhr, ron minnich wrote: >> >>> The project I'd like to see is AVATT v. 2 -- get it on real hardware. >>> >>> AVATT is a virtual machine in flash. kernel + kvm + coreboot. >>> >>> >> I have two more ideas: >> >> - vga option rom for geode LX (same as last year, didn't get done due >> too few students assigned to us) >> - storage option rom for usb boot in seabios. (I started this already, >> but I am not sure if I can finish it) >> >> > I like these :-) > > What about a filo read/write on-flash file system (1 block would be plenty) > to store filo.conf for filo 1.0?? > > Very good plan, too. -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Tue Mar 10 21:56:55 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Tue, 10 Mar 2009 21:56:55 +0100 Subject: [coreboot] r3989 - in trunk/coreboot-v2/src: mainboard/tyan/s2891 mainboard/tyan/s2892 mainboard/tyan/s2895 superio/smsc/lpc47b397 Message-ID: Author: myles Date: 2009-03-10 21:56:54 +0100 (Tue, 10 Mar 2009) New Revision: 3989 Added: trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c trunk/coreboot-v2/src/mainboard/tyan/s2891/dsdt.dsl trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c trunk/coreboot-v2/src/mainboard/tyan/s2892/dsdt.dsl trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c trunk/coreboot-v2/src/mainboard/tyan/s2895/dsdt.dsl Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c Log: This patch adds ACPI support for Tyan s2891, s2892, and s2895. There is still a problem with IRQ 9, but besides that Linux is happy. BSOD in Windows still. changes by file: src/mainboard/tyan/s289X/Options.lb: Add options and defaults for ACPI tables and resources. src/mainboard/tyan/s289X/mainboard.c: Add high_tables resource ala Stefan's code for the Kontron. src/mainboard/tyan/s289X/acpi_tables.c: Fill out the ACPI tables, using existing code where possible. Only the madt is different between the boards, to be combined later. src/mainboard/tyan/s289X/Config.lb: Compile in acpi_tables.c and dsdt.dsl. Turn on the parallel port and the real-time-clock. src/mainboard/tyan/s289x/dsdt.dsl: The board layout (thanks Rudolf) and interrupts from mptable.c src/mainboard/tyan/s289x/mptable.c: Minor formatting changes to make them diff better. src/superio/smsc/lpc47b397/superio.c: Correct the size of the real-time-clock so it can be where it belongs. Signed-off-by: Myles Watson Acked-by: Rudolf Marek Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2009-03-10 20:56:54 UTC (rev 3989) @@ -51,6 +51,18 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if HAVE_ACPI_TABLES + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb +end + if USE_DCACHE_RAM if CONFIG_USE_INIT Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-03-10 20:56:54 UTC (rev 3989) @@ -30,6 +30,12 @@ uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES +uses CONFIG_MULTIBOOT +uses HAVE_SMI_HANDLER uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR @@ -54,6 +60,7 @@ uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA +uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -77,12 +84,8 @@ uses CONFIG_LB_MEM_TOPK ## ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default ROM_SIZE=524288 +default ROM_SIZE=512*1024 -#1M bytes -#default ROM_SIZE=1048576 - ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## @@ -105,6 +108,11 @@ default HAVE_HARD_RESET=1 ## +## Build SMI handler +## +default HAVE_SMI_HANDLER=0 + +## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -117,6 +125,15 @@ default HAVE_MP_TABLE=1 ## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 +default HAVE_LOW_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=0 +default CONFIG_MULTIBOOT=0 + +## ## Build code to export a CMOS option table ## default HAVE_OPTION_TABLE=1 @@ -128,6 +145,11 @@ default LB_CKS_RANGE_END=122 default LB_CKS_LOC=123 +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 + ## ## Build code for SMP support ## Only worry about 2 micro processors Added: trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -0,0 +1,180 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + apic_addr, 0); + } + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk_debug("ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk_debug("ACPI: * DSDT %p\n", dsdt); + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk_debug("ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk_debug("ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk_debug("ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk_debug("ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk_debug("ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk_debug("ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdt, ssdt); + + printk_info("ACPI: done %p.\n", (void *)current); + return current; +} Added: trunk/coreboot-v2/src/mainboard/tyan/s2891/dsdt.dsl =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/dsdt.dsl (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/dsdt.dsl 2009-03-10 20:56:54 UTC (rev 3989) @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2007, 2008 Rudolf Marek + * + * ISA portions taken from QEMU acpi-dsdt.dsl. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl") + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + /* 2:00 PCIe x4 SB IRQ 17 */ + Device (PE4) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 shifted 3*/ + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1a }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ + Package (0x04) { 0x000aFFFF, 0x01, 0x00, 0x1b }, + Package (0x04) { 0x000aFFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x000aFFFF, 0x03, 0x00, 0x19 }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Onboard NIC */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, + }) + } + } + } +} Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -1,6 +1,22 @@ #include +#include +#include #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + + #if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2891 Mainboard") Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -122,8 +122,7 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); // Onboard ck804 smbus - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); -// 10 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 @@ -137,7 +136,7 @@ // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 -//Slot PCIE x16 +//Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2009-03-10 20:56:54 UTC (rev 3989) @@ -51,6 +51,18 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if HAVE_ACPI_TABLES + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb +end + if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -218,9 +230,10 @@ irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 3 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-03-10 20:56:54 UTC (rev 3989) @@ -30,6 +30,12 @@ uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES +uses CONFIG_MULTIBOOT +uses HAVE_SMI_HANDLER uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR @@ -54,6 +60,7 @@ uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA +uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -71,12 +78,8 @@ uses CONFIG_LB_MEM_TOPK ## ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default ROM_SIZE=524288 +default ROM_SIZE=1024*1024 -#1M bytes -#default ROM_SIZE=1048576 - ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## @@ -99,6 +102,11 @@ default HAVE_HARD_RESET=1 ## +## Build SMI handler +## +default HAVE_SMI_HANDLER=0 + +## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -111,6 +119,15 @@ default HAVE_MP_TABLE=1 ## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 +default HAVE_LOW_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=0 +default CONFIG_MULTIBOOT=0 + +## ## Build code to export a CMOS option table ## default HAVE_OPTION_TABLE=1 @@ -122,6 +139,11 @@ default LB_CKS_RANGE_END=122 default LB_CKS_LOC=123 +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 + ## ## Build code for SMP support ## Only worry about 2 micro processors Added: trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -0,0 +1,180 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + apic_addr, 0); + } + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk_debug("ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk_debug("ACPI: * DSDT %p\n", dsdt); + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk_debug("ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk_debug("ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk_debug("ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk_debug("ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk_debug("ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk_debug("ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdt, ssdt); + + printk_info("ACPI: done %p.\n", (void *)current); + return current; +} Added: trunk/coreboot-v2/src/mainboard/tyan/s2892/dsdt.dsl =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/dsdt.dsl (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/dsdt.dsl 2009-03-10 20:56:54 UTC (rev 3989) @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2007, 2008 Rudolf Marek + * + * ISA portions taken from QEMU acpi-dsdt.dsl. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl") + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, /* 1:08 Onboard Intel NIC IRQ 18 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + /* 2:00 PCIe x4 SB IRQ 17 */ + Device (PE4) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1b }, /* PCIE IRQ24-IRQ27 shifted 3*/ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1a }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1b }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Onboard NIC, SO-DIMM, Slot 4 */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f }, + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x1f }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 2 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1e }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1f }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1c }, + }) + } + } + } +} Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -1,6 +1,22 @@ #include +#include +#include #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + + #if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2892 Mainboard") Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -122,8 +122,7 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); // Onboard ck804 smbus - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); -// 10 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10 // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 @@ -137,7 +136,7 @@ // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 -//Slot PCIE x16 +//Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } @@ -150,7 +149,7 @@ //Slot 2 PCI 32 for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (4<<2)|i, apicid_ck804, 0x10+(0+i)%4); //16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16 } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-03-10 20:56:54 UTC (rev 3989) @@ -60,6 +60,18 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if HAVE_ACPI_TABLES + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb +end + if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -254,9 +266,10 @@ irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 on # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 3 end device pnp 2e.4 on # Com1 io 0x60 = 0x3f8 @@ -282,7 +295,8 @@ end end device pnp 2e.a on # RT - io 0x60 = 0x400 + io 0x60 = 0x90 + irq 0x70 = 8 end end end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-03-10 20:56:54 UTC (rev 3989) @@ -33,6 +33,12 @@ uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES +uses CONFIG_MULTIBOOT +uses HAVE_SMI_HANDLER uses MAINBOARD uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR @@ -56,6 +62,7 @@ uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA +uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK uses K8_HT_FREQ_1G_SUPPORT @@ -80,12 +87,8 @@ uses CONFIG_LB_MEM_TOPK ## ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default ROM_SIZE=524288 +default ROM_SIZE=1024*1024 -#1M bytes -#default ROM_SIZE=1048576 - ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## @@ -112,6 +115,11 @@ default HAVE_HARD_RESET=1 ## +## Build SMI handler +## +default HAVE_SMI_HANDLER=0 + +## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -124,6 +132,15 @@ default HAVE_MP_TABLE=1 ## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 +default HAVE_LOW_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=0 +default CONFIG_MULTIBOOT=0 + +## ## Build code to export a CMOS option table ## default HAVE_OPTION_TABLE=1 @@ -135,6 +152,11 @@ default LB_CKS_RANGE_END=122 default LB_CKS_LOC=123 +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 + ## ## Build code for SMP support ## Only worry about 2 micro processors Added: trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -0,0 +1,191 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned long apic_addr; + device_t dev; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, + apic_addr, 0); + } + + /* Write AMD 8131 two IOAPICs. */ + dev = dev_find_slot(0x40, PCI_DEVFN(0x0,1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, + apic_addr, 0x18); + } + + dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, + apic_addr, 0x1C); + } + + /* Write second NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x80, PCI_DEVFN(0x1, 0)); + if (dev) { + apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, + apic_addr, 0x20); + } + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + /* Doesn't work on this board. */ + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + + current = ALIGN(current, 16); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + printk_debug("ACPI: * FACS %p\n", facs); + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + current = ALIGN(current, 16); + dsdt = (acpi_header_t *) current; + printk_debug("ACPI: * DSDT %p\n", dsdt); + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + current = ALIGN(current, 16); + fadt = (acpi_fadt_t *) current; + printk_debug("ACPI: * FACP (FADT) @ %p\n", fadt); + current += sizeof(acpi_fadt_t); + + /* Add FADT now that we have facs and dsdt. */ + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + current = ALIGN(current, 16); + hpet = (acpi_hpet_t *) current; + printk_debug("ACPI: * HPET @ %p\n", hpet); + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + current = ALIGN(current, 16); + madt = (acpi_madt_t *) current; + printk_debug("ACPI: * APIC/MADT @ %p\n", madt); + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk_debug("ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk_debug("ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + current = ALIGN(current, 16); + ssdt = (acpi_header_t *)current; + printk_debug("ACPI: * SSDT @ %p\n", ssdt); + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdt, ssdt); + + printk_info("ACPI: done %p.\n", (void *)current); + return current; +} Added: trunk/coreboot-v2/src/mainboard/tyan/s2895/dsdt.dsl =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/dsdt.dsl (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/dsdt.dsl 2009-03-10 20:56:54 UTC (rev 3989) @@ -0,0 +1,344 @@ +/* + * This file is part of the coreboot project. + * + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2007, 2008 Rudolf Marek + * + * ISA portions taken from QEMU acpi-dsdt.dsl. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) +{ + Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl") + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */ + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x14 }, /* 0x2 AUDIO IRQ 20 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */ + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x15 }, /* 0xa LAN IRQ 21 */ + }) + + Device (PCIL) + { + Name (_ADR, 0x00090000) + Name (_UID, 0x00) + Name (_BBN, 0x01) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, /* 1:05 IEEE-1394 IRQ 19 */ + }) + } + + /* 2:00 PCIe x16 SB IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 }, + }) + } + + Device (ISA) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* RTC */ + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0090, 0x02) + IRQNoFlags () {8} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + + /* CK804 2050 */ + Device (PCI1) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x80) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x01, 0x00), BUF0, Local1) + Concatenate (\_SB.GIOR (0x01, 0x00), Local1, Local2) + Concatenate (\_SB.GWBN (0x01, 0x00), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table for this root bus */ + Name (_PRT, Package () { + /* Since source is 0, index is IRQ. */ + /* in ABCD, A=0, B=1, C=2, D=3 */ + /* SlotFFFF, ABCD, source, index */ + Package (0x04) { 0x000aFFFF, 0x00, 0x00, 0x35 }, /* 0xa LAN IRQ 53 */ + }) + + /* PCIe x16 SB2 IRQ 18 */ + Device (PE16) + { + Name (_ADR, 0x000e0000) + Name (_UID, 0x00) + Name (_BBN, 0x81) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x32 }, /* PCIE IRQ48-IRQ51 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x33 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x30 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x31 }, + }) + } + + } + + /* AMD 8131 PCI-X tunnel */ + Device (PCI2) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x40) + + /* There is no _PRT Here because I don't know what to + * put in it. Since the 8131 has its own APIC, it + * isn't wired to other IRQs. */ + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3) + Return (Local3) + } + + /* Channel A PCIX 133 */ + Device (PCXF) + { + Name (_ADR, 0x00000000) + Name (_UID, 0x00) + Name (_BBN, 0x41) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1a }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1b }, + }) + } + + /* Channel B PCIX 100 */ + Device (PCXS) /* Slot 4, Onboard SCSI, Slot 5 */ + { + Name (_ADR, 0x00010000) + Name (_UID, 0x00) + Name (_BBN, 0x42) + Name (_PRT, Package () { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1d }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1e }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1f }, + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x1e }, /* PCIE IRQ28-IRQ31 shifted 2 */ + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x1f }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1c }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1d }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 1 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1e }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1f }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1c }, + }) + } + } + } +} Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -1,6 +1,22 @@ #include +#include +#include #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + + #if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2895 Mainboard") Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -121,13 +121,13 @@ smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base); } - dword = 0x0000d218; + dword = 0x0000d218; // Why does the factory BIOS have 0? pci_write_config32(dev, 0x7c, dword); dword = 0x00000000; pci_write_config32(dev, 0x80, dword); - dword = 0x00000d00; + dword = 0x00000d00; // Same here. pci_write_config32(dev, 0x84, dword); } @@ -171,7 +171,7 @@ // Onboard ck804 NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 -//Slot 1 PCIE x16 +//Slot PCIE x16 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); } @@ -181,7 +181,7 @@ //Slot 2 PCI 32 for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16 } if(sysconf.pci1234[2] & 0xf) { Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2009-03-10 20:39:27 UTC (rev 3988) +++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2009-03-10 20:56:54 UTC (rev 3989) @@ -202,7 +202,7 @@ { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, }, - { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LPC47B397_RT, PNP_IO0 | PNP_IRQ0, { 0x7fc, 0 }, }, }; static void enable_dev(struct device *dev) From mylesgw at gmail.com Tue Mar 10 21:57:54 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 14:57:54 -0600 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <49B5A31F.5080502@assembler.cz> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> Message-ID: <2831fecf0903101357h66b802bcy19bb869852f816@mail.gmail.com> On Mon, Mar 9, 2009 at 5:15 PM, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > Acked-by: Rudolf Marek Rev 3989. Thanks, Myles From mylesgw at gmail.com Tue Mar 10 22:05:51 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 15:05:51 -0600 Subject: [coreboot] SimNOW and SeaBIOS In-Reply-To: <2831fecf0903091055w2fac2bb4x1e50271d6265e0d0@mail.gmail.com> References: <2831fecf0903091055w2fac2bb4x1e50271d6265e0d0@mail.gmail.com> Message-ID: <2831fecf0903101405y67a5120w80ec5d9bcee21d3d@mail.gmail.com> On Mon, Mar 9, 2009 at 11:55 AM, Myles Watson wrote: > SeaBIOS won't work with SimNOW unless you make the error checking in > ata.c less strict. > > This is the message you get: > ata_transfer : no sectors left (status 00000008) > > I reported it to the SimNOW team since it seems like they're not > following the spec, but it's been a long time and the bug is still > there. ?To get past it: > ? ?dprintf(6, "ata_transfer : no sectors left (status %02x)\n", status); > + ? ? ? if (status != 0x8) > ? ? ? ? ? ? ?return -7; It's been fixed internally, so at the next public release we shouldn't need this patch anymore. Thanks, Myles From mylesgw at gmail.com Tue Mar 10 22:27:03 2009 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 10 Mar 2009 15:27:03 -0600 Subject: [coreboot] amdk8_util (and amdfam10_util) fix and documentation Message-ID: <2831fecf0903101427y476962ads8cdf9523561ba265@mail.gmail.com> This patch is mostly documenting the functionality, but it also fixes a return value which wasn't added correctly when there is no resource. I've also added code in my tree to remove zero-sized resources, but since it hasn't made me magically boot Windows yet... I guess it's not worth risking breaking it for someone else. Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: amdk8_util_fix.diff Type: text/x-patch Size: 6680 bytes Desc: not available URL: From peter at stuge.se Tue Mar 10 23:17:56 2009 From: peter at stuge.se (Peter Stuge) Date: Tue, 10 Mar 2009 23:17:56 +0100 Subject: [coreboot] ACPI patches for Tyan s2895, s2892, s2891 In-Reply-To: <2831fecf0903100735w90eb109u177ae796d14824ae@mail.gmail.com> References: <2831fecf0902271423t1121c33dp264053085b6830ef@mail.gmail.com> <49B5A31F.5080502@assembler.cz> <2831fecf0903092046o26b2af16lf1579eea414a4085@mail.gmail.com> <49B67281.1020606@assembler.cz> <2831fecf0903100709o52b31a1drad7dcee4a29ebca4@mail.gmail.com> <49B676F9.5020406@assembler.cz> <2831fecf0903100735w90eb109u177ae796d14824ae@mail.gmail.com> Message-ID: <20090310221756.30008.qmail@stuge.se> Myles Watson wrote: > > Maybe some ACPI GP timer is generating the IRQ9? > > I wish I knew more about interrupts. Ok. Which chipset is this? Can we have a look at the interrupt router registers - maybe get them into msrtool - to see what is actually configured to IRQ9 with coreboot? //Peter From r.marek at assembler.cz Wed Mar 11 00:06:26 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Wed, 11 Mar 2009 00:06:26 +0100 Subject: [coreboot] IRQ 9 on s2895 and s2892 In-Reply-To: <2831fecf0903101332k77438458y628a22bd1689cc73@mail.gmail.com> References: <2831fecf0903101332k77438458y628a22bd1689cc73@mail.gmail.com> Message-ID: <49B6F272.4040304@assembler.cz> > I'm extracting this from a different thread hoping for more help :) > How do you find an interrupt source that's going crazy like that? > When I boot with acpi=off I IRQ9 doesn't even get registered. This matches whats going on. The shared IRQ handler for IRQ9 looks to all functions which has registered via request_irq. Each such function returns IRQ_HANDLED or IRQ_NONE when it detects its not their iRQ. To get a source look to: 1) superIO config 2) PCI IRQ router inside SB (it is used to route the IRQ to 8259, its just a bit more complex multiplexor which decides if IRQ goes to APIC or 8259 or both. I cannot find anything about nvidia IRQ routers :/ I hate no-docs state! 3) by observation a) boot kernel with initramfs filesystem (or initrd) b) mount /proc/ c) observe if any activity is on that IRQ d) if not load some drivers for PCI devices (network etc...) e) or even better try without ethernet plugged, USB... Or better method is to hack the "disabling IRQ" handler and printk the interrupt counter there to see if it matches some other count. Rudolf From r.marek at assembler.cz Wed Mar 11 00:17:41 2009 From: r.marek at assembler.cz (Rudolf Marek) Date: Wed, 11 Mar 2009 00:17:41 +0100 Subject: [coreboot] IRQ 9 on s2895 and s2892 In-Reply-To: <49B6F272.4040304@assembler.cz> References: <2831fecf0903101332k77438458y628a22bd1689cc73@mail.gmail.com> <49B6F272.4040304@assembler.cz> Message-ID: <49B6F515.4020704@assembler.cz> http://www.coreboot.org/Nvidia_CK804_Porting_Notes Maybe this will help a bit. So check the suggested registers. Rudolf From svn at coreboot.org Wed Mar 11 04:07:08 2009 From: svn at coreboot.org (svn at coreboot.org) Date: Wed, 11 Mar 2009 04:07:08 +0100 Subject: [coreboot] r86 - in trunk/filo: . drivers fs include main main/grub Message-ID: Author: stepan Date: 2009-03-11 04:07:08 +0100 (Wed, 11 Mar 2009) New Revision: 86 Added: trunk/filo/drivers/hdreg.h trunk/filo/drivers/ide_new.c trunk/filo/drivers/ide_new.h Modified: trunk/filo/Config.in trunk/filo/Makefile trunk/filo/drivers/Makefile.inc trunk/filo/drivers/ide.c trunk/filo/drivers/intel.c trunk/filo/fs/blockdev.c trunk/filo/include/fs.h trunk/filo/main/Makefile.inc trunk/filo/main/grub/builtins.c Log: * move openbios IDE driver over to filo. It works a lot more reliable than the old one. (Lacks PCI BAR reading though) * some helper commands * push version to 0.6.0 final Modified: trunk/filo/Config.in =================================================================== --- trunk/filo/Config.in 2008-12-20 11:23:33 UTC (rev 85) +++ trunk/filo/Config.in 2009-03-11 03:07:08 UTC (rev 86) @@ -118,15 +118,23 @@ Use PCMCIA compact flash on Via Epia MII10000 and MII6000E This device is referred to as hde. +config IDE_NEW_DISK + bool "New IDE driver" + default n + depends on !IDE_DISK + help + Jens Axboe's fine IDE driver + config USB_NEW_DISK - bool "new USB Stack" + bool "USB Stack" default y help Driver for USB Storage config USB_DISK - bool "USB Stack (obsolete?)" + bool "Old USB Stack (obsolete?)" default n + depends on !USB_NEW_DISK help Driver for USB Storage Modified: trunk/filo/Makefile =================================================================== --- trunk/filo/Makefile 2008-12-20 11:23:33 UTC (rev 85) +++ trunk/filo/Makefile 2009-03-11 03:07:08 UTC (rev 86) @@ -17,7 +17,7 @@ # export PROGRAM_NAME := FILO -export PROGRAM_VERSION := 0.6.0rc1 +export PROGRAM_VERSION := 0.6.0 export src := $(shell pwd) export srctree := $(src) Modified: trunk/filo/drivers/Makefile.inc =================================================================== --- trunk/filo/drivers/Makefile.inc 2008-12-20 11:23:33 UTC (rev 85) +++ trunk/filo/drivers/Makefile.inc 2009-03-11 03:07:08 UTC (rev 86) @@ -17,6 +17,7 @@ # TARGETS-$(CONFIG_IDE_DISK) += drivers/ide.o +TARGETS-$(CONFIG_IDE_NEW_DISK) += drivers/ide_new.o TARGETS-$(CONFIG_VIA_SOUND) += drivers/via-sound.o TARGETS-y += drivers/intel.o Added: trunk/filo/drivers/hdreg.h =================================================================== --- trunk/filo/drivers/hdreg.h (rev 0) +++ trunk/filo/drivers/hdreg.h 2009-03-11 03:07:08 UTC (rev 86) @@ -0,0 +1,297 @@ +/* + * this header holds data structures as dictated by spec + */ +#ifndef HDREG_H +#define HDREG_H +#include +//#include + +#define CONFIG_LITTLE_ENDIAN + +#define u8 uint8_t +#define u16 uint16_t +#define u32 uint32_t + +struct hd_driveid { + unsigned short config; /* lots of obsolete bit flags */ + unsigned short cyls; /* Obsolete, "physical" cyls */ + unsigned short reserved2; /* reserved (word 2) */ + unsigned short heads; /* Obsolete, "physical" heads */ + unsigned short track_bytes; /* unformatted bytes per track */ + unsigned short sector_bytes; /* unformatted bytes per sector */ + unsigned short sectors; /* Obsolete, "physical" sectors per track */ + unsigned short vendor0; /* vendor unique */ + unsigned short vendor1; /* vendor unique */ + unsigned short vendor2; /* Retired vendor unique */ + unsigned char serial_no[20]; /* 0 = not_specified */ + unsigned short buf_type; /* Retired */ + unsigned short buf_size; /* Retired, 512 byte increments + * 0 = not_specified + */ + unsigned short ecc_bytes; /* for r/w long cmds; 0 = not_specified */ + unsigned char fw_rev[8]; /* 0 = not_specified */ + unsigned char model[40]; /* 0 = not_specified */ + unsigned char max_multsect; /* 0=not_implemented */ + unsigned char vendor3; /* vendor unique */ + unsigned short dword_io; /* 0=not_implemented; 1=implemented */ + unsigned char vendor4; /* vendor unique */ + unsigned char capability; /* (upper byte of word 49) + * 3: IORDYsup + * 2: IORDYsw + * 1: LBA + * 0: DMA + */ + unsigned short reserved50; /* reserved (word 50) */ + unsigned char vendor5; /* Obsolete, vendor unique */ + unsigned char tPIO; /* Obsolete, 0=slow, 1=medium, 2=fast */ + unsigned char vendor6; /* Obsolete, vendor unique */ + unsigned char tDMA; /* Obsolete, 0=slow, 1=medium, 2=fast */ + unsigned short field_valid; /* (word 53) + * 2: ultra_ok word 88 + * 1: eide_ok words 64-70 + * 0: cur_ok words 54-58 + */ + unsigned short cur_cyls; /* Obsolete, logical cylinders */ + unsigned short cur_heads; /* Obsolete, l heads */ + unsigned short cur_sectors; /* Obsolete, l sectors per track */ + unsigned short cur_capacity0; /* Obsolete, l total sectors on drive */ + unsigned short cur_capacity1; /* Obsolete, (2 words, misaligned int) */ + unsigned char multsect; /* current multiple sector count */ + unsigned char multsect_valid; /* when (bit0==1) multsect is ok */ + unsigned int lba_capacity; /* Obsolete, total number of sectors */ + unsigned short dma_1word; /* Obsolete, single-word dma info */ + unsigned short dma_mword; /* multiple-word dma info */ + unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */ + unsigned short eide_dma_min; /* min mword dma cycle time (ns) */ + unsigned short eide_dma_time; /* recommended mword dma cycle time (ns) */ + unsigned short eide_pio; /* min cycle time (ns), no IORDY */ + unsigned short eide_pio_iordy; /* min cycle time (ns), with IORDY */ + unsigned short words69_70[2]; /* reserved words 69-70 + * future command overlap and queuing + */ + /* HDIO_GET_IDENTITY currently returns only words 0 through 70 */ + unsigned short words71_74[4]; /* reserved words 71-74 + * for IDENTIFY PACKET DEVICE command + */ + unsigned short queue_depth; /* (word 75) + * 15:5 reserved + * 4:0 Maximum queue depth -1 + */ + unsigned short words76_79[4]; /* reserved words 76-79 */ + unsigned short major_rev_num; /* (word 80) */ + unsigned short minor_rev_num; /* (word 81) */ + unsigned short command_set_1; /* (word 82) supported + * 15: Obsolete + * 14: NOP command + * 13: READ_BUFFER + * 12: WRITE_BUFFER + * 11: Obsolete + * 10: Host Protected Area + * 9: DEVICE Reset + * 8: SERVICE Interrupt + * 7: Release Interrupt + * 6: look-ahead + * 5: write cache + * 4: PACKET Command + * 3: Power Management Feature Set + * 2: Removable Feature Set + * 1: Security Feature Set + * 0: SMART Feature Set + */ + unsigned short command_set_2; /* (word 83) + * 15: Shall be ZERO + * 14: Shall be ONE + * 13: FLUSH CACHE EXT + * 12: FLUSH CACHE + * 11: Device Configuration Overlay + * 10: 48-bit Address Feature Set + * 9: Automatic Acoustic Management + * 8: SET MAX security + * 7: reserved 1407DT PARTIES + * 6: SetF sub-command Power-Up + * 5: Power-Up in Standby Feature Set + * 4: Removable Media Notification + * 3: APM Feature Set + * 2: CFA Feature Set + * 1: READ/WRITE DMA QUEUED + * 0: Download MicroCode + */ + unsigned short cfsse; /* (word 84) + * cmd set-feature supported extensions + * 15: Shall be ZERO + * 14: Shall be ONE + * 13:6 reserved + * 5: General Purpose Logging + * 4: Streaming Feature Set + * 3: Media Card Pass Through + * 2: Media Serial Number Valid + * 1: SMART selt-test supported + * 0: SMART error logging + */ + unsigned short cfs_enable_1; /* (word 85) + * command set-feature enabled + * 15: Obsolete + * 14: NOP command + * 13: READ_BUFFER + * 12: WRITE_BUFFER + * 11: Obsolete + * 10: Host Protected Area + * 9: DEVICE Reset + * 8: SERVICE Interrupt + * 7: Release Interrupt + * 6: look-ahead + * 5: write cache + * 4: PACKET Command + * 3: Power Management Feature Set + * 2: Removable Feature Set + * 1: Security Feature Set + * 0: SMART Feature Set + */ + unsigned short cfs_enable_2; /* (word 86) + * command set-feature enabled + * 15: Shall be ZERO + * 14: Shall be ONE + * 13: FLUSH CACHE EXT + * 12: FLUSH CACHE + * 11: Device Configuration Overlay + * 10: 48-bit Address Feature Set + * 9: Automatic Acoustic Management + * 8: SET MAX security + * 7: reserved 1407DT PARTIES + * 6: SetF sub-command Power-Up + * 5: Power-Up in Standby Feature Set + * 4: Removable Media Notification + * 3: APM Feature Set + * 2: CFA Feature Set + * 1: READ/WRITE DMA QUEUED + * 0: Download MicroCode + */ + unsigned short csf_default; /* (word 87) + * command set-feature default + * 15: Shall be ZERO + * 14: Shall be ONE + * 13:6 reserved + * 5: General Purpose Logging enabled + * 4: Valid CONFIGURE STREAM executed + * 3: Media Card Pass Through enabled + * 2: Media Serial Number Valid + * 1: SMART selt-test supported + * 0: SMART error logging + */ + unsigned short dma_ultra; /* (word 88) */ + unsigned short trseuc; /* time required for security erase */ + unsigned short trsEuc; /* time required for enhanced erase */ + unsigned short CurAPMvalues; /* current APM values */ + unsigned short mprc; /* master password revision code */ + unsigned short hw_config; /* hardware config (word 93) + * 15: Shall be ZERO + * 14: Shall be ONE + * 13: + * 12: + * 11: + * 10: + * 9: + * 8: + * 7: + * 6: + * 5: + * 4: + * 3: + * 2: + * 1: + * 0: Shall be ONE + */ + unsigned short acoustic; /* (word 94) + * 15:8 Vendor's recommended value + * 7:0 current value + */ + unsigned short msrqs; /* min stream request size */ + unsigned short sxfert; /* stream transfer time */ + unsigned short sal; /* stream access latency */ + unsigned int spg; /* stream performance granularity */ + unsigned long long lba_capacity_2;/* 48-bit total number of sectors */ + unsigned short words104_125[22];/* reserved words 104-125 */ + unsigned short last_lun; /* (word 126) */ + unsigned short word127; /* (word 127) Feature Set + * Removable Media Notification + * 15:2 reserved + * 1:0 00 = not supported + * 01 = supported + * 10 = reserved + * 11 = reserved + */ + unsigned short dlf; /* (word 128) + * device lock function + * 15:9 reserved + * 8 security level 1:max 0:high + * 7:6 reserved + * 5 enhanced erase + * 4 expire + * 3 frozen + * 2 locked + * 1 en/disabled + * 0 capability + */ + unsigned short csfo; /* (word 129) + * current set features options + * 15:4 reserved + * 3: auto reassign + * 2: reverting + * 1: read-look-ahead + * 0: write cache + */ + unsigned short words130_155[26];/* reserved vendor words 130-155 */ + unsigned short word156; /* reserved vendor word 156 */ + unsigned short words157_159[3];/* reserved vendor words 157-159 */ + unsigned short cfa_power; /* (word 160) CFA Power Mode + * 15 word 160 supported + * 14 reserved + * 13 + * 12 + * 11:0 + */ + unsigned short words161_175[15];/* Reserved for CFA */ + unsigned short words176_205[30];/* Current Media Serial Number */ + unsigned short words206_254[49];/* reserved words 206-254 */ + unsigned short integrity_word; /* (word 255) + * 15:8 Checksum + * 7:0 Signature + */ +}; + +struct request_sense { +#if defined(CONFIG_BIG_ENDIAN) + u8 valid : 1; + u8 error_code : 7; +#elif defined(CONFIG_LITTLE_ENDIAN) + u8 error_code : 7; + u8 valid : 1; +#endif + u8 segment_number; +#if defined(CONFIG_BIG_ENDIAN) + u8 reserved1 : 2; + u8 ili : 1; + u8 reserved2 : 1; + u8 sense_key : 4; +#elif defined(CONFIG_LITTLE_ENDIAN) + u8 sense_key : 4; + u8 reserved2 : 1; + u8 ili : 1; + u8 reserved1 : 2; +#endif + u8 information[4]; + u8 add_sense_len; + u8 command_info[4]; + u8 asc; + u8 ascq; + u8 fruc; + u8 sks[3]; + u8 asb[46]; +}; + +struct atapi_capacity { + u32 lba; + u32 block_size; +}; + +#endif Modified: trunk/filo/drivers/ide.c =================================================================== --- trunk/filo/drivers/ide.c 2008-12-20 11:23:33 UTC (rev 85) +++ trunk/filo/drivers/ide.c 2009-03-11 03:07:08 UTC (rev 86) @@ -1132,6 +1132,11 @@ if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) { unsigned int new_bus; new_bus = (pci_read_config32(currdev, REG_PRIMARY_BUS) >> 8) & 0xff; + if (new_bus == 0) { + debug("Misconfigured bridge at %02x:%02x.%02x skipped.\n", + bus, slot, func); + continue; + } if (pci_find_ata_device_on_bus(new_bus, dev, index, sata, pata)) return 1; } Added: trunk/filo/drivers/ide_new.c =================================================================== --- trunk/filo/drivers/ide_new.c (rev 0) +++ trunk/filo/drivers/ide_new.c 2009-03-11 03:07:08 UTC (rev 86) @@ -0,0 +1,1302 @@ +/* + * OpenBIOS polled ide driver + * + * Copyright (C) 2004 Jens Axboe + * Copyright (C) 2005 Stefan Reinauer + * + * Credit goes to Hale Landis for his excellent ata demo software + * OF node handling and some fixes by Stefan Reinauer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 + * + */ + +/* + * TODO: + * - Really probe for interfaces, don't just rely on legacy + */ + +#define GRUB + +#include +#include +#include + +#include +#include +#include "ide_new.h" +#include "hdreg.h" + +#if 0 +#define dprintf printf +#else +#define dprintf(x...) +#endif + +/* + * define to 2 for the standard 2 channels only + */ +#ifndef CONFIG_IDE_NUM_CHANNELS +#define IDE_NUM_CHANNELS 4 +#else +#define IDE_NUM_CHANNELS CONFIG_IDE_NUM_CHANNELS +#endif +#define IDE_MAX_CHANNELS 4 + +static struct ide_channel ob_ide_channels[IDE_MAX_CHANNELS]; + +/* + * FIXME: probe, we just hardwire legacy ports for now + */ +static const int io_ports[IDE_MAX_CHANNELS] = { 0x1f0, 0x170, 0x1e8, 0x168 }; +static const int ctl_ports[IDE_MAX_CHANNELS] = { 0x3f6, 0x376, 0x3ee, 0x36e }; + +/* + * don't be pedantic + */ +#undef ATA_PEDANTIC + +static void dump_drive(struct ide_drive *drive) +{ +#ifdef CONFIG_DEBUG_IDE + printk("IDE DRIVE @%lx:\n", (unsigned long)drive); + printk("unit: %d\n",drive->unit); + printk("present: %d\n",drive->present); + printk("type: %d\n",drive->type); + printk("media: %d\n",drive->media); + printk("model: %s\n",drive->model); + printk("nr: %d\n",drive->nr); + printk("cyl: %d\n",drive->cyl); + printk("head: %d\n",drive->head); + printk("sect: %d\n",drive->sect); + printk("bs: %d\n",drive->bs); +#endif +} + +/* + * old style io port operations + */ +static unsigned char +ob_ide_inb(unsigned long port) +{ + return inb(port); +} + +static void +ob_ide_outb(unsigned char data, unsigned long port) +{ + outb(data, port); +} + +static void +ob_ide_insw(unsigned long port, unsigned char *addr, unsigned int count) +{ + insw(port, addr, count); +} + +static void +ob_ide_outsw(unsigned long port, unsigned char *addr, unsigned int count) +{ + outsw(port, addr, count); +} + +static inline unsigned char +ob_ide_pio_readb(struct ide_drive *drive, unsigned int offset) +{ + struct ide_channel *chan = drive->channel; + + return chan->obide_inb(chan->io_regs[offset]); +} + +static inline void +ob_ide_pio_writeb(struct ide_drive *drive, unsigned int offset, + unsigned char data) +{ + struct ide_channel *chan = drive->channel; + + chan->obide_outb(data, chan->io_regs[offset]); +} + +static inline void +ob_ide_pio_insw(struct ide_drive *drive, unsigned int offset, + unsigned char *addr, unsigned int len) +{ + struct ide_channel *chan = drive->channel; + + if (len & 1) { + printf("%d: command not word aligned\n", drive->nr); + return; + } + + chan->obide_insw(chan->io_regs[offset], addr, len / 2); +} + +static inline void +ob_ide_pio_outsw(struct ide_drive *drive, unsigned int offset, + unsigned char *addr, unsigned int len) +{ + struct ide_channel *chan = drive->channel; + + if (len & 1) { + printf("%d: command not word aligned\n", drive->nr); + return; + } + + chan->obide_outsw(chan->io_regs[offset], addr, len / 2); +} + +static void +ob_ide_400ns_delay(struct ide_drive *drive) +{ + (void) ob_ide_pio_readb(drive, IDEREG_ASTATUS); + (void) ob_ide_pio_readb(drive, IDEREG_ASTATUS); + (void) ob_ide_pio_readb(drive, IDEREG_ASTATUS); + (void) ob_ide_pio_readb(drive, IDEREG_ASTATUS); + + udelay(1); +} + +static void +ob_ide_error(struct ide_drive *drive, unsigned char stat, char *msg) +{ + struct ide_channel *chan = drive->channel; + unsigned char err; + + if (!stat) + stat = ob_ide_pio_readb(drive, IDEREG_STATUS); + + printf("ob_ide_error drive<%d>: %s:\n", drive->nr, msg); + printf(" cmd=%x, stat=%x", chan->ata_cmd.command, stat); + + if ((stat & (BUSY_STAT | ERR_STAT)) == ERR_STAT) { + err = ob_ide_pio_readb(drive, IDEREG_ERROR); + printf(", err=%x", err); + } + printf("\n"); + + /* + * see if sense is valid and dump that + */ + if (chan->ata_cmd.command == WIN_PACKET) { + struct atapi_command *cmd = &chan->atapi_cmd; + unsigned char old_cdb = cmd->cdb[0]; + + if (cmd->cdb[0] == ATAPI_REQ_SENSE) { + old_cdb = cmd->old_cdb; + + printf(" atapi opcode=%02x", old_cdb); + } else { + int i; + + printf(" cdb: "); + for (i = 0; i < sizeof(cmd->cdb); i++) + printf("%02x ", cmd->cdb[i]); + } + if (cmd->sense_valid) + printf(", sense: %02x/%02x/%02x", cmd->sense.sense_key, cmd->sense.asc, cmd->sense.ascq); + else + printf(", no sense"); + printf("\n"); + } +} + +/* + * wait for 'stat' to be set. returns 1 if failed, 0 if succesful + */ +static int +ob_ide_wait_stat(struct ide_drive *drive, unsigned char ok_stat, + unsigned char bad_stat, unsigned char *ret_stat) +{ + unsigned char stat; + int i; + + ob_ide_400ns_delay(drive); + + for (i = 0; i < 5000; i++) { + stat = ob_ide_pio_readb(drive, IDEREG_STATUS); + if (!(stat & BUSY_STAT)) + break; + + udelay(1000); + } + + if (ret_stat) + *ret_stat = stat; + + if (stat & bad_stat) + return 1; + + if ((stat & ok_stat) || !ok_stat) + return 0; + + return 1; +} + +static int +ob_ide_select_drive(struct ide_drive *drive) +{ + struct ide_channel *chan = drive->channel; + unsigned char control = IDEHEAD_DEV0; + + if (ob_ide_wait_stat(drive, 0, BUSY_STAT, NULL)) { + printf("select_drive: timed out\n"); + return 1; + } + + /* + * don't select drive if already active. Note: we always + * wait for BUSY clear + */ + if (drive->unit == chan->selected) + return 0; + + if (drive->unit) + control = IDEHEAD_DEV1; + + ob_ide_pio_writeb(drive, IDEREG_CURRENT, control); + ob_ide_400ns_delay(drive); + + if (ob_ide_wait_stat(drive, 0, BUSY_STAT, NULL)) { + printf("select_drive: timed out\n"); + return 1; + } + + chan->selected = drive->unit; + return 0; +} + +static void +ob_ide_write_tasklet(struct ide_drive *drive, struct ata_command *cmd) +{ + ob_ide_pio_writeb(drive, IDEREG_FEATURE, cmd->task[1]); + ob_ide_pio_writeb(drive, IDEREG_NSECTOR, cmd->task[3]); + ob_ide_pio_writeb(drive, IDEREG_SECTOR, cmd->task[7]); + ob_ide_pio_writeb(drive, IDEREG_LCYL, cmd->task[8]); + ob_ide_pio_writeb(drive, IDEREG_HCYL, cmd->task[9]); + + ob_ide_pio_writeb(drive, IDEREG_FEATURE, cmd->task[0]); + ob_ide_pio_writeb(drive, IDEREG_NSECTOR, cmd->task[2]); + ob_ide_pio_writeb(drive, IDEREG_SECTOR, cmd->task[4]); + ob_ide_pio_writeb(drive, IDEREG_LCYL, cmd->task[5]); + ob_ide_pio_writeb(drive, IDEREG_HCYL, cmd->task[6]); + + if (drive->unit) + cmd->device_head |= IDEHEAD_DEV1; + + ob_ide_pio_writeb(drive, IDEREG_CURRENT, cmd->device_head); + + ob_ide_pio_writeb(drive, IDEREG_COMMAND, cmd->command); + ob_ide_400ns_delay(drive); +} + +static void +ob_ide_write_registers(struct ide_drive *drive, struct ata_command *cmd) +{ + /* + * we are _always_ polled + */ + ob_ide_pio_writeb(drive, IDEREG_CONTROL, cmd->control | IDECON_NIEN); + + ob_ide_pio_writeb(drive, IDEREG_FEATURE, cmd->feature); + ob_ide_pio_writeb(drive, IDEREG_NSECTOR, cmd->nsector); + ob_ide_pio_writeb(drive, IDEREG_SECTOR, cmd->sector); + ob_ide_pio_writeb(drive, IDEREG_LCYL, cmd->lcyl); + ob_ide_pio_writeb(drive, IDEREG_HCYL, cmd->hcyl); + + if (drive->unit) + cmd->device_head |= IDEHEAD_DEV1; + + ob_ide_pio_writeb(drive, IDEREG_CURRENT, cmd->device_head); + + ob_ide_pio_writeb(drive, IDEREG_COMMAND, cmd->command); + ob_ide_400ns_delay(drive); +} + +/* + * execute given command with a pio data-in phase. + */ +static int +ob_ide_pio_data_in(struct ide_drive *drive, struct ata_command *cmd) +{ + unsigned char stat; + unsigned int bytes, timeout; + + if (ob_ide_select_drive(drive)) + return 1; + + /* + * ATA must set ready and seek stat, ATAPI need only clear busy + */ + timeout = 0; + do { + stat = ob_ide_pio_readb(drive, IDEREG_STATUS); + + if (drive->type == ide_type_ata) { + /* + * this is BIOS code, don't be too pedantic + */ +#ifdef ATA_PEDANTIC + if ((stat & (BUSY_STAT | READY_STAT | SEEK_STAT)) == + (READY_STAT | SEEK_STAT)) + break; +#else + if ((stat & (BUSY_STAT | READY_STAT)) == READY_STAT) + break; +#endif + } else { + if (!(stat & BUSY_STAT)) + break; + } + ob_ide_400ns_delay(drive); + } while (timeout++ < 1000); + + if (timeout >= 1000) { + ob_ide_error(drive, stat, "drive timed out"); + cmd->stat = stat; + return 1; + } + + ob_ide_write_registers(drive, cmd); + + /* + * now read the data + */ + bytes = cmd->buflen; + do { + unsigned count = cmd->buflen; + + if (count > drive->bs) + count = drive->bs; + + /* delay 100ms for ATAPI? */ + + /* + * wait for BUSY clear + */ + if (ob_ide_wait_stat(drive, 0, BUSY_STAT | ERR_STAT, &stat)) { + ob_ide_error(drive, stat, "timed out waiting for BUSY clear"); + cmd->stat = stat; + break; + } + + /* + * transfer the data + */ + if ((stat & (BUSY_STAT | DRQ_STAT)) == DRQ_STAT) { + ob_ide_pio_insw(drive, IDEREG_DATA, cmd->buffer, count); + cmd->bytes -= count; + cmd->buffer += count; + bytes -= count; + + ob_ide_400ns_delay(drive); + } + + if (stat & (BUSY_STAT | WRERR_STAT | ERR_STAT)) { + cmd->stat = stat; + break; + } + + if (!(stat & DRQ_STAT)) { + cmd->stat = stat; + break; + } + } while (bytes); + + if (bytes) + printf("bytes=%d, stat=%x\n", bytes, stat); + + return bytes ? 1 : 0; +} + +/* + * execute ata command with pio packet protocol + */ +static int +ob_ide_pio_packet(struct ide_drive *drive, struct atapi_command *cmd) +{ + unsigned char stat, reason, lcyl, hcyl; + struct ata_command *acmd = &drive->channel->ata_cmd; + unsigned char *buffer; + unsigned int bytes; + + if (ob_ide_select_drive(drive)) + return 1; + + if (cmd->buflen && cmd->data_direction == atapi_ddir_none) + printf("non-zero buflen but no data direction\n"); + + memset(acmd, 0, sizeof(*acmd)); + acmd->lcyl = cmd->buflen & 0xff; + acmd->hcyl = (cmd->buflen >> 8) & 0xff; + acmd->command = WIN_PACKET; + ob_ide_write_registers(drive, acmd); + + /* + * BUSY must be set, _or_ DRQ | ERR + */ + stat = ob_ide_pio_readb(drive, IDEREG_ASTATUS); + if ((stat & BUSY_STAT) == 0) { + if (!(stat & (DRQ_STAT | ERR_STAT))) { + ob_ide_error(drive, stat, "bad stat in atapi cmd"); + cmd->stat = stat; + return 1; + } + } + + if (ob_ide_wait_stat(drive, 0, BUSY_STAT | ERR_STAT, &stat)) { + ob_ide_error(drive, stat, "timeout, ATAPI BUSY clear"); + cmd->stat = stat; + return 1; + } + + if ((stat & (BUSY_STAT | DRQ_STAT | ERR_STAT)) != DRQ_STAT) { + /* + * if command isn't request sense, then we have a problem. if + * we are doing a sense, ERR_STAT == CHECK_CONDITION + */ + if (cmd->cdb[0] != ATAPI_REQ_SENSE) { + printf("odd, drive didn't want to transfer %x\n", stat); + return 1; + } + } + + /* + * transfer cdb + */ + ob_ide_pio_outsw(drive, IDEREG_DATA, cmd->cdb,sizeof(cmd->cdb)); + ob_ide_400ns_delay(drive); + + /* + * ok, cdb was sent to drive, now do data transfer (if any) + */ + bytes = cmd->buflen; + buffer = cmd->buffer; + do { + unsigned int bc; + + if (ob_ide_wait_stat(drive, 0, BUSY_STAT | ERR_STAT, &stat)) { + ob_ide_error(drive, stat, "busy not clear after cdb"); + cmd->stat = stat; + break; + } + + /* + * transfer complete! + */ + if ((stat & (BUSY_STAT | DRQ_STAT)) == 0) + break; + + if ((stat & (BUSY_STAT | DRQ_STAT)) != DRQ_STAT) + break; + + reason = ob_ide_pio_readb(drive, IDEREG_NSECTOR); + lcyl = ob_ide_pio_readb(drive, IDEREG_LCYL); + hcyl = ob_ide_pio_readb(drive, IDEREG_HCYL); + + /* + * check if the drive wants to transfer data in the same + * direction as we do... + */ + if ((reason & IREASON_CD) && cmd->data_direction != atapi_ddir_read) { + ob_ide_error(drive, stat, "atapi, bad transfer ddir"); + break; + } + + bc = (hcyl << 8) | lcyl; + if (!bc) + break; + + if (bc > bytes) + bc = bytes; + + if (cmd->data_direction == atapi_ddir_read) + ob_ide_pio_insw(drive, IDEREG_DATA, buffer, bc); + else + ob_ide_pio_outsw(drive, IDEREG_DATA, buffer, bc); + + bytes -= bc; + buffer += bc; + + ob_ide_400ns_delay(drive); + } while (bytes); + + if (cmd->data_direction != atapi_ddir_none) + (void) ob_ide_wait_stat(drive, 0, BUSY_STAT, &stat); + + if (bytes) + printf("cdb failed, bytes=%d, stat=%x\n", bytes, stat); + + return (stat & ERR_STAT) || bytes; +} + +/* + * execute a packet command, with retries if appropriate + */ +static int +ob_ide_atapi_packet(struct ide_drive *drive, struct atapi_command *cmd) +{ + int retries = 5, ret; + + if (drive->type != ide_type_atapi) + return 1; + if (cmd->buflen > 0xffff) + return 1; + + /* + * retry loop + */ + do { + ret = ob_ide_pio_packet(drive, cmd); + if (!ret) + break; + + /* + * request sense failed, bummer + */ + if (cmd->cdb[0] == ATAPI_REQ_SENSE) + break; + + if (ob_ide_atapi_request_sense(drive)) + break; + + /* + * we know sense is valid. retry if the drive isn't ready, + * otherwise don't bother. + */ + if (cmd->sense.sense_key != ATAPI_SENSE_NOT_READY) + break; + /* + * ... except 'medium not present' + */ + if (cmd->sense.asc == 0x3a) + break; + + udelay(1000000); + } while (retries--); + + if (ret) + ob_ide_error(drive, 0, "atapi command"); + + return ret; +} + +static int +ob_ide_atapi_request_sense(struct ide_drive *drive) +{ + struct atapi_command *cmd = &drive->channel->atapi_cmd; + unsigned char old_cdb; + + /* + * save old cdb for debug error + */ + old_cdb = cmd->cdb[0]; + + memset(cmd, 0, sizeof(*cmd)); + cmd->cdb[0] = ATAPI_REQ_SENSE; + cmd->cdb[4] = 18; + cmd->buffer = (unsigned char *) &cmd->sense; + cmd->buflen = 18; + cmd->data_direction = atapi_ddir_read; + cmd->old_cdb = old_cdb; + + if (ob_ide_atapi_packet(drive, cmd)) + return 1; + + cmd->sense_valid = 1; + return 0; +} + +/* + * make sure drive is ready and media loaded + */ +static int +ob_ide_atapi_drive_ready(struct ide_drive *drive) +{ + struct atapi_command *cmd = &drive->channel->atapi_cmd; + struct atapi_capacity cap; + + /* + * Test Unit Ready is like a ping + */ + memset(cmd, 0, sizeof(*cmd)); + cmd->cdb[0] = ATAPI_TUR; + + if (ob_ide_atapi_packet(drive, cmd)) { + printf("%d: TUR failed\n", drive->nr); + return 1; + } + + /* + * don't force load of tray (bit 2 in byte 4 of cdb), it's + * annoying and we don't want to deal with errors from drives + * that cannot do it + */ + memset(cmd, 0, sizeof(*cmd)); + cmd->cdb[0] = ATAPI_START_STOP_UNIT; + cmd->cdb[4] = 0x01; + + if (ob_ide_atapi_packet(drive, cmd)) { + printf("%d: START_STOP unit failed\n", drive->nr); + return 1; + } + + /* + * finally, get capacity and block size + */ + memset(cmd, 0, sizeof(*cmd)); + memset(&cap, 0, sizeof(cap)); + + cmd->cdb[0] = ATAPI_READ_CAPACITY; + cmd->buffer = (unsigned char *) ∩ + cmd->buflen = sizeof(cap); + cmd->data_direction = atapi_ddir_read; + + if (ob_ide_atapi_packet(drive, cmd)) { + drive->sectors = 0x1fffff; + drive->bs = 2048; + return 1; + } + + drive->sectors = __be32_to_cpu(cap.lba) + 1; + drive->bs = __be32_to_cpu(cap.block_size); + return 0; +} + +/* + * read from an atapi device, using READ_10 + */ +static int +ob_ide_read_atapi(struct ide_drive *drive, unsigned long long block, char *buf, + unsigned int sectors) +{ + struct atapi_command *cmd = &drive->channel->atapi_cmd; + + if (ob_ide_atapi_drive_ready(drive)) + return 1; + + memset(cmd, 0, sizeof(*cmd)); + + /* + * READ_10 should work on generally any atapi device + */ + cmd->cdb[0] = ATAPI_READ_10; + cmd->cdb[2] = (block >> 24) & 0xff; + cmd->cdb[3] = (block >> 16) & 0xff; + cmd->cdb[4] = (block >> 8) & 0xff; + cmd->cdb[5] = block & 0xff; + cmd->cdb[7] = (sectors >> 8) & 0xff; + cmd->cdb[8] = sectors & 0xff; + + cmd->buffer = buf; + cmd->buflen = sectors * 2048; + cmd->data_direction = atapi_ddir_read; + + return ob_ide_atapi_packet(drive, cmd); +} + +static int +ob_ide_read_ata_chs(struct ide_drive *drive, unsigned long long block, + char *buf, unsigned int sectors) +{ + struct ata_command *cmd = &drive->channel->ata_cmd; + unsigned int track = (block / drive->sect); + unsigned int sect = (block % drive->sect) + 1; + unsigned int head = (track % drive->head); + unsigned int cyl = (track / drive->head); + struct ata_sector ata_sector; + + /* + * fill in chs command to read from disk at given location + */ + cmd->buffer = buf; + cmd->buflen = sectors * 512; + + ata_sector.all = sectors; + cmd->nsector = ata_sector.low; + cmd->sector = sect; + cmd->lcyl = cyl; + cmd->hcyl = cyl >> 8; + cmd->device_head = head; + + cmd->command = WIN_READ; + + return ob_ide_pio_data_in(drive, cmd); +} + +static int +ob_ide_read_ata_lba28(struct ide_drive *drive, unsigned long long block, + char *buf, unsigned int sectors) +{ + struct ata_command *cmd = &drive->channel->ata_cmd; + + memset(cmd, 0, sizeof(*cmd)); + + /* + * fill in 28-bit lba command to read from disk at given location + */ + cmd->buffer = buf; + cmd->buflen = sectors * 512; + + cmd->nsector = sectors; + cmd->sector = block; + cmd->lcyl = block >>= 8; + cmd->hcyl = block >>= 8; + cmd->device_head = ((block >> 8) & 0x0f); + cmd->device_head |= (1 << 6); + + cmd->command = WIN_READ; + + return ob_ide_pio_data_in(drive, cmd); +} + +static int +ob_ide_read_ata_lba48(struct ide_drive *drive, unsigned long long block, + char *buf, unsigned int sectors) +{ + struct ata_command *cmd = &drive->channel->ata_cmd; + struct ata_sector ata_sector; + + memset(cmd, 0, sizeof(*cmd)); + + cmd->buffer = buf; + cmd->buflen = sectors * 512; + ata_sector.all = sectors; + + /* + * we are using tasklet addressing here + */ + cmd->task[2] = ata_sector.low; + cmd->task[3] = ata_sector.high; + cmd->task[4] = block; + cmd->task[5] = block >> 8; + cmd->task[6] = block >> 16; + cmd->task[7] = block >> 24; + cmd->task[8] = (u64) block >> 32; + cmd->task[9] = (u64) block >> 40; + + cmd->command = WIN_READ_EXT; + + ob_ide_write_tasklet(drive, cmd); + + return ob_ide_pio_data_in(drive, cmd); +} +/* + * read 'sectors' sectors from ata device + */ +static int +ob_ide_read_ata(struct ide_drive *drive, unsigned long long block, char *buf, + unsigned int sectors) +{ + unsigned long long end_block = block + sectors; + const int need_lba48 = (end_block > (1ULL << 28)) || (sectors > 255); + + if (end_block > drive->sectors) + return 1; + if (need_lba48 && drive->addressing != ide_lba48) + return 1; + + /* + * use lba48 if we have to, otherwise use the faster lba28 + */ + if (need_lba48) + return ob_ide_read_ata_lba48(drive, block, buf, sectors); + else if (drive->addressing != ide_chs) + return ob_ide_read_ata_lba28(drive, block, buf, sectors); + + return ob_ide_read_ata_chs(drive, block, buf, sectors); +} + +static int +ob_ide_read_sectors(struct ide_drive *drive, unsigned long long block, + char *buf, unsigned int sectors) +{ + if (!sectors) + return 1; + if (block + sectors > drive->sectors) + return 1; + +#ifdef CONFIG_DEBUG_IDE + printf("ob_ide_read_sectors: block=%Ld sectors=%u\n", (unsigned long) block, sectors); +#endif + + if (drive->type == ide_type_ata) + return ob_ide_read_ata(drive, block, buf, sectors); + else + return ob_ide_read_atapi(drive, block, buf, sectors); +} + +/* + * byte swap the string if necessay, and strip leading/trailing blanks + */ +static void +ob_ide_fixup_string(unsigned char *s, unsigned int len) +{ + unsigned char *p = s, *end = &s[len & ~1]; + + /* + * if little endian arch, byte swap the string + */ +#ifdef CONFIG_LITTLE_ENDIAN + for (p = end ; p != s;) { + unsigned short *pp = (unsigned short *) (p -= 2); + *pp = __be16_to_cpu(*pp); + } +#endif + + while (s != end && *s == ' ') + ++s; + while (s != end && *s) + if (*s++ != ' ' || (s != end && *s && *s != ' ')) + *p++ = *(s-1); + while (p != end) + *p++ = '\0'; +} + +/* + * it's big endian, we need to swap (if on little endian) the items we use + */ +static int +ob_ide_fixup_id(struct hd_driveid *id) +{ + ob_ide_fixup_string(id->model, 40); + id->config = __le16_to_cpu(id->config); + id->lba_capacity = __le32_to_cpu(id->lba_capacity); + id->cyls = __le16_to_cpu(id->cyls); + id->heads = __le16_to_cpu(id->heads); + id->sectors = __le16_to_cpu(id->sectors); + id->command_set_2 = __le16_to_cpu(id->command_set_2); + id->cfs_enable_2 = __le16_to_cpu(id->cfs_enable_2); + + return 0; +} + +static int +ob_ide_identify_drive(struct ide_drive *drive) +{ + struct ata_command *cmd = &drive->channel->ata_cmd; + struct hd_driveid id; + + memset(cmd, 0, sizeof(*cmd)); + cmd->buffer = (unsigned char *) &id; + cmd->buflen = 512; + + if (drive->type == ide_type_ata) + cmd->command = WIN_IDENTIFY; + else if (drive->type == ide_type_atapi) + cmd->command = WIN_IDENTIFY_PACKET; + else { + printf("%s: called with bad device type %d\n", __FUNCTION__, drive->type); + return 1; + } + + if (ob_ide_pio_data_in(drive, cmd)) + return 1; + + ob_ide_fixup_id(&id); + + if (drive->type == ide_type_atapi) { + drive->media = (id.config >> 8) & 0x1f; + drive->sectors = 0x7fffffff; + drive->bs = 2048; + drive->max_sectors = 31; + } else { + drive->media = ide_media_disk; + drive->sectors = id.lba_capacity; + drive->bs = 512; + drive->max_sectors = 255; + +#ifdef CONFIG_IDE_LBA48 + if ((id.command_set_2 & 0x0400) && (id.cfs_enable_2 & 0x0400)) { + drive->addressing = ide_lba48; + drive->max_sectors = 65535; + } else +#endif + if (id.capability & 2) + drive->addressing = ide_lba28; + else { + drive->addressing = ide_chs; + } + + /* only set these in chs mode? */ + drive->cyl = id.cyls; + drive->head = id.heads; + drive->sect = id.sectors; + } + + strcpy(drive->model, id.model); + return 0; +} + +/* + * identify type of devices on channel. must have already been probed. + */ +static void +ob_ide_identify_drives(struct ide_channel *chan) +{ + struct ide_drive *drive; + int i; + + for (i = 0; i < 2; i++) { + drive = &chan->drives[i]; + + if (!drive->present) + continue; + + ob_ide_identify_drive(drive); + } +} + +/* + * software reset (ATA-4, section 8.3) + */ +static void +ob_ide_software_reset(struct ide_drive *drive) +{ + struct ide_channel *chan = drive->channel; + + ob_ide_pio_writeb(drive, IDEREG_CONTROL, IDECON_NIEN | IDECON_SRST); + ob_ide_400ns_delay(drive); + ob_ide_pio_writeb(drive, IDEREG_CONTROL, IDECON_NIEN); + ob_ide_400ns_delay(drive); + + /* + * if master is present, wait for BUSY clear + */ + if (chan->drives[0].present) + ob_ide_wait_stat(drive, 0, BUSY_STAT, NULL); + + /* + * if slave is present, wait until it allows register access + */ + if (chan->drives[1].present) { + unsigned char sectorn, sectorc; + int timeout = 1000; + + do { + /* + * select it + */ + ob_ide_pio_writeb(drive, IDEREG_CURRENT, IDEHEAD_DEV1); + ob_ide_400ns_delay(drive); + + sectorn = ob_ide_pio_readb(drive, IDEREG_SECTOR); + sectorc = ob_ide_pio_readb(drive, IDEREG_NSECTOR); + + if (sectorc == 0x01 && sectorn == 0x01) + break; + + } while (--timeout); + } + + /* + * reset done, reselect original device + */ + drive->channel->selected = -1; + ob_ide_select_drive(drive); +} + +/* + * this serves as both a device check, and also to verify that the drives + * we initially "found" are really there + */ +static void +ob_ide_device_type_check(struct ide_drive *drive) +{ + unsigned char sc, sn, cl, ch, st; + + if (ob_ide_select_drive(drive)) + return; + + sc = ob_ide_pio_readb(drive, IDEREG_NSECTOR); + sn = ob_ide_pio_readb(drive, IDEREG_SECTOR); + + if (sc == 0x01 && sn == 0x01) { + /* + * read device signature + */ + cl = ob_ide_pio_readb(drive, IDEREG_LCYL); + ch = ob_ide_pio_readb(drive, IDEREG_HCYL); + st = ob_ide_pio_readb(drive, IDEREG_STATUS); + if (cl == 0x14 && ch == 0xeb) + drive->type = ide_type_atapi; + else if (cl == 0x00 && ch == 0x00 && st != 0x00) + drive->type = ide_type_ata; + else + drive->present = 0; + } else + drive->present = 0; +} + +/* + * pure magic + */ +static void +ob_ide_device_check(struct ide_drive *drive) +{ + unsigned char sc, sn; + + /* + * non-existing io port should return 0xff, don't probe this + * channel at all then + */ + if (ob_ide_pio_readb(drive, IDEREG_STATUS) == 0xff) { + drive->channel->present = 0; + return; + } + + if (ob_ide_select_drive(drive)) + return; + + ob_ide_pio_writeb(drive, IDEREG_NSECTOR, 0x55); + ob_ide_pio_writeb(drive, IDEREG_SECTOR, 0xaa); + ob_ide_pio_writeb(drive, IDEREG_NSECTOR, 0xaa); + ob_ide_pio_writeb(drive, IDEREG_SECTOR, 0x55); + ob_ide_pio_writeb(drive, IDEREG_NSECTOR, 0x55); + ob_ide_pio_writeb(drive, IDEREG_SECTOR, 0xaa); + + sc = ob_ide_pio_readb(drive, IDEREG_NSECTOR); + sn = ob_ide_pio_readb(drive, IDEREG_SECTOR); + + /* + * we _think_ the device is there, we will make sure later + */ + if (sc == 0x55 && sn == 0xaa) { + drive->present = 1; + drive->type = ide_type_unknown; + } +} + +/* + * probe the legacy ide ports and find attached devices. + */ +static void +ob_ide_probe(struct ide_channel *chan) +{ + struct ide_drive *drive; + int i; + + for (i = 0; i < 2; i++) { + drive = &chan->drives[i]; + + ob_ide_device_check(drive); + + /* + * no point in continuing + */ + if (!chan->present) + break; + + if (!drive->present) + continue; + + /* + * select and reset device + */ + if (ob_ide_select_drive(drive)) + continue; + + ob_ide_software_reset(drive); + + ob_ide_device_type_check(drive); + } +} + +/* + * The following functions are interfacing with OpenBIOS. They + * are device node methods. Thus they have to do proper stack handling. + * + */ + +/* + * 255 sectors for ata lba28, 65535 for lba48, and 31 sectors for atapi + */ +static int +ob_ide_max_transfer(int *idx) +{ + struct ide_drive *drive=&ob_ide_channels[idx[1]].drives[idx[0]]; + + return (drive->max_sectors * drive->bs); +} + +int +ob_ide_read_blocks(struct ide_drive *drive, int n, u32 blk, char* dest) +{ + int cnt = n; + while (n) { + int len = n; + if (len > drive->max_sectors) + len = drive->max_sectors; + + dprintf("reading %d sectors from blk %d\n",len, blk); + if (ob_ide_read_sectors(drive, blk, dest, len)) { + return n-1; + } + dprintf("done\n"); + + dest += len * drive->bs; + n -= len; + blk += len; + } + + return (cnt); +} + +static int +ob_ide_block_size(int *idx) +{ + struct ide_drive *drive=&ob_ide_channels[idx[1]].drives[idx[0]]; + return(drive->bs); +} + +//int ob_ide_init(int (*func)(struct ide_drive*)) +int ob_ide_init(void) +{ + int i, j; + + for (i = 0; i < IDE_NUM_CHANNELS; i++) { + struct ide_channel *chan = &ob_ide_channels[i]; + + chan->mmio = 0; + + for (j = 0; j < 8; j++) + chan->io_regs[j] = io_ports[i] + j; + + chan->io_regs[8] = ctl_ports[i]; + chan->io_regs[9] = ctl_ports[i] + 1; + + chan->obide_inb = ob_ide_inb; + chan->obide_insw = ob_ide_insw; + chan->obide_outb = ob_ide_outb; + chan->ob