[coreboot] the seabios reboot in the post process

Kevin O'Connor kevin at koconnor.net
Thu Mar 5 14:37:29 CET 2009

On Thu, Mar 05, 2009 at 10:12:58AM +0000, Andrew Goodbody wrote:
> Kevin O'Connor wrote:
>> On Wed, Mar 04, 2009 at 10:15:21AM +0000, wei yang wrote:
>>> since IO port 0x70 also reponsible for the NMI enble/disable, is it
>>> caused the error?
>> I haven't seen this before.  It would be odd for port 0x70 to control
>> NMI, because it is usually used for rtc access.
> It's been this way since the IBM PC AT. If you write to 0x70 with bit 7  
> reset then you risk releasing any pending NMI. If the interrupt vectors  
> are not initialised then you always need to set bit 7 when writing to 
> 0x70.

Does the patch below stop the crash?


--- a/src/cmos.h
+++ b/src/cmos.h
@@ -56,14 +56,14 @@
 static inline u8
 inb_cmos(u8 reg)
-    outb(reg, PORT_CMOS_INDEX);
+    outb(reg | 0x80, PORT_CMOS_INDEX);
     return inb(PORT_CMOS_DATA);
 static inline void
 outb_cmos(u8 val, u8 reg)
-    outb(reg, PORT_CMOS_INDEX);
+    outb(reg | 0x80, PORT_CMOS_INDEX);
     outb(val, PORT_CMOS_DATA);

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